From 02d93bedab0c93e5d8f13d954142f9c419370b18 Mon Sep 17 00:00:00 2001 From: Aleksandr Rybalko Date: Sat, 29 Jun 2013 23:39:05 +0000 Subject: Import basic support for Samsung Exynos 5 support. Submitted by: Ruslan Bukin Reviewed by: gonzo --- sys/arm/samsung/exynos/arch_timer.c | 136 +++++++++++ sys/arm/samsung/exynos/bus_space.c | 153 +++++++++++++ sys/arm/samsung/exynos/common.c | 73 ++++++ sys/arm/samsung/exynos/ehci_exynos5.c | 367 ++++++++++++++++++++++++++++++ sys/arm/samsung/exynos/exynos5_machdep.c | 109 +++++++++ sys/arm/samsung/exynos/exynos5_mp.c | 92 ++++++++ sys/arm/samsung/exynos/files.exynos5 | 24 ++ sys/arm/samsung/exynos/std.exynos5 | 23 ++ sys/arm/samsung/exynos/uart.c | 377 +++++++++++++++++++++++++++++++ sys/arm/samsung/exynos/uart.h | 126 +++++++++++ 10 files changed, 1480 insertions(+) create mode 100644 sys/arm/samsung/exynos/arch_timer.c create mode 100644 sys/arm/samsung/exynos/bus_space.c create mode 100644 sys/arm/samsung/exynos/common.c create mode 100644 sys/arm/samsung/exynos/ehci_exynos5.c create mode 100644 sys/arm/samsung/exynos/exynos5_machdep.c create mode 100644 sys/arm/samsung/exynos/exynos5_mp.c create mode 100644 sys/arm/samsung/exynos/files.exynos5 create mode 100644 sys/arm/samsung/exynos/std.exynos5 create mode 100644 sys/arm/samsung/exynos/uart.c create mode 100644 sys/arm/samsung/exynos/uart.h (limited to 'sys/arm/samsung') diff --git a/sys/arm/samsung/exynos/arch_timer.c b/sys/arm/samsung/exynos/arch_timer.c new file mode 100644 index 000000000000..e5970b6f4bae --- /dev/null +++ b/sys/arm/samsung/exynos/arch_timer.c @@ -0,0 +1,136 @@ +/*- + * Copyright (c) 2013 Ruslan Bukin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * This module just enables Exynos MCT, so ARMv7 Generic Timer will works + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#define MCT_CTRL_START (1 << 8) +#define MCT_CTRL (0x240) +#define MCT_WRITE_STAT (0x24C) + +struct arm_tmr_softc { + struct resource *tmr_res[1]; + bus_space_tag_t bst; + bus_space_handle_t bsh; +}; + +static struct resource_spec arm_tmr_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Timer registers */ + { -1, 0 } +}; + +static int +arm_tmr_probe(device_t dev) +{ + if (!ofw_bus_is_compatible(dev, "exynos,mct")) + return (ENXIO); + + device_set_desc(dev, "Exynos MPCore Timer"); + return (BUS_PROBE_DEFAULT); +} + +static int +arm_tmr_attach(device_t dev) +{ + struct arm_tmr_softc *sc; + int reg, i; + int mask; + + sc = device_get_softc(dev); + + if (bus_alloc_resources(dev, arm_tmr_spec, sc->tmr_res)) { + device_printf(dev, "could not allocate resources\n"); + return (ENXIO); + } + + /* Timer interface */ + sc->bst = rman_get_bustag(sc->tmr_res[0]); + sc->bsh = rman_get_bushandle(sc->tmr_res[0]); + + reg = bus_space_read_4(sc->bst, sc->bsh, MCT_CTRL); + reg |= MCT_CTRL_START; + bus_space_write_4(sc->bst, sc->bsh, MCT_CTRL, reg); + + mask = (1 << 16); + + /* Wait 10 times until written value is applied */ + for (i = 0; i < 10; i++) { + reg = bus_space_read_4(sc->bst, sc->bsh, MCT_WRITE_STAT); + if (reg & mask) { + bus_space_write_4(sc->bst, sc->bsh, + MCT_WRITE_STAT, mask); + return (0); + } + cpufunc_nullop(); + } + + /* NOTREACHED */ + + panic("Can't enable timer\n"); +} + +static device_method_t arm_tmr_methods[] = { + DEVMETHOD(device_probe, arm_tmr_probe), + DEVMETHOD(device_attach, arm_tmr_attach), + { 0, 0 } +}; + +static driver_t arm_tmr_driver = { + "arch_timer", + arm_tmr_methods, + sizeof(struct arm_tmr_softc), +}; + +static devclass_t arm_tmr_devclass; + +DRIVER_MODULE(arch_timer, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0); diff --git a/sys/arm/samsung/exynos/bus_space.c b/sys/arm/samsung/exynos/bus_space.c new file mode 100644 index 000000000000..8d21f559c893 --- /dev/null +++ b/sys/arm/samsung/exynos/bus_space.c @@ -0,0 +1,153 @@ +/*- + * Copyright (c) 2012 Damjan Marion + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include + +#include + +/* Prototypes for all the bus_space structure functions */ +bs_protos(generic); +bs_protos(generic_armv4); + +/* + * The bus space tag. This is constant for all instances, so + * we never have to explicitly "create" it. + */ +static struct bus_space _base_tag = { + /* cookie */ + (void *) 0, + + /* mapping/unmapping */ + generic_bs_map, + generic_bs_unmap, + generic_bs_subregion, + + /* allocation/deallocation */ + generic_bs_alloc, + generic_bs_free, + + /* barrier */ + generic_bs_barrier, + + /* read (single) */ + generic_bs_r_1, + generic_armv4_bs_r_2, + generic_bs_r_4, + NULL, + + /* read multiple */ + generic_bs_rm_1, + generic_armv4_bs_rm_2, + generic_bs_rm_4, + NULL, + + /* read region */ + generic_bs_rr_1, + generic_armv4_bs_rr_2, + generic_bs_rr_4, + NULL, + + /* write (single) */ + generic_bs_w_1, + generic_armv4_bs_w_2, + generic_bs_w_4, + NULL, + + /* write multiple */ + generic_bs_wm_1, + generic_armv4_bs_wm_2, + generic_bs_wm_4, + NULL, + + /* write region */ + NULL, + NULL, + NULL, + NULL, + + /* set multiple */ + NULL, + NULL, + NULL, + NULL, + + /* set region */ + NULL, + NULL, + NULL, + NULL, + + /* copy */ + NULL, + NULL, + NULL, + NULL, + + /* read stream (single) */ + NULL, + NULL, + NULL, + NULL, + + /* read multiple stream */ + NULL, + generic_armv4_bs_rm_2, /* bus_space_read_multi_stream_2 */ + NULL, + NULL, + + /* read region stream */ + NULL, + NULL, + NULL, + NULL, + + /* write stream (single) */ + NULL, + NULL, + NULL, + NULL, + + /* write multiple stream */ + NULL, + generic_armv4_bs_wm_2, /* bus_space_write_multi_stream_2 */ + NULL, + NULL, + + /* write region stream */ + NULL, + NULL, + NULL, + NULL +}; + +bus_space_tag_t fdtbus_bs_tag = &_base_tag; diff --git a/sys/arm/samsung/exynos/common.c b/sys/arm/samsung/exynos/common.c new file mode 100644 index 000000000000..658efc417298 --- /dev/null +++ b/sys/arm/samsung/exynos/common.c @@ -0,0 +1,73 @@ +/*- + * Copyright (c) 2013 Ruslan Bukin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include + +#include +#include + +#include +#include + +void +cpu_reset(void) +{ + bus_space_handle_t bsh; + + bus_space_map(fdtbus_bs_tag, 0x10040400, 0x1000, 0, &bsh); + bus_space_write_4(fdtbus_bs_tag, bsh, 0, 1); + + while (1); +} + +struct fdt_fixup_entry fdt_fixup_table[] = { + { NULL, NULL } +}; + +static int +fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, + int *pol) +{ + + if (!fdt_is_compatible(node, "arm,gic")) + return (ENXIO); + + *interrupt = fdt32_to_cpu(intr[0]); + *trig = INTR_TRIGGER_CONFORM; + *pol = INTR_POLARITY_CONFORM; + return (0); +} + +fdt_pic_decode_t fdt_pic_table[] = { + &fdt_pic_decode_ic, + NULL +}; diff --git a/sys/arm/samsung/exynos/ehci_exynos5.c b/sys/arm/samsung/exynos/ehci_exynos5.c new file mode 100644 index 000000000000..ada0405754a9 --- /dev/null +++ b/sys/arm/samsung/exynos/ehci_exynos5.c @@ -0,0 +1,367 @@ +/*- + * Copyright (c) 2013 Ruslan Bukin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include "opt_bus.h" + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include "opt_platform.h" + +/* GPIO control */ +#define GPIO_CON(x, v) ((v) << ((x) * 4)) +#define GPIO_MASK 0xf +#define GPIO_OUTPUT 1 +#define GPIO_INPUT 0 +#define GPX3CON 0x0C60 +#define GPX3DAT 0x0C64 +#define PIN_USB 5 + +/* PWR control */ +#define EXYNOS5_PWR_USBHOST_PHY 0x708 +#define PHY_POWER_ON 1 +#define PHY_POWER_OFF 0 + +/* SYSREG */ +#define EXYNOS5_SYSREG_USB2_PHY 0x230 +#define USB2_MODE_HOST 0x1 + +/* USB HOST */ +#define HOST_CTRL_CLK_24MHZ (5 << 16) +#define HOST_CTRL_CLK_MASK (7 << 16) +#define HOST_CTRL_SIDDQ (1 << 6) +#define HOST_CTRL_SLEEP (1 << 5) +#define HOST_CTRL_SUSPEND (1 << 4) +#define HOST_CTRL_RESET_LINK (1 << 1) +#define HOST_CTRL_RESET_PHY (1 << 0) +#define HOST_CTRL_RESET_PHY_ALL (1 << 31) + +/* Forward declarations */ +static int exynos_ehci_attach(device_t dev); +static int exynos_ehci_detach(device_t dev); +static int exynos_ehci_probe(device_t dev); + +struct exynos_ehci_softc { + ehci_softc_t base; + struct resource *res[6]; + bus_space_tag_t host_bst; + bus_space_tag_t pwr_bst; + bus_space_tag_t sysreg_bst; + bus_space_tag_t gpio_bst; + bus_space_handle_t host_bsh; + bus_space_handle_t pwr_bsh; + bus_space_handle_t sysreg_bsh; + bus_space_handle_t gpio_bsh; + +}; + +static struct resource_spec exynos_ehci_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_MEMORY, 1, RF_ACTIVE }, + { SYS_RES_MEMORY, 2, RF_ACTIVE }, + { SYS_RES_MEMORY, 3, RF_ACTIVE }, + { SYS_RES_MEMORY, 4, RF_ACTIVE }, + { SYS_RES_IRQ, 0, RF_ACTIVE }, + { -1, 0 } +}; + +static device_method_t ehci_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, exynos_ehci_probe), + DEVMETHOD(device_attach, exynos_ehci_attach), + DEVMETHOD(device_detach, exynos_ehci_detach), + DEVMETHOD(device_suspend, bus_generic_suspend), + DEVMETHOD(device_resume, bus_generic_resume), + DEVMETHOD(device_shutdown, bus_generic_shutdown), + + /* Bus interface */ + DEVMETHOD(bus_print_child, bus_generic_print_child), + + { 0, 0 } +}; + +/* kobj_class definition */ +static driver_t ehci_driver = { + "ehci", + ehci_methods, + sizeof(ehci_softc_t) +}; + +static devclass_t ehci_devclass; + +DRIVER_MODULE(ehci, simplebus, ehci_driver, ehci_devclass, 0, 0); +MODULE_DEPEND(ehci, usb, 1, 1, 1); + +/* + * Public methods + */ +static int +exynos_ehci_probe(device_t dev) +{ + + if (ofw_bus_is_compatible(dev, "exynos,usb-ehci") == 0) + return (ENXIO); + + device_set_desc(dev, "Exynos integrated USB controller"); + return (BUS_PROBE_DEFAULT); +} + +static int +gpio_ctrl(struct exynos_ehci_softc *esc, int dir, int power) +{ + int reg; + + /* Power control */ + reg = bus_space_read_4(esc->gpio_bst, esc->gpio_bsh, GPX3DAT); + reg &= ~(1 << PIN_USB); + reg |= (power << PIN_USB); + bus_space_write_4(esc->gpio_bst, esc->gpio_bsh, GPX3DAT, reg); + + /* Input/Output control */ + reg = bus_space_read_4(esc->gpio_bst, esc->gpio_bsh, GPX3CON); + reg &= ~GPIO_CON(PIN_USB, GPIO_MASK); + reg |= GPIO_CON(PIN_USB, dir); + bus_space_write_4(esc->gpio_bst, esc->gpio_bsh, GPX3CON, reg); + + return (0); +} + +static int +phy_init(struct exynos_ehci_softc *esc) +{ + int reg; + + gpio_ctrl(esc, GPIO_INPUT, 1); + + /* set USB HOST mode */ + bus_space_write_4(esc->sysreg_bst, esc->sysreg_bsh, + EXYNOS5_SYSREG_USB2_PHY, USB2_MODE_HOST); + + /* Power ON phy */ + bus_space_write_4(esc->pwr_bst, esc->pwr_bsh, + EXYNOS5_PWR_USBHOST_PHY, PHY_POWER_ON); + + reg = bus_space_read_4(esc->host_bst, esc->host_bsh, 0x0); + reg &= ~(HOST_CTRL_CLK_MASK | + HOST_CTRL_RESET_PHY | + HOST_CTRL_RESET_PHY_ALL | + HOST_CTRL_SIDDQ | + HOST_CTRL_SUSPEND | + HOST_CTRL_SLEEP); + + reg |= (HOST_CTRL_CLK_24MHZ | + HOST_CTRL_RESET_LINK); + bus_space_write_4(esc->host_bst, esc->host_bsh, 0x0, reg); + + DELAY(10); + + reg = bus_space_read_4(esc->host_bst, esc->host_bsh, 0x0); + reg &= ~(HOST_CTRL_RESET_LINK); + bus_space_write_4(esc->host_bst, esc->host_bsh, 0x0, reg); + + gpio_ctrl(esc, GPIO_OUTPUT, 1); + + return (0); +} + +static int +exynos_ehci_attach(device_t dev) +{ + struct exynos_ehci_softc *esc; + ehci_softc_t *sc; + bus_space_handle_t bsh; + int err; + + esc = device_get_softc(dev); + sc = &esc->base; + sc->sc_bus.parent = dev; + sc->sc_bus.devices = sc->sc_devices; + sc->sc_bus.devices_max = EHCI_MAX_DEVICES; + + if (bus_alloc_resources(dev, exynos_ehci_spec, esc->res)) { + device_printf(dev, "could not allocate resources\n"); + return (ENXIO); + } + + /* EHCI registers */ + sc->sc_io_tag = rman_get_bustag(esc->res[0]); + bsh = rman_get_bushandle(esc->res[0]); + sc->sc_io_size = rman_get_size(esc->res[0]); + + /* EHCI HOST ctrl registers */ + esc->host_bst = rman_get_bustag(esc->res[1]); + esc->host_bsh = rman_get_bushandle(esc->res[1]); + + /* PWR registers */ + esc->pwr_bst = rman_get_bustag(esc->res[2]); + esc->pwr_bsh = rman_get_bushandle(esc->res[2]); + + /* SYSREG */ + esc->sysreg_bst = rman_get_bustag(esc->res[3]); + esc->sysreg_bsh = rman_get_bushandle(esc->res[3]); + + /* GPIO */ + esc->gpio_bst = rman_get_bustag(esc->res[4]); + esc->gpio_bsh = rman_get_bushandle(esc->res[4]); + + /* get all DMA memory */ + if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(dev), + &ehci_iterate_hw_softc)) + return (ENXIO); + + /* + * Set handle to USB related registers subregion used by + * generic EHCI driver. + */ + err = bus_space_subregion(sc->sc_io_tag, bsh, 0x0, + sc->sc_io_size, &sc->sc_io_hdl); + if (err != 0) + return (ENXIO); + + phy_init(esc); + + /* Setup interrupt handler */ + err = bus_setup_intr(dev, esc->res[5], INTR_TYPE_BIO | INTR_MPSAFE, + NULL, (driver_intr_t *)ehci_interrupt, sc, + &sc->sc_intr_hdl); + if (err) { + device_printf(dev, "Could not setup irq, " + "%d\n", err); + return (1); + } + + /* Add USB device */ + sc->sc_bus.bdev = device_add_child(dev, "usbus", -1); + if (!sc->sc_bus.bdev) { + device_printf(dev, "Could not add USB device\n"); + err = bus_teardown_intr(dev, esc->res[5], + sc->sc_intr_hdl); + if (err) + device_printf(dev, "Could not tear down irq," + " %d\n", err); + return (1); + } + device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); + + strlcpy(sc->sc_vendor, "Samsung", sizeof(sc->sc_vendor)); + + err = ehci_init(sc); + if (!err) { + sc->sc_flags |= EHCI_SCFLG_DONEINIT; + err = device_probe_and_attach(sc->sc_bus.bdev); + } else { + device_printf(dev, "USB init failed err=%d\n", err); + + device_delete_child(dev, sc->sc_bus.bdev); + sc->sc_bus.bdev = NULL; + + err = bus_teardown_intr(dev, esc->res[5], + sc->sc_intr_hdl); + if (err) + device_printf(dev, "Could not tear down irq," + " %d\n", err); + return (1); + } + return (0); +} + +static int +exynos_ehci_detach(device_t dev) +{ + struct exynos_ehci_softc *esc; + ehci_softc_t *sc; + int err; + + esc = device_get_softc(dev); + sc = &esc->base; + + if (sc->sc_flags & EHCI_SCFLG_DONEINIT) + return (0); + + /* + * only call ehci_detach() after ehci_init() + */ + if (sc->sc_flags & EHCI_SCFLG_DONEINIT) { + ehci_detach(sc); + sc->sc_flags &= ~EHCI_SCFLG_DONEINIT; + } + + /* + * Disable interrupts that might have been switched on in + * ehci_init. + */ + if (sc->sc_io_tag && sc->sc_io_hdl) + bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, + EHCI_USBINTR, 0); + + if (esc->res[5] && sc->sc_intr_hdl) { + err = bus_teardown_intr(dev, esc->res[5], + sc->sc_intr_hdl); + if (err) { + device_printf(dev, "Could not tear down irq," + " %d\n", err); + return (err); + } + sc->sc_intr_hdl = NULL; + } + + if (sc->sc_bus.bdev) { + device_delete_child(dev, sc->sc_bus.bdev); + sc->sc_bus.bdev = NULL; + } + + /* During module unload there are lots of children leftover */ + device_delete_children(dev); + + bus_release_resources(dev, exynos_ehci_spec, esc->res); + + return (0); +} diff --git a/sys/arm/samsung/exynos/exynos5_machdep.c b/sys/arm/samsung/exynos/exynos5_machdep.c new file mode 100644 index 000000000000..4927aed7a008 --- /dev/null +++ b/sys/arm/samsung/exynos/exynos5_machdep.c @@ -0,0 +1,109 @@ +/*- + * Copyright (c) 2013 Ruslan Bukin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "opt_ddb.h" +#include "opt_platform.h" + +#include +__FBSDID("$FreeBSD$"); + +#define _ARM32_BUS_DMA_PRIVATE +#include +#include +#include + +#include +#include + +#include +#include /* For trapframe_t, used in */ +#include +#include + +#include + +#define DEVMAP_BOOTSTRAP_MAP_START 0xE0000000 + +extern int unmapped_buf_allowed; + +vm_offset_t +initarm_lastaddr(void) +{ + + return (DEVMAP_BOOTSTRAP_MAP_START - ARM_NOCACHE_KVA_SIZE); +} + +void +initarm_gpio_init(void) +{ +} + +void +initarm_late_init(void) +{ + + /* XXX: PR arm/180080 */ + unmapped_buf_allowed = 0; +} + +#define FDT_DEVMAP_MAX (1 + 2 + 1 + 1) /* FIXME */ +static struct pmap_devmap fdt_devmap[FDT_DEVMAP_MAX] = { + { 0, 0, 0, 0, 0, } +}; + +/* + * Construct pmap_devmap[] with DT-derived config data. + */ +int +platform_devmap_init(void) +{ + int i; + + i = 0; + fdt_devmap[i].pd_va = 0xe2C00000; + fdt_devmap[i].pd_pa = 0x12C00000; + fdt_devmap[i].pd_size = 0x100000; + fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE; + fdt_devmap[i].pd_cache = PTE_NOCACHE; + i++; + + pmap_devmap_bootstrap_table = &fdt_devmap[0]; + return (0); +} + +struct arm32_dma_range * +bus_dma_get_range(void) +{ + + return (NULL); +} + +int +bus_dma_get_range_nb(void) +{ + + return (0); +} diff --git a/sys/arm/samsung/exynos/exynos5_mp.c b/sys/arm/samsung/exynos/exynos5_mp.c new file mode 100644 index 000000000000..e99b61e8c617 --- /dev/null +++ b/sys/arm/samsung/exynos/exynos5_mp.c @@ -0,0 +1,92 @@ +/*- + * Copyright (c) 2013 Ruslan Bukin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define EXYNOS_SYSRAM 0x02020000 + +void mpentry(void); +void mptramp(void); + +void +platform_mp_init_secondary(void) +{ + + gic_init_secondary(); +} + +void +platform_mp_setmaxid(void) +{ + + mp_maxid = 1; +} + +int +platform_mp_probe(void) +{ + + mp_ncpus = 2; + return (1); +} + +void +platform_mp_start_ap(void) +{ + bus_addr_t sysram; + int err; + + err = bus_space_map(fdtbus_bs_tag, EXYNOS_SYSRAM, 0x100, 0, &sysram); + if (err != 0) + panic("Couldn't map sysram\n"); + + bus_space_write_4(fdtbus_bs_tag, sysram, 0x0, + pmap_kextract((vm_offset_t)mpentry)); + + cpu_idcache_wbinv_all(); + cpu_l2cache_wbinv_all(); + + armv7_sev(); + bus_space_unmap(fdtbus_bs_tag, sysram, 0x100); +} + +void +platform_ipi_send(cpuset_t cpus, u_int ipi) +{ + + pic_ipi_send(cpus, ipi); +} diff --git a/sys/arm/samsung/exynos/files.exynos5 b/sys/arm/samsung/exynos/files.exynos5 new file mode 100644 index 000000000000..e0b74074d1eb --- /dev/null +++ b/sys/arm/samsung/exynos/files.exynos5 @@ -0,0 +1,24 @@ +# $FreeBSD$ + +kern/kern_clocksource.c standard + +arm/arm/bus_space_generic.c standard +arm/arm/bus_space_asm_generic.S standard +arm/arm/cpufunc_asm_armv5.S standard +arm/arm/cpufunc_asm_arm10.S standard +arm/arm/cpufunc_asm_arm11.S standard +arm/arm/cpufunc_asm_armv7.S standard +arm/arm/irq_dispatch.S standard + +arm/arm/gic.c standard +arm/arm/generic_timer.c standard + +arm/samsung/exynos/arch_timer.c standard +arm/samsung/exynos/exynos5_mp.c optional smp +arm/samsung/exynos/bus_space.c standard +arm/samsung/exynos/common.c standard +arm/samsung/exynos/exynos5_machdep.c standard +arm/samsung/exynos/uart.c optional uart +arm/samsung/exynos/ehci_exynos5.c optional ehci + +#dev/sdhci/sdhci_fdt.c optional sdhci diff --git a/sys/arm/samsung/exynos/std.exynos5 b/sys/arm/samsung/exynos/std.exynos5 new file mode 100644 index 000000000000..58f692cc0009 --- /dev/null +++ b/sys/arm/samsung/exynos/std.exynos5 @@ -0,0 +1,23 @@ +# $FreeBSD$ + +makeoption ARM_LITTLE_ENDIAN + +cpu CPU_CORTEXA +machine arm armv6 + +options PHYSADDR=0x40000000 + +makeoptions KERNPHYSADDR=0x40f00000 +options KERNPHYSADDR=0x40f00000 + +makeoptions KERNVIRTADDR=0xc0f00000 +options KERNVIRTADDR=0xc0f00000 + +options STARTUP_PAGETABLE_ADDR=0x40100000 + +options ARM_L2_PIPT + +options IPI_IRQ_START=0 +options IPI_IRQ_END=15 + +files "../samsung/exynos/files.exynos5" diff --git a/sys/arm/samsung/exynos/uart.c b/sys/arm/samsung/exynos/uart.c new file mode 100644 index 000000000000..eef99ff808b9 --- /dev/null +++ b/sys/arm/samsung/exynos/uart.c @@ -0,0 +1,377 @@ +/* + * Copyright (c) 2003 Marcel Moolenaar + * Copyright (c) 2007-2009 Andrew Turner + * Copyright (c) 2013 Ruslan Bukin + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "uart_if.h" + +#define DEF_CLK 100000000 + +static int sscomspeed(long, long); +static int s3c24x0_uart_param(struct uart_bas *, int, int, int, int); + +/* + * Low-level UART interface. + */ +static int s3c2410_probe(struct uart_bas *bas); +static void s3c2410_init(struct uart_bas *bas, int, int, int, int); +static void s3c2410_term(struct uart_bas *bas); +static void s3c2410_putc(struct uart_bas *bas, int); +static int s3c2410_rxready(struct uart_bas *bas); +static int s3c2410_getc(struct uart_bas *bas, struct mtx *mtx); + +extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; + +static int +sscomspeed(long speed, long frequency) +{ + int x; + + if (speed <= 0 || frequency <= 0) + return (-1); + x = (frequency / 16) / speed; + return (x-1); +} + +static int +s3c24x0_uart_param(struct uart_bas *bas, int baudrate, int databits, + int stopbits, int parity) +{ + int brd, ulcon; + + ulcon = 0; + + switch(databits) { + case 5: + ulcon |= ULCON_LENGTH_5; + break; + case 6: + ulcon |= ULCON_LENGTH_6; + break; + case 7: + ulcon |= ULCON_LENGTH_7; + break; + case 8: + ulcon |= ULCON_LENGTH_8; + break; + default: + return (EINVAL); + } + + switch (parity) { + case UART_PARITY_NONE: + ulcon |= ULCON_PARITY_NONE; + break; + case UART_PARITY_ODD: + ulcon |= ULCON_PARITY_ODD; + break; + case UART_PARITY_EVEN: + ulcon |= ULCON_PARITY_EVEN; + break; + case UART_PARITY_MARK: + case UART_PARITY_SPACE: + default: + return (EINVAL); + } + + if (stopbits == 2) + ulcon |= ULCON_STOP; + + uart_setreg(bas, SSCOM_ULCON, ulcon); + + brd = sscomspeed(baudrate, bas->rclk); + uart_setreg(bas, SSCOM_UBRDIV, brd); + + return (0); +} + +struct uart_ops uart_s3c2410_ops = { + .probe = s3c2410_probe, + .init = s3c2410_init, + .term = s3c2410_term, + .putc = s3c2410_putc, + .rxready = s3c2410_rxready, + .getc = s3c2410_getc, +}; + +static int +s3c2410_probe(struct uart_bas *bas) +{ + + return (0); +} + +static void +s3c2410_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, + int parity) +{ + + if (bas->rclk == 0) + bas->rclk = DEF_CLK; + + KASSERT(bas->rclk != 0, ("s3c2410_init: Invalid rclk")); + + uart_setreg(bas, SSCOM_UCON, 0); + uart_setreg(bas, SSCOM_UFCON, + UFCON_TXTRIGGER_8 | UFCON_RXTRIGGER_8 | + UFCON_TXFIFO_RESET | UFCON_RXFIFO_RESET | + UFCON_FIFO_ENABLE); + s3c24x0_uart_param(bas, baudrate, databits, stopbits, parity); + + /* Enable UART. */ + uart_setreg(bas, SSCOM_UCON, UCON_TXMODE_INT | UCON_RXMODE_INT | + UCON_TOINT); + uart_setreg(bas, SSCOM_UMCON, UMCON_RTS); +} + +static void +s3c2410_term(struct uart_bas *bas) +{ + /* XXX */ +} + +static void +s3c2410_putc(struct uart_bas *bas, int c) +{ + + while ((bus_space_read_4(bas->bst, bas->bsh, SSCOM_UFSTAT) & + UFSTAT_TXFULL) == UFSTAT_TXFULL) + continue; + + uart_setreg(bas, SSCOM_UTXH, c); +} + +static int +s3c2410_rxready(struct uart_bas *bas) +{ + + return ((uart_getreg(bas, SSCOM_UTRSTAT) & UTRSTAT_RXREADY) == + UTRSTAT_RXREADY); +} + +static int +s3c2410_getc(struct uart_bas *bas, struct mtx *mtx) +{ + int utrstat; + + utrstat = bus_space_read_1(bas->bst, bas->bsh, SSCOM_UTRSTAT); + while (!(utrstat & UTRSTAT_RXREADY)) { + utrstat = bus_space_read_1(bas->bst, bas->bsh, SSCOM_UTRSTAT); + continue; + } + + return (bus_space_read_1(bas->bst, bas->bsh, SSCOM_URXH)); +} + +static int s3c2410_bus_probe(struct uart_softc *sc); +static int s3c2410_bus_attach(struct uart_softc *sc); +static int s3c2410_bus_flush(struct uart_softc *, int); +static int s3c2410_bus_getsig(struct uart_softc *); +static int s3c2410_bus_ioctl(struct uart_softc *, int, intptr_t); +static int s3c2410_bus_ipend(struct uart_softc *); +static int s3c2410_bus_param(struct uart_softc *, int, int, int, int); +static int s3c2410_bus_receive(struct uart_softc *); +static int s3c2410_bus_setsig(struct uart_softc *, int); +static int s3c2410_bus_transmit(struct uart_softc *); + +static kobj_method_t s3c2410_methods[] = { + KOBJMETHOD(uart_probe, s3c2410_bus_probe), + KOBJMETHOD(uart_attach, s3c2410_bus_attach), + KOBJMETHOD(uart_flush, s3c2410_bus_flush), + KOBJMETHOD(uart_getsig, s3c2410_bus_getsig), + KOBJMETHOD(uart_ioctl, s3c2410_bus_ioctl), + KOBJMETHOD(uart_ipend, s3c2410_bus_ipend), + KOBJMETHOD(uart_param, s3c2410_bus_param), + KOBJMETHOD(uart_receive, s3c2410_bus_receive), + KOBJMETHOD(uart_setsig, s3c2410_bus_setsig), + KOBJMETHOD(uart_transmit, s3c2410_bus_transmit), + + {0, 0 } +}; + +int +s3c2410_bus_probe(struct uart_softc *sc) +{ + + sc->sc_txfifosz = 16; + sc->sc_rxfifosz = 16; + + return (0); +} + +static int +s3c2410_bus_attach(struct uart_softc *sc) +{ + + sc->sc_hwiflow = 0; + sc->sc_hwoflow = 0; + + return (0); +} + +static int +s3c2410_bus_transmit(struct uart_softc *sc) +{ + int i; + int reg; + + uart_lock(sc->sc_hwmtx); + + for (i = 0; i < sc->sc_txdatasz; i++) { + s3c2410_putc(&sc->sc_bas, sc->sc_txbuf[i]); + uart_barrier(&sc->sc_bas); + } + + sc->sc_txbusy = 1; + + uart_unlock(sc->sc_hwmtx); + + /* unmask TX interrupt */ + reg = bus_space_read_4(sc->sc_bas.bst, sc->sc_bas.bsh, SSCOM_UINTM); + reg &= ~(1 << 2); + bus_space_write_4(sc->sc_bas.bst, sc->sc_bas.bsh, SSCOM_UINTM, reg); + + return (0); +} + +static int +s3c2410_bus_setsig(struct uart_softc *sc, int sig) +{ + + return (0); +} + +static int +s3c2410_bus_receive(struct uart_softc *sc) +{ + + uart_rx_put(sc, uart_getreg(&sc->sc_bas, SSCOM_URXH)); + return (0); +} + +static int +s3c2410_bus_param(struct uart_softc *sc, int baudrate, int databits, + int stopbits, int parity) +{ + int error; + + if (sc->sc_bas.rclk == 0) + sc->sc_bas.rclk = DEF_CLK; + + KASSERT(sc->sc_bas.rclk != 0, ("s3c2410_init: Invalid rclk")); + + uart_lock(sc->sc_hwmtx); + error = s3c24x0_uart_param(&sc->sc_bas, baudrate, databits, stopbits, + parity); + uart_unlock(sc->sc_hwmtx); + + return (error); +} + +static int +s3c2410_bus_ipend(struct uart_softc *sc) +{ + uint32_t ints; + uint32_t txempty, rxready; + int reg; + int ipend; + + uart_lock(sc->sc_hwmtx); + ints = bus_space_read_4(sc->sc_bas.bst, sc->sc_bas.bsh, SSCOM_UINTP); + bus_space_write_4(sc->sc_bas.bst, sc->sc_bas.bsh, SSCOM_UINTP, ints); + + txempty = (1 << 2); + rxready = (1 << 0); + + ipend = 0; + if ((ints & txempty) > 0) { + if (sc->sc_txbusy != 0) + ipend |= SER_INT_TXIDLE; + + /* mask TX interrupt */ + reg = bus_space_read_4(sc->sc_bas.bst, sc->sc_bas.bsh, + SSCOM_UINTM); + reg |= (1 << 2); + bus_space_write_4(sc->sc_bas.bst, sc->sc_bas.bsh, + SSCOM_UINTM, reg); + } + + if ((ints & rxready) > 0) { + ipend |= SER_INT_RXREADY; + } + + uart_unlock(sc->sc_hwmtx); + return (ipend); +} + +static int +s3c2410_bus_flush(struct uart_softc *sc, int what) +{ + + return (0); +} + +static int +s3c2410_bus_getsig(struct uart_softc *sc) +{ + + return (0); +} + +static int +s3c2410_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) +{ + + return (EINVAL); +} + +struct uart_class uart_s3c2410_class = { + "s3c2410 class", + s3c2410_methods, + 1, + .uc_ops = &uart_s3c2410_ops, + .uc_range = 8, + .uc_rclk = 0, +}; diff --git a/sys/arm/samsung/exynos/uart.h b/sys/arm/samsung/exynos/uart.h new file mode 100644 index 000000000000..06afeff1f14b --- /dev/null +++ b/sys/arm/samsung/exynos/uart.h @@ -0,0 +1,126 @@ +/* $NetBSD: s3c2xx0reg.h,v 1.4 2004/02/12 03:47:29 bsh Exp $ */ + +/*- + * Copyright (c) 2002, 2003 Fujitsu Component Limited + * Copyright (c) 2002, 2003 Genetec Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of The Fujitsu Component Limited nor the name of + * Genetec corporation may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC + * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC + * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* s3c2410-specific registers */ +#define UMCON_AFC (1 << 4) /* auto flow control */ +#define UMSTAT_DCTS (1 << 2) /* CTS change */ +#define ULCON_IR (1 << 6) +#define ULCON_PARITY_SHIFT 3 + +/* + * Exynos-specific + * + * UFSTAT_TXFULL register differs between Exynos and others. + * Others have UFSTAT_TXFULL (1 << 9) + */ +#define UFSTAT_TXFULL (1 << 24) + +#define SSCOM_UINTM 0x038 +#define SSCOM_UINTP 0x030 + +/* common for s3c2800 and s3c24x0 */ +#define SSCOM_ULCON 0x00 /* UART line control */ +#define ULCON_PARITY_NONE (0 << ULCON_PARITY_SHIFT) +#define ULCON_PARITY_ODD (4 << ULCON_PARITY_SHIFT) +#define ULCON_PARITY_EVEN (5 << ULCON_PARITY_SHIFT) +#define ULCON_PARITY_ONE (6 << ULCON_PARITY_SHIFT) +#define ULCON_PARITY_ZERO (7 << ULCON_PARITY_SHIFT) +#define ULCON_STOP (1 << 2) +#define ULCON_LENGTH_5 0 +#define ULCON_LENGTH_6 1 +#define ULCON_LENGTH_7 2 +#define ULCON_LENGTH_8 3 +#define SSCOM_UCON 0x04 /* UART control */ +#define UCON_TXINT_TYPE (1 << 9) /* Tx interrupt. 0=pulse,1=level */ +#define UCON_TXINT_TYPE_LEVEL UCON_TXINT_TYPE +#define UCON_TXINT_TYPE_PULSE 0 +#define UCON_RXINT_TYPE (1 << 8) /* Rx interrupt */ +#define UCON_RXINT_TYPE_LEVEL UCON_RXINT_TYPE +#define UCON_RXINT_TYPE_PULSE 0 +#define UCON_TOINT (1 << 7) /* Rx timeout interrupt */ +#define UCON_ERRINT (1 << 6) /* receive error interrupt */ +#define UCON_LOOP (1 << 5) /* loopback */ +#define UCON_SBREAK (1 << 4) /* send break */ +#define UCON_TXMODE_DISABLE (0 << 2) +#define UCON_TXMODE_INT (1 << 2) +#define UCON_TXMODE_DMA (2 << 2) +#define UCON_TXMODE_MASK (3 << 2) +#define UCON_RXMODE_DISABLE (0 << 0) +#define UCON_RXMODE_INT (1 << 0) +#define UCON_RXMODE_DMA (2 << 0) +#define UCON_RXMODE_MASK (3 << 0) +#define SSCOM_UFCON 0x08 /* FIFO control */ +#define UFCON_TXTRIGGER_0 (0 << 6) +#define UFCON_TXTRIGGER_4 (1 << 6) +#define UFCON_TXTRIGGER_8 (2 << 6) +#define UFCON_TXTRIGGER_16 (3 << 6) +#define UFCON_RXTRIGGER_4 (0 << 4) +#define UFCON_RXTRIGGER_8 (1 << 4) +#define UFCON_RXTRIGGER_12 (2 << 4) +#define UFCON_RXTRIGGER_16 (3 << 4) +#define UFCON_TXFIFO_RESET (1 << 2) +#define UFCON_RXFIFO_RESET (1 << 1) +#define UFCON_FIFO_ENABLE (1 << 0) +#define SSCOM_UMCON 0x0c /* MODEM control */ +#define UMCON_RTS (1 << 0) /* Request to send */ +#define SSCOM_UTRSTAT 0x10 /* Status register */ +#define UTRSTAT_TXSHIFTER_EMPTY ( 1<< 2) +#define UTRSTAT_TXEMPTY (1 << 1) /* TX fifo or buffer empty */ +#define UTRSTAT_RXREADY (1 << 0) /* RX fifo or buffer is not empty */ +#define SSCOM_UERSTAT 0x14 /* Error status register */ +#define UERSTAT_BREAK (1 << 3) /* Break signal, not 2410 */ +#define UERSTAT_FRAME (1 << 2) /* Frame error */ +#define UERSTAT_PARITY (1 << 1) /* Parity error, not 2410 */ +#define UERSTAT_OVERRUN (1 << 0) /* Overrun */ +#define UERSTAT_ALL_ERRORS \ + (UERSTAT_OVERRUN|UERSTAT_BREAK|UERSTAT_FRAME|UERSTAT_PARITY) +#define SSCOM_UFSTAT 0x18 /* Fifo status register */ +#define UFSTAT_RXFULL (1 <<8) /* Rx fifo full */ +#define UFSTAT_TXCOUNT_SHIFT 4 /* TX FIFO count */ +#define UFSTAT_TXCOUNT (0x0f << UFSTAT_TXCOUNT_SHIFT) +#define UFSTAT_RXCOUNT_SHIFT 0 /* RX FIFO count */ +#define UFSTAT_RXCOUNT (0x0f << UFSTAT_RXCOUNT_SHIFT) +#define SSCOM_UMSTAT 0x1c /* Modem status register */ +#define UMSTAT_CTS (1 << 0) /* Clear to send */ +#if _BYTE_ORDER == _LITTLE_ENDIAN +#define SSCOM_UTXH 0x20 /* Transmit data register */ +#define SSCOM_URXH 0x24 /* Receive data register */ +#else +#define SSCOM_UTXH 0x23 /* Transmit data register */ +#define SSCOM_URXH 0x27 /* Receive data register */ +#endif +#define SSCOM_UBRDIV 0x28 /* baud-reate divisor */ +#define SSCOM_SIZE 0x2c -- cgit v1.2.3