From 470273d7d9b92df0a17b1eb50fd9bbd6897b0472 Mon Sep 17 00:00:00 2001 From: John Baldwin Date: Tue, 22 Feb 2005 22:17:03 +0000 Subject: MFi386: r1.17: Treat pin 0 as IRQ 0 rather than ExtINT if mixed mode is not enabled by the enumerator. --- sys/amd64/amd64/io_apic.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'sys/amd64') diff --git a/sys/amd64/amd64/io_apic.c b/sys/amd64/amd64/io_apic.c index 4db0c227b722..350a90ae6413 100644 --- a/sys/amd64/amd64/io_apic.c +++ b/sys/amd64/amd64/io_apic.c @@ -548,10 +548,11 @@ ioapic_create(uintptr_t addr, int32_t apic_id, int intbase) /* * Assume that pin 0 on the first I/O APIC is an ExtINT pin - * and that pins 1-15 are ISA interrupts. Assume that all + * if mixed mode is enabled and an ISA interrupt if not. + * Assume that pins 1-15 are ISA interrupts and that all * other pins are PCI interrupts. */ - if (intpin->io_vector == 0) + if (intpin->io_vector == 0 && mixed_mode_enabled) ioapic_set_extint(io, i); else if (intpin->io_vector < IOAPIC_ISA_INTS) { intpin->io_bus = APIC_BUS_ISA; -- cgit v1.2.3