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* pf: Fix compliation warning with gccKristof Provost2015-10-251-2/+2
| | | | | | | | | | | While fixing the PF_ANEQ() macro I messed up the parentheses, leading to compliation warnings with gcc. Spotted by: ian Pointy Hat: kp Notes: svn path=/head/; revision=289940
* Rework r289933 using already existing macro.Alexander Motin2015-10-251-3/+2
| | | | Notes: svn path=/head/; revision=289939
* Try to keep Loop IDs persistent across chip reinits.Alexander Motin2015-10-252-40/+34
| | | | Notes: svn path=/head/; revision=289937
* drm/i915: Reduce diff with Linux 3.8Jean-Sébastien Pédron2015-10-251-6/+8
| | | | | | | | | | There is no functional change. The goal is to ease the future update to Linux 3.8's i915 driver. MFC after: 2 month Notes: svn path=/head/; revision=289936
* drm/i915: Reduce diff with Linux 3.8Jean-Sébastien Pédron2015-10-252-598/+563
| | | | | | | | | | There is no functional change. The goal is to ease the future update to Linux 3.8's i915 driver. MFC after: 2 months Notes: svn path=/head/; revision=289934
* Improve Port Database Changed handling and reporting.Alexander Motin2015-10-252-14/+17
| | | | Notes: svn path=/head/; revision=289933
* PF_ANEQ() macro will in most situations returns TRUE comparing two identicalKristof Provost2015-10-251-2/+3
| | | | | | | | | | | | | | | | IPv4 packets (when it should return FALSE). It happens because PF_ANEQ() doesn't stop if first 32 bits of IPv4 packets are equal and starts to check next 3*32 bits (like for IPv6 packet). Those bits containt some garbage and in result PF_ANEQ() wrongly returns TRUE. Fix: Check if packet is of AF_INET type and if it is then compare only first 32 bits of data. PR: 204005 Submitted by: Miłosz Kaniewski Notes: svn path=/head/; revision=289932
* Formalize/unify chip (re-)inits.Alexander Motin2015-10-254-51/+29
| | | | Notes: svn path=/head/; revision=289930
* ioat: Actually bring the hardware back online after resetConrad Meyer2015-10-242-13/+65
| | | | | | | | | | | | We need to reset the chancmp and chainaddr MMIO registers to bring the device back to a working state. Name the chanerr bits while we're here. Sponsored by: EMC / Isilon Storage Division Notes: svn path=/head/; revision=289912
* ioat: Use bus_alloc_resource_any(9)Conrad Meyer2015-10-241-2/+2
| | | | | | | Sponsored by: EMC / Isilon Storage Division Notes: svn path=/head/; revision=289911
* ioat: Extract halted error-debugging to a functionConrad Meyer2015-10-241-8/+17
| | | | | | | Sponsored by: EMC / Isilon Storage Division Notes: svn path=/head/; revision=289910
* ioat: Always re-arm interrupts in process_eventsConrad Meyer2015-10-241-4/+3
| | | | | | | | | It doesn't hurt, even if there is nothing to do. Sponsored by: EMC / Isilon Storage Division Notes: svn path=/head/; revision=289909
* ioat: Add sysctl to force hw resetConrad Meyer2015-10-241-16/+47
| | | | | | | | | To enable controlled testing. Sponsored by: EMC / Isilon Storage Division Notes: svn path=/head/; revision=289908
* ioat: refcnt users so we can drain them at detachConrad Meyer2015-10-244-11/+115
| | | | | | | | | | | | | | | | We only need to borrow a mutex for the drain sleep and the 0->1 transition, so just reuse an existing one for now. The wchan is arbitrary. Using refcount itself would have required __DEVOLATILE(), so use the lock's address instead. Different uses are tagged by kind, although we only do anything with that information in INVARIANTS builds. Sponsored by: EMC / Isilon Storage Division Notes: svn path=/head/; revision=289907
* ioat: When queueing operations, assert the submit lockConrad Meyer2015-10-241-0/+2
| | | | | | | | | | Callers should have acquired this lock when they invoked ioat_acquire() before issuing operations. Assert it is held. Sponsored by: EMC / Isilon Storage Division Notes: svn path=/head/; revision=289906
* ioat: Don't use sleeping allocation in lock pathConrad Meyer2015-10-241-11/+22
| | | | | | | | | | | This is still the worst possible way to allocate memory if it will ever be under pressure, but at least it won't deadlock. Suggested by: WITNESS Sponsored by: EMC / Isilon Storage Division Notes: svn path=/head/; revision=289905
* ioat: Pull out timer callout delay into a constantConrad Meyer2015-10-241-7/+10
| | | | | | | | | | | | Pull out the timer callout delay into IOAT_INTR_TIMO and shorten it considerably (5s -> 100ms). Single operations do not take 5-10 seconds and when interrupts aren't working, waiting 100ms sucks a lot less than 5s. Sponsored by: EMC / Isilon Storage Division Notes: svn path=/head/; revision=289904
* arge(4): flip this on for AR9344 SoCs.Adrian Chadd2015-10-241-0/+3
| | | | | | | | | | | | | I couldn't test arge0->arge1 bridging, only arge0 VLAN bridging. The DIR-825C1 only hooks up arge0 to the switch GMAC0 and so you need to abuse VLANs to test. Tested: * DIR-825C1 (AR9344) Notes: svn path=/head/; revision=289898
* Make vers.c creation atomic by using a temporary file, then movingEnji Cooper2015-10-241-4/+8
| | | | | | | | | | | | | | | | | | | the temporary file to vers.c at the end of the script The previous logic wrote out to vers.c multiple times, so the file could be incorrectly interpreted as being completely written out after one of the echo calls with recursive make, when in reality it was only partially written. Also, in the event the build was interrupted when creating vers.c (small race window), it would have a leftover file that needed to be cleaned up before resuming the build. MFC after: 3 weeks Sponsored by: EMC / Isilon Storage Division Notes: svn path=/head/; revision=289896
* Reduce the amount of calls to VOP_BMAP() made from the local vnodeKonstantin Belousov2015-10-241-81/+39
| | | | | | | | | | | | | | | | | | | | pager. It is enough to execute VOP_BMAP() once to obtain both the disk block address for the requested page, and the before/after limits for the contiguous run. The clipping of the vm_page_t array passed to the vnode_pager_generic_getpages() and the disk address for the first page in the clipped array can be deduced from the call results. While there, remove some noise (like if (1) {...}) and adjust nearby code. Reviewed by: alc Discussed with: glebius Tested by: pho Sponsored by: The FreeBSD Foundation MFC after: 3 weeks Notes: svn path=/head/; revision=289895
* Intel SDM before revision 56 described the CLFLUSH instruction as onlyKonstantin Belousov2015-10-244-26/+76
| | | | | | | | | | | | | | | | | | | | | | | | | ordered with the MFENCE instruction. Similar weak guarantees are also specified by the AMD APM vol. 3 rev. 3.22. x86 pmap methods pmap_invalidate_cache_range() and pmap_invalidate_cache_pages() braced CLFLUSH loop with MFENCE both before and after the loop. In the revision 56 of SDM, Intel stated that all existing implementations of CLFLUSH are strict, CLFLUSH instructions execution is ordered WRT other CLFLUSH and writes. Also, the strict behaviour is made architectural. A new instruction CLFLUSHOPT (which was documented for some time in the Instruction Set Extensions Programming Reference) provides the weak behaviour which was previously attributed to CLFLUSH. Use CLFLUSHOPT when available. When CLFLUSH is used on Intel CPUs, do not execute MFENCE before and after the flushing loop. Reviewed by: alc Sponsored by: The FreeBSD Foundation Notes: svn path=/head/; revision=289894
* Define a couple macros to access cacheline size/mask in an arch-dependentIan Lepore2015-10-241-4/+12
| | | | | | | way. This code should now work for all arm versions v4 thru v7. Notes: svn path=/head/; revision=289893
* Provide armv4/v5 implementations of several of the armv6 cache maintenanceIan Lepore2015-10-241-0/+48
| | | | | | | | functions. This will make it possible to use the same busdma code for all arm platforms v4 thru v7. Notes: svn path=/head/; revision=289892
* urtwn(4): fix mbuf leak in the TX pathAndriy Voskoboinyk2015-10-241-13/+12
| | | | | | | | | Reviewed by: kevlo Approved by: adrian (mentor) Differential Revision: https://reviews.freebsd.org/D3988 Notes: svn path=/head/; revision=289891
* Skip reserved IP Broadcast handle from using.Alexander Motin2015-10-242-4/+4
| | | | Notes: svn path=/head/; revision=289890
* - Plugging a memory leak when malloc() failed during initialisation;Tai-hwa Liang2015-10-241-4/+8
| | | | | | | | | | - Plugging another memory leak inside the destructor. Reviewed by: matk MFC after: 3 weeks Notes: svn path=/head/; revision=289888
* Rename dcache_dma_preread() to dcache_inv_poc_dma() to make it clear that itIan Lepore2015-10-242-8/+10
| | | | | | | | | is a dcache invalidate to point of coherency just like dcache_inv_poc(), but a slightly different version specific to dma operations. Elaborate the comment about how and why it's different. Notes: svn path=/head/; revision=289887
* Add new field to Abort IOCB.Alexander Motin2015-10-242-1/+4
| | | | Notes: svn path=/head/; revision=289886
* xen: Add missing semi-colon for BITSET_DEFINE()Conrad Meyer2015-10-241-1/+1
| | | | | | | | | | Broken when it was removed from the macro in r289867. Pointy-hat: markj Sponsored by: EMC / Isilon Storage Division Notes: svn path=/head/; revision=289884
* Add PIM_EXTLUNS support to isp(4) driver.Alexander Motin2015-10-244-42/+122
| | | | | | | | | Now 24xx and above chips support full 8-byte LUN address space. Older FC chips may support up to 16K LUNs when firmware allows. Tested in both initiator and target modes for 23xx, 24xx and 25xx. Notes: svn path=/head/; revision=289882
* Give CTL support for PIM_EXTLUNS when talking to CAM.Alexander Motin2015-10-245-101/+103
| | | | | | | | CTL itself still lives in flat LUN space, but it can generate extended numbers if CAM SIM reports such capability. Notes: svn path=/head/; revision=289881
* Remove ISP_INTERNAL_TARGET code.Alexander Motin2015-10-242-898/+0
| | | | | | | We have CTL now, which is real and much more functional then this joke. Notes: svn path=/head/; revision=289877
* Decode few more response info codes.Alexander Motin2015-10-241-13/+21
| | | | | | | Though CAM still does not send any requests that would require those. Notes: svn path=/head/; revision=289875
* Remove an erroneous semicolon.Mark Johnston2015-10-241-1/+1
| | | | | | | MFC after: 3 days Notes: svn path=/head/; revision=289867
* A few more whitespace, style, and comment cleanups. No functional changes.Ian Lepore2015-10-241-15/+10
| | | | Notes: svn path=/head/; revision=289865
* Bring in all the new(-ish) statistics code from armv6.Ian Lepore2015-10-241-64/+146
| | | | Notes: svn path=/head/; revision=289864
* Change the preallocation of a busdma segment mapping array from per-tag toIan Lepore2015-10-241-156/+93
| | | | | | | | | per-map. The per-tag scheme is not safe, and a mutex can't be used to protect it because the mapping routines can't sleep. Code brought in from armv6 implementation. Notes: svn path=/head/; revision=289862
* Instead of all memory allocations using M_DEVBUF, use new categoriesIan Lepore2015-10-231-14/+18
| | | | | | | | M_BUSDMA for allocations of metadata (tags, maps, segment tracking lists), and M_BOUNCE for bounce pages. Notes: svn path=/head/; revision=289858
* Instead of all memory allocations using M_DEVBUF, use new categoriesIan Lepore2015-10-231-21/+24
| | | | | | | | M_BUSDMA for allocations of metadata (tags, maps, segment tracking lists), and M_BOUNCE for bounce pages. Notes: svn path=/head/; revision=289857
* Minor additions to Status Type 0 IOCB.Alexander Motin2015-10-232-6/+7
| | | | Notes: svn path=/head/; revision=289855
* Catch up to r232356: change the boundary constraint type to bus_addr_t.Ian Lepore2015-10-231-2/+2
| | | | | | | | This code lived in the projects/armv6 branch when that change got applied to all the other arches. Notes: svn path=/head/; revision=289854
* Add aarch64 files to the hwpmc(4) module buildEd Maste2015-10-231-0/+4
| | | | | | | | | | This was probably missed because FreeBSD/arm64 did not yet support modules when aarch64 support was added to hwpmc(4). Submitted by: andrew Notes: svn path=/head/; revision=289853
* Missed addition for r289812.Alexander Motin2015-10-231-1/+1
| | | | Notes: svn path=/head/; revision=289852
* Whitespace and style nits, no functional changes.Ian Lepore2015-10-232-149/+131
| | | | | | | | | | | The goal is to make these two files cosmetically alike so that the actual implementation differences are visible. The only changes which aren't spaces<->tabs and rewrapping and reindenting lines are a couple fields shuffled around in the tag and map structs so that everything is in the same order in both versions (which should amount to no functional change). Notes: svn path=/head/; revision=289851
* Add partial support for QUERY TMF to CAM and isp(4).Alexander Motin2015-10-236-10/+41
| | | | | | | | | | | This change allows to decode respective functions in isp(4) in target mode and pass them through CAM to CTL. Unfortunately neither CAM nor isp(4) support returning response info for those task management functions now. On the other side I just have no initiator to test this functionality. Notes: svn path=/head/; revision=289843
* run(4): convert to ieee80211_tx_complete()Andriy Voskoboinyk2015-10-231-14/+5
| | | | | | | | Approved by: adrian (mentor) Differential Revision: https://reviews.freebsd.org/D3992 Notes: svn path=/head/; revision=289841
* Improve INOTs handling for 24xx and above chips.Alexander Motin2015-10-235-90/+87
| | | | Notes: svn path=/head/; revision=289838
* blkfront: add support for unmapped IORoger Pau Monné2015-10-231-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | Using unmapped IO is really beneficial when running inside of a VM, since it avoids IPIs to other vCPUs in order to invalidate the mappings. This patch adds unmapped IO support to blkfront. The following tests results have been obtained when running on a Xen host without HAP: PVHVM 3165.84 real 6354.17 user 4483.32 sys PVHVM with unmapped IO 2099.46 real 4624.52 user 2967.38 sys This is because when running using shadow page tables TLB flushes and range invalidations are much more expensive, so using unmapped IO provides a very important performance boost. Sponsored by: Citrix Systems R&D MFC after: 2 weeks X-MFC-with: r289834 Notes: svn path=/head/; revision=289836
* x86/dma_bounce: rework _bus_dmamap_load_ma implementationRoger Pau Monné2015-10-231-16/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The implementation of bus_dmamap_load_ma_triv currently calls _bus_dmamap_load_phys on each page that is part of the passed in buffer. Since each page is treated as an individual buffer, the resulting behaviour is different from the behaviour of _bus_dmamap_load_buffer. This breaks certain drivers, like Xen blkfront. If an unmapped buffer of size 4096 that starts at offset 13 into the first page is passed to the current _bus_dmamap_load_ma implementation (so the ma array contains two pages), the result is that two segments are created, one with a size of 4083 and the other with size 13 (because two independant calls to _bus_dmamap_load_phys are performed, one for each physical page). If the same is done with a mapped buffer and calling _bus_dmamap_load_buffer the result is that only one segment is created, with a size of 4096. This patch relegates the usage of bus_dmamap_load_ma_triv in x86 bounce buffer code to drivers requesting BUS_DMA_KEEP_PG_OFFSET and implements _bus_dmamap_load_ma so that it's behaviour is the same as the mapped version (_bus_dmamap_load_buffer). This patch only modifies the x86 bounce buffer code, other arches are left untouched. Reviewed by: kib, jah Differential Revision: https://reviews.freebsd.org/D888 Sponsored by: Citrix Systems R&D Notes: svn path=/head/; revision=289834
* arm64: remove exception instruction length assertionEd Maste2015-10-231-14/+0
| | | | | | | | | | | | | | | | | From the (now removed) comment: * It is unclear in some cases if the bit is implementation defined. * The Foundation Model and QEMU disagree on if the IL bit should * be set when we are in a data fault from the same EL and the ISV * bit (bit 24) is also set. Instead of adding even more special cases just remove the assertion. Approved by: andrew Sponsored by: The FreeBSD Foundation Notes: svn path=/head/; revision=289833
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