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* The NetBSD Foundation has granted permission to remove clause 3 and 4 fromJoel Dahl2010-03-031-7/+0
| | | | | | | | | the software. Obtained from: NetBSD Notes: svn path=/head/; revision=204646
* The NetBSD Foundation has granted permission to remove clause 3 and 4 fromJoel Dahl2010-03-032-14/+0
| | | | | | | | | their software. Obtained from: NetBSD Notes: svn path=/head/; revision=204640
* Close a race involving the OEA64 scratchpage. When the scratch page'sNathan Whitehorn2010-02-241-0/+1
| | | | | | | | | | | | | | | | | | physical address is changed, there is a brief window during which its PTE is invalid. Since moea64_set_scratchpage_pa() does not and cannot hold the page table lock, it was possible for another CPU to insert a new PTE into the scratch page's PTEG slot during this interval, corrupting both mappings. Solve this by creating a new flag, LPTE_LOCKED, such that moea64_pte_insert will avoid claiming locked PTEG slots even if they are invalid. This change also incorporates some additional paranoia added to solve things I thought might be this bug. Reported by: linimon Notes: svn path=/head/; revision=204268
* Reduce KVA pressure on OEA64 systems running in bridge mode by mappingNathan Whitehorn2010-02-202-8/+3
| | | | | | | | | | | | | | | | UMA segments at their physical addresses instead of into KVA. This emulates the direct mapping behavior of OEA32 in an ad-hoc way. To make this work properly required sharing the entire kernel PMAP with Open Firmware, so ofw_pmap is transformed into a stub on 64-bit CPUs. Also implement some more tweaks to get more mileage out of our limited amount of KVA, principally by extending KVA into segment 16 until the beginning of the first OFW mapping. Reported by: linimon Notes: svn path=/head/; revision=204128
* Bump limits on PowerPC. This allows large executables like parts of LLVMNathan Whitehorn2009-12-021-5/+5
| | | | | | | | | | | to function. Reviewed by: grehan Obtained from: NetBSD MFC after: 2 weeks Notes: svn path=/head/; revision=200018
* Add a CPU features framework on PowerPC and simplify CPU setup a littleNathan Whitehorn2009-11-282-1/+21
| | | | | | | | | | | | | more. This provides three new sysctls to user space: hw.cpu_features - A bitmask of available CPU features hw.floatingpoint - Whether or not there is hardware FP support hw.altivec - Whether or not Altivec is available PR: powerpc/139154 MFC after: 10 days Notes: svn path=/head/; revision=199886
* Turn on NAP mode on G5 systems, and refactor the HID0 setup code a little.Nathan Whitehorn2009-10-241-0/+7
| | | | | | | | This makes my G5 Xserve sound slightly less like it is filled with howling banshees. Notes: svn path=/head/; revision=198445
* Add SMP support on U3-based G5 systems. This does not yet work perfectly:Nathan Whitehorn2009-10-233-7/+8
| | | | | | | | | | | | | at least on my Xserve, getting the decrementer and timebase on APs to tick requires setting up a clock chip over I2C, which is not yet done. While here, correct the 64-bit tlbie function to set the CPU to 64-bit mode correctly. Hardware donated by: grehan Notes: svn path=/head/; revision=198378
* o Introduce vm_sync_icache() for making the I-cache coherent withMarcel Moolenaar2009-10-211-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | the memory or D-cache, depending on the semantics of the platform. vm_sync_icache() is basically a wrapper around pmap_sync_icache(), that translates the vm_map_t argumument to pmap_t. o Introduce pmap_sync_icache() to all PMAP implementation. For powerpc it replaces the pmap_page_executable() function, added to solve the I-cache problem in uiomove_fromphys(). o In proc_rwmem() call vm_sync_icache() when writing to a page that has execute permissions. This assures that when breakpoints are written, the I-cache will be coherent and the process will actually hit the breakpoint. o This also fixes the Book-E PMAP implementation that was missing necessary locking while trying to deal with the I-cache coherency in pmap_enter() (read: mmu_booke_enter_locked). The key property of this change is that the I-cache is made coherent *after* writes have been done. Doing it in the PMAP layer when adding or changing a mapping means that the I-cache is made coherent *before* any writes happen. The difference is key when the I-cache prefetches. Notes: svn path=/head/; revision=198341
* Define architectural load bases for PIE binaries. Addresses were selectedKonstantin Belousov2009-10-101-0/+2
| | | | | | | | | | | | | by looking at the bases used for non-relocatable executables by gnu ld(1), and adjusting it slightly. Discussed with: bz Reviewed by: kan Tested by: bz (i386, amd64), bsam (linux) MFC after: some time Notes: svn path=/head/; revision=197933
* Add a new sysctl for reporting all of the supported page sizes.Alan Cox2009-09-181-0/+2
| | | | | | | | Reviewed by: jhb MFC after: 3 weeks Notes: svn path=/head/; revision=197316
* Get rid of the _NO_NAMESPACE_POLLUTION kludge by creating anPoul-Henning Kamp2009-09-082-18/+57
| | | | | | | | architecture specific include file containing the _ALIGN* stuff which <sys/socket.h> needs. Notes: svn path=/head/; revision=196994
* * Completely Remove the option STOP_NMI from the kernel. This optionAttilio Rao2009-08-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | has proven to have a good effect when entering KDB by using a NMI, but it completely violates all the good rules about interrupts disabled while holding a spinlock in other occasions. This can be the cause of deadlocks on events where a normal IPI_STOP is expected. * Adds an new IPI called IPI_STOP_HARD on all the supported architectures. This IPI is responsible for sending a stop message among CPUs using a privileged channel when disponible. In other cases it just does match a normal IPI_STOP. Right now the IPI_STOP_HARD functionality uses a NMI on ia32 and amd64 architectures, while on the other has a normal IPI_STOP effect. It is responsibility of maintainers to eventually implement an hard stop when necessary and possible. * Use the new IPI facility in order to implement a new userend SMP kernel function called stop_cpus_hard(). That is specular to stop_cpu() but it does use the privileged channel for the stopping facility. * Let KDB use the newly introduced function stop_cpus_hard() and leave stop_cpus() for all the other cases * Disable interrupts on CPU0 when starting the process of APs suspension. * Style cleanup and comments adding This patch should fix the reboot/shutdown deadlocks many users are constantly reporting on mailing lists. Please don't forget to update your config file with the STOP_NMI option removal Reviewed by: jhb Tested by: pho, bz, rink Approved by: re (kib) Notes: svn path=/head/; revision=196196
* Add support to the virtual memory system for configuring machine-Alan Cox2009-07-122-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dependent memory attributes: Rename vm_cache_mode_t to vm_memattr_t. The new name reflects the fact that there are machine-dependent memory attributes that have nothing to do with controlling the cache's behavior. Introduce vm_object_set_memattr() for setting the default memory attributes that will be given to an object's pages. Introduce and use pmap_page_{get,set}_memattr() for getting and setting a page's machine-dependent memory attributes. Add full support for these functions on amd64 and i386 and stubs for them on the other architectures. The function pmap_page_set_memattr() is also responsible for any other machine-dependent aspects of changing a page's memory attributes, such as flushing the cache or updating the direct map. The uses include kmem_alloc_contig(), vm_page_alloc(), and the device pager: kmem_alloc_contig() can now be used to allocate kernel memory with non-default memory attributes on amd64 and i386. vm_page_alloc() and the device pager will set the memory attributes for the real or fictitious page according to the object's default memory attributes. Update the various pmap functions on amd64 and i386 that map pages to incorporate each page's memory attributes in the mapping. Notes: (1) Inherent to this design are safety features that prevent the specification of inconsistent memory attributes by different mappings on amd64 and i386. In addition, the device pager provides a warning when a device driver creates a fictitious page with memory attributes that are inconsistent with the real page that the fictitious page is an alias for. (2) Storing the machine-dependent memory attributes for amd64 and i386 as a dedicated "int" in "struct md_page" represents a compromise between space efficiency and the ease of MFCing these changes to RELENG_7. In collaboration with: jhb Approved by: re (kib) Notes: svn path=/head/; revision=195649
* Cleanup ALIGNED_POINTER:Sam Leffler2009-07-051-0/+7
| | | | | | | | | | | | | | o add to platforms where it was missing (arm, i386, powerpc, sparc64, sun4v) o define as "1" on amd64 and i386 where there is no restriction o make the type returned consistent with ALIGN o remove _ALIGNED_POINTER o make associated comments consistent Reviewed by: bde, imp, marcel Approved by: re (kensmith) Notes: svn path=/head/; revision=195376
* Correct the #endif comment.Alan Cox2009-06-261-1/+1
| | | | | | | | Noticed by: jmallett Approved by: re (kib) Notes: svn path=/head/; revision=195060
* This change is the next step in implementing the cache control functionalityAlan Cox2009-06-261-0/+40
| | | | | | | | | | | | | | required by video card drivers. Specifically, this change introduces vm_cache_mode_t with an appropriate VM_CACHE_DEFAULT definition on all architectures. In addition, this changes adds a vm_cache_mode_t parameter to kmem_alloc_contig() and vm_phys_alloc_contig(). These will be the interfaces for allocating mapped kernel memory and physical memory, respectively, with non-default cache modes. In collaboration with: jhb Notes: svn path=/head/; revision=195033
* Fix copy/paste typo in last revision. PMC0 control should be shifted 8Nathan Whitehorn2009-06-231-1/+1
| | | | | | | bits, not 6, on the PPC 970. Notes: svn path=/head/; revision=194678
* Teach cpu_est_clockrate() about the G5's slightly different PMC. ThisNathan Whitehorn2009-06-171-1/+24
| | | | | | | | allows the boot messages to include the CPU speed and makes possible the forthcoming cpufreq support for the PPC 970. Notes: svn path=/head/; revision=194374
* Initial version of the sec(4) driver for the integrated security engine foundRafal Jaworowski2009-06-061-0/+1
| | | | | | | | | | | | | | in Freescale system-on-chip devices. The following algorithms and schemes are currently supported: - 3DES, AES, DES - MD5, SHA1, SHA256, SHA384, SHA512 Reviewed by: philip Obtained from: Freescale, Semihalf Notes: svn path=/head/; revision=193579
* Provide 64-bit big endian bus space operations for PowerPC. They are requiredRafal Jaworowski2009-06-061-0/+41
| | | | | | | | | | for the upcoming sec(4) driver. Submitted by: Piotr Ziecik Obtained from: Semihalf Notes: svn path=/head/; revision=193578
* Initial support for SMP on PowerPC MPC85xx.Rafal Jaworowski2009-05-213-0/+7
| | | | | | | | | Tested with Freescale dual-core MPC8572DS development system. Obtained from: Freescale, Semihalf Notes: svn path=/head/; revision=192532
* Improve style(9)Rafal Jaworowski2009-05-141-6/+6
| | | | Notes: svn path=/head/; revision=192110
* PowerPC common SMP startup and time base rework.Rafal Jaworowski2009-05-143-4/+27
| | | | | | | | | | | | | - make mftb() shared, rewrite in C, provide complementary mttb() - adjust SMP startup per the above, additional comments, minor naming changes - eliminate redundant TB defines, other minor cosmetics Reviewed by: marcel, nwhitehorn Obtained from: Freescale, Semihalf Notes: svn path=/head/; revision=192109
* Factor out platform dependent things unrelated to device drivers into aNathan Whitehorn2009-05-147-24/+111
| | | | | | | | | | | | | new platform module. These are probed in early boot, and have the responsibility of determining the layout of physical memory, determining the CPU timebase frequency, and handling the zoo of SMP mechanisms found on PowerPC. Reviewed by: marcel, raj Book-E parts by: raj Notes: svn path=/head/; revision=192067
* Add suppport for ISA and ISA interrupts to make the ATAMarcel Moolenaar2009-04-241-0/+2
| | | | | | | | | | controller in the VIA southbridge functional in the CDS (Configurable Development System) for MPC85XX. The embedded USB controllers look operational but the interrupt steering is still wrong. Notes: svn path=/head/; revision=191450
* Remove PTE_FAKE and PTE_ISFAKE().Marcel Moolenaar2009-04-241-2/+0
| | | | Notes: svn path=/head/; revision=191446
* Centralize setting HID0/1 for E500. Rename HID defines which are specificRafal Jaworowski2009-04-221-4/+11
| | | | | | | | | to E500 rather than shared within Book-E family. Obtained from: Freescale, Semihalf Notes: svn path=/head/; revision=191375
* Lower VM_MAX_KERNEL_ADDRESS to 0xf8000000. We actually haveMarcel Moolenaar2009-04-211-1/+1
| | | | | | | | devices below CCSRBAR_VA, which overlap with KVA if that's out limit. Notes: svn path=/head/; revision=191363
* Don't conditionally define CACHE_LINE_SHIFT, as we anticipate sizingRobert Watson2009-04-201-2/+0
| | | | | | | | | | | | | | | a fair number of static data structures, making this an unlikely option to try to change without also changing source code. [1] Change default cache line size on ia64, sparc64, and sun4v to 128 bytes, as this was what rtld-elf was already using on those platforms. [2] Suggested by: bde [1], jhb [2] MFC after: 2 weeks Notes: svn path=/head/; revision=191309
* Add description and cautionary note regarding CACHE_LINE_SIZE.Robert Watson2009-04-191-0/+4
| | | | | | | | MFC after: 2 weeks Suggested by: alc Notes: svn path=/head/; revision=191278
* For each architecture, define CACHE_LINE_SHIFT and a derivedRobert Watson2009-04-191-0/+5
| | | | | | | | | | | | | | | | CACHE_LINE_SIZE constant. These constants are intended to over-estimate the cache line size, and be used at compile-time when a run-time tuning alternative isn't appropriate or available. Defaults for all architectures are 64 bytes, except powerpc where it is 128 bytes (used on G5 systems). MFC after: 2 weeks Discussed on: arch@ Notes: svn path=/head/; revision=191276
* Fix a typo in the SRR1 comparison for program exceptions. While here,Nathan Whitehorn2009-04-191-0/+11
| | | | | | | | | | | | | | replace magic numbers with constants to keep this from happening again. Without this fix, some programs would occasionally get SIGTRAP instead of SIGILL on an illegal instruction. This affected Altivec detection in pixman, and possibly other software. Reported by: Andreas Tobler MFC after: 1 week Notes: svn path=/head/; revision=191261
* Rework the way we get the cacheline size. Instead of having a table ofNathan Whitehorn2009-04-122-0/+4
| | | | | | | | | CPUs known to use 128 byte cache lines and defaulting to 32, use the dcbz instruction to measure it. Also make dcbz behave the way you would expect on PPC 970. Notes: svn path=/head/; revision=190953
* Add sysarch.h. It's included by drm(4).Marcel Moolenaar2009-04-041-0/+43
| | | | Notes: svn path=/head/; revision=190703
* First round of cleanups. There's a lot of NetBSDism in this header.Marcel Moolenaar2009-04-041-77/+0
| | | | Notes: svn path=/head/; revision=190702
* PowerPC, meet kernel core dumps. The support is basedMarcel Moolenaar2009-04-041-0/+12
| | | | | | | | | | | | | | | | | | | | | on a generic dumper that creates an ELF core file and uses PMAP functions to scan and iterate over memory chunks, as well as handle memory mappings used during dumping. the PMAP layer can choose to return physical memory chunks or virtual memory chunks. For minidumps, the chunks should be virtual. The default MMU I/F implementation for the scan_md() method returns NULL. Thus, when a PMAP implementation does not implement the required methods, an empty core file is created. Here, empty means having an ELF header only. Obtained from: Juniper Networks Notes: svn path=/head/; revision=190684
* Add support for 64-bit PowerPC CPUs operating in the 64-bit bridge modeNathan Whitehorn2009-04-045-27/+68
| | | | | | | | | | | | | provided, for example, on the PowerPC 970 (G5), as well as on related CPUs like the POWER3 and POWER4. This also adds support for various built-in hardware found on Apple G5 hardware (e.g. the IBM CPC925 northbridge). Reviewed by: grehan Notes: svn path=/head/; revision=190681
* Add AT_EXECPATH ELF auxinfo entry type. The value's a_ptr is a pointerKonstantin Belousov2009-03-171-1/+2
| | | | | | | | | | | | | to the full path of the image that is being executed. Increase AT_COUNT. Remove no longer true comment about types used in Linux ELF binaries, listed types contain FreeBSD-specific entries. Reviewed by: kan Notes: svn path=/head/; revision=189926
* Make MPC85xx LAW handling and reset routines aware of the MPC8548 variant.Rafal Jaworowski2009-03-131-0/+2
| | | | | | | Inspired by discussion with Alexey V Fedorov on freebsd-powerpc@. Notes: svn path=/head/; revision=189757
* Make Book-E debug register state part of the PCB context.Rafal Jaworowski2009-02-272-0/+2
| | | | | | | | | | | | | | | | | | | Previously, DBCR0 flags were set "globally", but this leads to problems because Book-E fine grained debug settings work only in conjuction with the debug master enable bit in MSR: in scenarios when the DBCR0 was set with intention to debug one process, but another one with MSR[DE] set got scheduled, the latter would immediately cause debug exceptions to occur upon execution of its own code instructions (and not the one intended for debugging). To avoid such problems and properly handle debugging context, DBCR0 state should be managed individually per process. Submitted by: Grzegorz Bernacki gjb ! semihalf dot com Reviewed by: marcel Notes: svn path=/head/; revision=189100
* Add Altivec support for supported CPUs. This is derived from the FPU supportNathan Whitehorn2009-02-203-0/+46
| | | | | | | | | | | code, and also reducing the size of trapcode to fit inside a 32 byte handler slot. Reviewed by: grehan MFC after: 2 weeks Notes: svn path=/head/; revision=188860
* Rework BookE pmap towards multi-core support.Rafal Jaworowski2009-01-134-22/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | o Eliminate tlb0[] (a s/w copy of TLB0) - The table contents cannot be maintained reliably in multiple MMU environments, where asynchronous events (invalidations from other cores) can change our local TLB0 contents underneath. - Simplify and optimize TLB flushing: system wide invalidations are performed using tlbivax instruction (propagates to other cores), for local MMU invalidations a new optimized routine (assembly) is introduced. o Improve and simplify TID allocation and management. - Let each core keep track of its TID allocations. - Simplify TID recycling, eliminate dead code. - Drop the now unused powerpc/booke/support.S file. o Improve page tables management logic. o Simplify TLB1 manipulation routines. o Other improvements and polishing. Obtained from: Freescale, Semihalf Notes: svn path=/head/; revision=187149
* Modularize the Open Firmware client interface to allow run-time switchingNathan Whitehorn2008-12-201-0/+9
| | | | | | | | | | | | | | | of OFW access semantics, in order to allow future support for real-mode OF access and flattened device frees. OF client interface modules are implemented using KOBJ, in a similar way to the PPC PMAP modules. Because we need Open Firmware to be available before mutexes can be used on sparc64, changes are also included to allow KOBJ to be used very early in the boot process by only using the mutex once we know it has been initialized. Reviewed by: marius, grehan Notes: svn path=/head/; revision=186347
* Improve MPC85XX helper routines.Rafal Jaworowski2008-12-171-9/+9
| | | | | | | | | - Move CCSR accessors to the shared MPC85XX area - Simplify SVR version subfield handling - Adjust OCP Notes: svn path=/head/; revision=186227
* AT_DEBUG and AT_BRK were OBE like 10 years ago, so retire them.Warner Losh2008-12-171-3/+0
| | | | | | | Reviewed by: peter Notes: svn path=/head/; revision=186212
* Adapt parts of the sparc64 Open Firmware bus enumeration code (in particular,Nathan Whitehorn2008-12-151-0/+3
| | | | | | | | | | | | | | | | | | the code for parsing interrupt maps) to PowerPC and reflect their new MI status by moving them to the shared dev/ofw directory. This commit also modifies the OFW PCI enumeration procedure on PowerPC to allow the bus to find non-firmware-enumerated devices that Apple likes to add, and adds some useful Open Firmware properties (compat and name) to the pnpinfo string of children on OFW SBus, EBus, PCI, and MacIO links. Because of the change to PCI enumeration on PowerPC, X has started working again on PPC machines with Grackle hostbridges. Reviewed by: marius Obtained from: sparc64 Notes: svn path=/head/; revision=186128
* Unbreak previous commit.Marcel Moolenaar2008-11-221-2/+0
| | | | Notes: svn path=/head/; revision=185189
* - bump __FreeBSD version to reflect added buf_ring, memory barriers,Kip Macy2008-11-221-0/+4
| | | | | | | | | | | | | | | | | | | | and ifnet functions - add memory barriers to <machine/atomic.h> - update drivers to only conditionally define their own - add lockless producer / consumer ring buffer - remove ring buffer implementation from cxgb and update its callers - add if_transmit(struct ifnet *ifp, struct mbuf *m) to ifnet to allow drivers to efficiently manage multiple hardware queues (i.e. not serialize all packets through one ifq) - expose if_qflush to allow drivers to flush any driver managed queues This work was supported by Bitgravity Inc. and Chelsio Inc. Notes: svn path=/head/; revision=185162
* Define LDBL_EPSILON, LDBL_MAX and LDBL_MIN as long double constants.Marcel Moolenaar2008-11-161-3/+3
| | | | | | | | Submitted by: Andreas Tobler <andreast-list@fgznet.ch> Reviewed by: das@ Notes: svn path=/head/; revision=185005
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