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* Fix disassembly of the invala, itc, itr and hint instructionsMarcel Moolenaar2007-10-161-1/+1
| | | | | | | | | by fixing the opcode ordering. MFC after: 1 week Notes: svn path=/head/; revision=172689
* Update to SDM 2.2:Marcel Moolenaar2006-06-245-24/+124
| | | | | | | | | | | | o Add tf (test feature) instruction, o Add vmsw (VM switch) instruction. While here, update copyright. MFC after: 1 week Notes: svn path=/head/; revision=159916
* Sync up with SDM 2.1:Marcel Moolenaar2006-06-245-20/+77
| | | | | | | | | | o Add nop/hint formats F16, I18, M48 and X5, o Add format M47 for ptc.e, o Add hint instruction, o Fix decoding of cmp8xchg16. Notes: svn path=/head/; revision=159909
* /* -> /*- for copyright notices, minor format tweaks as necessaryWarner Losh2005-01-065-5/+5
| | | | Notes: svn path=/head/; revision=139790
* ITC.{i,d} instructions use format M41 not M42.Arun Sharma2004-08-161-2/+2
| | | | | | | reviewed by: marcel@ Notes: svn path=/head/; revision=133875
* Remove two unused fields in the operand structure (o_read & o_write).Marcel Moolenaar2003-10-241-2/+0
| | | | Notes: svn path=/head/; revision=121448
* Add a new disassembler that improves over the previous disassemblerMarcel Moolenaar2003-10-235-0/+5915
in that it provides an abstract (intermediate) representation for instructions. This significantly improves working with instructions such as emulation of instructions that are not implemented by the hardware (e.g. long branch) or enhancing implemented instructions (e.g. handling of misaligned memory accesses). Not to mention that it's much easier to print instructions. Functions are included that provide a textual representation for opcodes, completers and operands. The disassembler supports all ia64 instructions defined by revision 2.1 of the SDM (Oct 2002). Notes: svn path=/head/; revision=121404