| Commit message (Collapse) | Author | Age | Files | Lines |
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by fixing the opcode ordering.
MFC after: 1 week
Notes:
svn path=/head/; revision=172689
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o Add tf (test feature) instruction,
o Add vmsw (VM switch) instruction.
While here, update copyright.
MFC after: 1 week
Notes:
svn path=/head/; revision=159916
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o Add nop/hint formats F16, I18, M48 and X5,
o Add format M47 for ptc.e,
o Add hint instruction,
o Fix decoding of cmp8xchg16.
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svn path=/head/; revision=159909
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svn path=/head/; revision=139790
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reviewed by: marcel@
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svn path=/head/; revision=133875
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Notes:
svn path=/head/; revision=121448
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in that it provides an abstract (intermediate) representation for
instructions. This significantly improves working with instructions
such as emulation of instructions that are not implemented by the
hardware (e.g. long branch) or enhancing implemented instructions
(e.g. handling of misaligned memory accesses). Not to mention that
it's much easier to print instructions.
Functions are included that provide a textual representation for
opcodes, completers and operands.
The disassembler supports all ia64 instructions defined by revision
2.1 of the SDM (Oct 2002).
Notes:
svn path=/head/; revision=121404
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