src - FreeBSD source tree

	Commit message (Collapse)	Author	Age	Files	Lines
*	msun/riscv: expose fe{disable,enable}except	Brooks Davis	2024-05-20	1	-4/+3
\| \| \| \| \| \| \| \| \| \| \|	This is required for GCC to build. PR: 272759 Reported by: dgilbert@eicat.ca Submitted by: jrtc27 Differential Revision: https://reviews.freebsd.org/D44333 (cherry picked from commit 1947a9383ec3a048e334022365aa199a6ae55289)
*	Remove $FreeBSD$: two-line .h pattern	Warner Losh	2023-08-23	1	-2/+0
\| \| \| \| \| \| \|	Remove /^\s\\n \*\s+\$FreeBSD\$$\n/ Similar commit in main: (cherry picked from commit b3e7694832e8)
*	RISC-V: Fix feenableexcept return value	Alex Richardson	2021-04-10	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \|	The man page says "The feenableexcept(), fedisableexcept(), and fegetexcept() functions return a bitmap of the exceptions that were unmasked prior to the call.", so we should return zero not -1. Reviewed By: mhorne MFC after: 3 days Differential Revision: https://reviews.freebsd.org/D29386 (cherry picked from commit dd5ed53a2f93a5a54efe96bed6bbd0f18b6bdbe2)
*	Silence unused parameter warnings in the RISC-V fenv.h	Alex Richardson	2021-04-10	1	-3/+3
\| \| \| \| \| \| \| \| \| \|	After increasing the lib/msun/tests WARNS to 6, this triggers a compilation error for RISC-V. Fixes: 87d65c747a43 ("lib/msun: Allow building tests with WARNS=6") Reported by: Jenkins (cherry picked from commit 15211f19509282d9c9a418d4e5b6ac75d9d1fc85)
*	Replace SOFTFLOAT with __riscv_float_abi_*.	Brooks Davis	2018-04-19	1	-5/+13
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	With SOFTFLOAT, libc and libm were built correctly, but any program including fenv.h itself assumed it was on a hardfloat systen and emitted inline fpu instructions for fedisableexcept() and friends. Unlike r315424 which did this for MIPS, I've used riscv_float_abi_soft and riscv_float_abi_double macros as appropriate rather than using __riscv_float_abi_soft exclusively. This ensures that attempts to use an unsupported hardfloat ABI will fail. Reviewed by: br Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D10039 Notes: svn path=/head/; revision=332792
*	Add full softfloat and hardfloat support for RISC-V.	Ruslan Bukin	2016-11-16	1	-55/+79
\| \| \| \| \| \| \| \| \| \| \|	Hardfloat is now default (use riscv64sf as TARGET_ARCH for softfloat). Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D8529 Notes: svn path=/head/; revision=308731
*	Start support for the RISC-V 64-bit architecture developed by UC Berkeley.	Ruslan Bukin	2015-12-11	1	-0/+228
	RISC-V is a new ISA designed to support computer research and education, and is now become a standard open architecture for industry implementations. This is a minimal set of changes required to run 'make kernel-toolchain' using external (GNU) toolchain. The FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv. Reviewed by: andrew, bdrewery, emaste, imp Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4445 Notes: svn path=/head/; revision=292124