diff options
Diffstat (limited to 'test')
260 files changed, 5867 insertions, 1210 deletions
diff --git a/test/Analysis/BasicAA/cas.ll b/test/Analysis/BasicAA/cas.ll index 4ce7811634e2..8dd3695d6d57 100644 --- a/test/Analysis/BasicAA/cas.ll +++ b/test/Analysis/BasicAA/cas.ll @@ -12,4 +12,4 @@ define i32 @main() { ret i32 %d } -declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind
\ No newline at end of file +declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind diff --git a/test/Analysis/BasicAA/empty.ll b/test/Analysis/BasicAA/empty.ll new file mode 100644 index 000000000000..689efec26adb --- /dev/null +++ b/test/Analysis/BasicAA/empty.ll @@ -0,0 +1,10 @@ +; RUN: opt < %s -aa-eval -print-all-alias-modref-info -disable-output \ +; RUN: |& grep {NoAlias: \{\}\\* \[%\]p, \{\}\\* \[%\]q} + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" + +define void @foo({}* %p, {}* %q) { + store {} {}, {}* %p + store {} {}, {}* %q + ret void +} diff --git a/test/Analysis/CallGraph/2008-09-09-DirectCall.ll b/test/Analysis/CallGraph/2008-09-09-DirectCall.ll index 6e34209a0e36..784d6c7ba1b1 100644 --- a/test/Analysis/CallGraph/2008-09-09-DirectCall.ll +++ b/test/Analysis/CallGraph/2008-09-09-DirectCall.ll @@ -1,5 +1,5 @@ ; RUN: opt < %s -print-callgraph -disable-output |& \ -; RUN: grep {Calls function 'callee'} | count 2 +; RUN: grep {calls function 'callee'} | count 2 define internal void @callee(...) { entry: diff --git a/test/Analysis/CallGraph/2008-09-09-UsedByGlobal.ll b/test/Analysis/CallGraph/2008-09-09-UsedByGlobal.ll index 12849b7aa96c..0c5ef92ef71e 100644 --- a/test/Analysis/CallGraph/2008-09-09-UsedByGlobal.ll +++ b/test/Analysis/CallGraph/2008-09-09-UsedByGlobal.ll @@ -1,5 +1,4 @@ -; RUN: opt < %s -print-callgraph -disable-output |& \ -; RUN: grep {Calls function} +; RUN: opt < %s -print-callgraph -disable-output |& grep {calls function} @a = global void ()* @f ; <void ()**> [#uses=0] diff --git a/test/Analysis/ScalarEvolution/2008-11-18-LessThanOrEqual.ll b/test/Analysis/ScalarEvolution/2008-11-18-LessThanOrEqual.ll index 06637b5eaee7..335bbaf9ad09 100644 --- a/test/Analysis/ScalarEvolution/2008-11-18-LessThanOrEqual.ll +++ b/test/Analysis/ScalarEvolution/2008-11-18-LessThanOrEqual.ll @@ -1,6 +1,5 @@ ; RUN: opt < %s -analyze -scalar-evolution |& \ ; RUN: grep {Loop %bb: backedge-taken count is (7 + (-1 \\* %argc))} -; XFAIL: * define i32 @main(i32 %argc, i8** %argv) nounwind { entry: diff --git a/test/Analysis/ScalarEvolution/2008-11-18-Stride2.ll b/test/Analysis/ScalarEvolution/2008-11-18-Stride2.ll index 102acc65650f..fa9f21af3713 100644 --- a/test/Analysis/ScalarEvolution/2008-11-18-Stride2.ll +++ b/test/Analysis/ScalarEvolution/2008-11-18-Stride2.ll @@ -1,6 +1,9 @@ ; RUN: opt < %s -analyze -scalar-evolution |& grep {/u 3} ; XFAIL: * +; This is a tricky testcase for unsigned wrap detection which ScalarEvolution +; doesn't yet know how to do. + define i32 @f(i32 %x) nounwind readnone { entry: %0 = icmp ugt i32 %x, 999 ; <i1> [#uses=1] diff --git a/test/Analysis/ScalarEvolution/2008-12-08-FiniteSGE.ll b/test/Analysis/ScalarEvolution/2008-12-08-FiniteSGE.ll index 226221b297f9..25a0434b29e2 100644 --- a/test/Analysis/ScalarEvolution/2008-12-08-FiniteSGE.ll +++ b/test/Analysis/ScalarEvolution/2008-12-08-FiniteSGE.ll @@ -1,5 +1,4 @@ ; RUN: opt < %s -analyze -scalar-evolution | grep {backedge-taken count is 255} -; XFAIL: * define i32 @foo(i32 %x, i32 %y, i32* %lam, i32* %alp) nounwind { bb1.thread: diff --git a/test/Analysis/ScalarEvolution/2008-12-11-SMaxOverflow.ll b/test/Analysis/ScalarEvolution/2008-12-11-SMaxOverflow.ll index 33a74795d2ea..12254e37dcc7 100644 --- a/test/Analysis/ScalarEvolution/2008-12-11-SMaxOverflow.ll +++ b/test/Analysis/ScalarEvolution/2008-12-11-SMaxOverflow.ll @@ -1,5 +1,7 @@ -; RUN: opt < %s -analyze -scalar-evolution | grep {0 smax} -; XFAIL: * +; RUN: opt < %s -analyze -scalar-evolution | FileCheck %s + +; CHECK: @f +; CHECK: Loop %bb16.preheader: backedge-taken count is (-1 + %c.idx.val) define i32 @f(i32 %c.idx.val) { diff --git a/test/Analysis/ScalarEvolution/sle.ll b/test/Analysis/ScalarEvolution/sle.ll new file mode 100644 index 000000000000..f38f6b63dce4 --- /dev/null +++ b/test/Analysis/ScalarEvolution/sle.ll @@ -0,0 +1,27 @@ +; RUN: opt -analyze -scalar-evolution < %s | FileCheck %s + +; ScalarEvolution should be able to use nsw information to prove that +; this loop has a finite trip count. + +; CHECK: @le +; CHECK: Loop %for.body: backedge-taken count is %n +; CHECK: Loop %for.body: max backedge-taken count is 9223372036854775807 + +define void @le(i64 %n, double* nocapture %p) nounwind { +entry: + %cmp6 = icmp slt i64 %n, 0 ; <i1> [#uses=1] + br i1 %cmp6, label %for.end, label %for.body + +for.body: ; preds = %for.body, %entry + %i = phi i64 [ %i.next, %for.body ], [ 0, %entry ] ; <i64> [#uses=2] + %arrayidx = getelementptr double* %p, i64 %i ; <double*> [#uses=2] + %t4 = load double* %arrayidx ; <double> [#uses=1] + %mul = fmul double %t4, 2.200000e+00 ; <double> [#uses=1] + store double %mul, double* %arrayidx + %i.next = add nsw i64 %i, 1 ; <i64> [#uses=2] + %cmp = icmp sgt i64 %i.next, %n ; <i1> [#uses=1] + br i1 %cmp, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + ret void +} diff --git a/test/Analysis/ScalarEvolution/undefined.ll b/test/Analysis/ScalarEvolution/undefined.ll new file mode 100644 index 000000000000..b1f44460af6b --- /dev/null +++ b/test/Analysis/ScalarEvolution/undefined.ll @@ -0,0 +1,39 @@ +; RUN: opt -analyze -scalar-evolution < %s | FileCheck %s + +; ScalarEvolution shouldn't attempt to interpret expressions which have +; undefined results. + +define void @foo(i64 %x) { + + %a = udiv i64 %x, 0 +; CHECK: --> (%x /u 0) + + %B = shl i64 %x, 64 +; CHECK: --> %B + + %b = ashr i64 %B, 64 +; CHECK: --> %b + + %c = lshr i64 %x, 64 +; CHECK: --> %c + + %d = shl i64 %x, 64 +; CHECK: --> %d + + %E = shl i64 %x, -1 +; CHECK: --> %E + + %e = ashr i64 %E, -1 +; CHECK: --> %e + + %f = lshr i64 %x, -1 +; CHECK: --> %f + + %g = shl i64 %x, -1 +; CHECK: --> %g + + %h = bitcast i64 undef to i64 +; CHECK: --> undef + + ret void +} diff --git a/test/Analysis/ScalarEvolution/unsimplified-loop.ll b/test/Analysis/ScalarEvolution/unsimplified-loop.ll new file mode 100644 index 000000000000..a3175077b686 --- /dev/null +++ b/test/Analysis/ScalarEvolution/unsimplified-loop.ll @@ -0,0 +1,29 @@ +; RUN: opt -analyze -scalar-evolution < %s | FileCheck %s + +; This loop has no preheader, multiple backedges, etc., but ScalarEvolution +; should still be able to analyze it. + +; CHECK: %i = phi i64 [ 5, %entry ], [ 5, %alt ], [ %i.next, %loop.a ], [ %i.next, %loop.b ] +; CHECK-NEXT: --> {5,+,1}<%loop> + +define void @foo(i1 %p, i1 %q, i1 %s, i1 %u) { +entry: + br i1 %p, label %loop, label %alt + +alt: + br i1 %s, label %loop, label %exit + +loop: + %i = phi i64 [ 5, %entry ], [ 5, %alt ], [ %i.next, %loop.a ], [ %i.next, %loop.b ] + %i.next = add i64 %i, 1 + br i1 %q, label %loop.a, label %loop.b + +loop.a: + br label %loop + +loop.b: + br i1 %u, label %loop, label %exit + +exit: + ret void +} diff --git a/test/Assembler/metadata.ll b/test/Assembler/metadata.ll index a52de87650b7..50f27b4eb45f 100644 --- a/test/Assembler/metadata.ll +++ b/test/Assembler/metadata.ll @@ -19,4 +19,4 @@ declare void @llvm.dbg.func.start(metadata) nounwind readnone !foo = !{ !0 } !bar = !{ !1 } -; !foo = !{ !0, !"foo" }
\ No newline at end of file +; !foo = !{ !0, !"foo" } diff --git a/test/Bitcode/memcpy.ll b/test/Bitcode/memcpy.ll index b6573b5f6216..299eb1ed41e3 100644 --- a/test/Bitcode/memcpy.ll +++ b/test/Bitcode/memcpy.ll @@ -20,4 +20,4 @@ declare void @llvm.memset.i32(i8*, i8, i32, i32) declare void @llvm.memmove.i32(i8*, i8*, i32, i32) -declare void @llvm.memmove.i64(i8*, i8*, i32, i32) +declare void @llvm.memmove.i64(i8*, i8*, i64, i32) diff --git a/test/Bitcode/sse41_pmulld.ll b/test/Bitcode/sse41_pmulld.ll index caf85479bbc2..6872cc0b712d 100644 --- a/test/Bitcode/sse41_pmulld.ll +++ b/test/Bitcode/sse41_pmulld.ll @@ -1,2 +1,2 @@ ; RUN: llvm-dis < %s.bc | not grep {i32 @llvm\\.pmulld} -; RUN: llvm-dis < %s.bc | grep mul
\ No newline at end of file +; RUN: llvm-dis < %s.bc | grep mul diff --git a/test/Bitcode/ssse3_palignr.ll b/test/Bitcode/ssse3_palignr.ll new file mode 100644 index 000000000000..d596dd5eb363 --- /dev/null +++ b/test/Bitcode/ssse3_palignr.ll @@ -0,0 +1 @@ +; RUN: llvm-dis < %s.bc | not grep {@llvm\\.palign} diff --git a/test/Bitcode/ssse3_palignr.ll.bc b/test/Bitcode/ssse3_palignr.ll.bc Binary files differnew file mode 100644 index 000000000000..642f4dedc417 --- /dev/null +++ b/test/Bitcode/ssse3_palignr.ll.bc diff --git a/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll b/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll index f2a8ee1a1424..52937c1dd9fc 100644 --- a/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll +++ b/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll @@ -1,7 +1,5 @@ ; RUN: llc < %s -march=arm -enable-tail-merge | grep bl.*baz | count 1 ; RUN: llc < %s -march=arm -enable-tail-merge | grep bl.*quux | count 1 -; RUN: llc < %s -march=arm -enable-tail-merge -enable-eh | grep bl.*baz | count 1 -; RUN: llc < %s -march=arm -enable-tail-merge -enable-eh | grep bl.*quux | count 1 ; Check that calls to baz and quux are tail-merged. ; PR1628 diff --git a/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll b/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll index 275850581154..c925fa83ef36 100644 --- a/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll +++ b/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll @@ -1,7 +1,5 @@ ; RUN: llc < %s -march=arm -enable-tail-merge | grep bl.*baz | count 1 ; RUN: llc < %s -march=arm -enable-tail-merge | grep bl.*quux | count 1 -; RUN: llc < %s -march=arm -enable-tail-merge -enable-eh | grep bl.*baz | count 1 -; RUN: llc < %s -march=arm -enable-tail-merge -enable-eh | grep bl.*quux | count 1 ; Check that calls to baz and quux are tail-merged. ; PR1628 diff --git a/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll b/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll index 061bf5e851b0..9df5af59a79f 100644 --- a/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll +++ b/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll @@ -2,10 +2,6 @@ ; RUN: llc < %s -march=arm | grep bl.*quux | count 1 ; RUN: llc < %s -march=arm -enable-tail-merge=0 | grep bl.*baz | count 2 ; RUN: llc < %s -march=arm -enable-tail-merge=0 | grep bl.*quux | count 2 -; RUN: llc < %s -march=arm -enable-eh | grep bl.*baz | count 1 -; RUN: llc < %s -march=arm -enable-eh | grep bl.*quux | count 1 -; RUN: llc < %s -march=arm -enable-tail-merge=0 -enable-eh | grep bl.*baz | count 2 -; RUN: llc < %s -march=arm -enable-tail-merge=0 -enable-eh | grep bl.*quux | count 2 ; Check that tail merging is the default on ARM, and that -enable-tail-merge=0 works. ; PR1628 diff --git a/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll b/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll index b6cf880a3001..c0ad65f81b6b 100644 --- a/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll +++ b/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll @@ -86,7 +86,7 @@ bb: ; preds = %entry return: ; preds = %bb ret void } -;CHECK: L_LSDA_1: +;CHECK: L_LSDA_0: declare arm_apcscc void @_ZdlPv(i8*) nounwind diff --git a/test/CodeGen/ARM/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/ARM/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 000000000000..8a24cfa39785 --- /dev/null +++ b/test/CodeGen/ARM/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=arm -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/ARM/2010-04-09-NeonSelect.ll b/test/CodeGen/ARM/2010-04-09-NeonSelect.ll new file mode 100644 index 000000000000..71e0b0a36ce7 --- /dev/null +++ b/test/CodeGen/ARM/2010-04-09-NeonSelect.ll @@ -0,0 +1,23 @@ +; RUN: llc -march=arm -mattr=+neon < %s +; Radar 7770501: Don't crash on SELECT and SELECT_CC with NEON vector values. + +define arm_apcscc void @vDSP_FFT16_copv(float* nocapture %O, float* nocapture %I, i32 %Direction) nounwind { +entry: + %.22 = select i1 undef, <4 x float> undef, <4 x float> zeroinitializer ; <<4 x float>> [#uses=1] + %0 = fadd <4 x float> undef, %.22 ; <<4 x float>> [#uses=1] + %1 = fsub <4 x float> %0, undef ; <<4 x float>> [#uses=1] + %2 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> <i32 2, i32 6, i32 3, i32 7> ; <<4 x float>> [#uses=1] + %3 = shufflevector <4 x float> undef, <4 x float> %2, <4 x i32> <i32 2, i32 3, i32 6, i32 7> ; <<4 x float>> [#uses=1] + %4 = fmul <4 x float> %3, <float 0.000000e+00, float 0x3FED906BC0000000, float 0x3FE6A09E60000000, float 0xBFD87DE2A0000000> ; <<4 x float>> [#uses=1] + %5 = fadd <4 x float> undef, %4 ; <<4 x float>> [#uses=1] + %6 = fadd <4 x float> undef, %5 ; <<4 x float>> [#uses=1] + %7 = fadd <4 x float> undef, %6 ; <<4 x float>> [#uses=1] + br i1 undef, label %bb4, label %bb3 + +bb3: ; preds = %entry + %8 = shufflevector <4 x float> undef, <4 x float> %7, <4 x i32> <i32 2, i32 6, i32 3, i32 7> ; <<4 x float>> [#uses=0] + ret void + +bb4: ; preds = %entry + ret void +} diff --git a/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll b/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll new file mode 100644 index 000000000000..4f71b83b9495 --- /dev/null +++ b/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll @@ -0,0 +1,7 @@ +; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 +; Radar 7855014 + +define arm_apcscc void @test1(i32 %f0, i32 %f1, i32 %f2, <4 x i32> %f3) nounwind { +entry: + unreachable +} diff --git a/test/CodeGen/ARM/2010-04-14-SplitVector.ll b/test/CodeGen/ARM/2010-04-14-SplitVector.ll new file mode 100644 index 000000000000..42f98521e30c --- /dev/null +++ b/test/CodeGen/ARM/2010-04-14-SplitVector.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -march=arm -mcpu=arm1136jf-s +; Radar 7854640 + +define arm_apcscc void @test() nounwind { +bb: + br i1 undef, label %bb9, label %bb10 + +bb9: + %tmp63 = bitcast <4 x float> zeroinitializer to i128 + %tmp64 = trunc i128 %tmp63 to i32 + br label %bb10 + +bb10: + %0 = phi i32 [ %tmp64, %bb9 ], [ undef, %bb ] + ret void +} diff --git a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll new file mode 100644 index 000000000000..ed7bca8510d3 --- /dev/null +++ b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s +; PR6847 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32" +target triple = "armv4t-apple-darwin10" + +define hidden arm_apcscc i32 @__addvsi3(i32 %a, i32 %b) nounwind { +entry: + tail call void @llvm.dbg.value(metadata !{i32 %b}, i64 0, metadata !0) + %0 = add nsw i32 %b, %a, !dbg !9 ; <i32> [#uses=1] + ret i32 %0, !dbg !11 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!0 = metadata !{i32 524545, metadata !1, metadata !"b", metadata !2, i32 93, metadata !6} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"__addvsi3", metadata !"__addvsi3", metadata !"__addvsi3", metadata !2, i32 94, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 524329, metadata !"libgcc2.c", metadata !"/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"libgcc2.c", metadata !"/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 00)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{metadata !6, metadata !6, metadata !6} +!6 = metadata !{i32 524310, metadata !2, metadata !"SItype", metadata !7, i32 152, i64 0, i64 0, i64 0, i32 0, metadata !8} ; [ DW_TAG_typedef ] +!7 = metadata !{i32 524329, metadata !"libgcc2.h", metadata !"/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc", metadata !3} ; [ DW_TAG_file_type ] +!8 = metadata !{i32 524324, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!9 = metadata !{i32 95, i32 0, metadata !10, null} +!10 = metadata !{i32 524299, metadata !1, i32 94, i32 0} ; [ DW_TAG_lexical_block ] +!11 = metadata !{i32 100, i32 0, metadata !10, null} diff --git a/test/CodeGen/ARM/arguments7.ll b/test/CodeGen/ARM/arguments7.ll index 038e417b333a..fa97ee821b39 100644 --- a/test/CodeGen/ARM/arguments7.ll +++ b/test/CodeGen/ARM/arguments7.ll @@ -6,4 +6,4 @@ define double @f(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, double %b) { ret double %tmp } -declare double @g(double) +declare double @g(i32, i32, i32, i32, double) diff --git a/test/CodeGen/ARM/arguments8.ll b/test/CodeGen/ARM/arguments8.ll index 6999a4d4f656..abe059bf234e 100644 --- a/test/CodeGen/ARM/arguments8.ll +++ b/test/CodeGen/ARM/arguments8.ll @@ -6,4 +6,4 @@ define i64 @f(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i64 %b) { ret i64 %tmp } -declare i64 @g(i64) +declare i64 @g(i32, i32, i32, i32, i64) diff --git a/test/CodeGen/ARM/bfx.ll b/test/CodeGen/ARM/bfx.ll new file mode 100644 index 000000000000..fcca191a016e --- /dev/null +++ b/test/CodeGen/ARM/bfx.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -march=arm -mattr=+v7a | FileCheck %s + +define i32 @sbfx1(i32 %a) { +; CHECK: sbfx1 +; CHECK: sbfx r0, r0, #7, #11 + %t1 = lshr i32 %a, 7 + %t2 = trunc i32 %t1 to i11 + %t3 = sext i11 %t2 to i32 + ret i32 %t3 +} + +define i32 @ubfx1(i32 %a) { +; CHECK: ubfx1 +; CHECK: ubfx r0, r0, #7, #11 + %t1 = lshr i32 %a, 7 + %t2 = trunc i32 %t1 to i11 + %t3 = zext i11 %t2 to i32 + ret i32 %t3 +} + +define i32 @ubfx2(i32 %a) { +; CHECK: ubfx2 +; CHECK: ubfx r0, r0, #7, #11 + %t1 = lshr i32 %a, 7 + %t2 = and i32 %t1, 2047 + ret i32 %t2 +} + diff --git a/test/CodeGen/ARM/globals.ll b/test/CodeGen/ARM/globals.ll index adb449739743..ccb14280df9b 100644 --- a/test/CodeGen/ARM/globals.ll +++ b/test/CodeGen/ARM/globals.ll @@ -11,23 +11,23 @@ define i32 @test1() { } ; DarwinStatic: _test1: -; DarwinStatic: ldr r0, LCPI1_0 +; DarwinStatic: ldr r0, LCPI0_0 ; DarwinStatic: ldr r0, [r0] ; DarwinStatic: bx lr ; DarwinStatic: .align 2 -; DarwinStatic: LCPI1_0: +; DarwinStatic: LCPI0_0: ; DarwinStatic: .long {{_G$}} ; DarwinDynamic: _test1: -; DarwinDynamic: ldr r0, LCPI1_0 +; DarwinDynamic: ldr r0, LCPI0_0 ; DarwinDynamic: ldr r0, [r0] ; DarwinDynamic: ldr r0, [r0] ; DarwinDynamic: bx lr ; DarwinDynamic: .align 2 -; DarwinDynamic: LCPI1_0: +; DarwinDynamic: LCPI0_0: ; DarwinDynamic: .long L_G$non_lazy_ptr ; DarwinDynamic: .section __DATA,__nl_symbol_ptr,non_lazy_symbol_pointers @@ -39,15 +39,15 @@ define i32 @test1() { ; DarwinPIC: _test1: -; DarwinPIC: ldr r0, LCPI1_0 -; DarwinPIC: LPC1_0: +; DarwinPIC: ldr r0, LCPI0_0 +; DarwinPIC: LPC0_0: ; DarwinPIC: ldr r0, [pc, r0] ; DarwinPIC: ldr r0, [r0] ; DarwinPIC: bx lr ; DarwinPIC: .align 2 -; DarwinPIC: LCPI1_0: -; DarwinPIC: .long L_G$non_lazy_ptr-(LPC1_0+8) +; DarwinPIC: LCPI0_0: +; DarwinPIC: .long L_G$non_lazy_ptr-(LPC0_0+8) ; DarwinPIC: .section __DATA,__nl_symbol_ptr,non_lazy_symbol_pointers ; DarwinPIC: .align 2 @@ -58,18 +58,18 @@ define i32 @test1() { ; LinuxPIC: test1: -; LinuxPIC: ldr r0, .LCPI1_0 -; LinuxPIC: ldr r1, .LCPI1_1 +; LinuxPIC: ldr r0, .LCPI0_0 +; LinuxPIC: ldr r1, .LCPI0_1 -; LinuxPIC: .LPC1_0: +; LinuxPIC: .LPC0_0: ; LinuxPIC: add r0, pc, r0 ; LinuxPIC: ldr r0, [r1, r0] ; LinuxPIC: ldr r0, [r0] ; LinuxPIC: bx lr ; LinuxPIC: .align 2 -; LinuxPIC: .LCPI1_0: -; LinuxPIC: .long _GLOBAL_OFFSET_TABLE_-(.LPC1_0+8) +; LinuxPIC: .LCPI0_0: +; LinuxPIC: .long _GLOBAL_OFFSET_TABLE_-(.LPC0_0+8) ; LinuxPIC: .align 2 -; LinuxPIC: .LCPI1_1: +; LinuxPIC: .LCPI0_1: ; LinuxPIC: .long G(GOT) diff --git a/test/CodeGen/ARM/hidden-vis-3.ll b/test/CodeGen/ARM/hidden-vis-3.ll index 3bd710ae949f..fc8b2febc320 100644 --- a/test/CodeGen/ARM/hidden-vis-3.ll +++ b/test/CodeGen/ARM/hidden-vis-3.ll @@ -5,9 +5,9 @@ define i32 @t() nounwind readonly { entry: -; CHECK: LCPI1_0: +; CHECK: LCPI0_0: ; CHECK-NEXT: .long _x -; CHECK: LCPI1_1: +; CHECK: LCPI0_1: ; CHECK-NEXT: .long _y %0 = load i32* @x, align 4 ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/ifcvt2.ll b/test/CodeGen/ARM/ifcvt2.ll index ce57d736c167..d9cac8022b24 100644 --- a/test/CodeGen/ARM/ifcvt2.ll +++ b/test/CodeGen/ARM/ifcvt2.ll @@ -1,7 +1,8 @@ -; RUN: llc < %s -march=arm -; RUN: llc < %s -march=arm | grep bxlt | count 1 -; RUN: llc < %s -march=arm | grep bxgt | count 1 -; RUN: llc < %s -march=arm | grep bxge | count 1 +; RUN: llc < %s -march=arm > %t +; RUN: grep bxlt %t | count 1 +; RUN: grep bxgt %t | count 1 +; RUN: not grep bxge %t +; RUN: not grep bxle %t define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { %tmp2 = icmp sgt i32 %c, 10 diff --git a/test/CodeGen/ARM/ifcvt5.ll b/test/CodeGen/ARM/ifcvt5.ll index 8677ce535971..bca2ae346a6f 100644 --- a/test/CodeGen/ARM/ifcvt5.ll +++ b/test/CodeGen/ARM/ifcvt5.ll @@ -9,7 +9,7 @@ entry: ret void } -define void @t1(i32 %a, i32 %b) { +define i32 @t1(i32 %a, i32 %b) { ; CHECK: t1: ; CHECK: ldmialt sp!, {r7, pc} entry: @@ -18,8 +18,8 @@ entry: cond_true: ; preds = %entry tail call void @foo( i32 %b ) - ret void + ret i32 0 UnifiedReturnBlock: ; preds = %entry - ret void + ret i32 1 } diff --git a/test/CodeGen/ARM/sbfx.ll b/test/CodeGen/ARM/sbfx.ll index 6f1d87d2c17b..d29693e4cf92 100644 --- a/test/CodeGen/ARM/sbfx.ll +++ b/test/CodeGen/ARM/sbfx.ll @@ -12,7 +12,7 @@ entry: define i32 @f2(i32 %a) { entry: ; CHECK: f2: -; CHECK: ubfx r0, r0, #0, #20 +; CHECK: bfc r0, #20, #12 %tmp = shl i32 %a, 12 %tmp2 = lshr i32 %tmp, 12 ret i32 %tmp2 diff --git a/test/CodeGen/ARM/vadd.ll b/test/CodeGen/ARM/vadd.ll index 9fa530750aa1..9bb8bf561045 100644 --- a/test/CodeGen/ARM/vadd.ll +++ b/test/CodeGen/ARM/vadd.ll @@ -41,7 +41,7 @@ define <2 x float> @vaddf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK: vadd.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B - %tmp3 = add <2 x float> %tmp1, %tmp2 + %tmp3 = fadd <2 x float> %tmp1, %tmp2 ret <2 x float> %tmp3 } @@ -86,7 +86,7 @@ define <4 x float> @vaddQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK: vadd.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B - %tmp3 = add <4 x float> %tmp1, %tmp2 + %tmp3 = fadd <4 x float> %tmp1, %tmp2 ret <4 x float> %tmp3 } diff --git a/test/CodeGen/ARM/vld1.ll b/test/CodeGen/ARM/vld1.ll index f5383aafb2bb..c61ea8c9a789 100644 --- a/test/CodeGen/ARM/vld1.ll +++ b/test/CodeGen/ARM/vld1.ll @@ -10,28 +10,32 @@ define <8 x i8> @vld1i8(i8* %A) nounwind { define <4 x i16> @vld1i16(i16* %A) nounwind { ;CHECK: vld1i16: ;CHECK: vld1.16 - %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i16* %A) + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0) ret <4 x i16> %tmp1 } define <2 x i32> @vld1i32(i32* %A) nounwind { ;CHECK: vld1i32: ;CHECK: vld1.32 - %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i32* %A) + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0) ret <2 x i32> %tmp1 } define <2 x float> @vld1f(float* %A) nounwind { ;CHECK: vld1f: ;CHECK: vld1.32 - %tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32(float* %A) + %tmp0 = bitcast float* %A to i8* + %tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %tmp0) ret <2 x float> %tmp1 } define <1 x i64> @vld1i64(i64* %A) nounwind { ;CHECK: vld1i64: ;CHECK: vld1.64 - %tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64(i64* %A) + %tmp0 = bitcast i64* %A to i8* + %tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %tmp0) ret <1 x i64> %tmp1 } @@ -45,28 +49,32 @@ define <16 x i8> @vld1Qi8(i8* %A) nounwind { define <8 x i16> @vld1Qi16(i16* %A) nounwind { ;CHECK: vld1Qi16: ;CHECK: vld1.16 - %tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i16* %A) + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %tmp0) ret <8 x i16> %tmp1 } define <4 x i32> @vld1Qi32(i32* %A) nounwind { ;CHECK: vld1Qi32: ;CHECK: vld1.32 - %tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32(i32* %A) + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32(i8* %tmp0) ret <4 x i32> %tmp1 } define <4 x float> @vld1Qf(float* %A) nounwind { ;CHECK: vld1Qf: ;CHECK: vld1.32 - %tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(float* %A) + %tmp0 = bitcast float* %A to i8* + %tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %tmp0) ret <4 x float> %tmp1 } define <2 x i64> @vld1Qi64(i64* %A) nounwind { ;CHECK: vld1Qi64: ;CHECK: vld1.64 - %tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i64* %A) + %tmp0 = bitcast i64* %A to i8* + %tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %tmp0) ret <2 x i64> %tmp1 } diff --git a/test/CodeGen/ARM/vld2.ll b/test/CodeGen/ARM/vld2.ll index 23f7d2ca0cd3..0838636ce742 100644 --- a/test/CodeGen/ARM/vld2.ll +++ b/test/CodeGen/ARM/vld2.ll @@ -24,7 +24,8 @@ define <8 x i8> @vld2i8(i8* %A) nounwind { define <4 x i16> @vld2i16(i16* %A) nounwind { ;CHECK: vld2i16: ;CHECK: vld2.16 - %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i16* %A) + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp1, 1 %tmp4 = add <4 x i16> %tmp2, %tmp3 @@ -34,7 +35,8 @@ define <4 x i16> @vld2i16(i16* %A) nounwind { define <2 x i32> @vld2i32(i32* %A) nounwind { ;CHECK: vld2i32: ;CHECK: vld2.32 - %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i32* %A) + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp1, 1 %tmp4 = add <2 x i32> %tmp2, %tmp3 @@ -44,17 +46,19 @@ define <2 x i32> @vld2i32(i32* %A) nounwind { define <2 x float> @vld2f(float* %A) nounwind { ;CHECK: vld2f: ;CHECK: vld2.32 - %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(float* %A) + %tmp0 = bitcast float* %A to i8* + %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp1, 1 - %tmp4 = add <2 x float> %tmp2, %tmp3 + %tmp4 = fadd <2 x float> %tmp2, %tmp3 ret <2 x float> %tmp4 } define <1 x i64> @vld2i64(i64* %A) nounwind { ;CHECK: vld2i64: ;CHECK: vld1.64 - %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i64* %A) + %tmp0 = bitcast i64* %A to i8* + %tmp1 = call %struct.__neon_int64x1x2_t @llvm.arm.neon.vld2.v1i64(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int64x1x2_t %tmp1, 1 %tmp4 = add <1 x i64> %tmp2, %tmp3 @@ -74,7 +78,8 @@ define <16 x i8> @vld2Qi8(i8* %A) nounwind { define <8 x i16> @vld2Qi16(i16* %A) nounwind { ;CHECK: vld2Qi16: ;CHECK: vld2.16 - %tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16(i16* %A) + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2.v8i16(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp1, 1 %tmp4 = add <8 x i16> %tmp2, %tmp3 @@ -84,7 +89,8 @@ define <8 x i16> @vld2Qi16(i16* %A) nounwind { define <4 x i32> @vld2Qi32(i32* %A) nounwind { ;CHECK: vld2Qi32: ;CHECK: vld2.32 - %tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i32* %A) + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp1, 1 %tmp4 = add <4 x i32> %tmp2, %tmp3 @@ -94,10 +100,11 @@ define <4 x i32> @vld2Qi32(i32* %A) nounwind { define <4 x float> @vld2Qf(float* %A) nounwind { ;CHECK: vld2Qf: ;CHECK: vld2.32 - %tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32(float* %A) + %tmp0 = bitcast float* %A to i8* + %tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp1, 1 - %tmp4 = add <4 x float> %tmp2, %tmp3 + %tmp4 = fadd <4 x float> %tmp2, %tmp3 ret <4 x float> %tmp4 } diff --git a/test/CodeGen/ARM/vld3.ll b/test/CodeGen/ARM/vld3.ll index 207dc6a22e45..65a24486bc62 100644 --- a/test/CodeGen/ARM/vld3.ll +++ b/test/CodeGen/ARM/vld3.ll @@ -24,7 +24,8 @@ define <8 x i8> @vld3i8(i8* %A) nounwind { define <4 x i16> @vld3i16(i16* %A) nounwind { ;CHECK: vld3i16: ;CHECK: vld3.16 - %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i16* %A) + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp1, 2 %tmp4 = add <4 x i16> %tmp2, %tmp3 @@ -34,7 +35,8 @@ define <4 x i16> @vld3i16(i16* %A) nounwind { define <2 x i32> @vld3i32(i32* %A) nounwind { ;CHECK: vld3i32: ;CHECK: vld3.32 - %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i32* %A) + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int32x2x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x2x3_t %tmp1, 2 %tmp4 = add <2 x i32> %tmp2, %tmp3 @@ -44,17 +46,19 @@ define <2 x i32> @vld3i32(i32* %A) nounwind { define <2 x float> @vld3f(float* %A) nounwind { ;CHECK: vld3f: ;CHECK: vld3.32 - %tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32(float* %A) + %tmp0 = bitcast float* %A to i8* + %tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_float32x2x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_float32x2x3_t %tmp1, 2 - %tmp4 = add <2 x float> %tmp2, %tmp3 + %tmp4 = fadd <2 x float> %tmp2, %tmp3 ret <2 x float> %tmp4 } define <1 x i64> @vld3i64(i64* %A) nounwind { ;CHECK: vld3i64: ;CHECK: vld1.64 - %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i64* %A) + %tmp0 = bitcast i64* %A to i8* + %tmp1 = call %struct.__neon_int64x1x3_t @llvm.arm.neon.vld3.v1i64(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int64x1x3_t %tmp1, 2 %tmp4 = add <1 x i64> %tmp2, %tmp3 @@ -76,7 +80,8 @@ define <8 x i16> @vld3Qi16(i16* %A) nounwind { ;CHECK: vld3Qi16: ;CHECK: vld3.16 ;CHECK: vld3.16 - %tmp1 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3.v8i16(i16* %A) + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3.v8i16(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int16x8x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp1, 2 %tmp4 = add <8 x i16> %tmp2, %tmp3 @@ -87,7 +92,8 @@ define <4 x i32> @vld3Qi32(i32* %A) nounwind { ;CHECK: vld3Qi32: ;CHECK: vld3.32 ;CHECK: vld3.32 - %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i32* %A) + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp1, 2 %tmp4 = add <4 x i32> %tmp2, %tmp3 @@ -98,10 +104,11 @@ define <4 x float> @vld3Qf(float* %A) nounwind { ;CHECK: vld3Qf: ;CHECK: vld3.32 ;CHECK: vld3.32 - %tmp1 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3.v4f32(float* %A) + %tmp0 = bitcast float* %A to i8* + %tmp1 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3.v4f32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_float32x4x3_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_float32x4x3_t %tmp1, 2 - %tmp4 = add <4 x float> %tmp2, %tmp3 + %tmp4 = fadd <4 x float> %tmp2, %tmp3 ret <4 x float> %tmp4 } diff --git a/test/CodeGen/ARM/vld4.ll b/test/CodeGen/ARM/vld4.ll index 0624f2977ea4..e0b870638a18 100644 --- a/test/CodeGen/ARM/vld4.ll +++ b/test/CodeGen/ARM/vld4.ll @@ -24,7 +24,8 @@ define <8 x i8> @vld4i8(i8* %A) nounwind { define <4 x i16> @vld4i16(i16* %A) nounwind { ;CHECK: vld4i16: ;CHECK: vld4.16 - %tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i16* %A) + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 2 %tmp4 = add <4 x i16> %tmp2, %tmp3 @@ -34,7 +35,8 @@ define <4 x i16> @vld4i16(i16* %A) nounwind { define <2 x i32> @vld4i32(i32* %A) nounwind { ;CHECK: vld4i32: ;CHECK: vld4.32 - %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i32* %A) + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 2 %tmp4 = add <2 x i32> %tmp2, %tmp3 @@ -44,17 +46,19 @@ define <2 x i32> @vld4i32(i32* %A) nounwind { define <2 x float> @vld4f(float* %A) nounwind { ;CHECK: vld4f: ;CHECK: vld4.32 - %tmp1 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32(float* %A) + %tmp0 = bitcast float* %A to i8* + %tmp1 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_float32x2x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_float32x2x4_t %tmp1, 2 - %tmp4 = add <2 x float> %tmp2, %tmp3 + %tmp4 = fadd <2 x float> %tmp2, %tmp3 ret <2 x float> %tmp4 } define <1 x i64> @vld4i64(i64* %A) nounwind { ;CHECK: vld4i64: ;CHECK: vld1.64 - %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i64* %A) + %tmp0 = bitcast i64* %A to i8* + %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2 %tmp4 = add <1 x i64> %tmp2, %tmp3 @@ -76,7 +80,8 @@ define <8 x i16> @vld4Qi16(i16* %A) nounwind { ;CHECK: vld4Qi16: ;CHECK: vld4.16 ;CHECK: vld4.16 - %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i16* %A) + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2 %tmp4 = add <8 x i16> %tmp2, %tmp3 @@ -87,7 +92,8 @@ define <4 x i32> @vld4Qi32(i32* %A) nounwind { ;CHECK: vld4Qi32: ;CHECK: vld4.32 ;CHECK: vld4.32 - %tmp1 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32(i32* %A) + %tmp0 = bitcast i32* %A to i8* + %tmp1 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 2 %tmp4 = add <4 x i32> %tmp2, %tmp3 @@ -98,10 +104,11 @@ define <4 x float> @vld4Qf(float* %A) nounwind { ;CHECK: vld4Qf: ;CHECK: vld4.32 ;CHECK: vld4.32 - %tmp1 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32(float* %A) + %tmp0 = bitcast float* %A to i8* + %tmp1 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32(i8* %tmp0) %tmp2 = extractvalue %struct.__neon_float32x4x4_t %tmp1, 0 %tmp3 = extractvalue %struct.__neon_float32x4x4_t %tmp1, 2 - %tmp4 = add <4 x float> %tmp2, %tmp3 + %tmp4 = fadd <4 x float> %tmp2, %tmp3 ret <4 x float> %tmp4 } diff --git a/test/CodeGen/ARM/vldlane.ll b/test/CodeGen/ARM/vldlane.ll index 53881a3f924e..b32c59019f4c 100644 --- a/test/CodeGen/ARM/vldlane.ll +++ b/test/CodeGen/ARM/vldlane.ll @@ -23,8 +23,9 @@ define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vld2lanei16: ;CHECK: vld2.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - %tmp2 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) + %tmp2 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_int16x4x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x4x2_t %tmp2, 1 %tmp5 = add <4 x i16> %tmp3, %tmp4 @@ -34,8 +35,9 @@ define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vld2lanei32: ;CHECK: vld2.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) + %tmp2 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x2x2_t %tmp2, 1 %tmp5 = add <2 x i32> %tmp3, %tmp4 @@ -45,19 +47,21 @@ define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind { define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vld2lanef: ;CHECK: vld2.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B - %tmp2 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) + %tmp2 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x2x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x2x2_t %tmp2, 1 - %tmp5 = add <2 x float> %tmp3, %tmp4 + %tmp5 = fadd <2 x float> %tmp3, %tmp4 ret <2 x float> %tmp5 } define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vld2laneQi16: ;CHECK: vld2.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) + %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x8x2_t %tmp2, 1 %tmp5 = add <8 x i16> %tmp3, %tmp4 @@ -67,8 +71,9 @@ define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vld2laneQi32: ;CHECK: vld2.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - %tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2) + %tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2) %tmp3 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 1 %tmp5 = add <4 x i32> %tmp3, %tmp4 @@ -78,11 +83,12 @@ define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind { define <4 x float> @vld2laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vld2laneQf: ;CHECK: vld2.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B - %tmp2 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) + %tmp2 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x4x2_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x4x2_t %tmp2, 1 - %tmp5 = add <4 x float> %tmp3, %tmp4 + %tmp5 = fadd <4 x float> %tmp3, %tmp4 ret <4 x float> %tmp5 } @@ -120,8 +126,9 @@ define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vld3lanei16: ;CHECK: vld3.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - %tmp2 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) + %tmp2 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int16x4x3_t %tmp2, 2 @@ -133,8 +140,9 @@ define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vld3lanei32: ;CHECK: vld3.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - %tmp2 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) + %tmp2 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int32x2x3_t %tmp2, 2 @@ -146,21 +154,23 @@ define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind { define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vld3lanef: ;CHECK: vld3.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B - %tmp2 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) + %tmp2 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_float32x2x3_t %tmp2, 2 - %tmp6 = add <2 x float> %tmp3, %tmp4 - %tmp7 = add <2 x float> %tmp5, %tmp6 + %tmp6 = fadd <2 x float> %tmp3, %tmp4 + %tmp7 = fadd <2 x float> %tmp5, %tmp6 ret <2 x float> %tmp7 } define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vld3laneQi16: ;CHECK: vld3.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) + %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 2 @@ -172,8 +182,9 @@ define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vld3laneQi32: ;CHECK: vld3.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - %tmp2 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 3) + %tmp2 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 3) %tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 2 @@ -185,13 +196,14 @@ define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind { define <4 x float> @vld3laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vld3laneQf: ;CHECK: vld3.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B - %tmp2 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) + %tmp2 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 2 - %tmp6 = add <4 x float> %tmp3, %tmp4 - %tmp7 = add <4 x float> %tmp5, %tmp6 + %tmp6 = fadd <4 x float> %tmp3, %tmp4 + %tmp7 = fadd <4 x float> %tmp5, %tmp6 ret <4 x float> %tmp7 } @@ -231,8 +243,9 @@ define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vld4lanei16: ;CHECK: vld4.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - %tmp2 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) + %tmp2 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int16x4x4_t %tmp2, 2 @@ -246,8 +259,9 @@ define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind { define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vld4lanei32: ;CHECK: vld4.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - %tmp2 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) + %tmp2 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int32x2x4_t %tmp2, 2 @@ -261,23 +275,25 @@ define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind { define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vld4lanef: ;CHECK: vld4.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B - %tmp2 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) + %tmp2 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 2 %tmp6 = extractvalue %struct.__neon_float32x2x4_t %tmp2, 3 - %tmp7 = add <2 x float> %tmp3, %tmp4 - %tmp8 = add <2 x float> %tmp5, %tmp6 - %tmp9 = add <2 x float> %tmp7, %tmp8 + %tmp7 = fadd <2 x float> %tmp3, %tmp4 + %tmp8 = fadd <2 x float> %tmp5, %tmp6 + %tmp9 = fadd <2 x float> %tmp7, %tmp8 ret <2 x float> %tmp9 } define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vld4laneQi16: ;CHECK: vld4.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - %tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) + %tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int16x8x4_t %tmp2, 2 @@ -291,8 +307,9 @@ define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vld4laneQi32: ;CHECK: vld4.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - %tmp2 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1) + %tmp2 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_int32x4x4_t %tmp2, 2 @@ -306,15 +323,16 @@ define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind { define <4 x float> @vld4laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vld4laneQf: ;CHECK: vld4.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B - %tmp2 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) + %tmp2 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) %tmp3 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 0 %tmp4 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 1 %tmp5 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 2 %tmp6 = extractvalue %struct.__neon_float32x4x4_t %tmp2, 3 - %tmp7 = add <4 x float> %tmp3, %tmp4 - %tmp8 = add <4 x float> %tmp5, %tmp6 - %tmp9 = add <4 x float> %tmp7, %tmp8 + %tmp7 = fadd <4 x float> %tmp3, %tmp4 + %tmp8 = fadd <4 x float> %tmp5, %tmp6 + %tmp9 = fadd <4 x float> %tmp7, %tmp8 ret <4 x float> %tmp9 } diff --git a/test/CodeGen/ARM/vmla.ll b/test/CodeGen/ARM/vmla.ll index 840521827413..77cf10ad3e68 100644 --- a/test/CodeGen/ARM/vmla.ll +++ b/test/CodeGen/ARM/vmla.ll @@ -39,8 +39,8 @@ define <2 x float> @vmlaf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) n %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B %tmp3 = load <2 x float>* %C - %tmp4 = mul <2 x float> %tmp2, %tmp3 - %tmp5 = add <2 x float> %tmp1, %tmp4 + %tmp4 = fmul <2 x float> %tmp2, %tmp3 + %tmp5 = fadd <2 x float> %tmp1, %tmp4 ret <2 x float> %tmp5 } @@ -83,8 +83,8 @@ define <4 x float> @vmlaQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B %tmp3 = load <4 x float>* %C - %tmp4 = mul <4 x float> %tmp2, %tmp3 - %tmp5 = add <4 x float> %tmp1, %tmp4 + %tmp4 = fmul <4 x float> %tmp2, %tmp3 + %tmp5 = fadd <4 x float> %tmp1, %tmp4 ret <4 x float> %tmp5 } diff --git a/test/CodeGen/ARM/vmls.ll b/test/CodeGen/ARM/vmls.ll index c89552e6f9ea..2b70a7878ced 100644 --- a/test/CodeGen/ARM/vmls.ll +++ b/test/CodeGen/ARM/vmls.ll @@ -39,8 +39,8 @@ define <2 x float> @vmlsf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) n %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B %tmp3 = load <2 x float>* %C - %tmp4 = mul <2 x float> %tmp2, %tmp3 - %tmp5 = sub <2 x float> %tmp1, %tmp4 + %tmp4 = fmul <2 x float> %tmp2, %tmp3 + %tmp5 = fsub <2 x float> %tmp1, %tmp4 ret <2 x float> %tmp5 } @@ -83,8 +83,8 @@ define <4 x float> @vmlsQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B %tmp3 = load <4 x float>* %C - %tmp4 = mul <4 x float> %tmp2, %tmp3 - %tmp5 = sub <4 x float> %tmp1, %tmp4 + %tmp4 = fmul <4 x float> %tmp2, %tmp3 + %tmp5 = fsub <4 x float> %tmp1, %tmp4 ret <4 x float> %tmp5 } diff --git a/test/CodeGen/ARM/vmul.ll b/test/CodeGen/ARM/vmul.ll index 325da5deabe5..1d9168021279 100644 --- a/test/CodeGen/ARM/vmul.ll +++ b/test/CodeGen/ARM/vmul.ll @@ -32,7 +32,7 @@ define <2 x float> @vmulf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK: vmul.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B - %tmp3 = mul <2 x float> %tmp1, %tmp2 + %tmp3 = fmul <2 x float> %tmp1, %tmp2 ret <2 x float> %tmp3 } @@ -77,7 +77,7 @@ define <4 x float> @vmulQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK: vmul.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B - %tmp3 = mul <4 x float> %tmp1, %tmp2 + %tmp3 = fmul <4 x float> %tmp1, %tmp2 ret <4 x float> %tmp3 } diff --git a/test/CodeGen/ARM/vneg.ll b/test/CodeGen/ARM/vneg.ll index 7764e87c6ac6..4a10732458e8 100644 --- a/test/CodeGen/ARM/vneg.ll +++ b/test/CodeGen/ARM/vneg.ll @@ -28,7 +28,7 @@ define <2 x float> @vnegf32(<2 x float>* %A) nounwind { ;CHECK: vnegf32: ;CHECK: vneg.f32 %tmp1 = load <2 x float>* %A - %tmp2 = sub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1 + %tmp2 = fsub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1 ret <2 x float> %tmp2 } @@ -60,7 +60,7 @@ define <4 x float> @vnegQf32(<4 x float>* %A) nounwind { ;CHECK: vnegQf32: ;CHECK: vneg.f32 %tmp1 = load <4 x float>* %A - %tmp2 = sub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1 + %tmp2 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1 ret <4 x float> %tmp2 } diff --git a/test/CodeGen/ARM/vst1.ll b/test/CodeGen/ARM/vst1.ll index 602b124ffad9..95414c308914 100644 --- a/test/CodeGen/ARM/vst1.ll +++ b/test/CodeGen/ARM/vst1.ll @@ -11,32 +11,36 @@ define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind { define void @vst1i16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst1i16: ;CHECK: vst1.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - call void @llvm.arm.neon.vst1.v4i16(i16* %A, <4 x i16> %tmp1) + call void @llvm.arm.neon.vst1.v4i16(i8* %tmp0, <4 x i16> %tmp1) ret void } define void @vst1i32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst1i32: ;CHECK: vst1.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - call void @llvm.arm.neon.vst1.v2i32(i32* %A, <2 x i32> %tmp1) + call void @llvm.arm.neon.vst1.v2i32(i8* %tmp0, <2 x i32> %tmp1) ret void } define void @vst1f(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst1f: ;CHECK: vst1.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B - call void @llvm.arm.neon.vst1.v2f32(float* %A, <2 x float> %tmp1) + call void @llvm.arm.neon.vst1.v2f32(i8* %tmp0, <2 x float> %tmp1) ret void } define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind { ;CHECK: vst1i64: ;CHECK: vst1.64 + %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>* %B - call void @llvm.arm.neon.vst1.v1i64(i64* %A, <1 x i64> %tmp1) + call void @llvm.arm.neon.vst1.v1i64(i8* %tmp0, <1 x i64> %tmp1) ret void } @@ -51,32 +55,36 @@ define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind { define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst1Qi16: ;CHECK: vst1.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - call void @llvm.arm.neon.vst1.v8i16(i16* %A, <8 x i16> %tmp1) + call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %tmp1) ret void } define void @vst1Qi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst1Qi32: ;CHECK: vst1.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - call void @llvm.arm.neon.vst1.v4i32(i32* %A, <4 x i32> %tmp1) + call void @llvm.arm.neon.vst1.v4i32(i8* %tmp0, <4 x i32> %tmp1) ret void } define void @vst1Qf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst1Qf: ;CHECK: vst1.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B - call void @llvm.arm.neon.vst1.v4f32(float* %A, <4 x float> %tmp1) + call void @llvm.arm.neon.vst1.v4f32(i8* %tmp0, <4 x float> %tmp1) ret void } define void @vst1Qi64(i64* %A, <2 x i64>* %B) nounwind { ;CHECK: vst1Qi64: ;CHECK: vst1.64 + %tmp0 = bitcast i64* %A to i8* %tmp1 = load <2 x i64>* %B - call void @llvm.arm.neon.vst1.v2i64(i64* %A, <2 x i64> %tmp1) + call void @llvm.arm.neon.vst1.v2i64(i8* %tmp0, <2 x i64> %tmp1) ret void } diff --git a/test/CodeGen/ARM/vst2.ll b/test/CodeGen/ARM/vst2.ll index 17d6bee0f56c..3c98a2cbe60d 100644 --- a/test/CodeGen/ARM/vst2.ll +++ b/test/CodeGen/ARM/vst2.ll @@ -11,32 +11,36 @@ define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind { define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst2i16: ;CHECK: vst2.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - call void @llvm.arm.neon.vst2.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1) + call void @llvm.arm.neon.vst2.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1) ret void } define void @vst2i32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst2i32: ;CHECK: vst2.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - call void @llvm.arm.neon.vst2.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1) + call void @llvm.arm.neon.vst2.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1) ret void } define void @vst2f(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst2f: ;CHECK: vst2.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B - call void @llvm.arm.neon.vst2.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1) + call void @llvm.arm.neon.vst2.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1) ret void } define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind { ;CHECK: vst2i64: ;CHECK: vst1.64 + %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>* %B - call void @llvm.arm.neon.vst2.v1i64(i64* %A, <1 x i64> %tmp1, <1 x i64> %tmp1) + call void @llvm.arm.neon.vst2.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1) ret void } @@ -51,24 +55,27 @@ define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind { define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst2Qi16: ;CHECK: vst2.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - call void @llvm.arm.neon.vst2.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1) + call void @llvm.arm.neon.vst2.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1) ret void } define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst2Qi32: ;CHECK: vst2.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - call void @llvm.arm.neon.vst2.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1) + call void @llvm.arm.neon.vst2.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1) ret void } define void @vst2Qf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst2Qf: ;CHECK: vst2.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B - call void @llvm.arm.neon.vst2.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1) + call void @llvm.arm.neon.vst2.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1) ret void } diff --git a/test/CodeGen/ARM/vst3.ll b/test/CodeGen/ARM/vst3.ll index a831a0c08ce9..2599bc0db933 100644 --- a/test/CodeGen/ARM/vst3.ll +++ b/test/CodeGen/ARM/vst3.ll @@ -11,32 +11,36 @@ define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind { define void @vst3i16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst3i16: ;CHECK: vst3.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - call void @llvm.arm.neon.vst3.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1) + call void @llvm.arm.neon.vst3.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1) ret void } define void @vst3i32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst3i32: ;CHECK: vst3.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - call void @llvm.arm.neon.vst3.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1) + call void @llvm.arm.neon.vst3.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1) ret void } define void @vst3f(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst3f: ;CHECK: vst3.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B - call void @llvm.arm.neon.vst3.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1) + call void @llvm.arm.neon.vst3.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1) ret void } define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind { ;CHECK: vst3i64: ;CHECK: vst1.64 + %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>* %B - call void @llvm.arm.neon.vst3.v1i64(i64* %A, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1) + call void @llvm.arm.neon.vst3.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1) ret void } @@ -53,8 +57,9 @@ define void @vst3Qi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst3Qi16: ;CHECK: vst3.16 ;CHECK: vst3.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - call void @llvm.arm.neon.vst3.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1) + call void @llvm.arm.neon.vst3.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1) ret void } @@ -62,8 +67,9 @@ define void @vst3Qi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst3Qi32: ;CHECK: vst3.32 ;CHECK: vst3.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - call void @llvm.arm.neon.vst3.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1) + call void @llvm.arm.neon.vst3.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1) ret void } @@ -71,8 +77,9 @@ define void @vst3Qf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst3Qf: ;CHECK: vst3.32 ;CHECK: vst3.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B - call void @llvm.arm.neon.vst3.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1) + call void @llvm.arm.neon.vst3.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1) ret void } diff --git a/test/CodeGen/ARM/vst4.ll b/test/CodeGen/ARM/vst4.ll index d92c017c30b2..878f0efaa480 100644 --- a/test/CodeGen/ARM/vst4.ll +++ b/test/CodeGen/ARM/vst4.ll @@ -11,32 +11,36 @@ define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind { define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst4i16: ;CHECK: vst4.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - call void @llvm.arm.neon.vst4.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1) + call void @llvm.arm.neon.vst4.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1) ret void } define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst4i32: ;CHECK: vst4.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - call void @llvm.arm.neon.vst4.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1) + call void @llvm.arm.neon.vst4.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1) ret void } define void @vst4f(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst4f: ;CHECK: vst4.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B - call void @llvm.arm.neon.vst4.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1) + call void @llvm.arm.neon.vst4.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1) ret void } define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind { ;CHECK: vst4i64: ;CHECK: vst1.64 + %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>* %B - call void @llvm.arm.neon.vst4.v1i64(i64* %A, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1) + call void @llvm.arm.neon.vst4.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1) ret void } @@ -53,8 +57,9 @@ define void @vst4Qi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst4Qi16: ;CHECK: vst4.16 ;CHECK: vst4.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - call void @llvm.arm.neon.vst4.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1) + call void @llvm.arm.neon.vst4.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1) ret void } @@ -62,8 +67,9 @@ define void @vst4Qi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst4Qi32: ;CHECK: vst4.32 ;CHECK: vst4.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - call void @llvm.arm.neon.vst4.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1) + call void @llvm.arm.neon.vst4.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1) ret void } @@ -71,8 +77,9 @@ define void @vst4Qf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst4Qf: ;CHECK: vst4.32 ;CHECK: vst4.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B - call void @llvm.arm.neon.vst4.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1) + call void @llvm.arm.neon.vst4.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1) ret void } diff --git a/test/CodeGen/ARM/vstlane.ll b/test/CodeGen/ARM/vstlane.ll index 3bfb14f17b77..cf50756d465e 100644 --- a/test/CodeGen/ARM/vstlane.ll +++ b/test/CodeGen/ARM/vstlane.ll @@ -11,48 +11,54 @@ define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind { define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst2lanei16: ;CHECK: vst2.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - call void @llvm.arm.neon.vst2lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) + call void @llvm.arm.neon.vst2lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) ret void } define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst2lanei32: ;CHECK: vst2.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - call void @llvm.arm.neon.vst2lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) + call void @llvm.arm.neon.vst2lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) ret void } define void @vst2lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst2lanef: ;CHECK: vst2.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B - call void @llvm.arm.neon.vst2lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) + call void @llvm.arm.neon.vst2lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) ret void } define void @vst2laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst2laneQi16: ;CHECK: vst2.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - call void @llvm.arm.neon.vst2lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) + call void @llvm.arm.neon.vst2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1) ret void } define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst2laneQi32: ;CHECK: vst2.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - call void @llvm.arm.neon.vst2lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2) + call void @llvm.arm.neon.vst2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2) ret void } define void @vst2laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst2laneQf: ;CHECK: vst2.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B - call void @llvm.arm.neon.vst2lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, i32 3) + call void @llvm.arm.neon.vst2lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, i32 3) ret void } @@ -76,48 +82,54 @@ define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind { define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst3lanei16: ;CHECK: vst3.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - call void @llvm.arm.neon.vst3lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) + call void @llvm.arm.neon.vst3lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) ret void } define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst3lanei32: ;CHECK: vst3.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - call void @llvm.arm.neon.vst3lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) + call void @llvm.arm.neon.vst3lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) ret void } define void @vst3lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst3lanef: ;CHECK: vst3.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B - call void @llvm.arm.neon.vst3lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) + call void @llvm.arm.neon.vst3lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) ret void } define void @vst3laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst3laneQi16: ;CHECK: vst3.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - call void @llvm.arm.neon.vst3lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 6) + call void @llvm.arm.neon.vst3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 6) ret void } define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst3laneQi32: ;CHECK: vst3.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - call void @llvm.arm.neon.vst3lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0) + call void @llvm.arm.neon.vst3lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 0) ret void } define void @vst3laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst3laneQf: ;CHECK: vst3.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B - call void @llvm.arm.neon.vst3lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) + call void @llvm.arm.neon.vst3lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) ret void } @@ -142,48 +154,54 @@ define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind { define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vst4lanei16: ;CHECK: vst4.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B - call void @llvm.arm.neon.vst4lane.v4i16(i16* %A, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) + call void @llvm.arm.neon.vst4lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1) ret void } define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vst4lanei32: ;CHECK: vst4.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B - call void @llvm.arm.neon.vst4lane.v2i32(i32* %A, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) + call void @llvm.arm.neon.vst4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1) ret void } define void @vst4lanef(float* %A, <2 x float>* %B) nounwind { ;CHECK: vst4lanef: ;CHECK: vst4.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B - call void @llvm.arm.neon.vst4lane.v2f32(float* %A, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) + call void @llvm.arm.neon.vst4lane.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1) ret void } define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vst4laneQi16: ;CHECK: vst4.16 + %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B - call void @llvm.arm.neon.vst4lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 7) + call void @llvm.arm.neon.vst4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 7) ret void } define void @vst4laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst4laneQi32: ;CHECK: vst4.32 + %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B - call void @llvm.arm.neon.vst4lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2) + call void @llvm.arm.neon.vst4lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2) ret void } define void @vst4laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst4laneQf: ;CHECK: vst4.32 + %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B - call void @llvm.arm.neon.vst4lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) + call void @llvm.arm.neon.vst4lane.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1) ret void } diff --git a/test/CodeGen/ARM/vsub.ll b/test/CodeGen/ARM/vsub.ll index 8f0055fd4103..3416de76f123 100644 --- a/test/CodeGen/ARM/vsub.ll +++ b/test/CodeGen/ARM/vsub.ll @@ -41,7 +41,7 @@ define <2 x float> @vsubf32(<2 x float>* %A, <2 x float>* %B) nounwind { ;CHECK: vsub.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B - %tmp3 = sub <2 x float> %tmp1, %tmp2 + %tmp3 = fsub <2 x float> %tmp1, %tmp2 ret <2 x float> %tmp3 } @@ -86,7 +86,7 @@ define <4 x float> @vsubQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK: vsub.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B - %tmp3 = sub <4 x float> %tmp1, %tmp2 + %tmp3 = fsub <4 x float> %tmp1, %tmp2 ret <4 x float> %tmp3 } diff --git a/test/CodeGen/ARM/vtrn.ll b/test/CodeGen/ARM/vtrn.ll index 5122b0981e96..10bb10ac24a1 100644 --- a/test/CodeGen/ARM/vtrn.ll +++ b/test/CodeGen/ARM/vtrn.ll @@ -44,7 +44,7 @@ define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind { %tmp2 = load <2 x float>* %B %tmp3 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 0, i32 2> %tmp4 = shufflevector <2 x float> %tmp1, <2 x float> %tmp2, <2 x i32> <i32 1, i32 3> - %tmp5 = add <2 x float> %tmp3, %tmp4 + %tmp5 = fadd <2 x float> %tmp3, %tmp4 ret <2 x float> %tmp5 } @@ -92,6 +92,6 @@ define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind { %tmp2 = load <4 x float>* %B %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 2, i32 6> %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 5, i32 3, i32 7> - %tmp5 = add <4 x float> %tmp3, %tmp4 + %tmp5 = fadd <4 x float> %tmp3, %tmp4 ret <4 x float> %tmp5 } diff --git a/test/CodeGen/ARM/vuzp.ll b/test/CodeGen/ARM/vuzp.ll index e531718d94aa..6cef188d76dd 100644 --- a/test/CodeGen/ARM/vuzp.ll +++ b/test/CodeGen/ARM/vuzp.ll @@ -70,6 +70,6 @@ define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind { %tmp2 = load <4 x float>* %B %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7> - %tmp5 = add <4 x float> %tmp3, %tmp4 + %tmp5 = fadd <4 x float> %tmp3, %tmp4 ret <4 x float> %tmp5 } diff --git a/test/CodeGen/ARM/vzip.ll b/test/CodeGen/ARM/vzip.ll index 32f7e0d02c44..a9ecdcab42d7 100644 --- a/test/CodeGen/ARM/vzip.ll +++ b/test/CodeGen/ARM/vzip.ll @@ -70,6 +70,6 @@ define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind { %tmp2 = load <4 x float>* %B %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 4, i32 1, i32 5> %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 2, i32 6, i32 3, i32 7> - %tmp5 = add <4 x float> %tmp3, %tmp4 + %tmp5 = fadd <4 x float> %tmp3, %tmp4 ret <4 x float> %tmp5 } diff --git a/test/CodeGen/Alpha/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/Alpha/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 000000000000..cf3f0b90037d --- /dev/null +++ b/test/CodeGen/Alpha/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=alpha -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/Blackfin/jumptable.ll b/test/CodeGen/Blackfin/jumptable.ll index 5f49e9d193e4..263533c00097 100644 --- a/test/CodeGen/Blackfin/jumptable.ll +++ b/test/CodeGen/Blackfin/jumptable.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=bfin -verify-machineinstrs | FileCheck %s ; CHECK: .section .rodata -; CHECK: JTI1_0: -; CHECK: .long .BB1_1 +; CHECK: JTI0_0: +; CHECK: .long .BB0_1 define i32 @oper(i32 %op, i32 %A, i32 %B) { entry: diff --git a/test/CodeGen/CellSPU/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/CellSPU/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 000000000000..45d53c8c975f --- /dev/null +++ b/test/CodeGen/CellSPU/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=cellspu -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/CellSPU/bss.ll b/test/CodeGen/CellSPU/bss.ll index 05a0f5003931..327800d09cbf 100644 --- a/test/CodeGen/CellSPU/bss.ll +++ b/test/CodeGen/CellSPU/bss.ll @@ -1,5 +1,11 @@ -; RUN: llc < %s -march=cellspu > %t1.s -; RUN: grep "\.section" %t1.s | grep "\.bss" | count 1 +; RUN: llc < %s -march=cellspu | FileCheck %s @bssVar = global i32 zeroinitializer +; CHECK: .section .bss +; CHECK-NEXT: .globl + +@localVar= internal global i32 zeroinitializer +; CHECK-NOT: .lcomm +; CHECK: .local +; CHECK-NEXT: .comm diff --git a/test/CodeGen/CellSPU/crash.ll b/test/CodeGen/CellSPU/crash.ll new file mode 100644 index 000000000000..cc2ab71db3b3 --- /dev/null +++ b/test/CodeGen/CellSPU/crash.ll @@ -0,0 +1,8 @@ +; RUN: llc %s -march=cellspu -o - +declare i8 @return_i8() +declare i16 @return_i16() +define void @testfunc() { + %rv1 = call i8 @return_i8() + %rv2 = call i16 @return_i16() + ret void +}
\ No newline at end of file diff --git a/test/CodeGen/Generic/2007-05-03-EHTypeInfo.ll b/test/CodeGen/Generic/2007-05-03-EHTypeInfo.ll index bb774b45d8ee..81347a23b864 100644 --- a/test/CodeGen/Generic/2007-05-03-EHTypeInfo.ll +++ b/test/CodeGen/Generic/2007-05-03-EHTypeInfo.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -enable-eh +; RUN: llc < %s %struct.exception = type { i8, i8, i32, i8*, i8*, i32, i8* } @program_error = external global %struct.exception ; <%struct.exception*> [#uses=1] diff --git a/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll b/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll index 4cc1e7c181ed..5df2200dec76 100644 --- a/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll +++ b/test/CodeGen/Generic/2007-12-17-InvokeAsm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -enable-eh +; RUN: llc < %s define fastcc void @bc__support__high_resolution_time__initialize_clock_rate() { entry: diff --git a/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll b/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll index d2e97a477b44..00e027b8d3c8 100644 --- a/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll +++ b/test/CodeGen/Generic/2007-12-31-UnusedSelector.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -enable-eh +; RUN: llc < %s ; PR1833 %struct.__class_type_info_pseudo = type { %struct.__type_info_pseudo } diff --git a/test/CodeGen/Generic/crash.ll b/test/CodeGen/Generic/crash.ll new file mode 100644 index 000000000000..7218565617fc --- /dev/null +++ b/test/CodeGen/Generic/crash.ll @@ -0,0 +1,8 @@ +; RUN: llc %s -o - + +; PR6332 +%struct.AVCodecTag = type opaque +@ff_codec_bmp_tags = external global [0 x %struct.AVCodecTag] +@tags = global [1 x %struct.AVCodecTag*] [%struct.AVCodecTag* getelementptr +inbounds ([0 x %struct.AVCodecTag]* @ff_codec_bmp_tags, i32 0, i32 0)] + diff --git a/test/CodeGen/MBlaze/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/MBlaze/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 000000000000..854352a70111 --- /dev/null +++ b/test/CodeGen/MBlaze/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=mblaze -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/MSP430/2009-05-17-Rot.ll b/test/CodeGen/MSP430/2009-05-17-Rot.ll index 2ae005259d4f..d622aa71164b 100644 --- a/test/CodeGen/MSP430/2009-05-17-Rot.ll +++ b/test/CodeGen/MSP430/2009-05-17-Rot.ll @@ -14,4 +14,4 @@ define i16 @rol1u16(i16 %x.arg) nounwind { return: %6 = load i16* %retval ret i16 %6 -}
\ No newline at end of file +} diff --git a/test/CodeGen/MSP430/2009-05-17-Shift.ll b/test/CodeGen/MSP430/2009-05-17-Shift.ll index 25aff60c2b3f..e23df7851666 100644 --- a/test/CodeGen/MSP430/2009-05-17-Shift.ll +++ b/test/CodeGen/MSP430/2009-05-17-Shift.ll @@ -12,4 +12,4 @@ return: %3 = load i16* %retval ret i16 %3 -}
\ No newline at end of file +} diff --git a/test/CodeGen/MSP430/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/MSP430/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 000000000000..8de044cf48ba --- /dev/null +++ b/test/CodeGen/MSP430/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=msp430 -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/MSP430/2010-05-01-CombinerAnd.ll b/test/CodeGen/MSP430/2010-05-01-CombinerAnd.ll new file mode 100644 index 000000000000..99100377034b --- /dev/null +++ b/test/CodeGen/MSP430/2010-05-01-CombinerAnd.ll @@ -0,0 +1,27 @@ +; RUN: llc < %s +; PR7001 + +target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16" +target triple = "msp430-elf" + +define i16 @main() nounwind { +entry: + br label %while.cond + +while.cond: ; preds = %while.body, %entry + br i1 undef, label %land.rhs, label %land.end + +land.rhs: ; preds = %while.cond + br label %land.end + +land.end: ; preds = %land.rhs, %while.cond + %0 = phi i1 [ false, %while.cond ], [ undef, %land.rhs ] ; <i1> [#uses=1] + br i1 %0, label %while.body, label %while.end + +while.body: ; preds = %land.end + %tmp4 = load i16* undef ; <i16> [#uses=0] + br label %while.cond + +while.end: ; preds = %land.end + ret i16 undef +} diff --git a/test/CodeGen/MSP430/indirectbr.ll b/test/CodeGen/MSP430/indirectbr.ll new file mode 100644 index 000000000000..2a62c9135c6a --- /dev/null +++ b/test/CodeGen/MSP430/indirectbr.ll @@ -0,0 +1,41 @@ +; RUN: llc -march=msp430 < %s + +@nextaddr = global i8* null ; <i8**> [#uses=2] +@C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1] + +define internal i16 @foo(i16 %i) nounwind { +entry: + %0 = load i8** @nextaddr, align 4 ; <i8*> [#uses=2] + %1 = icmp eq i8* %0, null ; <i1> [#uses=1] + br i1 %1, label %bb3, label %bb2 + +bb2: ; preds = %bb3, %entry + %gotovar.4.0 = phi i8* [ %gotovar.4.0.pre, %bb3 ], [ %0, %entry ] ; <i8*> [#uses=1] + indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1] + +bb3: ; preds = %entry + %2 = getelementptr inbounds [5 x i8*]* @C.0.2070, i16 0, i16 %i ; <i8**> [#uses=1] + %gotovar.4.0.pre = load i8** %2, align 4 ; <i8*> [#uses=1] + br label %bb2 + +L5: ; preds = %bb2 + br label %L4 + +L4: ; preds = %L5, %bb2 + %res.0 = phi i16 [ 385, %L5 ], [ 35, %bb2 ] ; <i16> [#uses=1] + br label %L3 + +L3: ; preds = %L4, %bb2 + %res.1 = phi i16 [ %res.0, %L4 ], [ 5, %bb2 ] ; <i16> [#uses=1] + br label %L2 + +L2: ; preds = %L3, %bb2 + %res.2 = phi i16 [ %res.1, %L3 ], [ 1, %bb2 ] ; <i16> [#uses=1] + %phitmp = mul i16 %res.2, 6 ; <i16> [#uses=1] + br label %L1 + +L1: ; preds = %L2, %bb2 + %res.3 = phi i16 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i16> [#uses=1] + store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4 + ret i16 %res.3 +} diff --git a/test/CodeGen/MSP430/indirectbr2.ll b/test/CodeGen/MSP430/indirectbr2.ll new file mode 100644 index 000000000000..93cfb2506bb4 --- /dev/null +++ b/test/CodeGen/MSP430/indirectbr2.ll @@ -0,0 +1,29 @@ +; RUN: llc -march=msp430 < %s | FileCheck %s +@C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1] + +define internal i16 @foo(i16 %i) nounwind { +entry: + %tmp1 = getelementptr inbounds [5 x i8*]* @C.0.2070, i16 0, i16 %i ; <i8**> [#uses=1] + %gotovar.4.0 = load i8** %tmp1, align 4 ; <i8*> [#uses=1] +; CHECK: mov.w .LC.0.2070(r15), pc + indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1] + +L5: ; preds = %bb2 + br label %L4 + +L4: ; preds = %L5, %bb2 + %res.0 = phi i16 [ 385, %L5 ], [ 35, %entry ] ; <i16> [#uses=1] + br label %L3 + +L3: ; preds = %L4, %bb2 + %res.1 = phi i16 [ %res.0, %L4 ], [ 5, %entry ] ; <i16> [#uses=1] + br label %L2 + +L2: ; preds = %L3, %bb2 + %res.2 = phi i16 [ %res.1, %L3 ], [ 1, %entry ] ; <i16> [#uses=1] + br label %L1 + +L1: ; preds = %L2, %bb2 + %res.3 = phi i16 [ %res.2, %L2 ], [ 2, %entry ] ; <i16> [#uses=1] + ret i16 %res.3 +} diff --git a/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll b/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll index 636b318014a5..b8d68269af42 100644 --- a/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll +++ b/test/CodeGen/Mips/2009-11-16-CstPoolLoad.ll @@ -4,7 +4,7 @@ target triple = "mips-unknown-linux" define float @h() nounwind readnone { entry: -; CHECK: lw $2, %got($CPI1_0)($gp) -; CHECK: lwc1 $f0, %lo($CPI1_0)($2) +; CHECK: lw $2, %got($CPI0_0)($gp) +; CHECK: lwc1 $f0, %lo($CPI0_0)($2) ret float 0x400B333340000000 } diff --git a/test/CodeGen/Mips/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/Mips/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 000000000000..4161c1d686e6 --- /dev/null +++ b/test/CodeGen/Mips/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=mips -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/PIC16/2009-11-20-NewNode.ll b/test/CodeGen/PIC16/2009-11-20-NewNode.ll index f9d66ca63471..d68f0f41c4a5 100644 --- a/test/CodeGen/PIC16/2009-11-20-NewNode.ll +++ b/test/CodeGen/PIC16/2009-11-20-NewNode.ll @@ -1,6 +1,5 @@ ; RUN: llc -march=pic16 < %s ; PR5558 -; XFAIL: vg_leak define i64 @_strtoll_r(i16 %base) nounwind { entry: diff --git a/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll b/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll index 439ef14d8b24..0c1167409447 100644 --- a/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll +++ b/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -enable-eh +; RUN: llc < %s ;; Formerly crashed, see PR 1508 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc64-apple-darwin8" diff --git a/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll b/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll index a05245d542fc..db2ab877ff7d 100644 --- a/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll +++ b/test/CodeGen/PowerPC/2008-01-25-EmptyFunction.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc32 | grep .byte +; RUN: llc < %s -march=ppc32 | grep nop target triple = "powerpc-apple-darwin8" diff --git a/test/CodeGen/PowerPC/2010-02-04-EmptyGlobal.ll b/test/CodeGen/PowerPC/2010-02-04-EmptyGlobal.ll index 32ddb3484812..1ba11d3fd036 100644 --- a/test/CodeGen/PowerPC/2010-02-04-EmptyGlobal.ll +++ b/test/CodeGen/PowerPC/2010-02-04-EmptyGlobal.ll @@ -8,4 +8,13 @@ ; CHECK: .globl __cmd ; CHECK-NEXT: .align 3 ; CHECK-NEXT: __cmd: -; CHECK-NEXT: .space 1 +; CHECK-NEXT: .byte 0 + +; PR6340 + +%Ty = type { i32, {}, i32 } +@k = global %Ty { i32 1, {} zeroinitializer, i32 3 } + +; CHECK: _k: +; CHECK-NEXT: .long 1 +; CHECK-NEXT: .long 3 diff --git a/test/CodeGen/PowerPC/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/PowerPC/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 000000000000..f48f32f8fb17 --- /dev/null +++ b/test/CodeGen/PowerPC/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=ppc32 -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll b/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll new file mode 100644 index 000000000000..b10920a6c10d --- /dev/null +++ b/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mcpu=g5 | FileCheck %s + +declare i8* @llvm.frameaddress(i32) nounwind readnone + +define i8* @g2() nounwind readnone { +entry: +; CHECK: _g2: +; CHECK: lwz r3, 0(r1) + %0 = tail call i8* @llvm.frameaddress(i32 1) ; <i8*> [#uses=1] + ret i8* %0 +} + +declare i8* @llvm.returnaddress(i32) nounwind readnone + +define i8* @g() nounwind readnone { +entry: +; CHECK: _g: +; CHECK: mflr r0 +; CHECK: stw r0, 8(r1) +; CHECK: lwz r3, 0(r1) +; CHECK: lwz r3, 8(r3) + %0 = tail call i8* @llvm.returnaddress(i32 1) ; <i8*> [#uses=1] + ret i8* %0 +} diff --git a/test/CodeGen/PowerPC/indirectbr.ll b/test/CodeGen/PowerPC/indirectbr.ll index 9b76ecc43db9..ab8d9dca5dc4 100644 --- a/test/CodeGen/PowerPC/indirectbr.ll +++ b/test/CodeGen/PowerPC/indirectbr.ll @@ -43,8 +43,8 @@ L2: ; preds = %L3, %bb2 L1: ; preds = %L2, %bb2 %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1] -; PIC: addis r4, r4, ha16(Ltmp0-"L1$pb") -; PIC: li r6, lo16(Ltmp0-"L1$pb") +; PIC: addis r4, r4, ha16(Ltmp0-"L0$pb") +; PIC: li r6, lo16(Ltmp0-"L0$pb") ; PIC: add r4, r4, r6 ; PIC: stw r4 ; STATIC: li r5, lo16(Ltmp0) diff --git a/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll b/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll index 7bce01c00afa..3dc8061a52a7 100644 --- a/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll +++ b/test/CodeGen/PowerPC/rlwimi-keep-rsh.ll @@ -25,4 +25,4 @@ entry: return: ret void ; CHECK: blr -}
\ No newline at end of file +} diff --git a/test/CodeGen/SPARC/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/SPARC/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 000000000000..f66ee216089d --- /dev/null +++ b/test/CodeGen/SPARC/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=sparc -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/SystemZ/00-RetVoid.ll b/test/CodeGen/SystemZ/00-RetVoid.ll index de23795ab08a..6f3cbac738f8 100644 --- a/test/CodeGen/SystemZ/00-RetVoid.ll +++ b/test/CodeGen/SystemZ/00-RetVoid.ll @@ -3,4 +3,4 @@ define void @foo() { entry: ret void -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/01-RetArg.ll b/test/CodeGen/SystemZ/01-RetArg.ll index 9ab2097a0c89..8e1ff49c26fa 100644 --- a/test/CodeGen/SystemZ/01-RetArg.ll +++ b/test/CodeGen/SystemZ/01-RetArg.ll @@ -3,4 +3,4 @@ define i64 @foo(i64 %a, i64 %b) { entry: ret i64 %b -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/02-RetAdd.ll b/test/CodeGen/SystemZ/02-RetAdd.ll index 9ff9b6ac3833..d5dfa220ad23 100644 --- a/test/CodeGen/SystemZ/02-RetAdd.ll +++ b/test/CodeGen/SystemZ/02-RetAdd.ll @@ -3,4 +3,4 @@ define i64 @foo(i64 %a, i64 %b) { entry: %c = add i64 %a, %b ret i64 %c -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/02-RetAddImm.ll b/test/CodeGen/SystemZ/02-RetAddImm.ll index 6d73e4d42ab2..40f6cce936bd 100644 --- a/test/CodeGen/SystemZ/02-RetAddImm.ll +++ b/test/CodeGen/SystemZ/02-RetAddImm.ll @@ -3,4 +3,4 @@ define i64 @foo(i64 %a, i64 %b) { entry: %c = add i64 %a, 1 ret i64 %c -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/02-RetAnd.ll b/test/CodeGen/SystemZ/02-RetAnd.ll index 1492f9dbee75..b568a57f8bee 100644 --- a/test/CodeGen/SystemZ/02-RetAnd.ll +++ b/test/CodeGen/SystemZ/02-RetAnd.ll @@ -4,4 +4,4 @@ define i64 @foo(i64 %a, i64 %b) { entry: %c = and i64 %a, %b ret i64 %c -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/02-RetNeg.ll b/test/CodeGen/SystemZ/02-RetNeg.ll index 7f3380dc16ac..3f6ba2f27fd4 100644 --- a/test/CodeGen/SystemZ/02-RetNeg.ll +++ b/test/CodeGen/SystemZ/02-RetNeg.ll @@ -4,4 +4,4 @@ define i64 @foo(i64 %a) { entry: %c = sub i64 0, %a ret i64 %c -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/02-RetOr.ll b/test/CodeGen/SystemZ/02-RetOr.ll index 1e8134d2ddcc..a1ddb63d04ab 100644 --- a/test/CodeGen/SystemZ/02-RetOr.ll +++ b/test/CodeGen/SystemZ/02-RetOr.ll @@ -3,4 +3,4 @@ define i64 @foo(i64 %a, i64 %b) { entry: %c = or i64 %a, %b ret i64 %c -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/02-RetSub.ll b/test/CodeGen/SystemZ/02-RetSub.ll index 1c4514f36c93..98e1861365fd 100644 --- a/test/CodeGen/SystemZ/02-RetSub.ll +++ b/test/CodeGen/SystemZ/02-RetSub.ll @@ -4,4 +4,4 @@ define i64 @foo(i64 %a, i64 %b) { entry: %c = sub i64 %a, %b ret i64 %c -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/02-RetSubImm.ll b/test/CodeGen/SystemZ/02-RetSubImm.ll index 4f91cb073997..8479fbf8656e 100644 --- a/test/CodeGen/SystemZ/02-RetSubImm.ll +++ b/test/CodeGen/SystemZ/02-RetSubImm.ll @@ -4,4 +4,4 @@ define i64 @foo(i64 %a, i64 %b) { entry: %c = sub i64 %a, 1 ret i64 %c -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/02-RetXor.ll b/test/CodeGen/SystemZ/02-RetXor.ll index a9439bf452a7..4d1adf2f367c 100644 --- a/test/CodeGen/SystemZ/02-RetXor.ll +++ b/test/CodeGen/SystemZ/02-RetXor.ll @@ -3,4 +3,4 @@ define i64 @foo(i64 %a, i64 %b) { entry: %c = xor i64 %a, %b ret i64 %c -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/02-RetXorImm.ll b/test/CodeGen/SystemZ/02-RetXorImm.ll index ea4b8290df3b..473bbf74f5bc 100644 --- a/test/CodeGen/SystemZ/02-RetXorImm.ll +++ b/test/CodeGen/SystemZ/02-RetXorImm.ll @@ -3,4 +3,4 @@ define i64 @foo(i64 %a, i64 %b) { entry: %c = xor i64 %a, 1 ret i64 %c -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/2009-07-11-FloatBitConvert.ll b/test/CodeGen/SystemZ/2009-07-11-FloatBitConvert.ll index 564d3438310a..5457b12afcba 100644 --- a/test/CodeGen/SystemZ/2009-07-11-FloatBitConvert.ll +++ b/test/CodeGen/SystemZ/2009-07-11-FloatBitConvert.ll @@ -13,4 +13,4 @@ define i32 @bar(float %a) { entry: %b = bitcast float %a to i32 ret i32 %b -}
\ No newline at end of file +} diff --git a/test/CodeGen/SystemZ/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/SystemZ/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 000000000000..610aa40197e3 --- /dev/null +++ b/test/CodeGen/SystemZ/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=systemz -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/Thumb/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/Thumb/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 000000000000..6b6c14f40871 --- /dev/null +++ b/test/CodeGen/Thumb/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=thumb -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/Thumb/machine-licm.ll b/test/CodeGen/Thumb/machine-licm.ll index dae1412b9130..a69a64f5c15d 100644 --- a/test/CodeGen/Thumb/machine-licm.ll +++ b/test/CodeGen/Thumb/machine-licm.ll @@ -15,12 +15,12 @@ entry: bb.nph: ; preds = %entry ; CHECK: BB#1 -; CHECK: ldr.n r2, LCPI1_0 +; CHECK: ldr.n r2, LCPI0_0 ; CHECK: add r2, pc ; CHECK: ldr r{{[0-9]+}}, [r2] -; CHECK: LBB1_2 -; CHECK: LCPI1_0: -; CHECK-NOT: LCPI1_1: +; CHECK: LBB0_2 +; CHECK: LCPI0_0: +; CHECK-NOT: LCPI0_1: ; CHECK: .section %.pre = load i32* @GV, align 4 ; <i32> [#uses=1] br label %bb diff --git a/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll b/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll index bfb7f6eabc7f..e3086a332a8b 100644 --- a/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll +++ b/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s -mtriple=thumbv7-eabi -mcpu=cortex-a8 -float-abi=hard | FileCheck %s - -; A fix for PR5204 will require this check to be changed. +; PR5204 %"struct.__gnu_cxx::__normal_iterator<char*,std::basic_string<char, std::char_traits<char>, std::allocator<char> > >" = type { i8* } %"struct.__gnu_cxx::new_allocator<char>" = type <{ i8 }> @@ -11,11 +10,9 @@ define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this, %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) { ; CHECK: _ZNKSs7compareERKSs: -; CHECK: it ne -; CHECK-NEXT: ldmiane.w -; CHECK-NEXT: itt eq -; CHECK-NEXT: subeq.w -; CHECK-NEXT: ldmiaeq.w +; CHECK: it eq +; CHECK-NEXT: subeq.w r0, r6, r8 +; CHECK-NEXT: ldmia.w sp, {r4, r5, r6, r8, r9, pc} entry: %0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i32> [#uses=3] %1 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) ; <i32> [#uses=3] diff --git a/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll b/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll new file mode 100644 index 000000000000..fea2dca6a273 --- /dev/null +++ b/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -O3 | FileCheck %s +; rdar://7493908 + +; Make sure the result of the first dynamic_alloc isn't copied back to sp more +; than once. We'll deal with poor codegen later. + +define arm_apcscc void @t() nounwind ssp { +entry: +; CHECK: t: +; CHECK: mov r0, sp +; CHECK: bfc r0, #0, #3 +; CHECK: subs r0, #16 +; CHECK: mov sp, r0 +; Yes, this is stupid codegen, but it's correct. +; CHECK: mov r0, sp +; CHECK: bfc r0, #0, #3 +; CHECK: subs r0, #16 +; CHECK: mov sp, r0 + %size = mul i32 8, 2 + %vla_a = alloca i8, i32 %size, align 8 + %vla_b = alloca i8, i32 %size, align 8 + unreachable +} diff --git a/test/CodeGen/Thumb2/2010-04-26-CopyRegCrash.ll b/test/CodeGen/Thumb2/2010-04-26-CopyRegCrash.ll new file mode 100644 index 000000000000..950b67e6a596 --- /dev/null +++ b/test/CodeGen/Thumb2/2010-04-26-CopyRegCrash.ll @@ -0,0 +1,73 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin +; Radar 7896289 + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +define arm_apcscc void @test(i32 %mode) nounwind optsize noinline { +entry: + br i1 undef, label %return, label %bb3 + +bb3: ; preds = %entry + br i1 undef, label %bb15, label %bb18 + +bb15: ; preds = %bb3 + unreachable + +bb18: ; preds = %bb3 + switch i32 %mode, label %return [ + i32 0, label %bb26 + i32 1, label %bb56 + i32 2, label %bb107 + i32 6, label %bb150.preheader + i32 9, label %bb310.preheader + i32 13, label %bb414.preheader + i32 15, label %bb468.preheader + i32 16, label %bb522.preheader + ] + +bb150.preheader: ; preds = %bb18 + br i1 undef, label %bb154, label %bb160 + +bb310.preheader: ; preds = %bb18 + unreachable + +bb414.preheader: ; preds = %bb18 + unreachable + +bb468.preheader: ; preds = %bb18 + unreachable + +bb522.preheader: ; preds = %bb18 + unreachable + +bb26: ; preds = %bb18 + unreachable + +bb56: ; preds = %bb18 + unreachable + +bb107: ; preds = %bb18 + br label %bb110 + +bb110: ; preds = %bb122, %bb107 + %asmtmp.i.i179 = tail call i16 asm "rev16 $0, $1\0A", "=l,l"(i16 undef) nounwind ; <i16> [#uses=1] + %asmtmp.i.i178 = tail call i16 asm "rev16 $0, $1\0A", "=l,l"(i16 %asmtmp.i.i179) nounwind ; <i16> [#uses=1] + store i16 %asmtmp.i.i178, i16* undef, align 2 + br i1 undef, label %bb122, label %bb121 + +bb121: ; preds = %bb110 + br label %bb122 + +bb122: ; preds = %bb121, %bb110 + br label %bb110 + +bb154: ; preds = %bb150.preheader + unreachable + +bb160: ; preds = %bb150.preheader + unreachable + +return: ; preds = %bb18, %entry + ret void +} diff --git a/test/CodeGen/Thumb2/bfx.ll b/test/CodeGen/Thumb2/bfx.ll new file mode 100644 index 000000000000..489349d61552 --- /dev/null +++ b/test/CodeGen/Thumb2/bfx.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s + +define i32 @sbfx1(i32 %a) { +; CHECK: sbfx1 +; CHECK: sbfx r0, r0, #7, #11 + %t1 = lshr i32 %a, 7 + %t2 = trunc i32 %t1 to i11 + %t3 = sext i11 %t2 to i32 + ret i32 %t3 +} + +define i32 @ubfx1(i32 %a) { +; CHECK: ubfx1 +; CHECK: ubfx r0, r0, #7, #11 + %t1 = lshr i32 %a, 7 + %t2 = trunc i32 %t1 to i11 + %t3 = zext i11 %t2 to i32 + ret i32 %t3 +} + +define i32 @ubfx2(i32 %a) { +; CHECK: ubfx2 +; CHECK: ubfx r0, r0, #7, #11 + %t1 = lshr i32 %a, 7 + %t2 = and i32 %t1, 2047 + ret i32 %t2 +} + diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll index 2b209319792d..6c453499a431 100644 --- a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll +++ b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 3 +; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 1 define arm_apcscc void @fht(float* nocapture %fz, i16 signext %n) nounwind { entry: diff --git a/test/CodeGen/Thumb2/load-global.ll b/test/CodeGen/Thumb2/load-global.ll index 92866700bd65..46e053ca4ea5 100644 --- a/test/CodeGen/Thumb2/load-global.ll +++ b/test/CodeGen/Thumb2/load-global.ll @@ -14,7 +14,7 @@ define i32 @test1() { ; PIC: _test1 ; PIC: add r0, pc -; PIC: .long L_G$non_lazy_ptr-(LPC1_0+4) +; PIC: .long L_G$non_lazy_ptr-(LPC0_0+4) ; LINUX: test1 ; LINUX: .long G(GOT) diff --git a/test/CodeGen/Thumb2/lsr-deficiency.ll b/test/CodeGen/Thumb2/lsr-deficiency.ll index ac2cd34e4b34..2038606aa8c4 100644 --- a/test/CodeGen/Thumb2/lsr-deficiency.ll +++ b/test/CodeGen/Thumb2/lsr-deficiency.ll @@ -19,7 +19,7 @@ entry: br label %bb bb: ; preds = %bb, %entry -; CHECK: LBB1_1: +; CHECK: LBB0_1: ; CHECK: cmp r2, #0 ; CHECK: sub.w r9, r2, #1 ; CHECK: mov r2, r9 diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll index 53ff53725c57..c298aa2dd936 100644 --- a/test/CodeGen/Thumb2/machine-licm.ll +++ b/test/CodeGen/Thumb2/machine-licm.ll @@ -17,22 +17,22 @@ entry: bb.nph: ; preds = %entry ; CHECK: BB#1 -; CHECK: ldr.n r2, LCPI1_0 +; CHECK: ldr.n r2, LCPI0_0 ; CHECK: ldr r2, [r2] ; CHECK: ldr r3, [r2] -; CHECK: LBB1_2 -; CHECK: LCPI1_0: +; CHECK: LBB0_2 +; CHECK: LCPI0_0: ; CHECK-NOT: LCPI1_1: ; CHECK: .section ; PIC: BB#1 -; PIC: ldr.n r2, LCPI1_0 +; PIC: ldr.n r2, LCPI0_0 ; PIC: add r2, pc ; PIC: ldr r2, [r2] ; PIC: ldr r3, [r2] -; PIC: LBB1_2 -; PIC: LCPI1_0: -; PIC-NOT: LCPI1_1: +; PIC: LBB0_2 +; PIC: LCPI0_0: +; PIC-NOT: LCPI0_1: ; PIC: .section %.pre = load i32* @GV, align 4 ; <i32> [#uses=1] br label %bb diff --git a/test/CodeGen/Thumb2/thumb2-branch.ll b/test/CodeGen/Thumb2/thumb2-branch.ll index 129838457b26..1d2af7a54745 100644 --- a/test/CodeGen/Thumb2/thumb2-branch.ll +++ b/test/CodeGen/Thumb2/thumb2-branch.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s -define void @f1(i32 %a, i32 %b, i32* %v) { +define i32 @f1(i32 %a, i32 %b, i32* %v) { entry: ; CHECK: f1: ; CHECK: bne LBB @@ -9,13 +9,13 @@ entry: cond_true: ; preds = %entry store i32 0, i32* %v - ret void + ret i32 0 return: ; preds = %entry - ret void + ret i32 1 } -define void @f2(i32 %a, i32 %b, i32* %v) { +define i32 @f2(i32 %a, i32 %b, i32* %v) { entry: ; CHECK: f2: ; CHECK: bge LBB @@ -24,13 +24,13 @@ entry: cond_true: ; preds = %entry store i32 0, i32* %v - ret void + ret i32 0 return: ; preds = %entry - ret void + ret i32 1 } -define void @f3(i32 %a, i32 %b, i32* %v) { +define i32 @f3(i32 %a, i32 %b, i32* %v) { entry: ; CHECK: f3: ; CHECK: bhs LBB @@ -39,13 +39,13 @@ entry: cond_true: ; preds = %entry store i32 0, i32* %v - ret void + ret i32 0 return: ; preds = %entry - ret void + ret i32 1 } -define void @f4(i32 %a, i32 %b, i32* %v) { +define i32 @f4(i32 %a, i32 %b, i32* %v) { entry: ; CHECK: f4: ; CHECK: blo LBB @@ -54,8 +54,8 @@ entry: cond_true: ; preds = %entry store i32 0, i32* %v - ret void + ret i32 0 return: ; preds = %entry - ret void + ret i32 1 } diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt3.ll b/test/CodeGen/Thumb2/thumb2-ifcvt3.ll index 496158c9a0c0..e465c00eae9f 100644 --- a/test/CodeGen/Thumb2/thumb2-ifcvt3.ll +++ b/test/CodeGen/Thumb2/thumb2-ifcvt3.ll @@ -23,7 +23,7 @@ bb52: ; preds = %newFuncRoot ; CHECK: movne ; CHECK: moveq ; CHECK: pop -; CHECK-NEXT: LBB1_1: +; CHECK-NEXT: LBB0_1: %0 = load i64* @posed, align 4 ; <i64> [#uses=3] %1 = sub i64 %0, %.reload78 ; <i64> [#uses=1] %2 = ashr i64 %1, 1 ; <i64> [#uses=3] diff --git a/test/CodeGen/X86/2007-01-08-InstrSched.ll b/test/CodeGen/X86/2007-01-08-InstrSched.ll index 58e186b4c4f8..ef19d72150a0 100644 --- a/test/CodeGen/X86/2007-01-08-InstrSched.ll +++ b/test/CodeGen/X86/2007-01-08-InstrSched.ll @@ -11,12 +11,12 @@ define float @foo(float %x) nounwind { %tmp14 = fadd float %tmp12, %tmp7 ret float %tmp14 -; CHECK: mulss LCPI1_0(%rip) -; CHECK: mulss LCPI1_1(%rip) +; CHECK: mulss LCPI0_0(%rip) +; CHECK: mulss LCPI0_1(%rip) ; CHECK: addss -; CHECK: mulss LCPI1_2(%rip) +; CHECK: mulss LCPI0_2(%rip) ; CHECK: addss -; CHECK: mulss LCPI1_3(%rip) +; CHECK: mulss LCPI0_3(%rip) ; CHECK: addss ; CHECK: ret } diff --git a/test/CodeGen/X86/2007-05-05-Personality.ll b/test/CodeGen/X86/2007-05-05-Personality.ll index c92783e5e4eb..a9b17d3b8f36 100644 --- a/test/CodeGen/X86/2007-05-05-Personality.ll +++ b/test/CodeGen/X86/2007-05-05-Personality.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i686-pc-linux-gnu -enable-eh -o - | grep zPL +; RUN: llc < %s -mtriple=i686-pc-linux-gnu -o - | grep zPL @error = external global i8 ; <i8*> [#uses=2] diff --git a/test/CodeGen/X86/2007-05-07-InvokeSRet.ll b/test/CodeGen/X86/2007-05-07-InvokeSRet.ll index a3ff2f60c8d7..ae49bd002208 100644 --- a/test/CodeGen/X86/2007-05-07-InvokeSRet.ll +++ b/test/CodeGen/X86/2007-05-07-InvokeSRet.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i686-pc-linux-gnu -enable-eh -disable-fp-elim | not grep {addl .12, %esp} +; RUN: llc < %s -mtriple=i686-pc-linux-gnu -disable-fp-elim | not grep {addl .12, %esp} ; PR1398 %struct.S = type { i32, i32 } diff --git a/test/CodeGen/X86/2007-06-04-tailmerge4.ll b/test/CodeGen/X86/2007-06-04-tailmerge4.ll index baf2377c5a02..d5ec0898b9a9 100644 --- a/test/CodeGen/X86/2007-06-04-tailmerge4.ll +++ b/test/CodeGen/X86/2007-06-04-tailmerge4.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -enable-eh -asm-verbose | grep invcont131 +; RUN: llc < %s -asm-verbose | grep invcont131 ; PR 1496: tail merge was incorrectly removing this block ; ModuleID = 'report.1.bc' diff --git a/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll b/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll index 56ee2a314990..c3403a0b4eeb 100644 --- a/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll +++ b/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin -enable-eh | grep {isNullOrNil].eh"} | count 2 +; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin | grep {isNullOrNil].eh"} | count 2 %struct.NSString = type { } %struct._objc__method_prototype_list = type opaque diff --git a/test/CodeGen/X86/2008-01-25-EmptyFunction.ll b/test/CodeGen/X86/2008-01-25-EmptyFunction.ll index 387645f74366..b936686798f0 100644 --- a/test/CodeGen/X86/2008-01-25-EmptyFunction.ll +++ b/test/CodeGen/X86/2008-01-25-EmptyFunction.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | grep {.byte 0} +; RUN: llc < %s -march=x86 | grep nop target triple = "i686-apple-darwin8" diff --git a/test/CodeGen/X86/2008-07-11-SpillerBug.ll b/test/CodeGen/X86/2008-07-11-SpillerBug.ll index 548b44db6d27..d0023b28c6dd 100644 --- a/test/CodeGen/X86/2008-07-11-SpillerBug.ll +++ b/test/CodeGen/X86/2008-07-11-SpillerBug.ll @@ -3,6 +3,7 @@ ; CHECK: andl $65534, % ; CHECK-NEXT: movl % +; CHECK-NEXT: movzwl ; CHECK-NEXT: movl $17 @g_5 = external global i16 ; <i16*> [#uses=2] diff --git a/test/CodeGen/X86/2008-10-16-SpillerBug.ll b/test/CodeGen/X86/2008-10-16-SpillerBug.ll index b8ca364d1798..87305a0b3116 100644 --- a/test/CodeGen/X86/2008-10-16-SpillerBug.ll +++ b/test/CodeGen/X86/2008-10-16-SpillerBug.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin | grep {andl.*7.*edi} +; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin -stats |& grep asm-printer | grep 41 +; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin | FileCheck %s %struct.XXDActiveTextureTargets = type { i64, i64, i64, i64, i64, i64 } %struct.XXDAlphaTest = type { float, i16, i8, i8 } @@ -61,11 +62,15 @@ define void @t(%struct.XXDState* %gldst, <4 x float>* %prgrm, <4 x float>** %buffs, %struct._XXVMConstants* %cnstn, %struct.YYToken* %pstrm, %struct.XXVMVPContext* %vmctx, %struct.XXVMTextures* %txtrs, %struct.XXVMVPStack* %vpstk, <4 x float>* %atr0, <4 x float>* %atr1, <4 x float>* %atr2, <4 x float>* %atr3, <4 x float>* %vtx0, <4 x float>* %vtx1, <4 x float>* %vtx2, <4 x float>* %vtx3, [4 x <4 x float>]* %tmpGbl, i32* %oldMsk, <4 x i32>* %adrGbl, i64 %key_token) nounwind { entry: +; CHECK: t: %0 = trunc i64 %key_token to i32 ; <i32> [#uses=1] %1 = getelementptr %struct.YYToken* %pstrm, i32 %0 ; <%struct.YYToken*> [#uses=5] br label %bb1132 bb51: ; preds = %bb1132 +; CHECK: .align 4 +; CHECK: xorl %ecx, %ecx +; CHECK: andl $7 %2 = getelementptr %struct.YYToken* %1, i32 %operation.0.rec, i32 0, i32 0 ; <i16*> [#uses=1] %3 = load i16* %2, align 1 ; <i16> [#uses=3] %4 = lshr i16 %3, 6 ; <i16> [#uses=1] diff --git a/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll b/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll index a6cabc4fd331..5eba9b9c3022 100644 --- a/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll +++ b/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll @@ -3,7 +3,7 @@ ; Make sure the copy after inline asm is not coalesced away. ; CHECK: ## InlineAsm End -; CHECK-NEXT: BB1_2: +; CHECK-NEXT: BB0_2: ; CHECK-NEXT: movl %esi, %eax diff --git a/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll b/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll index abbe97ac193e..69f644f5834b 100644 --- a/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll +++ b/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll @@ -4,7 +4,7 @@ ; rdar://6808032 ; CHECK: pextrw $14 -; CHECK-NEXT: movzbl +; CHECK-NEXT: shrl $8 ; CHECK-NEXT: (%ebp) ; CHECK-NEXT: pinsrw diff --git a/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll b/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll index 2fd42f40d891..1d1462075492 100644 --- a/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll +++ b/test/CodeGen/X86/2009-05-28-DAGCombineCrash.ll @@ -1,38 +1,15 @@ ; RUN: llc < %s -march=x86-64 - %struct.tempsym_t = type { i8*, i8*, i8*, i8*, i32, i32, i32, i32, i32 } - -define fastcc signext i8 @S_next_symbol(%struct.tempsym_t* %symptr) nounwind ssp { +define fastcc void @S_next_symbol(i448* %P) nounwind ssp { entry: - br label %bb116 - -bb: ; preds = %bb116 - switch i8 undef, label %bb14 [ - i8 9, label %bb116 - i8 32, label %bb116 - i8 10, label %bb116 - i8 13, label %bb116 - i8 12, label %bb116 - ] + br label %bb14 bb14: ; preds = %bb - br i1 undef, label %bb75, label %bb115 - -bb75: ; preds = %bb14 - %srcval16 = load i448* null, align 8 ; <i448> [#uses=1] + %srcval16 = load i448* %P, align 8 ; <i448> [#uses=1] %tmp = zext i32 undef to i448 ; <i448> [#uses=1] %tmp15 = shl i448 %tmp, 288 ; <i448> [#uses=1] %mask = and i448 %srcval16, -2135987035423586845985235064014169866455883682256196619149693890381755748887481053010428711403521 ; <i448> [#uses=1] %ins = or i448 %tmp15, %mask ; <i448> [#uses=1] - store i448 %ins, i448* null, align 8 - ret i8 1 - -bb115: ; preds = %bb14 - ret i8 1 - -bb116: ; preds = %bb, %bb, %bb, %bb, %bb, %entry - br i1 undef, label %bb, label %bb117 - -bb117: ; preds = %bb116 - ret i8 0 + store i448 %ins, i448* %P, align 8 + ret void } diff --git a/test/CodeGen/X86/2009-11-16-MachineLICM.ll b/test/CodeGen/X86/2009-11-16-MachineLICM.ll index 8f274df918d1..2ac688fd80af 100644 --- a/test/CodeGen/X86/2009-11-16-MachineLICM.ll +++ b/test/CodeGen/X86/2009-11-16-MachineLICM.ll @@ -15,7 +15,7 @@ bb.nph: ; preds = %entry br label %bb bb: ; preds = %bb, %bb.nph -; CHECK: LBB1_2: +; CHECK: LBB0_2: %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %bb ] ; <i64> [#uses=2] %tmp9 = shl i64 %indvar, 2 ; <i64> [#uses=4] %tmp1016 = or i64 %tmp9, 1 ; <i64> [#uses=1] diff --git a/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll b/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll index 26bf09c723a0..d33f93ea7b27 100644 --- a/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll +++ b/test/CodeGen/X86/2009-11-16-UnfoldMemOpBug.ll @@ -13,7 +13,7 @@ entry: br label %bb1 bb1: -; CHECK: LBB1_1: +; CHECK: LBB0_1: ; CHECK: movaps %xmm0, (%rsp) %tmp2 = phi i32 [ %tmp3, %bb1 ], [ 0, %entry ] call void @llvm.memcpy.i64(i8* %tmp1, i8* getelementptr inbounds ([28 x i8]* @str, i64 0, i64 0), i64 28, i32 1) diff --git a/test/CodeGen/X86/2010-01-07-UAMemFeature.ll b/test/CodeGen/X86/2010-01-07-UAMemFeature.ll index 3728f15d969c..bb24adb41817 100644 --- a/test/CodeGen/X86/2010-01-07-UAMemFeature.ll +++ b/test/CodeGen/X86/2010-01-07-UAMemFeature.ll @@ -6,6 +6,6 @@ target triple = "x86_64-unknown-linux-gnu" define <4 x float> @foo(<4 x float>* %P, <4 x float> %In) nounwind { %A = load <4 x float>* %P, align 4 - %B = add <4 x float> %A, %In + %B = fadd <4 x float> %A, %In ret <4 x float> %B } diff --git a/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll b/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll index 172e1c73d568..c6936362048b 100644 --- a/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll +++ b/test/CodeGen/X86/2010-01-08-Atomic64Bug.ll @@ -10,7 +10,7 @@ entry: ; CHECK: movl $1 ; CHECK: movl (%ebp), %eax ; CHECK: movl 4(%ebp), %edx -; CHECK: LBB1_1: +; CHECK: LBB0_1: ; CHECK-NOT: movl $1 ; CHECK-NOT: movl $0 ; CHECK: addl diff --git a/test/CodeGen/X86/2010-04-06-SSEDomainFixCrash.ll b/test/CodeGen/X86/2010-04-06-SSEDomainFixCrash.ll new file mode 100644 index 000000000000..ef1798d1ae43 --- /dev/null +++ b/test/CodeGen/X86/2010-04-06-SSEDomainFixCrash.ll @@ -0,0 +1,64 @@ +; RUN: llc < %s -O3 -relocation-model=pic -disable-fp-elim -mcpu=nocona +; +; This test case is reduced from Bullet. It crashes SSEDomainFix. +; +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" +target triple = "i386-apple-darwin10.0" + +declare i32 @_ZN11HullLibrary16CreateConvexHullERK8HullDescR10HullResult(i8*, i8* nocapture, i8* nocapture) ssp align 2 + +define void @_ZN17btSoftBodyHelpers4DrawEP10btSoftBodyP12btIDebugDrawi(i8* %psb, i8* %idraw, i32 %drawflags) ssp align 2 { +entry: + br i1 undef, label %bb92, label %bb58 + +bb58: ; preds = %entry + %0 = invoke i32 @_ZN11HullLibrary16CreateConvexHullERK8HullDescR10HullResult(i8* undef, i8* undef, i8* undef) + to label %invcont64 unwind label %lpad159 ; <i32> [#uses=0] + +invcont64: ; preds = %bb58 + br i1 undef, label %invcont65, label %bb.i.i + +bb.i.i: ; preds = %invcont64 + %1 = load <4 x float>* undef, align 16 ; <<4 x float>> [#uses=5] + br i1 undef, label %bb.nph.i.i, label %invcont65 + +bb.nph.i.i: ; preds = %bb.i.i + %tmp22.i.i = bitcast <4 x float> %1 to i128 ; <i128> [#uses=1] + %tmp23.i.i = trunc i128 %tmp22.i.i to i32 ; <i32> [#uses=1] + %2 = bitcast i32 %tmp23.i.i to float ; <float> [#uses=1] + %tmp6.i = extractelement <4 x float> %1, i32 1 ; <float> [#uses=1] + %tmp2.i = extractelement <4 x float> %1, i32 2 ; <float> [#uses=1] + br label %bb1.i.i + +bb1.i.i: ; preds = %bb1.i.i, %bb.nph.i.i + %.tmp6.0.i.i = phi float [ %tmp2.i, %bb.nph.i.i ], [ %5, %bb1.i.i ] ; <float> [#uses=1] + %.tmp5.0.i.i = phi float [ %tmp6.i, %bb.nph.i.i ], [ %4, %bb1.i.i ] ; <float> [#uses=1] + %.tmp.0.i.i = phi float [ %2, %bb.nph.i.i ], [ %3, %bb1.i.i ] ; <float> [#uses=1] + %3 = fadd float %.tmp.0.i.i, undef ; <float> [#uses=2] + %4 = fadd float %.tmp5.0.i.i, undef ; <float> [#uses=2] + %5 = fadd float %.tmp6.0.i.i, undef ; <float> [#uses=2] + br i1 undef, label %bb2.return.loopexit_crit_edge.i.i, label %bb1.i.i + +bb2.return.loopexit_crit_edge.i.i: ; preds = %bb1.i.i + %tmp8.i = insertelement <4 x float> %1, float %3, i32 0 ; <<4 x float>> [#uses=1] + %tmp4.i = insertelement <4 x float> %tmp8.i, float %4, i32 1 ; <<4 x float>> [#uses=1] + %tmp.i = insertelement <4 x float> %tmp4.i, float %5, i32 2 ; <<4 x float>> [#uses=1] + br label %invcont65 + +invcont65: ; preds = %bb2.return.loopexit_crit_edge.i.i, %bb.i.i, %invcont64 + %.0.i = phi <4 x float> [ %tmp.i, %bb2.return.loopexit_crit_edge.i.i ], [ undef, %invcont64 ], [ %1, %bb.i.i ] ; <<4 x float>> [#uses=1] + %tmp15.i = extractelement <4 x float> %.0.i, i32 2 ; <float> [#uses=1] + %6 = fmul float %tmp15.i, undef ; <float> [#uses=1] + br label %bb.i265 + +bb.i265: ; preds = %bb.i265, %invcont65 + %7 = fsub float 0.000000e+00, %6 ; <float> [#uses=1] + store float %7, float* undef, align 4 + br label %bb.i265 + +bb92: ; preds = %entry + unreachable + +lpad159: ; preds = %bb58 + unreachable +} diff --git a/test/CodeGen/X86/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/X86/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 000000000000..76cc1a497d3d --- /dev/null +++ b/test/CodeGen/X86/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,34 @@ +; RUN: llc -O0 -march=x86 -asm-verbose < %s | FileCheck %s +; RUN: llc -O0 -march=x86-64 -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/X86/2010-04-08-CoalescerBug.ll b/test/CodeGen/X86/2010-04-08-CoalescerBug.ll new file mode 100644 index 000000000000..1c7c28c68e9f --- /dev/null +++ b/test/CodeGen/X86/2010-04-08-CoalescerBug.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; rdar://7842028 + +; Do not delete partially dead copy instructions. +; %RDI<def,dead> = MOV64rr %RAX<kill>, %EDI<imp-def> +; REP_MOVSD %ECX<imp-def,dead>, %EDI<imp-def,dead>, %ESI<imp-def,dead>, %ECX<imp-use,kill>, %EDI<imp-use,kill>, %ESI<imp-use,kill> + + +%struct.F = type { %struct.FC*, i32, i32, i8, i32, i32, i32 } +%struct.FC = type { [10 x i8], [32 x i32], %struct.FC*, i32 } + +define void @t(%struct.F* %this) nounwind { +entry: +; CHECK: t: +; CHECK: addq $12, %rsi + %BitValueArray = alloca [32 x i32], align 4 + %tmp2 = getelementptr inbounds %struct.F* %this, i64 0, i32 0 + %tmp3 = load %struct.FC** %tmp2, align 8 + %tmp4 = getelementptr inbounds %struct.FC* %tmp3, i64 0, i32 1, i64 0 + %tmp5 = bitcast [32 x i32]* %BitValueArray to i8* + %tmp6 = bitcast i32* %tmp4 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp5, i8* %tmp6, i64 128, i32 4, i1 false) + unreachable +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind diff --git a/test/CodeGen/X86/2010-04-13-AnalyzeBranchCrash.ll b/test/CodeGen/X86/2010-04-13-AnalyzeBranchCrash.ll new file mode 100644 index 000000000000..fadbd2191989 --- /dev/null +++ b/test/CodeGen/X86/2010-04-13-AnalyzeBranchCrash.ll @@ -0,0 +1,42 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=core2 +; rdar://7857830 + +%0 = type opaque +%1 = type opaque + +define void @t(%0* %self, i8* nocapture %_cmd, %1* %scroller, i32 %hitPart, float %multiplier) nounwind optsize ssp { +entry: + switch i32 %hitPart, label %if.else [ + i32 7, label %if.then + i32 8, label %if.then + ] + +if.then: ; preds = %entry, %entry + %tmp69 = load float* null, align 4 ; <float> [#uses=1] + %cmp19 = icmp eq %1* null, %scroller ; <i1> [#uses=2] + %cond = select i1 %cmp19, float %tmp69, float 0.000000e+00 ; <float> [#uses=1] + %call36 = call i64 bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i64 (i8*, i8*)*)(i8* undef, i8* undef) nounwind optsize ; <i64> [#uses=2] + br i1 %cmp19, label %cond.true32, label %cond.false39 + +cond.true32: ; preds = %if.then + %sroa.store.elt68 = lshr i64 %call36, 32 ; <i64> [#uses=1] + %0 = trunc i64 %sroa.store.elt68 to i32 ; <i32> [#uses=1] + br label %cond.end47 + +cond.false39: ; preds = %if.then + %1 = trunc i64 %call36 to i32 ; <i32> [#uses=1] + br label %cond.end47 + +cond.end47: ; preds = %cond.false39, %cond.true32 + %cond48.in = phi i32 [ %0, %cond.true32 ], [ %1, %cond.false39 ] ; <i32> [#uses=1] + %cond48 = bitcast i32 %cond48.in to float ; <float> [#uses=1] + %div = fdiv float %cond, undef ; <float> [#uses=1] + %div58 = fdiv float %div, %cond48 ; <float> [#uses=1] + call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, float)*)(i8* undef, i8* undef, float %div58) nounwind optsize + ret void + +if.else: ; preds = %entry + ret void +} + +declare i8* @objc_msgSend(i8*, i8*, ...) diff --git a/test/CodeGen/X86/2010-04-21-CoalescerBug.ll b/test/CodeGen/X86/2010-04-21-CoalescerBug.ll new file mode 100644 index 000000000000..d5987645cfca --- /dev/null +++ b/test/CodeGen/X86/2010-04-21-CoalescerBug.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin +; rdar://7886733 + +%struct.CMTime = type <{ i64, i32, i32, i64 }> +%struct.CMTimeMapping = type { %struct.CMTimeRange, %struct.CMTimeRange } +%struct.CMTimeRange = type { %struct.CMTime, %struct.CMTime } + +define void @t(%struct.CMTimeMapping* noalias nocapture sret %agg.result) nounwind optsize ssp { +entry: + %agg.result1 = bitcast %struct.CMTimeMapping* %agg.result to i8* ; <i8*> [#uses=1] + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %agg.result1, i8* null, i64 96, i32 4, i1 false) + ret void +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind diff --git a/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll b/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll new file mode 100644 index 000000000000..4cd3be35e820 --- /dev/null +++ b/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll @@ -0,0 +1,45 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | FileCheck %s + +define void @ti8(double %a, double %b) nounwind { +entry: + %tmp1 = bitcast double %a to <8 x i8> +; CHECK: movdq2q + %tmp2 = bitcast double %b to <8 x i8> +; CHECK: movdq2q + %tmp3 = add <8 x i8> %tmp1, %tmp2 + store <8 x i8> %tmp3, <8 x i8>* null + ret void +} + +define void @ti16(double %a, double %b) nounwind { +entry: + %tmp1 = bitcast double %a to <4 x i16> +; CHECK: movdq2q + %tmp2 = bitcast double %b to <4 x i16> +; CHECK: movdq2q + %tmp3 = add <4 x i16> %tmp1, %tmp2 + store <4 x i16> %tmp3, <4 x i16>* null + ret void +} + +define void @ti32(double %a, double %b) nounwind { +entry: + %tmp1 = bitcast double %a to <2 x i32> +; CHECK: movdq2q + %tmp2 = bitcast double %b to <2 x i32> +; CHECK: movdq2q + %tmp3 = add <2 x i32> %tmp1, %tmp2 + store <2 x i32> %tmp3, <2 x i32>* null + ret void +} + +define void @ti64(double %a, double %b) nounwind { +entry: + %tmp1 = bitcast double %a to <1 x i64> +; CHECK: movdq2q + %tmp2 = bitcast double %b to <1 x i64> +; CHECK: movdq2q + %tmp3 = add <1 x i64> %tmp1, %tmp2 + store <1 x i64> %tmp3, <1 x i64>* null + ret void +} diff --git a/test/CodeGen/X86/2010-04-29-CoalescerCrash.ll b/test/CodeGen/X86/2010-04-29-CoalescerCrash.ll new file mode 100644 index 000000000000..a22f38ae3baa --- /dev/null +++ b/test/CodeGen/X86/2010-04-29-CoalescerCrash.ll @@ -0,0 +1,142 @@ +; RUN: llc < %s -relocation-model=pic -disable-fp-elim -verify-machineinstrs +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +define void @_ZN12_GLOBAL__N_113SPUAsmPrinter15EmitInstructionEPKN4llvm12MachineInstrE(i8* %this, i8* %MI) nounwind inlinehint align 2 { +entry: + br i1 undef, label %"3.i", label %"4.i" + +"3.i": ; preds = %entry + unreachable + +"4.i": ; preds = %entry + switch i32 undef, label %_ZN12_GLOBAL__N_113SPUAsmPrinter16printInstructionEPKN4llvm12MachineInstrERNS1_11raw_ostreamE.exit [ + i32 1, label %"5.i" + i32 2, label %"6.i" + i32 3, label %"7.i" + i32 4, label %"8.i" + i32 5, label %"9.i" + ] + +"5.i": ; preds = %"4.i" + unreachable + +"6.i": ; preds = %"4.i" + switch i32 undef, label %"11.i" [ + i32 1, label %"12.i" + i32 2, label %"13.i" + i32 3, label %_ZN12_GLOBAL__N_113SPUAsmPrinter16printInstructionEPKN4llvm12MachineInstrERNS1_11raw_ostreamE.exit + i32 4, label %"14.i" + ] + +"7.i": ; preds = %"4.i" + unreachable + +"8.i": ; preds = %"4.i" + unreachable + +"9.i": ; preds = %"4.i" + unreachable + +"11.i": ; preds = %"6.i" + switch i32 undef, label %"15.i" [ + i32 1, label %"16.i" + i32 2, label %"17.i" + i32 3, label %"18.i" + i32 4, label %"19.i" + i32 5, label %"20.i" + i32 6, label %"21.i" + i32 7, label %"24.i" + i32 8, label %"27.i" + i32 9, label %"28.i" + i32 10, label %"29.i" + i32 11, label %"30.i" + i32 12, label %"31.i" + i32 13, label %"32.i" + i32 14, label %"39.i" + ] + +"12.i": ; preds = %"6.i" + unreachable + +"13.i": ; preds = %"6.i" + unreachable + +"14.i": ; preds = %"6.i" + unreachable + +"15.i": ; preds = %"11.i" + unreachable + +"16.i": ; preds = %"11.i" + unreachable + +"17.i": ; preds = %"11.i" + unreachable + +"18.i": ; preds = %"11.i" + unreachable + +"19.i": ; preds = %"11.i" + unreachable + +"20.i": ; preds = %"11.i" + unreachable + +"21.i": ; preds = %"11.i" + br i1 undef, label %"22.i", label %"23.i" + +"22.i": ; preds = %"21.i" + unreachable + +"23.i": ; preds = %"21.i" + unreachable + +"24.i": ; preds = %"11.i" + unreachable + +"27.i": ; preds = %"11.i" + unreachable + +"28.i": ; preds = %"11.i" + unreachable + +"29.i": ; preds = %"11.i" + unreachable + +"30.i": ; preds = %"11.i" + unreachable + +"31.i": ; preds = %"11.i" + unreachable + +"32.i": ; preds = %"11.i" + unreachable + +"39.i": ; preds = %"11.i" + br i1 undef, label %"41.i", label %"40.i" + +"40.i": ; preds = %"39.i" + unreachable + +"41.i": ; preds = %"39.i" + %0 = call i64 @_ZNK4llvm14MachineOperand6getImmEv(i8 undef) nounwind inlinehint ; <i64> [#uses=1] + %1 = trunc i64 %0 to i16 ; <i16> [#uses=1] + br i1 undef, label %"42.i", label %"43.i" + +"42.i": ; preds = %"41.i" + unreachable + +"43.i": ; preds = %"41.i" + %2 = and i16 %1, -16 ; <i16> [#uses=1] + %3 = sext i16 %2 to i64 ; <i64> [#uses=1] + %4 = call i8 @_ZN4llvm11raw_ostreamlsEl(i8 undef, i64 %3) nounwind ; <i8> [#uses=0] + unreachable + +_ZN12_GLOBAL__N_113SPUAsmPrinter16printInstructionEPKN4llvm12MachineInstrERNS1_11raw_ostreamE.exit: ; preds = %"6.i", %"4.i" + ret void +} + +declare i64 @_ZNK4llvm14MachineOperand6getImmEv(i8) nounwind inlinehint align 2 + +declare i8 @_ZN4llvm11raw_ostreamlsEl(i8, i64) diff --git a/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll b/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll new file mode 100644 index 000000000000..f5048afd7cc2 --- /dev/null +++ b/test/CodeGen/X86/2010-04-30-LocalAlloc-LandingPad.ll @@ -0,0 +1,143 @@ +; RUN: llc < %s -O0 -regalloc=local -relocation-model=pic -disable-fp-elim | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" +target triple = "i386-apple-darwin10.0.0" + +%struct.S = type { [2 x i8*] } + +@_ZTIi = external constant i8* ; <i8**> [#uses=1] +@.str = internal constant [4 x i8] c"%p\0A\00" ; <[4 x i8]*> [#uses=1] +@llvm.used = appending global [1 x i8*] [i8* bitcast (i8* (%struct.S*, i32, %struct.S*)* @_Z4test1SiS_ to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] + +; Verify that %esi gets spilled before the call. +; CHECK: Z4test1SiS +; CHECK: movl %esi,{{.*}}(%ebp) +; CHECK: call __Z6throwsv + +define i8* @_Z4test1SiS_(%struct.S* byval %s1, i32 %n, %struct.S* byval %s2) ssp { +entry: + %retval = alloca i8*, align 4 ; <i8**> [#uses=2] + %n.addr = alloca i32, align 4 ; <i32*> [#uses=1] + %_rethrow = alloca i8* ; <i8**> [#uses=4] + %0 = alloca i32, align 4 ; <i32*> [#uses=1] + %cleanup.dst = alloca i32 ; <i32*> [#uses=3] + %cleanup.dst7 = alloca i32 ; <i32*> [#uses=6] + store i32 %n, i32* %n.addr + invoke void @_Z6throwsv() + to label %invoke.cont unwind label %try.handler + +invoke.cont: ; preds = %entry + store i32 1, i32* %cleanup.dst7 + br label %finally + +terminate.handler: ; preds = %match.end + %exc = call i8* @llvm.eh.exception() ; <i8*> [#uses=1] + %1 = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exc, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i32 1) ; <i32> [#uses=0] + call void @_ZSt9terminatev() noreturn nounwind + unreachable + +try.handler: ; preds = %entry + %exc1 = call i8* @llvm.eh.exception() ; <i8*> [#uses=3] + %selector = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exc1, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* bitcast (i8** @_ZTIi to i8*), i8* null) ; <i32> [#uses=1] + %2 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) ; <i32> [#uses=1] + %3 = icmp eq i32 %selector, %2 ; <i1> [#uses=1] + br i1 %3, label %match, label %catch.next + +match: ; preds = %try.handler + %4 = call i8* @__cxa_begin_catch(i8* %exc1) ; <i8*> [#uses=1] + %5 = bitcast i8* %4 to i32* ; <i32*> [#uses=1] + %6 = load i32* %5 ; <i32> [#uses=1] + store i32 %6, i32* %0 + %call = invoke i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), %struct.S* %s2) + to label %invoke.cont2 unwind label %match.handler ; <i32> [#uses=0] + +invoke.cont2: ; preds = %match + store i32 1, i32* %cleanup.dst + br label %match.end + +match.handler: ; preds = %match + %exc3 = call i8* @llvm.eh.exception() ; <i8*> [#uses=2] + %7 = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exc3, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i32 0) ; <i32> [#uses=0] + store i8* %exc3, i8** %_rethrow + store i32 2, i32* %cleanup.dst + br label %match.end + +cleanup.pad: ; preds = %cleanup.switch + store i32 1, i32* %cleanup.dst7 + br label %finally + +cleanup.pad4: ; preds = %cleanup.switch + store i32 2, i32* %cleanup.dst7 + br label %finally + +match.end: ; preds = %match.handler, %invoke.cont2 + invoke void @__cxa_end_catch() + to label %invoke.cont5 unwind label %terminate.handler + +invoke.cont5: ; preds = %match.end + br label %cleanup.switch + +cleanup.switch: ; preds = %invoke.cont5 + %tmp = load i32* %cleanup.dst ; <i32> [#uses=1] + switch i32 %tmp, label %cleanup.end [ + i32 1, label %cleanup.pad + i32 2, label %cleanup.pad4 + ] + +cleanup.end: ; preds = %cleanup.switch + %exc6 = call i8* @llvm.eh.exception() ; <i8*> [#uses=1] + store i8* %exc6, i8** %_rethrow + store i32 2, i32* %cleanup.dst7 + br label %finally + +catch.next: ; preds = %try.handler + store i8* %exc1, i8** %_rethrow + store i32 2, i32* %cleanup.dst7 + br label %finally + +finally: ; preds = %catch.next, %cleanup.end, %cleanup.pad4, %cleanup.pad, %invoke.cont + br label %cleanup.switch9 + +cleanup.switch9: ; preds = %finally + %tmp8 = load i32* %cleanup.dst7 ; <i32> [#uses=1] + switch i32 %tmp8, label %cleanup.end10 [ + i32 1, label %finally.end + i32 2, label %finally.throw + ] + +cleanup.end10: ; preds = %cleanup.switch9 + br label %finally.end + +finally.throw: ; preds = %cleanup.switch9 + %8 = load i8** %_rethrow ; <i8*> [#uses=1] + call void @_Unwind_Resume_or_Rethrow(i8* %8) + unreachable + +finally.end: ; preds = %cleanup.end10, %cleanup.switch9 + %tmp11 = getelementptr inbounds %struct.S* %s1, i32 0, i32 0 ; <[2 x i8*]*> [#uses=1] + %arraydecay = getelementptr inbounds [2 x i8*]* %tmp11, i32 0, i32 0 ; <i8**> [#uses=1] + %arrayidx = getelementptr inbounds i8** %arraydecay, i32 1 ; <i8**> [#uses=1] + %tmp12 = load i8** %arrayidx ; <i8*> [#uses=1] + store i8* %tmp12, i8** %retval + %9 = load i8** %retval ; <i8*> [#uses=1] + ret i8* %9 +} + +declare void @_Z6throwsv() ssp + +declare i32 @__gxx_personality_v0(...) + +declare i8* @llvm.eh.exception() nounwind readonly + +declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind + +declare void @_ZSt9terminatev() + +declare void @_Unwind_Resume_or_Rethrow(i8*) + +declare i32 @llvm.eh.typeid.for(i8*) nounwind + +declare i8* @__cxa_begin_catch(i8*) + +declare i32 @printf(i8*, ...) + +declare void @__cxa_end_catch() diff --git a/test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll b/test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll new file mode 100644 index 000000000000..323925c7ff68 --- /dev/null +++ b/test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll @@ -0,0 +1,33 @@ +; RUN: llc < %s | FileCheck %s +; PR6941 +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +define i32 @snd_xbytes(i32 %v, i32 %from, i32 %to) nounwind readnone ssp { +entry: + %cmp19 = icmp eq i32 %to, 0 ; <i1> [#uses=1] + br i1 %cmp19, label %while.end, label %while.cond + +while.cond: ; preds = %entry, %while.cond + %y.021 = phi i32 [ %rem, %while.cond ], [ %to, %entry ] ; <i32> [#uses=3] + %x.020 = phi i32 [ %y.021, %while.cond ], [ %from, %entry ] ; <i32> [#uses=1] + %rem = urem i32 %x.020, %y.021 ; <i32> [#uses=2] + %cmp = icmp eq i32 %rem, 0 ; <i1> [#uses=1] + br i1 %cmp, label %while.end, label %while.cond + +while.end: ; preds = %while.cond, %entry + %x.0.lcssa = phi i32 [ %from, %entry ], [ %y.021, %while.cond ] ; <i32> [#uses=2] + %div = udiv i32 %from, %x.0.lcssa ; <i32> [#uses=1] + %div11 = udiv i32 %to, %x.0.lcssa ; <i32> [#uses=1] + %conv = zext i32 %v to i64 ; <i64> [#uses=1] + %conv14 = zext i32 %div11 to i64 ; <i64> [#uses=1] +; Verify that we don't clobber %eax after putting the imulq result in %rax +; CHECK: imulq %r{{.}}x, %r[[RES:.]]x +; CHECK-NOT: movl {{.*}}, %e[[RES]]x +; CHECK: div + %mul = mul i64 %conv14, %conv ; <i64> [#uses=1] + %conv16 = zext i32 %div to i64 ; <i64> [#uses=1] + %div17 = udiv i64 %mul, %conv16 ; <i64> [#uses=1] + %conv18 = trunc i64 %div17 to i32 ; <i32> [#uses=1] + ret i32 %conv18 +} diff --git a/test/CodeGen/X86/MachineSink-CritEdge.ll b/test/CodeGen/X86/MachineSink-CritEdge.ll new file mode 100644 index 000000000000..74a1049772a0 --- /dev/null +++ b/test/CodeGen/X86/MachineSink-CritEdge.ll @@ -0,0 +1,58 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +define i32 @f(i32 %x) nounwind ssp { +entry: + %shl.i = shl i32 %x, 12 + %neg.i = xor i32 %shl.i, -1 + %add.i = add nsw i32 %neg.i, %x + %shr.i = ashr i32 %add.i, 22 + %xor.i = xor i32 %shr.i, %add.i + %shl5.i = shl i32 %xor.i, 13 + %neg6.i = xor i32 %shl5.i, -1 + %add8.i = add nsw i32 %xor.i, %neg6.i + %shr10.i = ashr i32 %add8.i, 8 + %xor12.i = xor i32 %shr10.i, %add8.i + %add16.i = mul i32 %xor12.i, 9 + %shr18.i = ashr i32 %add16.i, 15 + %xor20.i = xor i32 %shr18.i, %add16.i + %shl22.i = shl i32 %xor20.i, 27 + %neg23.i = xor i32 %shl22.i, -1 + %add25.i = add nsw i32 %xor20.i, %neg23.i + %shr27.i = ashr i32 %add25.i, 31 + %rem = srem i32 %x, 7 + %cmp = icmp eq i32 %rem, 3 + br i1 %cmp, label %land.lhs.true, label %do.body.preheader + +land.lhs.true: + %call3 = tail call i32 @g(i32 %x) nounwind + %cmp4 = icmp eq i32 %call3, 10 + br i1 %cmp4, label %do.body.preheader, label %if.then + +; %shl.i should be sinked all the way down to do.body.preheader, but not into the loop. +; CHECK: do.body.preheader +; CHECK-NOT: do.body +; CHECK: shll $12 + +do.body.preheader: + %xor29.i = xor i32 %shr27.i, %add25.i + br label %do.body + +if.then: + %add = add nsw i32 %x, 11 + ret i32 %add + +do.body: + %x.addr.1 = phi i32 [ %add9, %do.body ], [ %x, %do.body.preheader ] + %xor = xor i32 %xor29.i, %x.addr.1 + %add9 = add nsw i32 %xor, %x.addr.1 + %and = and i32 %add9, 13 + %tobool = icmp eq i32 %and, 0 + br i1 %tobool, label %if.end, label %do.body + +if.end: + ret i32 %add9 +} + +declare i32 @g(i32) diff --git a/test/CodeGen/X86/abi-isel.ll b/test/CodeGen/X86/abi-isel.ll index 920873813e45..23042b6eff3e 100644 --- a/test/CodeGen/X86/abi-isel.ll +++ b/test/CodeGen/X86/abi-isel.ll @@ -72,12 +72,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo00: -; DARWIN-32-PIC: call L1$pb -; DARWIN-32-PIC-NEXT: L1$pb: +; DARWIN-32-PIC: call L0$pb +; DARWIN-32-PIC-NEXT: L0$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L1$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L0$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L1$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L0$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -144,12 +144,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _fxo00: -; DARWIN-32-PIC: call L2$pb -; DARWIN-32-PIC-NEXT: L2$pb: +; DARWIN-32-PIC: call L1$pb +; DARWIN-32-PIC-NEXT: L1$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L2$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L1$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L2$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L1$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -208,11 +208,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo01: -; DARWIN-32-PIC: call L3$pb -; DARWIN-32-PIC-NEXT: L3$pb: +; DARWIN-32-PIC: call L2$pb +; DARWIN-32-PIC-NEXT: L2$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L3$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L3$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L2$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L2$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -268,11 +268,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _fxo01: -; DARWIN-32-PIC: call L4$pb -; DARWIN-32-PIC-NEXT: L4$pb: +; DARWIN-32-PIC: call L3$pb +; DARWIN-32-PIC-NEXT: L3$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L4$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L4$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L3$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L3$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -342,12 +342,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo02: -; DARWIN-32-PIC: call L5$pb -; DARWIN-32-PIC-NEXT: L5$pb: +; DARWIN-32-PIC: call L4$pb +; DARWIN-32-PIC-NEXT: L4$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L5$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L4$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L5$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L4$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -424,12 +424,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _fxo02: -; DARWIN-32-PIC: call L6$pb -; DARWIN-32-PIC-NEXT: L6$pb: +; DARWIN-32-PIC: call L5$pb +; DARWIN-32-PIC-NEXT: L5$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L6$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L5$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L6$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L5$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -497,11 +497,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo03: -; DARWIN-32-PIC: call L7$pb -; DARWIN-32-PIC-NEXT: L7$pb: +; DARWIN-32-PIC: call L6$pb +; DARWIN-32-PIC-NEXT: L6$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _dsrc-L7$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _ddst-L7$pb(%eax) +; DARWIN-32-PIC-NEXT: movl _dsrc-L6$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _ddst-L6$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo03: @@ -551,11 +551,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo04: -; DARWIN-32-PIC: call L8$pb -; DARWIN-32-PIC-NEXT: L8$pb: +; DARWIN-32-PIC: call L7$pb +; DARWIN-32-PIC-NEXT: L7$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ddst-L8$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L8$pb(%eax) +; DARWIN-32-PIC-NEXT: leal _ddst-L7$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L7$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo04: @@ -619,11 +619,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo05: -; DARWIN-32-PIC: call L9$pb -; DARWIN-32-PIC-NEXT: L9$pb: +; DARWIN-32-PIC: call L8$pb +; DARWIN-32-PIC-NEXT: L8$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _dsrc-L9$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _dptr-L9$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _dsrc-L8$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl _dptr-L8$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -682,11 +682,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo06: -; DARWIN-32-PIC: call L10$pb -; DARWIN-32-PIC-NEXT: L10$pb: +; DARWIN-32-PIC: call L9$pb +; DARWIN-32-PIC-NEXT: L9$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _lsrc-L10$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _ldst-L10$pb(%eax) +; DARWIN-32-PIC-NEXT: movl _lsrc-L9$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _ldst-L9$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo06: @@ -735,11 +735,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo07: -; DARWIN-32-PIC: call L11$pb -; DARWIN-32-PIC-NEXT: L11$pb: +; DARWIN-32-PIC: call L10$pb +; DARWIN-32-PIC-NEXT: L10$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ldst-L11$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L11$pb(%eax) +; DARWIN-32-PIC-NEXT: leal _ldst-L10$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L10$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo07: @@ -801,11 +801,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo08: -; DARWIN-32-PIC: call L12$pb -; DARWIN-32-PIC-NEXT: L12$pb: +; DARWIN-32-PIC: call L11$pb +; DARWIN-32-PIC-NEXT: L11$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _lsrc-L12$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _lptr-L12$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _lsrc-L11$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl _lptr-L11$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -868,12 +868,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux00: -; DARWIN-32-PIC: call L13$pb -; DARWIN-32-PIC-NEXT: L13$pb: +; DARWIN-32-PIC: call L12$pb +; DARWIN-32-PIC-NEXT: L12$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L13$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L12$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L13$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L12$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -939,12 +939,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qxx00: -; DARWIN-32-PIC: call L14$pb -; DARWIN-32-PIC-NEXT: L14$pb: +; DARWIN-32-PIC: call L13$pb +; DARWIN-32-PIC-NEXT: L13$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L14$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L13$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L14$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L13$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1005,12 +1005,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux01: -; DARWIN-32-PIC: call L15$pb -; DARWIN-32-PIC-NEXT: L15$pb: +; DARWIN-32-PIC: call L14$pb +; DARWIN-32-PIC-NEXT: L14$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L15$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L14$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: addl $64, %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L15$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L14$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1071,12 +1071,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qxx01: -; DARWIN-32-PIC: call L16$pb -; DARWIN-32-PIC-NEXT: L16$pb: +; DARWIN-32-PIC: call L15$pb +; DARWIN-32-PIC-NEXT: L15$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L16$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L15$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: addl $64, %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L16$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L15$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1150,12 +1150,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux02: -; DARWIN-32-PIC: call L17$pb -; DARWIN-32-PIC-NEXT: L17$pb: +; DARWIN-32-PIC: call L16$pb +; DARWIN-32-PIC-NEXT: L16$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L17$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L16$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L17$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L16$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1233,12 +1233,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qxx02: -; DARWIN-32-PIC: call L18$pb -; DARWIN-32-PIC-NEXT: L18$pb: +; DARWIN-32-PIC: call L17$pb +; DARWIN-32-PIC-NEXT: L17$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L18$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L17$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L18$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L17$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1306,11 +1306,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux03: -; DARWIN-32-PIC: call L19$pb -; DARWIN-32-PIC-NEXT: L19$pb: +; DARWIN-32-PIC: call L18$pb +; DARWIN-32-PIC-NEXT: L18$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_dsrc-L19$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, (_ddst-L19$pb)+64(%eax) +; DARWIN-32-PIC-NEXT: movl (_dsrc-L18$pb)+64(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, (_ddst-L18$pb)+64(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux03: @@ -1361,11 +1361,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux04: -; DARWIN-32-PIC: call L20$pb -; DARWIN-32-PIC-NEXT: L20$pb: +; DARWIN-32-PIC: call L19$pb +; DARWIN-32-PIC-NEXT: L19$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ddst-L20$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L20$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ddst-L19$pb)+64(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L19$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux04: @@ -1430,11 +1430,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux05: -; DARWIN-32-PIC: call L21$pb -; DARWIN-32-PIC-NEXT: L21$pb: +; DARWIN-32-PIC: call L20$pb +; DARWIN-32-PIC-NEXT: L20$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_dsrc-L21$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _dptr-L21$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_dsrc-L20$pb)+64(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl _dptr-L20$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1493,11 +1493,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux06: -; DARWIN-32-PIC: call L22$pb -; DARWIN-32-PIC-NEXT: L22$pb: +; DARWIN-32-PIC: call L21$pb +; DARWIN-32-PIC-NEXT: L21$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_lsrc-L22$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, (_ldst-L22$pb)+64(%eax) +; DARWIN-32-PIC-NEXT: movl (_lsrc-L21$pb)+64(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, (_ldst-L21$pb)+64(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux06: @@ -1546,11 +1546,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux07: -; DARWIN-32-PIC: call L23$pb -; DARWIN-32-PIC-NEXT: L23$pb: +; DARWIN-32-PIC: call L22$pb +; DARWIN-32-PIC-NEXT: L22$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ldst-L23$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L23$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ldst-L22$pb)+64(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L22$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux07: @@ -1613,11 +1613,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux08: -; DARWIN-32-PIC: call L24$pb -; DARWIN-32-PIC-NEXT: L24$pb: +; DARWIN-32-PIC: call L23$pb +; DARWIN-32-PIC-NEXT: L23$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_lsrc-L24$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _lptr-L24$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_lsrc-L23$pb)+64(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl _lptr-L23$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1686,13 +1686,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind00: -; DARWIN-32-PIC: call L25$pb -; DARWIN-32-PIC-NEXT: L25$pb: +; DARWIN-32-PIC: call L24$pb +; DARWIN-32-PIC-NEXT: L24$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L25$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L24$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L25$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L24$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -1764,13 +1764,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ixd00: -; DARWIN-32-PIC: call L26$pb -; DARWIN-32-PIC-NEXT: L26$pb: +; DARWIN-32-PIC: call L25$pb +; DARWIN-32-PIC-NEXT: L25$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L26$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L25$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L26$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L25$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -1840,13 +1840,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind01: -; DARWIN-32-PIC: call L27$pb -; DARWIN-32-PIC-NEXT: L27$pb: +; DARWIN-32-PIC: call L26$pb +; DARWIN-32-PIC-NEXT: L26$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx ; DARWIN-32-PIC-NEXT: shll $2, %ecx -; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L27$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L27$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L26$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L26$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -1916,13 +1916,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ixd01: -; DARWIN-32-PIC: call L28$pb -; DARWIN-32-PIC-NEXT: L28$pb: +; DARWIN-32-PIC: call L27$pb +; DARWIN-32-PIC-NEXT: L27$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx ; DARWIN-32-PIC-NEXT: shll $2, %ecx -; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-L28$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L28$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-L27$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L27$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -2001,13 +2001,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind02: -; DARWIN-32-PIC: call L29$pb -; DARWIN-32-PIC-NEXT: L29$pb: +; DARWIN-32-PIC: call L28$pb +; DARWIN-32-PIC-NEXT: L28$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L29$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L28$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L29$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L28$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -2090,13 +2090,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ixd02: -; DARWIN-32-PIC: call L30$pb -; DARWIN-32-PIC-NEXT: L30$pb: +; DARWIN-32-PIC: call L29$pb +; DARWIN-32-PIC-NEXT: L29$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L30$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L29$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L30$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L29$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -2170,12 +2170,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind03: -; DARWIN-32-PIC: call L31$pb -; DARWIN-32-PIC-NEXT: L31$pb: +; DARWIN-32-PIC: call L30$pb +; DARWIN-32-PIC-NEXT: L30$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _dsrc-L31$pb(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, _ddst-L31$pb(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: movl _dsrc-L30$pb(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl %edx, _ddst-L30$pb(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind03: @@ -2242,12 +2242,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind04: -; DARWIN-32-PIC: call L32$pb -; DARWIN-32-PIC-NEXT: L32$pb: +; DARWIN-32-PIC: call L31$pb +; DARWIN-32-PIC-NEXT: L31$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal _ddst-L32$pb(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L32$pb(%eax) +; DARWIN-32-PIC-NEXT: leal _ddst-L31$pb(%eax,%ecx,4), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L31$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind04: @@ -2320,12 +2320,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind05: -; DARWIN-32-PIC: call L33$pb -; DARWIN-32-PIC-NEXT: L33$pb: +; DARWIN-32-PIC: call L32$pb +; DARWIN-32-PIC-NEXT: L32$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _dsrc-L33$pb(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _dptr-L33$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _dsrc-L32$pb(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl _dptr-L32$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -2395,12 +2395,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind06: -; DARWIN-32-PIC: call L34$pb -; DARWIN-32-PIC-NEXT: L34$pb: +; DARWIN-32-PIC: call L33$pb +; DARWIN-32-PIC-NEXT: L33$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _lsrc-L34$pb(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, _ldst-L34$pb(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: movl _lsrc-L33$pb(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl %edx, _ldst-L33$pb(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind06: @@ -2466,12 +2466,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind07: -; DARWIN-32-PIC: call L35$pb -; DARWIN-32-PIC-NEXT: L35$pb: +; DARWIN-32-PIC: call L34$pb +; DARWIN-32-PIC-NEXT: L34$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal _ldst-L35$pb(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L35$pb(%eax) +; DARWIN-32-PIC-NEXT: leal _ldst-L34$pb(%eax,%ecx,4), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L34$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind07: @@ -2543,12 +2543,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind08: -; DARWIN-32-PIC: call L36$pb -; DARWIN-32-PIC-NEXT: L36$pb: +; DARWIN-32-PIC: call L35$pb +; DARWIN-32-PIC-NEXT: L35$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _lsrc-L36$pb(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _lptr-L36$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _lsrc-L35$pb(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl _lptr-L35$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -2621,13 +2621,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off00: -; DARWIN-32-PIC: call L37$pb -; DARWIN-32-PIC-NEXT: L37$pb: +; DARWIN-32-PIC: call L36$pb +; DARWIN-32-PIC-NEXT: L36$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L37$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L36$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L37$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L36$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -2700,13 +2700,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _oxf00: -; DARWIN-32-PIC: call L38$pb -; DARWIN-32-PIC-NEXT: L38$pb: +; DARWIN-32-PIC: call L37$pb +; DARWIN-32-PIC-NEXT: L37$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L38$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L37$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L38$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L37$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -2777,13 +2777,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off01: -; DARWIN-32-PIC: call L39$pb -; DARWIN-32-PIC-NEXT: L39$pb: +; DARWIN-32-PIC: call L38$pb +; DARWIN-32-PIC-NEXT: L38$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L39$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L38$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: leal 64(%edx,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L39$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L38$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -2854,13 +2854,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _oxf01: -; DARWIN-32-PIC: call L40$pb -; DARWIN-32-PIC-NEXT: L40$pb: +; DARWIN-32-PIC: call L39$pb +; DARWIN-32-PIC-NEXT: L39$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L40$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L39$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: leal 64(%edx,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L40$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L39$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -2940,13 +2940,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off02: -; DARWIN-32-PIC: call L41$pb -; DARWIN-32-PIC-NEXT: L41$pb: +; DARWIN-32-PIC: call L40$pb +; DARWIN-32-PIC-NEXT: L40$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L41$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L40$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L41$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L40$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -3030,13 +3030,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _oxf02: -; DARWIN-32-PIC: call L42$pb -; DARWIN-32-PIC-NEXT: L42$pb: +; DARWIN-32-PIC: call L41$pb +; DARWIN-32-PIC-NEXT: L41$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L42$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L41$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L42$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L41$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -3111,12 +3111,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off03: -; DARWIN-32-PIC: call L43$pb -; DARWIN-32-PIC-NEXT: L43$pb: +; DARWIN-32-PIC: call L42$pb +; DARWIN-32-PIC-NEXT: L42$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_dsrc-L43$pb)+64(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, (_ddst-L43$pb)+64(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: movl (_dsrc-L42$pb)+64(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl %edx, (_ddst-L42$pb)+64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off03: @@ -3184,12 +3184,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off04: -; DARWIN-32-PIC: call L44$pb -; DARWIN-32-PIC-NEXT: L44$pb: +; DARWIN-32-PIC: call L43$pb +; DARWIN-32-PIC-NEXT: L43$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ddst-L44$pb)+64(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L44$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ddst-L43$pb)+64(%eax,%ecx,4), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L43$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off04: @@ -3263,12 +3263,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off05: -; DARWIN-32-PIC: call L45$pb -; DARWIN-32-PIC-NEXT: L45$pb: +; DARWIN-32-PIC: call L44$pb +; DARWIN-32-PIC-NEXT: L44$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_dsrc-L45$pb)+64(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _dptr-L45$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_dsrc-L44$pb)+64(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl _dptr-L44$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -3339,12 +3339,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off06: -; DARWIN-32-PIC: call L46$pb -; DARWIN-32-PIC-NEXT: L46$pb: +; DARWIN-32-PIC: call L45$pb +; DARWIN-32-PIC-NEXT: L45$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_lsrc-L46$pb)+64(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, (_ldst-L46$pb)+64(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: movl (_lsrc-L45$pb)+64(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl %edx, (_ldst-L45$pb)+64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off06: @@ -3411,12 +3411,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off07: -; DARWIN-32-PIC: call L47$pb -; DARWIN-32-PIC-NEXT: L47$pb: +; DARWIN-32-PIC: call L46$pb +; DARWIN-32-PIC-NEXT: L46$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ldst-L47$pb)+64(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L47$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ldst-L46$pb)+64(%eax,%ecx,4), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L46$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off07: @@ -3489,12 +3489,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off08: -; DARWIN-32-PIC: call L48$pb -; DARWIN-32-PIC-NEXT: L48$pb: +; DARWIN-32-PIC: call L47$pb +; DARWIN-32-PIC-NEXT: L47$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_lsrc-L48$pb)+64(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _lptr-L48$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_lsrc-L47$pb)+64(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl _lptr-L47$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -3560,12 +3560,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo00: -; DARWIN-32-PIC: call L49$pb -; DARWIN-32-PIC-NEXT: L49$pb: +; DARWIN-32-PIC: call L48$pb +; DARWIN-32-PIC-NEXT: L48$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L49$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L48$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl 262144(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L49$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L48$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -3626,12 +3626,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo01: -; DARWIN-32-PIC: call L50$pb -; DARWIN-32-PIC-NEXT: L50$pb: +; DARWIN-32-PIC: call L49$pb +; DARWIN-32-PIC-NEXT: L49$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl $262144, %ecx -; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L50$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L50$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L49$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L49$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -3705,12 +3705,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo02: -; DARWIN-32-PIC: call L51$pb -; DARWIN-32-PIC-NEXT: L51$pb: +; DARWIN-32-PIC: call L50$pb +; DARWIN-32-PIC-NEXT: L50$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L51$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L50$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl 262144(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L51$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L50$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -3778,11 +3778,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo03: -; DARWIN-32-PIC: call L52$pb -; DARWIN-32-PIC-NEXT: L52$pb: +; DARWIN-32-PIC: call L51$pb +; DARWIN-32-PIC-NEXT: L51$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_dsrc-L52$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, (_ddst-L52$pb)+262144(%eax) +; DARWIN-32-PIC-NEXT: movl (_dsrc-L51$pb)+262144(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, (_ddst-L51$pb)+262144(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo03: @@ -3833,11 +3833,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo04: -; DARWIN-32-PIC: call L53$pb -; DARWIN-32-PIC-NEXT: L53$pb: +; DARWIN-32-PIC: call L52$pb +; DARWIN-32-PIC-NEXT: L52$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ddst-L53$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L53$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ddst-L52$pb)+262144(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L52$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo04: @@ -3902,11 +3902,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo05: -; DARWIN-32-PIC: call L54$pb -; DARWIN-32-PIC-NEXT: L54$pb: +; DARWIN-32-PIC: call L53$pb +; DARWIN-32-PIC-NEXT: L53$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_dsrc-L54$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _dptr-L54$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_dsrc-L53$pb)+262144(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl _dptr-L53$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -3965,11 +3965,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo06: -; DARWIN-32-PIC: call L55$pb -; DARWIN-32-PIC-NEXT: L55$pb: +; DARWIN-32-PIC: call L54$pb +; DARWIN-32-PIC-NEXT: L54$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_lsrc-L55$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, (_ldst-L55$pb)+262144(%eax) +; DARWIN-32-PIC-NEXT: movl (_lsrc-L54$pb)+262144(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, (_ldst-L54$pb)+262144(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo06: @@ -4018,11 +4018,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo07: -; DARWIN-32-PIC: call L56$pb -; DARWIN-32-PIC-NEXT: L56$pb: +; DARWIN-32-PIC: call L55$pb +; DARWIN-32-PIC-NEXT: L55$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ldst-L56$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L56$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ldst-L55$pb)+262144(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L55$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo07: @@ -4085,11 +4085,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo08: -; DARWIN-32-PIC: call L57$pb -; DARWIN-32-PIC-NEXT: L57$pb: +; DARWIN-32-PIC: call L56$pb +; DARWIN-32-PIC-NEXT: L56$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_lsrc-L57$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _lptr-L57$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_lsrc-L56$pb)+262144(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl _lptr-L56$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax) ; DARWIN-32-PIC-NEXT: ret @@ -4159,13 +4159,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big00: -; DARWIN-32-PIC: call L58$pb -; DARWIN-32-PIC-NEXT: L58$pb: +; DARWIN-32-PIC: call L57$pb +; DARWIN-32-PIC-NEXT: L57$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L58$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L57$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl 262144(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L58$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L57$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -4236,13 +4236,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big01: -; DARWIN-32-PIC: call L59$pb -; DARWIN-32-PIC-NEXT: L59$pb: +; DARWIN-32-PIC: call L58$pb +; DARWIN-32-PIC-NEXT: L58$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L59$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L58$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: leal 262144(%edx,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L59$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L58$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) ; DARWIN-32-PIC-NEXT: ret @@ -4322,13 +4322,13 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big02: -; DARWIN-32-PIC: call L60$pb -; DARWIN-32-PIC-NEXT: L60$pb: +; DARWIN-32-PIC: call L59$pb +; DARWIN-32-PIC-NEXT: L59$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L60$pb(%eax), %edx +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L59$pb(%eax), %edx ; DARWIN-32-PIC-NEXT: movl 262144(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L60$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L59$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -4403,12 +4403,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big03: -; DARWIN-32-PIC: call L61$pb -; DARWIN-32-PIC-NEXT: L61$pb: +; DARWIN-32-PIC: call L60$pb +; DARWIN-32-PIC-NEXT: L60$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_dsrc-L61$pb)+262144(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, (_ddst-L61$pb)+262144(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: movl (_dsrc-L60$pb)+262144(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl %edx, (_ddst-L60$pb)+262144(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big03: @@ -4476,12 +4476,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big04: -; DARWIN-32-PIC: call L62$pb -; DARWIN-32-PIC-NEXT: L62$pb: +; DARWIN-32-PIC: call L61$pb +; DARWIN-32-PIC-NEXT: L61$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ddst-L62$pb)+262144(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L62$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ddst-L61$pb)+262144(%eax,%ecx,4), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L61$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big04: @@ -4555,12 +4555,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big05: -; DARWIN-32-PIC: call L63$pb -; DARWIN-32-PIC-NEXT: L63$pb: +; DARWIN-32-PIC: call L62$pb +; DARWIN-32-PIC-NEXT: L62$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_dsrc-L63$pb)+262144(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _dptr-L63$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_dsrc-L62$pb)+262144(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl _dptr-L62$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -4631,12 +4631,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big06: -; DARWIN-32-PIC: call L64$pb -; DARWIN-32-PIC-NEXT: L64$pb: +; DARWIN-32-PIC: call L63$pb +; DARWIN-32-PIC-NEXT: L63$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_lsrc-L64$pb)+262144(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, (_ldst-L64$pb)+262144(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: movl (_lsrc-L63$pb)+262144(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl %edx, (_ldst-L63$pb)+262144(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big06: @@ -4703,12 +4703,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big07: -; DARWIN-32-PIC: call L65$pb -; DARWIN-32-PIC-NEXT: L65$pb: +; DARWIN-32-PIC: call L64$pb +; DARWIN-32-PIC-NEXT: L64$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ldst-L65$pb)+262144(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L65$pb(%eax) +; DARWIN-32-PIC-NEXT: leal (_ldst-L64$pb)+262144(%eax,%ecx,4), %ecx +; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L64$pb(%eax) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big07: @@ -4781,12 +4781,12 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big08: -; DARWIN-32-PIC: call L66$pb -; DARWIN-32-PIC-NEXT: L66$pb: +; DARWIN-32-PIC: call L65$pb +; DARWIN-32-PIC-NEXT: L65$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_lsrc-L66$pb)+262144(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _lptr-L66$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl (_lsrc-L65$pb)+262144(%eax,%ecx,4), %edx +; DARWIN-32-PIC-NEXT: movl _lptr-L65$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4) ; DARWIN-32-PIC-NEXT: ret @@ -4840,10 +4840,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar00: -; DARWIN-32-PIC: call L67$pb -; DARWIN-32-PIC-NEXT: L67$pb: +; DARWIN-32-PIC: call L66$pb +; DARWIN-32-PIC-NEXT: L66$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L67$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L66$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar00: @@ -4887,10 +4887,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bxr00: -; DARWIN-32-PIC: call L68$pb -; DARWIN-32-PIC-NEXT: L68$pb: +; DARWIN-32-PIC: call L67$pb +; DARWIN-32-PIC-NEXT: L67$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L68$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L67$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bxr00: @@ -4934,10 +4934,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar01: -; DARWIN-32-PIC: call L69$pb -; DARWIN-32-PIC-NEXT: L69$pb: +; DARWIN-32-PIC: call L68$pb +; DARWIN-32-PIC-NEXT: L68$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L69$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L68$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar01: @@ -4981,10 +4981,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bxr01: -; DARWIN-32-PIC: call L70$pb -; DARWIN-32-PIC-NEXT: L70$pb: +; DARWIN-32-PIC: call L69$pb +; DARWIN-32-PIC-NEXT: L69$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L70$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L69$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bxr01: @@ -5028,10 +5028,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar02: -; DARWIN-32-PIC: call L71$pb -; DARWIN-32-PIC-NEXT: L71$pb: +; DARWIN-32-PIC: call L70$pb +; DARWIN-32-PIC-NEXT: L70$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L71$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L70$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar02: @@ -5075,10 +5075,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar03: -; DARWIN-32-PIC: call L72$pb -; DARWIN-32-PIC-NEXT: L72$pb: +; DARWIN-32-PIC: call L71$pb +; DARWIN-32-PIC-NEXT: L71$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _dsrc-L72$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _dsrc-L71$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar03: @@ -5122,10 +5122,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar04: -; DARWIN-32-PIC: call L73$pb -; DARWIN-32-PIC-NEXT: L73$pb: +; DARWIN-32-PIC: call L72$pb +; DARWIN-32-PIC-NEXT: L72$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ddst-L73$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _ddst-L72$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar04: @@ -5169,10 +5169,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar05: -; DARWIN-32-PIC: call L74$pb -; DARWIN-32-PIC-NEXT: L74$pb: +; DARWIN-32-PIC: call L73$pb +; DARWIN-32-PIC-NEXT: L73$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _dptr-L74$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _dptr-L73$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar05: @@ -5216,10 +5216,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar06: -; DARWIN-32-PIC: call L75$pb -; DARWIN-32-PIC-NEXT: L75$pb: +; DARWIN-32-PIC: call L74$pb +; DARWIN-32-PIC-NEXT: L74$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _lsrc-L75$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _lsrc-L74$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar06: @@ -5263,10 +5263,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar07: -; DARWIN-32-PIC: call L76$pb -; DARWIN-32-PIC-NEXT: L76$pb: +; DARWIN-32-PIC: call L75$pb +; DARWIN-32-PIC-NEXT: L75$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ldst-L76$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _ldst-L75$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar07: @@ -5310,10 +5310,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bar08: -; DARWIN-32-PIC: call L77$pb -; DARWIN-32-PIC-NEXT: L77$pb: +; DARWIN-32-PIC: call L76$pb +; DARWIN-32-PIC-NEXT: L76$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _lptr-L77$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _lptr-L76$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar08: @@ -5357,10 +5357,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har00: -; DARWIN-32-PIC: call L78$pb -; DARWIN-32-PIC-NEXT: L78$pb: +; DARWIN-32-PIC: call L77$pb +; DARWIN-32-PIC-NEXT: L77$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L78$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L77$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har00: @@ -5404,10 +5404,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _hxr00: -; DARWIN-32-PIC: call L79$pb -; DARWIN-32-PIC-NEXT: L79$pb: +; DARWIN-32-PIC: call L78$pb +; DARWIN-32-PIC-NEXT: L78$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L79$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L78$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _hxr00: @@ -5451,10 +5451,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har01: -; DARWIN-32-PIC: call L80$pb -; DARWIN-32-PIC-NEXT: L80$pb: +; DARWIN-32-PIC: call L79$pb +; DARWIN-32-PIC-NEXT: L79$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L80$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L79$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har01: @@ -5498,10 +5498,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _hxr01: -; DARWIN-32-PIC: call L81$pb -; DARWIN-32-PIC-NEXT: L81$pb: +; DARWIN-32-PIC: call L80$pb +; DARWIN-32-PIC-NEXT: L80$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L81$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L80$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _hxr01: @@ -5549,10 +5549,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har02: -; DARWIN-32-PIC: call L82$pb -; DARWIN-32-PIC-NEXT: L82$pb: +; DARWIN-32-PIC: call L81$pb +; DARWIN-32-PIC-NEXT: L81$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L82$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L81$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: ret @@ -5600,10 +5600,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har03: -; DARWIN-32-PIC: call L83$pb -; DARWIN-32-PIC-NEXT: L83$pb: +; DARWIN-32-PIC: call L82$pb +; DARWIN-32-PIC-NEXT: L82$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _dsrc-L83$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _dsrc-L82$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har03: @@ -5647,10 +5647,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har04: -; DARWIN-32-PIC: call L84$pb -; DARWIN-32-PIC-NEXT: L84$pb: +; DARWIN-32-PIC: call L83$pb +; DARWIN-32-PIC-NEXT: L83$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ddst-L84$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _ddst-L83$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har04: @@ -5697,10 +5697,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har05: -; DARWIN-32-PIC: call L85$pb -; DARWIN-32-PIC-NEXT: L85$pb: +; DARWIN-32-PIC: call L84$pb +; DARWIN-32-PIC-NEXT: L84$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _dptr-L85$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _dptr-L84$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har05: @@ -5744,10 +5744,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har06: -; DARWIN-32-PIC: call L86$pb -; DARWIN-32-PIC-NEXT: L86$pb: +; DARWIN-32-PIC: call L85$pb +; DARWIN-32-PIC-NEXT: L85$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _lsrc-L86$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _lsrc-L85$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har06: @@ -5791,10 +5791,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har07: -; DARWIN-32-PIC: call L87$pb -; DARWIN-32-PIC-NEXT: L87$pb: +; DARWIN-32-PIC: call L86$pb +; DARWIN-32-PIC-NEXT: L86$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ldst-L87$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _ldst-L86$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har07: @@ -5840,10 +5840,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har08: -; DARWIN-32-PIC: call L88$pb -; DARWIN-32-PIC-NEXT: L88$pb: +; DARWIN-32-PIC: call L87$pb +; DARWIN-32-PIC-NEXT: L87$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _lptr-L88$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _lptr-L87$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har08: @@ -5889,10 +5889,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat00: -; DARWIN-32-PIC: call L89$pb -; DARWIN-32-PIC-NEXT: L89$pb: +; DARWIN-32-PIC: call L88$pb +; DARWIN-32-PIC-NEXT: L88$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L89$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L88$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -5942,10 +5942,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bxt00: -; DARWIN-32-PIC: call L90$pb -; DARWIN-32-PIC-NEXT: L90$pb: +; DARWIN-32-PIC: call L89$pb +; DARWIN-32-PIC-NEXT: L89$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L90$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L89$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -5995,10 +5995,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat01: -; DARWIN-32-PIC: call L91$pb -; DARWIN-32-PIC-NEXT: L91$pb: +; DARWIN-32-PIC: call L90$pb +; DARWIN-32-PIC-NEXT: L90$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L91$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L90$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -6048,10 +6048,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bxt01: -; DARWIN-32-PIC: call L92$pb -; DARWIN-32-PIC-NEXT: L92$pb: +; DARWIN-32-PIC: call L91$pb +; DARWIN-32-PIC-NEXT: L91$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L92$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L91$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -6110,10 +6110,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat02: -; DARWIN-32-PIC: call L93$pb -; DARWIN-32-PIC-NEXT: L93$pb: +; DARWIN-32-PIC: call L92$pb +; DARWIN-32-PIC-NEXT: L92$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L93$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L92$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -6166,10 +6166,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat03: -; DARWIN-32-PIC: call L94$pb -; DARWIN-32-PIC-NEXT: L94$pb: +; DARWIN-32-PIC: call L93$pb +; DARWIN-32-PIC-NEXT: L93$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_dsrc-L94$pb)+64(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_dsrc-L93$pb)+64(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bat03: @@ -6214,10 +6214,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat04: -; DARWIN-32-PIC: call L95$pb -; DARWIN-32-PIC-NEXT: L95$pb: +; DARWIN-32-PIC: call L94$pb +; DARWIN-32-PIC-NEXT: L94$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ddst-L95$pb)+64(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_ddst-L94$pb)+64(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bat04: @@ -6271,10 +6271,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat05: -; DARWIN-32-PIC: call L96$pb -; DARWIN-32-PIC-NEXT: L96$pb: +; DARWIN-32-PIC: call L95$pb +; DARWIN-32-PIC-NEXT: L95$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _dptr-L96$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _dptr-L95$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -6322,10 +6322,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat06: -; DARWIN-32-PIC: call L97$pb -; DARWIN-32-PIC-NEXT: L97$pb: +; DARWIN-32-PIC: call L96$pb +; DARWIN-32-PIC-NEXT: L96$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_lsrc-L97$pb)+64(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_lsrc-L96$pb)+64(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bat06: @@ -6369,10 +6369,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat07: -; DARWIN-32-PIC: call L98$pb -; DARWIN-32-PIC-NEXT: L98$pb: +; DARWIN-32-PIC: call L97$pb +; DARWIN-32-PIC-NEXT: L97$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ldst-L98$pb)+64(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_ldst-L97$pb)+64(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bat07: @@ -6425,10 +6425,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat08: -; DARWIN-32-PIC: call L99$pb -; DARWIN-32-PIC-NEXT: L99$pb: +; DARWIN-32-PIC: call L98$pb +; DARWIN-32-PIC-NEXT: L98$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _lptr-L99$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _lptr-L98$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -6478,11 +6478,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam00: -; DARWIN-32-PIC: call L100$pb -; DARWIN-32-PIC-NEXT: L100$pb: +; DARWIN-32-PIC: call L99$pb +; DARWIN-32-PIC-NEXT: L99$pb: ; DARWIN-32-PIC-NEXT: popl %ecx ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl L_src$non_lazy_ptr-L100$pb(%ecx), %eax +; DARWIN-32-PIC-NEXT: addl L_src$non_lazy_ptr-L99$pb(%ecx), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam00: @@ -6531,11 +6531,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam01: -; DARWIN-32-PIC: call L101$pb -; DARWIN-32-PIC-NEXT: L101$pb: +; DARWIN-32-PIC: call L100$pb +; DARWIN-32-PIC-NEXT: L100$pb: ; DARWIN-32-PIC-NEXT: popl %ecx ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L101$pb(%ecx), %eax +; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L100$pb(%ecx), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam01: @@ -6584,11 +6584,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bxm01: -; DARWIN-32-PIC: call L102$pb -; DARWIN-32-PIC-NEXT: L102$pb: +; DARWIN-32-PIC: call L101$pb +; DARWIN-32-PIC-NEXT: L101$pb: ; DARWIN-32-PIC-NEXT: popl %ecx ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-L102$pb(%ecx), %eax +; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-L101$pb(%ecx), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bxm01: @@ -6646,10 +6646,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam02: -; DARWIN-32-PIC: call L103$pb -; DARWIN-32-PIC-NEXT: L103$pb: +; DARWIN-32-PIC: call L102$pb +; DARWIN-32-PIC-NEXT: L102$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L103$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L102$pb(%eax), %ecx ; DARWIN-32-PIC-NEXT: movl $262144, %eax ; DARWIN-32-PIC-NEXT: addl (%ecx), %eax ; DARWIN-32-PIC-NEXT: ret @@ -6702,10 +6702,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam03: -; DARWIN-32-PIC: call L104$pb -; DARWIN-32-PIC-NEXT: L104$pb: +; DARWIN-32-PIC: call L103$pb +; DARWIN-32-PIC-NEXT: L103$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_dsrc-L104$pb)+262144(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_dsrc-L103$pb)+262144(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam03: @@ -6750,10 +6750,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam04: -; DARWIN-32-PIC: call L105$pb -; DARWIN-32-PIC-NEXT: L105$pb: +; DARWIN-32-PIC: call L104$pb +; DARWIN-32-PIC-NEXT: L104$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ddst-L105$pb)+262144(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_ddst-L104$pb)+262144(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam04: @@ -6807,11 +6807,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam05: -; DARWIN-32-PIC: call L106$pb -; DARWIN-32-PIC-NEXT: L106$pb: +; DARWIN-32-PIC: call L105$pb +; DARWIN-32-PIC-NEXT: L105$pb: ; DARWIN-32-PIC-NEXT: popl %ecx ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl _dptr-L106$pb(%ecx), %eax +; DARWIN-32-PIC-NEXT: addl _dptr-L105$pb(%ecx), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam05: @@ -6858,10 +6858,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam06: -; DARWIN-32-PIC: call L107$pb -; DARWIN-32-PIC-NEXT: L107$pb: +; DARWIN-32-PIC: call L106$pb +; DARWIN-32-PIC-NEXT: L106$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_lsrc-L107$pb)+262144(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_lsrc-L106$pb)+262144(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam06: @@ -6905,10 +6905,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam07: -; DARWIN-32-PIC: call L108$pb -; DARWIN-32-PIC-NEXT: L108$pb: +; DARWIN-32-PIC: call L107$pb +; DARWIN-32-PIC-NEXT: L107$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ldst-L108$pb)+262144(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_ldst-L107$pb)+262144(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam07: @@ -6961,11 +6961,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam08: -; DARWIN-32-PIC: call L109$pb -; DARWIN-32-PIC-NEXT: L109$pb: +; DARWIN-32-PIC: call L108$pb +; DARWIN-32-PIC-NEXT: L108$pb: ; DARWIN-32-PIC-NEXT: popl %ecx ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl _lptr-L109$pb(%ecx), %eax +; DARWIN-32-PIC-NEXT: addl _lptr-L108$pb(%ecx), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam08: @@ -7021,11 +7021,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat00: -; DARWIN-32-PIC: call L110$pb -; DARWIN-32-PIC-NEXT: L110$pb: +; DARWIN-32-PIC: call L109$pb +; DARWIN-32-PIC-NEXT: L109$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L110$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L109$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7082,11 +7082,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cxt00: -; DARWIN-32-PIC: call L111$pb -; DARWIN-32-PIC-NEXT: L111$pb: +; DARWIN-32-PIC: call L110$pb +; DARWIN-32-PIC-NEXT: L110$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L111$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L110$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7143,11 +7143,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat01: -; DARWIN-32-PIC: call L112$pb -; DARWIN-32-PIC-NEXT: L112$pb: +; DARWIN-32-PIC: call L111$pb +; DARWIN-32-PIC-NEXT: L111$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L112$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L111$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7204,11 +7204,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cxt01: -; DARWIN-32-PIC: call L113$pb -; DARWIN-32-PIC-NEXT: L113$pb: +; DARWIN-32-PIC: call L112$pb +; DARWIN-32-PIC-NEXT: L112$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L113$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L112$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7272,10 +7272,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat02: -; DARWIN-32-PIC: call L114$pb -; DARWIN-32-PIC-NEXT: L114$pb: +; DARWIN-32-PIC: call L113$pb +; DARWIN-32-PIC-NEXT: L113$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L114$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L113$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax @@ -7336,11 +7336,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat03: -; DARWIN-32-PIC: call L115$pb -; DARWIN-32-PIC-NEXT: L115$pb: +; DARWIN-32-PIC: call L114$pb +; DARWIN-32-PIC-NEXT: L114$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_dsrc-L115$pb)+64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_dsrc-L114$pb)+64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat03: @@ -7395,11 +7395,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat04: -; DARWIN-32-PIC: call L116$pb -; DARWIN-32-PIC-NEXT: L116$pb: +; DARWIN-32-PIC: call L115$pb +; DARWIN-32-PIC-NEXT: L115$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ddst-L116$pb)+64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_ddst-L115$pb)+64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat04: @@ -7461,11 +7461,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat05: -; DARWIN-32-PIC: call L117$pb -; DARWIN-32-PIC-NEXT: L117$pb: +; DARWIN-32-PIC: call L116$pb +; DARWIN-32-PIC-NEXT: L116$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _dptr-L117$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _dptr-L116$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7521,11 +7521,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat06: -; DARWIN-32-PIC: call L118$pb -; DARWIN-32-PIC-NEXT: L118$pb: +; DARWIN-32-PIC: call L117$pb +; DARWIN-32-PIC-NEXT: L117$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_lsrc-L118$pb)+64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_lsrc-L117$pb)+64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat06: @@ -7580,11 +7580,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat07: -; DARWIN-32-PIC: call L119$pb -; DARWIN-32-PIC-NEXT: L119$pb: +; DARWIN-32-PIC: call L118$pb +; DARWIN-32-PIC-NEXT: L118$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ldst-L119$pb)+64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_ldst-L118$pb)+64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat07: @@ -7645,11 +7645,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat08: -; DARWIN-32-PIC: call L120$pb -; DARWIN-32-PIC-NEXT: L120$pb: +; DARWIN-32-PIC: call L119$pb +; DARWIN-32-PIC-NEXT: L119$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _lptr-L120$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _lptr-L119$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7706,11 +7706,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam00: -; DARWIN-32-PIC: call L121$pb -; DARWIN-32-PIC-NEXT: L121$pb: +; DARWIN-32-PIC: call L120$pb +; DARWIN-32-PIC-NEXT: L120$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L121$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L120$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7767,11 +7767,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cxm00: -; DARWIN-32-PIC: call L122$pb -; DARWIN-32-PIC-NEXT: L122$pb: +; DARWIN-32-PIC: call L121$pb +; DARWIN-32-PIC-NEXT: L121$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L122$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L121$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7828,11 +7828,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam01: -; DARWIN-32-PIC: call L123$pb -; DARWIN-32-PIC-NEXT: L123$pb: +; DARWIN-32-PIC: call L122$pb +; DARWIN-32-PIC-NEXT: L122$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L123$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L122$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7889,11 +7889,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cxm01: -; DARWIN-32-PIC: call L124$pb -; DARWIN-32-PIC-NEXT: L124$pb: +; DARWIN-32-PIC: call L123$pb +; DARWIN-32-PIC-NEXT: L123$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L124$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L123$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -7957,10 +7957,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam02: -; DARWIN-32-PIC: call L125$pb -; DARWIN-32-PIC-NEXT: L125$pb: +; DARWIN-32-PIC: call L124$pb +; DARWIN-32-PIC-NEXT: L124$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L125$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L124$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: movl (%eax), %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax @@ -8021,11 +8021,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam03: -; DARWIN-32-PIC: call L126$pb -; DARWIN-32-PIC-NEXT: L126$pb: +; DARWIN-32-PIC: call L125$pb +; DARWIN-32-PIC-NEXT: L125$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_dsrc-L126$pb)+262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_dsrc-L125$pb)+262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam03: @@ -8080,11 +8080,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam04: -; DARWIN-32-PIC: call L127$pb -; DARWIN-32-PIC-NEXT: L127$pb: +; DARWIN-32-PIC: call L126$pb +; DARWIN-32-PIC-NEXT: L126$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ddst-L127$pb)+262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_ddst-L126$pb)+262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam04: @@ -8146,11 +8146,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam05: -; DARWIN-32-PIC: call L128$pb -; DARWIN-32-PIC-NEXT: L128$pb: +; DARWIN-32-PIC: call L127$pb +; DARWIN-32-PIC-NEXT: L127$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _dptr-L128$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _dptr-L127$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -8206,11 +8206,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam06: -; DARWIN-32-PIC: call L129$pb -; DARWIN-32-PIC-NEXT: L129$pb: +; DARWIN-32-PIC: call L128$pb +; DARWIN-32-PIC-NEXT: L128$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_lsrc-L129$pb)+262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_lsrc-L128$pb)+262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam06: @@ -8265,11 +8265,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam07: -; DARWIN-32-PIC: call L130$pb -; DARWIN-32-PIC-NEXT: L130$pb: +; DARWIN-32-PIC: call L129$pb +; DARWIN-32-PIC-NEXT: L129$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ldst-L130$pb)+262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: leal (_ldst-L129$pb)+262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam07: @@ -8330,11 +8330,11 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam08: -; DARWIN-32-PIC: call L131$pb -; DARWIN-32-PIC-NEXT: L131$pb: +; DARWIN-32-PIC: call L130$pb +; DARWIN-32-PIC-NEXT: L130$pb: ; DARWIN-32-PIC-NEXT: popl %eax ; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _lptr-L131$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl _lptr-L130$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax ; DARWIN-32-PIC-NEXT: ret @@ -8644,10 +8644,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _address: -; DARWIN-32-PIC: call L134$pb -; DARWIN-32-PIC-NEXT: L134$pb: +; DARWIN-32-PIC: call L133$pb +; DARWIN-32-PIC-NEXT: L133$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_callee$non_lazy_ptr-L134$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: movl L_callee$non_lazy_ptr-L133$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _address: @@ -8693,10 +8693,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _laddress: -; DARWIN-32-PIC: call L135$pb -; DARWIN-32-PIC-NEXT: L135$pb: +; DARWIN-32-PIC: call L134$pb +; DARWIN-32-PIC-NEXT: L134$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _lcallee-L135$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _lcallee-L134$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _laddress: @@ -8740,10 +8740,10 @@ entry: ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _daddress: -; DARWIN-32-PIC: call L136$pb -; DARWIN-32-PIC-NEXT: L136$pb: +; DARWIN-32-PIC: call L135$pb +; DARWIN-32-PIC-NEXT: L135$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _dcallee-L136$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: leal _dcallee-L135$pb(%eax), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _daddress: @@ -9224,10 +9224,10 @@ entry: ; DARWIN-32-PIC: _icaller: ; DARWIN-32-PIC: pushl %esi ; DARWIN-32-PIC-NEXT: subl $8, %esp -; DARWIN-32-PIC-NEXT: call L143$pb -; DARWIN-32-PIC-NEXT: L143$pb: +; DARWIN-32-PIC-NEXT: call L142$pb +; DARWIN-32-PIC-NEXT: L142$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-L143$pb(%eax), %esi +; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-L142$pb(%eax), %esi ; DARWIN-32-PIC-NEXT: call *(%esi) ; DARWIN-32-PIC-NEXT: call *(%esi) ; DARWIN-32-PIC-NEXT: addl $8, %esp @@ -9310,11 +9310,11 @@ entry: ; DARWIN-32-PIC: _dicaller: ; DARWIN-32-PIC: pushl %esi ; DARWIN-32-PIC-NEXT: subl $8, %esp -; DARWIN-32-PIC-NEXT: call L144$pb -; DARWIN-32-PIC-NEXT: L144$pb: +; DARWIN-32-PIC-NEXT: call L143$pb +; DARWIN-32-PIC-NEXT: L143$pb: ; DARWIN-32-PIC-NEXT: popl %esi -; DARWIN-32-PIC-NEXT: call *_difunc-L144$pb(%esi) -; DARWIN-32-PIC-NEXT: call *_difunc-L144$pb(%esi) +; DARWIN-32-PIC-NEXT: call *_difunc-L143$pb(%esi) +; DARWIN-32-PIC-NEXT: call *_difunc-L143$pb(%esi) ; DARWIN-32-PIC-NEXT: addl $8, %esp ; DARWIN-32-PIC-NEXT: popl %esi ; DARWIN-32-PIC-NEXT: ret @@ -9391,11 +9391,11 @@ entry: ; DARWIN-32-PIC: _licaller: ; DARWIN-32-PIC: pushl %esi ; DARWIN-32-PIC-NEXT: subl $8, %esp -; DARWIN-32-PIC-NEXT: call L145$pb -; DARWIN-32-PIC-NEXT: L145$pb: +; DARWIN-32-PIC-NEXT: call L144$pb +; DARWIN-32-PIC-NEXT: L144$pb: ; DARWIN-32-PIC-NEXT: popl %esi -; DARWIN-32-PIC-NEXT: call *_lifunc-L145$pb(%esi) -; DARWIN-32-PIC-NEXT: call *_lifunc-L145$pb(%esi) +; DARWIN-32-PIC-NEXT: call *_lifunc-L144$pb(%esi) +; DARWIN-32-PIC-NEXT: call *_lifunc-L144$pb(%esi) ; DARWIN-32-PIC-NEXT: addl $8, %esp ; DARWIN-32-PIC-NEXT: popl %esi ; DARWIN-32-PIC-NEXT: ret @@ -9476,10 +9476,10 @@ entry: ; DARWIN-32-PIC: _itailcaller: ; DARWIN-32-PIC: pushl %esi ; DARWIN-32-PIC-NEXT: subl $8, %esp -; DARWIN-32-PIC-NEXT: call L146$pb -; DARWIN-32-PIC-NEXT: L146$pb: +; DARWIN-32-PIC-NEXT: call L145$pb +; DARWIN-32-PIC-NEXT: L145$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-L146$pb(%eax), %esi +; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-L145$pb(%eax), %esi ; DARWIN-32-PIC-NEXT: call *(%esi) ; DARWIN-32-PIC-NEXT: call *(%esi) ; DARWIN-32-PIC-NEXT: addl $8, %esp @@ -9553,10 +9553,10 @@ entry: ; DARWIN-32-PIC: _ditailcaller: ; DARWIN-32-PIC: subl $12, %esp -; DARWIN-32-PIC-NEXT: call L147$pb -; DARWIN-32-PIC-NEXT: L147$pb: +; DARWIN-32-PIC-NEXT: call L146$pb +; DARWIN-32-PIC-NEXT: L146$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: call *_difunc-L147$pb(%eax) +; DARWIN-32-PIC-NEXT: call *_difunc-L146$pb(%eax) ; DARWIN-32-PIC-NEXT: addl $12, %esp ; DARWIN-32-PIC-NEXT: ret @@ -9619,10 +9619,10 @@ entry: ; DARWIN-32-PIC: _litailcaller: ; DARWIN-32-PIC: subl $12, %esp -; DARWIN-32-PIC-NEXT: call L148$pb -; DARWIN-32-PIC-NEXT: L148$pb: +; DARWIN-32-PIC-NEXT: call L147$pb +; DARWIN-32-PIC-NEXT: L147$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: call *_lifunc-L148$pb(%eax) +; DARWIN-32-PIC-NEXT: call *_lifunc-L147$pb(%eax) ; DARWIN-32-PIC-NEXT: addl $12, %esp ; DARWIN-32-PIC-NEXT: ret diff --git a/test/CodeGen/X86/alignment.ll b/test/CodeGen/X86/alignment.ll new file mode 100644 index 000000000000..9678e6df740e --- /dev/null +++ b/test/CodeGen/X86/alignment.ll @@ -0,0 +1,43 @@ +; RUN: llc %s -o - -mtriple=x86_64-linux-gnu | FileCheck %s + +; This cannot get rounded up to the preferred alignment (16) if they have an +; explicit alignment specified. +@GlobalA = global { [384 x i8] } zeroinitializer, align 8 + +; CHECK: .bss +; CHECK: .globl GlobalA +; CHECK: .align 16 +; CHECK: GlobalA: +; CHECK: .zero 384 + +; Common variables should not get rounded up to the preferred alignment (16) if +; they have an explicit alignment specified. +; PR6921 +@GlobalB = common global { [384 x i8] } zeroinitializer, align 8 + +; CHECK: .comm GlobalB,384,16 + + +@GlobalC = common global { [384 x i8] } zeroinitializer, align 2 + +; CHECK: .comm GlobalC,384,16 + + + +; This cannot get rounded up to the preferred alignment (16) if they have an +; explicit alignment specified *and* a section specified. +@GlobalAS = global { [384 x i8] } zeroinitializer, align 8, section "foo" + +; CHECK: .globl GlobalAS +; CHECK: .align 8 +; CHECK: GlobalAS: +; CHECK: .zero 384 + +; Common variables should not get rounded up to the preferred alignment (16) if +; they have an explicit alignment specified and a section specified. +; PR6921 +@GlobalBS = common global { [384 x i8] } zeroinitializer, align 8, section "foo" +; CHECK: .comm GlobalBS,384,8 + +@GlobalCS = common global { [384 x i8] } zeroinitializer, align 2, section "foo" +; CHECK: .comm GlobalCS,384,2
\ No newline at end of file diff --git a/test/CodeGen/X86/atomic_add.ll b/test/CodeGen/X86/atomic_add.ll index d00f8e861c21..26d25e24dfbc 100644 --- a/test/CodeGen/X86/atomic_add.ll +++ b/test/CodeGen/X86/atomic_add.ll @@ -192,7 +192,7 @@ entry: define void @sub2(i16* nocapture %p, i32 %v) nounwind ssp { entry: ; CHECK: sub2: -; CHECK: subw +; CHECK: negl %0 = trunc i32 %v to i16 ; <i16> [#uses=1] %1 = tail call i16 @llvm.atomic.load.sub.i16.p0i16(i16* %p, i16 %0) ; <i16> [#uses=0] ret void diff --git a/test/CodeGen/X86/avoid-loop-align.ll b/test/CodeGen/X86/avoid-loop-align.ll index d4c5c6723243..7957db72fe6d 100644 --- a/test/CodeGen/X86/avoid-loop-align.ll +++ b/test/CodeGen/X86/avoid-loop-align.ll @@ -3,9 +3,9 @@ ; CodeGen should align the top of the loop, which differs from the loop ; header in this case. -; CHECK: jmp LBB1_2 +; CHECK: jmp LBB0_2 ; CHECK: .align -; CHECK: LBB1_1: +; CHECK: LBB0_1: @A = common global [100 x i32] zeroinitializer, align 32 ; <[100 x i32]*> [#uses=1] diff --git a/test/CodeGen/X86/brcond.ll b/test/CodeGen/X86/brcond.ll index 130483ad8410..5cdc1000f3cd 100644 --- a/test/CodeGen/X86/brcond.ll +++ b/test/CodeGen/X86/brcond.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin10 | FileCheck %s +; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=core2 | FileCheck %s ; rdar://7475489 define i32 @test1(i32 %a, i32 %b) nounwind ssp { @@ -46,7 +46,7 @@ return: ; preds = %entry ; CHECK: test2: ; CHECK: movl 4(%esp), %eax ; CHECK-NEXT: orl 8(%esp), %eax -; CHECK-NEXT: jne LBB2_2 +; CHECK-NEXT: jne LBB1_2 } ; PR3351 - (P != 0) | (Q != 0) -> (P|Q) != 0 @@ -65,5 +65,44 @@ return: ; preds = %entry ; CHECK: test3: ; CHECK: movl 4(%esp), %eax ; CHECK-NEXT: orl 8(%esp), %eax -; CHECK-NEXT: je LBB3_2 +; CHECK-NEXT: je LBB2_2 +} + +; <rdar://problem/7598384>: +; +; jCC L1 +; jmp L2 +; L1: +; ... +; L2: +; ... +; +; to: +; +; jnCC L2 +; L1: +; ... +; L2: +; ... +define float @test4(float %x, float %y) nounwind readnone optsize ssp { +entry: + %0 = fpext float %x to double ; <double> [#uses=1] + %1 = fpext float %y to double ; <double> [#uses=1] + %2 = fmul double %0, %1 ; <double> [#uses=3] + %3 = fcmp oeq double %2, 0.000000e+00 ; <i1> [#uses=1] + br i1 %3, label %bb2, label %bb1 + +; CHECK: jne +; CHECK-NEXT: jnp +; CHECK-NOT: jmp +; CHECK: LBB + +bb1: ; preds = %entry + %4 = fadd double %2, -1.000000e+00 ; <double> [#uses=1] + br label %bb2 + +bb2: ; preds = %entry, %bb1 + %.0.in = phi double [ %4, %bb1 ], [ %2, %entry ] ; <double> [#uses=1] + %.0 = fptrunc double %.0.in to float ; <float> [#uses=1] + ret float %.0 } diff --git a/test/CodeGen/X86/const-select.ll b/test/CodeGen/X86/const-select.ll index ca8cc1464c77..665984ce28ed 100644 --- a/test/CodeGen/X86/const-select.ll +++ b/test/CodeGen/X86/const-select.ll @@ -2,7 +2,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin7" -; RUN: llc < %s | grep {LCPI1_0(,%eax,4)} +; RUN: llc < %s | grep {LCPI0_0(,%eax,4)} define float @f(i32 %x) nounwind readnone { entry: %0 = icmp eq i32 %x, 0 ; <i1> [#uses=1] diff --git a/test/CodeGen/X86/constant-pool-sharing.ll b/test/CodeGen/X86/constant-pool-sharing.ll index c3e97adffb19..33de5767ad65 100644 --- a/test/CodeGen/X86/constant-pool-sharing.ll +++ b/test/CodeGen/X86/constant-pool-sharing.ll @@ -3,7 +3,7 @@ ; llc should share constant pool entries between this integer vector ; and this floating-point vector since they have the same encoding. -; CHECK: LCPI1_0(%rip), %xmm0 +; CHECK: LCPI0_0(%rip), %xmm0 ; CHECK: movaps %xmm0, (%rdi) ; CHECK: movaps %xmm0, (%rsi) diff --git a/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll b/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll index 8e38fe309f7c..17cb2b305721 100644 --- a/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll +++ b/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=x86-64 -o %t -stats -info-output-file - | \ -; RUN: grep {asm-printer} | grep {Number of machine instrs printed} | grep 10 +; RUN: grep {asm-printer} | grep {Number of machine instrs printed} | grep 9 ; RUN: grep {leal 1(\%rsi),} %t define fastcc zeroext i8 @fullGtU(i32 %i1, i32 %i2, i8* %ptr) nounwind optsize { diff --git a/test/CodeGen/X86/crash.ll b/test/CodeGen/X86/crash.ll index 4b7c85099389..2f27f35f0acd 100644 --- a/test/CodeGen/X86/crash.ll +++ b/test/CodeGen/X86/crash.ll @@ -92,3 +92,41 @@ foo: } +; Crash commoning identical asms. +; PR6803 +define void @test6(i1 %C) nounwind optsize ssp { +entry: + br i1 %C, label %do.body55, label %do.body92 + +do.body55: ; preds = %if.else36 + call void asm sideeffect "foo", "~{dirflag},~{fpsr},~{flags}"() nounwind, !srcloc !0 + ret void + +do.body92: ; preds = %if.then66 + call void asm sideeffect "foo", "~{dirflag},~{fpsr},~{flags}"() nounwind, !srcloc !1 + ret void +} + +!0 = metadata !{i32 633550} +!1 = metadata !{i32 634261} + + +; Crash during XOR optimization. +; <rdar://problem/7869290> + +define void @test7() nounwind ssp { +entry: + br i1 undef, label %bb14, label %bb67 + +bb14: + %tmp0 = trunc i16 undef to i1 + %tmp1 = load i8* undef, align 8 + %tmp2 = shl i8 %tmp1, 4 + %tmp3 = lshr i8 %tmp2, 7 + %tmp4 = trunc i8 %tmp3 to i1 + %tmp5 = icmp ne i1 %tmp0, %tmp4 + br i1 %tmp5, label %bb14, label %bb67 + +bb67: + ret void +} diff --git a/test/CodeGen/X86/dbg-byval-parameter.ll b/test/CodeGen/X86/dbg-byval-parameter.ll new file mode 100644 index 000000000000..5e5577620d97 --- /dev/null +++ b/test/CodeGen/X86/dbg-byval-parameter.ll @@ -0,0 +1,45 @@ +; RUN: llc -march=x86 -asm-verbose < %s | grep DW_TAG_formal_parameter + + +%struct.Pt = type { double, double } +%struct.Rect = type { %struct.Pt, %struct.Pt } + +define double @foo(%struct.Rect* byval %my_r0) nounwind ssp { +entry: + %retval = alloca double ; <double*> [#uses=2] + %0 = alloca double ; <double*> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + call void @llvm.dbg.declare(metadata !{%struct.Rect* %my_r0}, metadata !0), !dbg !15 + %1 = getelementptr inbounds %struct.Rect* %my_r0, i32 0, i32 0, !dbg !16 ; <%struct.Pt*> [#uses=1] + %2 = getelementptr inbounds %struct.Pt* %1, i32 0, i32 0, !dbg !16 ; <double*> [#uses=1] + %3 = load double* %2, align 8, !dbg !16 ; <double> [#uses=1] + store double %3, double* %0, align 8, !dbg !16 + %4 = load double* %0, align 8, !dbg !16 ; <double> [#uses=1] + store double %4, double* %retval, align 8, !dbg !16 + br label %return, !dbg !16 + +return: ; preds = %entry + %retval1 = load double* %retval, !dbg !16 ; <double> [#uses=1] + ret double %retval1, !dbg !16 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +!0 = metadata !{i32 524545, metadata !1, metadata !"my_r0", metadata !2, i32 11, metadata !7} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 11, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 524329, metadata !"b2.c", metadata !"/tmp/", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"b2.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{metadata !6, metadata !7} +!6 = metadata !{i32 524324, metadata !2, metadata !"double", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 524307, metadata !2, metadata !"Rect", metadata !2, i32 6, i64 256, i64 64, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_structure_type ] +!8 = metadata !{metadata !9, metadata !14} +!9 = metadata !{i32 524301, metadata !7, metadata !"P1", metadata !2, i32 7, i64 128, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_member ] +!10 = metadata !{i32 524307, metadata !2, metadata !"Pt", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_structure_type ] +!11 = metadata !{metadata !12, metadata !13} +!12 = metadata !{i32 524301, metadata !10, metadata !"x", metadata !2, i32 2, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] +!13 = metadata !{i32 524301, metadata !10, metadata !"y", metadata !2, i32 3, i64 64, i64 64, i64 64, i32 0, metadata !6} ; [ DW_TAG_member ] +!14 = metadata !{i32 524301, metadata !7, metadata !"P2", metadata !2, i32 8, i64 128, i64 64, i64 128, i32 0, metadata !10} ; [ DW_TAG_member ] +!15 = metadata !{i32 11, i32 0, metadata !1, null} +!16 = metadata !{i32 12, i32 0, metadata !17, null} +!17 = metadata !{i32 524299, metadata !1, i32 11, i32 0} ; [ DW_TAG_lexical_block ] diff --git a/test/CodeGen/X86/dllexport.ll b/test/CodeGen/X86/dllexport.ll index 2c699bfb0db4..bdbaac05f118 100644 --- a/test/CodeGen/X86/dllexport.ll +++ b/test/CodeGen/X86/dllexport.ll @@ -9,4 +9,4 @@ entry: } ; CHECK: .section .drectve -; CHECK: -export:@foo@0
\ No newline at end of file +; CHECK: -export:@foo@0 diff --git a/test/CodeGen/X86/fast-isel-constpool.ll b/test/CodeGen/X86/fast-isel-constpool.ll index 84d10f32c294..323c8533cec2 100644 --- a/test/CodeGen/X86/fast-isel-constpool.ll +++ b/test/CodeGen/X86/fast-isel-constpool.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -fast-isel | grep {LCPI1_0(%rip)} +; RUN: llc < %s -fast-isel | grep {LCPI0_0(%rip)} ; Make sure fast isel uses rip-relative addressing when required. target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-apple-darwin9.0" diff --git a/test/CodeGen/X86/fast-isel-phys.ll b/test/CodeGen/X86/fast-isel-phys.ll deleted file mode 100644 index 158ef551ce42..000000000000 --- a/test/CodeGen/X86/fast-isel-phys.ll +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86 - -define i8 @t2(i8 %a, i8 %c) nounwind { - %tmp = shl i8 %a, %c - ret i8 %tmp -} - -define i8 @t1(i8 %a) nounwind { - %tmp = mul i8 %a, 17 - ret i8 %tmp -} diff --git a/test/CodeGen/X86/fast-isel-trunc.ll b/test/CodeGen/X86/fast-isel-trunc.ll deleted file mode 100644 index 69b26c5442e4..000000000000 --- a/test/CodeGen/X86/fast-isel-trunc.ll +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: llc < %s -march=x86 -fast-isel -fast-isel-abort -; RUN: llc < %s -march=x86-64 -fast-isel -fast-isel-abort - -define i8 @t1(i32 %x) signext nounwind { - %tmp1 = trunc i32 %x to i8 - ret i8 %tmp1 -} - -define i8 @t2(i16 signext %x) signext nounwind { - %tmp1 = trunc i16 %x to i8 - ret i8 %tmp1 -} diff --git a/test/CodeGen/X86/fast-isel.ll b/test/CodeGen/X86/fast-isel.ll index 84b3fd7caf3a..3d26ae7018b5 100644 --- a/test/CodeGen/X86/fast-isel.ll +++ b/test/CodeGen/X86/fast-isel.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86 -mattr=sse2 +; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86-64 ; This tests very minimal fast-isel functionality. @@ -65,6 +66,26 @@ define i8* @inttoptr_i32(i32 %p) nounwind { ret i8* %t } +define i8 @trunc_i32_i8(i32 %x) signext nounwind { + %tmp1 = trunc i32 %x to i8 + ret i8 %tmp1 +} + +define i8 @trunc_i16_i8(i16 signext %x) signext nounwind { + %tmp1 = trunc i16 %x to i8 + ret i8 %tmp1 +} + +define i8 @shl_i8(i8 %a, i8 %c) nounwind { + %tmp = shl i8 %a, %c + ret i8 %tmp +} + +define i8 @mul_i8(i8 %a) nounwind { + %tmp = mul i8 %a, 17 + ret i8 %tmp +} + define void @store_i1(i1* %p, i1 %t) nounwind { store i1 %t, i1* %p ret void diff --git a/test/CodeGen/X86/field-extract-use-trunc.ll b/test/CodeGen/X86/field-extract-use-trunc.ll index 60205305a977..735e1341f65b 100644 --- a/test/CodeGen/X86/field-extract-use-trunc.ll +++ b/test/CodeGen/X86/field-extract-use-trunc.ll @@ -1,38 +1,38 @@ ; RUN: llc < %s -march=x86 | grep sar | count 1 ; RUN: llc < %s -march=x86-64 | not grep sar -define i32 @test(i32 %f12) { +define i32 @test(i32 %f12) nounwind { %tmp7.25 = lshr i32 %f12, 16 %tmp7.26 = trunc i32 %tmp7.25 to i8 %tmp78.2 = sext i8 %tmp7.26 to i32 ret i32 %tmp78.2 } -define i32 @test2(i32 %f12) { +define i32 @test2(i32 %f12) nounwind { %f11 = shl i32 %f12, 8 %tmp7.25 = ashr i32 %f11, 24 ret i32 %tmp7.25 } -define i32 @test3(i32 %f12) { +define i32 @test3(i32 %f12) nounwind { %f11 = shl i32 %f12, 13 %tmp7.25 = ashr i32 %f11, 24 ret i32 %tmp7.25 } -define i64 @test4(i64 %f12) { +define i64 @test4(i64 %f12) nounwind { %f11 = shl i64 %f12, 32 %tmp7.25 = ashr i64 %f11, 32 ret i64 %tmp7.25 } -define i16 @test5(i16 %f12) { +define i16 @test5(i16 %f12) nounwind { %f11 = shl i16 %f12, 2 %tmp7.25 = ashr i16 %f11, 8 ret i16 %tmp7.25 } -define i16 @test6(i16 %f12) { +define i16 @test6(i16 %f12) nounwind { %f11 = shl i16 %f12, 8 %tmp7.25 = ashr i16 %f11, 8 ret i16 %tmp7.25 diff --git a/test/CodeGen/X86/fold-pcmpeqd-0.ll b/test/CodeGen/X86/fold-pcmpeqd-0.ll index ef5202f554c5..e5be58e1aaa3 100644 --- a/test/CodeGen/X86/fold-pcmpeqd-0.ll +++ b/test/CodeGen/X86/fold-pcmpeqd-0.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | not grep pcmpeqd -; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | grep orps | grep CPI1_2 | count 2 +; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | grep orps | grep CPI0_2 | count 2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep pcmpeqd | count 1 ; This testcase shouldn't need to spill the -1 value, diff --git a/test/CodeGen/X86/fp-elim.ll b/test/CodeGen/X86/fp-elim.ll new file mode 100644 index 000000000000..60892a2352fb --- /dev/null +++ b/test/CodeGen/X86/fp-elim.ll @@ -0,0 +1,44 @@ +; RUN: llc < %s -march=x86 -asm-verbose=false | FileCheck %s -check-prefix=FP-ELIM +; RUN: llc < %s -march=x86 -asm-verbose=false -disable-fp-elim | FileCheck %s -check-prefix=NO-ELIM +; RUN: llc < %s -march=x86 -asm-verbose=false -disable-non-leaf-fp-elim | FileCheck %s -check-prefix=NON-LEAF + +; Implement -momit-leaf-frame-pointer +; rdar://7886181 + +define i32 @t1() nounwind readnone { +entry: +; FP-ELIM: t1: +; FP-ELIM-NEXT: movl +; FP-ELIM-NEXT: ret + +; NO-ELIM: t1: +; NO-ELIM-NEXT: pushl %ebp +; NO-ELIM: popl %ebp +; NO-ELIM-NEXT: ret + +; NON-LEAF: t1: +; NON-LEAF-NEXT: movl +; NON-LEAF-NEXT: ret + ret i32 10 +} + +define void @t2() nounwind { +entry: +; FP-ELIM: t2: +; FP-ELIM-NOT: pushl %ebp +; FP-ELIM: ret + +; NO-ELIM: t2: +; NO-ELIM-NEXT: pushl %ebp +; NO-ELIM: popl %ebp +; NO-ELIM-NEXT: ret + +; NON-LEAF: t2: +; NON-LEAF-NEXT: pushl %ebp +; NON-LEAF: popl %ebp +; NON-LEAF-NEXT: ret + tail call void @foo(i32 0) nounwind + ret void +} + +declare void @foo(i32) diff --git a/test/CodeGen/X86/global-sections.ll b/test/CodeGen/X86/global-sections.ll index d79c56bc4637..6d211913b015 100644 --- a/test/CodeGen/X86/global-sections.ll +++ b/test/CodeGen/X86/global-sections.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -mtriple=i386-unknown-linux-gnu | FileCheck %s -check-prefix=LINUX ; RUN: llc < %s -mtriple=i386-apple-darwin9.7 | FileCheck %s -check-prefix=DARWIN +; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -fdata-sections | FileCheck %s -check-prefix=LINUX-SECTIONS ; int G1; @@ -32,6 +33,12 @@ ; DARWIN: _G3: ; DARWIN: .long _G1 +; LINUX: .section .rodata,"a",@progbits +; LINUX: .globl G3 + +; LINUX-SECTIONS: .section .rodata.G3,"a",@progbits +; LINUX-SECTIONS: .globl G3 + ; _Complex long long const G4 = 34; @G4 = constant {i64,i64} { i64 34, i64 0 } @@ -97,6 +104,9 @@ ; LINUX: G7: ; LINUX: .asciz "abcdefghi" +; LINUX-SECTIONS: .section .rodata.G7,"aMS",@progbits,1 +; LINUX-SECTIONS: .globl G7 + @G8 = constant [4 x i16] [ i16 1, i16 2, i16 3, i16 0 ] @@ -134,3 +144,17 @@ ; LINUX: G10: ; LINUX: .zero 400 + + +;; Zero sized objects should round up to 1 byte in zerofill directives. +; rdar://7886017 +@G11 = global [0 x i32] zeroinitializer +@G12 = global {} zeroinitializer +@G13 = global { [0 x {}] } zeroinitializer + +; DARWIN: .globl _G11 +; DARWIN: .zerofill __DATA,__common,_G11,1,2 +; DARWIN: .globl _G12 +; DARWIN: .zerofill __DATA,__common,_G12,1,3 +; DARWIN: .globl _G13 +; DARWIN: .zerofill __DATA,__common,_G13,1,3 diff --git a/test/CodeGen/X86/h-registers-0.ll b/test/CodeGen/X86/h-registers-0.ll index 878fd93b737c..e84bb9a34a26 100644 --- a/test/CodeGen/X86/h-registers-0.ll +++ b/test/CodeGen/X86/h-registers-0.ll @@ -1,12 +1,16 @@ -; RUN: llc < %s -march=x86-64 | grep {movzbl %\[abcd\]h,} | count 4 -; RUN: llc < %s -march=x86 > %t -; RUN: grep {incb %ah} %t | count 3 -; RUN: grep {movzbl %ah,} %t | count 3 +; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X86-64 +; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X86-32 ; Use h registers. On x86-64, codegen doesn't support general allocation ; of h registers yet, due to x86 encoding complications. define void @bar64(i64 inreg %x, i8* inreg %p) nounwind { +; X86-64: bar64: +; X86-64: shrq $8, %rdi +; X86-64: incb %dil + +; X86-32: bar64: +; X86-32: incb %ah %t0 = lshr i64 %x, 8 %t1 = trunc i64 %t0 to i8 %t2 = add i8 %t1, 1 @@ -15,6 +19,12 @@ define void @bar64(i64 inreg %x, i8* inreg %p) nounwind { } define void @bar32(i32 inreg %x, i8* inreg %p) nounwind { +; X86-64: bar32: +; X86-64: shrl $8, %edi +; X86-64: incb %dil + +; X86-32: bar32: +; X86-32: incb %ah %t0 = lshr i32 %x, 8 %t1 = trunc i32 %t0 to i8 %t2 = add i8 %t1, 1 @@ -23,6 +33,12 @@ define void @bar32(i32 inreg %x, i8* inreg %p) nounwind { } define void @bar16(i16 inreg %x, i8* inreg %p) nounwind { +; X86-64: bar16: +; X86-64: shrl $8, %edi +; X86-64: incb %dil + +; X86-32: bar16: +; X86-32: incb %ah %t0 = lshr i16 %x, 8 %t1 = trunc i16 %t0 to i8 %t2 = add i8 %t1, 1 @@ -31,18 +47,36 @@ define void @bar16(i16 inreg %x, i8* inreg %p) nounwind { } define i64 @qux64(i64 inreg %x) nounwind { +; X86-64: qux64: +; X86-64: movq %rdi, %rax +; X86-64: movzbl %ah, %eax + +; X86-32: qux64: +; X86-32: movzbl %ah, %eax %t0 = lshr i64 %x, 8 %t1 = and i64 %t0, 255 ret i64 %t1 } define i32 @qux32(i32 inreg %x) nounwind { +; X86-64: qux32: +; X86-64: movl %edi, %eax +; X86-64: movzbl %ah, %eax + +; X86-32: qux32: +; X86-32: movzbl %ah, %eax %t0 = lshr i32 %x, 8 %t1 = and i32 %t0, 255 ret i32 %t1 } define i16 @qux16(i16 inreg %x) nounwind { +; X86-64: qux16: +; X86-64: movl %edi, %eax +; X86-64: movzbl %ah, %eax + +; X86-32: qux16: +; X86-32: movzbl %ah, %eax %t0 = lshr i16 %x, 8 ret i16 %t0 } diff --git a/test/CodeGen/X86/ins_subreg_coalesce-1.ll b/test/CodeGen/X86/ins_subreg_coalesce-1.ll index 2243f93f3ddd..83674361a773 100644 --- a/test/CodeGen/X86/ins_subreg_coalesce-1.ll +++ b/test/CodeGen/X86/ins_subreg_coalesce-1.ll @@ -1,7 +1,13 @@ -; RUN: llc < %s -march=x86 | grep mov | count 3 +; RUN: llc < %s -march=x86 | FileCheck %s -define fastcc i32 @sqlite3ExprResolveNames() nounwind { +define fastcc i32 @t() nounwind { entry: +; CHECK: t: +; CHECK: movzwl 0, %eax +; CHECK: orl $2, %eax +; CHECK: movw %ax, 0 +; CHECK: shrl $3, %eax +; CHECK: andl $1, %eax br i1 false, label %UnifiedReturnBlock, label %bb4 bb4: ; preds = %entry br i1 false, label %bb17, label %bb22 diff --git a/test/CodeGen/X86/loop-blocks.ll b/test/CodeGen/X86/loop-blocks.ll index a125e54050bb..354d08206972 100644 --- a/test/CodeGen/X86/loop-blocks.ll +++ b/test/CodeGen/X86/loop-blocks.ll @@ -7,11 +7,11 @@ ; order to avoid a branch within the loop. ; CHECK: simple: -; CHECK: jmp .LBB1_1 +; CHECK: jmp .LBB0_1 ; CHECK-NEXT: align -; CHECK-NEXT: .LBB1_2: +; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: callq loop_latch -; CHECK-NEXT: .LBB1_1: +; CHECK-NEXT: .LBB0_1: ; CHECK-NEXT: callq loop_header define void @simple() nounwind { @@ -37,11 +37,11 @@ done: ; falls through into the loop, avoiding a branch within the loop. ; CHECK: slightly_more_involved: -; CHECK: jmp .LBB2_1 +; CHECK: jmp .LBB1_1 ; CHECK-NEXT: align -; CHECK-NEXT: .LBB2_4: +; CHECK-NEXT: .LBB1_4: ; CHECK-NEXT: callq bar99 -; CHECK-NEXT: .LBB2_1: +; CHECK-NEXT: .LBB1_1: ; CHECK-NEXT: callq body define void @slightly_more_involved() nounwind { @@ -72,20 +72,20 @@ exit: ; fallthrough edges which should be preserved. ; CHECK: yet_more_involved: -; CHECK: jmp .LBB3_1 +; CHECK: jmp .LBB2_1 ; CHECK-NEXT: align -; CHECK-NEXT: .LBB3_4: +; CHECK-NEXT: .LBB2_4: ; CHECK-NEXT: callq bar99 ; CHECK-NEXT: callq get ; CHECK-NEXT: cmpl $2999, %eax -; CHECK-NEXT: jg .LBB3_6 +; CHECK-NEXT: jg .LBB2_6 ; CHECK-NEXT: callq block_a_true_func -; CHECK-NEXT: jmp .LBB3_7 -; CHECK-NEXT: .LBB3_6: +; CHECK-NEXT: jmp .LBB2_7 +; CHECK-NEXT: .LBB2_6: ; CHECK-NEXT: callq block_a_false_func -; CHECK-NEXT: .LBB3_7: +; CHECK-NEXT: .LBB2_7: ; CHECK-NEXT: callq block_a_merge_func -; CHECK-NEXT: .LBB3_1: +; CHECK-NEXT: .LBB2_1: ; CHECK-NEXT: callq body define void @yet_more_involved() nounwind { @@ -131,20 +131,20 @@ exit: ; loop. ; CHECK: cfg_islands: -; CHECK: jmp .LBB4_1 +; CHECK: jmp .LBB3_1 ; CHECK-NEXT: align -; CHECK-NEXT: .LBB4_7: +; CHECK-NEXT: .LBB3_7: ; CHECK-NEXT: callq bar100 -; CHECK-NEXT: jmp .LBB4_1 -; CHECK-NEXT: .LBB4_8: +; CHECK-NEXT: jmp .LBB3_1 +; CHECK-NEXT: .LBB3_8: ; CHECK-NEXT: callq bar101 -; CHECK-NEXT: jmp .LBB4_1 -; CHECK-NEXT: .LBB4_9: +; CHECK-NEXT: jmp .LBB3_1 +; CHECK-NEXT: .LBB3_9: ; CHECK-NEXT: callq bar102 -; CHECK-NEXT: jmp .LBB4_1 -; CHECK-NEXT: .LBB4_5: +; CHECK-NEXT: jmp .LBB3_1 +; CHECK-NEXT: .LBB3_5: ; CHECK-NEXT: callq loop_latch -; CHECK-NEXT: .LBB4_1: +; CHECK-NEXT: .LBB3_1: ; CHECK-NEXT: callq loop_header define void @cfg_islands() nounwind { diff --git a/test/CodeGen/X86/loop-hoist.ll b/test/CodeGen/X86/loop-hoist.ll index b9008e5e3022..c103e29f3bf3 100644 --- a/test/CodeGen/X86/loop-hoist.ll +++ b/test/CodeGen/X86/loop-hoist.ll @@ -4,7 +4,7 @@ ; CHECK: _foo: ; CHECK: L_Arr$non_lazy_ptr -; CHECK: LBB1_1: +; CHECK: LBB0_1: @Arr = external global [0 x i32] ; <[0 x i32]*> [#uses=1] diff --git a/test/CodeGen/X86/loop-strength-reduce8.ll b/test/CodeGen/X86/loop-strength-reduce8.ll index 6b2247d1d619..1d042769b0ba 100644 --- a/test/CodeGen/X86/loop-strength-reduce8.ll +++ b/test/CodeGen/X86/loop-strength-reduce8.ll @@ -4,7 +4,7 @@ ; CHECK: align ; CHECK: addl $4, %edx ; CHECK: decl %ecx -; CHECK: jne LBB1_2 +; CHECK: jne LBB0_2 %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32 } %struct.bitmap_element = type { %struct.bitmap_element*, %struct.bitmap_element*, i32, [2 x i64] } diff --git a/test/CodeGen/X86/lsr-delayed-fold.ll b/test/CodeGen/X86/lsr-delayed-fold.ll new file mode 100644 index 000000000000..17d6a4c0915f --- /dev/null +++ b/test/CodeGen/X86/lsr-delayed-fold.ll @@ -0,0 +1,51 @@ +; RUN: llc -march=x86-64 < %s > /dev/null + +; ScalarEvolution misses an opportunity to fold ((trunc x) + (trunc -x) + y), +; but LSR should tolerate this. +; rdar://7886751 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin11.0" + +define fastcc void @formatValue(i64 %arg5) nounwind { +bb12: ; preds = %bb11 + %t = trunc i64 %arg5 to i32 ; <i32> [#uses=1] + %t13 = sub i64 0, %arg5 ; <i64> [#uses=1] + %t14 = and i64 %t13, 4294967295 ; <i64> [#uses=1] + br label %bb15 + +bb15: ; preds = %bb21, %bb12 + %t16 = phi i64 [ 0, %bb12 ], [ %t23, %bb15 ] ; <i64> [#uses=2] + %t17 = mul i64 %t14, %t16 ; <i64> [#uses=1] + %t18 = add i64 undef, %t17 ; <i64> [#uses=1] + %t19 = trunc i64 %t18 to i32 ; <i32> [#uses=1] + %t22 = icmp eq i32 %t19, %t ; <i1> [#uses=1] + %t23 = add i64 %t16, 1 ; <i64> [#uses=1] + br i1 %t22, label %bb24, label %bb15 + +bb24: ; preds = %bb21, %bb11 + unreachable +} + +; ScalarEvolution should be able to correctly expand the crazy addrec here. +; PR6914 + +define void @int323() nounwind { +entry: + br label %for.cond + +for.cond: ; preds = %lbl_264, %for.inc, %entry + %g_263.tmp.1 = phi i8 [ undef, %entry ], [ %g_263.tmp.1, %for.cond ] + %p_95.addr.0 = phi i8 [ 0, %entry ], [ %add, %for.cond ] + %add = add i8 %p_95.addr.0, 1 ; <i8> [#uses=1] + br i1 undef, label %for.cond, label %lbl_264 + +lbl_264: ; preds = %if.end, %lbl_264.preheader + %g_263.tmp.0 = phi i8 [ %g_263.tmp.1, %for.cond ] ; <i8> [#uses=1] + %tmp7 = load i16* undef ; <i16> [#uses=1] + %conv8 = trunc i16 %tmp7 to i8 ; <i8> [#uses=1] + %mul.i = mul i8 %p_95.addr.0, %p_95.addr.0 ; <i8> [#uses=1] + %mul.i18 = mul i8 %mul.i, %conv8 ; <i8> [#uses=1] + %tobool12 = icmp eq i8 %mul.i18, 0 ; <i1> [#uses=1] + unreachable +} diff --git a/test/CodeGen/X86/lsr-reuse.ll b/test/CodeGen/X86/lsr-reuse.ll index ab71555950b2..b80ee0897d89 100644 --- a/test/CodeGen/X86/lsr-reuse.ll +++ b/test/CodeGen/X86/lsr-reuse.ll @@ -260,7 +260,7 @@ return: ; CHECK: count_me_2: ; CHECK: movl $10, %eax ; CHECK: align -; CHECK: BB7_1: +; CHECK: BB6_1: ; CHECK: movsd -40(%rdi,%rax,8), %xmm0 ; CHECK: addsd -40(%rsi,%rax,8), %xmm0 ; CHECK: movsd %xmm0, -40(%rdx,%rax,8) @@ -305,7 +305,7 @@ return: ; CHECK: full_me_1: ; CHECK: align -; CHECK: BB8_1: +; CHECK: BB7_1: ; CHECK: movsd (%rdi), %xmm0 ; CHECK: addsd (%rsi), %xmm0 ; CHECK: movsd %xmm0, (%rdx) @@ -389,7 +389,7 @@ return: ; rdar://7657764 ; CHECK: asd: -; CHECK: BB10_5: +; CHECK: BB9_5: ; CHECK-NEXT: addl (%r{{[^,]*}},%rdi,4), %e ; CHECK-NEXT: incq %rdi ; CHECK-NEXT: cmpq %rdi, %r{{[^,]*}} diff --git a/test/CodeGen/X86/memcpy-2.ll b/test/CodeGen/X86/memcpy-2.ll index 4fe32d974d05..17cd8e868a25 100644 --- a/test/CodeGen/X86/memcpy-2.ll +++ b/test/CodeGen/X86/memcpy-2.ll @@ -3,20 +3,20 @@ ; RUN: llc < %s -mattr=-sse -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=NOSSE ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=X86-64 - %struct.ParmT = type { [25 x i8], i8, i8* } -@.str12 = internal constant [25 x i8] c"image\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00" ; <[25 x i8]*> [#uses=1] +@.str = internal constant [25 x i8] c"image\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00" +@.str2 = internal constant [30 x i8] c"xxxxxxxxxxxxxxxxxxxxxxxxxxxxx\00", align 4 define void @t1(i32 %argc, i8** %argv) nounwind { entry: ; SSE2: t1: -; SSE2: movaps _.str12, %xmm0 +; SSE2: movaps _.str, %xmm0 ; SSE2: movaps %xmm0 ; SSE2: movb $0 ; SSE2: movl $0 ; SSE2: movl $0 ; SSE1: t1: -; SSE1: movaps _.str12, %xmm0 +; SSE1: movaps _.str, %xmm0 ; SSE1: movaps %xmm0 ; SSE1: movb $0 ; SSE1: movl $0 @@ -32,14 +32,14 @@ entry: ; NOSSE: movl $1734438249 ; X86-64: t1: -; X86-64: movaps _.str12(%rip), %xmm0 +; X86-64: movaps _.str(%rip), %xmm0 ; X86-64: movaps %xmm0 ; X86-64: movb $0 ; X86-64: movq $0 - %parms.i = alloca [13 x %struct.ParmT] ; <[13 x %struct.ParmT]*> [#uses=1] - %parms1.i = getelementptr [13 x %struct.ParmT]* %parms.i, i32 0, i32 0, i32 0, i32 0 ; <i8*> [#uses=1] - call void @llvm.memcpy.i32( i8* %parms1.i, i8* getelementptr ([25 x i8]* @.str12, i32 0, i32 0), i32 25, i32 1 ) nounwind - unreachable + %tmp1 = alloca [25 x i8] + %tmp2 = bitcast [25 x i8]* %tmp1 to i8* + call void @llvm.memcpy.i32( i8* %tmp2, i8* getelementptr ([25 x i8]* @.str, i32 0, i32 0), i32 25, i32 1 ) nounwind + unreachable } ;rdar://7774704 @@ -119,4 +119,49 @@ entry: ret void } +define void @t4() nounwind { +entry: +; SSE2: t4: +; SSE2: movw $120 +; SSE2: movl $2021161080 +; SSE2: movl $2021161080 +; SSE2: movl $2021161080 +; SSE2: movl $2021161080 +; SSE2: movl $2021161080 +; SSE2: movl $2021161080 +; SSE2: movl $2021161080 + +; SSE1: t4: +; SSE1: movw $120 +; SSE1: movl $2021161080 +; SSE1: movl $2021161080 +; SSE1: movl $2021161080 +; SSE1: movl $2021161080 +; SSE1: movl $2021161080 +; SSE1: movl $2021161080 +; SSE1: movl $2021161080 + +; NOSSE: t4: +; NOSSE: movw $120 +; NOSSE: movl $2021161080 +; NOSSE: movl $2021161080 +; NOSSE: movl $2021161080 +; NOSSE: movl $2021161080 +; NOSSE: movl $2021161080 +; NOSSE: movl $2021161080 +; NOSSE: movl $2021161080 + +; X86-64: t4: +; X86-64: movabsq $8680820740569200760, %rax +; X86-64: movq %rax +; X86-64: movq %rax +; X86-64: movq %rax +; X86-64: movw $120 +; X86-64: movl $2021161080 + %tmp1 = alloca [30 x i8] + %tmp2 = bitcast [30 x i8]* %tmp1 to i8* + call void @llvm.memcpy.i32(i8* %tmp2, i8* getelementptr inbounds ([30 x i8]* @.str2, i32 0, i32 0), i32 30, i32 1) + unreachable +} + declare void @llvm.memcpy.i32(i8* nocapture, i8* nocapture, i32, i32) nounwind diff --git a/test/CodeGen/X86/multiple-loop-post-inc.ll b/test/CodeGen/X86/multiple-loop-post-inc.ll new file mode 100644 index 000000000000..51a06112aada --- /dev/null +++ b/test/CodeGen/X86/multiple-loop-post-inc.ll @@ -0,0 +1,304 @@ +; RUN: llc -asm-verbose=false -disable-branch-fold -disable-code-place -disable-tail-duplicate -march=x86-64 < %s | FileCheck %s +; rdar://7236213 + +; CodeGen shouldn't require any lea instructions inside the marked loop. +; It should properly set up post-increment uses and do coalescing for +; the induction variables. + +; CHECK: # Start +; CHECK-NOT: lea +; CHECK: # Stop + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" + +define void @foo(float* %I, i64 %IS, float* nocapture %Start, float* nocapture %Step, float* %O, i64 %OS, i64 %N) nounwind { +entry: + %times4 = alloca float, align 4 ; <float*> [#uses=3] + %timesN = alloca float, align 4 ; <float*> [#uses=2] + %0 = load float* %Step, align 4 ; <float> [#uses=8] + %1 = ptrtoint float* %I to i64 ; <i64> [#uses=1] + %2 = ptrtoint float* %O to i64 ; <i64> [#uses=1] + %tmp = xor i64 %2, %1 ; <i64> [#uses=1] + %tmp16 = and i64 %tmp, 15 ; <i64> [#uses=1] + %3 = icmp eq i64 %tmp16, 0 ; <i1> [#uses=1] + %4 = trunc i64 %IS to i32 ; <i32> [#uses=1] + %5 = xor i32 %4, 1 ; <i32> [#uses=1] + %6 = trunc i64 %OS to i32 ; <i32> [#uses=1] + %7 = xor i32 %6, 1 ; <i32> [#uses=1] + %8 = or i32 %7, %5 ; <i32> [#uses=1] + %9 = icmp eq i32 %8, 0 ; <i1> [#uses=1] + br i1 %9, label %bb, label %return + +bb: ; preds = %entry + %10 = load float* %Start, align 4 ; <float> [#uses=1] + br label %bb2 + +bb1: ; preds = %bb3 + %11 = load float* %I_addr.0, align 4 ; <float> [#uses=1] + %12 = fmul float %11, %x.0 ; <float> [#uses=1] + store float %12, float* %O_addr.0, align 4 + %13 = fadd float %x.0, %0 ; <float> [#uses=1] + %indvar.next53 = add i64 %14, 1 ; <i64> [#uses=1] + br label %bb2 + +bb2: ; preds = %bb1, %bb + %14 = phi i64 [ %indvar.next53, %bb1 ], [ 0, %bb ] ; <i64> [#uses=21] + %x.0 = phi float [ %13, %bb1 ], [ %10, %bb ] ; <float> [#uses=6] + %N_addr.0 = sub i64 %N, %14 ; <i64> [#uses=4] + %O_addr.0 = getelementptr float* %O, i64 %14 ; <float*> [#uses=4] + %I_addr.0 = getelementptr float* %I, i64 %14 ; <float*> [#uses=3] + %15 = icmp slt i64 %N_addr.0, 1 ; <i1> [#uses=1] + br i1 %15, label %bb4, label %bb3 + +bb3: ; preds = %bb2 + %16 = ptrtoint float* %O_addr.0 to i64 ; <i64> [#uses=1] + %17 = and i64 %16, 15 ; <i64> [#uses=1] + %18 = icmp eq i64 %17, 0 ; <i1> [#uses=1] + br i1 %18, label %bb4, label %bb1 + +bb4: ; preds = %bb3, %bb2 + %19 = fmul float %0, 4.000000e+00 ; <float> [#uses=1] + store float %19, float* %times4, align 4 + %20 = fmul float %0, 1.600000e+01 ; <float> [#uses=1] + store float %20, float* %timesN, align 4 + %21 = fmul float %0, 0.000000e+00 ; <float> [#uses=1] + %22 = fadd float %21, %x.0 ; <float> [#uses=1] + %23 = fadd float %x.0, %0 ; <float> [#uses=1] + %24 = fmul float %0, 2.000000e+00 ; <float> [#uses=1] + %25 = fadd float %24, %x.0 ; <float> [#uses=1] + %26 = fmul float %0, 3.000000e+00 ; <float> [#uses=1] + %27 = fadd float %26, %x.0 ; <float> [#uses=1] + %28 = insertelement <4 x float> undef, float %22, i32 0 ; <<4 x float>> [#uses=1] + %29 = insertelement <4 x float> %28, float %23, i32 1 ; <<4 x float>> [#uses=1] + %30 = insertelement <4 x float> %29, float %25, i32 2 ; <<4 x float>> [#uses=1] + %31 = insertelement <4 x float> %30, float %27, i32 3 ; <<4 x float>> [#uses=5] + %asmtmp.i = call <4 x float> asm "movss $1, $0\09\0Apshufd $$0, $0, $0", "=x,*m,~{dirflag},~{fpsr},~{flags}"(float* %times4) nounwind ; <<4 x float>> [#uses=3] + %32 = fadd <4 x float> %31, %asmtmp.i ; <<4 x float>> [#uses=3] + %33 = fadd <4 x float> %32, %asmtmp.i ; <<4 x float>> [#uses=3] + %34 = fadd <4 x float> %33, %asmtmp.i ; <<4 x float>> [#uses=2] + %asmtmp.i18 = call <4 x float> asm "movss $1, $0\09\0Apshufd $$0, $0, $0", "=x,*m,~{dirflag},~{fpsr},~{flags}"(float* %timesN) nounwind ; <<4 x float>> [#uses=8] + %35 = icmp sgt i64 %N_addr.0, 15 ; <i1> [#uses=2] + br i1 %3, label %bb6.preheader, label %bb8 + +bb6.preheader: ; preds = %bb4 + br i1 %35, label %bb.nph43, label %bb7 + +bb.nph43: ; preds = %bb6.preheader + %tmp108 = add i64 %14, 16 ; <i64> [#uses=1] + %tmp111 = add i64 %14, 4 ; <i64> [#uses=1] + %tmp115 = add i64 %14, 8 ; <i64> [#uses=1] + %tmp119 = add i64 %14, 12 ; <i64> [#uses=1] + %tmp134 = add i64 %N, -16 ; <i64> [#uses=1] + %tmp135 = sub i64 %tmp134, %14 ; <i64> [#uses=1] + call void asm sideeffect "# Start.", "~{dirflag},~{fpsr},~{flags}"() nounwind + br label %bb5 + +bb5: ; preds = %bb.nph43, %bb5 + %indvar102 = phi i64 [ 0, %bb.nph43 ], [ %indvar.next103, %bb5 ] ; <i64> [#uses=3] + %vX3.041 = phi <4 x float> [ %34, %bb.nph43 ], [ %45, %bb5 ] ; <<4 x float>> [#uses=2] + %vX0.039 = phi <4 x float> [ %31, %bb.nph43 ], [ %41, %bb5 ] ; <<4 x float>> [#uses=2] + %vX2.037 = phi <4 x float> [ %33, %bb.nph43 ], [ %46, %bb5 ] ; <<4 x float>> [#uses=2] + %vX1.036 = phi <4 x float> [ %32, %bb.nph43 ], [ %47, %bb5 ] ; <<4 x float>> [#uses=2] + %tmp104 = shl i64 %indvar102, 4 ; <i64> [#uses=5] + %tmp105 = add i64 %14, %tmp104 ; <i64> [#uses=2] + %scevgep106 = getelementptr float* %I, i64 %tmp105 ; <float*> [#uses=1] + %scevgep106107 = bitcast float* %scevgep106 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp109 = add i64 %tmp108, %tmp104 ; <i64> [#uses=2] + %tmp112 = add i64 %tmp111, %tmp104 ; <i64> [#uses=2] + %scevgep113 = getelementptr float* %I, i64 %tmp112 ; <float*> [#uses=1] + %scevgep113114 = bitcast float* %scevgep113 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp116 = add i64 %tmp115, %tmp104 ; <i64> [#uses=2] + %scevgep117 = getelementptr float* %I, i64 %tmp116 ; <float*> [#uses=1] + %scevgep117118 = bitcast float* %scevgep117 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp120 = add i64 %tmp119, %tmp104 ; <i64> [#uses=2] + %scevgep121 = getelementptr float* %I, i64 %tmp120 ; <float*> [#uses=1] + %scevgep121122 = bitcast float* %scevgep121 to <4 x float>* ; <<4 x float>*> [#uses=1] + %scevgep123 = getelementptr float* %O, i64 %tmp105 ; <float*> [#uses=1] + %scevgep123124 = bitcast float* %scevgep123 to <4 x float>* ; <<4 x float>*> [#uses=1] + %scevgep126 = getelementptr float* %O, i64 %tmp112 ; <float*> [#uses=1] + %scevgep126127 = bitcast float* %scevgep126 to <4 x float>* ; <<4 x float>*> [#uses=1] + %scevgep128 = getelementptr float* %O, i64 %tmp116 ; <float*> [#uses=1] + %scevgep128129 = bitcast float* %scevgep128 to <4 x float>* ; <<4 x float>*> [#uses=1] + %scevgep130 = getelementptr float* %O, i64 %tmp120 ; <float*> [#uses=1] + %scevgep130131 = bitcast float* %scevgep130 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp132 = mul i64 %indvar102, -16 ; <i64> [#uses=1] + %tmp136 = add i64 %tmp135, %tmp132 ; <i64> [#uses=2] + %36 = load <4 x float>* %scevgep106107, align 16 ; <<4 x float>> [#uses=1] + %37 = load <4 x float>* %scevgep113114, align 16 ; <<4 x float>> [#uses=1] + %38 = load <4 x float>* %scevgep117118, align 16 ; <<4 x float>> [#uses=1] + %39 = load <4 x float>* %scevgep121122, align 16 ; <<4 x float>> [#uses=1] + %40 = fmul <4 x float> %36, %vX0.039 ; <<4 x float>> [#uses=1] + %41 = fadd <4 x float> %vX0.039, %asmtmp.i18 ; <<4 x float>> [#uses=2] + %42 = fmul <4 x float> %37, %vX1.036 ; <<4 x float>> [#uses=1] + %43 = fmul <4 x float> %38, %vX2.037 ; <<4 x float>> [#uses=1] + %44 = fmul <4 x float> %39, %vX3.041 ; <<4 x float>> [#uses=1] + store <4 x float> %40, <4 x float>* %scevgep123124, align 16 + store <4 x float> %42, <4 x float>* %scevgep126127, align 16 + store <4 x float> %43, <4 x float>* %scevgep128129, align 16 + store <4 x float> %44, <4 x float>* %scevgep130131, align 16 + %45 = fadd <4 x float> %vX3.041, %asmtmp.i18 ; <<4 x float>> [#uses=1] + %46 = fadd <4 x float> %vX2.037, %asmtmp.i18 ; <<4 x float>> [#uses=1] + %47 = fadd <4 x float> %vX1.036, %asmtmp.i18 ; <<4 x float>> [#uses=1] + %48 = icmp sgt i64 %tmp136, 15 ; <i1> [#uses=1] + %indvar.next103 = add i64 %indvar102, 1 ; <i64> [#uses=1] + br i1 %48, label %bb5, label %bb6.bb7_crit_edge + +bb6.bb7_crit_edge: ; preds = %bb5 + call void asm sideeffect "# Stop.", "~{dirflag},~{fpsr},~{flags}"() nounwind + %scevgep110 = getelementptr float* %I, i64 %tmp109 ; <float*> [#uses=1] + %scevgep125 = getelementptr float* %O, i64 %tmp109 ; <float*> [#uses=1] + br label %bb7 + +bb7: ; preds = %bb6.bb7_crit_edge, %bb6.preheader + %I_addr.1.lcssa = phi float* [ %scevgep110, %bb6.bb7_crit_edge ], [ %I_addr.0, %bb6.preheader ] ; <float*> [#uses=1] + %O_addr.1.lcssa = phi float* [ %scevgep125, %bb6.bb7_crit_edge ], [ %O_addr.0, %bb6.preheader ] ; <float*> [#uses=1] + %vX0.0.lcssa = phi <4 x float> [ %41, %bb6.bb7_crit_edge ], [ %31, %bb6.preheader ] ; <<4 x float>> [#uses=1] + %N_addr.1.lcssa = phi i64 [ %tmp136, %bb6.bb7_crit_edge ], [ %N_addr.0, %bb6.preheader ] ; <i64> [#uses=1] + %asmtmp.i17 = call <4 x float> asm "movss $1, $0\09\0Apshufd $$0, $0, $0", "=x,*m,~{dirflag},~{fpsr},~{flags}"(float* %times4) nounwind ; <<4 x float>> [#uses=0] + br label %bb11 + +bb8: ; preds = %bb4 + br i1 %35, label %bb.nph, label %bb11 + +bb.nph: ; preds = %bb8 + %I_addr.0.sum = add i64 %14, -1 ; <i64> [#uses=1] + %49 = getelementptr inbounds float* %I, i64 %I_addr.0.sum ; <float*> [#uses=1] + %50 = bitcast float* %49 to <4 x float>* ; <<4 x float>*> [#uses=1] + %51 = load <4 x float>* %50, align 16 ; <<4 x float>> [#uses=1] + %tmp54 = add i64 %14, 16 ; <i64> [#uses=1] + %tmp56 = add i64 %14, 3 ; <i64> [#uses=1] + %tmp60 = add i64 %14, 7 ; <i64> [#uses=1] + %tmp64 = add i64 %14, 11 ; <i64> [#uses=1] + %tmp68 = add i64 %14, 15 ; <i64> [#uses=1] + %tmp76 = add i64 %14, 4 ; <i64> [#uses=1] + %tmp80 = add i64 %14, 8 ; <i64> [#uses=1] + %tmp84 = add i64 %14, 12 ; <i64> [#uses=1] + %tmp90 = add i64 %N, -16 ; <i64> [#uses=1] + %tmp91 = sub i64 %tmp90, %14 ; <i64> [#uses=1] + br label %bb9 + +bb9: ; preds = %bb.nph, %bb9 + %indvar = phi i64 [ 0, %bb.nph ], [ %indvar.next, %bb9 ] ; <i64> [#uses=3] + %vX3.125 = phi <4 x float> [ %34, %bb.nph ], [ %69, %bb9 ] ; <<4 x float>> [#uses=2] + %vX0.223 = phi <4 x float> [ %31, %bb.nph ], [ %65, %bb9 ] ; <<4 x float>> [#uses=2] + %vX2.121 = phi <4 x float> [ %33, %bb.nph ], [ %70, %bb9 ] ; <<4 x float>> [#uses=2] + %vX1.120 = phi <4 x float> [ %32, %bb.nph ], [ %71, %bb9 ] ; <<4 x float>> [#uses=2] + %vI0.019 = phi <4 x float> [ %51, %bb.nph ], [ %55, %bb9 ] ; <<4 x float>> [#uses=1] + %tmp51 = shl i64 %indvar, 4 ; <i64> [#uses=9] + %tmp55 = add i64 %tmp54, %tmp51 ; <i64> [#uses=2] + %tmp57 = add i64 %tmp56, %tmp51 ; <i64> [#uses=1] + %scevgep58 = getelementptr float* %I, i64 %tmp57 ; <float*> [#uses=1] + %scevgep5859 = bitcast float* %scevgep58 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp61 = add i64 %tmp60, %tmp51 ; <i64> [#uses=1] + %scevgep62 = getelementptr float* %I, i64 %tmp61 ; <float*> [#uses=1] + %scevgep6263 = bitcast float* %scevgep62 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp65 = add i64 %tmp64, %tmp51 ; <i64> [#uses=1] + %scevgep66 = getelementptr float* %I, i64 %tmp65 ; <float*> [#uses=1] + %scevgep6667 = bitcast float* %scevgep66 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp69 = add i64 %tmp68, %tmp51 ; <i64> [#uses=1] + %scevgep70 = getelementptr float* %I, i64 %tmp69 ; <float*> [#uses=1] + %scevgep7071 = bitcast float* %scevgep70 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp72 = add i64 %14, %tmp51 ; <i64> [#uses=1] + %scevgep73 = getelementptr float* %O, i64 %tmp72 ; <float*> [#uses=1] + %scevgep7374 = bitcast float* %scevgep73 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp77 = add i64 %tmp76, %tmp51 ; <i64> [#uses=1] + %scevgep78 = getelementptr float* %O, i64 %tmp77 ; <float*> [#uses=1] + %scevgep7879 = bitcast float* %scevgep78 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp81 = add i64 %tmp80, %tmp51 ; <i64> [#uses=1] + %scevgep82 = getelementptr float* %O, i64 %tmp81 ; <float*> [#uses=1] + %scevgep8283 = bitcast float* %scevgep82 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp85 = add i64 %tmp84, %tmp51 ; <i64> [#uses=1] + %scevgep86 = getelementptr float* %O, i64 %tmp85 ; <float*> [#uses=1] + %scevgep8687 = bitcast float* %scevgep86 to <4 x float>* ; <<4 x float>*> [#uses=1] + %tmp88 = mul i64 %indvar, -16 ; <i64> [#uses=1] + %tmp92 = add i64 %tmp91, %tmp88 ; <i64> [#uses=2] + %52 = load <4 x float>* %scevgep5859, align 16 ; <<4 x float>> [#uses=2] + %53 = load <4 x float>* %scevgep6263, align 16 ; <<4 x float>> [#uses=2] + %54 = load <4 x float>* %scevgep6667, align 16 ; <<4 x float>> [#uses=2] + %55 = load <4 x float>* %scevgep7071, align 16 ; <<4 x float>> [#uses=2] + %56 = shufflevector <4 x float> %vI0.019, <4 x float> %52, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] + %57 = shufflevector <4 x float> %56, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> ; <<4 x float>> [#uses=1] + %58 = shufflevector <4 x float> %52, <4 x float> %53, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] + %59 = shufflevector <4 x float> %58, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> ; <<4 x float>> [#uses=1] + %60 = shufflevector <4 x float> %53, <4 x float> %54, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] + %61 = shufflevector <4 x float> %60, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> ; <<4 x float>> [#uses=1] + %62 = shufflevector <4 x float> %54, <4 x float> %55, <4 x i32> <i32 4, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] + %63 = shufflevector <4 x float> %62, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0> ; <<4 x float>> [#uses=1] + %64 = fmul <4 x float> %57, %vX0.223 ; <<4 x float>> [#uses=1] + %65 = fadd <4 x float> %vX0.223, %asmtmp.i18 ; <<4 x float>> [#uses=2] + %66 = fmul <4 x float> %59, %vX1.120 ; <<4 x float>> [#uses=1] + %67 = fmul <4 x float> %61, %vX2.121 ; <<4 x float>> [#uses=1] + %68 = fmul <4 x float> %63, %vX3.125 ; <<4 x float>> [#uses=1] + store <4 x float> %64, <4 x float>* %scevgep7374, align 16 + store <4 x float> %66, <4 x float>* %scevgep7879, align 16 + store <4 x float> %67, <4 x float>* %scevgep8283, align 16 + store <4 x float> %68, <4 x float>* %scevgep8687, align 16 + %69 = fadd <4 x float> %vX3.125, %asmtmp.i18 ; <<4 x float>> [#uses=1] + %70 = fadd <4 x float> %vX2.121, %asmtmp.i18 ; <<4 x float>> [#uses=1] + %71 = fadd <4 x float> %vX1.120, %asmtmp.i18 ; <<4 x float>> [#uses=1] + %72 = icmp sgt i64 %tmp92, 15 ; <i1> [#uses=1] + %indvar.next = add i64 %indvar, 1 ; <i64> [#uses=1] + br i1 %72, label %bb9, label %bb10.bb11.loopexit_crit_edge + +bb10.bb11.loopexit_crit_edge: ; preds = %bb9 + %scevgep = getelementptr float* %I, i64 %tmp55 ; <float*> [#uses=1] + %scevgep75 = getelementptr float* %O, i64 %tmp55 ; <float*> [#uses=1] + br label %bb11 + +bb11: ; preds = %bb8, %bb10.bb11.loopexit_crit_edge, %bb7 + %N_addr.2 = phi i64 [ %N_addr.1.lcssa, %bb7 ], [ %tmp92, %bb10.bb11.loopexit_crit_edge ], [ %N_addr.0, %bb8 ] ; <i64> [#uses=2] + %vX0.1 = phi <4 x float> [ %vX0.0.lcssa, %bb7 ], [ %65, %bb10.bb11.loopexit_crit_edge ], [ %31, %bb8 ] ; <<4 x float>> [#uses=1] + %O_addr.2 = phi float* [ %O_addr.1.lcssa, %bb7 ], [ %scevgep75, %bb10.bb11.loopexit_crit_edge ], [ %O_addr.0, %bb8 ] ; <float*> [#uses=1] + %I_addr.2 = phi float* [ %I_addr.1.lcssa, %bb7 ], [ %scevgep, %bb10.bb11.loopexit_crit_edge ], [ %I_addr.0, %bb8 ] ; <float*> [#uses=1] + %73 = extractelement <4 x float> %vX0.1, i32 0 ; <float> [#uses=2] + %74 = icmp sgt i64 %N_addr.2, 0 ; <i1> [#uses=1] + br i1 %74, label %bb12, label %bb14 + +bb12: ; preds = %bb11, %bb12 + %indvar94 = phi i64 [ %indvar.next95, %bb12 ], [ 0, %bb11 ] ; <i64> [#uses=3] + %x.130 = phi float [ %77, %bb12 ], [ %73, %bb11 ] ; <float> [#uses=2] + %I_addr.433 = getelementptr float* %I_addr.2, i64 %indvar94 ; <float*> [#uses=1] + %O_addr.432 = getelementptr float* %O_addr.2, i64 %indvar94 ; <float*> [#uses=1] + %75 = load float* %I_addr.433, align 4 ; <float> [#uses=1] + %76 = fmul float %75, %x.130 ; <float> [#uses=1] + store float %76, float* %O_addr.432, align 4 + %77 = fadd float %x.130, %0 ; <float> [#uses=2] + %indvar.next95 = add i64 %indvar94, 1 ; <i64> [#uses=2] + %exitcond = icmp eq i64 %indvar.next95, %N_addr.2 ; <i1> [#uses=1] + br i1 %exitcond, label %bb14, label %bb12 + +bb14: ; preds = %bb12, %bb11 + %x.1.lcssa = phi float [ %73, %bb11 ], [ %77, %bb12 ] ; <float> [#uses=1] + store float %x.1.lcssa, float* %Start, align 4 + ret void + +return: ; preds = %entry + ret void +} + +; Codegen shouldn't crash on this testcase. + +define void @bar(i32 %a, i32 %b) nounwind { +entry: ; preds = %bb1, %entry, %for.end204 + br label %outer + +outer: ; preds = %bb1, %entry + %i6 = phi i32 [ %storemerge171, %bb1 ], [ %a, %entry ] ; <i32> [#uses=2] + %storemerge171 = add i32 %i6, 1 ; <i32> [#uses=1] + br label %inner + +inner: ; preds = %bb0, %if.end275 + %i8 = phi i32 [ %a, %outer ], [ %indvar.next159, %bb0 ] ; <i32> [#uses=2] + %t338 = load i32* undef ; <i32> [#uses=1] + %t191 = mul i32 %i8, %t338 ; <i32> [#uses=1] + %t179 = add i32 %i6, %t191 ; <i32> [#uses=1] + br label %bb0 + +bb0: ; preds = %for.body332 + %indvar.next159 = add i32 %i8, 1 ; <i32> [#uses=1] + br i1 undef, label %bb1, label %inner + +bb1: ; preds = %bb0, %outer + %midx.4 = phi i32 [ %t179, %bb0 ] ; <i32> [#uses=0] + br label %outer +} diff --git a/test/CodeGen/X86/optimize-max-3.ll b/test/CodeGen/X86/optimize-max-3.ll new file mode 100644 index 000000000000..bf8bfa28dafd --- /dev/null +++ b/test/CodeGen/X86/optimize-max-3.ll @@ -0,0 +1,32 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s + +; LSR's OptimizeMax should eliminate the select (max). + +; CHECK: foo: +; CHECK-NOT: cmov +; CHECK: jle + +define void @foo(i64 %n, double* nocapture %p) nounwind { +entry: + %cmp6 = icmp slt i64 %n, 0 ; <i1> [#uses=1] + br i1 %cmp6, label %for.end, label %for.body.preheader + +for.body.preheader: ; preds = %entry + %tmp = icmp sgt i64 %n, 0 ; <i1> [#uses=1] + %n.op = add i64 %n, 1 ; <i64> [#uses=1] + %tmp1 = select i1 %tmp, i64 %n.op, i64 1 ; <i64> [#uses=1] + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %i = phi i64 [ %i.next, %for.body ], [ 0, %for.body.preheader ] ; <i64> [#uses=2] + %arrayidx = getelementptr double* %p, i64 %i ; <double*> [#uses=2] + %t4 = load double* %arrayidx ; <double> [#uses=1] + %mul = fmul double %t4, 2.200000e+00 ; <double> [#uses=1] + store double %mul, double* %arrayidx + %i.next = add nsw i64 %i, 1 ; <i64> [#uses=2] + %exitcond = icmp eq i64 %i.next, %tmp1 ; <i1> [#uses=1] + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + ret void +} diff --git a/test/CodeGen/X86/or-address.ll b/test/CodeGen/X86/or-address.ll new file mode 100644 index 000000000000..6447680e623b --- /dev/null +++ b/test/CodeGen/X86/or-address.ll @@ -0,0 +1,90 @@ +; PR1135 +; RUN: llc %s -o - | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.3" + + +; CHECK: movl %{{.*}}, (%rdi,%rdx,4) +; CHECK: movl %{{.*}}, 8(%rdi,%rdx,4) +; CHECK: movl %{{.*}}, 4(%rdi,%rdx,4) +; CHECK: movl %{{.*}}, 12(%rdi,%rdx,4) + +define void @test(i32* nocapture %array, i32 %r0) nounwind ssp noredzone { +bb.nph: + br label %bb + +bb: ; preds = %bb, %bb.nph + %j.010 = phi i8 [ 0, %bb.nph ], [ %14, %bb ] ; <i8> [#uses=1] + %k.19 = phi i8 [ 0, %bb.nph ], [ %.k.1, %bb ] ; <i8> [#uses=1] + %i0.08 = phi i8 [ 0, %bb.nph ], [ %15, %bb ] ; <i8> [#uses=3] + %0 = icmp slt i8 %i0.08, 4 ; <i1> [#uses=1] + %iftmp.0.0 = select i1 %0, i8 %i0.08, i8 0 ; <i8> [#uses=2] + %1 = icmp eq i8 %i0.08, 4 ; <i1> [#uses=1] + %2 = zext i1 %1 to i8 ; <i8> [#uses=1] + %.k.1 = add i8 %2, %k.19 ; <i8> [#uses=2] + %3 = shl i8 %.k.1, 2 ; <i8> [#uses=1] + %4 = add i8 %3, %iftmp.0.0 ; <i8> [#uses=1] + %5 = shl i8 %4, 2 ; <i8> [#uses=1] + %6 = zext i8 %5 to i64 ; <i64> [#uses=4] + %7 = getelementptr inbounds i32* %array, i64 %6 ; <i32*> [#uses=1] + store i32 %r0, i32* %7, align 4 + %8 = or i64 %6, 2 ; <i64> [#uses=1] + %9 = getelementptr inbounds i32* %array, i64 %8 ; <i32*> [#uses=1] + store i32 %r0, i32* %9, align 4 + %10 = or i64 %6, 1 ; <i64> [#uses=1] + %11 = getelementptr inbounds i32* %array, i64 %10 ; <i32*> [#uses=1] + store i32 %r0, i32* %11, align 4 + %12 = or i64 %6, 3 ; <i64> [#uses=1] + %13 = getelementptr inbounds i32* %array, i64 %12 ; <i32*> [#uses=1] + store i32 %r0, i32* %13, align 4 + %14 = add nsw i8 %j.010, 1 ; <i8> [#uses=2] + %15 = add i8 %iftmp.0.0, 1 ; <i8> [#uses=1] + %exitcond = icmp eq i8 %14, 32 ; <i1> [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb + ret void +} + +; CHECK: test1: +; CHECK: movl %{{.*}}, (%rdi,%rcx,4) +; CHECK: movl %{{.*}}, 8(%rdi,%rcx,4) +; CHECK: movl %{{.*}}, 4(%rdi,%rcx,4) +; CHECK: movl %{{.*}}, 12(%rdi,%rcx,4) + +define void @test1(i32* nocapture %array, i32 %r0, i8 signext %k, i8 signext %i0) nounwind { +bb.nph: + br label %for.body + +for.body: ; preds = %for.body, %bb.nph + %j.065 = phi i8 [ 0, %bb.nph ], [ %inc52, %for.body ] ; <i8> [#uses=1] + %i0.addr.064 = phi i8 [ %i0, %bb.nph ], [ %add, %for.body ] ; <i8> [#uses=3] + %k.addr.163 = phi i8 [ %k, %bb.nph ], [ %inc.k.addr.1, %for.body ] ; <i8> [#uses=1] + %cmp5 = icmp slt i8 %i0.addr.064, 4 ; <i1> [#uses=1] + %cond = select i1 %cmp5, i8 %i0.addr.064, i8 0 ; <i8> [#uses=2] + %cmp12 = icmp eq i8 %i0.addr.064, 4 ; <i1> [#uses=1] + %inc = zext i1 %cmp12 to i8 ; <i8> [#uses=1] + %inc.k.addr.1 = add i8 %inc, %k.addr.163 ; <i8> [#uses=2] + %mul = shl i8 %cond, 2 ; <i8> [#uses=1] + %mul22 = shl i8 %inc.k.addr.1, 4 ; <i8> [#uses=1] + %add23 = add i8 %mul22, %mul ; <i8> [#uses=1] + %idxprom = zext i8 %add23 to i64 ; <i64> [#uses=4] + %arrayidx = getelementptr inbounds i32* %array, i64 %idxprom ; <i32*> [#uses=1] + store i32 %r0, i32* %arrayidx + %add3356 = or i64 %idxprom, 2 ; <i64> [#uses=1] + %arrayidx36 = getelementptr inbounds i32* %array, i64 %add3356 ; <i32*> [#uses=1] + store i32 %r0, i32* %arrayidx36 + %add4058 = or i64 %idxprom, 1 ; <i64> [#uses=1] + %arrayidx43 = getelementptr inbounds i32* %array, i64 %add4058 ; <i32*> [#uses=1] + store i32 %r0, i32* %arrayidx43 + %add4760 = or i64 %idxprom, 3 ; <i64> [#uses=1] + %arrayidx50 = getelementptr inbounds i32* %array, i64 %add4760 ; <i32*> [#uses=1] + store i32 %r0, i32* %arrayidx50 + %inc52 = add nsw i8 %j.065, 1 ; <i8> [#uses=2] + %add = add i8 %cond, 1 ; <i8> [#uses=1] + %exitcond = icmp eq i8 %inc52, 32 ; <i1> [#uses=1] + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void +} diff --git a/test/CodeGen/X86/pic.ll b/test/CodeGen/X86/pic.ll index 35b172509c95..9506c9b5db11 100644 --- a/test/CodeGen/X86/pic.ll +++ b/test/CodeGen/X86/pic.ll @@ -4,18 +4,18 @@ @dst = external global i32 @src = external global i32 -define void @test1() nounwind { +define void @test0() nounwind { entry: store i32* @dst, i32** @ptr %tmp.s = load i32* @src store i32 %tmp.s, i32* @dst ret void -; LINUX: test1: -; LINUX: call .L1$pb -; LINUX-NEXT: .L1$pb: +; LINUX: test0: +; LINUX: call .L0$pb +; LINUX-NEXT: .L0$pb: ; LINUX-NEXT: popl -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L1$pb), +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L0$pb), ; LINUX: movl dst@GOT(%eax), ; LINUX: movl ptr@GOT(%eax), ; LINUX: movl src@GOT(%eax), @@ -26,18 +26,18 @@ entry: @dst2 = global i32 0 @src2 = global i32 0 -define void @test2() nounwind { +define void @test1() nounwind { entry: store i32* @dst2, i32** @ptr2 %tmp.s = load i32* @src2 store i32 %tmp.s, i32* @dst2 ret void -; LINUX: test2: -; LINUX: call .L2$pb -; LINUX-NEXT: .L2$pb: +; LINUX: test1: +; LINUX: call .L1$pb +; LINUX-NEXT: .L1$pb: ; LINUX-NEXT: popl -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L2$pb), %eax +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L1$pb), %eax ; LINUX: movl dst2@GOT(%eax), ; LINUX: movl ptr2@GOT(%eax), ; LINUX: movl src2@GOT(%eax), @@ -47,17 +47,17 @@ entry: declare i8* @malloc(i32) -define void @test3() nounwind { +define void @test2() nounwind { entry: %ptr = call i8* @malloc(i32 40) ret void -; LINUX: test3: +; LINUX: test2: ; LINUX: pushl %ebx ; LINUX-NEXT: subl $8, %esp -; LINUX-NEXT: call .L3$pb -; LINUX-NEXT: .L3$pb: +; LINUX-NEXT: call .L2$pb +; LINUX-NEXT: .L2$pb: ; LINUX-NEXT: popl %ebx -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L3$pb), %ebx +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L2$pb), %ebx ; LINUX: movl $40, (%esp) ; LINUX: call malloc@PLT ; LINUX: addl $8, %esp @@ -67,18 +67,18 @@ entry: @pfoo = external global void(...)* -define void @test4() nounwind { +define void @test3() nounwind { entry: %tmp = call void(...)*(...)* @afoo() store void(...)* %tmp, void(...)** @pfoo %tmp1 = load void(...)** @pfoo call void(...)* %tmp1() ret void -; LINUX: test4: -; LINUX: call .L4$pb -; LINUX-NEXT: .L4$pb: +; LINUX: test3: +; LINUX: call .L3$pb +; LINUX-NEXT: .L3$pb: ; LINUX: popl -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L4$pb), +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L3$pb), ; LINUX: movl pfoo@GOT(%esi), ; LINUX: call afoo@PLT ; LINUX: call * @@ -86,14 +86,14 @@ entry: declare void(...)* @afoo(...) -define void @test5() nounwind { +define void @test4() nounwind { entry: call void(...)* @foo() ret void -; LINUX: test5: -; LINUX: call .L5$pb +; LINUX: test4: +; LINUX: call .L4$pb ; LINUX: popl %ebx -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L5$pb), %ebx +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L4$pb), %ebx ; LINUX: call foo@PLT } @@ -104,18 +104,18 @@ declare void @foo(...) @dst6 = internal global i32 0 @src6 = internal global i32 0 -define void @test6() nounwind { +define void @test5() nounwind { entry: store i32* @dst6, i32** @ptr6 %tmp.s = load i32* @src6 store i32 %tmp.s, i32* @dst6 ret void -; LINUX: test6: -; LINUX: call .L6$pb -; LINUX-NEXT: .L6$pb: +; LINUX: test5: +; LINUX: call .L5$pb +; LINUX-NEXT: .L5$pb: ; LINUX-NEXT: popl %eax -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L6$pb), %eax +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L5$pb), %eax ; LINUX: leal dst6@GOTOFF(%eax), %ecx ; LINUX: movl %ecx, ptr6@GOTOFF(%eax) ; LINUX: movl src6@GOTOFF(%eax), %ecx @@ -125,24 +125,24 @@ entry: ;; Test constant pool references. -define double @test7(i32 %a.u) nounwind { +define double @test6(i32 %a.u) nounwind { entry: %tmp = icmp eq i32 %a.u,0 %retval = select i1 %tmp, double 4.561230e+02, double 1.234560e+02 ret double %retval -; LINUX: .LCPI7_0: +; LINUX: .LCPI6_0: -; LINUX: test7: -; LINUX: call .L7$pb -; LINUX: .L7$pb: -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L7$pb), -; LINUX: fldl .LCPI7_0@GOTOFF( +; LINUX: test6: +; LINUX: call .L6$pb +; LINUX: .L6$pb: +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L6$pb), +; LINUX: fldl .LCPI6_0@GOTOFF( } ;; Test jump table references. -define void @test8(i32 %n.u) nounwind { +define void @test7(i32 %n.u) nounwind { entry: switch i32 %n.u, label %bb12 [i32 1, label %bb i32 2, label %bb6 i32 4, label %bb7 i32 5, label %bb8 i32 6, label %bb10 i32 7, label %bb1 i32 8, label %bb3 i32 9, label %bb4 i32 10, label %bb9 i32 11, label %bb2 i32 12, label %bb5 i32 13, label %bb11 ] bb: @@ -185,19 +185,19 @@ bb12: tail call void(...)* @foo6() ret void -; LINUX: test8: -; LINUX: call .L8$pb -; LINUX: .L8$pb: -; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L8$pb), -; LINUX: addl .LJTI8_0@GOTOFF( +; LINUX: test7: +; LINUX: call .L7$pb +; LINUX: .L7$pb: +; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L7$pb), +; LINUX: addl .LJTI7_0@GOTOFF( ; LINUX: jmpl * -; LINUX: .LJTI8_0: -; LINUX: .long .LBB8_2@GOTOFF -; LINUX: .long .LBB8_8@GOTOFF -; LINUX: .long .LBB8_14@GOTOFF -; LINUX: .long .LBB8_9@GOTOFF -; LINUX: .long .LBB8_10@GOTOFF +; LINUX: .LJTI7_0: +; LINUX: .long .LBB7_2@GOTOFF +; LINUX: .long .LBB7_8@GOTOFF +; LINUX: .long .LBB7_14@GOTOFF +; LINUX: .long .LBB7_9@GOTOFF +; LINUX: .long .LBB7_10@GOTOFF } declare void @foo1(...) diff --git a/test/CodeGen/X86/pic_jumptable.ll b/test/CodeGen/X86/pic_jumptable.ll index b3750c1e8e67..31071bc74a78 100644 --- a/test/CodeGen/X86/pic_jumptable.ll +++ b/test/CodeGen/X86/pic_jumptable.ll @@ -1,13 +1,18 @@ ; RUN: llc < %s -relocation-model=pic -mtriple=i386-linux-gnu -asm-verbose=false | not grep -F .text -; RUN: llc < %s -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false | not grep lea -; RUN: llc < %s -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false | grep add | count 2 +; RUN: llc < %s -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin | not grep 'lJTI' ; rdar://6971437 +; rdar://7738756 declare void @_Z3bari(i32) define linkonce void @_Z3fooILi1EEvi(i32 %Y) nounwind { entry: +; CHECK: L0$pb +; CHECK-NOT: leal +; CHECK: Ltmp0 = LJTI0_0-L0$pb +; CHECK-NEXT: addl Ltmp0(%eax,%ecx,4) +; CHECK-NEXT: jmpl *%eax %Y_addr = alloca i32 ; <i32*> [#uses=2] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] store i32 %Y, i32* %Y_addr diff --git a/test/CodeGen/X86/postra-licm.ll b/test/CodeGen/X86/postra-licm.ll new file mode 100644 index 000000000000..97cc7b4977cf --- /dev/null +++ b/test/CodeGen/X86/postra-licm.ll @@ -0,0 +1,185 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s -check-prefix=X86-32 +; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s -check-prefix=X86-64 + +; MachineLICM should be able to hoist loop invariant reload out of the loop. +; rdar://7233099 + +%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } +%struct.__sFILEX = type opaque +%struct.__sbuf = type { i8*, i32 } +%struct.epoch_t = type { %struct.trans_t*, %struct.trans_t*, i32, i32, i32, i32, i32 } +%struct.trans_t = type { i32, i32, i32, i8* } + +@.str12 = external constant [2 x i8], align 1 ; <[2 x i8]*> [#uses=1] +@.str19 = external constant [7 x i8], align 1 ; <[7 x i8]*> [#uses=1] +@.str24 = external constant [4 x i8], align 1 ; <[4 x i8]*> [#uses=1] + +define i32 @t1(i32 %c, i8** nocapture %v) nounwind ssp { +; X86-32: t1: +entry: + br i1 undef, label %bb, label %bb3 + +bb: ; preds = %entry + unreachable + +bb3: ; preds = %entry + br i1 undef, label %bb.i, label %bb.nph41 + +bb.i: ; preds = %bb3 + unreachable + +bb.nph41: ; preds = %bb3 + %0 = call %struct.FILE* @"\01_fopen$UNIX2003"(i8* undef, i8* getelementptr inbounds ([2 x i8]* @.str12, i32 0, i32 0)) nounwind ; <%struct.FILE*> [#uses=3] + br i1 undef, label %bb4, label %bb5.preheader + +bb5.preheader: ; preds = %bb.nph41 + br label %bb5 + +bb4: ; preds = %bb.nph41 + unreachable + +bb5: ; preds = %bb5, %bb5.preheader + br i1 undef, label %bb7, label %bb5 + +bb7: ; preds = %bb5 + br i1 undef, label %bb9, label %bb12 + +bb9: ; preds = %bb7 + unreachable + +bb12: ; preds = %bb7 + br i1 undef, label %bb16, label %bb22 + +bb16: ; preds = %bb12 + unreachable + +bb22: ; preds = %bb12 + br label %bb.i1 + +bb.i1: ; preds = %bb.i1, %bb22 + %1 = icmp eq i8 undef, 69 ; <i1> [#uses=1] + br i1 %1, label %imix_test.exit, label %bb.i1 + +imix_test.exit: ; preds = %bb.i1 + br i1 undef, label %bb23, label %bb26.preheader + +bb26.preheader: ; preds = %imix_test.exit + br i1 undef, label %bb28, label %bb30 + +bb23: ; preds = %imix_test.exit + unreachable +; X86-32: %bb26.preheader.bb28_crit_edge +; X86-32: movl -16(%ebp), +; X86-32-NEXT: .align 4 +; X86-32-NEXT: %bb28 + +bb28: ; preds = %bb28, %bb26.preheader + %counter.035 = phi i32 [ %3, %bb28 ], [ 0, %bb26.preheader ] ; <i32> [#uses=2] + %tmp56 = shl i32 %counter.035, 2 ; <i32> [#uses=0] + %2 = call i8* @fgets(i8* undef, i32 50, %struct.FILE* %0) nounwind ; <i8*> [#uses=0] + %3 = add nsw i32 %counter.035, 1 ; <i32> [#uses=1] + %4 = call i32 @feof(%struct.FILE* %0) nounwind ; <i32> [#uses=0] + br label %bb28 + +bb30: ; preds = %bb26.preheader + %5 = call i32 @strcmp(i8* undef, i8* getelementptr inbounds ([7 x i8]* @.str19, i32 0, i32 0)) nounwind readonly ; <i32> [#uses=0] + br i1 undef, label %bb34, label %bb70 + +bb32.loopexit: ; preds = %bb45 + %6 = icmp eq i32 undef, 0 ; <i1> [#uses=1] + %indvar.next55 = add i32 %indvar54, 1 ; <i32> [#uses=1] + br i1 %6, label %bb34, label %bb70 + +bb34: ; preds = %bb32.loopexit, %bb30 + %indvar54 = phi i32 [ %indvar.next55, %bb32.loopexit ], [ 0, %bb30 ] ; <i32> [#uses=3] + br i1 false, label %bb35, label %bb39.preheader + +bb35: ; preds = %bb34 + unreachable + +bb39.preheader: ; preds = %bb34 + %7 = getelementptr inbounds %struct.epoch_t* undef, i32 %indvar54, i32 3 ; <i32*> [#uses=1] + %8 = getelementptr inbounds %struct.epoch_t* undef, i32 %indvar54, i32 2 ; <i32*> [#uses=0] + br i1 false, label %bb42, label %bb45 + +bb42: ; preds = %bb39.preheader + unreachable + +bb45: ; preds = %bb39.preheader + %9 = call i32 @strcmp(i8* undef, i8* getelementptr inbounds ([4 x i8]* @.str24, i32 0, i32 0)) nounwind readonly ; <i32> [#uses=0] + br i1 false, label %bb47, label %bb32.loopexit + +bb47: ; preds = %bb45 + %10 = load i32* %7, align 4 ; <i32> [#uses=0] + unreachable + +bb70: ; preds = %bb32.loopexit, %bb30 + br i1 undef, label %bb78, label %bb76 + +bb76: ; preds = %bb70 + unreachable + +bb78: ; preds = %bb70 + br i1 undef, label %bb83, label %bb79 + +bb79: ; preds = %bb78 + unreachable + +bb83: ; preds = %bb78 + call void @rewind(%struct.FILE* %0) nounwind + unreachable +} + +declare %struct.FILE* @"\01_fopen$UNIX2003"(i8*, i8*) + +declare i8* @fgets(i8*, i32, %struct.FILE* nocapture) nounwind + +declare void @rewind(%struct.FILE* nocapture) nounwind + +declare i32 @feof(%struct.FILE* nocapture) nounwind + +declare i32 @strcmp(i8* nocapture, i8* nocapture) nounwind readonly + +@map_4_to_16 = external constant [16 x i16], align 32 ; <[16 x i16]*> [#uses=2] + +define void @t2(i8* nocapture %bufp, i8* nocapture %data, i32 %dsize) nounwind ssp { +; X86-64: t2: +entry: + br i1 undef, label %return, label %bb.nph + +bb.nph: ; preds = %entry +; X86-64: movq _map_4_to_16@GOTPCREL(%rip) +; X86-64: .align 4 + %tmp5 = zext i32 undef to i64 ; <i64> [#uses=1] + %tmp6 = add i64 %tmp5, 1 ; <i64> [#uses=1] + %tmp11 = shl i64 undef, 1 ; <i64> [#uses=1] + %tmp14 = mul i64 undef, 3 ; <i64> [#uses=1] + br label %bb + +bb: ; preds = %bb, %bb.nph + %tmp9 = mul i64 undef, undef ; <i64> [#uses=2] + %tmp12 = add i64 %tmp11, %tmp9 ; <i64> [#uses=1] + %scevgep13 = getelementptr i8* %bufp, i64 %tmp12 ; <i8*> [#uses=1] + %tmp15 = add i64 %tmp14, %tmp9 ; <i64> [#uses=1] + %scevgep16 = getelementptr i8* %bufp, i64 %tmp15 ; <i8*> [#uses=1] + %0 = load i8* undef, align 1 ; <i8> [#uses=1] + %1 = zext i8 %0 to i32 ; <i32> [#uses=1] + %2 = getelementptr inbounds [16 x i16]* @map_4_to_16, i64 0, i64 0 ; <i16*> [#uses=1] + %3 = load i16* %2, align 2 ; <i16> [#uses=1] + %4 = trunc i16 %3 to i8 ; <i8> [#uses=1] + store i8 %4, i8* undef, align 1 + %5 = and i32 %1, 15 ; <i32> [#uses=1] + %6 = zext i32 %5 to i64 ; <i64> [#uses=1] + %7 = getelementptr inbounds [16 x i16]* @map_4_to_16, i64 0, i64 %6 ; <i16*> [#uses=1] + %8 = load i16* %7, align 2 ; <i16> [#uses=2] + %9 = lshr i16 %8, 8 ; <i16> [#uses=1] + %10 = trunc i16 %9 to i8 ; <i8> [#uses=1] + store i8 %10, i8* %scevgep13, align 1 + %11 = trunc i16 %8 to i8 ; <i8> [#uses=1] + store i8 %11, i8* %scevgep16, align 1 + %exitcond = icmp eq i64 undef, %tmp6 ; <i1> [#uses=1] + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb, %entry + ret void +} diff --git a/test/CodeGen/X86/promote-i16.ll b/test/CodeGen/X86/promote-i16.ll new file mode 100644 index 000000000000..101bb29593cc --- /dev/null +++ b/test/CodeGen/X86/promote-i16.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s -march=x86 | FileCheck %s + +define signext i16 @foo(i16 signext %x) nounwind { +entry: +; CHECK: foo: +; CHECK: movzwl 4(%esp), %eax +; CHECK: xorl $21998, %eax +; CHECK: movswl %ax, %eax + %0 = xor i16 %x, 21998 + ret i16 %0 +} diff --git a/test/CodeGen/X86/rot16.ll b/test/CodeGen/X86/rot16.ll index 42ece47b0300..de23dcb78f10 100644 --- a/test/CodeGen/X86/rot16.ll +++ b/test/CodeGen/X86/rot16.ll @@ -1,11 +1,9 @@ -; RUN: llc < %s -march=x86 > %t -; RUN: grep rol %t | count 3 -; RUN: grep ror %t | count 1 -; RUN: grep shld %t | count 2 -; RUN: grep shrd %t | count 2 +; RUN: llc < %s -march=x86 | FileCheck %s define i16 @foo(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: foo: +; CHECK: rolw %cl %0 = shl i16 %x, %z %1 = sub i16 16, %z %2 = lshr i16 %x, %1 @@ -15,6 +13,8 @@ entry: define i16 @bar(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: bar: +; CHECK: shldw %cl %0 = shl i16 %y, %z %1 = sub i16 16, %z %2 = lshr i16 %x, %1 @@ -24,6 +24,8 @@ entry: define i16 @un(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: un: +; CHECK: rorw %cl %0 = lshr i16 %x, %z %1 = sub i16 16, %z %2 = shl i16 %x, %1 @@ -33,6 +35,8 @@ entry: define i16 @bu(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: bu: +; CHECK: shrdw %0 = lshr i16 %y, %z %1 = sub i16 16, %z %2 = shl i16 %x, %1 @@ -42,6 +46,8 @@ entry: define i16 @xfoo(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: xfoo: +; CHECK: rolw $5 %0 = lshr i16 %x, 11 %1 = shl i16 %x, 5 %2 = or i16 %0, %1 @@ -50,6 +56,8 @@ entry: define i16 @xbar(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: xbar: +; CHECK: shldw $5 %0 = shl i16 %y, 5 %1 = lshr i16 %x, 11 %2 = or i16 %0, %1 @@ -58,6 +66,8 @@ entry: define i16 @xun(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: xun: +; CHECK: rolw $11 %0 = lshr i16 %x, 5 %1 = shl i16 %x, 11 %2 = or i16 %0, %1 @@ -66,6 +76,8 @@ entry: define i16 @xbu(i16 %x, i16 %y, i16 %z) nounwind readnone { entry: +; CHECK: xbu: +; CHECK: shldw $11 %0 = lshr i16 %y, 5 %1 = shl i16 %x, 11 %2 = or i16 %0, %1 diff --git a/test/CodeGen/X86/rot32.ll b/test/CodeGen/X86/rot32.ll index 655ed272837a..99602fd64ff5 100644 --- a/test/CodeGen/X86/rot32.ll +++ b/test/CodeGen/X86/rot32.ll @@ -1,11 +1,9 @@ -; RUN: llc < %s -march=x86 > %t -; RUN: grep rol %t | count 3 -; RUN: grep ror %t | count 1 -; RUN: grep shld %t | count 2 -; RUN: grep shrd %t | count 2 +; RUN: llc < %s -march=x86 | FileCheck %s define i32 @foo(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: foo: +; CHECK: roll %cl %0 = shl i32 %x, %z %1 = sub i32 32, %z %2 = lshr i32 %x, %1 @@ -15,6 +13,8 @@ entry: define i32 @bar(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: bar: +; CHECK: shldl %cl %0 = shl i32 %y, %z %1 = sub i32 32, %z %2 = lshr i32 %x, %1 @@ -24,6 +24,8 @@ entry: define i32 @un(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: un: +; CHECK: rorl %cl %0 = lshr i32 %x, %z %1 = sub i32 32, %z %2 = shl i32 %x, %1 @@ -33,6 +35,8 @@ entry: define i32 @bu(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: bu: +; CHECK: shrdl %cl %0 = lshr i32 %y, %z %1 = sub i32 32, %z %2 = shl i32 %x, %1 @@ -42,6 +46,8 @@ entry: define i32 @xfoo(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: xfoo: +; CHECK: roll $7 %0 = lshr i32 %x, 25 %1 = shl i32 %x, 7 %2 = or i32 %0, %1 @@ -50,6 +56,8 @@ entry: define i32 @xbar(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: xbar: +; CHECK: shldl $7 %0 = shl i32 %y, 7 %1 = lshr i32 %x, 25 %2 = or i32 %0, %1 @@ -58,6 +66,8 @@ entry: define i32 @xun(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: xun: +; CHECK: roll $25 %0 = lshr i32 %x, 7 %1 = shl i32 %x, 25 %2 = or i32 %0, %1 @@ -66,6 +76,8 @@ entry: define i32 @xbu(i32 %x, i32 %y, i32 %z) nounwind readnone { entry: +; CHECK: xbu: +; CHECK: shldl %0 = lshr i32 %y, 7 %1 = shl i32 %x, 25 %2 = or i32 %0, %1 diff --git a/test/CodeGen/X86/shl_elim.ll b/test/CodeGen/X86/shl_elim.ll index 445889166bd5..0827221875b1 100644 --- a/test/CodeGen/X86/shl_elim.ll +++ b/test/CodeGen/X86/shl_elim.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -march=x86 | grep {shrl .eax} ; RUN: llc < %s -march=x86 | grep {movswl .ax, .eax} -define i32 @test1(i64 %a) { +define i32 @test1(i64 %a) nounwind { %tmp29 = lshr i64 %a, 24 ; <i64> [#uses=1] %tmp23 = trunc i64 %tmp29 to i32 ; <i32> [#uses=1] %tmp410 = lshr i32 %tmp23, 9 ; <i32> [#uses=1] diff --git a/test/CodeGen/X86/sibcall-2.ll b/test/CodeGen/X86/sibcall-2.ll new file mode 100644 index 000000000000..f8a746563b51 --- /dev/null +++ b/test/CodeGen/X86/sibcall-2.ll @@ -0,0 +1,52 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin -disable-fp-elim | FileCheck %s -check-prefix=32 +; RUN: llc < %s -mtriple=x86_64-apple-darwin -disable-fp-elim | FileCheck %s -check-prefix=64 + +; Tail call should not use ebp / rbp after it's popped. Use esp / rsp. + +define void @t1(i8* nocapture %value) nounwind { +entry: +; 32: t1: +; 32: jmpl *4(%esp) + +; 64: t1: +; 64: jmpq *%rdi + %0 = bitcast i8* %value to void ()* + tail call void %0() nounwind + ret void +} + +define void @t2(i32 %a, i8* nocapture %value) nounwind { +entry: +; 32: t2: +; 32: jmpl *8(%esp) + +; 64: t2: +; 64: jmpq *%rsi + %0 = bitcast i8* %value to void ()* + tail call void %0() nounwind + ret void +} + +define void @t3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i8* nocapture %value) nounwind { +entry: +; 32: t3: +; 32: jmpl *28(%esp) + +; 64: t3: +; 64: jmpq *8(%rsp) + %0 = bitcast i8* %value to void ()* + tail call void %0() nounwind + ret void +} + +define void @t4(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i8* nocapture %value) nounwind { +entry: +; 32: t4: +; 32: jmpl *32(%esp) + +; 64: t4: +; 64: jmpq *16(%rsp) + %0 = bitcast i8* %value to void ()* + tail call void %0() nounwind + ret void +} diff --git a/test/CodeGen/X86/sibcall.ll b/test/CodeGen/X86/sibcall.ll index 8e52a7cbfe78..4b27f2edb759 100644 --- a/test/CodeGen/X86/sibcall.ll +++ b/test/CodeGen/X86/sibcall.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=x86 -asm-verbose=false | FileCheck %s -check-prefix=32 -; RUN: llc < %s -march=x86-64 -asm-verbose=false | FileCheck %s -check-prefix=64 +; RUN: llc < %s -march=x86 -mattr=+sse2 -asm-verbose=false | FileCheck %s -check-prefix=32 +; RUN: llc < %s -march=x86-64 -mattr=+sse2 -asm-verbose=false | FileCheck %s -check-prefix=64 define void @t1(i32 %x) nounwind ssp { entry: @@ -313,3 +313,21 @@ entry: } declare void @foo() + +; If caller / callee calling convention mismatch then check if the return +; values are returned in the same registers. +; rdar://7874780 + +define double @t20(double %x) nounwind { +entry: +; 32: t20: +; 32: call {{_?}}foo20 +; 32: fldl (%esp) + +; 64: t20: +; 64: jmp {{_?}}foo20 + %0 = tail call fastcc double @foo20(double %x) nounwind + ret double %0 +} + +declare fastcc double @foo20(double) nounwind diff --git a/test/CodeGen/X86/sink-hoist.ll b/test/CodeGen/X86/sink-hoist.ll index 01d73736d6c2..031c01e9af7d 100644 --- a/test/CodeGen/X86/sink-hoist.ll +++ b/test/CodeGen/X86/sink-hoist.ll @@ -61,9 +61,9 @@ entry: ; Codegen should hoist and CSE these constants. ; CHECK: vv: -; CHECK: LCPI4_0(%rip), %xmm0 -; CHECK: LCPI4_1(%rip), %xmm1 -; CHECK: LCPI4_2(%rip), %xmm2 +; CHECK: LCPI3_0(%rip), %xmm0 +; CHECK: LCPI3_1(%rip), %xmm1 +; CHECK: LCPI3_2(%rip), %xmm2 ; CHECK: align ; CHECK-NOT: LCPI ; CHECK: ret diff --git a/test/CodeGen/X86/sse41.ll b/test/CodeGen/X86/sse41.ll index a734c05b8686..ef66d1a44a18 100644 --- a/test/CodeGen/X86/sse41.ll +++ b/test/CodeGen/X86/sse41.ll @@ -123,11 +123,11 @@ define float @ext_1(<4 x float> %v) nounwind { ; X32: _ext_1: ; X32: pshufd $3, %xmm0, %xmm0 -; X32: addss LCPI8_0, %xmm0 +; X32: addss LCPI7_0, %xmm0 ; X64: _ext_1: ; X64: pshufd $3, %xmm0, %xmm0 -; X64: addss LCPI8_0(%rip), %xmm0 +; X64: addss LCPI7_0(%rip), %xmm0 } define float @ext_2(<4 x float> %v) nounwind { %s = extractelement <4 x float> %v, i32 3 diff --git a/test/CodeGen/X86/stack-align.ll b/test/CodeGen/X86/stack-align.ll index e971ef70dbd4..271ad1aad0ba 100644 --- a/test/CodeGen/X86/stack-align.ll +++ b/test/CodeGen/X86/stack-align.ll @@ -31,7 +31,7 @@ define <2 x double> @test3(<2 x double> %x, <2 x double> %y) alignstack(32) { entry: ; CHECK: andl{{.*}}$-32, %esp call void @test2() - %A = mul <2 x double> %x, %y + %A = fmul <2 x double> %x, %y ret <2 x double> %A } diff --git a/test/CodeGen/X86/stack-color-with-reg.ll b/test/CodeGen/X86/stack-color-with-reg.ll index 83f56c10bb75..001a54096408 100644 --- a/test/CodeGen/X86/stack-color-with-reg.ll +++ b/test/CodeGen/X86/stack-color-with-reg.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t -; RUN: grep asm-printer %t | grep 156 -; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 4 +; RUN: grep asm-printer %t | grep 166 +; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 5 type { [62 x %struct.Bitvec*] } ; type %0 type { i8* } ; type %1 diff --git a/test/CodeGen/X86/store-narrow.ll b/test/CodeGen/X86/store-narrow.ll new file mode 100644 index 000000000000..b1100fa960c0 --- /dev/null +++ b/test/CodeGen/X86/store-narrow.ll @@ -0,0 +1,127 @@ +; rdar://7860110 +; RUN: llc < %s | FileCheck %s -check-prefix=X64 +; RUN: llc -march=x86 < %s | FileCheck %s -check-prefix=X32 +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.2" + +define void @test1(i32* nocapture %a0, i8 zeroext %a1) nounwind ssp { +entry: + %A = load i32* %a0, align 4 + %B = and i32 %A, -256 ; 0xFFFFFF00 + %C = zext i8 %a1 to i32 + %D = or i32 %C, %B + store i32 %D, i32* %a0, align 4 + ret void + +; X64: test1: +; X64: movb %sil, (%rdi) + +; X32: test1: +; X32: movb 8(%esp), %al +; X32: movb %al, (%{{.*}}) +} + +define void @test2(i32* nocapture %a0, i8 zeroext %a1) nounwind ssp { +entry: + %A = load i32* %a0, align 4 + %B = and i32 %A, -65281 ; 0xFFFF00FF + %C = zext i8 %a1 to i32 + %CS = shl i32 %C, 8 + %D = or i32 %B, %CS + store i32 %D, i32* %a0, align 4 + ret void +; X64: test2: +; X64: movb %sil, 1(%rdi) + +; X32: test2: +; X32: movb 8(%esp), %al +; X32: movb %al, 1(%{{.*}}) +} + +define void @test3(i32* nocapture %a0, i16 zeroext %a1) nounwind ssp { +entry: + %A = load i32* %a0, align 4 + %B = and i32 %A, -65536 ; 0xFFFF0000 + %C = zext i16 %a1 to i32 + %D = or i32 %B, %C + store i32 %D, i32* %a0, align 4 + ret void +; X64: test3: +; X64: movw %si, (%rdi) + +; X32: test3: +; X32: movw 8(%esp), %ax +; X32: movw %ax, (%{{.*}}) +} + +define void @test4(i32* nocapture %a0, i16 zeroext %a1) nounwind ssp { +entry: + %A = load i32* %a0, align 4 + %B = and i32 %A, 65535 ; 0x0000FFFF + %C = zext i16 %a1 to i32 + %CS = shl i32 %C, 16 + %D = or i32 %B, %CS + store i32 %D, i32* %a0, align 4 + ret void +; X64: test4: +; X64: movw %si, 2(%rdi) + +; X32: test4: +; X32: movzwl 8(%esp), %eax +; X32: movw %ax, 2(%{{.*}}) +} + +define void @test5(i64* nocapture %a0, i16 zeroext %a1) nounwind ssp { +entry: + %A = load i64* %a0, align 4 + %B = and i64 %A, -4294901761 ; 0xFFFFFFFF0000FFFF + %C = zext i16 %a1 to i64 + %CS = shl i64 %C, 16 + %D = or i64 %B, %CS + store i64 %D, i64* %a0, align 4 + ret void +; X64: test5: +; X64: movw %si, 2(%rdi) + +; X32: test5: +; X32: movzwl 8(%esp), %eax +; X32: movw %ax, 2(%{{.*}}) +} + +define void @test6(i64* nocapture %a0, i8 zeroext %a1) nounwind ssp { +entry: + %A = load i64* %a0, align 4 + %B = and i64 %A, -280375465082881 ; 0xFFFF00FFFFFFFFFF + %C = zext i8 %a1 to i64 + %CS = shl i64 %C, 40 + %D = or i64 %B, %CS + store i64 %D, i64* %a0, align 4 + ret void +; X64: test6: +; X64: movb %sil, 5(%rdi) + + +; X32: test6: +; X32: movb 8(%esp), %al +; X32: movb %al, 5(%{{.*}}) +} + +define i32 @test7(i64* nocapture %a0, i8 zeroext %a1, i32* %P2) nounwind { +entry: + %OtherLoad = load i32 *%P2 + %A = load i64* %a0, align 4 + %B = and i64 %A, -280375465082881 ; 0xFFFF00FFFFFFFFFF + %C = zext i8 %a1 to i64 + %CS = shl i64 %C, 40 + %D = or i64 %B, %CS + store i64 %D, i64* %a0, align 4 + ret i32 %OtherLoad +; X64: test7: +; X64: movb %sil, 5(%rdi) + + +; X32: test7: +; X32: movb 8(%esp), %cl +; X32: movb %cl, 5(%{{.*}}) +} + diff --git a/test/CodeGen/X86/tail-opts.ll b/test/CodeGen/X86/tail-opts.ll index 7b21e1bd7209..9662ad6cd740 100644 --- a/test/CodeGen/X86/tail-opts.ll +++ b/test/CodeGen/X86/tail-opts.ll @@ -110,16 +110,16 @@ altret: ; CHECK: dont_merge_oddly: ; CHECK-NOT: ret ; CHECK: ucomiss %xmm1, %xmm2 -; CHECK-NEXT: jbe .LBB3_3 +; CHECK-NEXT: jbe .LBB2_3 ; CHECK-NEXT: ucomiss %xmm0, %xmm1 -; CHECK-NEXT: ja .LBB3_4 -; CHECK-NEXT: .LBB3_2: +; CHECK-NEXT: ja .LBB2_4 +; CHECK-NEXT: .LBB2_2: ; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB3_3: +; CHECK-NEXT: .LBB2_3: ; CHECK-NEXT: ucomiss %xmm0, %xmm2 -; CHECK-NEXT: jbe .LBB3_2 -; CHECK-NEXT: .LBB3_4: +; CHECK-NEXT: jbe .LBB2_2 +; CHECK-NEXT: .LBB2_4: ; CHECK-NEXT: xorb %al, %al ; CHECK-NEXT: ret @@ -153,19 +153,19 @@ bb30: ; an unconditional jump to complete a two-way conditional branch. ; CHECK: c_expand_expr_stmt: -; CHECK: jmp .LBB4_7 -; CHECK-NEXT: .LBB4_12: +; CHECK: jmp .LBB3_7 +; CHECK-NEXT: .LBB3_12: ; CHECK-NEXT: movq 8(%rax), %rax ; CHECK-NEXT: movb 16(%rax), %al ; CHECK-NEXT: cmpb $16, %al -; CHECK-NEXT: je .LBB4_6 +; CHECK-NEXT: je .LBB3_6 ; CHECK-NEXT: cmpb $23, %al -; CHECK-NEXT: je .LBB4_6 -; CHECK-NEXT: jmp .LBB4_15 -; CHECK-NEXT: .LBB4_14: +; CHECK-NEXT: je .LBB3_6 +; CHECK-NEXT: jmp .LBB3_15 +; CHECK-NEXT: .LBB3_14: ; CHECK-NEXT: cmpb $23, %bl -; CHECK-NEXT: jne .LBB4_15 -; CHECK-NEXT: .LBB4_15: +; CHECK-NEXT: jne .LBB3_15 +; CHECK-NEXT: .LBB3_15: %0 = type { %struct.rtx_def* } %struct.lang_decl = type opaque @@ -275,7 +275,7 @@ declare fastcc %union.tree_node* @default_conversion(%union.tree_node*) nounwind ; CHECK: foo: ; CHECK: callq func -; CHECK-NEXT: .LBB5_2: +; CHECK-NEXT: .LBB4_2: ; CHECK-NEXT: addq $8, %rsp ; CHECK-NEXT: ret @@ -406,3 +406,26 @@ bb12: return: ret void } + +; Tail-merging should merge the two ret instructions since one side +; can fall-through into the ret and the other side has to branch anyway. + +; CHECK: TESTE: +; CHECK: imulq +; CHECK-NEXT: LBB8_2: +; CHECK-NEXT: ret + +define i64 @TESTE(i64 %parami, i64 %paraml) nounwind readnone { +entry: + %cmp = icmp slt i64 %parami, 1 ; <i1> [#uses=1] + %varx.0 = select i1 %cmp, i64 1, i64 %parami ; <i64> [#uses=1] + %cmp410 = icmp slt i64 %paraml, 1 ; <i1> [#uses=1] + br i1 %cmp410, label %for.end, label %bb.nph + +bb.nph: ; preds = %entry + %tmp15 = mul i64 %paraml, %parami ; <i64> [#uses=1] + ret i64 %tmp15 + +for.end: ; preds = %entry + ret i64 %varx.0 +} diff --git a/test/CodeGen/X86/tls11.ll b/test/CodeGen/X86/tls11.ll index a2c1a1f75deb..514a168c5387 100644 --- a/test/CodeGen/X86/tls11.ll +++ b/test/CodeGen/X86/tls11.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu > %t -; RUN: grep {movw %gs:i@NTPOFF, %ax} %t +; RUN: grep {movzwl %gs:i@NTPOFF, %eax} %t ; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu > %t2 -; RUN: grep {movw %fs:i@TPOFF, %ax} %t2 +; RUN: grep {movzwl %fs:i@TPOFF, %eax} %t2 @i = thread_local global i16 15 diff --git a/test/CodeGen/X86/unaligned-load.ll b/test/CodeGen/X86/unaligned-load.ll index 47b7896bb8f1..a99af0605b12 100644 --- a/test/CodeGen/X86/unaligned-load.ll +++ b/test/CodeGen/X86/unaligned-load.ll @@ -13,9 +13,7 @@ entry: bb: %String2Loc9 = getelementptr inbounds [31 x i8]* %String2Loc, i64 0, i64 0 call void @llvm.memcpy.i64(i8* %String2Loc9, i8* getelementptr inbounds ([31 x i8]* @.str3, i64 0, i64 0), i64 31, i32 1) -; I386: movsd _.str3+16 -; I386: movsd _.str3+8 -; I386: movsd _.str3 +; I386: call {{_?}}memcpy ; CORE2: movabsq ; CORE2: movabsq @@ -30,8 +28,9 @@ return: declare void @llvm.memcpy.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind -; CORE2: .align 3 +; CORE2: .section +; CORE2: .align 4 ; CORE2-NEXT: _.str1: ; CORE2-NEXT: .asciz "DHRYSTONE PROGRAM, SOME STRING" -; CORE2: .align 3 +; CORE2: .align 4 ; CORE2-NEXT: _.str3: diff --git a/test/CodeGen/X86/vec_shuffle-36.ll b/test/CodeGen/X86/vec_shuffle-36.ll index 1ea37c881e71..8090afc7434d 100644 --- a/test/CodeGen/X86/vec_shuffle-36.ll +++ b/test/CodeGen/X86/vec_shuffle-36.ll @@ -13,4 +13,4 @@ define <8 x i16> @shuf7(<8 x i16> %t0) { ; CHECK: pshufd %tmp10 = shufflevector <8 x i16> %t0, <8 x i16> undef, <8 x i32> < i32 undef, i32 2, i32 2, i32 2, i32 2, i32 2, i32 undef, i32 undef > ret <8 x i16> %tmp10 -}
\ No newline at end of file +} diff --git a/test/CodeGen/X86/vec_ss_load_fold.ll b/test/CodeGen/X86/vec_ss_load_fold.ll index c8b2927b71f3..3bd3f7b60b3b 100644 --- a/test/CodeGen/X86/vec_ss_load_fold.ll +++ b/test/CodeGen/X86/vec_ss_load_fold.ll @@ -16,9 +16,9 @@ define i16 @test1(float %f) nounwind { %tmp69 = trunc i32 %tmp.upgrd.1 to i16 ; <i16> [#uses=1] ret i16 %tmp69 ; CHECK: test1: -; CHECK: subss LCPI1_ -; CHECK: mulss LCPI1_ -; CHECK: minss LCPI1_ +; CHECK: subss LCPI0_ +; CHECK: mulss LCPI0_ +; CHECK: minss LCPI0_ } define i16 @test2(float %f) nounwind { @@ -31,9 +31,9 @@ define i16 @test2(float %f) nounwind { %tmp69 = trunc i32 %tmp to i16 ; <i16> [#uses=1] ret i16 %tmp69 ; CHECK: test2: -; CHECK: addss LCPI2_ -; CHECK: mulss LCPI2_ -; CHECK: minss LCPI2_ +; CHECK: addss LCPI1_ +; CHECK: mulss LCPI1_ +; CHECK: minss LCPI1_ } declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>) diff --git a/test/CodeGen/X86/widen_load-2.ll b/test/CodeGen/X86/widen_load-2.ll index 658c05143e84..551704c498fa 100644 --- a/test/CodeGen/X86/widen_load-2.ll +++ b/test/CodeGen/X86/widen_load-2.ll @@ -24,10 +24,10 @@ define void @add3i32_2(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) { ; CHECK: paddd ; CHECK: pextrd ; CHECK: movq - %a = load %i32vec3* %ap - %b = load %i32vec3* %bp + %a = load %i32vec3* %ap, align 8 + %b = load %i32vec3* %bp, align 8 %x = add %i32vec3 %a, %b - store %i32vec3 %x, %i32vec3* %ret + store %i32vec3 %x, %i32vec3* %ret, align 8 ret void } diff --git a/test/CodeGen/X86/xor.ll b/test/CodeGen/X86/xor.ll index f270d9d56e21..6c623cb15538 100644 --- a/test/CodeGen/X86/xor.ll +++ b/test/CodeGen/X86/xor.ll @@ -80,11 +80,11 @@ bb: bb12: ret i16 %tmp3 ; X64: test5: -; X64: notw [[REG:%[a-z]+]] -; X64: andw {{.*}}[[REG]] +; X64: notl [[REG:%[a-z]+]] +; X64: andl {{.*}}[[REG]] ; X32: test5: -; X32: notw [[REG:%[a-z]+]] -; X32: andw {{.*}}[[REG]] +; X32: notl [[REG:%[a-z]+]] +; X32: andl {{.*}}[[REG]] } define i8 @test6(i8 %a, i8 %b) nounwind { diff --git a/test/CodeGen/XCore/2010-04-07-DbgValueOtherTargets.ll b/test/CodeGen/XCore/2010-04-07-DbgValueOtherTargets.ll new file mode 100644 index 000000000000..f24e1d1851b4 --- /dev/null +++ b/test/CodeGen/XCore/2010-04-07-DbgValueOtherTargets.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -march=xcore -asm-verbose < %s | FileCheck %s +; Check that DEBUG_VALUE comments come through on a variety of targets. + +%tart.reflect.ComplexType = type { double, double } + +@.type.SwitchStmtTest = constant %tart.reflect.ComplexType { double 3.0, double 2.0 } + +define i32 @"main(tart.core.String[])->int32"(i32 %args) { +entry: +; CHECK: DEBUG_VALUE + tail call void @llvm.dbg.value(metadata !14, i64 0, metadata !8) + tail call void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType* @.type.SwitchStmtTest) ; <%tart.core.Object*> [#uses=2] + ret i32 3 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare void @"tart.reflect.ComplexType.create->tart.core.Object"(%tart.reflect.ComplexType*) nounwind readnone + +!0 = metadata !{i32 458769, i32 0, i32 1, metadata !"sm.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 458790, metadata !0, metadata !"", metadata !0, i32 0, i64 192, i64 64, i64 0, i32 0, metadata !2} ; [ DW_TAG_const_type ] +!2 = metadata !{i32 458771, metadata !0, metadata !"C", metadata !0, i32 1, i64 192, i64 64, i64 0, i32 0, null, metadata !3, i32 0, null} ; [ DW_TAG_structure_type ] +!3 = metadata !{metadata !4, metadata !6, metadata !7} +!4 = metadata !{i32 458765, metadata !2, metadata !"x", metadata !0, i32 1, i64 64, i64 64, i64 0, i32 0, metadata !5} ; [ DW_TAG_member ] +!5 = metadata !{i32 458788, metadata !0, metadata !"double", metadata !0, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 458765, metadata !2, metadata !"y", metadata !0, i32 1, i64 64, i64 64, i64 64, i32 0, metadata !5} ; [ DW_TAG_member ] +!7 = metadata !{i32 458765, metadata !2, metadata !"z", metadata !0, i32 1, i64 64, i64 64, i64 128, i32 0, metadata !5} ; [ DW_TAG_member ] +!8 = metadata !{i32 459008, metadata !9, metadata !"t", metadata !0, i32 5, metadata !2} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 458763, metadata !10} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 458798, i32 0, metadata !0, metadata !"foo", metadata !"foo", metadata !"foo", metadata !0, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 458773, metadata !0, metadata !"", metadata !0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 458788, metadata !0, metadata !"int", metadata !0, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{%tart.reflect.ComplexType* @.type.SwitchStmtTest} diff --git a/test/CodeGen/XCore/constants.ll b/test/CodeGen/XCore/constants.ll index 95fa11e77470..cad1a2153f4f 100644 --- a/test/CodeGen/XCore/constants.ll +++ b/test/CodeGen/XCore/constants.ll @@ -1,10 +1,10 @@ ; RUN: llc < %s -march=xcore -mcpu=xs1b-generic | FileCheck %s ; CHECK: .section .cp.rodata.cst4,"aMc",@progbits,4 -; CHECK: .LCPI1_0: +; CHECK: .LCPI0_0: ; CHECK: .long 12345678 ; CHECK: f: -; CHECK: ldw r0, cp[.LCPI1_0] +; CHECK: ldw r0, cp[.LCPI0_0] define i32 @f() { entry: ret i32 12345678 diff --git a/test/DebugInfo/2009-10-16-Phi.ll b/test/DebugInfo/2009-10-16-Phi.ll index fc0375186df9..0f799e3a7892 100644 --- a/test/DebugInfo/2009-10-16-Phi.ll +++ b/test/DebugInfo/2009-10-16-Phi.ll @@ -10,4 +10,4 @@ B2: ret i32 %0 } -!0 = metadata !{i32 42}
\ No newline at end of file +!0 = metadata !{i32 42} diff --git a/test/DebugInfo/2010-01-18-DbgValue.ll b/test/DebugInfo/2010-01-18-DbgValue.ll index ff97b189440e..001f853dd236 100644 --- a/test/DebugInfo/2010-01-18-DbgValue.ll +++ b/test/DebugInfo/2010-01-18-DbgValue.ll @@ -5,51 +5,47 @@ target triple = "i386-apple-darwin9.8" ; Currently, dbg.declare generates a DEBUG_VALUE comment. Eventually it will ; generate DWARF and this test will need to be modified or removed. -@Y = common global i32 0 ; <i32*> [#uses=1] -define i32 @test() nounwind { +%struct.Pt = type { double, double } +%struct.Rect = type { %struct.Pt, %struct.Pt } + +define double @foo(%struct.Rect* byval %my_r0) nounwind ssp { entry: -; CHECK: DEBUG_VALUE: - %retval = alloca i32 ; <i32*> [#uses=2] - %X = alloca i32 ; <i32*> [#uses=5] - %0 = alloca i32 ; <i32*> [#uses=2] +;CHECK: DEBUG_VALUE + %retval = alloca double ; <double*> [#uses=2] + %0 = alloca double ; <double*> [#uses=2] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] - call void @llvm.dbg.declare(metadata !{i32* %X}, metadata !3), !dbg !7 - store i32 4, i32* %X, align 4, !dbg !8 - %1 = load i32* %X, align 4, !dbg !9 ; <i32> [#uses=1] - call void @use(i32 %1) nounwind, !dbg !9 - %2 = load i32* @Y, align 4, !dbg !10 ; <i32> [#uses=1] - %3 = add nsw i32 %2, 2, !dbg !10 ; <i32> [#uses=1] - store i32 %3, i32* %X, align 4, !dbg !10 - %4 = load i32* %X, align 4, !dbg !11 ; <i32> [#uses=1] - call void @use(i32 %4) nounwind, !dbg !11 - %5 = load i32* %X, align 4, !dbg !12 ; <i32> [#uses=1] - store i32 %5, i32* %0, align 4, !dbg !12 - %6 = load i32* %0, align 4, !dbg !12 ; <i32> [#uses=1] - store i32 %6, i32* %retval, align 4, !dbg !12 - br label %return, !dbg !12 + call void @llvm.dbg.declare(metadata !{%struct.Rect* %my_r0}, metadata !0), !dbg !15 + %1 = getelementptr inbounds %struct.Rect* %my_r0, i32 0, i32 0, !dbg !16 ; <%struct.Pt*> [#uses=1] + %2 = getelementptr inbounds %struct.Pt* %1, i32 0, i32 0, !dbg !16 ; <double*> [#uses=1] + %3 = load double* %2, align 8, !dbg !16 ; <double> [#uses=1] + store double %3, double* %0, align 8, !dbg !16 + %4 = load double* %0, align 8, !dbg !16 ; <double> [#uses=1] + store double %4, double* %retval, align 8, !dbg !16 + br label %return, !dbg !16 return: ; preds = %entry - %retval1 = load i32* %retval, !dbg !12 ; <i32> [#uses=1] - ret i32 %retval1, !dbg !12 + %retval1 = load double* %retval, !dbg !16 ; <double> [#uses=1] + ret double %retval1, !dbg !16 } declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone -declare void @use(i32) - -!llvm.dbg.gv = !{!0} - -!0 = metadata !{i32 458804, i32 0, metadata !1, metadata !"Y", metadata !"Y", metadata !"Y", metadata !1, i32 2, metadata !2, i1 false, i1 true, i32* @Y} ; [ DW_TAG_variable ] -!1 = metadata !{i32 458769, i32 0, i32 1, metadata !"try.c", metadata !"/Volumes/MacOS9/tests/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!2 = metadata !{i32 458788, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!3 = metadata !{i32 459008, metadata !4, metadata !"X", metadata !1, i32 4, metadata !2} ; [ DW_TAG_auto_variable ] -!4 = metadata !{i32 458798, i32 0, metadata !1, metadata !"", metadata !"", metadata !"test", metadata !1, i32 3, metadata !5, i1 false, i1 true, i32 0, i32 0, null} ; [ DW_TAG_subprogram ] -!5 = metadata !{i32 458773, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0} ; [ DW_TAG_subroutine_type ] -!6 = metadata !{metadata !2} -!7 = metadata !{i32 3, i32 0, metadata !4, null} -!8 = metadata !{i32 4, i32 0, metadata !4, null} -!9 = metadata !{i32 5, i32 0, metadata !4, null} -!10 = metadata !{i32 6, i32 0, metadata !4, null} -!11 = metadata !{i32 7, i32 0, metadata !4, null} -!12 = metadata !{i32 8, i32 0, metadata !4, null} +!0 = metadata !{i32 524545, metadata !1, metadata !"my_r0", metadata !2, i32 11, metadata !7} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 11, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 524329, metadata !"b2.c", metadata !"/tmp/", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"b2.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{metadata !6, metadata !7} +!6 = metadata !{i32 524324, metadata !2, metadata !"double", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 524307, metadata !2, metadata !"Rect", metadata !2, i32 6, i64 256, i64 64, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_structure_type ] +!8 = metadata !{metadata !9, metadata !14} +!9 = metadata !{i32 524301, metadata !7, metadata !"P1", metadata !2, i32 7, i64 128, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_member ] +!10 = metadata !{i32 524307, metadata !2, metadata !"Pt", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_structure_type ] +!11 = metadata !{metadata !12, metadata !13} +!12 = metadata !{i32 524301, metadata !10, metadata !"x", metadata !2, i32 2, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] +!13 = metadata !{i32 524301, metadata !10, metadata !"y", metadata !2, i32 3, i64 64, i64 64, i64 64, i32 0, metadata !6} ; [ DW_TAG_member ] +!14 = metadata !{i32 524301, metadata !7, metadata !"P2", metadata !2, i32 8, i64 128, i64 64, i64 128, i32 0, metadata !10} ; [ DW_TAG_member ] +!15 = metadata !{i32 11, i32 0, metadata !1, null} +!16 = metadata !{i32 12, i32 0, metadata !17, null} +!17 = metadata !{i32 524299, metadata !1, i32 11, i32 0} ; [ DW_TAG_lexical_block ] diff --git a/test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll b/test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll new file mode 100644 index 000000000000..dd6c5a965eb6 --- /dev/null +++ b/test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll @@ -0,0 +1,89 @@ +; RUN: llvm-as < %s | llc -asm-verbose -O0 | grep AT_specification | count 2 +; Radar 7833483 +; Do not emit AT_specification for nested function foo. + +%class.A = type { i8 } +%class.B = type { i8 } + +define i32 @main() ssp { +entry: + %retval = alloca i32, align 4 ; <i32*> [#uses=3] + %b = alloca %class.A, align 1 ; <%class.A*> [#uses=1] + store i32 0, i32* %retval + call void @llvm.dbg.declare(metadata !{%class.A* %b}, metadata !0), !dbg !14 + %call = call i32 @_ZN1B2fnEv(%class.A* %b), !dbg !15 ; <i32> [#uses=1] + store i32 %call, i32* %retval, !dbg !15 + %0 = load i32* %retval, !dbg !16 ; <i32> [#uses=1] + ret i32 %0, !dbg !16 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +define linkonce_odr i32 @_ZN1B2fnEv(%class.A* %this) ssp align 2 { +entry: + %retval = alloca i32, align 4 ; <i32*> [#uses=2] + %this.addr = alloca %class.A*, align 8 ; <%class.A**> [#uses=2] + %a = alloca %class.A, align 1 ; <%class.A*> [#uses=1] + %i = alloca i32, align 4 ; <i32*> [#uses=2] + store %class.A* %this, %class.A** %this.addr + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !17), !dbg !18 + %this1 = load %class.A** %this.addr ; <%class.A*> [#uses=0] + call void @llvm.dbg.declare(metadata !{%class.A* %a}, metadata !19), !dbg !27 + call void @llvm.dbg.declare(metadata !{i32* %i}, metadata !28), !dbg !29 + %call = call i32 @_ZZN1B2fnEvEN1A3fooEv(%class.A* %a), !dbg !30 ; <i32> [#uses=1] + store i32 %call, i32* %i, !dbg !30 + %tmp = load i32* %i, !dbg !31 ; <i32> [#uses=1] + store i32 %tmp, i32* %retval, !dbg !31 + %0 = load i32* %retval, !dbg !32 ; <i32> [#uses=1] + ret i32 %0, !dbg !32 +} + +define internal i32 @_ZZN1B2fnEvEN1A3fooEv(%class.A* %this) ssp align 2 { +entry: + %retval = alloca i32, align 4 ; <i32*> [#uses=2] + %this.addr = alloca %class.A*, align 8 ; <%class.A**> [#uses=2] + store %class.A* %this, %class.A** %this.addr + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !33), !dbg !34 + %this1 = load %class.A** %this.addr ; <%class.A*> [#uses=0] + store i32 42, i32* %retval, !dbg !35 + %0 = load i32* %retval, !dbg !35 ; <i32> [#uses=1] + ret i32 %0, !dbg !35 +} + +!0 = metadata !{i32 524544, metadata !1, metadata !"b", metadata !3, i32 16, metadata !8} ; [ DW_TAG_auto_variable ] +!1 = metadata !{i32 524299, metadata !2, i32 15, i32 12} ; [ DW_TAG_lexical_block ] +!2 = metadata !{i32 524334, i32 0, metadata !3, metadata !"main", metadata !"main", metadata !"main", metadata !3, i32 15, metadata !5, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!3 = metadata !{i32 524329, metadata !"one.cc", metadata !"/tmp", metadata !4} ; [ DW_TAG_file_type ] +!4 = metadata !{i32 524305, i32 0, i32 4, metadata !"one.cc", metadata !"/tmp", metadata !"clang 1.5", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!5 = metadata !{i32 524309, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0, null} ; [ DW_TAG_subroutine_type ] +!6 = metadata !{metadata !7} +!7 = metadata !{i32 524324, metadata !3, metadata !"int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!8 = metadata !{i32 524290, metadata !3, metadata !"B", metadata !3, i32 2, i64 8, i64 8, i64 0, i32 0, null, metadata !9, i32 0, null} ; [ DW_TAG_class_type ] +!9 = metadata !{metadata !10} +!10 = metadata !{i32 524334, i32 0, metadata !8, metadata !"fn", metadata !"fn", metadata !"_ZN1B2fnEv", metadata !3, i32 4, metadata !11, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 524309, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !7, metadata !13} +!13 = metadata !{i32 524303, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !8} ; [ DW_TAG_pointer_type ] +!14 = metadata !{i32 16, i32 5, metadata !1, null} +!15 = metadata !{i32 17, i32 3, metadata !1, null} +!16 = metadata !{i32 18, i32 1, metadata !2, null} +!17 = metadata !{i32 524545, metadata !10, metadata !"this", metadata !3, i32 4, metadata !13} ; [ DW_TAG_arg_variable ] +!18 = metadata !{i32 4, i32 7, metadata !10, null} +!19 = metadata !{i32 524544, metadata !20, metadata !"a", metadata !3, i32 9, metadata !21} ; [ DW_TAG_auto_variable ] +!20 = metadata !{i32 524299, metadata !10, i32 4, i32 12} ; [ DW_TAG_lexical_block ] +!21 = metadata !{i32 524290, metadata !10, metadata !"A", metadata !3, i32 5, i64 8, i64 8, i64 0, i32 0, null, metadata !22, i32 0, null} ; [ DW_TAG_class_type ] +!22 = metadata !{metadata !23} +!23 = metadata !{i32 524334, i32 0, metadata !21, metadata !"foo", metadata !"foo", metadata !"_ZZN1B2fnEvEN1A3fooEv", metadata !3, i32 7, metadata !24, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!24 = metadata !{i32 524309, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !25, i32 0, null} ; [ DW_TAG_subroutine_type ] +!25 = metadata !{metadata !7, metadata !26} +!26 = metadata !{i32 524303, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !21} ; [ DW_TAG_pointer_type ] +!27 = metadata !{i32 9, i32 7, metadata !20, null} +!28 = metadata !{i32 524544, metadata !20, metadata !"i", metadata !3, i32 10, metadata !7} ; [ DW_TAG_auto_variable ] +!29 = metadata !{i32 10, i32 9, metadata !20, null} +!30 = metadata !{i32 10, i32 5, metadata !20, null} +!31 = metadata !{i32 11, i32 5, metadata !20, null} +!32 = metadata !{i32 12, i32 3, metadata !10, null} +!33 = metadata !{i32 524545, metadata !23, metadata !"this", metadata !3, i32 7, metadata !26} ; [ DW_TAG_arg_variable ] +!34 = metadata !{i32 7, i32 11, metadata !23, null} +!35 = metadata !{i32 7, i32 19, metadata !36, null} +!36 = metadata !{i32 524299, metadata !23, i32 7, i32 17} ; [ DW_TAG_lexical_block ] diff --git a/test/DebugInfo/2010-04-13-PubType.ll b/test/DebugInfo/2010-04-13-PubType.ll new file mode 100644 index 000000000000..371169fe1839 --- /dev/null +++ b/test/DebugInfo/2010-04-13-PubType.ll @@ -0,0 +1,47 @@ +; RUN: llc -O0 -asm-verbose < %s > %t +; RUN: grep "External Name" %t | grep -v X +; RUN: grep "External Name" %t | grep Y | count 1 +; Test to check type with no defintion is listed in pubtypes section. +%struct.X = type opaque +%struct.Y = type { i32 } + +define i32 @foo(%struct.X* %x, %struct.Y* %y) nounwind ssp { +entry: + %x_addr = alloca %struct.X* ; <%struct.X**> [#uses=1] + %y_addr = alloca %struct.Y* ; <%struct.Y**> [#uses=1] + %retval = alloca i32 ; <i32*> [#uses=2] + %0 = alloca i32 ; <i32*> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + call void @llvm.dbg.declare(metadata !{%struct.X** %x_addr}, metadata !0), !dbg !13 + store %struct.X* %x, %struct.X** %x_addr + call void @llvm.dbg.declare(metadata !{%struct.Y** %y_addr}, metadata !14), !dbg !13 + store %struct.Y* %y, %struct.Y** %y_addr + store i32 0, i32* %0, align 4, !dbg !13 + %1 = load i32* %0, align 4, !dbg !13 ; <i32> [#uses=1] + store i32 %1, i32* %retval, align 4, !dbg !13 + br label %return, !dbg !13 + +return: ; preds = %entry + %retval1 = load i32* %retval, !dbg !13 ; <i32> [#uses=1] + ret i32 %retval1, !dbg !15 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +!0 = metadata !{i32 524545, metadata !1, metadata !"x", metadata !2, i32 7, metadata !7} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 7, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 524329, metadata !"a.c", metadata !"/tmp/", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"a.c", metadata !"/tmp/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{metadata !6, metadata !7, metadata !9} +!6 = metadata !{i32 524324, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !8} ; [ DW_TAG_pointer_type ] +!8 = metadata !{i32 524307, metadata !2, metadata !"X", metadata !2, i32 3, i64 0, i64 0, i64 0, i32 4, null, null, i32 0, null} ; [ DW_TAG_structure_type ] +!9 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_pointer_type ] +!10 = metadata !{i32 524307, metadata !2, metadata !"Y", metadata !2, i32 4, i64 32, i64 32, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_structure_type ] +!11 = metadata !{metadata !12} +!12 = metadata !{i32 524301, metadata !10, metadata !"x", metadata !2, i32 5, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] +!13 = metadata !{i32 7, i32 0, metadata !1, null} +!14 = metadata !{i32 524545, metadata !1, metadata !"y", metadata !2, i32 7, metadata !9} ; [ DW_TAG_arg_variable ] +!15 = metadata !{i32 7, i32 0, metadata !16, null} +!16 = metadata !{i32 524299, metadata !1, i32 7, i32 0} ; [ DW_TAG_lexical_block ] diff --git a/test/DebugInfo/2010-04-19-FramePtr.ll b/test/DebugInfo/2010-04-19-FramePtr.ll new file mode 100644 index 000000000000..30031219d4ea --- /dev/null +++ b/test/DebugInfo/2010-04-19-FramePtr.ll @@ -0,0 +1,30 @@ +; RUN: llc -asm-verbose -O0 -o %t < %s +; RUN: grep DW_AT_APPLE_omit_frame_ptr %t +; RUN: llc -disable-fp-elim -asm-verbose -O0 -o %t < %s +; RUN: grep -v DW_AT_APPLE_omit_frame_ptr %t + + +define i32 @foo() nounwind ssp { +entry: + %retval = alloca i32 ; <i32*> [#uses=2] + %0 = alloca i32 ; <i32*> [#uses=2] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + store i32 42, i32* %0, align 4, !dbg !0 + %1 = load i32* %0, align 4, !dbg !0 ; <i32> [#uses=1] + store i32 %1, i32* %retval, align 4, !dbg !0 + br label %return, !dbg !0 + +return: ; preds = %entry + %retval1 = load i32* %retval, !dbg !0 ; <i32> [#uses=1] + ret i32 %retval1, !dbg !7 +} + +!0 = metadata !{i32 2, i32 0, metadata !1, null} +!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 2, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 524329, metadata !"a.c", metadata !"/tmp", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"a.c", metadata !"/tmp", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{metadata !6} +!6 = metadata !{i32 524324, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 2, i32 0, metadata !8, null} +!8 = metadata !{i32 524299, metadata !1, i32 2, i32 0} ; [ DW_TAG_lexical_block ] diff --git a/test/DebugInfo/2010-03-22-CU-HighLow.ll b/test/DebugInfo/2010-04-25-CU-entry_pc.ll index 42c25e4711cc..de099b6b9c50 100644 --- a/test/DebugInfo/2010-03-22-CU-HighLow.ll +++ b/test/DebugInfo/2010-04-25-CU-entry_pc.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | grep low_pc | count 2 +; RUN: llc < %s | grep entry_pc | count 2 @i = global i32 1 ; <i32*> [#uses=0] !llvm.dbg.gv = !{!0} diff --git a/test/DebugInfo/2010-05-03-DisableFramePtr.ll b/test/DebugInfo/2010-05-03-DisableFramePtr.ll new file mode 100644 index 000000000000..4061bdc834d7 --- /dev/null +++ b/test/DebugInfo/2010-05-03-DisableFramePtr.ll @@ -0,0 +1,34 @@ +; RUN: llc -o /dev/null -disable-non-leaf-fp-elim < %s +; Radar 7937664 +%struct.AppleEvent = type opaque + +define void @DisposeDMNotificationUPP(void (%struct.AppleEvent*)* %userUPP) nounwind ssp { +entry: + %userUPP_addr = alloca void (%struct.AppleEvent*)* ; <void (%struct.AppleEvent*)**> [#uses=1] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + call void @llvm.dbg.declare(metadata !{void (%struct.AppleEvent*)** %userUPP_addr}, metadata !0), !dbg !13 + store void (%struct.AppleEvent*)* %userUPP, void (%struct.AppleEvent*)** %userUPP_addr + br label %return, !dbg !14 + +return: ; preds = %entry + ret void, !dbg !14 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +!0 = metadata !{i32 524545, metadata !1, metadata !"userUPP", metadata !2, i32 7, metadata !6} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"DisposeDMNotificationUPP", metadata !"DisposeDMNotificationUPP", metadata !"DisposeDMNotificationUPP", metadata !2, i32 7, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 524329, metadata !"t.c", metadata !"/Users/echeng/LLVM/radars/r7937664/", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"t.c", metadata !"/Users/echeng/LLVM/radars/r7937664/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 9999)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{null, metadata !6} +!6 = metadata !{i32 524310, metadata !2, metadata !"DMNotificationUPP", metadata !2, i32 6, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_typedef ] +!7 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !8} ; [ DW_TAG_pointer_type ] +!8 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !9, i32 0, null} ; [ DW_TAG_subroutine_type ] +!9 = metadata !{null, metadata !10} +!10 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ] +!11 = metadata !{i32 524310, metadata !2, metadata !"AppleEvent", metadata !2, i32 4, i64 0, i64 0, i64 0, i32 0, metadata !12} ; [ DW_TAG_typedef ] +!12 = metadata !{i32 524307, metadata !2, metadata !"AEDesc", metadata !2, i32 1, i64 0, i64 0, i64 0, i32 4, null, null, i32 0, null} ; [ DW_TAG_structure_type ] +!13 = metadata !{i32 7, i32 0, metadata !1, null} +!14 = metadata !{i32 8, i32 0, metadata !15, null} +!15 = metadata !{i32 524299, metadata !1, i32 7, i32 0} ; [ DW_TAG_lexical_block ] diff --git a/test/DebugInfo/2010-05-03-OriginDIE.ll b/test/DebugInfo/2010-05-03-OriginDIE.ll new file mode 100644 index 000000000000..0e1d1fddc412 --- /dev/null +++ b/test/DebugInfo/2010-05-03-OriginDIE.ll @@ -0,0 +1,86 @@ + +;RUN: llc < %s -o /dev/null +;Radar 7937109 + +%struct.anon = type { i64, i32, i32, i32, [1 x i32] } +%struct.gpm_t = type { i32, i8*, [16 x i8], i32, i64, i64, i64, i64, i64, i64, i32, i16, i16, [8 x %struct.gpmr_t] } +%struct.gpmr_t = type { [48 x i8], [48 x i8], [16 x i8], i64, i64, i64, i64, i16 } +%struct.gpt_t = type { [8 x i8], i32, i32, i32, i32, i64, i64, i64, i64, [16 x i8], %struct.anon } + +@llvm.used = appending global [1 x i8*] [i8* bitcast (void (%struct.gpm_t*, %struct.gpt_t*)* @gpt2gpm to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] + +define fastcc void @gpt2gpm(%struct.gpm_t* %gpm, %struct.gpt_t* %gpt) nounwind optsize ssp { +entry: + %data_addr.i18 = alloca i64, align 8 ; <i64*> [#uses=1] + %data_addr.i17 = alloca i64, align 8 ; <i64*> [#uses=2] + %data_addr.i16 = alloca i64, align 8 ; <i64*> [#uses=0] + %data_addr.i15 = alloca i32, align 4 ; <i32*> [#uses=0] + %data_addr.i = alloca i64, align 8 ; <i64*> [#uses=0] + %0 = getelementptr inbounds %struct.gpm_t* %gpm, i32 0, i32 2, i32 0 ; <i8*> [#uses=1] + %1 = getelementptr inbounds %struct.gpt_t* %gpt, i32 0, i32 9, i32 0 ; <i8*> [#uses=1] + call void @uuid_LtoB(i8* %0, i8* %1) nounwind, !dbg !0 + %a9 = volatile load i64* %data_addr.i18, align 8 ; <i64> [#uses=1] + %a10 = call i64 @llvm.bswap.i64(i64 %a9) nounwind ; <i64> [#uses=1] + %a11 = getelementptr inbounds %struct.gpt_t* %gpt, i32 0, i32 8, !dbg !7 ; <i64*> [#uses=1] + %a12 = load i64* %a11, align 4, !dbg !7 ; <i64> [#uses=1] + call void @llvm.dbg.declare(metadata !{i64* %data_addr.i17}, metadata !8) nounwind, !dbg !14 + store i64 %a12, i64* %data_addr.i17, align 8 + call void @llvm.dbg.value(metadata !6, i64 0, metadata !15) nounwind + call void @llvm.dbg.value(metadata !18, i64 0, metadata !19) nounwind + call void @llvm.dbg.declare(metadata !6, metadata !23) nounwind + call void @llvm.dbg.value(metadata !{i64* %data_addr.i17}, i64 0, metadata !34) nounwind + %a13 = volatile load i64* %data_addr.i17, align 8 ; <i64> [#uses=1] + %a14 = call i64 @llvm.bswap.i64(i64 %a13) nounwind ; <i64> [#uses=2] + %a15 = add i64 %a10, %a14, !dbg !7 ; <i64> [#uses=1] + %a16 = sub i64 %a15, %a14 ; <i64> [#uses=1] + %a17 = getelementptr inbounds %struct.gpm_t* %gpm, i32 0, i32 5, !dbg !7 ; <i64*> [#uses=1] + store i64 %a16, i64* %a17, align 4, !dbg !7 + ret void, !dbg !7 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +declare i32 @llvm.bswap.i32(i32) nounwind readnone + +declare i64 @llvm.bswap.i64(i64) nounwind readnone + +declare void @uuid_LtoB(i8*, i8*) + +!0 = metadata !{i32 808, i32 0, metadata !1, null} +!1 = metadata !{i32 524299, metadata !2, i32 807, i32 0} ; [ DW_TAG_lexical_block ] +!2 = metadata !{i32 524334, i32 0, metadata !3, metadata !"gpt2gpm", metadata !"gpt2gpm", metadata !"gpt2gpm", metadata !3, i32 807, metadata !5, i1 true, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!3 = metadata !{i32 524329, metadata !"G.c", metadata !"/tmp", metadata !4} ; [ DW_TAG_file_type ] +!4 = metadata !{i32 524305, i32 0, i32 1, metadata !"G.c", metadata !"/tmp", metadata !"llvm-gcc", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!5 = metadata !{i32 524309, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0, null} ; [ DW_TAG_subroutine_type ] +!6 = metadata !{null} +!7 = metadata !{i32 810, i32 0, metadata !1, null} +!8 = metadata !{i32 524545, metadata !9, metadata !"data", metadata !10, i32 201, metadata !11} ; [ DW_TAG_arg_variable ] +!9 = metadata !{i32 524334, i32 0, metadata !3, metadata !"_OSSwapInt64", metadata !"_OSSwapInt64", metadata !"_OSSwapInt64", metadata !10, i32 202, metadata !5, i1 true, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 524329, metadata !"OSByteOrder.h", metadata !"/usr/include/libkern/ppc", metadata !4} ; [ DW_TAG_file_type ] +!11 = metadata !{i32 524310, metadata !3, metadata !"uint64_t", metadata !12, i32 59, i64 0, i64 0, i64 0, i32 0, metadata !13} ; [ DW_TAG_typedef ] +!12 = metadata !{i32 524329, metadata !"stdint.h", metadata !"/usr/4.2.1/include", metadata !4} ; [ DW_TAG_file_type ] +!13 = metadata !{i32 524324, metadata !3, metadata !"long long unsigned int", metadata !3, i32 0, i64 64, i64 64, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!14 = metadata !{i32 202, i32 0, metadata !9, metadata !7} +!15 = metadata !{i32 524545, metadata !16, metadata !"base", metadata !10, i32 92, metadata !17} ; [ DW_TAG_arg_variable ] +!16 = metadata !{i32 524334, i32 0, metadata !3, metadata !"OSReadSwapInt64", metadata !"OSReadSwapInt64", metadata !"OSReadSwapInt64", metadata !10, i32 95, metadata !5, i1 true, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!17 = metadata !{i32 524303, metadata !3, metadata !"", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] +!18 = metadata !{i32 0} +!19 = metadata !{i32 524545, metadata !16, metadata !"byteOffset", metadata !10, i32 94, metadata !20} ; [ DW_TAG_arg_variable ] +!20 = metadata !{i32 524310, metadata !3, metadata !"uintptr_t", metadata !21, i32 114, i64 0, i64 0, i64 0, i32 0, metadata !22} ; [ DW_TAG_typedef ] +!21 = metadata !{i32 524329, metadata !"types.h", metadata !"/usr/include/ppc", metadata !4} ; [ DW_TAG_file_type ] +!22 = metadata !{i32 524324, metadata !3, metadata !"long unsigned int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!23 = metadata !{i32 524544, metadata !24, metadata !"u", metadata !10, i32 100, metadata !25} ; [ DW_TAG_auto_variable ] +!24 = metadata !{i32 524299, metadata !16, i32 95, i32 0} ; [ DW_TAG_lexical_block ] +!25 = metadata !{i32 524311, metadata !16, metadata !"", metadata !10, i32 97, i64 64, i64 64, i64 0, i32 0, null, metadata !26, i32 0, null} ; [ DW_TAG_union_type ] +!26 = metadata !{metadata !27, metadata !28} +!27 = metadata !{i32 524301, metadata !25, metadata !"u64", metadata !10, i32 98, i64 64, i64 64, i64 0, i32 0, metadata !11} ; [ DW_TAG_member ] +!28 = metadata !{i32 524301, metadata !25, metadata !"u32", metadata !10, i32 99, i64 64, i64 32, i64 0, i32 0, metadata !29} ; [ DW_TAG_member ] +!29 = metadata !{i32 524289, metadata !3, metadata !"", metadata !3, i32 0, i64 64, i64 32, i64 0, i32 0, metadata !30, metadata !32, i32 0, null} ; [ DW_TAG_array_type ] +!30 = metadata !{i32 524310, metadata !3, metadata !"uint32_t", metadata !12, i32 55, i64 0, i64 0, i64 0, i32 0, metadata !31} ; [ DW_TAG_typedef ] +!31 = metadata !{i32 524324, metadata !3, metadata !"unsigned int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!32 = metadata !{metadata !33} +!33 = metadata !{i32 524321, i64 0, i64 1} ; [ DW_TAG_subrange_type ] +!34 = metadata !{i32 524544, metadata !24, metadata !"addr", metadata !10, i32 96, metadata !35} ; [ DW_TAG_auto_variable ] +!35 = metadata !{i32 524303, metadata !3, metadata !"", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !11} ; [ DW_TAG_pointer_type ] diff --git a/test/FrontendC++/2009-07-16-Using.cpp b/test/FrontendC++/2009-07-16-Using.cpp index 1acadf642122..c0e031424acb 100644 --- a/test/FrontendC++/2009-07-16-Using.cpp +++ b/test/FrontendC++/2009-07-16-Using.cpp @@ -1,4 +1,4 @@ -// RUN: %llvmgxx %s -S +// RUN: %llvmgxx %s -S -o /dev/null namespace A { typedef int B; diff --git a/test/FrontendC++/2009-10-27-crash.cpp b/test/FrontendC++/2009-10-27-crash.cpp index 5641aa420507..21d0064c687b 100644 --- a/test/FrontendC++/2009-10-27-crash.cpp +++ b/test/FrontendC++/2009-10-27-crash.cpp @@ -1,4 +1,4 @@ -// RUN: %llvmgxx -emit-llvm -S %s +// RUN: %llvmgxx -emit-llvm -S %s -o /dev/null // Radar 7328944 typedef struct diff --git a/test/FrontendC++/2010-04-30-OptimizedMethod-Dbg.cpp b/test/FrontendC++/2010-04-30-OptimizedMethod-Dbg.cpp new file mode 100644 index 000000000000..dc9b16c28227 --- /dev/null +++ b/test/FrontendC++/2010-04-30-OptimizedMethod-Dbg.cpp @@ -0,0 +1,17 @@ +// RUN: %llvmgcc -g -S -O2 %s -o %t +// RUN: grep "i1 false, i1 true. . . DW_TAG_subprogram" %t | count 2 + +class foo { +public: + int bar(int x); + static int baz(int x); +}; + +int foo::bar(int x) { + return x*4 + 1; +} + +int foo::baz(int x) { + return x*4 + 1; +} + diff --git a/test/FrontendC/2007-05-16-EmptyStruct.c b/test/FrontendC/2007-05-16-EmptyStruct.c index 748aa98351d5..23c0b1d6a3f6 100644 --- a/test/FrontendC/2007-05-16-EmptyStruct.c +++ b/test/FrontendC/2007-05-16-EmptyStruct.c @@ -1,5 +1,5 @@ // PR 1417 -// RUN: %llvmgcc -xc %s -c -o - | llvm-dis | grep "struct.anon = type \{ \}" +// RUN: %llvmgcc -xc %s -c -o - | llvm-dis | grep "struct.anon = type \{\}" struct { } *X; diff --git a/test/FrontendC/2008-11-02-WeakAlias.c b/test/FrontendC/2008-11-02-WeakAlias.c index 4bdc5c7bec93..befafe455149 100644 --- a/test/FrontendC/2008-11-02-WeakAlias.c +++ b/test/FrontendC/2008-11-02-WeakAlias.c @@ -2,4 +2,4 @@ // PR2691 void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ"))); -void native_init_IRQ(void) {}
\ No newline at end of file +void native_init_IRQ(void) {} diff --git a/test/FrontendC/2009-01-20-k8.c b/test/FrontendC/2009-01-20-k8.c index d28302b4ce80..2cd15387390c 100644 --- a/test/FrontendC/2009-01-20-k8.c +++ b/test/FrontendC/2009-01-20-k8.c @@ -1,4 +1,4 @@ -// RUN: %llvmgcc %s -S -march=k8 +// RUN: %llvmgcc %s -S -march=k8 -o /dev/null // XFAIL: * // XTARGET: x86,i386,i686 long double x; diff --git a/test/FrontendC/2009-01-21-InvalidIterator.c b/test/FrontendC/2009-01-21-InvalidIterator.c index 310ea3bfa17b..6ac61f8a748b 100644 --- a/test/FrontendC/2009-01-21-InvalidIterator.c +++ b/test/FrontendC/2009-01-21-InvalidIterator.c @@ -1,4 +1,4 @@ -// RUN: %llvmgcc %s -S -g +// RUN: %llvmgcc %s -S -g -o /dev/null typedef long unsigned int size_t; typedef unsigned short int uint16_t; diff --git a/test/FrontendC/2009-04-22-UnknownSize.c b/test/FrontendC/2009-04-22-UnknownSize.c index 2b90c91fe22c..7db9c0730c80 100644 --- a/test/FrontendC/2009-04-22-UnknownSize.c +++ b/test/FrontendC/2009-04-22-UnknownSize.c @@ -1,4 +1,4 @@ -// RUN: not %llvmgcc -O1 %s -S |& grep {error: storage size} +// RUN: not %llvmgcc -O1 %s -S -o /dev/null |& grep {error: storage size} // PR2958 static struct foo s; struct foo *p = &s; diff --git a/test/FrontendC/2009-06-14-HighlyAligned.c b/test/FrontendC/2009-06-14-HighlyAligned.c index 4678b75b6daf..227db74f47a0 100644 --- a/test/FrontendC/2009-06-14-HighlyAligned.c +++ b/test/FrontendC/2009-06-14-HighlyAligned.c @@ -1,4 +1,4 @@ -// RUN: %llvmgcc %s -S +// RUN: %llvmgcc %s -S -o /dev/null // PR4332 static int highly_aligned __attribute__((aligned(4096))); diff --git a/test/FrontendC/2009-12-07-BitFieldAlignment.c b/test/FrontendC/2009-12-07-BitFieldAlignment.c index a8312a5fd8a9..02ff8bce1821 100644 --- a/test/FrontendC/2009-12-07-BitFieldAlignment.c +++ b/test/FrontendC/2009-12-07-BitFieldAlignment.c @@ -9,7 +9,7 @@ struct S { }; void f0(struct S *a) { -// CHECK: %3 = load i32* %2, align 4 -// CHECK: store i32 %4, i32* %2, align 4 +// CHECK: load {{.*}}, align 4 +// CHECK: store {{.*}}, align 4 a->e = 0; } diff --git a/test/FrontendC/crash-invalid-array.c b/test/FrontendC/crash-invalid-array.c new file mode 100644 index 000000000000..d602f7854585 --- /dev/null +++ b/test/FrontendC/crash-invalid-array.c @@ -0,0 +1,17 @@ +// RUN: not %llvmgcc -O1 %s -S |& grep {error: invalid use of array with unspecified bounds} +// PR6913 + +#include <stdio.h> + +int main() +{ + int x[10][10]; + int (*p)[] = x; // <-- this line is what triggered it + + int i; + + for(i = 0; i < 10; ++i) + { + p[i][i] = i; + } +} diff --git a/test/FrontendC/cstring-align.c b/test/FrontendC/cstring-align.c index 715d0f312690..b9ec281f5677 100644 --- a/test/FrontendC/cstring-align.c +++ b/test/FrontendC/cstring-align.c @@ -1,6 +1,5 @@ // RUN: %llvmgcc %s -c -Os -m32 -emit-llvm -o - | llc -march=x86 -mtriple=i386-apple-darwin10 | FileCheck %s -check-prefix=DARWIN32 // RUN: %llvmgcc %s -c -Os -m64 -emit-llvm -o - | llc -march=x86-64 -mtriple=x86_64-apple-darwin10 | FileCheck %s -check-prefix=DARWIN64 -// XFAIL: * // XTARGET: darwin extern void func(const char *, const char *); @@ -9,10 +8,10 @@ void long_function_name() { func("%s: the function name", __func__); } -// DARWIN64: .align 3 +// DARWIN64: .align 4 // DARWIN64: ___func__. // DARWIN64: .asciz "long_function_name" -// DARWIN32: .align 2 +// DARWIN32: .align 4 // DARWIN32: ___func__. // DARWIN32: .asciz "long_function_name" diff --git a/test/FrontendC/inline-asm-function.c b/test/FrontendC/inline-asm-function.c new file mode 100644 index 000000000000..e5848409865b --- /dev/null +++ b/test/FrontendC/inline-asm-function.c @@ -0,0 +1,6 @@ +// RUN: %llvmgcc -S %s -fasm-blocks -o - -O | grep naked +// 7533078 (partial). + +asm int f() { + xyz +} diff --git a/test/MC/AsmParser/X86/x86_32-encoding.s b/test/MC/AsmParser/X86/x86_32-encoding.s index 22627585220f..f973cb23b57a 100644 --- a/test/MC/AsmParser/X86/x86_32-encoding.s +++ b/test/MC/AsmParser/X86/x86_32-encoding.s @@ -9961,3 +9961,89 @@ // CHECK: aeskeygenassist $125, (%edx,%eax,4), %xmm2 // CHECK: encoding: [0x66,0x0f,0x3a,0xdf,0x14,0x82,0x7d] aeskeygenassist $125, (%edx,%eax,4), %xmm2 + +// rdar://7840289 +// CHECK: pshufb CPI1_0(%rip), %xmm1 +// CHECK: encoding: [0x66,0x0f,0x38,0x00,0x0d,A,A,A,A] +// CHECK: fixup A - offset: 5, value: CPI1_0-4 +pshufb CPI1_0(%rip), %xmm1 + +// rdar://7910087 +// CHECK: bsfw %bx, %bx +// CHECK: encoding: [0x66,0x0f,0xbc,0xdb] + bsfw %bx, %bx + +// CHECK: bsfw 3735928559(%ebx,%ecx,8), %bx +// CHECK: encoding: [0x66,0x0f,0xbc,0x9c,0xcb,0xef,0xbe,0xad,0xde] + bsfw 3735928559(%ebx,%ecx,8), %bx + +// CHECK: bsrw %bx, %bx +// CHECK: encoding: [0x66,0x0f,0xbd,0xdb] + bsrw %bx, %bx + +// CHECK: bsrw 305419896, %bx +// CHECK: encoding: [0x66,0x0f,0xbd,0x1d,0x78,0x56,0x34,0x12] + bsrw 305419896, %bx + +// radr://7901779 +// CHECK: pushl $127 +// CHECK: encoding: [0x6a,0xfe] + pushl $127 + +// CHECK: pushw $254 +// CHECK: encoding: [0x66,0x68,0xfe,0x00] + pushw $254 + +// CHECK: pushl $254 +// CHECK: encoding: [0x68,0xfe,0x00,0x00,0x00] + pushl $254 + +// radr://7928400 +// CHECK: movq %mm3, 3735928559(%ebx,%ecx,8) +// CHECK: encoding: [0x0f,0x7f,0x9c,0xcb,0xef,0xbe,0xad,0xde] + movq %mm3, 3735928559(%ebx,%ecx,8) + +// CHECK: movd %mm3, 3735928559(%ebx,%ecx,8) +// CHECK: encoding: [0x0f,0x7e,0x9c,0xcb,0xef,0xbe,0xad,0xde] + movd %mm3, 3735928559(%ebx,%ecx,8) + +// CHECK: movq 3735928559(%ebx,%ecx,8), %xmm5 +// CHECK: encoding: [0xf3,0x0f,0x7e,0xac,0xcb,0xef,0xbe,0xad,0xde] + movq 3735928559(%ebx,%ecx,8), %xmm5 + +// CHECK: movd 3735928559(%ebx,%ecx,8), %xmm5 +// CHECK: encoding: [0x66,0x0f,0x6e,0xac,0xcb,0xef,0xbe,0xad,0xde] + movd 3735928559(%ebx,%ecx,8), %xmm5 + +// radr://7914715 +// CHECK: fcoml 3735928559(%ebx,%ecx,8) +// CHECK: encoding: [0xdc,0x94,0xcb,0xef,0xbe,0xad,0xde] + fcoml 3735928559(%ebx,%ecx,8) + +// CHECK: fcoms 32493 +// CHECK: encoding: [0xd8,0x15,0xed,0x7e,0x00,0x00] + fcoms 32493 + +// CHECK: fcompl 3735928559(%ebx,%ecx,8) +// CHECK: encoding: [0xdc,0x9c,0xcb,0xef,0xbe,0xad,0xde] + fcompl 3735928559(%ebx,%ecx,8) + +// CHECK: fcomps 32493 +// CHECK: encoding: [0xd8,0x1d,0xed,0x7e,0x00,0x00] + fcomps 32493 + +// CHECK: ficoml 3735928559(%ebx,%ecx,8) +// CHECK: encoding: [0xda,0x94,0xcb,0xef,0xbe,0xad,0xde] + ficoml 3735928559(%ebx,%ecx,8) + +// CHECK: ficoms 32493 +// CHECK: encoding: [0xde,0x15,0xed,0x7e,0x00,0x00] + ficoms 32493 + +// CHECK: ficompl 3735928559(%ebx,%ecx,8) +// CHECK: encoding: [0xda,0x9c,0xcb,0xef,0xbe,0xad,0xde] + ficompl 3735928559(%ebx,%ecx,8) + +// CHECK: ficomps 32493 +// CHECK: encoding: [0xde,0x1d,0xed,0x7e,0x00,0x00] + ficomps 32493 diff --git a/test/MC/AsmParser/X86/x86_operands.s b/test/MC/AsmParser/X86/x86_operands.s index edddd1fc4492..bf958d8478ca 100644 --- a/test/MC/AsmParser/X86/x86_operands.s +++ b/test/MC/AsmParser/X86/x86_operands.s @@ -55,4 +55,6 @@ # CHECK: call *4(%eax) call *4(%eax) - +# CHECK: movl %gs:8, %eax +movl %gs:8, %eax + diff --git a/test/MC/AsmParser/exprs.s b/test/MC/AsmParser/exprs.s index 62b11c2d4e4e..d9a248cd94ff 100644 --- a/test/MC/AsmParser/exprs.s +++ b/test/MC/AsmParser/exprs.s @@ -61,3 +61,14 @@ n: movw $8, (42)+66(%eax) + +// "." support: +_f0: +L0: + jmp L1 + .long . - L0 +L1: + jmp A + .long . - L1 + + .zerofill __DATA,_bss,A,0 diff --git a/test/MC/Disassembler/arm-tests.txt b/test/MC/Disassembler/arm-tests.txt index 81261c59028d..a1e229caebf8 100644 --- a/test/MC/Disassembler/arm-tests.txt +++ b/test/MC/Disassembler/arm-tests.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s -# XFAIL: * # CHECK: b #0 0xfe 0xff 0xff 0xea @@ -16,9 +15,21 @@ # CHECK: dmb nshst 0x56 0xf0 0x7f 0xf5 +# CHECK: ldclvc p5, cr15, [r8], #-0 +0x00 0xf5 0x78 0x7c + # CHECK: ldr r0, [r2], #15 0x0f 0x00 0x92 0xe4 +# CHECK: ldrh r0, [r2], #0 +0xb0 0x00 0xd2 0xe0 + +# CHECK: ldrht r0, [r2], #15 +0xbf 0x00 0xf2 0xe0 + +# CHECK: ldrsbtvs lr, [r2], -r9 +0xd9 0xe9 0x32 0x60 + # CHECK: lsls r0, r2, #31 0x82 0x0f 0xb0 0xe1 @@ -28,6 +39,9 @@ # CHECK: movt r8, #65535 0xff 0x8f 0x4f 0xe3 +# CHECK: mvnpls r7, #245, 2 +0xf5 0x71 0xf0 0x53 + # CHECK: pkhbt r8, r9, r10, lsl #4 0x1a 0x82 0x89 0xe6 diff --git a/test/MC/Disassembler/dg.exp b/test/MC/Disassembler/dg.exp index 68d5f1de395b..fc2f17a6fbaa 100644 --- a/test/MC/Disassembler/dg.exp +++ b/test/MC/Disassembler/dg.exp @@ -1,4 +1,6 @@ load_lib llvm.exp -RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{txt}]] +if { [llvm_supports_target ARM] } { + RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{txt}]] +} diff --git a/test/MC/Disassembler/neon-tests.txt b/test/MC/Disassembler/neon-tests.txt index 25099c0a39b8..51b31e7c1a6e 100644 --- a/test/MC/Disassembler/neon-tests.txt +++ b/test/MC/Disassembler/neon-tests.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s -# XFAIL: * # CHECK: vbif q15, q7, q0 0x50 0xe1 0x7e 0xf3 @@ -10,6 +9,10 @@ # CHECK: vdup.32 q3, d1[0] 0x41 0x6c 0xb4 0xf3 +# VLD1q8_UPD (with ${dst:dregpair} operand) +# CHECK: vld1.8 {d17, d18}, [r6], r5 +0x05 0x1a 0x66 0xf4 + # CHECK: vld4.8 {d0, d1, d2, d3}, [r2], r7 0x07 0x00 0x22 0xf4 @@ -19,6 +22,9 @@ # CHECK: vmov d0, d15 0x1f 0x01 0x2f 0xf2 +# CHECK: vmov.i64 q6, #0xFF00FF00FF +0x75 0xce 0x81 0xf2 + # CHECK: vmul.f32 d0, d0, d6 0x16 0x0d 0x00 0xf3 diff --git a/test/MC/Disassembler/simple-tests.txt b/test/MC/Disassembler/simple-tests.txt index b6bb35dc56a1..41552612cf58 100644 --- a/test/MC/Disassembler/simple-tests.txt +++ b/test/MC/Disassembler/simple-tests.txt @@ -51,3 +51,6 @@ # CHECK: vmptrst 0x0f 0xc7 0x38 + +# CHECK: movl $0, -4(%rbp) +0xc7 0x45 0xfc 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/thumb-tests.txt b/test/MC/Disassembler/thumb-tests.txt index 343e6c94b19f..14e91295276b 100644 --- a/test/MC/Disassembler/thumb-tests.txt +++ b/test/MC/Disassembler/thumb-tests.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 | FileCheck %s -# XFAIL: * # CHECK: add r5, sp, #68 0x11 0xad @@ -10,6 +9,9 @@ # CHECK: b #34 0x0f 0xe0 +# CHECK: b.w #-12 +0xff 0xf7 0xf8 0xaf + # CHECK: bfi r2, r10, #0, #1 0x6a 0xf3 0x00 0x02 @@ -25,6 +27,9 @@ # CHECK: ldmia r0!, {r1} 0x02 0xc8 +# CHECK: ldrb.w r8, #-24 +0x1f 0xf8 0x18 0x80 + # CHECK: ldrd r0, r1, [r7, #64]! 0xf7 0xe9 0x10 0x01 @@ -55,6 +60,9 @@ # CHECK: subw r0, pc, #1 0xaf 0xf2 0x01 0x00 +# CHECK: subw r0, sp, #835 +0xad 0xf2 0x43 0x30 + # CHECK: uqadd16 r3, r4, r5 0x94 0xfa 0x55 0xf3 @@ -77,6 +85,9 @@ # CHECK: lsleq r1, r0, #28 0x01 0x07 -# CHECK: rsbne r1, r2, #0 -0x51 0x42 +# CHECK: stmiane r0!, {r1, r2, r3} +0x0e 0xc0 + # IT block end +# CHECK: rsbs r1, r2, #0 +0x51 0x42 diff --git a/test/Other/lint.ll b/test/Other/lint.ll new file mode 100644 index 000000000000..d0db5e46c668 --- /dev/null +++ b/test/Other/lint.ll @@ -0,0 +1,84 @@ +; RUN: opt -lint -disable-output < %s |& FileCheck %s +target datalayout = "e-p:64:64:64" + +declare fastcc void @bar() + +@CG = constant i32 7 + +define i32 @foo() noreturn { +; CHECK: Caller and callee calling convention differ + call void @bar() +; CHECK: Null pointer dereference + store i32 0, i32* null +; CHECK: Null pointer dereference + %t = load i32* null +; CHECK: Undef pointer dereference + store i32 0, i32* undef +; CHECK: Undef pointer dereference + %u = load i32* undef +; CHECK: Memory reference address is misaligned + %x = inttoptr i32 1 to i32* + load i32* %x, align 4 +; CHECK: Division by zero + %sd = sdiv i32 2, 0 +; CHECK: Division by zero + %ud = udiv i32 2, 0 +; CHECK: Division by zero + %sr = srem i32 2, 0 +; CHECK: Division by zero + %ur = urem i32 2, 0 +; CHECK: extractelement index out of range + %ee = extractelement <4 x i32> zeroinitializer, i32 4 +; CHECK: insertelement index out of range + %ie = insertelement <4 x i32> zeroinitializer, i32 0, i32 4 +; CHECK: Shift count out of range + %r = lshr i32 0, 32 +; CHECK: Shift count out of range + %q = ashr i32 0, 32 +; CHECK: Shift count out of range + %l = shl i32 0, 32 +; CHECK: xor(undef, undef) + %xx = xor i32 undef, undef +; CHECK: sub(undef, undef) + %xs = sub i32 undef, undef + +; CHECK: Write to read-only memory + store i32 8, i32* @CG +; CHECK: Write to text section + store i32 8, i32* bitcast (i32()* @foo to i32*) +; CHECK: Load from block address + %lb = load i32* bitcast (i8* blockaddress(@foo, %next) to i32*) +; CHECK: Call to block address + call void()* bitcast (i8* blockaddress(@foo, %next) to void()*)() + + br label %next + +next: +; CHECK: Static alloca outside of entry block + %a = alloca i32 +; CHECK: Return statement in function with noreturn attribute + ret i32 0 + +foo: + %z = add i32 0, 0 +; CHECK: unreachable immediately preceded by instruction without side effects + unreachable +} + +; CHECK: Unnamed function with non-local linkage +define void @0() nounwind { + ret void +} + +; CHECK: va_start called in a non-varargs function +declare void @llvm.va_start(i8*) +define void @not_vararg(i8* %p) nounwind { + call void @llvm.va_start(i8* %p) + ret void +} + +define void @use_indbr() { + indirectbr i8* bitcast (i32()* @foo to i8*), [label %block] +block: + unreachable +} diff --git a/test/Transforms/ArgumentPromotion/crash.ll b/test/Transforms/ArgumentPromotion/crash.ll new file mode 100644 index 000000000000..e2d3d4de9edb --- /dev/null +++ b/test/Transforms/ArgumentPromotion/crash.ll @@ -0,0 +1,38 @@ +; rdar://7879828 +; RUN: opt -inline -argpromotion %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +define void @foo() { + invoke void @foo2() + to label %if.end432 unwind label %for.end520 + +if.end432: + unreachable + +for.end520: + unreachable +} + +define internal void @foo2() ssp { + %call7 = call fastcc i8* @foo3(i1 (i8*)* @foo4) + %call58 = call fastcc i8* @foo3(i1 (i8*)* @foo5) + unreachable +} + +define internal fastcc i8* @foo3(i1 (i8*)* %Pred) { +entry: + unreachable +} + +define internal i1 @foo4(i8* %O) nounwind { +entry: + %call = call zeroext i1 @foo5(i8* %O) ; <i1> [#uses=0] + unreachable +} + +define internal i1 @foo5(i8* %O) nounwind { +entry: + ret i1 undef +} + diff --git a/test/Transforms/DeadArgElim/2009-03-17-MRE-Invoke.ll b/test/Transforms/DeadArgElim/2009-03-17-MRE-Invoke.ll index f251d6ce882c..161821f3f8f7 100644 --- a/test/Transforms/DeadArgElim/2009-03-17-MRE-Invoke.ll +++ b/test/Transforms/DeadArgElim/2009-03-17-MRE-Invoke.ll @@ -23,4 +23,4 @@ T: ret i32 %y T2: unreachable -}
\ No newline at end of file +} diff --git a/test/Transforms/DeadArgElim/2010-04-30-DbgInfo.ll b/test/Transforms/DeadArgElim/2010-04-30-DbgInfo.ll new file mode 100644 index 000000000000..2f820bad8474 --- /dev/null +++ b/test/Transforms/DeadArgElim/2010-04-30-DbgInfo.ll @@ -0,0 +1,68 @@ +; RUN: opt -S -deadargelim < %s | FileCheck %s + +@.str = private constant [1 x i8] zeroinitializer, align 1 ; <[1 x i8]*> [#uses=1] + +define i8* @vfs_addname(i8* %name, i32 %len, i32 %hash, i32 %flags) nounwind ssp { +entry: + call void @llvm.dbg.value(metadata !{i8* %name}, i64 0, metadata !0) + call void @llvm.dbg.value(metadata !{i32 %len}, i64 0, metadata !10) + call void @llvm.dbg.value(metadata !{i32 %hash}, i64 0, metadata !11) + call void @llvm.dbg.value(metadata !{i32 %flags}, i64 0, metadata !12) +; CHECK: call fastcc i8* @add_name_internal(i8* %name, i32 %hash) nounwind, !dbg !13 + %0 = call fastcc i8* @add_name_internal(i8* %name, i32 %len, i32 %hash, i8 zeroext 0, i32 %flags) nounwind, !dbg !13 ; <i8*> [#uses=1] + ret i8* %0, !dbg !13 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +define internal fastcc i8* @add_name_internal(i8* %name, i32 %len, i32 %hash, i8 zeroext %extra, i32 %flags) nounwind noinline ssp { +entry: + call void @llvm.dbg.value(metadata !{i8* %name}, i64 0, metadata !15) + call void @llvm.dbg.value(metadata !{i32 %len}, i64 0, metadata !20) + call void @llvm.dbg.value(metadata !{i32 %hash}, i64 0, metadata !21) + call void @llvm.dbg.value(metadata !{i8 %extra}, i64 0, metadata !22) + call void @llvm.dbg.value(metadata !{i32 %flags}, i64 0, metadata !23) + %0 = icmp eq i32 %hash, 0, !dbg !24 ; <i1> [#uses=1] + br i1 %0, label %bb, label %bb1, !dbg !24 + +bb: ; preds = %entry + br label %bb2, !dbg !26 + +bb1: ; preds = %entry + br label %bb2, !dbg !27 + +bb2: ; preds = %bb1, %bb + %.0 = phi i8* [ getelementptr inbounds ([1 x i8]* @.str, i64 0, i64 0), %bb ], [ %name, %bb1 ] ; <i8*> [#uses=1] + ret i8* %.0, !dbg !27 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!0 = metadata !{i32 524545, metadata !1, metadata !"name", metadata !2, i32 8, metadata !6} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 524334, i32 0, metadata !2, metadata !"vfs_addname", metadata !"vfs_addname", metadata !"vfs_addname", metadata !2, i32 12, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 524329, metadata !"tail.c", metadata !"/Users/echeng/LLVM/radars/r7927803/", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 524305, i32 0, i32 1, metadata !"tail.c", metadata !"/Users/echeng/LLVM/radars/r7927803/", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 9999)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{metadata !6, metadata !6, metadata !9, metadata !9, metadata !9} +!6 = metadata !{i32 524303, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !7} ; [ DW_TAG_pointer_type ] +!7 = metadata !{i32 524326, metadata !2, metadata !"", metadata !2, i32 0, i64 8, i64 8, i64 0, i32 0, metadata !8} ; [ DW_TAG_const_type ] +!8 = metadata !{i32 524324, metadata !2, metadata !"char", metadata !2, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] +!9 = metadata !{i32 524324, metadata !2, metadata !"unsigned int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!10 = metadata !{i32 524545, metadata !1, metadata !"len", metadata !2, i32 9, metadata !9} ; [ DW_TAG_arg_variable ] +!11 = metadata !{i32 524545, metadata !1, metadata !"hash", metadata !2, i32 10, metadata !9} ; [ DW_TAG_arg_variable ] +!12 = metadata !{i32 524545, metadata !1, metadata !"flags", metadata !2, i32 11, metadata !9} ; [ DW_TAG_arg_variable ] +!13 = metadata !{i32 13, i32 0, metadata !14, null} +!14 = metadata !{i32 524299, metadata !1, i32 12, i32 0} ; [ DW_TAG_lexical_block ] +!15 = metadata !{i32 524545, metadata !16, metadata !"name", metadata !2, i32 17, metadata !6} ; [ DW_TAG_arg_variable ] +!16 = metadata !{i32 524334, i32 0, metadata !2, metadata !"add_name_internal", metadata !"add_name_internal", metadata !"add_name_internal", metadata !2, i32 22, metadata !17, i1 true, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ] +!17 = metadata !{i32 524309, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !18, i32 0, null} ; [ DW_TAG_subroutine_type ] +!18 = metadata !{metadata !6, metadata !6, metadata !9, metadata !9, metadata !19, metadata !9} +!19 = metadata !{i32 524324, metadata !2, metadata !"unsigned char", metadata !2, i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ] +!20 = metadata !{i32 524545, metadata !16, metadata !"len", metadata !2, i32 18, metadata !9} ; [ DW_TAG_arg_variable ] +!21 = metadata !{i32 524545, metadata !16, metadata !"hash", metadata !2, i32 19, metadata !9} ; [ DW_TAG_arg_variable ] +!22 = metadata !{i32 524545, metadata !16, metadata !"extra", metadata !2, i32 20, metadata !19} ; [ DW_TAG_arg_variable ] +!23 = metadata !{i32 524545, metadata !16, metadata !"flags", metadata !2, i32 21, metadata !9} ; [ DW_TAG_arg_variable ] +!24 = metadata !{i32 23, i32 0, metadata !25, null} +!25 = metadata !{i32 524299, metadata !16, i32 22, i32 0} ; [ DW_TAG_lexical_block ] +!26 = metadata !{i32 24, i32 0, metadata !25, null} +!27 = metadata !{i32 26, i32 0, metadata !25, null} diff --git a/test/Transforms/DeadArgElim/deadexternal.ll b/test/Transforms/DeadArgElim/deadexternal.ll new file mode 100644 index 000000000000..7256b93af1a2 --- /dev/null +++ b/test/Transforms/DeadArgElim/deadexternal.ll @@ -0,0 +1,13 @@ +; RUN: opt -deadargelim -S %s | FileCheck %s +; XFAIL: * + +define void @test(i32) { + ret void +} + +define void @foo() { + call void @test(i32 0) + ret void +; CHECK: @foo +; CHECK: i32 undef +} diff --git a/test/Transforms/DeadStoreElimination/crash.ll b/test/Transforms/DeadStoreElimination/crash.ll index 6d8ba71b2094..5aac877a9ecf 100644 --- a/test/Transforms/DeadStoreElimination/crash.ll +++ b/test/Transforms/DeadStoreElimination/crash.ll @@ -54,4 +54,4 @@ dead: store i32 4, i32* %P2 store i32 4, i32* %Q2 br label %dead -}
\ No newline at end of file +} diff --git a/test/Transforms/GVN/2010-03-31-RedundantPHIs.ll b/test/Transforms/GVN/2010-03-31-RedundantPHIs.ll new file mode 100644 index 000000000000..066e3038b087 --- /dev/null +++ b/test/Transforms/GVN/2010-03-31-RedundantPHIs.ll @@ -0,0 +1,46 @@ +; RUN: opt < %s -gvn -enable-full-load-pre -S | FileCheck %s + +define i8* @cat(i8* %s1, ...) nounwind { +entry: + br i1 undef, label %bb, label %bb3 + +bb: ; preds = %entry + unreachable + +bb3: ; preds = %entry + store i8* undef, i8** undef, align 4 + br i1 undef, label %bb5, label %bb6 + +bb5: ; preds = %bb3 + unreachable + +bb6: ; preds = %bb3 + br label %bb12 + +bb8: ; preds = %bb12 + br i1 undef, label %bb9, label %bb10 + +bb9: ; preds = %bb8 + %0 = load i8** undef, align 4 ; <i8*> [#uses=0] + %1 = load i8** undef, align 4 ; <i8*> [#uses=0] + br label %bb11 + +bb10: ; preds = %bb8 + br label %bb11 + +bb11: ; preds = %bb10, %bb9 +; CHECK: bb11: +; CHECK: phi +; CHECK-NOT: phi + br label %bb12 + +bb12: ; preds = %bb11, %bb6 +; CHECK: bb12: +; CHECK: phi +; CHECK-NOT: phi + br i1 undef, label %bb8, label %bb13 + +bb13: ; preds = %bb12 +; CHECK: bb13: + ret i8* undef +} diff --git a/test/Transforms/GVN/invariant-simple.ll b/test/Transforms/GVN/invariant-simple.ll index 6de75f14350a..0a4182c410ae 100644 --- a/test/Transforms/GVN/invariant-simple.ll +++ b/test/Transforms/GVN/invariant-simple.ll @@ -33,4 +33,4 @@ entry: declare i32 @foo(i8*) nounwind declare i32 @bar(i8*) nounwind readonly declare {}* @llvm.invariant.start(i64 %S, i8* nocapture %P) readonly -declare void @llvm.invariant.end({}* %S, i64 %SS, i8* nocapture %P)
\ No newline at end of file +declare void @llvm.invariant.end({}* %S, i64 %SS, i8* nocapture %P) diff --git a/test/Transforms/GVN/lifetime-simple.ll b/test/Transforms/GVN/lifetime-simple.ll index 8139246dcf3c..48e5bc8bb63f 100644 --- a/test/Transforms/GVN/lifetime-simple.ll +++ b/test/Transforms/GVN/lifetime-simple.ll @@ -16,5 +16,5 @@ entry: ret i8 %1 } -declare {}* @llvm.lifetime.start(i64 %S, i8* nocapture %P) readonly -declare void @llvm.lifetime.end(i64 %S, i8* nocapture %P)
\ No newline at end of file +declare void @llvm.lifetime.start(i64 %S, i8* nocapture %P) readonly +declare void @llvm.lifetime.end(i64 %S, i8* nocapture %P) diff --git a/test/Transforms/GlobalOpt/crash.ll b/test/Transforms/GlobalOpt/crash.ll index a45cbe9c0f6f..701472c059a8 100644 --- a/test/Transforms/GlobalOpt/crash.ll +++ b/test/Transforms/GlobalOpt/crash.ll @@ -9,8 +9,34 @@ target triple = "i386-apple-darwin9.8" @_ZL6vTwist = global %struct.btSimdScalar zeroinitializer ; <%struct.btSimdScalar*> [#uses=1] @llvm.global_ctors = appending global [1 x %0] [%0 { i32 65535, void ()* @_GLOBAL__I__ZN21btConeTwistConstraintC2Ev }] ; <[12 x %0]*> [#uses=0] -define internal void @_GLOBAL__I__ZN21btConeTwistConstraintC2Ev() nounwind section "__TEXT,__StaticInit,regular,pure_instructions" { +define internal void @_GLOBAL__I__ZN21btConeTwistConstraintC2Ev() nounwind section "__TEXT,__StaticInit,regular,pure_instructions" { entry: store float 1.0, float* getelementptr inbounds (%struct.btSimdScalar* @_ZL6vTwist, i32 0, i32 0, i32 0, i32 3), align 4 ret void } + + +; PR6760 +%T = type { [5 x i32] } + +@switch_inf = internal global %T* null + +define void @test(i8* %arch_file, i32 %route_type) { +entry: + %A = sext i32 1 to i64 + %B = mul i64 %A, 20 + %C = call noalias i8* @malloc(i64 %B) nounwind + %D = bitcast i8* %C to %T* + store %T* %D, %T** @switch_inf, align 8 + unreachable + +bb.nph.i: + %scevgep.i539 = getelementptr i8* %C, i64 4 + unreachable + +xx: + %E = load %T** @switch_inf, align 8 + unreachable +} + +declare noalias i8* @malloc(i64) nounwind diff --git a/test/Transforms/GlobalOpt/malloc-promote-2.ll b/test/Transforms/GlobalOpt/malloc-promote-2.ll index f989b798b45f..6cb44812d2b6 100644 --- a/test/Transforms/GlobalOpt/malloc-promote-2.ll +++ b/test/Transforms/GlobalOpt/malloc-promote-2.ll @@ -1,24 +1,19 @@ -; RUN: opt < %s -globalopt -globaldce -S | not grep malloc +; RUN: opt < %s -globalopt -S | FileCheck %s target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" -@G = internal global i32* null ; <i32**> [#uses=3] +@G = internal global i32* null -define void @init() { - %malloccall = tail call i8* @malloc(i64 mul (i64 100, i64 4)) ; <i8*> [#uses=1] - %P = bitcast i8* %malloccall to i32* ; <i32*> [#uses=1] - store i32* %P, i32** @G - %GV = load i32** @G ; <i32*> [#uses=1] - %GVe = getelementptr i32* %GV, i32 40 ; <i32*> [#uses=1] - store i32 20, i32* %GVe - ret void +define void @t() { +; CHECK: @t() +; CHECK-NOT: call i8* @malloc +; CHECK-NEXT: ret void + %malloccall = tail call i8* @malloc(i64 mul (i64 100, i64 4)) + %P = bitcast i8* %malloccall to i32* + store i32* %P, i32** @G + %GV = load i32** @G + %GVe = getelementptr i32* %GV, i32 40 + store i32 20, i32* %GVe + ret void } declare noalias i8* @malloc(i64) - -define i32 @get() { - %GV = load i32** @G ; <i32*> [#uses=1] - %GVe = getelementptr i32* %GV, i32 40 ; <i32*> [#uses=1] - %V = load i32* %GVe ; <i32> [#uses=1] - ret i32 %V -} - diff --git a/test/Transforms/GlobalOpt/malloc-promote-3.ll b/test/Transforms/GlobalOpt/malloc-promote-3.ll deleted file mode 100644 index 57f937d8c929..000000000000 --- a/test/Transforms/GlobalOpt/malloc-promote-3.ll +++ /dev/null @@ -1,30 +0,0 @@ -; RUN: opt < %s -globalopt -globaldce -S | not grep malloc -target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" - -@G = internal global i32* null ; <i32**> [#uses=4] - -define void @init() { - %malloccall = tail call i8* @malloc(i64 mul (i64 100, i64 4)) ; <i8*> [#uses=1] - %P = bitcast i8* %malloccall to i32* ; <i32*> [#uses=1] - store i32* %P, i32** @G - %GV = load i32** @G ; <i32*> [#uses=1] - %GVe = getelementptr i32* %GV, i32 40 ; <i32*> [#uses=1] - store i32 20, i32* %GVe - ret void -} - -declare noalias i8* @malloc(i64) - -define i32 @get() { - %GV = load i32** @G ; <i32*> [#uses=1] - %GVe = getelementptr i32* %GV, i32 40 ; <i32*> [#uses=1] - %V = load i32* %GVe ; <i32> [#uses=1] - ret i32 %V -} - -define i1 @check() { - %GV = load i32** @G ; <i32*> [#uses=1] - %V = icmp eq i32* %GV, null ; <i1> [#uses=1] - ret i1 %V -} - diff --git a/test/Transforms/GlobalOpt/metadata.ll b/test/Transforms/GlobalOpt/metadata.ll new file mode 100644 index 000000000000..a09ba72439fc --- /dev/null +++ b/test/Transforms/GlobalOpt/metadata.ll @@ -0,0 +1,19 @@ +; RUN: opt -S -globalopt < %s | FileCheck %s + +; PR6112 - When globalopt does RAUW(@G, %G), the metadata reference should drop +; to null. +@G = internal global i8** null + +define i32 @main(i32 %argc, i8** %argv) { +; CHECK: @main +; CHECK: %G = alloca + store i8** %argv, i8*** @G + ret i32 0 +} + +!named = !{!0} + +; CHECK: !0 = metadata !{null} +!0 = metadata !{i8*** @G} + + diff --git a/test/Transforms/IndVarSimplify/casted-argument.ll b/test/Transforms/IndVarSimplify/casted-argument.ll index dfefe1dc5bbe..a5e002b4578f 100644 --- a/test/Transforms/IndVarSimplify/casted-argument.ll +++ b/test/Transforms/IndVarSimplify/casted-argument.ll @@ -47,4 +47,4 @@ if.end54: ; preds = %if.end54, %if.else declare void @bcopy(i8* nocapture) nounwind -declare void @bcopy_4038(i8*, i32) nounwind +declare void @bcopy_4038(i8*, i8*, i32) nounwind diff --git a/test/Transforms/IndVarSimplify/crash.ll b/test/Transforms/IndVarSimplify/crash.ll index 14f79fefb180..ab438334c660 100644 --- a/test/Transforms/IndVarSimplify/crash.ll +++ b/test/Transforms/IndVarSimplify/crash.ll @@ -16,4 +16,4 @@ define void @t2(i1* %P) nounwind { ; <label>:6 ; preds = %1 ret void -}
\ No newline at end of file +} diff --git a/test/Transforms/IndVarSimplify/eliminate-comparison.ll b/test/Transforms/IndVarSimplify/eliminate-comparison.ll new file mode 100644 index 000000000000..953bbdff5c62 --- /dev/null +++ b/test/Transforms/IndVarSimplify/eliminate-comparison.ll @@ -0,0 +1,108 @@ +; RUN: opt -indvars -S < %s | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" + +@X = external global [0 x double] + +; Indvars should be able to simplify simple comparisons involving +; induction variables. + +; CHECK: @foo +; CHECK: %cond = and i1 %tobool.not, true + +define void @foo(i64 %n, i32* nocapture %p) nounwind { +entry: + %cmp9 = icmp sgt i64 %n, 0 + br i1 %cmp9, label %pre, label %return + +pre: + %t3 = load i32* %p + %tobool.not = icmp ne i32 %t3, 0 + br label %loop + +loop: + %i = phi i64 [ 0, %pre ], [ %inc, %for.inc ] + %cmp6 = icmp slt i64 %i, %n + %cond = and i1 %tobool.not, %cmp6 + br i1 %cond, label %if.then, label %for.inc + +if.then: + %arrayidx = getelementptr [0 x double]* @X, i64 0, i64 %i + store double 3.200000e+00, double* %arrayidx + br label %for.inc + +for.inc: + %inc = add nsw i64 %i, 1 + %exitcond = icmp sge i64 %inc, %n + br i1 %exitcond, label %return, label %loop + +return: + ret void +} + +; Don't eliminate an icmp that's contributing to the loop exit test though. + +; CHECK: @_ZNK4llvm5APInt3ultERKS0_ +; CHECK: %tmp99 = icmp sgt i32 %i, -1 + +define i32 @_ZNK4llvm5APInt3ultERKS0_(i32 %tmp2.i1, i64** %tmp65, i64** %tmp73, i64** %tmp82, i64** %tmp90) { +entry: + br label %bb18 + +bb13: + %tmp66 = load i64** %tmp65, align 4 + %tmp68 = getelementptr inbounds i64* %tmp66, i32 %i + %tmp69 = load i64* %tmp68, align 4 + %tmp74 = load i64** %tmp73, align 4 + %tmp76 = getelementptr inbounds i64* %tmp74, i32 %i + %tmp77 = load i64* %tmp76, align 4 + %tmp78 = icmp ugt i64 %tmp69, %tmp77 + br i1 %tmp78, label %bb20.loopexit, label %bb15 + +bb15: + %tmp83 = load i64** %tmp82, align 4 + %tmp85 = getelementptr inbounds i64* %tmp83, i32 %i + %tmp86 = load i64* %tmp85, align 4 + %tmp91 = load i64** %tmp90, align 4 + %tmp93 = getelementptr inbounds i64* %tmp91, i32 %i + %tmp94 = load i64* %tmp93, align 4 + %tmp95 = icmp ult i64 %tmp86, %tmp94 + br i1 %tmp95, label %bb20.loopexit, label %bb17 + +bb17: + %tmp97 = add nsw i32 %i, -1 + br label %bb18 + +bb18: + %i = phi i32 [ %tmp2.i1, %entry ], [ %tmp97, %bb17 ] + %tmp99 = icmp sgt i32 %i, -1 + br i1 %tmp99, label %bb13, label %bb20.loopexit + +bb20.loopexit: + %tmp.0.ph = phi i32 [ 0, %bb18 ], [ 1, %bb15 ], [ 0, %bb13 ] + ret i32 %tmp.0.ph +} + +; Indvars should eliminate the icmp here. + +; CHECK: @func_10 +; CHECK-NOT: icmp +; CHECK: ret void + +define void @func_10() nounwind { +entry: + br label %loop + +loop: + %i = phi i32 [ %i.next, %loop ], [ 0, %entry ] + %t0 = icmp slt i32 %i, 0 + %t1 = zext i1 %t0 to i32 + %t2 = add i32 %t1, %i + %u3 = zext i32 %t2 to i64 + store i64 %u3, i64* null + %i.next = add i32 %i, 1 + br i1 undef, label %loop, label %return + +return: + ret void +} diff --git a/test/Transforms/IndVarSimplify/eliminate-max.ll b/test/Transforms/IndVarSimplify/eliminate-max.ll new file mode 100644 index 000000000000..c25bd0e35418 --- /dev/null +++ b/test/Transforms/IndVarSimplify/eliminate-max.ll @@ -0,0 +1,52 @@ +; RUN: opt < %s -S -indvars | grep {= icmp} | count 3 +; PR4914.ll + +; Indvars should be able to do range analysis and eliminate icmps. +; There are two here which cannot be eliminated. +; There's one that icmp which can be eliminated and which indvars currently +; cannot eliminate, because it requires analyzing more than just the +; range of the induction variable. + +@0 = private constant [4 x i8] c"%d\0A\00", align 1 ; <[4 x i8]*> [#uses=1] + +define i32 @main() nounwind { +bb: + br label %bb1 + +bb1: ; preds = %bb14, %bb + %t = phi i32 [ 0, %bb ], [ %t19, %bb14 ] ; <i32> [#uses=5] + %t2 = phi i32 [ 0, %bb ], [ %t18, %bb14 ] ; <i32> [#uses=1] + %t3 = icmp slt i32 %t, 0 ; <i1> [#uses=1] + br i1 %t3, label %bb7, label %bb4 + +bb4: ; preds = %bb1 + %t5 = icmp sgt i32 %t, 255 ; <i1> [#uses=1] + %t6 = select i1 %t5, i32 255, i32 %t ; <i32> [#uses=1] + br label %bb7 + +bb7: ; preds = %bb4, %bb1 + %t8 = phi i32 [ %t6, %bb4 ], [ 0, %bb1 ] ; <i32> [#uses=1] + %t9 = sub i32 0, %t ; <i32> [#uses=3] + %t10 = icmp slt i32 %t9, 0 ; <i1> [#uses=1] + br i1 %t10, label %bb14, label %bb11 + +bb11: ; preds = %bb7 + %t12 = icmp sgt i32 %t9, 255 ; <i1> [#uses=1] + %t13 = select i1 %t12, i32 255, i32 %t9 ; <i32> [#uses=1] + br label %bb14 + +bb14: ; preds = %bb11, %bb7 + %t15 = phi i32 [ %t13, %bb11 ], [ 0, %bb7 ] ; <i32> [#uses=1] + %t16 = add nsw i32 %t2, 255 ; <i32> [#uses=1] + %t17 = add nsw i32 %t16, %t8 ; <i32> [#uses=1] + %t18 = add nsw i32 %t17, %t15 ; <i32> [#uses=2] + %t19 = add nsw i32 %t, 1 ; <i32> [#uses=2] + %t20 = icmp slt i32 %t19, 1000000000 ; <i1> [#uses=1] + br i1 %t20, label %bb1, label %bb21 + +bb21: ; preds = %bb14 + %t22 = call i32 (i8*, ...)* @printf(i8* noalias getelementptr inbounds ([4 x i8]* @0, i32 0, i32 0), i32 %t18) nounwind + ret i32 0 +} + +declare i32 @printf(i8* noalias nocapture, ...) nounwind diff --git a/test/Transforms/IndVarSimplify/eliminate-rem.ll b/test/Transforms/IndVarSimplify/eliminate-rem.ll new file mode 100644 index 000000000000..f756389398fb --- /dev/null +++ b/test/Transforms/IndVarSimplify/eliminate-rem.ll @@ -0,0 +1,121 @@ +; RUN: opt -indvars -S < %s | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" + +; Indvars should be able to eliminate this srem. +; CHECK: @simple +; CHECK-NOT: rem +; CHECK: ret + +define void @simple(i64 %arg, double* %arg3) nounwind { +bb: + %t = icmp slt i64 0, %arg ; <i1> [#uses=1] + br i1 %t, label %bb4, label %bb12 + +bb4: ; preds = %bb + br label %bb5 + +bb5: ; preds = %bb4, %bb5 + %t6 = phi i64 [ %t9, %bb5 ], [ 0, %bb4 ] ; <i64> [#uses=2] + %t7 = srem i64 %t6, %arg ; <i64> [#uses=1] + %t8 = getelementptr inbounds double* %arg3, i64 %t7 ; <double*> [#uses=1] + store double 0.000000e+00, double* %t8 + %t9 = add nsw i64 %t6, 1 ; <i64> [#uses=2] + %t10 = icmp slt i64 %t9, %arg ; <i1> [#uses=1] + br i1 %t10, label %bb5, label %bb11 + +bb11: ; preds = %bb5 + br label %bb12 + +bb12: ; preds = %bb11, %bb + ret void +} + +; Indvars should be able to eliminate the (i+1)%n. +; CHECK: @f +; CHECK-NOT: rem +; CHECK: rem +; CHECK-NOT: rem +; CHECK: ret + +define i32 @f(i64* %arg, i64 %arg1, i64 %arg2, i64 %arg3) nounwind { +bb: + %t = icmp sgt i64 %arg1, 0 ; <i1> [#uses=1] + br i1 %t, label %bb4, label %bb54 + +bb4: ; preds = %bb + br label %bb5 + +bb5: ; preds = %bb49, %bb4 + %t6 = phi i64 [ %t51, %bb49 ], [ 0, %bb4 ] ; <i64> [#uses=4] + %t7 = phi i32 [ %t50, %bb49 ], [ 0, %bb4 ] ; <i32> [#uses=2] + %t8 = add nsw i64 %t6, %arg1 ; <i64> [#uses=1] + %t9 = add nsw i64 %t8, -2 ; <i64> [#uses=1] + %t10 = srem i64 %t9, %arg1 ; <i64> [#uses=1] + %t11 = add nsw i64 %t10, 1 ; <i64> [#uses=1] + %t12 = add nsw i64 %t6, 1 ; <i64> [#uses=1] + %t13 = srem i64 %t12, %arg1 ; <i64> [#uses=1] + %t14 = icmp sgt i64 %arg1, 0 ; <i1> [#uses=1] + br i1 %t14, label %bb15, label %bb49 + +bb15: ; preds = %bb5 + br label %bb16 + +bb16: ; preds = %bb44, %bb15 + %t17 = phi i64 [ %t46, %bb44 ], [ 0, %bb15 ] ; <i64> [#uses=1] + %t18 = phi i32 [ %t45, %bb44 ], [ %t7, %bb15 ] ; <i32> [#uses=2] + %t19 = icmp sgt i64 %arg1, 0 ; <i1> [#uses=1] + br i1 %t19, label %bb20, label %bb44 + +bb20: ; preds = %bb16 + br label %bb21 + +bb21: ; preds = %bb21, %bb20 + %t22 = phi i64 [ %t41, %bb21 ], [ 0, %bb20 ] ; <i64> [#uses=4] + %t23 = phi i32 [ %t40, %bb21 ], [ %t18, %bb20 ] ; <i32> [#uses=1] + %t24 = mul i64 %t6, %arg1 ; <i64> [#uses=1] + %t25 = mul i64 %t13, %arg1 ; <i64> [#uses=1] + %t26 = add nsw i64 %t24, %t22 ; <i64> [#uses=1] + %t27 = mul i64 %t11, %arg1 ; <i64> [#uses=1] + %t28 = add nsw i64 %t25, %t22 ; <i64> [#uses=1] + %t29 = getelementptr inbounds i64* %arg, i64 %t26 ; <i64*> [#uses=1] + %t30 = add nsw i64 %t27, %t22 ; <i64> [#uses=1] + %t31 = getelementptr inbounds i64* %arg, i64 %t28 ; <i64*> [#uses=1] + %t32 = zext i32 %t23 to i64 ; <i64> [#uses=1] + %t33 = load i64* %t29 ; <i64> [#uses=1] + %t34 = getelementptr inbounds i64* %arg, i64 %t30 ; <i64*> [#uses=1] + %t35 = load i64* %t31 ; <i64> [#uses=1] + %t36 = add nsw i64 %t32, %t33 ; <i64> [#uses=1] + %t37 = add nsw i64 %t36, %t35 ; <i64> [#uses=1] + %t38 = load i64* %t34 ; <i64> [#uses=1] + %t39 = add nsw i64 %t37, %t38 ; <i64> [#uses=1] + %t40 = trunc i64 %t39 to i32 ; <i32> [#uses=2] + %t41 = add nsw i64 %t22, 1 ; <i64> [#uses=2] + %t42 = icmp slt i64 %t41, %arg1 ; <i1> [#uses=1] + br i1 %t42, label %bb21, label %bb43 + +bb43: ; preds = %bb21 + br label %bb44 + +bb44: ; preds = %bb43, %bb16 + %t45 = phi i32 [ %t18, %bb16 ], [ %t40, %bb43 ] ; <i32> [#uses=2] + %t46 = add nsw i64 %t17, 1 ; <i64> [#uses=2] + %t47 = icmp slt i64 %t46, %arg1 ; <i1> [#uses=1] + br i1 %t47, label %bb16, label %bb48 + +bb48: ; preds = %bb44 + br label %bb49 + +bb49: ; preds = %bb48, %bb5 + %t50 = phi i32 [ %t7, %bb5 ], [ %t45, %bb48 ] ; <i32> [#uses=2] + %t51 = add nsw i64 %t6, 1 ; <i64> [#uses=2] + %t52 = icmp slt i64 %t51, %arg1 ; <i1> [#uses=1] + br i1 %t52, label %bb5, label %bb53 + +bb53: ; preds = %bb49 + br label %bb54 + +bb54: ; preds = %bb53, %bb + %t55 = phi i32 [ 0, %bb ], [ %t50, %bb53 ] ; <i32> [#uses=1] + ret i32 %t55 +} diff --git a/test/Transforms/IndVarSimplify/udiv.ll b/test/Transforms/IndVarSimplify/udiv.ll new file mode 100644 index 000000000000..8260093d1c37 --- /dev/null +++ b/test/Transforms/IndVarSimplify/udiv.ll @@ -0,0 +1,162 @@ +; RUN: opt -indvars -S < %s | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" + +@main.flags = internal global [8193 x i8] zeroinitializer, align 1 ; <[8193 x i8]*> [#uses=5] +@.str = private constant [11 x i8] c"Count: %d\0A\00" ; <[11 x i8]*> [#uses=1] + +; Indvars shouldn't emit a udiv here, because there's no udiv in the +; original code. This comes from SingleSource/Benchmarks/Shootout/sieve.c. + +; CHECK: @main +; CHECK-NOT: div + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind { +entry: + %cmp = icmp eq i32 %argc, 2 ; <i1> [#uses=1] + br i1 %cmp, label %cond.true, label %while.cond.preheader + +cond.true: ; preds = %entry + %arrayidx = getelementptr inbounds i8** %argv, i64 1 ; <i8**> [#uses=1] + %tmp2 = load i8** %arrayidx ; <i8*> [#uses=1] + %call = tail call i32 @atoi(i8* %tmp2) nounwind readonly ; <i32> [#uses=1] + br label %while.cond.preheader + +while.cond.preheader: ; preds = %entry, %cond.true + %NUM.0.ph = phi i32 [ %call, %cond.true ], [ 170000, %entry ] ; <i32> [#uses=2] + %tobool18 = icmp eq i32 %NUM.0.ph, 0 ; <i1> [#uses=1] + br i1 %tobool18, label %while.end, label %bb.nph30 + +while.cond.loopexit: ; preds = %for.cond12.while.cond.loopexit_crit_edge, %for.cond12.loopexit + %count.2.lcssa = phi i32 [ %count.1.lcssa, %for.cond12.while.cond.loopexit_crit_edge ], [ 0, %for.cond12.loopexit ] ; <i32> [#uses=1] + br label %while.cond + +while.cond: ; preds = %while.cond.loopexit + %tobool = icmp eq i32 %dec19, 0 ; <i1> [#uses=1] + br i1 %tobool, label %while.cond.while.end_crit_edge, label %for.cond.preheader + +while.cond.while.end_crit_edge: ; preds = %while.cond + %count.2.lcssa.lcssa = phi i32 [ %count.2.lcssa, %while.cond ] ; <i32> [#uses=1] + br label %while.end + +bb.nph30: ; preds = %while.cond.preheader + br label %for.cond.preheader + +for.cond.preheader: ; preds = %bb.nph30, %while.cond + %dec19.in = phi i32 [ %NUM.0.ph, %bb.nph30 ], [ %dec19, %while.cond ] ; <i32> [#uses=1] + %dec19 = add i32 %dec19.in, -1 ; <i32> [#uses=2] + br i1 true, label %bb.nph, label %for.cond12.loopexit + +for.cond: ; preds = %for.body + %cmp8 = icmp slt i64 %inc, 8193 ; <i1> [#uses=1] + br i1 %cmp8, label %for.body, label %for.cond.for.cond12.loopexit_crit_edge + +for.cond.for.cond12.loopexit_crit_edge: ; preds = %for.cond + br label %for.cond12.loopexit + +bb.nph: ; preds = %for.cond.preheader + br label %for.body + +for.body: ; preds = %bb.nph, %for.cond + %i.02 = phi i64 [ 2, %bb.nph ], [ %inc, %for.cond ] ; <i64> [#uses=2] + %arrayidx10 = getelementptr inbounds [8193 x i8]* @main.flags, i64 0, i64 %i.02 ; <i8*> [#uses=1] + store i8 1, i8* %arrayidx10 + %inc = add nsw i64 %i.02, 1 ; <i64> [#uses=2] + br label %for.cond + +for.cond12.loopexit: ; preds = %for.cond.for.cond12.loopexit_crit_edge, %for.cond.preheader + br i1 true, label %bb.nph16, label %while.cond.loopexit + +for.cond12: ; preds = %for.inc35 + %cmp14 = icmp slt i64 %inc37, 8193 ; <i1> [#uses=1] + br i1 %cmp14, label %for.body15, label %for.cond12.while.cond.loopexit_crit_edge + +for.cond12.while.cond.loopexit_crit_edge: ; preds = %for.cond12 + %count.1.lcssa = phi i32 [ %count.1, %for.cond12 ] ; <i32> [#uses=1] + br label %while.cond.loopexit + +bb.nph16: ; preds = %for.cond12.loopexit + br label %for.body15 + +for.body15: ; preds = %bb.nph16, %for.cond12 + %count.212 = phi i32 [ 0, %bb.nph16 ], [ %count.1, %for.cond12 ] ; <i32> [#uses=2] + %i.17 = phi i64 [ 2, %bb.nph16 ], [ %inc37, %for.cond12 ] ; <i64> [#uses=4] + %arrayidx17 = getelementptr inbounds [8193 x i8]* @main.flags, i64 0, i64 %i.17 ; <i8*> [#uses=1] + %tmp18 = load i8* %arrayidx17 ; <i8> [#uses=1] + %tobool19 = icmp eq i8 %tmp18, 0 ; <i1> [#uses=1] + br i1 %tobool19, label %for.inc35, label %if.then + +if.then: ; preds = %for.body15 + %add = shl i64 %i.17, 1 ; <i64> [#uses=2] + %cmp243 = icmp slt i64 %add, 8193 ; <i1> [#uses=1] + br i1 %cmp243, label %bb.nph5, label %for.end32 + +for.cond22: ; preds = %for.body25 + %cmp24 = icmp slt i64 %add31, 8193 ; <i1> [#uses=1] + br i1 %cmp24, label %for.body25, label %for.cond22.for.end32_crit_edge + +for.cond22.for.end32_crit_edge: ; preds = %for.cond22 + br label %for.end32 + +bb.nph5: ; preds = %if.then + br label %for.body25 + +for.body25: ; preds = %bb.nph5, %for.cond22 + %k.04 = phi i64 [ %add, %bb.nph5 ], [ %add31, %for.cond22 ] ; <i64> [#uses=2] + %arrayidx27 = getelementptr inbounds [8193 x i8]* @main.flags, i64 0, i64 %k.04 ; <i8*> [#uses=1] + store i8 0, i8* %arrayidx27 + %add31 = add nsw i64 %k.04, %i.17 ; <i64> [#uses=2] + br label %for.cond22 + +for.end32: ; preds = %for.cond22.for.end32_crit_edge, %if.then + %inc34 = add nsw i32 %count.212, 1 ; <i32> [#uses=1] + br label %for.inc35 + +for.inc35: ; preds = %for.body15, %for.end32 + %count.1 = phi i32 [ %inc34, %for.end32 ], [ %count.212, %for.body15 ] ; <i32> [#uses=2] + %inc37 = add nsw i64 %i.17, 1 ; <i64> [#uses=2] + br label %for.cond12 + +while.end: ; preds = %while.cond.while.end_crit_edge, %while.cond.preheader + %count.0.lcssa = phi i32 [ %count.2.lcssa.lcssa, %while.cond.while.end_crit_edge ], [ 0, %while.cond.preheader ] ; <i32> [#uses=1] + %call40 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i64 0, i64 0), i32 %count.0.lcssa) nounwind ; <i32> [#uses=0] + ret i32 0 +} + +declare i32 @atoi(i8* nocapture) nounwind readonly + +declare i32 @printf(i8* nocapture, ...) nounwind + +; IndVars shouldn't be afraid to emit a udiv here, since there's a udiv in +; the original code. + +; CHECK: @foo +; CHECK: for.body.preheader: +; CHECK-NEXT: udiv + +define void @foo(double* %p, i64 %n) nounwind { +entry: + %div0 = udiv i64 %n, 7 ; <i64> [#uses=1] + %div1 = add i64 %div0, 1 + %cmp2 = icmp ult i64 0, %div1 ; <i1> [#uses=1] + br i1 %cmp2, label %for.body.preheader, label %for.end + +for.body.preheader: ; preds = %entry + br label %for.body + +for.body: ; preds = %for.body.preheader, %for.body + %i.03 = phi i64 [ %inc, %for.body ], [ 0, %for.body.preheader ] ; <i64> [#uses=2] + %arrayidx = getelementptr inbounds double* %p, i64 %i.03 ; <double*> [#uses=1] + store double 0.000000e+00, double* %arrayidx + %inc = add i64 %i.03, 1 ; <i64> [#uses=2] + %divx = udiv i64 %n, 7 ; <i64> [#uses=1] + %div = add i64 %divx, 1 + %cmp = icmp ult i64 %inc, %div ; <i1> [#uses=1] + br i1 %cmp, label %for.body, label %for.end.loopexit + +for.end.loopexit: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry + ret void +} diff --git a/test/Transforms/Inline/2009-01-12-RecursiveInline.ll b/test/Transforms/Inline/2009-01-12-RecursiveInline.ll deleted file mode 100644 index 1a3325a68b61..000000000000 --- a/test/Transforms/Inline/2009-01-12-RecursiveInline.ll +++ /dev/null @@ -1,92 +0,0 @@ -; RUN: opt < %s -inline -S | grep {call.*fib} | count 4 -; First call to fib from fib is inlined, producing 2 instead of 1, total 3. -; Second call to fib from fib is not inlined because new body of fib exceeds -; inlining limit of 200. Plus call in main = 4 total. - -; ModuleID = '<stdin>' -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" -target triple = "i386-apple-darwin9.6" -@"\01LC" = internal constant [5 x i8] c"%ld\0A\00" ; <[5 x i8]*> [#uses=1] - -define i32 @fib(i32 %n) nounwind { -entry: - %n_addr = alloca i32 ; <i32*> [#uses=4] - %retval = alloca i32 ; <i32*> [#uses=2] - %0 = alloca i32 ; <i32*> [#uses=3] - %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] - store i32 %n, i32* %n_addr - %1 = load i32* %n_addr, align 4 ; <i32> [#uses=1] - %2 = icmp ule i32 %1, 1 ; <i1> [#uses=1] - br i1 %2, label %bb, label %bb1 - -bb: ; preds = %entry - store i32 1, i32* %0, align 4 - br label %bb2 - -bb1: ; preds = %entry - %3 = load i32* %n_addr, align 4 ; <i32> [#uses=1] - %4 = sub i32 %3, 2 ; <i32> [#uses=1] - %5 = call i32 @fib(i32 %4) nounwind ; <i32> [#uses=1] - %6 = load i32* %n_addr, align 4 ; <i32> [#uses=1] - %7 = sub i32 %6, 1 ; <i32> [#uses=1] - %8 = call i32 @fib(i32 %7) nounwind ; <i32> [#uses=1] - %9 = add i32 %5, %8 ; <i32> [#uses=1] - store i32 %9, i32* %0, align 4 - br label %bb2 - -bb2: ; preds = %bb1, %bb - %10 = load i32* %0, align 4 ; <i32> [#uses=1] - store i32 %10, i32* %retval, align 4 - br label %return - -return: ; preds = %bb2 - %retval3 = load i32* %retval ; <i32> [#uses=1] - ret i32 %retval3 -} - -define i32 @main(i32 %argc, i8** %argv) nounwind { -entry: - %argc_addr = alloca i32 ; <i32*> [#uses=2] - %argv_addr = alloca i8** ; <i8***> [#uses=2] - %retval = alloca i32 ; <i32*> [#uses=2] - %N = alloca i32 ; <i32*> [#uses=2] - %0 = alloca i32 ; <i32*> [#uses=2] - %iftmp.0 = alloca i32 ; <i32*> [#uses=3] - %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] - store i32 %argc, i32* %argc_addr - store i8** %argv, i8*** %argv_addr - %1 = load i32* %argc_addr, align 4 ; <i32> [#uses=1] - %2 = icmp eq i32 %1, 2 ; <i1> [#uses=1] - br i1 %2, label %bb, label %bb1 - -bb: ; preds = %entry - %3 = load i8*** %argv_addr, align 4 ; <i8**> [#uses=1] - %4 = getelementptr i8** %3, i32 1 ; <i8**> [#uses=1] - %5 = load i8** %4, align 4 ; <i8*> [#uses=1] - %6 = call i32 @atoi(i8* %5) nounwind ; <i32> [#uses=1] - store i32 %6, i32* %iftmp.0, align 4 - br label %bb2 - -bb1: ; preds = %entry - store i32 43, i32* %iftmp.0, align 4 - br label %bb2 - -bb2: ; preds = %bb1, %bb - %7 = load i32* %iftmp.0, align 4 ; <i32> [#uses=1] - store i32 %7, i32* %N, align 4 - %8 = load i32* %N, align 4 ; <i32> [#uses=1] - %9 = call i32 @fib(i32 %8) nounwind ; <i32> [#uses=1] - %10 = call i32 (i8*, ...)* @printf(i8* getelementptr ([5 x i8]* @"\01LC", i32 0, i32 0), i32 %9) nounwind ; <i32> [#uses=0] - store i32 0, i32* %0, align 4 - %11 = load i32* %0, align 4 ; <i32> [#uses=1] - store i32 %11, i32* %retval, align 4 - br label %return - -return: ; preds = %bb2 - %retval3 = load i32* %retval ; <i32> [#uses=1] - ret i32 %retval3 -} - -declare i32 @atoi(i8*) - -declare i32 @printf(i8*, ...) nounwind diff --git a/test/Transforms/Inline/crash.ll b/test/Transforms/Inline/crash.ll index f34b44c2aa08..1df4d6063e84 100644 --- a/test/Transforms/Inline/crash.ll +++ b/test/Transforms/Inline/crash.ll @@ -86,3 +86,34 @@ bb260: lpad: unwind } + + + +;; This exposed a crash handling devirtualized calls. +define void @f1(void ()* %f) ssp { +entry: + call void %f() + ret void +} + +define void @f4(i32 %size) ssp { +entry: + invoke void @f1(void ()* @f3) + to label %invcont3 unwind label %lpad18 + +invcont3: ; preds = %bb1 + ret void + +lpad18: ; preds = %invcont3, %bb1 + unreachable +} + +define void @f3() ssp { +entry: + unreachable +} + +declare void @f5() ssp + + + diff --git a/test/Transforms/Inline/crash2.ll b/test/Transforms/Inline/crash2.ll new file mode 100644 index 000000000000..cb1f44d5cca7 --- /dev/null +++ b/test/Transforms/Inline/crash2.ll @@ -0,0 +1,29 @@ +; RUN: opt -inline -scalarrepl -max-cg-scc-iterations=1 %s -disable-output +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.3" + +declare i8* @f1(i8*) ssp align 2 + +define linkonce_odr void @f2(i8* %t) inlinehint ssp { +entry: + unreachable +} + +define linkonce_odr void @f3(void (i8*)* %__f) ssp { +entry: + %__f_addr = alloca void (i8*)*, align 8 + store void (i8*)* %__f, void (i8*)** %__f_addr + + %0 = load void (i8*)** %__f_addr, align 8 + call void %0(i8* undef) + call i8* @f1(i8* undef) ssp + unreachable +} + +define linkonce_odr void @f4(i8* %this) ssp align 2 { +entry: + %0 = alloca i32 + call void @f3(void (i8*)* @f2) ssp + ret void +} + diff --git a/test/Transforms/Inline/devirtualize-2.ll b/test/Transforms/Inline/devirtualize-2.ll new file mode 100644 index 000000000000..02ff7679148d --- /dev/null +++ b/test/Transforms/Inline/devirtualize-2.ll @@ -0,0 +1,44 @@ +; RUN: opt < %s -inline -S | FileCheck %s +; PR4834 + +define i32 @test1() { + %funcall1_ = call fastcc i32 ()* ()* @f1() + %executecommandptr1_ = call i32 %funcall1_() + ret i32 %executecommandptr1_ +} + +define internal fastcc i32 ()* @f1() nounwind readnone { + ret i32 ()* @f2 +} + +define internal i32 @f2() nounwind readnone { + ret i32 1 +} + +; CHECK: @test1() +; CHECK-NEXT: ret i32 1 + + + + + +declare i8* @f1a(i8*) ssp align 2 + +define internal i32 @f2a(i8* %t) inlinehint ssp { +entry: + ret i32 41 +} + +define internal i32 @f3a(i32 (i8*)* %__f) ssp { +entry: + %A = call i32 %__f(i8* undef) + ret i32 %A +} + +define i32 @test2(i8* %this) ssp align 2 { + %X = call i32 @f3a(i32 (i8*)* @f2a) ssp + ret i32 %X +} + +; CHECK: @test2 +; CHECK-NEXT: ret i32 41 diff --git a/test/Transforms/Inline/devirtualize-3.ll b/test/Transforms/Inline/devirtualize-3.ll new file mode 100644 index 000000000000..0a50786498df --- /dev/null +++ b/test/Transforms/Inline/devirtualize-3.ll @@ -0,0 +1,79 @@ +; RUN: opt -inline -S -scalarrepl -gvn -instcombine %s | FileCheck %s +; PR5009 + +; CHECK: define i32 @main() +; CHECK-NEXT: entry: +; CHECK-NEXT: call void @exit(i32 38) + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +%struct.cont_t = type { void (i8*, i32)*, i8* } +%struct.foo_sf_t = type { %struct.cont_t*, i32 } + +define i32 @main() nounwind ssp { +entry: + %cont = alloca %struct.cont_t, align 8 ; <%struct.cont_t*> [#uses=4] + %tmp = getelementptr inbounds %struct.cont_t* %cont, i32 0, i32 0 ; <void (i8*, i32)**> [#uses=1] + %tmp1 = getelementptr inbounds %struct.cont_t* %cont, i32 0, i32 0 ; <void (i8*, i32)**> [#uses=2] + store void (i8*, i32)* bitcast (void (%struct.cont_t*, i32)* @quit to void (i8*, i32)*), void (i8*, i32)** %tmp1 + %tmp2 = load void (i8*, i32)** %tmp1 ; <void (i8*, i32)*> [#uses=1] + store void (i8*, i32)* %tmp2, void (i8*, i32)** %tmp + %tmp3 = getelementptr inbounds %struct.cont_t* %cont, i32 0, i32 1 ; <i8**> [#uses=1] + store i8* null, i8** %tmp3 + call void @foo(%struct.cont_t* %cont) + ret i32 0 +} + +define internal void @quit(%struct.cont_t* %cont, i32 %rcode) nounwind ssp { +entry: + call void @exit(i32 %rcode) noreturn + unreachable +} + +define internal void @foo(%struct.cont_t* %c) nounwind ssp { +entry: + %sf = alloca %struct.foo_sf_t, align 8 ; <%struct.foo_sf_t*> [#uses=3] + %next = alloca %struct.cont_t, align 8 ; <%struct.cont_t*> [#uses=3] + %tmp = getelementptr inbounds %struct.foo_sf_t* %sf, i32 0, i32 0 ; <%struct.cont_t**> [#uses=1] + store %struct.cont_t* %c, %struct.cont_t** %tmp + %tmp2 = getelementptr inbounds %struct.foo_sf_t* %sf, i32 0, i32 1 ; <i32*> [#uses=1] + store i32 2, i32* %tmp2 + %tmp4 = getelementptr inbounds %struct.cont_t* %next, i32 0, i32 0 ; <void (i8*, i32)**> [#uses=1] + store void (i8*, i32)* bitcast (void (%struct.foo_sf_t*, i32)* @foo2 to void (i8*, i32)*), void (i8*, i32)** %tmp4 + %tmp5 = getelementptr inbounds %struct.cont_t* %next, i32 0, i32 1 ; <i8**> [#uses=1] + %conv = bitcast %struct.foo_sf_t* %sf to i8* ; <i8*> [#uses=1] + store i8* %conv, i8** %tmp5 + call void @bar(%struct.cont_t* %next, i32 14) + ret void +} + +define internal void @foo2(%struct.foo_sf_t* %sf, i32 %y) nounwind ssp { +entry: + %tmp1 = getelementptr inbounds %struct.foo_sf_t* %sf, i32 0, i32 0 ; <%struct.cont_t**> [#uses=1] + %tmp2 = load %struct.cont_t** %tmp1 ; <%struct.cont_t*> [#uses=1] + %tmp3 = getelementptr inbounds %struct.cont_t* %tmp2, i32 0, i32 0 ; <void (i8*, i32)**> [#uses=1] + %tmp4 = load void (i8*, i32)** %tmp3 ; <void (i8*, i32)*> [#uses=1] + %tmp6 = getelementptr inbounds %struct.foo_sf_t* %sf, i32 0, i32 0 ; <%struct.cont_t**> [#uses=1] + %tmp7 = load %struct.cont_t** %tmp6 ; <%struct.cont_t*> [#uses=1] + %conv = bitcast %struct.cont_t* %tmp7 to i8* ; <i8*> [#uses=1] + %tmp9 = getelementptr inbounds %struct.foo_sf_t* %sf, i32 0, i32 1 ; <i32*> [#uses=1] + %tmp10 = load i32* %tmp9 ; <i32> [#uses=1] + %mul = mul i32 %tmp10, %y ; <i32> [#uses=1] + call void %tmp4(i8* %conv, i32 %mul) + ret void +} + +define internal void @bar(%struct.cont_t* %c, i32 %y) nounwind ssp { +entry: + %tmp1 = getelementptr inbounds %struct.cont_t* %c, i32 0, i32 0 ; <void (i8*, i32)**> [#uses=1] + %tmp2 = load void (i8*, i32)** %tmp1 ; <void (i8*, i32)*> [#uses=1] + %tmp4 = getelementptr inbounds %struct.cont_t* %c, i32 0, i32 1 ; <i8**> [#uses=1] + %tmp5 = load i8** %tmp4 ; <i8*> [#uses=1] + %add = add nsw i32 %y, 5 ; <i32> [#uses=1] + call void %tmp2(i8* %tmp5, i32 %add) + ret void +} + +declare void @exit(i32) noreturn + diff --git a/test/Transforms/Inline/devirtualize.ll b/test/Transforms/Inline/devirtualize.ll new file mode 100644 index 000000000000..9ed4b6958c38 --- /dev/null +++ b/test/Transforms/Inline/devirtualize.ll @@ -0,0 +1,182 @@ +; RUN: opt -S -inline -scalarrepl -instcombine -simplifycfg -instcombine -gvn -globaldce %s | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + + +; Simple devirt testcase, requires iteration between inliner and GVN. +; rdar://6295824 +define i32 @foo(i32 ()** noalias %p, i64* noalias %q) nounwind ssp { +entry: + store i32 ()* @bar, i32 ()** %p + store i64 0, i64* %q + %tmp3 = load i32 ()** %p ; <i32 ()*> [#uses=1] + %call = call i32 %tmp3() ; <i32> [#uses=1] + %X = add i32 %call, 4 + ret i32 %X + +; CHECK: @foo +; CHECK-NEXT: entry: +; CHECK-NEXT: store +; CHECK-NEXT: store +; CHECK-NEXT: ret i32 11 +} + +define internal i32 @bar() nounwind ssp { +entry: + ret i32 7 +} + + +;; More complex devirt case, from PR6724 +; CHECK: @_Z1gv() +; CHECK-NEXT: entry: +; CHECK-NEXT: ret i32 7 + +%0 = type { i8*, i8* } +%1 = type { i8*, i8*, i32, i32, i8*, i64, i8*, i64 } +%2 = type { i8*, i8*, i8* } +%struct.A = type { i8** } +%struct.B = type { i8** } +%struct.C = type { [16 x i8] } +%struct.D = type { [16 x i8] } + +@_ZTV1D = linkonce_odr constant [6 x i8*] [i8* null, i8* bitcast (%2* @_ZTI1D to i8*), i8* bitcast (i32 (%struct.C*)* @_ZN1D1fEv to i8*), i8* inttoptr (i64 -8 to i8*), i8* bitcast (%2* @_ZTI1D to i8*), i8* bitcast (i32 (%struct.C*)* @_ZThn8_N1D1fEv to i8*)] ; <[6 x i8*]*> [#uses=2] +@_ZTVN10__cxxabiv120__si_class_type_infoE = external global i8* ; <i8**> [#uses=1] +@_ZTS1D = linkonce_odr constant [3 x i8] c"1D\00" ; <[3 x i8]*> [#uses=1] +@_ZTVN10__cxxabiv121__vmi_class_type_infoE = external global i8* ; <i8**> [#uses=1] +@_ZTS1C = linkonce_odr constant [3 x i8] c"1C\00" ; <[3 x i8]*> [#uses=1] +@_ZTVN10__cxxabiv117__class_type_infoE = external global i8* ; <i8**> [#uses=1] +@_ZTS1A = linkonce_odr constant [3 x i8] c"1A\00" ; <[3 x i8]*> [#uses=1] +@_ZTI1A = linkonce_odr constant %0 { i8* bitcast (i8** getelementptr inbounds (i8** @_ZTVN10__cxxabiv117__class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([3 x i8]* @_ZTS1A, i32 0, i32 0) } ; <%0*> [#uses=1] +@_ZTS1B = linkonce_odr constant [3 x i8] c"1B\00" ; <[3 x i8]*> [#uses=1] +@_ZTI1B = linkonce_odr constant %0 { i8* bitcast (i8** getelementptr inbounds (i8** @_ZTVN10__cxxabiv117__class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([3 x i8]* @_ZTS1B, i32 0, i32 0) } ; <%0*> [#uses=1] +@_ZTI1C = linkonce_odr constant %1 { i8* bitcast (i8** getelementptr inbounds (i8** @_ZTVN10__cxxabiv121__vmi_class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([3 x i8]* @_ZTS1C, i32 0, i32 0), i32 0, i32 2, i8* bitcast (%0* @_ZTI1A to i8*), i64 2, i8* bitcast (%0* @_ZTI1B to i8*), i64 2050 } ; <%1*> [#uses=1] +@_ZTI1D = linkonce_odr constant %2 { i8* bitcast (i8** getelementptr inbounds (i8** @_ZTVN10__cxxabiv120__si_class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([3 x i8]* @_ZTS1D, i32 0, i32 0), i8* bitcast (%1* @_ZTI1C to i8*) } ; <%2*> [#uses=1] +@_ZTV1C = linkonce_odr constant [6 x i8*] [i8* null, i8* bitcast (%1* @_ZTI1C to i8*), i8* bitcast (i32 (%struct.C*)* @_ZN1C1fEv to i8*), i8* inttoptr (i64 -8 to i8*), i8* bitcast (%1* @_ZTI1C to i8*), i8* bitcast (i32 (%struct.C*)* @_ZThn8_N1C1fEv to i8*)] ; <[6 x i8*]*> [#uses=2] +@_ZTV1B = linkonce_odr constant [3 x i8*] [i8* null, i8* bitcast (%0* @_ZTI1B to i8*), i8* bitcast (i32 (%struct.A*)* @_ZN1B1fEv to i8*)] ; <[3 x i8*]*> [#uses=1] +@_ZTV1A = linkonce_odr constant [3 x i8*] [i8* null, i8* bitcast (%0* @_ZTI1A to i8*), i8* bitcast (i32 (%struct.A*)* @_ZN1A1fEv to i8*)] ; <[3 x i8*]*> [#uses=1] + +define i32 @_Z1gv() ssp { +entry: + %d = alloca %struct.C, align 8 ; <%struct.C*> [#uses=2] + call void @_ZN1DC1Ev(%struct.C* %d) + %call = call i32 @_Z1fP1D(%struct.C* %d) ; <i32> [#uses=1] + %X = add i32 %call, 3 + ret i32 %X +} + +define linkonce_odr void @_ZN1DC1Ev(%struct.C* %this) inlinehint ssp align 2 { +entry: + call void @_ZN1DC2Ev(%struct.C* %this) + ret void +} + +define internal i32 @_Z1fP1D(%struct.C* %d) ssp { +entry: + %0 = icmp eq %struct.C* %d, null ; <i1> [#uses=1] + br i1 %0, label %cast.end, label %cast.notnull + +cast.notnull: ; preds = %entry + %1 = bitcast %struct.C* %d to i8* ; <i8*> [#uses=1] + %add.ptr = getelementptr i8* %1, i64 8 ; <i8*> [#uses=1] + %2 = bitcast i8* %add.ptr to %struct.A* ; <%struct.A*> [#uses=1] + br label %cast.end + +cast.end: ; preds = %entry, %cast.notnull + %3 = phi %struct.A* [ %2, %cast.notnull ], [ null, %entry ] ; <%struct.A*> [#uses=2] + %4 = bitcast %struct.A* %3 to i32 (%struct.A*)*** ; <i32 (%struct.A*)***> [#uses=1] + %5 = load i32 (%struct.A*)*** %4 ; <i32 (%struct.A*)**> [#uses=1] + %vfn = getelementptr inbounds i32 (%struct.A*)** %5, i64 0 ; <i32 (%struct.A*)**> [#uses=1] + %6 = load i32 (%struct.A*)** %vfn ; <i32 (%struct.A*)*> [#uses=1] + %call = call i32 %6(%struct.A* %3) ; <i32> [#uses=1] + ret i32 %call +} + +define linkonce_odr i32 @_ZN1D1fEv(%struct.C* %this) ssp align 2 { +entry: + ret i32 4 +} + +define linkonce_odr i32 @_ZThn8_N1D1fEv(%struct.C* %this) { +entry: + %0 = bitcast %struct.C* %this to i8* ; <i8*> [#uses=1] + %1 = getelementptr inbounds i8* %0, i64 -8 ; <i8*> [#uses=1] + %2 = bitcast i8* %1 to %struct.C* ; <%struct.C*> [#uses=1] + %call = call i32 @_ZN1D1fEv(%struct.C* %2) ; <i32> [#uses=1] + ret i32 %call +} + +define linkonce_odr void @_ZN1DC2Ev(%struct.C* %this) inlinehint ssp align 2 { +entry: + call void @_ZN1CC2Ev(%struct.C* %this) + %0 = bitcast %struct.C* %this to i8* ; <i8*> [#uses=1] + %1 = getelementptr inbounds i8* %0, i64 0 ; <i8*> [#uses=1] + %2 = bitcast i8* %1 to i8*** ; <i8***> [#uses=1] + store i8** getelementptr inbounds ([6 x i8*]* @_ZTV1D, i64 0, i64 2), i8*** %2 + %3 = bitcast %struct.C* %this to i8* ; <i8*> [#uses=1] + %4 = getelementptr inbounds i8* %3, i64 8 ; <i8*> [#uses=1] + %5 = bitcast i8* %4 to i8*** ; <i8***> [#uses=1] + store i8** getelementptr inbounds ([6 x i8*]* @_ZTV1D, i64 0, i64 5), i8*** %5 + ret void +} + +define linkonce_odr void @_ZN1CC2Ev(%struct.C* %this) inlinehint ssp align 2 { +entry: + %0 = bitcast %struct.C* %this to %struct.A* ; <%struct.A*> [#uses=1] + call void @_ZN1AC2Ev(%struct.A* %0) + %1 = bitcast %struct.C* %this to i8* ; <i8*> [#uses=1] + %2 = getelementptr inbounds i8* %1, i64 8 ; <i8*> [#uses=1] + %3 = bitcast i8* %2 to %struct.A* ; <%struct.A*> [#uses=1] + call void @_ZN1BC2Ev(%struct.A* %3) + %4 = bitcast %struct.C* %this to i8* ; <i8*> [#uses=1] + %5 = getelementptr inbounds i8* %4, i64 0 ; <i8*> [#uses=1] + %6 = bitcast i8* %5 to i8*** ; <i8***> [#uses=1] + store i8** getelementptr inbounds ([6 x i8*]* @_ZTV1C, i64 0, i64 2), i8*** %6 + %7 = bitcast %struct.C* %this to i8* ; <i8*> [#uses=1] + %8 = getelementptr inbounds i8* %7, i64 8 ; <i8*> [#uses=1] + %9 = bitcast i8* %8 to i8*** ; <i8***> [#uses=1] + store i8** getelementptr inbounds ([6 x i8*]* @_ZTV1C, i64 0, i64 5), i8*** %9 + ret void +} + +define linkonce_odr i32 @_ZN1C1fEv(%struct.C* %this) ssp align 2 { +entry: + ret i32 3 +} + +define linkonce_odr i32 @_ZThn8_N1C1fEv(%struct.C* %this) { +entry: + %0 = bitcast %struct.C* %this to i8* ; <i8*> [#uses=1] + %1 = getelementptr inbounds i8* %0, i64 -8 ; <i8*> [#uses=1] + %2 = bitcast i8* %1 to %struct.C* ; <%struct.C*> [#uses=1] + %call = call i32 @_ZN1C1fEv(%struct.C* %2) ; <i32> [#uses=1] + ret i32 %call +} + +define linkonce_odr void @_ZN1AC2Ev(%struct.A* %this) inlinehint ssp align 2 { +entry: + %0 = bitcast %struct.A* %this to i8* ; <i8*> [#uses=1] + %1 = getelementptr inbounds i8* %0, i64 0 ; <i8*> [#uses=1] + %2 = bitcast i8* %1 to i8*** ; <i8***> [#uses=1] + store i8** getelementptr inbounds ([3 x i8*]* @_ZTV1A, i64 0, i64 2), i8*** %2 + ret void +} + +define linkonce_odr void @_ZN1BC2Ev(%struct.A* %this) inlinehint ssp align 2 { +entry: + %0 = bitcast %struct.A* %this to i8* ; <i8*> [#uses=1] + %1 = getelementptr inbounds i8* %0, i64 0 ; <i8*> [#uses=1] + %2 = bitcast i8* %1 to i8*** ; <i8***> [#uses=1] + store i8** getelementptr inbounds ([3 x i8*]* @_ZTV1B, i64 0, i64 2), i8*** %2 + ret void +} + +define linkonce_odr i32 @_ZN1B1fEv(%struct.A* %this) ssp align 2 { +entry: + ret i32 2 +} + +define linkonce_odr i32 @_ZN1A1fEv(%struct.A* %this) ssp align 2 { +entry: + ret i32 1 +} diff --git a/test/Transforms/Inline/externally_available.ll b/test/Transforms/Inline/externally_available.ll index 43fe5d37f9e8..08b56385ac07 100644 --- a/test/Transforms/Inline/externally_available.ll +++ b/test/Transforms/Inline/externally_available.ll @@ -13,4 +13,4 @@ define i32 @result() { %A = call i32 @test_function() %B = add i32 %A, 1 ret i32 %B -}
\ No newline at end of file +} diff --git a/test/Transforms/Inline/gvn-inline-iteration.ll b/test/Transforms/Inline/gvn-inline-iteration.ll new file mode 100644 index 000000000000..32144d4ebba5 --- /dev/null +++ b/test/Transforms/Inline/gvn-inline-iteration.ll @@ -0,0 +1,23 @@ +; RUN: opt -inline -gvn %s -S -max-cg-scc-iterations=1 | FileCheck %s +; rdar://6295824 and PR6724 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +define i32 @foo(i32 ()** noalias nocapture %p, i64* noalias nocapture %q) nounwind ssp { +entry: + store i32 ()* @bar, i32 ()** %p + store i64 0, i64* %q + %tmp3 = load i32 ()** %p ; <i32 ()*> [#uses=1] + %call = tail call i32 %tmp3() nounwind ; <i32> [#uses=1] + ret i32 %call +} +; CHECK: @foo +; CHECK: ret i32 7 +; CHECK: @bar +; CHECK: ret i32 7 + +define internal i32 @bar() nounwind readnone ssp { +entry: + ret i32 7 +} diff --git a/test/Transforms/Inline/indirect_resolve.ll b/test/Transforms/Inline/indirect_resolve.ll deleted file mode 100644 index 76182e2fe4f6..000000000000 --- a/test/Transforms/Inline/indirect_resolve.ll +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: opt < %s -inline | llvm-dis -; PR4834 - -define i32 @main() { - %funcall1_ = call fastcc i32 ()* ()* @f1() - %executecommandptr1_ = call i32 %funcall1_() - ret i32 %executecommandptr1_ -} - -define internal fastcc i32 ()* @f1() nounwind readnone { - ret i32 ()* @f2 -} - -define internal i32 @f2() nounwind readnone { - ret i32 1 -} diff --git a/test/Transforms/Inline/noinline-recursive-fn.ll b/test/Transforms/Inline/noinline-recursive-fn.ll new file mode 100644 index 000000000000..1d5ebbbf0fa9 --- /dev/null +++ b/test/Transforms/Inline/noinline-recursive-fn.ll @@ -0,0 +1,73 @@ +; The inliner should never inline recursive functions into other functions. +; This effectively is just peeling off the first iteration of a loop, and the +; inliner heuristics are not set up for this. + +; RUN: opt -inline %s -S | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.3" + +@g = common global i32 0 ; <i32*> [#uses=1] + +define internal void @foo(i32 %x) nounwind ssp { +entry: + %0 = icmp slt i32 %x, 0 ; <i1> [#uses=1] + br i1 %0, label %return, label %bb + +bb: ; preds = %entry + %1 = sub nsw i32 %x, 1 ; <i32> [#uses=1] + call void @foo(i32 %1) nounwind ssp + volatile store i32 1, i32* @g, align 4 + ret void + +return: ; preds = %entry + ret void +} + + +;; CHECK: @bonk +;; CHECK: call void @foo(i32 42) +define void @bonk() nounwind ssp { +entry: + call void @foo(i32 42) nounwind ssp + ret void +} + + + +;; Here is an indirect case that should not be infinitely inlined. + +define internal void @f1(i32 %x, i8* %Foo, i8* %Bar) nounwind ssp { +entry: + %0 = bitcast i8* %Bar to void (i32, i8*, i8*)* + %1 = sub nsw i32 %x, 1 + call void %0(i32 %1, i8* %Foo, i8* %Bar) nounwind + volatile store i32 42, i32* @g, align 4 + ret void +} + +define internal void @f2(i32 %x, i8* %Foo, i8* %Bar) nounwind ssp { +entry: + %0 = icmp slt i32 %x, 0 ; <i1> [#uses=1] + br i1 %0, label %return, label %bb + +bb: ; preds = %entry + %1 = bitcast i8* %Foo to void (i32, i8*, i8*)* ; <void (i32, i8*, i8*)*> [#uses=1] + call void %1(i32 %x, i8* %Foo, i8* %Bar) nounwind + volatile store i32 13, i32* @g, align 4 + ret void + +return: ; preds = %entry + ret void +} + + +; CHECK: @top_level +; CHECK: call void @f2(i32 122 +; Here we inline one instance of the cycle, but we don't want to completely +; unroll it. +define void @top_level() nounwind ssp { +entry: + call void @f2(i32 123, i8* bitcast (void (i32, i8*, i8*)* @f1 to i8*), i8* bitcast (void (i32, i8*, i8*)* @f2 to i8*)) nounwind ssp + ret void +} diff --git a/test/Transforms/InstCombine/2007-12-28-IcmpSub2.ll b/test/Transforms/InstCombine/2007-12-28-IcmpSub2.ll index b59548fd8e6f..8721c83521bf 100644 --- a/test/Transforms/InstCombine/2007-12-28-IcmpSub2.ll +++ b/test/Transforms/InstCombine/2007-12-28-IcmpSub2.ll @@ -86,4 +86,4 @@ entry: %cmp = icmp ne i32 %sub, 0 %retval = select i1 %cmp, i32 1, i32 0 ret i32 %retval -}
\ No newline at end of file +} diff --git a/test/Transforms/InstCombine/invariant.ll b/test/Transforms/InstCombine/invariant.ll index c67ad3319593..383238022692 100644 --- a/test/Transforms/InstCombine/invariant.ll +++ b/test/Transforms/InstCombine/invariant.ll @@ -3,13 +3,13 @@ declare void @g(i8*) -declare { }* @llvm.invariant.start(i64, i8* nocapture) nounwind readonly +declare {}* @llvm.invariant.start(i64, i8* nocapture) nounwind readonly define i8 @f() { %a = alloca i8 ; <i8*> [#uses=4] store i8 0, i8* %a - %i = call { }* @llvm.invariant.start(i64 1, i8* %a) ; <{ }*> [#uses=0] - ; CHECK: call { }* @llvm.invariant.start + %i = call {}* @llvm.invariant.start(i64 1, i8* %a) ; <{}*> [#uses=0] + ; CHECK: call {}* @llvm.invariant.start call void @g(i8* %a) %r = load i8* %a ; <i8> [#uses=1] ret i8 %r diff --git a/test/Transforms/InstCombine/objsize.ll b/test/Transforms/InstCombine/objsize.ll index d74312d2e7e9..664701bf2114 100644 --- a/test/Transforms/InstCombine/objsize.ll +++ b/test/Transforms/InstCombine/objsize.ll @@ -111,10 +111,10 @@ define i32 @test4() nounwind ssp { entry: %0 = alloca %struct.data, align 8 %1 = bitcast %struct.data* %0 to i8* - %2 = call i64 @llvm.objectsize.i64(i8* %1, i1 false) nounwind + %2 = call i32 @llvm.objectsize.i32(i8* %1, i1 false) nounwind ; CHECK-NOT: @llvm.objectsize -; CHECK: @llvm.memset.p0i8.i64(i8* %1, i8 0, i64 1824, i32 8, i1 false) - %3 = call i8* @__memset_chk(i8* %1, i32 0, i64 1824, i64 %2) nounwind +; CHECK: @llvm.memset.p0i8.i32(i8* %1, i8 0, i32 1824, i32 8, i1 false) + %3 = call i8* @__memset_chk(i8* %1, i32 0, i32 1824, i32 %2) nounwind ret i32 0 } @@ -145,10 +145,8 @@ entry: ret void } -declare i8* @__memset_chk(i8*, i32, i64, i64) nounwind +declare i8* @__memset_chk(i8*, i32, i32, i32) nounwind declare noalias i8* @malloc(i32) nounwind declare i32 @llvm.objectsize.i32(i8*, i1) nounwind readonly - -declare i64 @llvm.objectsize.i64(i8*, i1) nounwind readonly diff --git a/test/Transforms/InstCombine/odr-linkage.ll b/test/Transforms/InstCombine/odr-linkage.ll index a64ef289a4b6..61365b4848ab 100644 --- a/test/Transforms/InstCombine/odr-linkage.ll +++ b/test/Transforms/InstCombine/odr-linkage.ll @@ -16,4 +16,4 @@ define i32 @test() { %c = add i32 %b, %D ret i32 %c } -
\ No newline at end of file + diff --git a/test/Transforms/InstCombine/strcpy_chk.ll b/test/Transforms/InstCombine/strcpy_chk.ll index a20a13c78b23..8835a0ba467c 100644 --- a/test/Transforms/InstCombine/strcpy_chk.ll +++ b/test/Transforms/InstCombine/strcpy_chk.ll @@ -1,4 +1,5 @@ ; RUN: opt < %s -instcombine -S | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" @a = common global [60 x i8] zeroinitializer, align 1 ; <[60 x i8]*> [#uses=1] @.str = private constant [8 x i8] c"abcdefg\00" ; <[8 x i8]*> [#uses=1] diff --git a/test/Transforms/InstCombine/vec_shuffle.ll b/test/Transforms/InstCombine/vec_shuffle.ll index 29adc1e20890..5132a8ff9bd1 100644 --- a/test/Transforms/InstCombine/vec_shuffle.ll +++ b/test/Transforms/InstCombine/vec_shuffle.ll @@ -86,4 +86,4 @@ define <4 x i8> @test9(<16 x i8> %tmp6) nounwind { %tmp7 = shufflevector <16 x i8> %tmp6, <16 x i8> undef, <4 x i32> < i32 13, i32 9, i32 4, i32 13 > ; <<4 x i8>> [#uses=1] %tmp9 = shufflevector <4 x i8> %tmp7, <4 x i8> undef, <4 x i32> < i32 3, i32 1, i32 2, i32 0 > ; <<4 x i8>> [#uses=1] ret <4 x i8> %tmp9 -}
\ No newline at end of file +} diff --git a/test/Transforms/JumpThreading/crash.ll b/test/Transforms/JumpThreading/crash.ll index c65fd1014be4..21620bef9ccc 100644 --- a/test/Transforms/JumpThreading/crash.ll +++ b/test/Transforms/JumpThreading/crash.ll @@ -324,3 +324,20 @@ A: ; preds = %entry call void undef(i64 ptrtoint (i8* blockaddress(@test11, %A) to i64)) nounwind unreachable } + +; PR6743 +define void @test12() nounwind ssp { +entry: + br label %lbl_51 + +lbl_51: ; preds = %if.then, %entry + %tmp3 = phi i1 [ false, %if.then ], [ undef, %entry ] ; <i1> [#uses=2] + br i1 %tmp3, label %if.end12, label %if.then + +if.then: ; preds = %lbl_51 + br i1 %tmp3, label %lbl_51, label %if.end12 + +if.end12: ; preds = %if.then, %lbl_51 + ret void +} + diff --git a/test/Transforms/LoopIndexSplit/2008-02-08-Crash.ll b/test/Transforms/LoopIndexSplit/2008-02-08-Crash.ll index 084746494357..3cfd6c96b7b2 100644 --- a/test/Transforms/LoopIndexSplit/2008-02-08-Crash.ll +++ b/test/Transforms/LoopIndexSplit/2008-02-08-Crash.ll @@ -45,4 +45,4 @@ bb39: ; preds = %bb12, %bb3, %bb17 return: ; preds = %bb39 ret void -}
\ No newline at end of file +} diff --git a/test/Transforms/LoopIndexSplit/PR4174-2.ll b/test/Transforms/LoopIndexSplit/PR4174-2.ll new file mode 100644 index 000000000000..cc17bc0a9337 --- /dev/null +++ b/test/Transforms/LoopIndexSplit/PR4174-2.ll @@ -0,0 +1,38 @@ +; RUN: llvm-as < %s | opt -loop-index-split | llvm-dis | not grep clone + +declare void @f() + +define fastcc i32 @main() nounwind { +entry: + br label %bb1552 + +bb1552: + %j295.0.reg2mem.0 = phi i32 [ %storemerge110, %bb1669 ], [ 0, %entry ] + br label %bb1553 + +bb1553: + call void @f() + %tmp1628 = icmp sgt i32 %j295.0.reg2mem.0, -3 + br i1 %tmp1628, label %bb1588, label %bb1616 + +bb1588: + br label %bb1616 + +bb1616: + %tmp1629 = icmp sgt i32 %j295.0.reg2mem.0, -3 + br i1 %tmp1629, label %bb1649, label %bb1632 + +bb1632: + br label %bb1669 + +bb1649: + br label %bb1669 + +bb1669: + %storemerge110 = add i32 %j295.0.reg2mem.0, 1 + %tmp1672 = icmp sgt i32 %storemerge110, 3 + br i1 %tmp1672, label %bb1678, label %bb1552 + +bb1678: + ret i32 0 +} diff --git a/test/Transforms/LoopIndexSplit/PR4174.ll b/test/Transforms/LoopIndexSplit/PR4174.ll new file mode 100644 index 000000000000..e8f5a737f05b --- /dev/null +++ b/test/Transforms/LoopIndexSplit/PR4174.ll @@ -0,0 +1,23 @@ +; RUN: llvm-as < %s | opt -loop-index-split | llvm-dis | not grep clone + +declare void @f() + +define i32 @main() { +entry: + br label %head +head: + %i = phi i32 [0, %entry], [%i1, %tail] + call void @f() + %splitcond = icmp slt i32 %i, 2 + br i1 %splitcond, label %yes, label %no +yes: + br label %tail +no: + br label %tail +tail: + %i1 = add i32 %i, 1 + %exitcond = icmp slt i32 %i1, 4 + br i1 %exitcond, label %head, label %exit +exit: + ret i32 0 +} diff --git a/test/Transforms/LoopStrengthReduce/insert-positions.ll b/test/Transforms/LoopStrengthReduce/insert-positions.ll new file mode 100644 index 000000000000..1a695f35e3b0 --- /dev/null +++ b/test/Transforms/LoopStrengthReduce/insert-positions.ll @@ -0,0 +1,69 @@ +; RUN: llc < %s -march=x86-64 >/dev/null + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" + +define void @test0() nounwind { +if.end90.i.i: + br label %while.body.i.i221.i + +while.body.i.i221.i: ; preds = %while.cond.backedge.i.i.i, %if.end90.i.i + br i1 undef, label %if.then.i.i224.i, label %while.cond.backedge.i.i.i + +while.cond.backedge.i.i.i: ; preds = %for.end.i.i.i, %while.body.i.i221.i + br label %while.body.i.i221.i + +if.then.i.i224.i: ; preds = %while.body.i.i221.i + switch i32 undef, label %for.cond.i.i226.i [ + i32 92, label %sw.bb.i.i225.i + i32 34, label %sw.bb.i.i225.i + i32 110, label %sw.bb21.i.i.i + ] + +sw.bb.i.i225.i: ; preds = %if.then.i.i224.i, %if.then.i.i224.i + unreachable + +sw.bb21.i.i.i: ; preds = %if.then.i.i224.i + unreachable + +for.cond.i.i226.i: ; preds = %for.body.i.i.i, %if.then.i.i224.i + %0 = phi i64 [ %tmp154.i.i.i, %for.body.i.i.i ], [ 0, %if.then.i.i224.i ] ; <i64> [#uses=2] + %tmp154.i.i.i = add i64 %0, 1 ; <i64> [#uses=2] + %i.0.i.i.i = trunc i64 %0 to i32 ; <i32> [#uses=1] + br i1 undef, label %land.rhs.i.i.i, label %for.end.i.i.i + +land.rhs.i.i.i: ; preds = %for.cond.i.i226.i + br i1 undef, label %for.body.i.i.i, label %for.end.i.i.i + +for.body.i.i.i: ; preds = %land.rhs.i.i.i + br label %for.cond.i.i226.i + +for.end.i.i.i: ; preds = %land.rhs.i.i.i, %for.cond.i.i226.i + %idx.ext.i.i.i = sext i32 %i.0.i.i.i to i64 ; <i64> [#uses=1] + %sub.ptr72.sum.i.i.i = xor i64 %idx.ext.i.i.i, -1 ; <i64> [#uses=1] + %pos.addr.1.sum155.i.i.i = add i64 %tmp154.i.i.i, %sub.ptr72.sum.i.i.i ; <i64> [#uses=1] + %arrayidx76.i.i.i = getelementptr inbounds i8* undef, i64 %pos.addr.1.sum155.i.i.i ; <i8*> [#uses=0] + br label %while.cond.backedge.i.i.i +} + +define void @test1() nounwind { +entry: + %t = shl i32 undef, undef ; <i32> [#uses=1] + %t9 = sub nsw i32 0, %t ; <i32> [#uses=1] + br label %outer + +outer: ; preds = %bb18, %bb + %i12 = phi i32 [ %t21, %bb18 ], [ 0, %entry ] ; <i32> [#uses=2] + %i13 = phi i32 [ %t20, %bb18 ], [ 0, %entry ] ; <i32> [#uses=2] + br label %inner + +inner: ; preds = %bb16, %bb11 + %t17 = phi i32 [ %i13, %outer ], [ undef, %inner ] ; <i32> [#uses=1] + store i32 %t17, i32* undef + br i1 undef, label %bb18, label %inner + +bb18: ; preds = %bb16 + %t19 = add i32 %i13, %t9 ; <i32> [#uses=1] + %t20 = add i32 %t19, %i12 ; <i32> [#uses=1] + %t21 = add i32 %i12, 1 ; <i32> [#uses=1] + br label %outer +} diff --git a/test/Transforms/LoopStrengthReduce/pr2537.ll b/test/Transforms/LoopStrengthReduce/pr2537.ll index 73c3152d30e7..46ad70e736d8 100644 --- a/test/Transforms/LoopStrengthReduce/pr2537.ll +++ b/test/Transforms/LoopStrengthReduce/pr2537.ll @@ -18,4 +18,4 @@ afterdo: ; preds = %dobody ret void } -declare void @b(i128 %add)
\ No newline at end of file +declare void @b(i128 %add) diff --git a/test/Transforms/LoopStrengthReduce/quadradic-exit-value.ll b/test/Transforms/LoopStrengthReduce/quadradic-exit-value.ll index 8959c1774099..59f14fcd1ce5 100644 --- a/test/Transforms/LoopStrengthReduce/quadradic-exit-value.ll +++ b/test/Transforms/LoopStrengthReduce/quadradic-exit-value.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -analyze -iv-users | grep {\{1,+,3,+,2\}<%loop> (post-inc)} +; RUN: opt < %s -analyze -iv-users | grep {\{1,+,3,+,2\}<%loop> (post-inc with loop %loop)} ; The value of %r is dependent on a polynomial iteration expression. diff --git a/test/Transforms/LoopStrengthReduce/uglygep.ll b/test/Transforms/LoopStrengthReduce/uglygep.ll new file mode 100644 index 000000000000..dca97e9ad187 --- /dev/null +++ b/test/Transforms/LoopStrengthReduce/uglygep.ll @@ -0,0 +1,67 @@ +; RUN: opt < %s -loop-reduce -S | not grep uglygep + +; LSR shouldn't consider %t8 to be an interesting user of %t6, and it +; should be able to form pretty GEPs. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +define void @Z4() nounwind { +bb: + br label %bb3 + +bb1: ; preds = %bb3 + br i1 undef, label %bb10, label %bb2 + +bb2: ; preds = %bb1 + %t = add i64 %t4, 1 ; <i64> [#uses=1] + br label %bb3 + +bb3: ; preds = %bb2, %bb + %t4 = phi i64 [ %t, %bb2 ], [ 0, %bb ] ; <i64> [#uses=3] + br label %bb1 + +bb10: ; preds = %bb9 + %t7 = icmp eq i64 %t4, 0 ; <i1> [#uses=1] + %t3 = add i64 %t4, 16 ; <i64> [#uses=1] + br label %bb14 + +bb14: ; preds = %bb14, %bb10 + %t2 = getelementptr inbounds i8* undef, i64 %t4 ; <i8*> [#uses=1] + store i8 undef, i8* %t2 + %t6 = load float** undef + %t8 = bitcast float* %t6 to i8* ; <i8*> [#uses=1] + %t9 = getelementptr inbounds i8* %t8, i64 %t3 ; <i8*> [#uses=1] + store i8 undef, i8* %t9 + br label %bb14 +} + +define fastcc void @TransformLine() nounwind { +bb: + br label %loop0 + +loop0: ; preds = %loop0, %bb + %i0 = phi i32 [ %i0.next, %loop0 ], [ 0, %bb ] ; <i32> [#uses=2] + %i0.next = add i32 %i0, 1 ; <i32> [#uses=1] + br i1 false, label %loop0, label %bb0 + +bb0: ; preds = %loop0 + br label %loop1 + +loop1: ; preds = %bb5, %bb0 + %i1 = phi i32 [ 0, %bb0 ], [ %i1.next, %bb5 ] ; <i32> [#uses=4] + %t0 = add i32 %i0, %i1 ; <i32> [#uses=1] + br i1 false, label %bb2, label %bb6 + +bb2: ; preds = %loop1 + br i1 true, label %bb6, label %bb5 + +bb5: ; preds = %bb2 + %i1.next = add i32 %i1, 1 ; <i32> [#uses=1] + br i1 true, label %bb6, label %loop1 + +bb6: ; preds = %bb5, %bb2, %loop1 + %p8 = phi i32 [ %t0, %bb5 ], [ undef, %loop1 ], [ undef, %bb2 ] ; <i32> [#uses=0] + %p9 = phi i32 [ undef, %bb5 ], [ %i1, %loop1 ], [ %i1, %bb2 ] ; <i32> [#uses=0] + unreachable +} diff --git a/test/Transforms/LoopUnswitch/crash.ll b/test/Transforms/LoopUnswitch/crash.ll index fac55a6bb1a7..101fb7a2c2ce 100644 --- a/test/Transforms/LoopUnswitch/crash.ll +++ b/test/Transforms/LoopUnswitch/crash.ll @@ -45,3 +45,22 @@ for.body: ; preds = %for.body, %bb.nph for.end: ; preds = %for.body, %entry ret void } + +; PR6879 +define i32* @test3(i32** %p_45, i16 zeroext %p_46, i64 %p_47, i64 %p_48, i16 signext %p_49) nounwind { +entry: + br label %for.cond + +for.cond: ; preds = %for.cond4, %entry + br i1 false, label %for.cond4, label %for.end88 + +for.cond4: ; preds = %for.cond + %conv46 = trunc i32 0 to i8 ; <i8> [#uses=2] + %cmp60 = icmp sgt i8 %conv46, 124 ; <i1> [#uses=1] + %or.cond = and i1 undef, %cmp60 ; <i1> [#uses=1] + %cond = select i1 %or.cond, i8 %conv46, i8 undef ; <i8> [#uses=0] + br label %for.cond + +for.end88: ; preds = %for.cond + ret i32* undef +} diff --git a/test/Transforms/PruneEH/2008-09-05-CGUpdate.ll b/test/Transforms/PruneEH/2008-09-05-CGUpdate.ll index 347af8f8463c..33e0cfa3ce53 100644 --- a/test/Transforms/PruneEH/2008-09-05-CGUpdate.ll +++ b/test/Transforms/PruneEH/2008-09-05-CGUpdate.ll @@ -1,6 +1,6 @@ ; RUN: opt < %s -prune-eh -inline -print-callgraph \ ; RUN: -disable-output |& \ -; RUN: grep {Calls.*ce3806g__fxio__put__put_int64__4.1339} | count 2 +; RUN: grep {calls.*ce3806g__fxio__put__put_int64__4.1339} | count 2 %struct.FRAME.ce3806g = type { %struct.string___XUB, %struct.string___XUB, %struct.string___XUB, %struct.string___XUB } %struct.FRAME.ce3806g__fxio__put__4 = type { i32, i32, i32, %struct.system__file_control_block__pstring*, i32, i32, i8 } %struct.RETURN = type { i8, i32 } diff --git a/test/Transforms/SCCP/ipsccp-basic.ll b/test/Transforms/SCCP/ipsccp-basic.ll index e3699209a35b..a3c7637f986b 100644 --- a/test/Transforms/SCCP/ipsccp-basic.ll +++ b/test/Transforms/SCCP/ipsccp-basic.ll @@ -188,7 +188,7 @@ define void @test8b(i32* %P) { %X = call {} @test8a(i32 5, i32* %P) ret void ; CHECK: define void @test8b -; CHECK-NEXT: call { } @test8a +; CHECK-NEXT: call {} @test8a ; CHECK-NEXT: ret void } diff --git a/test/Transforms/SCCP/undef-resolve.ll b/test/Transforms/SCCP/undef-resolve.ll new file mode 100644 index 000000000000..bed561c8e4f2 --- /dev/null +++ b/test/Transforms/SCCP/undef-resolve.ll @@ -0,0 +1,106 @@ +; RUN: opt %s -sccp -S | FileCheck %s + + +; PR6940 +define double @test1() { + %t = sitofp i32 undef to double + ret double %t +; CHECK: @test1 +; CHECK: ret double 0.0 +} + + +; rdar://7832370 +; Check that lots of stuff doesn't get turned into undef. +define i32 @test2() nounwind readnone ssp { +; CHECK: @test2 +init: + br label %control.outer.outer + +control.outer.loopexit.us-lcssa: ; preds = %control + br label %control.outer.loopexit + +control.outer.loopexit: ; preds = %control.outer.loopexit.us-lcssa.us, %control.outer.loopexit.us-lcssa + br label %control.outer.outer.backedge + +control.outer.outer: ; preds = %control.outer.outer.backedge, %init + %switchCond.0.ph.ph = phi i32 [ 2, %init ], [ 3, %control.outer.outer.backedge ] ; <i32> [#uses=2] + %i.0.ph.ph = phi i32 [ undef, %init ], [ %i.0.ph.ph.be, %control.outer.outer.backedge ] ; <i32> [#uses=1] + %tmp4 = icmp eq i32 %i.0.ph.ph, 0 ; <i1> [#uses=1] + br i1 %tmp4, label %control.outer.outer.split.us, label %control.outer.outer.control.outer.outer.split_crit_edge + +control.outer.outer.control.outer.outer.split_crit_edge: ; preds = %control.outer.outer + br label %control.outer + +control.outer.outer.split.us: ; preds = %control.outer.outer + br label %control.outer.us + +control.outer.us: ; preds = %bb3.us, %control.outer.outer.split.us + %A.0.ph.us = phi i32 [ %switchCond.0.us, %bb3.us ], [ 4, %control.outer.outer.split.us ] ; <i32> [#uses=2] + %switchCond.0.ph.us = phi i32 [ %A.0.ph.us, %bb3.us ], [ %switchCond.0.ph.ph, %control.outer.outer.split.us ] ; <i32> [#uses=1] + br label %control.us + +bb3.us: ; preds = %control.us + br label %control.outer.us + +bb0.us: ; preds = %control.us + br label %control.us + +; CHECK: control.us: ; preds = %bb0.us, %control.outer.us +; CHECK-NEXT: %switchCond.0.us = phi i32 +; CHECK-NEXT: switch i32 %switchCond.0.us +control.us: ; preds = %bb0.us, %control.outer.us + %switchCond.0.us = phi i32 [ %A.0.ph.us, %bb0.us ], [ %switchCond.0.ph.us, %control.outer.us ] ; <i32> [#uses=2] + switch i32 %switchCond.0.us, label %control.outer.loopexit.us-lcssa.us [ + i32 0, label %bb0.us + i32 1, label %bb1.us-lcssa.us + i32 3, label %bb3.us + i32 4, label %bb4.us-lcssa.us + ] + +control.outer.loopexit.us-lcssa.us: ; preds = %control.us + br label %control.outer.loopexit + +bb1.us-lcssa.us: ; preds = %control.us + br label %bb1 + +bb4.us-lcssa.us: ; preds = %control.us + br label %bb4 + +control.outer: ; preds = %bb3, %control.outer.outer.control.outer.outer.split_crit_edge + %A.0.ph = phi i32 [ %nextId17, %bb3 ], [ 4, %control.outer.outer.control.outer.outer.split_crit_edge ] ; <i32> [#uses=1] + %switchCond.0.ph = phi i32 [ 0, %bb3 ], [ %switchCond.0.ph.ph, %control.outer.outer.control.outer.outer.split_crit_edge ] ; <i32> [#uses=1] + br label %control + +control: ; preds = %bb0, %control.outer + %switchCond.0 = phi i32 [ %A.0.ph, %bb0 ], [ %switchCond.0.ph, %control.outer ] ; <i32> [#uses=2] + switch i32 %switchCond.0, label %control.outer.loopexit.us-lcssa [ + i32 0, label %bb0 + i32 1, label %bb1.us-lcssa + i32 3, label %bb3 + i32 4, label %bb4.us-lcssa + ] + +bb4.us-lcssa: ; preds = %control + br label %bb4 + +bb4: ; preds = %bb4.us-lcssa, %bb4.us-lcssa.us + br label %control.outer.outer.backedge + +control.outer.outer.backedge: ; preds = %bb4, %control.outer.loopexit + %i.0.ph.ph.be = phi i32 [ 1, %bb4 ], [ 0, %control.outer.loopexit ] ; <i32> [#uses=1] + br label %control.outer.outer + +bb3: ; preds = %control + %nextId17 = add i32 %switchCond.0, -2 ; <i32> [#uses=1] + br label %control.outer + +bb0: ; preds = %control + br label %control + +bb1.us-lcssa: ; preds = %control + br label %bb1 + +bb1: ; preds = %bb1.us-lcssa, %bb1.us-lcssa.us + ret i32 0 +} diff --git a/test/Transforms/ScalarRepl/memcpy-align.ll b/test/Transforms/ScalarRepl/memcpy-align.ll new file mode 100644 index 000000000000..91d354d31a3b --- /dev/null +++ b/test/Transforms/ScalarRepl/memcpy-align.ll @@ -0,0 +1,32 @@ +; RUN: opt %s -scalarrepl -S | FileCheck %s +; PR6832 +target datalayout = +"e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" +target triple = "arm-u-u" + +%0 = type { %struct.anon, %struct.anon } +%struct.anon = type { [4 x i8] } + +@c = external global %0 ; <%0*> [#uses=1] + +define arm_aapcscc void @good() nounwind { +entry: + %x0 = alloca %struct.anon, align 4 ; <%struct.anon*> [#uses=2] + %tmp = bitcast %struct.anon* %x0 to i8* ; <i8*> [#uses=1] + call void @llvm.memset.p0i8.i32(i8* %tmp, i8 0, i32 4, i32 4, i1 false) + %tmp1 = bitcast %struct.anon* %x0 to i8* ; <i8*> [#uses=1] + call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%0* @c, i32 +0, i32 0, i32 0, i32 0), i8* %tmp1, i32 4, i32 4, i1 false) + ret void + +; CHECK: store i8 0, i8*{{.*}}, align 4 +; CHECK: store i8 0, i8*{{.*}}, align 1 +; CHECK: store i8 0, i8*{{.*}}, align 2 +; CHECK: store i8 0, i8*{{.*}}, align 1 +} + +declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind + +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, +i1) nounwind + diff --git a/test/Transforms/TailCallElim/inf-recursion.ll b/test/Transforms/TailCallElim/inf-recursion.ll index a5f246d36ce1..e4ac9283aec5 100644 --- a/test/Transforms/TailCallElim/inf-recursion.ll +++ b/test/Transforms/TailCallElim/inf-recursion.ll @@ -1,6 +1,10 @@ -; RUN: opt < %s -tailcallelim -S | grep call +; RUN: opt < %s -tailcallelim -S | FileCheck %s + ; Don't turn this into an infinite loop, this is probably the implementation ; of fabs and we expect the codegen to lower fabs. +; CHECK: @fabs(double %f) +; CHECK: call +; CHECK: ret define double @fabs(double %f) { entry: @@ -8,3 +12,23 @@ entry: ret double %tmp2 } +; Do turn other calls into infinite loops though. + +; CHECK: define double @foo +; CHECK-NOT: call +; CHECK: } +define double @foo(double %f) { + %t= call double @foo(double %f) + ret double %t +} + +; CHECK: define float @fabsf +; CHECK-NOT: call +; CHECK: } +define float @fabsf(float %f) { + %t= call float @fabsf(float 2.0) + ret float %t +} + +declare float @fabsf(float %f) +declare x86_fp80 @fabsl(x86_fp80 %f) |