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-rw-r--r--test/CodeGen/R600/fmad.ll22
1 files changed, 11 insertions, 11 deletions
diff --git a/test/CodeGen/R600/fmad.ll b/test/CodeGen/R600/fmad.ll
index 62001edc3aa5..935e35123f45 100644
--- a/test/CodeGen/R600/fmad.ll
+++ b/test/CodeGen/R600/fmad.ll
@@ -1,19 +1,19 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-;CHECK: MULADD_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+;CHECK: MULADD_IEEE * {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-define void @test() {
- %r0 = call float @llvm.R600.load.input(i32 0)
- %r1 = call float @llvm.R600.load.input(i32 1)
- %r2 = call float @llvm.R600.load.input(i32 2)
+define void @test(<4 x float> inreg %reg0) #0 {
+ %r0 = extractelement <4 x float> %reg0, i32 0
+ %r1 = extractelement <4 x float> %reg0, i32 1
+ %r2 = extractelement <4 x float> %reg0, i32 2
%r3 = fmul float %r0, %r1
- %r4 = fadd float %r3, %r2
- call void @llvm.AMDGPU.store.output(float %r4, i32 0)
+ %r4 = fadd float %r3, %r2
+ %vec = insertelement <4 x float> undef, float %r4, i32 0
+ call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void
}
-declare float @llvm.R600.load.input(i32) readnone
-
-declare void @llvm.AMDGPU.store.output(float, i32)
-
declare float @fabs(float ) readnone
+declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
+
+attributes #0 = { "ShaderType"="0" } \ No newline at end of file