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-rw-r--r--test/CodeGen/Mips/llvm-ir/add.ll8
-rw-r--r--test/CodeGen/Mips/llvm-ir/and.ll13
-rw-r--r--test/CodeGen/Mips/llvm-ir/ashr.ll93
-rw-r--r--test/CodeGen/Mips/llvm-ir/call.ll4
-rw-r--r--test/CodeGen/Mips/llvm-ir/indirectbr.ll4
-rw-r--r--test/CodeGen/Mips/llvm-ir/lshr.ll93
-rw-r--r--test/CodeGen/Mips/llvm-ir/mul.ll58
-rw-r--r--test/CodeGen/Mips/llvm-ir/or.ll14
-rw-r--r--test/CodeGen/Mips/llvm-ir/ret.ll4
-rw-r--r--test/CodeGen/Mips/llvm-ir/sdiv.ll28
-rw-r--r--test/CodeGen/Mips/llvm-ir/select.ll24
-rw-r--r--test/CodeGen/Mips/llvm-ir/shl.ll77
-rw-r--r--test/CodeGen/Mips/llvm-ir/srem.ll30
-rw-r--r--test/CodeGen/Mips/llvm-ir/sub.ll8
-rw-r--r--test/CodeGen/Mips/llvm-ir/udiv.ll8
-rw-r--r--test/CodeGen/Mips/llvm-ir/urem.ll38
-rw-r--r--test/CodeGen/Mips/llvm-ir/xor.ll13
17 files changed, 322 insertions, 195 deletions
diff --git a/test/CodeGen/Mips/llvm-ir/add.ll b/test/CodeGen/Mips/llvm-ir/add.ll
index 83774eda634f..6cccc7df19f9 100644
--- a/test/CodeGen/Mips/llvm-ir/add.ll
+++ b/test/CodeGen/Mips/llvm-ir/add.ll
@@ -4,6 +4,10 @@
; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -14,6 +18,10 @@
; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
diff --git a/test/CodeGen/Mips/llvm-ir/and.ll b/test/CodeGen/Mips/llvm-ir/and.ll
index 09d0ef9238af..8ebcfe4a3f64 100644
--- a/test/CodeGen/Mips/llvm-ir/and.ll
+++ b/test/CodeGen/Mips/llvm-ir/and.ll
@@ -4,6 +4,10 @@
; RUN: -check-prefix=ALL -check-prefix=GP32
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -14,6 +18,10 @@
; RUN: -check-prefix=ALL -check-prefix=GP64
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64
@@ -51,10 +59,7 @@ define signext i32 @and_i32(i32 signext %a, i32 signext %b) {
entry:
; ALL-LABEL: and_i32:
- ; GP32: and $2, $4, $5
-
- ; GP64: and $[[T0:[0-9]+]], $4, $5
- ; GP64: sll $2, $[[T0]], 0
+ ; ALL: and $2, $4, $5
%r = and i32 %a, %b
ret i32 %r
diff --git a/test/CodeGen/Mips/llvm-ir/ashr.ll b/test/CodeGen/Mips/llvm-ir/ashr.ll
index 415998929aa0..cad4a39d7743 100644
--- a/test/CodeGen/Mips/llvm-ir/ashr.ll
+++ b/test/CodeGen/Mips/llvm-ir/ashr.ll
@@ -1,30 +1,42 @@
; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32 \
-; RUN: -check-prefix=M2 -check-prefix=NOT-R2-R6
+; RUN: -check-prefix=M2
; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
-; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \
-; RUN: -check-prefix=32R1-R2
+; RUN: -check-prefix=ALL -check-prefix=GP32 \
+; RUN: -check-prefix=32R1-R5
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32 \
-; RUN: -check-prefix=32R1-R2 -check-prefix=R2-R6
+; RUN: -check-prefix=32R1-R5
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32 \
+; RUN: -check-prefix=32R1-R5
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32 \
+; RUN: -check-prefix=32R1-R5
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32 \
-; RUN: -check-prefix=32R6 -check-prefix=R2-R6
+; RUN: -check-prefix=32R6
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64 \
-; RUN: -check-prefix=M3 -check-prefix=NOT-R2-R6
+; RUN: -check-prefix=M3
; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64 \
-; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6
+; RUN: -check-prefix=GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64 \
-; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6
+; RUN: -check-prefix=GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64 \
-; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
+; RUN: -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64 \
+; RUN: -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64 \
+; RUN: -check-prefix=GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64 \
-; RUN: -check-prefix=64R6 -check-prefix=R2-R6
+; RUN: -check-prefix=64R6
define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -91,17 +103,17 @@ entry:
; M2: jr $ra
; M2: nop
- ; 32R1-R2: srlv $[[T0:[0-9]+]], $5, $7
- ; 32R1-R2: not $[[T1:[0-9]+]], $7
- ; 32R1-R2: sll $[[T2:[0-9]+]], $4, 1
- ; 32R1-R2: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
- ; 32R1-R2: or $3, $[[T3]], $[[T0]]
- ; 32R1-R2: srav $[[T4:[0-9]+]], $4, $7
- ; 32R1-R2: andi $[[T5:[0-9]+]], $7, 32
- ; 32R1-R2: movn $3, $[[T4]], $[[T5]]
- ; 32R1-R2: sra $4, $4, 31
- ; 32R1-R2: jr $ra
- ; 32R1-R2: movn $2, $4, $[[T5]]
+ ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7
+ ; 32R1-R5: not $[[T1:[0-9]+]], $7
+ ; 32R1-R5: sll $[[T2:[0-9]+]], $4, 1
+ ; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+ ; 32R1-R5: or $3, $[[T3]], $[[T0]]
+ ; 32R1-R5: srav $[[T4:[0-9]+]], $4, $7
+ ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32
+ ; 32R1-R5: movn $3, $[[T4]], $[[T5]]
+ ; 32R1-R5: sra $4, $4, 31
+ ; 32R1-R5: jr $ra
+ ; 32R1-R5: movn $2, $4, $[[T5]]
; 32R6: srav $[[T0:[0-9]+]], $4, $7
; 32R6: andi $[[T1:[0-9]+]], $7, 32
@@ -119,9 +131,7 @@ entry:
; 32R6: jr $ra
; 32R6: or $3, $[[T0]], $[[T11]]
- ; FIXME: The sll instruction below is redundant.
- ; GP64: sll $[[T0:[0-9]+]], $5, 0
- ; GP64: dsrav $2, $4, $[[T0]]
+ ; GP64: dsrav $2, $4, $5
%r = ashr i64 %a, %b
ret i64 %r
@@ -134,11 +144,11 @@ entry:
; GP32: lw $25, %call16(__ashrti3)($gp)
; M3: sll $[[T0:[0-9]+]], $7, 0
- ; M3: dsrav $[[T1:[0-9]+]], $4, $[[T0]]
+ ; M3: dsrav $[[T1:[0-9]+]], $4, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
; M3: move $3, $[[T1]]
- ; M3: dsrlv $[[T4:[0-9]+]], $5, $[[T0]]
+ ; M3: dsrlv $[[T4:[0-9]+]], $5, $7
; M3: dsll $[[T5:[0-9]+]], $4, 1
; M3: not $[[T6:[0-9]+]], $[[T0]]
; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
@@ -151,35 +161,34 @@ entry:
; M3: jr $ra
; M3: nop
- ; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0
- ; GP64-NOT-R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]]
- ; GP64-NOT-R6: dsll $[[T2:[0-9]+]], $4, 1
- ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]]
- ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
- ; GP64-NOT-R6: or $3, $[[T4]], $[[T1]]
- ; GP64-NOT-R6: dsrav $2, $4, $[[T0]]
- ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 64
-
+ ; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7
+ ; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1
+ ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0
+ ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]]
+ ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
+ ; GP64-NOT-R6: or $3, $[[T4]], $[[T0]]
+ ; GP64-NOT-R6: dsrav $2, $4, $7
+ ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64
; GP64-NOT-R6: movn $3, $2, $[[T5]]
; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 63
; GP64-NOT-R6: jr $ra
; GP64-NOT-R6: movn $2, $[[T6]], $[[T5]]
- ; 64R6: sll $[[T0:[0-9]+]], $7, 0
- ; 64R6: dsrav $[[T1:[0-9]+]], $4, $[[T0]]
- ; 64R6: andi $[[T2:[0-9]+]], $[[T0]], 64
+ ; 64R6: dsrav $[[T0:[0-9]+]], $4, $7
+ ; 64R6: sll $[[T1:[0-9]+]], $7, 0
+ ; 64R6: andi $[[T2:[0-9]+]], $[[T1]], 64
; 64R6: sll $[[T3:[0-9]+]], $[[T2]], 0
- ; 64R6: seleqz $[[T4:[0-9]+]], $[[T1]], $[[T3]]
+ ; 64R6: seleqz $[[T4:[0-9]+]], $[[T0]], $[[T3]]
; 64R6: dsra $[[T5:[0-9]+]], $4, 63
; 64R6: selnez $[[T6:[0-9]+]], $[[T5]], $[[T3]]
; 64R6: or $2, $[[T6]], $[[T4]]
- ; 64R6: dsrlv $[[T7:[0-9]+]], $5, $[[T0]]
+ ; 64R6: dsrlv $[[T7:[0-9]+]], $5, $7
; 64R6: dsll $[[T8:[0-9]+]], $4, 1
- ; 64R6: not $[[T9:[0-9]+]], $[[T0]]
+ ; 64R6: not $[[T9:[0-9]+]], $[[T1]]
; 64R6: dsllv $[[T10:[0-9]+]], $[[T8]], $[[T9]]
; 64R6: or $[[T11:[0-9]+]], $[[T10]], $[[T7]]
; 64R6: seleqz $[[T12:[0-9]+]], $[[T11]], $[[T3]]
- ; 64R6: selnez $[[T13:[0-9]+]], $[[T1]], $[[T3]]
+ ; 64R6: selnez $[[T13:[0-9]+]], $[[T0]], $[[T3]]
; 64R6: jr $ra
; 64R6: or $3, $[[T13]], $[[T12]]
diff --git a/test/CodeGen/Mips/llvm-ir/call.ll b/test/CodeGen/Mips/llvm-ir/call.ll
index 4cbf43cae28e..112ab8ee8c7f 100644
--- a/test/CodeGen/Mips/llvm-ir/call.ll
+++ b/test/CodeGen/Mips/llvm-ir/call.ll
@@ -3,10 +3,14 @@
; FIXME: We should remove the need for -enable-mips-tail-calls
; RUN: llc -march=mips -mcpu=mips32 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
; RUN: llc -march=mips -mcpu=mips32r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
+; RUN: llc -march=mips -mcpu=mips32r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
+; RUN: llc -march=mips -mcpu=mips32r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
; RUN: llc -march=mips -mcpu=mips32r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32
; RUN: llc -march=mips64 -mcpu=mips4 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
; RUN: llc -march=mips64 -mcpu=mips64 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
+; RUN: llc -march=mips64 -mcpu=mips64r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
+; RUN: llc -march=mips64 -mcpu=mips64r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
; RUN: llc -march=mips64 -mcpu=mips64r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64
declare void @extern_void_void()
diff --git a/test/CodeGen/Mips/llvm-ir/indirectbr.ll b/test/CodeGen/Mips/llvm-ir/indirectbr.ll
index d8fd78774553..debfeb35b213 100644
--- a/test/CodeGen/Mips/llvm-ir/indirectbr.ll
+++ b/test/CodeGen/Mips/llvm-ir/indirectbr.ll
@@ -2,10 +2,14 @@
; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
+; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
+; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6
; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
+; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
+; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6
; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6
define i32 @br(i8 *%addr) {
diff --git a/test/CodeGen/Mips/llvm-ir/lshr.ll b/test/CodeGen/Mips/llvm-ir/lshr.ll
index 59f4330dde6c..3a7029fa5b7a 100644
--- a/test/CodeGen/Mips/llvm-ir/lshr.ll
+++ b/test/CodeGen/Mips/llvm-ir/lshr.ll
@@ -1,30 +1,42 @@
; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32 \
-; RUN: -check-prefix=M2 -check-prefix=NOT-R2-R6
+; RUN: -check-prefix=M2
; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
-; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \
-; RUN: -check-prefix=32R1-R2
+; RUN: -check-prefix=ALL -check-prefix=GP32 \
+; RUN: -check-prefix=32R1-R5
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32 \
-; RUN: -check-prefix=32R1-R2 -check-prefix=R2-R6
+; RUN: -check-prefix=32R1-R5
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32 \
+; RUN: -check-prefix=32R1-R5
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32 \
+; RUN: -check-prefix=32R1-R5
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32 \
-; RUN: -check-prefix=32R6 -check-prefix=R2-R6
+; RUN: -check-prefix=32R6
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64 \
-; RUN: -check-prefix=M3 -check-prefix=NOT-R2-R6
+; RUN: -check-prefix=M3
; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64 \
-; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6
+; RUN: -check-prefix=GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64 \
-; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6
+; RUN: -check-prefix=GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64 \
-; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
+; RUN: -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64 \
+; RUN: -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64 \
+; RUN: -check-prefix=GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64 \
-; RUN: -check-prefix=64R6 -check-prefix=R2-R6
+; RUN: -check-prefix=64R6
define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) {
entry:
@@ -89,16 +101,16 @@ entry:
; M2: jr $ra
; M2: nop
- ; 32R1-R2: srlv $[[T0:[0-9]+]], $5, $7
- ; 32R1-R2: not $[[T1:[0-9]+]], $7
- ; 32R1-R2: sll $[[T2:[0-9]+]], $4, 1
- ; 32R1-R2: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
- ; 32R1-R2: or $3, $[[T3]], $[[T0]]
- ; 32R1-R2: srlv $[[T4:[0-9]+]], $4, $7
- ; 32R1-R2: andi $[[T5:[0-9]+]], $7, 32
- ; 32R1-R2: movn $3, $[[T4]], $[[T5]]
- ; 32R1-R2: jr $ra
- ; 32R1-R2: movn $2, $zero, $[[T5]]
+ ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7
+ ; 32R1-R5: not $[[T1:[0-9]+]], $7
+ ; 32R1-R5: sll $[[T2:[0-9]+]], $4, 1
+ ; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+ ; 32R1-R5: or $3, $[[T3]], $[[T0]]
+ ; 32R1-R5: srlv $[[T4:[0-9]+]], $4, $7
+ ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32
+ ; 32R1-R5: movn $3, $[[T4]], $[[T5]]
+ ; 32R1-R5: jr $ra
+ ; 32R1-R5: movn $2, $zero, $[[T5]]
; 32R6: srlv $[[T0:[0-9]+]], $5, $7
; 32R6: not $[[T1:[0-9]+]], $7
@@ -113,8 +125,7 @@ entry:
; 32R6: jr $ra
; 32R6: seleqz $2, $[[T7]], $[[T5]]
- ; GP64: sll $[[T0:[0-9]+]], $5, 0
- ; GP64: dsrlv $2, $4, $[[T0]]
+ ; GP64: dsrlv $2, $4, $5
%r = lshr i64 %a, %b
ret i64 %r
@@ -127,11 +138,11 @@ entry:
; GP32: lw $25, %call16(__lshrti3)($gp)
; M3: sll $[[T0:[0-9]+]], $7, 0
- ; M3: dsrlv $[[T1:[0-9]+]], $4, $[[T0]]
+ ; M3: dsrlv $[[T1:[0-9]+]], $4, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
; M3: move $3, $[[T1]]
- ; M3: dsrlv $[[T4:[0-9]+]], $5, $[[T0]]
+ ; M3: dsrlv $[[T4:[0-9]+]], $5, $7
; M3: dsll $[[T5:[0-9]+]], $4, 1
; M3: not $[[T6:[0-9]+]], $[[T0]]
; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
@@ -144,32 +155,32 @@ entry:
; M3: jr $ra
; M3: nop
- ; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0
- ; GP64-NOT-R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]]
- ; GP64-NOT-R6: dsll $[[T2:[0-9]+]], $4, 1
- ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]]
- ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
- ; GP64-NOT-R6: or $3, $[[T4]], $[[T1]]
- ; GP64-NOT-R6: dsrlv $2, $4, $[[T0]]
- ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 64
+ ; GP64-NOT-R6: dsrlv $[[T0:[0-9]+]], $5, $7
+ ; GP64-NOT-R6: dsll $[[T1:[0-9]+]], $4, 1
+ ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0
+ ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]]
+ ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
+ ; GP64-NOT-R6: or $3, $[[T4]], $[[T0]]
+ ; GP64-NOT-R6: dsrlv $2, $4, $7
+ ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64
; GP64-NOT-R6: movn $3, $2, $[[T5]]
; GP64-NOT-R6: jr $ra
; GP64-NOT-R6: movn $2, $zero, $1
- ; 64R6: sll $[[T0:[0-9]+]], $7, 0
- ; 64R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]]
- ; 64R6: dsll $[[T2:[0-9]+]], $4, 1
- ; 64R6: not $[[T3:[0-9]+]], $[[T0]]
- ; 64R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
- ; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T1]]
- ; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 64
+ ; 64R6: dsrlv $[[T0:[0-9]+]], $5, $7
+ ; 64R6: dsll $[[T1:[0-9]+]], $4, 1
+ ; 64R6: sll $[[T2:[0-9]+]], $7, 0
+ ; 64R6: not $[[T3:[0-9]+]], $[[T2]]
+ ; 64R6: dsllv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
+ ; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T0]]
+ ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 64
; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0
; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]]
- ; 64R6: dsrlv $[[T9:[0-9]+]], $4, $[[T0]]
+ ; 64R6: dsrlv $[[T9:[0-9]+]], $4, $7
; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]]
; 64R6: or $3, $[[T10]], $[[T8]]
; 64R6: jr $ra
- ; 64R6: seleqz $2, $[[T0]], $[[T7]]
+ ; 64R6: seleqz $2, $[[T9]], $[[T7]]
%r = lshr i128 %a, %b
ret i128 %r
diff --git a/test/CodeGen/Mips/llvm-ir/mul.ll b/test/CodeGen/Mips/llvm-ir/mul.ll
index 5f7f338c7789..a7582805dd74 100644
--- a/test/CodeGen/Mips/llvm-ir/mul.ll
+++ b/test/CodeGen/Mips/llvm-ir/mul.ll
@@ -1,17 +1,25 @@
; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL \
; RUN: -check-prefix=M2 -check-prefix=GP32
; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=ALL \
-; RUN: -check-prefix=32R1-R2 -check-prefix=GP32
+; RUN: -check-prefix=32R1-R5 -check-prefix=GP32
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL \
-; RUN: -check-prefix=32R1-R2 -check-prefix=32R2 -check-prefix=GP32
+; RUN: -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=ALL \
+; RUN: -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=ALL \
+; RUN: -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL \
; RUN: -check-prefix=32R6 -check-prefix=GP32
; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL \
; RUN: -check-prefix=M4 -check-prefix=GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL \
-; RUN: -check-prefix=64R1-R2 -check-prefix=GP64-NOT-R6
+; RUN: -check-prefix=64R1-R5 -check-prefix=GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL \
-; RUN: -check-prefix=64R1-R2 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
+; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefix=ALL \
+; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefix=ALL \
+; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL \
; RUN: -check-prefix=64R6
@@ -24,9 +32,9 @@ entry:
; M2: sll $[[T0]], $[[T0]], 31
; M2: sra $2, $[[T0]], 31
- ; 32R1-R2: mul $[[T0:[0-9]+]], $4, $5
- ; 32R1-R2: sll $[[T0]], $[[T0]], 31
- ; 32R1-R2: sra $2, $[[T0]], 31
+ ; 32R1-R5: mul $[[T0:[0-9]+]], $4, $5
+ ; 32R1-R5: sll $[[T0]], $[[T0]], 31
+ ; 32R1-R5: sra $2, $[[T0]], 31
; 32R6: mul $[[T0:[0-9]+]], $4, $5
; 32R6: sll $[[T0]], $[[T0]], 31
@@ -37,9 +45,9 @@ entry:
; M4: sll $[[T0]], $[[T0]], 31
; M4: sra $2, $[[T0]], 31
- ; 64R1-R2: mul $[[T0:[0-9]+]], $4, $5
- ; 64R1-R2: sll $[[T0]], $[[T0]], 31
- ; 64R1-R2: sra $2, $[[T0]], 31
+ ; 64R1-R5: mul $[[T0:[0-9]+]], $4, $5
+ ; 64R1-R5: sll $[[T0]], $[[T0]], 31
+ ; 64R1-R5: sra $2, $[[T0]], 31
; 64R6: mul $[[T0:[0-9]+]], $4, $5
; 64R6: sll $[[T0]], $[[T0]], 31
@@ -62,8 +70,8 @@ entry:
; 32R1: sll $[[T0]], $[[T0]], 24
; 32R1: sra $2, $[[T0]], 24
- ; 32R2: mul $[[T0:[0-9]+]], $4, $5
- ; 32R2: seb $2, $[[T0]]
+ ; 32R2-R5: mul $[[T0:[0-9]+]], $4, $5
+ ; 32R2-R5: seb $2, $[[T0]]
; 32R6: mul $[[T0:[0-9]+]], $4, $5
; 32R6: seb $2, $[[T0]]
@@ -99,8 +107,8 @@ entry:
; 32R1: sll $[[T0]], $[[T0]], 16
; 32R1: sra $2, $[[T0]], 16
- ; 32R2: mul $[[T0:[0-9]+]], $4, $5
- ; 32R2: seh $2, $[[T0]]
+ ; 32R2-R5: mul $[[T0:[0-9]+]], $4, $5
+ ; 32R2-R5: seh $2, $[[T0]]
; 32R6: mul $[[T0:[0-9]+]], $4, $5
; 32R6: seh $2, $[[T0]]
@@ -130,10 +138,10 @@ entry:
; M2: mult $4, $5
; M2: mflo $2
- ; 32R1-R2: mul $2, $4, $5
+ ; 32R1-R5: mul $2, $4, $5
; 32R6: mul $2, $4, $5
- ; 64R1-R2: mul $2, $4, $5
+ ; 64R1-R5: mul $2, $4, $5
; 64R6: mul $2, $4, $5
%r = mul i32 %a, %b
ret i32 %r
@@ -153,13 +161,13 @@ entry:
; M2: addu $[[T2:[0-9]+]], $4, $[[T1]]
; M2: addu $2, $[[T2]], $[[T0]]
- ; 32R1-R2: multu $5, $7
- ; 32R1-R2: mflo $3
- ; 32R1-R2: mfhi $[[T0:[0-9]+]]
- ; 32R1-R2: mul $[[T1:[0-9]+]], $4, $7
- ; 32R1-R2: mul $[[T2:[0-9]+]], $5, $6
- ; 32R1-R2: addu $[[T0]], $[[T0]], $[[T2:[0-9]+]]
- ; 32R1-R2: addu $2, $[[T0]], $[[T1]]
+ ; 32R1-R5: multu $5, $7
+ ; 32R1-R5: mflo $3
+ ; 32R1-R5: mfhi $[[T0:[0-9]+]]
+ ; 32R1-R5: mul $[[T1:[0-9]+]], $4, $7
+ ; 32R1-R5: mul $[[T2:[0-9]+]], $5, $6
+ ; 32R1-R5: addu $[[T0]], $[[T0]], $[[T2:[0-9]+]]
+ ; 32R1-R5: addu $2, $[[T0]], $[[T1]]
; 32R6: mul $[[T0:[0-9]+]], $5, $6
; 32R6: muhu $[[T1:[0-9]+]], $5, $7
@@ -171,8 +179,8 @@ entry:
; M4: dmult $4, $5
; M4: mflo $2
- ; 64R1-R2: dmult $4, $5
- ; 64R1-R2: mflo $2
+ ; 64R1-R5: dmult $4, $5
+ ; 64R1-R5: mflo $2
; 64R6: dmul $2, $4, $5
diff --git a/test/CodeGen/Mips/llvm-ir/or.ll b/test/CodeGen/Mips/llvm-ir/or.ll
index 21d1d4fca2a3..6215e4036325 100644
--- a/test/CodeGen/Mips/llvm-ir/or.ll
+++ b/test/CodeGen/Mips/llvm-ir/or.ll
@@ -4,6 +4,10 @@
; RUN: -check-prefix=ALL -check-prefix=GP32
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -14,6 +18,10 @@
; RUN: -check-prefix=ALL -check-prefix=GP64
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64
@@ -51,11 +59,7 @@ define signext i32 @or_i32(i32 signext %a, i32 signext %b) {
entry:
; ALL-LABEL: or_i32:
- ; GP32: or $2, $4, $5
-
- ; GP64: or $[[T0:[0-9]+]], $4, $5
- ; FIXME: The sll instruction below is redundant.
- ; GP64: sll $2, $[[T0]], 0
+ ; ALL: or $2, $4, $5
%r = or i32 %a, %b
ret i32 %r
diff --git a/test/CodeGen/Mips/llvm-ir/ret.ll b/test/CodeGen/Mips/llvm-ir/ret.ll
index 8f5b1159760c..0561c24219ce 100644
--- a/test/CodeGen/Mips/llvm-ir/ret.ll
+++ b/test/CodeGen/Mips/llvm-ir/ret.ll
@@ -9,10 +9,14 @@
; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NO-MTHC1 -check-prefix=NOT-R6
; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6
; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=R6
; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
+; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6
; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=R6
define void @ret_void() {
diff --git a/test/CodeGen/Mips/llvm-ir/sdiv.ll b/test/CodeGen/Mips/llvm-ir/sdiv.ll
index 54b7f70b1dac..929ee88bb7f7 100644
--- a/test/CodeGen/Mips/llvm-ir/sdiv.ll
+++ b/test/CodeGen/Mips/llvm-ir/sdiv.ll
@@ -3,7 +3,11 @@
; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP32
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
-; RUN: -check-prefix=NOT-R6 -check-prefix=R2 -check-prefix=GP32
+; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefix=R6 -check-prefix=GP32
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -13,7 +17,11 @@
; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
-; RUN: -check-prefix=NOT-R6 -check-prefix=R2 -check-prefix=GP64-NOT-R6
+; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=R6 -check-prefix=64R6
@@ -49,11 +57,11 @@ entry:
; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 24
; NOT-R2-R6: sra $2, $[[T1]], 24
- ; R2: div $zero, $4, $5
- ; R2: teq $5, $zero, 7
- ; R2: mflo $[[T0:[0-9]+]]
+ ; R2-R5: div $zero, $4, $5
+ ; R2-R5: teq $5, $zero, 7
+ ; R2-R5: mflo $[[T0:[0-9]+]]
; FIXME: This instruction is redundant.
- ; R2: seb $2, $[[T0]]
+ ; R2-R5: seb $2, $[[T0]]
; R6: div $[[T0:[0-9]+]], $4, $5
; R6: teq $5, $zero, 7
@@ -75,11 +83,11 @@ entry:
; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 16
; NOT-R2-R6: sra $2, $[[T1]], 16
- ; R2: div $zero, $4, $5
- ; R2: teq $5, $zero, 7
- ; R2: mflo $[[T0:[0-9]+]]
+ ; R2-R5: div $zero, $4, $5
+ ; R2-R5: teq $5, $zero, 7
+ ; R2-R5: mflo $[[T0:[0-9]+]]
; FIXME: This is instruction is redundant since div is signed.
- ; R2: seh $2, $[[T0]]
+ ; R2-R5: seh $2, $[[T0]]
; R6: div $[[T0:[0-9]+]], $4, $5
; R6: teq $5, $zero, 7
diff --git a/test/CodeGen/Mips/llvm-ir/select.ll b/test/CodeGen/Mips/llvm-ir/select.ll
index 736bc579088d..f17670adca33 100644
--- a/test/CodeGen/Mips/llvm-ir/select.ll
+++ b/test/CodeGen/Mips/llvm-ir/select.ll
@@ -5,7 +5,13 @@
; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R1
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=CMOV \
-; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2
+; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=CMOV \
+; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=CMOV \
+; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -16,6 +22,10 @@
; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
@@ -232,12 +242,12 @@ entry:
; M2: jr $ra
; M2: mtc1 $6, $f1
- ; CMOV-32: mtc1 $7, $[[F0:f[0-9]+]]
- ; CMOV-32R1: mtc1 $6, $f{{[0-9]+}}
- ; CMOV-32R2 mthc1 $6, $[[F0]]
- ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
- ; CMOV-32: ldc1 $f0, 16($sp)
- ; CMOV-32: movn.d $f0, $[[F0]], $[[T0]]
+ ; CMOV-32: mtc1 $7, $[[F0:f[0-9]+]]
+ ; CMOV-32R1: mtc1 $6, $f{{[0-9]+}}
+ ; CMOV-32R2-R5: mthc1 $6, $[[F0]]
+ ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
+ ; CMOV-32: ldc1 $f0, 16($sp)
+ ; CMOV-32: movn.d $f0, $[[F0]], $[[T0]]
; SEL-32: mtc1 $7, $[[F0:f[0-9]+]]
; SEL-32: mthc1 $6, $[[F0]]
diff --git a/test/CodeGen/Mips/llvm-ir/shl.ll b/test/CodeGen/Mips/llvm-ir/shl.ll
index fc5243cc97f2..bba34c47ea82 100644
--- a/test/CodeGen/Mips/llvm-ir/shl.ll
+++ b/test/CodeGen/Mips/llvm-ir/shl.ll
@@ -3,10 +3,16 @@
; RUN: -check-prefix=M2 -check-prefix=NOT-R2-R6
; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \
-; RUN: -check-prefix=32R1-R2
+; RUN: -check-prefix=32R1-R5
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32 \
-; RUN: -check-prefix=32R1-R2 -check-prefix=R2-R6
+; RUN: -check-prefix=32R1-R5 -check-prefix=R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32 \
+; RUN: -check-prefix=32R1-R5 -check-prefix=R2-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32 \
+; RUN: -check-prefix=32R1-R5 -check-prefix=R2-R6
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32 \
; RUN: -check-prefix=32R6 -check-prefix=R2-R6
@@ -22,6 +28,12 @@
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64 \
; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64 \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64 \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64 \
; RUN: -check-prefix=64R6 -check-prefix=R2-R6
@@ -101,16 +113,16 @@ entry:
; M2: jr $ra
; M2: nop
- ; 32R1-R2: sllv $[[T0:[0-9]+]], $4, $7
- ; 32R1-R2: not $[[T1:[0-9]+]], $7
- ; 32R1-R2: srl $[[T2:[0-9]+]], $5, 1
- ; 32R1-R2: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
- ; 32R1-R2: or $2, $[[T0]], $[[T3]]
- ; 32R1-R2: sllv $[[T4:[0-9]+]], $5, $7
- ; 32R1-R2: andi $[[T5:[0-9]+]], $7, 32
- ; 32R1-R2: movn $2, $[[T4]], $[[T5]]
- ; 32R1-R2: jr $ra
- ; 32R1-R2: movn $3, $zero, $[[T5]]
+ ; 32R1-R5: sllv $[[T0:[0-9]+]], $4, $7
+ ; 32R1-R5: not $[[T1:[0-9]+]], $7
+ ; 32R1-R5: srl $[[T2:[0-9]+]], $5, 1
+ ; 32R1-R5: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+ ; 32R1-R5: or $2, $[[T0]], $[[T3]]
+ ; 32R1-R5: sllv $[[T4:[0-9]+]], $5, $7
+ ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32
+ ; 32R1-R5: movn $2, $[[T4]], $[[T5]]
+ ; 32R1-R5: jr $ra
+ ; 32R1-R5: movn $3, $zero, $[[T5]]
; 32R6: sllv $[[T0:[0-9]+]], $4, $7
; 32R6: not $[[T1:[0-9]+]], $7
@@ -125,8 +137,7 @@ entry:
; 32R6: jr $ra
; 32R6: seleqz $3, $[[T7]], $[[T5]]
- ; GP64: sll $[[T0:[0-9]+]], $5, 0
- ; GP64: dsllv $2, $4, $1
+ ; GP64: dsllv $2, $4, $5
%r = shl i64 %a, %b
ret i64 %r
@@ -139,11 +150,11 @@ entry:
; GP32: lw $25, %call16(__ashlti3)($gp)
; M3: sll $[[T0:[0-9]+]], $7, 0
- ; M3: dsllv $[[T1:[0-9]+]], $5, $[[T0]]
+ ; M3: dsllv $[[T1:[0-9]+]], $5, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
; M3: move $2, $[[T1]]
- ; M3: dsllv $[[T4:[0-9]+]], $4, $[[T0]]
+ ; M3: dsllv $[[T4:[0-9]+]], $4, $7
; M3: dsrl $[[T5:[0-9]+]], $5, 1
; M3: not $[[T6:[0-9]+]], $[[T0]]
; M3: dsrlv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
@@ -156,32 +167,32 @@ entry:
; M3: jr $ra
; M3: nop
- ; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0
- ; GP64-NOT-R6: dsllv $[[T1:[0-9]+]], $4, $[[T0]]
- ; GP64-NOT-R6: dsrl $[[T2:[0-9]+]], $5, 1
- ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]]
- ; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
- ; GP64-NOT-R6: or $2, $[[T1]], $[[T4]]
- ; GP64-NOT-R6: dsllv $3, $5, $[[T0]]
- ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 64
+ ; GP64-NOT-R6: dsllv $[[T0:[0-9]+]], $4, $7
+ ; GP64-NOT-R6: dsrl $[[T1:[0-9]+]], $5, 1
+ ; GP64-NOT-R6: sll $[[T2:[0-9]+]], $7, 0
+ ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T2]]
+ ; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
+ ; GP64-NOT-R6: or $2, $[[T0]], $[[T4]]
+ ; GP64-NOT-R6: dsllv $3, $5, $7
+ ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64
; GP64-NOT-R6: movn $2, $3, $[[T5]]
; GP64-NOT-R6: jr $ra
; GP64-NOT-R6: movn $3, $zero, $1
- ; 64R6: sll $[[T0:[0-9]+]], $7, 0
- ; 64R6: dsllv $[[T1:[0-9]+]], $4, $[[T0]]
- ; 64R6: dsrl $[[T2:[0-9]+]], $5, 1
- ; 64R6: not $[[T3:[0-9]+]], $[[T0]]
- ; 64R6: dsrlv $[[T4:[0-9]+]], $[[T2]], $[[T3]]
- ; 64R6: or $[[T5:[0-9]+]], $[[T1]], $[[T4]]
- ; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 64
+ ; 64R6: dsllv $[[T0:[0-9]+]], $4, $7
+ ; 64R6: dsrl $[[T1:[0-9]+]], $5, 1
+ ; 64R6: sll $[[T2:[0-9]+]], $7, 0
+ ; 64R6: not $[[T3:[0-9]+]], $[[T2]]
+ ; 64R6: dsrlv $[[T4:[0-9]+]], $[[T1]], $[[T3]]
+ ; 64R6: or $[[T5:[0-9]+]], $[[T0]], $[[T4]]
+ ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 64
; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0
; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]]
- ; 64R6: dsllv $[[T9:[0-9]+]], $5, $[[T0]]
+ ; 64R6: dsllv $[[T9:[0-9]+]], $5, $7
; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]]
; 64R6: or $2, $[[T10]], $[[T8]]
; 64R6: jr $ra
- ; 64R6: seleqz $3, $[[T0]], $[[T7]]
+ ; 64R6: seleqz $3, $[[T9]], $[[T7]]
%r = shl i128 %a, %b
ret i128 %r
diff --git a/test/CodeGen/Mips/llvm-ir/srem.ll b/test/CodeGen/Mips/llvm-ir/srem.ll
index 1e949d24678b..ceb53ee7033a 100644
--- a/test/CodeGen/Mips/llvm-ir/srem.ll
+++ b/test/CodeGen/Mips/llvm-ir/srem.ll
@@ -3,7 +3,11 @@
; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \
-; RUN: -check-prefix=R2 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=GP32 \
+; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=GP32 \
+; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -13,7 +17,13 @@
; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
-; RUN: -check-prefix=R2 -check-prefix=R2-R6 \
+; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \
; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6
@@ -47,10 +57,10 @@ entry:
; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 24
; NOT-R2-R6: sra $2, $[[T1]], 24
- ; R2: div $zero, $4, $5
- ; R2: teq $5, $zero, 7
- ; R2: mfhi $[[T0:[0-9]+]]
- ; R2: seb $2, $[[T0]]
+ ; R2-R5: div $zero, $4, $5
+ ; R2-R5: teq $5, $zero, 7
+ ; R2-R5: mfhi $[[T0:[0-9]+]]
+ ; R2-R5: seb $2, $[[T0]]
; R6: mod $[[T0:[0-9]+]], $4, $5
; R6: teq $5, $zero, 7
@@ -70,10 +80,10 @@ entry:
; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 16
; NOT-R2-R6: sra $2, $[[T1]], 16
- ; R2: div $zero, $4, $5
- ; R2: teq $5, $zero, 7
- ; R2: mfhi $[[T0:[0-9]+]]
- ; R2: seh $2, $[[T1]]
+ ; R2-R5: div $zero, $4, $5
+ ; R2-R5: teq $5, $zero, 7
+ ; R2-R5: mfhi $[[T0:[0-9]+]]
+ ; R2-R5: seh $2, $[[T1]]
; R6: mod $[[T0:[0-9]+]], $4, $5
; R6: teq $5, $zero, 7
diff --git a/test/CodeGen/Mips/llvm-ir/sub.ll b/test/CodeGen/Mips/llvm-ir/sub.ll
index 6d592be38211..164975844d73 100644
--- a/test/CodeGen/Mips/llvm-ir/sub.ll
+++ b/test/CodeGen/Mips/llvm-ir/sub.ll
@@ -4,6 +4,10 @@
; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -14,6 +18,10 @@
; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
diff --git a/test/CodeGen/Mips/llvm-ir/udiv.ll b/test/CodeGen/Mips/llvm-ir/udiv.ll
index 1f7aa0d5f4ce..a7cafe52d1ac 100644
--- a/test/CodeGen/Mips/llvm-ir/udiv.ll
+++ b/test/CodeGen/Mips/llvm-ir/udiv.ll
@@ -4,6 +4,10 @@
; RUN: -check-prefix=NOT-R6 -check-prefix=GP32
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
; RUN: -check-prefix=NOT-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN: -check-prefix=NOT-R6 -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN: -check-prefix=NOT-R6 -check-prefix=GP32
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefix=R6 -check-prefix=GP32
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -14,6 +18,10 @@
; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=R6 -check-prefix=64R6
diff --git a/test/CodeGen/Mips/llvm-ir/urem.ll b/test/CodeGen/Mips/llvm-ir/urem.ll
index 73235341a42f..d5a231c8dfca 100644
--- a/test/CodeGen/Mips/llvm-ir/urem.ll
+++ b/test/CodeGen/Mips/llvm-ir/urem.ll
@@ -3,7 +3,11 @@
; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \
-; RUN: -check-prefix=R2 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=GP32 \
+; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=GP32 \
+; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -13,7 +17,13 @@
; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
-; RUN: -check-prefix=R2 -check-prefix=R2-R6 \
+; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \
+; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \
; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6
@@ -53,12 +63,12 @@ entry:
; NOT-R2-R6: sll $[[T3:[0-9]+]], $[[T2]], 24
; NOT-R2-R6: sra $2, $[[T3]], 24
- ; R2: andi $[[T0:[0-9]+]], $5, 255
- ; R2: andi $[[T1:[0-9]+]], $4, 255
- ; R2: divu $zero, $[[T1]], $[[T0]]
- ; R2: teq $[[T0]], $zero, 7
- ; R2: mfhi $[[T2:[0-9]+]]
- ; R2: seb $2, $[[T2]]
+ ; R2-R5: andi $[[T0:[0-9]+]], $5, 255
+ ; R2-R5: andi $[[T1:[0-9]+]], $4, 255
+ ; R2-R5: divu $zero, $[[T1]], $[[T0]]
+ ; R2-R5: teq $[[T0]], $zero, 7
+ ; R2-R5: mfhi $[[T2:[0-9]+]]
+ ; R2-R5: seb $2, $[[T2]]
; R6: andi $[[T0:[0-9]+]], $5, 255
; R6: andi $[[T1:[0-9]+]], $4, 255
@@ -82,12 +92,12 @@ entry:
; NOT-R2-R6: sll $[[T3:[0-9]+]], $[[T2]], 16
; NOT-R2-R6: sra $2, $[[T3]], 16
- ; R2: andi $[[T0:[0-9]+]], $5, 65535
- ; R2: andi $[[T1:[0-9]+]], $4, 65535
- ; R2: divu $zero, $[[T1]], $[[T0]]
- ; R2: teq $[[T0]], $zero, 7
- ; R2: mfhi $[[T3:[0-9]+]]
- ; R2: seh $2, $[[T2]]
+ ; R2-R5: andi $[[T0:[0-9]+]], $5, 65535
+ ; R2-R5: andi $[[T1:[0-9]+]], $4, 65535
+ ; R2-R5: divu $zero, $[[T1]], $[[T0]]
+ ; R2-R5: teq $[[T0]], $zero, 7
+ ; R2-R5: mfhi $[[T3:[0-9]+]]
+ ; R2-R5: seh $2, $[[T2]]
; R6: andi $[[T0:[0-9]+]], $5, 65535
; R6: andi $[[T1:[0-9]+]], $4, 65535
diff --git a/test/CodeGen/Mips/llvm-ir/xor.ll b/test/CodeGen/Mips/llvm-ir/xor.ll
index 94dead1eff41..89af99981a3c 100644
--- a/test/CodeGen/Mips/llvm-ir/xor.ll
+++ b/test/CodeGen/Mips/llvm-ir/xor.ll
@@ -4,6 +4,10 @@
; RUN: -check-prefix=ALL -check-prefix=GP32
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32
+; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP32
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP32
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
@@ -14,6 +18,10 @@
; RUN: -check-prefix=ALL -check-prefix=GP64
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64
+; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=GP64
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=GP64
@@ -51,10 +59,7 @@ define signext i32 @xor_i32(i32 signext %a, i32 signext %b) {
entry:
; ALL-LABEL: xor_i32:
- ; GP32: xor $2, $4, $5
-
- ; GP64: xor $[[T0:[0-9]+]], $4, $5
- ; GP64: sll $2, $[[T0]], 0
+ ; ALL: xor $2, $4, $5
%r = xor i32 %a, %b
ret i32 %r
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-13 13:07:17 +0000