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-rw-r--r--test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir20
1 files changed, 3 insertions, 17 deletions
diff --git a/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir b/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
index d73503223aa8..8cffc86373a3 100644
--- a/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
+++ b/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
@@ -1,4 +1,4 @@
-# RUN: not llc -march=amdgcn -mcpu=SI -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
@@ -6,7 +6,7 @@
@float_gv = internal unnamed_addr addrspace(2) constant [5 x float] [float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00], align 4
- define void @float(float addrspace(1)* %out, i32 %index) #0 {
+ define amdgpu_kernel void @float(float addrspace(1)* %out, i32 %index) #0 {
entry:
%0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index
%1 = load float, float addrspace(2)* %0
@@ -14,21 +14,7 @@
ret void
}
- declare { i1, i64 } @llvm.SI.if(i1)
-
- declare { i1, i64 } @llvm.SI.else(i64)
-
- declare i64 @llvm.SI.break(i64)
-
- declare i64 @llvm.SI.if.break(i1, i64)
-
- declare i64 @llvm.SI.else.break(i64, i64)
-
- declare i1 @llvm.SI.loop(i64)
-
- declare void @llvm.SI.end.cf(i64)
-
- attributes #0 = { "target-cpu"="SI" }
+ attributes #0 = { nounwind }
...
---