diff options
Diffstat (limited to 'test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir')
| -rw-r--r-- | test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir | 115 |
1 files changed, 108 insertions, 7 deletions
diff --git a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir index 72c3b715d36e..16642d85d9cf 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir @@ -28,6 +28,10 @@ define void @test_sdiv_s32() #2 { ret void } define void @test_udiv_s32() #2 { ret void } + define void @test_and_s32() { ret void } + define void @test_or_s32() { ret void } + define void @test_xor_s32() { ret void } + define void @test_load_from_stack() { ret void } define void @test_load_f32() #0 { ret void } define void @test_load_f64() #0 { ret void } @@ -783,6 +787,105 @@ body: | ; CHECK: BX_RET 14, _, implicit %r0 ... --- +name: test_and_s32 +# CHECK-LABEL: name: test_and_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: gprb } + - { id: 1, class: gprb } + - { id: 2, class: gprb } +# CHECK: id: 0, class: gpr +# CHECK: id: 1, class: gpr +# CHECK: id: 2, class: gpr +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0 + + %1(s32) = COPY %r1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1 + + %2(s32) = G_AND %0, %1 + ; CHECK: [[VREGRES:%[0-9]+]] = ANDrr [[VREGX]], [[VREGY]], 14, _ + + %r0 = COPY %2(s32) + ; CHECK: %r0 = COPY [[VREGRES]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_or_s32 +# CHECK-LABEL: name: test_or_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: gprb } + - { id: 1, class: gprb } + - { id: 2, class: gprb } +# CHECK: id: 0, class: gpr +# CHECK: id: 1, class: gpr +# CHECK: id: 2, class: gpr +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0 + + %1(s32) = COPY %r1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1 + + %2(s32) = G_OR %0, %1 + ; CHECK: [[VREGRES:%[0-9]+]] = ORRrr [[VREGX]], [[VREGY]], 14, _ + + %r0 = COPY %2(s32) + ; CHECK: %r0 = COPY [[VREGRES]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- +name: test_xor_s32 +# CHECK-LABEL: name: test_xor_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: gprb } + - { id: 1, class: gprb } + - { id: 2, class: gprb } +# CHECK: id: 0, class: gpr +# CHECK: id: 1, class: gpr +# CHECK: id: 2, class: gpr +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0 + + %1(s32) = COPY %r1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1 + + %2(s32) = G_XOR %0, %1 + ; CHECK: [[VREGRES:%[0-9]+]] = EORrr [[VREGX]], [[VREGY]], 14, _ + + %r0 = COPY %2(s32) + ; CHECK: %r0 = COPY [[VREGRES]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- name: test_load_from_stack # CHECK-LABEL: name: test_load_from_stack legalized: true @@ -802,8 +905,8 @@ fixedStack: - { id: 0, offset: 0, size: 1, alignment: 4, isImmutable: true, isAliased: false } - { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false } - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false } -# CHECK-DAG: id: [[FI1:[0-9]+]], offset: 0 -# CHECK-DAG: id: [[FI32:[0-9]+]], offset: 8 +# CHECK-DAG: id: [[FI1:[0-9]+]], type: default, offset: 0, size: 1 +# CHECK-DAG: id: [[FI32:[0-9]+]], type: default, offset: 8 body: | bb.0: liveins: %r0, %r1, %r2, %r3 @@ -1024,13 +1127,11 @@ body: | %1(s32) = COPY %r3 ; CHECK: [[IN2:%[0-9]+]] = COPY %r3 - %2(s64) = G_SEQUENCE %0(s32), 0, %1(s32), 1 + %2(s64) = G_MERGE_VALUES %0(s32), %1(s32) ; CHECK: %[[DREG]] = VMOVDRR [[IN1]], [[IN2]] - %3(s32) = G_EXTRACT %2(s64), 0 - %4(s32) = G_EXTRACT %2(s64), 32 - ; CHECK: [[OUT1:%[0-9]+]] = VGETLNi32 %[[DREG]], 0 - ; CHECK: [[OUT2:%[0-9]+]] = VGETLNi32 %[[DREG]], 1 + %3(s32), %4(s32) = G_UNMERGE_VALUES %2(s64) + ; CHECK: [[OUT1:%[0-9]+]], [[OUT2:%[0-9]+]] = VMOVRRD %[[DREG]] %r0 = COPY %3 ; CHECK: %r0 = COPY [[OUT1]] |