diff options
Diffstat (limited to 'test/CodeGen/AMDGPU/vselect.ll')
| -rw-r--r-- | test/CodeGen/AMDGPU/vselect.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/test/CodeGen/AMDGPU/vselect.ll b/test/CodeGen/AMDGPU/vselect.ll index fe5be7526b19..bb6234729f90 100644 --- a/test/CodeGen/AMDGPU/vselect.ll +++ b/test/CodeGen/AMDGPU/vselect.ll @@ -10,7 +10,7 @@ ; SI: v_cndmask_b32_e64 ; SI: v_cndmask_b32_e32 -define void @test_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1, <2 x i32> %val) { +define amdgpu_kernel void @test_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1, <2 x i32> %val) { entry: %load0 = load <2 x i32>, <2 x i32> addrspace(1)* %in0 %load1 = load <2 x i32>, <2 x i32> addrspace(1)* %in1 @@ -28,7 +28,7 @@ entry: ;SI: v_cndmask_b32_e64 ;SI: v_cndmask_b32_e32 -define void @test_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in0, <2 x float> addrspace(1)* %in1) { +define amdgpu_kernel void @test_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in0, <2 x float> addrspace(1)* %in1) { entry: %0 = load <2 x float>, <2 x float> addrspace(1)* %in0 %1 = load <2 x float>, <2 x float> addrspace(1)* %in1 @@ -52,7 +52,7 @@ entry: ; SI: v_cndmask_b32 ; SI: v_cndmask_b32 -define void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1, <4 x i32> %val) { +define amdgpu_kernel void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1, <4 x i32> %val) { entry: %load0 = load <4 x i32>, <4 x i32> addrspace(1)* %in0 %load1 = load <4 x i32>, <4 x i32> addrspace(1)* %in1 @@ -68,7 +68,7 @@ entry: ;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @test_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in0, <4 x float> addrspace(1)* %in1) { +define amdgpu_kernel void @test_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in0, <4 x float> addrspace(1)* %in1) { entry: %0 = load <4 x float>, <4 x float> addrspace(1)* %in0 %1 = load <4 x float>, <4 x float> addrspace(1)* %in1 |