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-rw-r--r--sys/arm/arm/cpuinfo.c48
-rw-r--r--sys/arm/arm/identcpu-v6.c53
-rw-r--r--sys/arm/arm/mp_machdep.c4
-rw-r--r--sys/arm/arm/pmap-v6.c9
-rw-r--r--sys/arm/arm/syscall.c11
-rw-r--r--sys/arm/cloudabi32/cloudabi32_sysvec.c8
-rw-r--r--sys/arm/conf/ARMADA38X1
-rw-r--r--sys/arm/include/cpuinfo.h4
-rw-r--r--sys/arm/include/pmap-v6.h1
-rw-r--r--sys/arm/mv/armada38x/armada38x.c28
-rw-r--r--sys/arm/mv/armadaxp/armadaxp.c7
-rw-r--r--sys/arm/mv/discovery/discovery.c7
-rw-r--r--sys/arm/mv/files.mv2
-rw-r--r--sys/arm/mv/kirkwood/kirkwood.c7
-rw-r--r--sys/arm/mv/mpic.c33
-rw-r--r--sys/arm/mv/mv_common.c25
-rw-r--r--sys/arm/mv/mvreg.h3
-rw-r--r--sys/arm/mv/mvvar.h1
-rw-r--r--sys/arm/mv/mvwin.h4
-rw-r--r--sys/arm/mv/orion/orion.c7
20 files changed, 225 insertions, 38 deletions
diff --git a/sys/arm/arm/cpuinfo.c b/sys/arm/arm/cpuinfo.c
index 3cb013cb2faf..4b4b67ed7d89 100644
--- a/sys/arm/arm/cpuinfo.c
+++ b/sys/arm/arm/cpuinfo.c
@@ -30,10 +30,15 @@ __FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
+#include <sys/sysctl.h>
#include <machine/cpu.h>
#include <machine/cpuinfo.h>
+#if __ARM_ARCH >= 6
+void reinit_mmu(uint32_t ttb, uint32_t aux_clr, uint32_t aux_set);
+#endif
+
struct cpuinfo cpuinfo =
{
/* Use safe defaults for start */
@@ -43,6 +48,30 @@ struct cpuinfo cpuinfo =
.icache_line_mask = 31,
};
+static SYSCTL_NODE(_hw, OID_AUTO, cpu, CTLFLAG_RD, 0,
+ "CPU");
+static SYSCTL_NODE(_hw_cpu, OID_AUTO, quirks, CTLFLAG_RD, 0,
+ "CPU quirks");
+
+/*
+ * Tunable CPU quirks.
+ * Be careful, ACTRL cannot be changed if CPU is started in secure
+ * mode(world) and write to ACTRL can cause exception!
+ * These quirks are intended for optimizing CPU performance, not for
+ * applying errata workarounds. Nobody can expect that CPU with unfixed
+ * errata is stable enough to execute the kernel until quirks are applied.
+ */
+static uint32_t cpu_quirks_actlr_mask;
+SYSCTL_INT(_hw_cpu_quirks, OID_AUTO, actlr_mask,
+ CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &cpu_quirks_actlr_mask, 0,
+ "Bits to be masked in ACTLR");
+
+static uint32_t cpu_quirks_actlr_set;
+SYSCTL_INT(_hw_cpu_quirks, OID_AUTO, actlr_set,
+ CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &cpu_quirks_actlr_set, 0,
+ "Bits to be set in ACTLR");
+
+
/* Read and parse CPU id scheme */
void
cpuinfo_init(void)
@@ -155,15 +184,17 @@ cpuinfo_init(void)
#endif
}
+#if __ARM_ARCH >= 6
/*
* Get bits that must be set or cleared in ACLR register.
* Note: Bits in ACLR register are IMPLEMENTATION DEFINED.
* Its expected that SCU is in operational state before this
* function is called.
*/
-void
+static void
cpuinfo_get_actlr_modifier(uint32_t *actlr_mask, uint32_t *actlr_set)
{
+
*actlr_mask = 0;
*actlr_set = 0;
@@ -238,3 +269,18 @@ cpuinfo_get_actlr_modifier(uint32_t *actlr_mask, uint32_t *actlr_set)
return;
}
}
+
+/* Reinitialize MMU to final kernel mapping and apply all CPU quirks. */
+void
+cpuinfo_reinit_mmu(uint32_t ttb)
+{
+ uint32_t actlr_mask;
+ uint32_t actlr_set;
+
+ cpuinfo_get_actlr_modifier(&actlr_mask, &actlr_set);
+ actlr_mask |= cpu_quirks_actlr_mask;
+ actlr_set |= cpu_quirks_actlr_set;
+ reinit_mmu(ttb, actlr_mask, actlr_set);
+}
+
+#endif /* __ARM_ARCH >= 6 */
diff --git a/sys/arm/arm/identcpu-v6.c b/sys/arm/arm/identcpu-v6.c
index 7cc8170325cb..819f8cdb1b50 100644
--- a/sys/arm/arm/identcpu-v6.c
+++ b/sys/arm/arm/identcpu-v6.c
@@ -60,29 +60,47 @@ static char hw_buf[81];
static int hw_buf_idx;
static bool hw_buf_newline;
+enum cpu_class cpu_class = CPU_CLASS_NONE;
+
static struct {
int implementer;
int part_number;
char *impl_name;
char *core_name;
+ enum cpu_class cpu_class;
} cpu_names[] = {
- {CPU_IMPLEMENTER_ARM, CPU_ARCH_ARM1176, "ARM", "ARM1176"},
- {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A5 , "ARM", "Cortex-A5"},
- {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A7 , "ARM", "Cortex-A7"},
- {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A8 , "ARM", "Cortex-A8"},
- {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A9 , "ARM", "Cortex-A9"},
- {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A12, "ARM", "Cortex-A12"},
- {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A15, "ARM", "Cortex-A15"},
- {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A17, "ARM", "Cortex-A17"},
- {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A53, "ARM", "Cortex-A53"},
- {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A57, "ARM", "Cortex-A57"},
- {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A72, "ARM", "Cortex-A72"},
- {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A73, "ARM", "Cortex-A73"},
-
- {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_581, "Marwell", "PJ4 v7"},
- {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_584, "Marwell", "PJ4MP v7"},
-
- {CPU_IMPLEMENTER_QCOM, CPU_ARCH_KRAIT_300, "Qualcomm", "Krait 300"},
+ {CPU_IMPLEMENTER_ARM, CPU_ARCH_ARM1176, "ARM", "ARM1176",
+ CPU_CLASS_ARM11J},
+ {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A5 , "ARM", "Cortex-A5",
+ CPU_CLASS_CORTEXA},
+ {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A7 , "ARM", "Cortex-A7",
+ CPU_CLASS_CORTEXA},
+ {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A8 , "ARM", "Cortex-A8",
+ CPU_CLASS_CORTEXA},
+ {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A9 , "ARM", "Cortex-A9",
+ CPU_CLASS_CORTEXA},
+ {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A12, "ARM", "Cortex-A12",
+ CPU_CLASS_CORTEXA},
+ {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A15, "ARM", "Cortex-A15",
+ CPU_CLASS_CORTEXA},
+ {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A17, "ARM", "Cortex-A17",
+ CPU_CLASS_CORTEXA},
+ {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A53, "ARM", "Cortex-A53",
+ CPU_CLASS_CORTEXA},
+ {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A57, "ARM", "Cortex-A57",
+ CPU_CLASS_CORTEXA},
+ {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A72, "ARM", "Cortex-A72",
+ CPU_CLASS_CORTEXA},
+ {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A73, "ARM", "Cortex-A73",
+ CPU_CLASS_CORTEXA},
+
+ {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_581, "Marvell", "PJ4 v7",
+ CPU_CLASS_MARVELL},
+ {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_584, "Marvell", "PJ4MP v7",
+ CPU_CLASS_MARVELL},
+
+ {CPU_IMPLEMENTER_QCOM, CPU_ARCH_KRAIT_300, "Qualcomm", "Krait 300",
+ CPU_CLASS_KRAIT},
};
@@ -266,6 +284,7 @@ identify_arm_cpu(void)
for(i = 0; i < nitems(cpu_names); i++) {
if (cpu_names[i].implementer == cpuinfo.implementer &&
cpu_names[i].part_number == cpuinfo.part_number) {
+ cpu_class = cpu_names[i].cpu_class;
printf("CPU: %s %s r%dp%d (ECO: 0x%08X)\n",
cpu_names[i].impl_name, cpu_names[i].core_name,
cpuinfo.revision, cpuinfo.patch,
diff --git a/sys/arm/arm/mp_machdep.c b/sys/arm/arm/mp_machdep.c
index 25a9fcaebe15..a1af0d1abd0d 100644
--- a/sys/arm/arm/mp_machdep.c
+++ b/sys/arm/arm/mp_machdep.c
@@ -154,11 +154,9 @@ init_secondary(int cpu)
#ifndef INTRNG
int start = 0, end = 0;
#endif
- uint32_t actlr_mask, actlr_set;
pmap_set_tex();
- cpuinfo_get_actlr_modifier(&actlr_mask, &actlr_set);
- reinit_mmu(pmap_kern_ttb, actlr_mask, actlr_set);
+ cpuinfo_reinit_mmu(pmap_kern_ttb);
cpu_setup();
/* Provide stack pointers for other processor modes. */
diff --git a/sys/arm/arm/pmap-v6.c b/sys/arm/arm/pmap-v6.c
index 047c419861cc..deb5a148455f 100644
--- a/sys/arm/arm/pmap-v6.c
+++ b/sys/arm/arm/pmap-v6.c
@@ -523,11 +523,11 @@ void
pmap_remap_vm_attr(vm_memattr_t old_attr, vm_memattr_t new_attr)
{
int old_idx, new_idx;
-
+
/* Map VM memattrs to indexes to tex_class table. */
old_idx = pte2_attr_tab[(int)old_attr];
new_idx = pte2_attr_tab[(int)new_attr];
-
+
/* Replace TEX attribute and apply it. */
tex_class[old_idx] = tex_class[new_idx];
pmap_set_tex();
@@ -763,7 +763,7 @@ pmap_bootstrap_prepare(vm_paddr_t last)
pt1_entry_t *pte1p;
pt2_entry_t *pte2p;
u_int i;
- uint32_t actlr_mask, actlr_set, l1_attr;
+ uint32_t l1_attr;
/*
* Now, we are going to make real kernel mapping. Note that we are
@@ -880,8 +880,7 @@ pmap_bootstrap_prepare(vm_paddr_t last)
/* Finally, switch from 'boot_pt1' to 'kern_pt1'. */
pmap_kern_ttb = base_pt1 | ttb_flags;
- cpuinfo_get_actlr_modifier(&actlr_mask, &actlr_set);
- reinit_mmu(pmap_kern_ttb, actlr_mask, actlr_set);
+ cpuinfo_reinit_mmu(pmap_kern_ttb);
/*
* Initialize the first available KVA. As kernel image is mapped by
* sections, we are leaving some gap behind.
diff --git a/sys/arm/arm/syscall.c b/sys/arm/arm/syscall.c
index 1ff48abd22e8..8c33fff30a19 100644
--- a/sys/arm/arm/syscall.c
+++ b/sys/arm/arm/syscall.c
@@ -99,12 +99,14 @@ __FBSDID("$FreeBSD$");
void swi_handler(struct trapframe *);
int
-cpu_fetch_syscall_args(struct thread *td, struct syscall_args *sa)
+cpu_fetch_syscall_args(struct thread *td)
{
struct proc *p;
register_t *ap;
+ struct syscall_args *sa;
int error;
+ sa = &td->td_sa;
sa->code = td->td_frame->tf_r7;
ap = &td->td_frame->tf_r0;
if (sa->code == SYS_syscall) {
@@ -141,15 +143,14 @@ cpu_fetch_syscall_args(struct thread *td, struct syscall_args *sa)
static void
syscall(struct thread *td, struct trapframe *frame)
{
- struct syscall_args sa;
int error;
- sa.nap = 4;
+ td->td_sa.nap = 4;
- error = syscallenter(td, &sa);
+ error = syscallenter(td);
KASSERT(error != 0 || td->td_ar == NULL,
("returning from syscall with td_ar set!"));
- syscallret(td, error, &sa);
+ syscallret(td, error);
}
void
diff --git a/sys/arm/cloudabi32/cloudabi32_sysvec.c b/sys/arm/cloudabi32/cloudabi32_sysvec.c
index 100fa479acda..a0bebcc99641 100644
--- a/sys/arm/cloudabi32/cloudabi32_sysvec.c
+++ b/sys/arm/cloudabi32/cloudabi32_sysvec.c
@@ -67,11 +67,15 @@ cloudabi32_proc_setregs(struct thread *td, struct image_params *imgp,
}
static int
-cloudabi32_fetch_syscall_args(struct thread *td, struct syscall_args *sa)
+cloudabi32_fetch_syscall_args(struct thread *td)
{
- struct trapframe *frame = td->td_frame;
+ struct trapframe *frame;
+ struct syscall_args *sa;
int error;
+ frame = td->td_frame;
+ sa = &td->td_sa;
+
/* Obtain system call number. */
sa->code = frame->tf_r12;
if (sa->code >= CLOUDABI32_SYS_MAXSYSCALL)
diff --git a/sys/arm/conf/ARMADA38X b/sys/arm/conf/ARMADA38X
index 35b68a1db9d5..718c728e0e06 100644
--- a/sys/arm/conf/ARMADA38X
+++ b/sys/arm/conf/ARMADA38X
@@ -43,6 +43,7 @@ device re
device mdio
device etherswitch
device e6000sw
+device neta
# PCI
device pci
diff --git a/sys/arm/include/cpuinfo.h b/sys/arm/include/cpuinfo.h
index b11a1697bddf..943391ada4d2 100644
--- a/sys/arm/include/cpuinfo.h
+++ b/sys/arm/include/cpuinfo.h
@@ -124,5 +124,7 @@ struct cpuinfo {
extern struct cpuinfo cpuinfo;
void cpuinfo_init(void);
-void cpuinfo_get_actlr_modifier(uint32_t *actlr_mask, uint32_t *actlr_set);
+#if __ARM_ARCH >= 6
+void cpuinfo_reinit_mmu(uint32_t ttb);
+#endif
#endif /* _MACHINE_CPUINFO_H_ */
diff --git a/sys/arm/include/pmap-v6.h b/sys/arm/include/pmap-v6.h
index 0aaaa5c955b6..7f67b113c2dc 100644
--- a/sys/arm/include/pmap-v6.h
+++ b/sys/arm/include/pmap-v6.h
@@ -176,7 +176,6 @@ vm_paddr_t pmap_dump_kextract(vm_offset_t, pt2_entry_t *);
int pmap_fault(pmap_t, vm_offset_t, uint32_t, int, bool);
void pmap_set_tex(void);
-void reinit_mmu(ttb_entry_t ttb, u_int aux_clr, u_int aux_set);
/*
* Pre-bootstrap epoch functions set.
diff --git a/sys/arm/mv/armada38x/armada38x.c b/sys/arm/mv/armada38x/armada38x.c
index b1e72838c6c4..a72d31432eb1 100644
--- a/sys/arm/mv/armada38x/armada38x.c
+++ b/sys/arm/mv/armada38x/armada38x.c
@@ -29,6 +29,7 @@
__FBSDID("$FreeBSD$");
#include <sys/param.h>
+#include <sys/sysctl.h>
#include <sys/systm.h>
#include <sys/bus.h>
@@ -43,6 +44,10 @@ int armada38x_scu_enable(void);
int armada38x_win_set_iosync_barrier(void);
int armada38x_mbus_optimization(void);
+static int hw_clockrate;
+SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
+ &hw_clockrate, 0, "CPU instruction clock rate");
+
uint32_t
get_tclk(void)
{
@@ -60,6 +65,29 @@ get_tclk(void)
return (TCLK_200MHZ);
}
+uint32_t
+get_cpu_freq(void)
+{
+ uint32_t sar;
+
+ static const uint32_t cpu_frequencies[] = {
+ 0, 0, 0, 0,
+ 1066, 0, 0, 0,
+ 1332, 0, 0, 0,
+ 1600, 0, 0, 0,
+ 1866, 0, 0, 2000
+ };
+
+ sar = (uint32_t)get_sar_value();
+ sar = (sar & A38X_CPU_DDR_CLK_MASK) >> A38X_CPU_DDR_CLK_SHIFT;
+ if (sar >= nitems(cpu_frequencies))
+ return (0);
+
+ hw_clockrate = cpu_frequencies[sar];
+
+ return (hw_clockrate * 1000 * 1000);
+}
+
int
armada38x_win_set_iosync_barrier(void)
{
diff --git a/sys/arm/mv/armadaxp/armadaxp.c b/sys/arm/mv/armadaxp/armadaxp.c
index 29b2642f847d..eae069f124b6 100644
--- a/sys/arm/mv/armadaxp/armadaxp.c
+++ b/sys/arm/mv/armadaxp/armadaxp.c
@@ -136,6 +136,13 @@ get_tclk(void)
return (TCLK_200MHZ);
}
+uint32_t
+get_cpu_freq(void)
+{
+
+ return (0);
+}
+
static uint32_t
count_l2clk(void)
{
diff --git a/sys/arm/mv/discovery/discovery.c b/sys/arm/mv/discovery/discovery.c
index 3968b78d4cc7..96878a2ad72f 100644
--- a/sys/arm/mv/discovery/discovery.c
+++ b/sys/arm/mv/discovery/discovery.c
@@ -109,3 +109,10 @@ get_tclk(void)
panic("Unknown TCLK settings!");
}
}
+
+uint32_t
+get_cpu_freq(void)
+{
+
+ return (0);
+}
diff --git a/sys/arm/mv/files.mv b/sys/arm/mv/files.mv
index 4d70d2941e6c..b37a2a66fb33 100644
--- a/sys/arm/mv/files.mv
+++ b/sys/arm/mv/files.mv
@@ -24,6 +24,8 @@ arm/mv/timer.c optional !soc_mv_armada38x
dev/cesa/cesa.c optional cesa
dev/iicbus/twsi/mv_twsi.c optional twsi
dev/mge/if_mge.c optional mge
+dev/neta/if_mvneta_fdt.c optional neta fdt
+dev/neta/if_mvneta.c optional neta mdio mii
dev/nand/nfc_mv.c optional nand
dev/mvs/mvs_soc.c optional mvs
dev/uart/uart_dev_ns8250.c optional uart
diff --git a/sys/arm/mv/kirkwood/kirkwood.c b/sys/arm/mv/kirkwood/kirkwood.c
index e6fd44275972..b8e9f1dffe53 100644
--- a/sys/arm/mv/kirkwood/kirkwood.c
+++ b/sys/arm/mv/kirkwood/kirkwood.c
@@ -79,3 +79,10 @@ get_tclk(void)
return (TCLK_166MHZ);
}
+
+uint32_t
+get_cpu_freq(void)
+{
+
+ return (0);
+}
diff --git a/sys/arm/mv/mpic.c b/sys/arm/mv/mpic.c
index 49e4bd49da68..c16bf83bba30 100644
--- a/sys/arm/mv/mpic.c
+++ b/sys/arm/mv/mpic.c
@@ -47,6 +47,7 @@ __FBSDID("$FreeBSD$");
#include <sys/mutex.h>
#include <sys/rman.h>
#include <sys/proc.h>
+#include <sys/smp.h>
#include <machine/bus.h>
#include <machine/intr.h>
@@ -70,6 +71,7 @@ __FBSDID("$FreeBSD$");
#define debugf(fmt, args...)
#endif
+#define MPIC_INT_LOCAL 3
#define MPIC_INT_ERR 4
#define MPIC_INT_MSI 96
@@ -93,7 +95,9 @@ __FBSDID("$FreeBSD$");
#define MPIC_IIACK 0x44
#define MPIC_ISM 0x48
#define MPIC_ICM 0x4c
-#define MPIC_ERR_MASK 0xe50
+#define MPIC_ERR_MASK 0x50
+#define MPIC_LOCAL_MASK 0x54
+#define MPIC_CPU(n) (n) * 0x100
#define MPIC_PPI 32
@@ -223,6 +227,7 @@ mv_mpic_attach(device_t dev)
struct mv_mpic_softc *sc;
int error;
uint32_t val;
+ int cpu;
sc = (struct mv_mpic_softc *)device_get_softc(dev);
@@ -283,6 +288,12 @@ mv_mpic_attach(device_t dev)
mpic_unmask_msi();
+ /* Unmask CPU performance counters overflow irq */
+ for (cpu = 0; cpu < mp_ncpus; cpu++)
+ MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CPU(cpu) + MPIC_LOCAL_MASK,
+ (1 << cpu) | MPIC_CPU_READ(mv_mpic_sc,
+ MPIC_CPU(cpu) + MPIC_LOCAL_MASK));
+
return (0);
}
@@ -488,6 +499,16 @@ static void
mpic_unmask_irq(uintptr_t nb)
{
+#ifdef SMP
+ int cpu;
+
+ if (nb == MPIC_INT_LOCAL) {
+ for (cpu = 0; cpu < mp_ncpus; cpu++)
+ MPIC_CPU_WRITE(mv_mpic_sc,
+ MPIC_CPU(cpu) + MPIC_ICM, nb);
+ return;
+ }
+#endif
if (mpic_irq_is_percpu(nb))
MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb);
else if (nb < ERR_IRQ)
@@ -503,6 +524,16 @@ static void
mpic_mask_irq(uintptr_t nb)
{
+#ifdef SMP
+ int cpu;
+
+ if (nb == MPIC_INT_LOCAL) {
+ for (cpu = 0; cpu < mp_ncpus; cpu++)
+ MPIC_CPU_WRITE(mv_mpic_sc,
+ MPIC_CPU(cpu) + MPIC_ISM, nb);
+ return;
+ }
+#endif
if (mpic_irq_is_percpu(nb))
MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb);
else if (nb < ERR_IRQ)
diff --git a/sys/arm/mv/mv_common.c b/sys/arm/mv/mv_common.c
index 02214bef0463..d6be930b26be 100644
--- a/sys/arm/mv/mv_common.c
+++ b/sys/arm/mv/mv_common.c
@@ -96,6 +96,7 @@ static void decode_win_cesa_setup(u_long);
static void decode_win_usb_setup(u_long);
static void decode_win_usb3_setup(u_long);
static void decode_win_eth_setup(u_long);
+static void decode_win_neta_setup(u_long);
static void decode_win_sata_setup(u_long);
static void decode_win_ahci_setup(u_long);
static void decode_win_sdhci_setup(u_long);
@@ -107,6 +108,7 @@ static void decode_win_cesa_dump(u_long);
static void decode_win_usb_dump(u_long);
static void decode_win_usb3_dump(u_long);
static void decode_win_eth_dump(u_long base);
+static void decode_win_neta_dump(u_long base);
static void decode_win_idma_dump(u_long base);
static void decode_win_xor_dump(u_long base);
static void decode_win_ahci_dump(u_long base);
@@ -152,6 +154,7 @@ struct soc_node_spec {
static struct soc_node_spec soc_nodes[] = {
{ "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump },
+ { "marvell,armada-370-neta", &decode_win_neta_setup, &decode_win_neta_dump },
{ "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump },
{ "marvell,orion-ehci", &decode_win_usb_setup, &decode_win_usb_dump },
{ "marvell,armada-380-xhci", &decode_win_usb3_setup, &decode_win_usb3_dump },
@@ -416,7 +419,7 @@ soc_id(uint32_t *dev, uint32_t *rev)
static void
soc_identify(void)
{
- uint32_t d, r, size, mode;
+ uint32_t d, r, size, mode, freq;
const char *dev;
const char *rev;
@@ -509,7 +512,11 @@ soc_identify(void)
printf("%s", dev);
if (*rev != '\0')
printf(" rev %s", rev);
- printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000);
+ printf(", TClock %dMHz", get_tclk() / 1000 / 1000);
+ freq = get_cpu_freq();
+ if (freq != 0)
+ printf(", Frequency %dMHz", freq / 1000 / 1000);
+ printf("\n");
mode = read_cpu_ctrl(CPU_CONFIG);
printf(" Instruction cache prefetch %s, data cache prefetch %s\n",
@@ -1433,6 +1440,20 @@ decode_win_eth_setup(u_long base)
}
}
+static void
+decode_win_neta_dump(u_long base)
+{
+
+ decode_win_eth_dump(base + MV_WIN_NETA_OFFSET);
+}
+
+static void
+decode_win_neta_setup(u_long base)
+{
+
+ decode_win_eth_setup(base + MV_WIN_NETA_OFFSET);
+}
+
static int
decode_win_eth_valid(void)
{
diff --git a/sys/arm/mv/mvreg.h b/sys/arm/mv/mvreg.h
index df83d50dc872..dfc07d1c084e 100644
--- a/sys/arm/mv/mvreg.h
+++ b/sys/arm/mv/mvreg.h
@@ -355,6 +355,9 @@
#define TCLK_300MHZ 300000000
#define TCLK_667MHZ 667000000
+#define A38X_CPU_DDR_CLK_MASK 0x00007c00
+#define A38X_CPU_DDR_CLK_SHIFT 10
+
/*
* CPU Cache Configuration
*/
diff --git a/sys/arm/mv/mvvar.h b/sys/arm/mv/mvvar.h
index c08064feb1da..1356ae29ed6e 100644
--- a/sys/arm/mv/mvvar.h
+++ b/sys/arm/mv/mvvar.h
@@ -104,6 +104,7 @@ uint32_t ddr_target(int i);
uint32_t cpu_extra_feat(void);
uint32_t get_tclk(void);
+uint32_t get_cpu_freq(void);
uint32_t get_l2clk(void);
uint32_t read_cpu_ctrl(uint32_t);
void write_cpu_ctrl(uint32_t, uint32_t);
diff --git a/sys/arm/mv/mvwin.h b/sys/arm/mv/mvwin.h
index 65a6eb9362d8..b8c36b307aa3 100644
--- a/sys/arm/mv/mvwin.h
+++ b/sys/arm/mv/mvwin.h
@@ -229,6 +229,9 @@
#define MV_WIN_USB3_BASE(n) (0x8 * (n) + 0x4004)
#define MV_WIN_USB3_MAX 8
+#define MV_WIN_NETA_OFFSET 0x2000
+#define MV_WIN_NETA_BASE(n) MV_WIN_ETH_BASE(n) + MV_WIN_NETA_OFFSET
+
#define MV_WIN_ETH_BASE(n) (0x8 * (n) + 0x200)
#define MV_WIN_ETH_SIZE(n) (0x8 * (n) + 0x204)
#define MV_WIN_ETH_REMAP(n) (0x4 * (n) + 0x280)
@@ -325,6 +328,7 @@
/* IO Window Control Register fields */
#define IO_WIN_SIZE_SHIFT 16
#define IO_WIN_SIZE_MASK 0xFFFF
+#define IO_WIN_COH_ATTR_MASK (0xF << 12)
#define IO_WIN_ATTR_SHIFT 8
#define IO_WIN_ATTR_MASK 0xFF
#define IO_WIN_TGT_SHIFT 4
diff --git a/sys/arm/mv/orion/orion.c b/sys/arm/mv/orion/orion.c
index d4c3a165dedc..2d1774e8fd95 100644
--- a/sys/arm/mv/orion/orion.c
+++ b/sys/arm/mv/orion/orion.c
@@ -100,3 +100,10 @@ get_tclk(void)
panic("Unknown TCLK settings!");
}
}
+
+uint32_t
+get_cpu_freq(void)
+{
+
+ return (0);
+}
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-09 17:16:58 +0000