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path: root/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
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Diffstat (limited to 'llvm/utils/TableGen/DAGISelMatcherEmitter.cpp')
-rw-r--r--llvm/utils/TableGen/DAGISelMatcherEmitter.cpp33
1 files changed, 22 insertions, 11 deletions
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index 94799267e896..6fd5698e7372 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -737,24 +737,35 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
case Matcher::EmitRegister: {
const EmitRegisterMatcher *Matcher = cast<EmitRegisterMatcher>(N);
const CodeGenRegister *Reg = Matcher->getReg();
+ MVT::SimpleValueType VT = Matcher->getVT();
// If the enum value of the register is larger than one byte can handle,
// use EmitRegister2.
if (Reg && Reg->EnumValue > 255) {
- OS << "OPC_EmitRegister2, " << getEnumName(Matcher->getVT()) << ", ";
+ OS << "OPC_EmitRegister2, " << getEnumName(VT) << ", ";
OS << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n";
return 4;
+ }
+ unsigned OpBytes;
+ switch (VT) {
+ case MVT::i32:
+ case MVT::i64:
+ OpBytes = 1;
+ OS << "OPC_EmitRegisterI" << MVT(VT).getSizeInBits() << ", ";
+ break;
+ default:
+ OpBytes = 2;
+ OS << "OPC_EmitRegister, " << getEnumName(VT) << ", ";
+ break;
+ }
+ if (Reg) {
+ OS << getQualifiedName(Reg->TheDef) << ",\n";
} else {
- OS << "OPC_EmitRegister, " << getEnumName(Matcher->getVT()) << ", ";
- if (Reg) {
- OS << getQualifiedName(Reg->TheDef) << ",\n";
- } else {
- OS << "0 ";
- if (!OmitComments)
- OS << "/*zero_reg*/";
- OS << ",\n";
- }
- return 3;
+ OS << "0 ";
+ if (!OmitComments)
+ OS << "/*zero_reg*/";
+ OS << ",\n";
}
+ return OpBytes + 1;
}
case Matcher::EmitConvertToTarget: {