diff options
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVInstrInfo.cpp')
-rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 44 |
1 files changed, 35 insertions, 9 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 3b416ce3d3f4..d39ec505127c 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -24,14 +24,14 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" +using namespace llvm; + #define GEN_CHECK_COMPRESS_INSTR #include "RISCVGenCompressInstEmitter.inc" #define GET_INSTRINFO_CTOR_DTOR #include "RISCVGenInstrInfo.inc" -using namespace llvm; - RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI) : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP), STI(STI) {} @@ -76,10 +76,10 @@ unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI, break; } - if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() && - MI.getOperand(1).getImm() == 0) { - FrameIndex = MI.getOperand(0).getIndex(); - return MI.getOperand(2).getReg(); + if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() && + MI.getOperand(2).getImm() == 0) { + FrameIndex = MI.getOperand(1).getIndex(); + return MI.getOperand(0).getReg(); } return 0; @@ -112,7 +112,7 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB, void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned SrcReg, bool IsKill, int FI, + Register SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { DebugLoc DL; @@ -139,7 +139,7 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned DstReg, int FI, + Register DstReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { DebugLoc DL; @@ -342,7 +342,7 @@ unsigned RISCVInstrInfo::insertBranch( *BytesAdded = 0; // Shouldn't be a fall through. - assert(TBB && "InsertBranch must not be told to insert a fallthrough"); + assert(TBB && "insertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 3 || Cond.size() == 0) && "RISCV branch conditions have two components!"); @@ -471,14 +471,38 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { case TargetOpcode::KILL: case TargetOpcode::DBG_VALUE: return 0; + // These values are determined based on RISCVExpandAtomicPseudoInsts, + // RISCVExpandPseudoInsts and RISCVMCCodeEmitter, depending on where the + // pseudos are expanded. case RISCV::PseudoCALLReg: case RISCV::PseudoCALL: + case RISCV::PseudoJump: case RISCV::PseudoTAIL: case RISCV::PseudoLLA: case RISCV::PseudoLA: case RISCV::PseudoLA_TLS_IE: case RISCV::PseudoLA_TLS_GD: return 8; + case RISCV::PseudoAtomicLoadNand32: + case RISCV::PseudoAtomicLoadNand64: + return 20; + case RISCV::PseudoMaskedAtomicSwap32: + case RISCV::PseudoMaskedAtomicLoadAdd32: + case RISCV::PseudoMaskedAtomicLoadSub32: + return 28; + case RISCV::PseudoMaskedAtomicLoadNand32: + return 32; + case RISCV::PseudoMaskedAtomicLoadMax32: + case RISCV::PseudoMaskedAtomicLoadMin32: + return 44; + case RISCV::PseudoMaskedAtomicLoadUMax32: + case RISCV::PseudoMaskedAtomicLoadUMin32: + return 36; + case RISCV::PseudoCmpXchg32: + case RISCV::PseudoCmpXchg64: + return 16; + case RISCV::PseudoMaskedCmpXchg32: + return 32; case TargetOpcode::INLINEASM: case TargetOpcode::INLINEASM_BR: { const MachineFunction &MF = *MI.getParent()->getParent(); @@ -777,6 +801,8 @@ void RISCVInstrInfo::buildOutlinedFrame( } } + MBB.addLiveIn(RISCV::X5); + // Add in a return instruction to the end of the outlined frame. MBB.insert(MBB.end(), BuildMI(MF, DebugLoc(), get(RISCV::JALR)) .addReg(RISCV::X0, RegState::Define) |