diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index 29572e3106d1..88effed9f076 100644 --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -442,8 +442,7 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, CLI.IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, IsVarArg, IsStructRet, StructAttrFlag, Outs, OutVals, Ins, DAG); - for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { - CCValAssign &VA = ArgLocs[i]; + for (const CCValAssign &VA : ArgLocs) { if (VA.isMemLoc()) { CLI.IsTailCall = false; break; @@ -2549,7 +2548,8 @@ HexagonTargetLowering::extractVector(SDValue VecV, SDValue IdxV, // Special case for v{8,4,2}i1 (the only boolean vectors legal in Hexagon // without any coprocessors). if (ElemWidth == 1) { - assert(VecWidth == VecTy.getVectorNumElements() && "Sanity failure"); + assert(VecWidth == VecTy.getVectorNumElements() && + "Vector elements should equal vector width size"); assert(VecWidth == 8 || VecWidth == 4 || VecWidth == 2); // Check if this is an extract of the lowest bit. if (IdxN) { @@ -2863,8 +2863,7 @@ HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op, Scale /= 2; } - // Another sanity check. At this point there should only be two words - // left, and Scale should be 2. + // At this point there should only be two words left, and Scale should be 2. assert(Scale == 2 && Words[IdxW].size() == 2); SDValue WW = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, |