diff options
Diffstat (limited to 'llvm/lib/Target/ARM/Thumb2SizeReduction.cpp')
-rw-r--r-- | llvm/lib/Target/ARM/Thumb2SizeReduction.cpp | 26 |
1 files changed, 18 insertions, 8 deletions
diff --git a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp index c5a62aa33990..ae661594bdc9 100644 --- a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp +++ b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp @@ -457,7 +457,7 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, return false; if (!MI->hasOneMemOperand() || - (*MI->memoperands_begin())->getAlignment() < 4) + (*MI->memoperands_begin())->getAlign() < Align(4)) return false; // We're creating a completely different type of load/store - LDM from LDR. @@ -516,13 +516,23 @@ Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, isLdStMul = true; break; } - case ARM::t2STMIA: - // If the base register is killed, we don't care what its value is after the - // instruction, so we can use an updating STMIA. + case ARM::t2STMIA: { + // t2STMIA is reduced to tSTMIA_UPD which has writeback. We can only do this + // if the base register is killed, as then it doesn't matter what its value + // is after the instruction. if (!MI->getOperand(0).isKill()) return false; + // If the base register is in the register list and isn't the lowest + // numbered register (i.e. it's in operand 4 onwards) then with writeback + // the stored value is unknown, so we can't convert to tSTMIA_UPD. + Register BaseReg = MI->getOperand(0).getReg(); + for (unsigned i = 4; i < MI->getNumOperands(); ++i) + if (MI->getOperand(i).getReg() == BaseReg) + return false; + break; + } case ARM::t2LDMIA_RET: { Register BaseReg = MI->getOperand(1).getReg(); if (BaseReg != ARM::SP) @@ -676,7 +686,7 @@ Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI, default: break; case ARM::t2ADDSri: case ARM::t2ADDSrr: { - unsigned PredReg = 0; + Register PredReg; if (getInstrPredicate(*MI, PredReg) == ARMCC::AL) { switch (Opc) { default: break; @@ -718,7 +728,7 @@ Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI, return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop); } case ARM::t2TEQrr: { - unsigned PredReg = 0; + Register PredReg; // Can only convert to eors if we're not in an IT block. if (getInstrPredicate(*MI, PredReg) != ARMCC::AL) break; @@ -789,7 +799,7 @@ Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI, // Check if it's possible / necessary to transfer the predicate. const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2); - unsigned PredReg = 0; + Register PredReg; ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); bool SkipPred = false; if (Pred != ARMCC::AL) { @@ -882,7 +892,7 @@ Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI, // Check if it's possible / necessary to transfer the predicate. const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1); - unsigned PredReg = 0; + Register PredReg; ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); bool SkipPred = false; if (Pred != ARMCC::AL) { |