diff options
Diffstat (limited to 'llvm/lib/CodeGen/MachineInstr.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/MachineInstr.cpp | 142 |
1 files changed, 88 insertions, 54 deletions
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index 08d786f8f12c..d4181591deab 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -61,6 +61,7 @@ #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/FormattedStream.h" #include "llvm/Support/LowLevelTypeImpl.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" @@ -696,6 +697,26 @@ void MachineInstr::eraseFromBundle() { getParent()->erase_instr(this); } +bool MachineInstr::isCandidateForCallSiteEntry(QueryType Type) const { + if (!isCall(Type)) + return false; + switch (getOpcode()) { + case TargetOpcode::PATCHABLE_EVENT_CALL: + case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL: + case TargetOpcode::PATCHPOINT: + case TargetOpcode::STACKMAP: + case TargetOpcode::STATEPOINT: + return false; + } + return true; +} + +bool MachineInstr::shouldUpdateCallSiteInfo() const { + if (isBundle()) + return isCandidateForCallSiteEntry(MachineInstr::AnyInBundle); + return isCandidateForCallSiteEntry(); +} + unsigned MachineInstr::getNumExplicitOperands() const { unsigned NumOperands = MCID->getNumOperands(); if (!MCID->isVariadic()) @@ -813,11 +834,26 @@ const DILabel *MachineInstr::getDebugLabel() const { return cast<DILabel>(getOperand(0).getMetadata()); } +const MachineOperand &MachineInstr::getDebugVariableOp() const { + assert(isDebugValue() && "not a DBG_VALUE"); + return getOperand(2); +} + +MachineOperand &MachineInstr::getDebugVariableOp() { + assert(isDebugValue() && "not a DBG_VALUE"); + return getOperand(2); +} + const DILocalVariable *MachineInstr::getDebugVariable() const { assert(isDebugValue() && "not a DBG_VALUE"); return cast<DILocalVariable>(getOperand(2).getMetadata()); } +MachineOperand &MachineInstr::getDebugExpressionOp() { + assert(isDebugValue() && "not a DBG_VALUE"); + return getOperand(3); +} + const DIExpression *MachineInstr::getDebugExpression() const { assert(isDebugValue() && "not a DBG_VALUE"); return cast<DIExpression>(getOperand(3).getMetadata()); @@ -1199,6 +1235,10 @@ bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other, if (!mayStore() && !Other.mayStore()) return false; + // Both instructions must be memory operations to be able to alias. + if (!mayLoadOrStore() || !Other.mayLoadOrStore()) + return false; + // Let the target decide if memory accesses cannot possibly overlap. if (TII->areMemAccessesTriviallyDisjoint(*this, Other)) return false; @@ -1449,6 +1489,37 @@ LLVM_DUMP_METHOD void MachineInstr::dump() const { dbgs() << " "; print(dbgs()); } + +LLVM_DUMP_METHOD void MachineInstr::dumprImpl( + const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth, + SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const { + if (Depth >= MaxDepth) + return; + if (!AlreadySeenInstrs.insert(this).second) + return; + // PadToColumn always inserts at least one space. + // Don't mess up the alignment if we don't want any space. + if (Depth) + fdbgs().PadToColumn(Depth * 2); + print(fdbgs()); + for (const MachineOperand &MO : operands()) { + if (!MO.isReg() || MO.isDef()) + continue; + Register Reg = MO.getReg(); + if (Reg.isPhysical()) + continue; + const MachineInstr *NewMI = MRI.getUniqueVRegDef(Reg); + if (NewMI == nullptr) + continue; + NewMI->dumprImpl(MRI, Depth + 1, MaxDepth, AlreadySeenInstrs); + } +} + +LLVM_DUMP_METHOD void MachineInstr::dumpr(const MachineRegisterInfo &MRI, + unsigned MaxDepth) const { + SmallPtrSet<const MachineInstr *, 16> AlreadySeenInstrs; + dumprImpl(MRI, 0, MaxDepth, AlreadySeenInstrs); +} #endif void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers, @@ -1473,7 +1544,6 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone, bool SkipOpers, bool SkipDebugLoc, bool AddNewLine, const TargetInstrInfo *TII) const { // We can be a bit tidier if we know the MachineFunction. - const MachineFunction *MF = nullptr; const TargetRegisterInfo *TRI = nullptr; const MachineRegisterInfo *MRI = nullptr; const TargetIntrinsicInfo *IntrinsicInfo = nullptr; @@ -1540,6 +1610,8 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, OS << "exact "; if (getFlag(MachineInstr::NoFPExcept)) OS << "nofpexcept "; + if (getFlag(MachineInstr::NoMerge)) + OS << "nomerge "; // Print the opcode name. if (TII) @@ -1618,15 +1690,8 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, // Pretty print the inline asm operand descriptor. OS << '$' << AsmOpCount++; unsigned Flag = MO.getImm(); - switch (InlineAsm::getKind(Flag)) { - case InlineAsm::Kind_RegUse: OS << ":[reguse"; break; - case InlineAsm::Kind_RegDef: OS << ":[regdef"; break; - case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break; - case InlineAsm::Kind_Clobber: OS << ":[clobber"; break; - case InlineAsm::Kind_Imm: OS << ":[imm"; break; - case InlineAsm::Kind_Mem: OS << ":[mem"; break; - default: OS << ":[??" << InlineAsm::getKind(Flag); break; - } + OS << ":["; + OS << InlineAsm::getKindName(InlineAsm::getKind(Flag)); unsigned RCID = 0; if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) && @@ -1639,29 +1704,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, if (InlineAsm::isMemKind(Flag)) { unsigned MCID = InlineAsm::getMemoryConstraintID(Flag); - switch (MCID) { - case InlineAsm::Constraint_es: OS << ":es"; break; - case InlineAsm::Constraint_i: OS << ":i"; break; - case InlineAsm::Constraint_m: OS << ":m"; break; - case InlineAsm::Constraint_o: OS << ":o"; break; - case InlineAsm::Constraint_v: OS << ":v"; break; - case InlineAsm::Constraint_Q: OS << ":Q"; break; - case InlineAsm::Constraint_R: OS << ":R"; break; - case InlineAsm::Constraint_S: OS << ":S"; break; - case InlineAsm::Constraint_T: OS << ":T"; break; - case InlineAsm::Constraint_Um: OS << ":Um"; break; - case InlineAsm::Constraint_Un: OS << ":Un"; break; - case InlineAsm::Constraint_Uq: OS << ":Uq"; break; - case InlineAsm::Constraint_Us: OS << ":Us"; break; - case InlineAsm::Constraint_Ut: OS << ":Ut"; break; - case InlineAsm::Constraint_Uv: OS << ":Uv"; break; - case InlineAsm::Constraint_Uy: OS << ":Uy"; break; - case InlineAsm::Constraint_X: OS << ":X"; break; - case InlineAsm::Constraint_Z: OS << ":Z"; break; - case InlineAsm::Constraint_ZC: OS << ":ZC"; break; - case InlineAsm::Constraint_Zy: OS << ":Zy"; break; - default: OS << ":?"; break; - } + OS << ":" << InlineAsm::getMemConstraintName(MCID); } unsigned TiedTo = 0; @@ -1758,21 +1801,13 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, } // Print extra comments for DEBUG_VALUE. - if (isDebugValue() && getOperand(e - 2).isMetadata()) { + if (isDebugValue() && getDebugVariableOp().isMetadata()) { if (!HaveSemi) { OS << ";"; HaveSemi = true; } - auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata()); + auto *DV = getDebugVariable(); OS << " line no:" << DV->getLine(); - if (auto *InlinedAt = debugLoc->getInlinedAt()) { - DebugLoc InlinedAtDL(InlinedAt); - if (InlinedAtDL && MF) { - OS << " inlined @[ "; - InlinedAtDL.print(OS); - OS << " ]"; - } - } if (isIndirectDebugValue()) OS << " indirect"; } @@ -2077,7 +2112,8 @@ static const DIExpression *computeExprForSpill(const MachineInstr &MI) { const DIExpression *Expr = MI.getDebugExpression(); if (MI.isIndirectDebugValue()) { - assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset"); + assert(MI.getDebugOffset().getImm() == 0 && + "DBG_VALUE with nonzero offset"); Expr = DIExpression::prepend(Expr, DIExpression::DerefBefore); } return Expr; @@ -2097,9 +2133,9 @@ MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB, void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex) { const DIExpression *Expr = computeExprForSpill(Orig); - Orig.getOperand(0).ChangeToFrameIndex(FrameIndex); - Orig.getOperand(1).ChangeToImmediate(0U); - Orig.getOperand(3).setMetadata(Expr); + Orig.getDebugOperand(0).ChangeToFrameIndex(FrameIndex); + Orig.getDebugOffset().ChangeToImmediate(0U); + Orig.getDebugExpressionOp().setMetadata(Expr); } void MachineInstr::collectDebugValues( @@ -2113,8 +2149,7 @@ void MachineInstr::collectDebugValues( DI != DE; ++DI) { if (!DI->isDebugValue()) return; - if (DI->getOperand(0).isReg() && - DI->getOperand(0).getReg() == MI.getOperand(0).getReg()) + if (DI->getDebugOperandForReg(MI.getOperand(0).getReg())) DbgValues.push_back(&*DI); } } @@ -2126,26 +2161,25 @@ void MachineInstr::changeDebugValuesDefReg(Register Reg) { if (!getOperand(0).isReg()) return; - unsigned DefReg = getOperand(0).getReg(); + Register DefReg = getOperand(0).getReg(); auto *MRI = getRegInfo(); for (auto &MO : MRI->use_operands(DefReg)) { auto *DI = MO.getParent(); if (!DI->isDebugValue()) continue; - if (DI->getOperand(0).isReg() && - DI->getOperand(0).getReg() == DefReg){ + if (DI->getDebugOperandForReg(DefReg)) { DbgValues.push_back(DI); } } // Propagate Reg to debug value instructions. for (auto *DBI : DbgValues) - DBI->getOperand(0).setReg(Reg); + DBI->getDebugOperandForReg(DefReg)->setReg(Reg); } using MMOList = SmallVector<const MachineMemOperand *, 2>; -static unsigned getSpillSlotSize(MMOList &Accesses, +static unsigned getSpillSlotSize(const MMOList &Accesses, const MachineFrameInfo &MFI) { unsigned Size = 0; for (auto A : Accesses) |