diff options
Diffstat (limited to 'lib/libpmcstat/pmu-events/arch/x86/haswell/virtual-memory.json')
-rw-r--r-- | lib/libpmcstat/pmu-events/arch/x86/haswell/virtual-memory.json | 484 |
1 files changed, 0 insertions, 484 deletions
diff --git a/lib/libpmcstat/pmu-events/arch/x86/haswell/virtual-memory.json b/lib/libpmcstat/pmu-events/arch/x86/haswell/virtual-memory.json deleted file mode 100644 index 777b500a5c9f..000000000000 --- a/lib/libpmcstat/pmu-events/arch/x86/haswell/virtual-memory.json +++ /dev/null @@ -1,484 +0,0 @@ -[ - { - "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", - "SampleAfterValue": "100003", - "BriefDescription": "Load misses in all DTLB levels that cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", - "SampleAfterValue": "2000003", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", - "SampleAfterValue": "2000003", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", - "SampleAfterValue": "2000003", - "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0xe", - "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", - "SampleAfterValue": "100003", - "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", - "SampleAfterValue": "2000003", - "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", - "SampleAfterValue": "2000003", - "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of cache load STLB hits. No page walk.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x60", - "EventName": "DTLB_LOAD_MISSES.STLB_HIT", - "SampleAfterValue": "2000003", - "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.", - "EventCode": "0x08", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", - "SampleAfterValue": "100003", - "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", - "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.", - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", - "SampleAfterValue": "100003", - "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.", - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", - "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", - "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).", - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0xe", - "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", - "SampleAfterValue": "100003", - "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.", - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "DTLB_STORE_MISSES.WALK_DURATION", - "SampleAfterValue": "100003", - "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", - "SampleAfterValue": "100003", - "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", - "SampleAfterValue": "100003", - "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x60", - "EventName": "DTLB_STORE_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.", - "EventCode": "0x49", - "Counter": "0,1,2,3", - "UMask": "0x80", - "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", - "SampleAfterValue": "100003", - "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x4f", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "EPT.WALK_CYCLES", - "SampleAfterValue": "2000003", - "BriefDescription": "Cycle count for an Extended Page table walk.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Misses in ITLB that causes a page walk of any page size.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", - "SampleAfterValue": "100003", - "BriefDescription": "Misses at all ITLB levels that cause page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x2", - "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", - "SampleAfterValue": "100003", - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x4", - "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", - "SampleAfterValue": "100003", - "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x8", - "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", - "SampleAfterValue": "100003", - "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Completed page walks in ITLB of any page size.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0xe", - "EventName": "ITLB_MISSES.WALK_COMPLETED", - "SampleAfterValue": "100003", - "BriefDescription": "Misses in all ITLB levels that cause completed page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x10", - "EventName": "ITLB_MISSES.WALK_DURATION", - "SampleAfterValue": "100003", - "BriefDescription": "Cycles when PMH is busy with page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "ITLB misses that hit STLB (4K).", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "ITLB_MISSES.STLB_HIT_4K", - "SampleAfterValue": "100003", - "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "ITLB misses that hit STLB (2M).", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x40", - "EventName": "ITLB_MISSES.STLB_HIT_2M", - "SampleAfterValue": "100003", - "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "ITLB misses that hit STLB. No page walk.", - "EventCode": "0x85", - "Counter": "0,1,2,3", - "UMask": "0x60", - "EventName": "ITLB_MISSES.STLB_HIT", - "SampleAfterValue": "100003", - "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", - "EventCode": "0xae", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "ITLB.ITLB_FLUSH", - "SampleAfterValue": "100003", - "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.", - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x11", - "EventName": "PAGE_WALKER_LOADS.DTLB_L1", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of DTLB page walker hits in the L1+FB", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of DTLB page walker loads that hit in the L2.", - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x12", - "EventName": "PAGE_WALKER_LOADS.DTLB_L2", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of DTLB page walker hits in the L2", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of DTLB page walker loads that hit in the L3.", - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x14", - "Errata": "HSD25", - "EventName": "PAGE_WALKER_LOADS.DTLB_L3", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of DTLB page walker loads from memory.", - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x18", - "Errata": "HSD25", - "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of DTLB page walker hits in Memory", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.", - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x21", - "EventName": "PAGE_WALKER_LOADS.ITLB_L1", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of ITLB page walker hits in the L1+FB", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of ITLB page walker loads that hit in the L2.", - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x22", - "EventName": "PAGE_WALKER_LOADS.ITLB_L2", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of ITLB page walker hits in the L2", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of ITLB page walker loads that hit in the L3.", - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x24", - "Errata": "HSD25", - "EventName": "PAGE_WALKER_LOADS.ITLB_L3", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "Number of ITLB page walker loads from memory.", - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x28", - "Errata": "HSD25", - "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY", - "SampleAfterValue": "2000003", - "BriefDescription": "Number of ITLB page walker hits in Memory", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x41", - "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x42", - "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x44", - "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x48", - "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x81", - "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x82", - "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x84", - "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", - "CounterHTOff": "0,1,2,3" - }, - { - "EventCode": "0xBC", - "Counter": "0,1,2,3", - "UMask": "0x88", - "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY", - "SampleAfterValue": "2000003", - "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.", - "CounterHTOff": "0,1,2,3" - }, - { - "PublicDescription": "DTLB flush attempts of the thread-specific entries.", - "EventCode": "0xBD", - "Counter": "0,1,2,3", - "UMask": "0x1", - "EventName": "TLB_FLUSH.DTLB_THREAD", - "SampleAfterValue": "100003", - "BriefDescription": "DTLB flush attempts of the thread-specific entries", - "CounterHTOff": "0,1,2,3,4,5,6,7" - }, - { - "PublicDescription": "Count number of STLB flush attempts.", - "EventCode": "0xBD", - "Counter": "0,1,2,3", - "UMask": "0x20", - "EventName": "TLB_FLUSH.STLB_ANY", - "SampleAfterValue": "100003", - "BriefDescription": "STLB flush attempts", - "CounterHTOff": "0,1,2,3,4,5,6,7" - } -]
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