diff options
Diffstat (limited to 'lib/Target')
62 files changed, 1643 insertions, 1641 deletions
diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index 6486a608e46d..8d9c62253cdd 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -140,23 +140,7 @@ include "ARMCallingConv.td" include "ARMInstrInfo.td" -def ARMInstrInfo : InstrInfo { - // Define how we want to layout our target-specific information field. - let TSFlagsFields = ["AddrModeBits", - "SizeFlag", - "IndexModeBits", - "Form", - "isUnaryDataProc", - "canXformTo16Bit", - "Dom"]; - let TSFlagsShifts = [0, - 4, - 7, - 9, - 15, - 16, - 17]; -} +def ARMInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// // Declare the target which we are implementing diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index b6c81f6910aa..77fb0c3cdbd0 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -861,7 +861,8 @@ CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, DebugLoc dl) { SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), - /*AlwaysInline=*/false, NULL, 0, NULL, 0); + /*isVolatile=*/false, /*AlwaysInline=*/false, + NULL, 0, NULL, 0); } /// LowerMemOpCallTo - Store the argument to the stack. @@ -2053,7 +2054,7 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, - bool AlwaysInline, + bool isVolatile, bool AlwaysInline, const Value *DstSV, uint64_t DstSVOff, const Value *SrcSV, uint64_t SrcSVOff){ // Do repeated 4-byte loads and stores. To be improved. @@ -2089,7 +2090,7 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, Loads[i] = DAG.getLoad(VT, dl, Chain, DAG.getNode(ISD::ADD, dl, MVT::i32, Src, DAG.getConstant(SrcOff, MVT::i32)), - SrcSV, SrcSVOff + SrcOff, false, false, 0); + SrcSV, SrcSVOff + SrcOff, isVolatile, false, 0); TFOps[i] = Loads[i].getValue(1); SrcOff += VTSize; } @@ -2100,7 +2101,7 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, TFOps[i] = DAG.getStore(Chain, dl, Loads[i], DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, DAG.getConstant(DstOff, MVT::i32)), - DstSV, DstSVOff + DstOff, false, false, 0); + DstSV, DstSVOff + DstOff, isVolatile, false, 0); DstOff += VTSize; } Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h index f8f8adc70af8..fa33ad307506 100644 --- a/lib/Target/ARM/ARMISelLowering.h +++ b/lib/Target/ARM/ARMISelLowering.h @@ -305,7 +305,7 @@ namespace llvm { SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, - bool AlwaysInline, + bool isVolatile, bool AlwaysInline, const Value *DstSV, uint64_t DstSVOff, const Value *SrcSV, uint64_t SrcSVOff); SDValue LowerCallResult(SDValue Chain, SDValue InFlag, diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 4427e50bbdb1..b466d0dd994e 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -185,28 +185,25 @@ class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im, : Instruction { let Namespace = "ARM"; - // TSFlagsFields AddrMode AM = am; - bits<4> AddrModeBits = AM.Value; - SizeFlagVal SZ = sz; - bits<3> SizeFlag = SZ.Value; - IndexMode IM = im; bits<2> IndexModeBits = IM.Value; - Format F = f; bits<6> Form = F.Value; - Domain D = d; - bits<2> Dom = D.Value; - - // - // Attributes specific to ARM instructions... - // bit isUnaryDataProc = 0; bit canXformTo16Bit = 0; + // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h. + let TSFlags{3-0} = AM.Value; + let TSFlags{6-4} = SZ.Value; + let TSFlags{8-7} = IndexModeBits; + let TSFlags{14-9} = Form; + let TSFlags{15} = isUnaryDataProc; + let TSFlags{16} = canXformTo16Bit; + let TSFlags{18-17} = D.Value; + let Constraints = cstr; let Itinerary = itin; } @@ -1317,7 +1314,7 @@ class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, let Inst{11-8} = 0b1011; // 64-bit loads & stores operate on both NEON and VFP pipelines. - let Dom = VFPNeonDomain.Value; + let D = VFPNeonDomain; } class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, @@ -1341,7 +1338,7 @@ class AXDI5<dag oops, dag iops, IndexMode im, InstrItinClass itin, let Inst{11-8} = 0b1011; // 64-bit loads & stores operate on both NEON and VFP pipelines. - let Dom = VFPNeonDomain.Value; + let D = VFPNeonDomain; } class AXSI5<dag oops, dag iops, IndexMode im, InstrItinClass itin, diff --git a/lib/Target/ARM/ARMMCAsmInfo.cpp b/lib/Target/ARM/ARMMCAsmInfo.cpp index 20197e487d31..53edfcad9308 100644 --- a/lib/Target/ARM/ARMMCAsmInfo.cpp +++ b/lib/Target/ARM/ARMMCAsmInfo.cpp @@ -58,7 +58,6 @@ ARMELFMCAsmInfo::ARMELFMCAsmInfo() { CommentString = "@"; HasLEB128 = true; - AbsoluteDebugSectionOffsets = true; PrivateGlobalPrefix = ".L"; WeakRefDirective = "\t.weak\t"; HasLCOMMDirective = true; diff --git a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp index ba736e3c0777..15c52946cf58 100644 --- a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp @@ -26,7 +26,6 @@ #include "llvm/Type.h" #include "llvm/Assembly/Writer.h" #include "llvm/CodeGen/AsmPrinter.h" -#include "llvm/CodeGen/DwarfWriter.h" #include "llvm/CodeGen/MachineModuleInfoImpls.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" @@ -46,11 +45,9 @@ #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" -#include "llvm/ADT/StringSet.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/FormattedStream.h" -#include "llvm/Support/MathExtras.h" +#include "llvm/Support/raw_ostream.h" #include <cctype> using namespace llvm; @@ -74,9 +71,8 @@ namespace { const MachineConstantPool *MCP; public: - explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM, - MCStreamer &Streamer) - : AsmPrinter(O, TM, Streamer), AFI(NULL), MCP(NULL) { + explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) + : AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) { Subtarget = &TM.getSubtarget<ARMSubtarget>(); } @@ -87,80 +83,123 @@ namespace { void printInstructionThroughMCStreamer(const MachineInstr *MI); - void printOperand(const MachineInstr *MI, int OpNum, + void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O, const char *Modifier = 0); - void printSOImmOperand(const MachineInstr *MI, int OpNum); - void printSOImm2PartOperand(const MachineInstr *MI, int OpNum); - void printSORegOperand(const MachineInstr *MI, int OpNum); - void printAddrMode2Operand(const MachineInstr *MI, int OpNum); - void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum); - void printAddrMode3Operand(const MachineInstr *MI, int OpNum); - void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum); - void printAddrMode4Operand(const MachineInstr *MI, int OpNum, + void printSOImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O); + void printSOImm2PartOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printSORegOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printAddrMode2Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printAddrMode3Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printAddrMode4Operand(const MachineInstr *MI, int OpNum,raw_ostream &O, const char *Modifier = 0); - void printAddrMode5Operand(const MachineInstr *MI, int OpNum, + void printAddrMode5Operand(const MachineInstr *MI, int OpNum,raw_ostream &O, const char *Modifier = 0); - void printAddrMode6Operand(const MachineInstr *MI, int OpNum); - void printAddrMode6OffsetOperand(const MachineInstr *MI, int OpNum); + void printAddrMode6Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printAddrMode6OffsetOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); void printAddrModePCOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O, const char *Modifier = 0); - void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum); - - void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum); - void printThumbITMask(const MachineInstr *MI, int OpNum); - void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum); + void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum, + raw_ostream &O); + + void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printThumbITMask(const MachineInstr *MI, int OpNum, raw_ostream &O); + void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O, unsigned Scale); - void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum); - void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum); - void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum); - void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum); - - void printT2SOOperand(const MachineInstr *MI, int OpNum); - void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum); - void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum); - void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum); - void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum); - void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum) {} - void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum); - - void printCPSOptionOperand(const MachineInstr *MI, int OpNum) {} - void printMSRMaskOperand(const MachineInstr *MI, int OpNum) {} - void printNegZeroOperand(const MachineInstr *MI, int OpNum) {} - void printPredicateOperand(const MachineInstr *MI, int OpNum); - void printMandatoryPredicateOperand(const MachineInstr *MI, int OpNum); - void printSBitModifierOperand(const MachineInstr *MI, int OpNum); - void printPCLabel(const MachineInstr *MI, int OpNum); - void printRegisterList(const MachineInstr *MI, int OpNum); + void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + + void printT2SOOperand(const MachineInstr *MI, int OpNum, raw_ostream &O); + void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) {} + void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + + void printCPSOptionOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) {} + void printMSRMaskOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) {} + void printNegZeroOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) {} + void printPredicateOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printMandatoryPredicateOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printSBitModifierOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printPCLabel(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printRegisterList(const MachineInstr *MI, int OpNum, + raw_ostream &O); void printCPInstOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O, const char *Modifier); - void printJTBlockOperand(const MachineInstr *MI, int OpNum); - void printJT2BlockOperand(const MachineInstr *MI, int OpNum); - void printTBAddrMode(const MachineInstr *MI, int OpNum); - void printNoHashImmediate(const MachineInstr *MI, int OpNum); - void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum); - void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum); - - void printHex8ImmOperand(const MachineInstr *MI, int OpNum) { + void printJTBlockOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printJT2BlockOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printTBAddrMode(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printNoHashImmediate(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + + void printHex8ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff); } - void printHex16ImmOperand(const MachineInstr *MI, int OpNum) { + void printHex16ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff); } - void printHex32ImmOperand(const MachineInstr *MI, int OpNum) { + void printHex32ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff); } - void printHex64ImmOperand(const MachineInstr *MI, int OpNum) { + void printHex64ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm()); } virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, - unsigned AsmVariant, const char *ExtraCode); + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O); virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, - const char *ExtraCode); + const char *ExtraCode, raw_ostream &O); - void printInstruction(const MachineInstr *MI); // autogenerated. + void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen static const char *getRegisterName(unsigned RegNo); virtual void EmitInstruction(const MachineInstr *MI); @@ -178,6 +217,14 @@ namespace { /// EmitMachineConstantPoolValue - Print a machine constantpool value to /// the .s file. virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) { + SmallString<128> Str; + raw_svector_ostream OS(Str); + EmitMachineConstantPoolValue(MCPV, OS); + OutStreamer.EmitRawText(OS.str()); + } + + void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV, + raw_ostream &O) { switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) { case 1: O << MAI->getData8bitsDirective(0); break; case 2: O << MAI->getData16bitsDirective(0); break; @@ -186,14 +233,11 @@ namespace { } ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV); - SmallString<128> TmpNameStr; if (ACPV->isLSDA()) { - raw_svector_ostream(TmpNameStr) << MAI->getPrivateGlobalPrefix() << - "_LSDA_" << getFunctionNumber(); - O << TmpNameStr.str(); + O << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber(); } else if (ACPV->isBlockAddress()) { - O << GetBlockAddressSymbol(ACPV->getBlockAddress())->getName(); + O << *GetBlockAddressSymbol(ACPV->getBlockAddress()); } else if (ACPV->isGlobalValue()) { GlobalValue *GV = ACPV->getGV(); bool isIndirect = Subtarget->isTargetDarwin() && @@ -228,14 +272,6 @@ namespace { O << "-."; O << ')'; } - OutStreamer.AddBlankLine(); - } - - void getAnalysisUsage(AnalysisUsage &AU) const { - AsmPrinter::getAnalysisUsage(AU); - AU.setPreservesAll(); - AU.addRequired<MachineModuleInfo>(); - AU.addRequired<DwarfWriter>(); } }; } // end of anonymous namespace @@ -244,11 +280,17 @@ namespace { void ARMAsmPrinter::EmitFunctionEntryLabel() { if (AFI->isThumbFunction()) { - O << "\t.code\t16\n"; - O << "\t.thumb_func"; - if (Subtarget->isTargetDarwin()) - O << '\t' << *CurrentFnSym; - O << '\n'; + OutStreamer.EmitRawText(StringRef("\t.code\t16")); + if (!Subtarget->isTargetDarwin()) + OutStreamer.EmitRawText(StringRef("\t.thumb_func")); + else { + // This needs to emit to a temporary string to get properly quoted + // MCSymbols when they have spaces in them. + SmallString<128> Tmp; + raw_svector_ostream OS(Tmp); + OS << "\t.thumb_func\t" << *CurrentFnSym; + OutStreamer.EmitRawText(OS.str()); + } } OutStreamer.EmitLabel(CurrentFnSym); @@ -265,7 +307,7 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) { } void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, - const char *Modifier) { + raw_ostream &O, const char *Modifier) { const MachineOperand &MO = MI->getOperand(OpNum); unsigned TF = MO.getTargetFlags(); @@ -276,15 +318,16 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, unsigned Reg = MO.getReg(); assert(TargetRegisterInfo::isPhysicalRegister(Reg)); if (Modifier && strcmp(Modifier, "dregpair") == 0) { - unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0 - unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1 + unsigned DRegLo = TM.getRegisterInfo()->getSubReg(Reg, 5);// arm_dsubreg_0 + unsigned DRegHi = TM.getRegisterInfo()->getSubReg(Reg, 6);// arm_dsubreg_1 O << '{' << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi) << '}'; } else if (Modifier && strcmp(Modifier, "lane") == 0) { unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg); - unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1, - &ARM::DPR_VFP2RegClass); + unsigned DReg = + TM.getRegisterInfo()->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1, + &ARM::DPR_VFP2RegClass); O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']'; } else { assert(!MO.getSubReg() && "Subregs should be eliminated!"); @@ -319,7 +362,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, O << ":upper16:"; O << *Mang->getSymbol(GV); - printOffset(MO.getOffset()); + printOffset(MO.getOffset(), O); if (isCallOp && Subtarget->isTargetELF() && TM.getRelocationModel() == Reloc::PIC_) @@ -344,7 +387,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, } } -static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm, +static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm, const MCAsmInfo *MAI) { // Break it up into two parts that make up a shifter immediate. V = ARM_AM::getSOImmVal(V); @@ -359,8 +402,7 @@ static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm, O << "#" << Imm << ", " << Rot; // Pretty printed version. if (VerboseAsm) { - O.PadToColumn(MAI->getCommentColumn()); - O << MAI->getCommentString() << ' '; + O << "\t" << MAI->getCommentString() << ' '; O << (int)ARM_AM::rotr32(Imm, Rot); } } else { @@ -370,28 +412,30 @@ static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm, /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit /// immediate in bits 0-7. -void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNum); assert(MO.isImm() && "Not a valid so_imm value!"); - printSOImm(O, MO.getImm(), VerboseAsm, MAI); + printSOImm(O, MO.getImm(), isVerbose(), MAI); } /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov' /// followed by an 'orr' to materialize. -void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNum); assert(MO.isImm() && "Not a valid so_imm value!"); unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm()); unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm()); - printSOImm(O, V1, VerboseAsm, MAI); + printSOImm(O, V1, isVerbose(), MAI); O << "\n\torr"; - printPredicateOperand(MI, 2); + printPredicateOperand(MI, 2, O); O << "\t"; - printOperand(MI, 0); + printOperand(MI, 0, O); O << ", "; - printOperand(MI, 0); + printOperand(MI, 0, O); O << ", "; - printSOImm(O, V2, VerboseAsm, MAI); + printSOImm(O, V2, isVerbose(), MAI); } // so_reg is a 4-operand unit corresponding to register forms of the A5.1 @@ -399,7 +443,8 @@ void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) { // REG 0 0 - e.g. R5 // REG REG 0,SH_OPC - e.g. R5, ROR R3 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3 -void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) { +void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); const MachineOperand &MO3 = MI->getOperand(Op+2); @@ -419,13 +464,14 @@ void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) { } } -void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) { +void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); const MachineOperand &MO3 = MI->getOperand(Op+2); if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op); + printOperand(MI, Op, O); return; } @@ -451,7 +497,8 @@ void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) { O << "]"; } -void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){ +void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); @@ -473,7 +520,8 @@ void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){ << " #" << ShImm; } -void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) { +void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); const MachineOperand &MO3 = MI->getOperand(Op+2); @@ -496,7 +544,8 @@ void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) { O << "]"; } -void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){ +void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op, + raw_ostream &O){ const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); @@ -514,6 +563,7 @@ void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){ } void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op, + raw_ostream &O, const char *Modifier) { const MachineOperand &MO2 = MI->getOperand(Op+1); ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm()); @@ -524,17 +574,18 @@ void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op, if (Mode == ARM_AM::ia) O << ".w"; } else { - printOperand(MI, Op); + printOperand(MI, Op, O); } } void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op, + raw_ostream &O, const char *Modifier) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op); + printOperand(MI, Op, O); return; } @@ -560,7 +611,8 @@ void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op, O << "]"; } -void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) { +void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); @@ -572,7 +624,8 @@ void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) { O << "]"; } -void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op){ +void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op, + raw_ostream &O){ const MachineOperand &MO = MI->getOperand(Op); if (MO.getReg() == 0) O << "!"; @@ -581,9 +634,10 @@ void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op){ } void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op, + raw_ostream &O, const char *Modifier) { if (Modifier && strcmp(Modifier, "label") == 0) { - printPCLabel(MI, Op+1); + printPCLabel(MI, Op+1, O); return; } @@ -593,7 +647,8 @@ void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op, } void -ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) { +ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(Op); uint32_t v = ~MO.getImm(); int32_t lsb = CountTrailingZeros_32(v); @@ -604,12 +659,14 @@ ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) { //===--------------------------------------------------------------------===// -void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op) { +void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op, + raw_ostream &O) { O << "#" << MI->getOperand(Op).getImm() * 4; } void -ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) { +ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op, + raw_ostream &O) { // (3 - the number of trailing zeros) is the number of then / else. unsigned Mask = MI->getOperand(Op).getImm(); unsigned CondBit0 = Mask >> 4 & 1; @@ -625,7 +682,8 @@ ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) { } void -ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) { +ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); O << "[" << getRegisterName(MO1.getReg()); @@ -634,13 +692,14 @@ ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) { void ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op, + raw_ostream &O, unsigned Scale) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); const MachineOperand &MO3 = MI->getOperand(Op+2); if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op); + printOperand(MI, Op, O); return; } @@ -653,19 +712,23 @@ ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op, } void -ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) { - printThumbAddrModeRI5Operand(MI, Op, 1); +ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op, + raw_ostream &O) { + printThumbAddrModeRI5Operand(MI, Op, O, 1); } void -ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) { - printThumbAddrModeRI5Operand(MI, Op, 2); +ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op, + raw_ostream &O) { + printThumbAddrModeRI5Operand(MI, Op, O, 2); } void -ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) { - printThumbAddrModeRI5Operand(MI, Op, 4); +ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op, + raw_ostream &O) { + printThumbAddrModeRI5Operand(MI, Op, O, 4); } -void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) { +void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); O << "[" << getRegisterName(MO1.getReg()); @@ -680,7 +743,8 @@ void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) { // register with shift forms. // REG 0 0 - e.g. R5 // REG IMM, SH_OPC - e.g. R5, LSL #3 -void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); const MachineOperand &MO2 = MI->getOperand(OpNum+1); @@ -698,7 +762,8 @@ void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) { } void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI, - int OpNum) { + int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); const MachineOperand &MO2 = MI->getOperand(OpNum+1); @@ -711,7 +776,8 @@ void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI, } void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI, - int OpNum) { + int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); const MachineOperand &MO2 = MI->getOperand(OpNum+1); @@ -727,7 +793,8 @@ void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI, } void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI, - int OpNum) { + int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); const MachineOperand &MO2 = MI->getOperand(OpNum+1); @@ -743,7 +810,8 @@ void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI, } void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, - int OpNum) { + int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); int32_t OffImm = (int32_t)MO1.getImm(); // Don't print +0. @@ -754,7 +822,8 @@ void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, } void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI, - int OpNum) { + int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); const MachineOperand &MO2 = MI->getOperand(OpNum+1); const MachineOperand &MO3 = MI->getOperand(OpNum+2); @@ -775,19 +844,22 @@ void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI, //===--------------------------------------------------------------------===// -void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); if (CC != ARMCC::AL) O << ARMCondCodeToString(CC); } void ARMAsmPrinter::printMandatoryPredicateOperand(const MachineInstr *MI, - int OpNum) { + int OpNum, + raw_ostream &O) { ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); O << ARMCondCodeToString(CC); } -void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){ +void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O){ unsigned Reg = MI->getOperand(OpNum).getReg(); if (Reg) { assert(Reg == ARM::CPSR && "Expect ARM CPSR register!"); @@ -795,25 +867,27 @@ void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){ } } -void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum, + raw_ostream &O) { int Id = (int)MI->getOperand(OpNum).getImm(); O << MAI->getPrivateGlobalPrefix() << "PC" << getFunctionNumber() << "_" << Id; } -void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << "{"; for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) { if (MI->getOperand(i).isImplicit()) continue; if ((int)i != OpNum) O << ", "; - printOperand(MI, i); + printOperand(MI, i, O); } O << "}"; } void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum, - const char *Modifier) { + raw_ostream &O, const char *Modifier) { assert(Modifier && "This operand only works with a modifier!"); // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the // data itself. @@ -852,7 +926,8 @@ GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const { return OutContext.GetOrCreateSymbol(Name.str()); } -void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!"); const MachineOperand &MO1 = MI->getOperand(OpNum); @@ -860,7 +935,9 @@ void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) { unsigned JTI = MO1.getIndex(); MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm()); - OutStreamer.EmitLabel(JTISymbol); + // Can't use EmitLabel until instprinter happens, label comes out in the wrong + // order. + O << *JTISymbol << ":\n"; const char *JTEntryDirective = MAI->getData32bitsDirective(); @@ -892,13 +969,17 @@ void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) { } } -void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id unsigned JTI = MO1.getIndex(); MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm()); - OutStreamer.EmitLabel(JTISymbol); + + // Can't use EmitLabel until instprinter happens, label comes out in the wrong + // order. + O << *JTISymbol << ":\n"; const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); @@ -924,48 +1005,44 @@ void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) { if (i != e-1) O << '\n'; } - - // Make sure the instruction that follows TBB is 2-byte aligned. - // FIXME: Constant island pass should insert an "ALIGN" instruction instead. - if (ByteOffset && (JTBBs.size() & 1)) { - O << '\n'; - EmitAlignment(1); - } } -void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg()); if (MI->getOpcode() == ARM::t2TBH) O << ", lsl #1"; O << ']'; } -void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << MI->getOperand(OpNum).getImm(); } -void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { const ConstantFP *FP = MI->getOperand(OpNum).getFPImm(); O << '#' << FP->getValueAPF().convertToFloat(); - if (VerboseAsm) { - O.PadToColumn(MAI->getCommentColumn()); - O << MAI->getCommentString() << ' '; + if (isVerbose()) { + O << "\t\t" << MAI->getCommentString() << ' '; WriteAsOperand(O, FP, /*PrintType=*/false); } } -void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { const ConstantFP *FP = MI->getOperand(OpNum).getFPImm(); O << '#' << FP->getValueAPF().convertToDouble(); - if (VerboseAsm) { - O.PadToColumn(MAI->getCommentColumn()); - O << MAI->getCommentString() << ' '; + if (isVerbose()) { + O << "\t\t" << MAI->getCommentString() << ' '; WriteAsOperand(O, FP, /*PrintType=*/false); } } bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, - unsigned AsmVariant, const char *ExtraCode){ + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O) { // Does this asm operand have a single letter operand modifier? if (ExtraCode && ExtraCode[0]) { if (ExtraCode[1] != 0) return true; // Unknown modifier. @@ -981,11 +1058,11 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, case 'c': // Don't print "#" before an immediate operand. if (!MI->getOperand(OpNum).isImm()) return true; - printNoHashImmediate(MI, OpNum); + printNoHashImmediate(MI, OpNum, O); return false; case 'P': // Print a VFP double precision register. case 'q': // Print a NEON quad precision register. - printOperand(MI, OpNum); + printOperand(MI, OpNum, O); return false; case 'Q': if (TM.getTargetData()->isLittleEndian()) @@ -1005,13 +1082,14 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, } } - printOperand(MI, OpNum); + printOperand(MI, OpNum, O); return false; } bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, - const char *ExtraCode) { + const char *ExtraCode, + raw_ostream &O) { if (ExtraCode && ExtraCode[0]) return true; // Unknown modifier. @@ -1024,14 +1102,21 @@ bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { if (EnableMCInst) { printInstructionThroughMCStreamer(MI); - } else { - int Opc = MI->getOpcode(); - if (Opc == ARM::CONSTPOOL_ENTRY) - EmitAlignment(2); - - printInstruction(MI); - OutStreamer.AddBlankLine(); + return; } + + if (MI->getOpcode() == ARM::CONSTPOOL_ENTRY) + EmitAlignment(2); + + SmallString<128> Str; + raw_svector_ostream OS(Str); + printInstruction(MI, OS); + OutStreamer.EmitRawText(OS.str()); + + // Make sure the instruction that follows TBB is 2-byte aligned. + // FIXME: Constant island pass should insert an "ALIGN" instruction instead. + if (MI->getOpcode() == ARM::t2TBB) + EmitAlignment(1); } void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) { @@ -1066,38 +1151,48 @@ void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) { } // Use unified assembler syntax. - O << "\t.syntax unified\n"; + OutStreamer.EmitRawText(StringRef("\t.syntax unified")); // Emit ARM Build Attributes if (Subtarget->isTargetELF()) { // CPU Type std::string CPUString = Subtarget->getCPUString(); if (CPUString != "generic") - O << "\t.cpu " << CPUString << '\n'; + OutStreamer.EmitRawText("\t.cpu " + Twine(CPUString)); // FIXME: Emit FPU type if (Subtarget->hasVFP2()) - O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n"; + OutStreamer.EmitRawText("\t.eabi_attribute " + + Twine(ARMBuildAttrs::VFP_arch) + ", 2"); // Signal various FP modes. - if (!UnsafeFPMath) - O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n" - << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n"; - + if (!UnsafeFPMath) { + OutStreamer.EmitRawText("\t.eabi_attribute " + + Twine(ARMBuildAttrs::ABI_FP_denormal) + ", 1"); + OutStreamer.EmitRawText("\t.eabi_attribute " + + Twine(ARMBuildAttrs::ABI_FP_exceptions) + ", 1"); + } + if (FiniteOnlyFPMath()) - O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n"; + OutStreamer.EmitRawText("\t.eabi_attribute " + + Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 1"); else - O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n"; + OutStreamer.EmitRawText("\t.eabi_attribute " + + Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 3"); // 8-bytes alignment stuff. - O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n" - << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n"; + OutStreamer.EmitRawText("\t.eabi_attribute " + + Twine(ARMBuildAttrs::ABI_align8_needed) + ", 1"); + OutStreamer.EmitRawText("\t.eabi_attribute " + + Twine(ARMBuildAttrs::ABI_align8_preserved) + ", 1"); // Hard float. Use both S and D registers and conform to AAPCS-VFP. - if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) - O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n" - << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n"; - + if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) { + OutStreamer.EmitRawText("\t.eabi_attribute " + + Twine(ARMBuildAttrs::ABI_HardFP_use) + ", 3"); + OutStreamer.EmitRawText("\t.eabi_attribute " + + Twine(ARMBuildAttrs::ABI_VFP_args) + ", 1"); + } // FIXME: Should we signal R9 usage? } } @@ -1111,8 +1206,6 @@ void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) { MachineModuleInfoMachO &MMIMacho = MMI->getObjFileInfo<MachineModuleInfoMachO>(); - O << '\n'; - // Output non-lazy-pointers for external and common global variables. MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList(); @@ -1308,10 +1401,9 @@ void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) { static MCInstPrinter *createARMMCInstPrinter(const Target &T, unsigned SyntaxVariant, - const MCAsmInfo &MAI, - raw_ostream &O) { + const MCAsmInfo &MAI) { if (SyntaxVariant == 0) - return new ARMInstPrinter(O, MAI, false); + return new ARMInstPrinter(MAI, false); return 0; } diff --git a/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp index 30763a9952e4..ef5ead6e473b 100644 --- a/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp +++ b/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp @@ -98,7 +98,7 @@ static unsigned NextReg(unsigned Reg) { } } -void ARMInstPrinter::printInst(const MCInst *MI) { +void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) { // Check for MOVs and print canonical forms, instead. if (MI->getOpcode() == ARM::MOVs) { const MCOperand &Dst = MI->getOperand(0); @@ -107,8 +107,8 @@ void ARMInstPrinter::printInst(const MCInst *MI) { const MCOperand &MO3 = MI->getOperand(3); O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); - printSBitModifierOperand(MI, 6); - printPredicateOperand(MI, 4); + printSBitModifierOperand(MI, 6, O); + printPredicateOperand(MI, 4, O); O << '\t' << getRegisterName(Dst.getReg()) << ", " << getRegisterName(MO1.getReg()); @@ -133,9 +133,9 @@ void ARMInstPrinter::printInst(const MCInst *MI) { const MCOperand &MO1 = MI->getOperand(2); if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) { O << '\t' << "push"; - printPredicateOperand(MI, 3); + printPredicateOperand(MI, 3, O); O << '\t'; - printRegisterList(MI, 5); + printRegisterList(MI, 5, O); return; } } @@ -146,9 +146,9 @@ void ARMInstPrinter::printInst(const MCInst *MI) { const MCOperand &MO1 = MI->getOperand(2); if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) { O << '\t' << "pop"; - printPredicateOperand(MI, 3); + printPredicateOperand(MI, 3, O); O << '\t'; - printRegisterList(MI, 5); + printRegisterList(MI, 5, O); return; } } @@ -159,9 +159,9 @@ void ARMInstPrinter::printInst(const MCInst *MI) { const MCOperand &MO1 = MI->getOperand(2); if (ARM_AM::getAM5SubMode(MO1.getImm()) == ARM_AM::db) { O << '\t' << "vpush"; - printPredicateOperand(MI, 3); + printPredicateOperand(MI, 3, O); O << '\t'; - printRegisterList(MI, 5); + printRegisterList(MI, 5, O); return; } } @@ -172,18 +172,18 @@ void ARMInstPrinter::printInst(const MCInst *MI) { const MCOperand &MO1 = MI->getOperand(2); if (ARM_AM::getAM5SubMode(MO1.getImm()) == ARM_AM::ia) { O << '\t' << "vpop"; - printPredicateOperand(MI, 3); + printPredicateOperand(MI, 3, O); O << '\t'; - printRegisterList(MI, 5); + printRegisterList(MI, 5, O); return; } } - printInstruction(MI); + printInstruction(MI, O); } void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - const char *Modifier) { + raw_ostream &O, const char *Modifier) { const MCOperand &Op = MI->getOperand(OpNo); if (Op.isReg()) { unsigned Reg = Op.getReg(); @@ -247,7 +247,8 @@ static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm, /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit /// immediate in bits 0-7. -void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &MO = MI->getOperand(OpNum); assert(MO.isImm() && "Not a valid so_imm value!"); printSOImm(O, MO.getImm(), VerboseAsm, &MAI); @@ -255,7 +256,8 @@ void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum) { /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov' /// followed by an 'orr' to materialize. -void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { // FIXME: REMOVE this method. abort(); } @@ -265,7 +267,8 @@ void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum) { // REG 0 0 - e.g. R5 // REG REG 0,SH_OPC - e.g. R5, ROR R3 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3 -void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); const MCOperand &MO3 = MI->getOperand(OpNum+2); @@ -286,13 +289,14 @@ void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum) { } -void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op) { +void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(Op); const MCOperand &MO2 = MI->getOperand(Op+1); const MCOperand &MO3 = MI->getOperand(Op+2); if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op); + printOperand(MI, Op, O); return; } @@ -319,7 +323,8 @@ void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op) { } void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -341,7 +346,8 @@ void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI, << " #" << ShImm; } -void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); const MCOperand &MO3 = MI->getOperand(OpNum+2); @@ -362,7 +368,8 @@ void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum) { } void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -381,6 +388,7 @@ void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI, void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O, const char *Modifier) { const MCOperand &MO2 = MI->getOperand(OpNum+1); ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm()); @@ -391,17 +399,18 @@ void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum, if (Mode == ARM_AM::ia) O << ".w"; } else { - printOperand(MI, OpNum); + printOperand(MI, OpNum, O); } } void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O, const char *Modifier) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, OpNum); + printOperand(MI, OpNum, O); return; } @@ -425,7 +434,8 @@ void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum, O << "]"; } -void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -438,7 +448,8 @@ void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum) { } void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO = MI->getOperand(OpNum); if (MO.getReg() == 0) O << "!"; @@ -447,12 +458,14 @@ void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI, } void ARMInstPrinter::printAddrModePCOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O, const char *Modifier) { assert(0 && "FIXME: Implement printAddrModePCOperand"); } void ARMInstPrinter::printBitfieldInvMaskImmOperand (const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO = MI->getOperand(OpNum); uint32_t v = ~MO.getImm(); int32_t lsb = CountTrailingZeros_32(v); @@ -461,7 +474,8 @@ void ARMInstPrinter::printBitfieldInvMaskImmOperand (const MCInst *MI, O << '#' << lsb << ", #" << width; } -void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { O << "{"; for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) { if (i != OpNum) O << ", "; @@ -470,7 +484,8 @@ void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum) { O << "}"; } -void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNum); unsigned option = Op.getImm(); unsigned mode = option & 31; @@ -492,7 +507,8 @@ void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum) { O << '#' << mode; } -void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNum); unsigned Mask = Op.getImm(); if (Mask) { @@ -504,7 +520,8 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum) { } } -void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum){ +void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNum); O << '#'; if (Op.getImm() < 0) @@ -513,19 +530,22 @@ void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum){ O << Op.getImm(); } -void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); if (CC != ARMCC::AL) O << ARMCondCodeToString(CC); } void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); O << ARMCondCodeToString(CC); } -void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum){ +void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { if (MI->getOperand(OpNum).getReg()) { assert(MI->getOperand(OpNum).getReg() == ARM::CPSR && "Expect ARM CPSR register!"); @@ -536,26 +556,31 @@ void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum){ void ARMInstPrinter::printCPInstOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O, const char *Modifier) { // FIXME: remove this. abort(); } -void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { O << MI->getOperand(OpNum).getImm(); } -void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { // FIXME: remove this. abort(); } -void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { O << "#" << MI->getOperand(OpNum).getImm() * 4; } -void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { // (3 - the number of trailing zeros) is the number of then / else. unsigned Mask = MI->getOperand(OpNum).getImm(); unsigned CondBit0 = Mask >> 4 & 1; @@ -570,8 +595,8 @@ void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum) { } } -void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op) -{ +void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(Op); const MCOperand &MO2 = MI->getOperand(Op+1); O << "[" << getRegisterName(MO1.getReg()); @@ -579,13 +604,14 @@ void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op) } void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op, + raw_ostream &O, unsigned Scale) { const MCOperand &MO1 = MI->getOperand(Op); const MCOperand &MO2 = MI->getOperand(Op+1); const MCOperand &MO3 = MI->getOperand(Op+2); if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op); + printOperand(MI, Op, O); return; } @@ -597,22 +623,23 @@ void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op, O << "]"; } -void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op) -{ - printThumbAddrModeRI5Operand(MI, Op, 1); +void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op, + raw_ostream &O) { + printThumbAddrModeRI5Operand(MI, Op, O, 1); } -void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op) -{ - printThumbAddrModeRI5Operand(MI, Op, 2); +void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op, + raw_ostream &O) { + printThumbAddrModeRI5Operand(MI, Op, O, 2); } -void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op) -{ - printThumbAddrModeRI5Operand(MI, Op, 4); +void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op, + raw_ostream &O) { + printThumbAddrModeRI5Operand(MI, Op, O, 4); } -void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI,unsigned Op) { +void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(Op); const MCOperand &MO2 = MI->getOperand(Op+1); O << "[" << getRegisterName(MO1.getReg()); @@ -621,7 +648,8 @@ void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI,unsigned Op) { O << "]"; } -void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg()); if (MI->getOpcode() == ARM::t2TBH) O << ", lsl #1"; @@ -632,7 +660,8 @@ void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum) { // register with shift forms. // REG 0 0 - e.g. R5 // REG IMM, SH_OPC - e.g. R5, LSL #3 -void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -649,7 +678,8 @@ void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum) { } void ARMInstPrinter::printT2AddrModeImm12Operand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -662,7 +692,8 @@ void ARMInstPrinter::printT2AddrModeImm12Operand(const MCInst *MI, } void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -678,7 +709,8 @@ void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI, } void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -694,7 +726,8 @@ void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI, } void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); int32_t OffImm = (int32_t)MO1.getImm(); // Don't print +0. @@ -705,7 +738,8 @@ void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI, } void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); int32_t OffImm = (int32_t)MO1.getImm() / 4; // Don't print +0. @@ -716,7 +750,8 @@ void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, } void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); const MCOperand &MO3 = MI->getOperand(OpNum+2); @@ -734,11 +769,13 @@ void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI, O << "]"; } -void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { O << '#' << MI->getOperand(OpNum).getImm(); } -void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { O << '#' << MI->getOperand(OpNum).getImm(); } diff --git a/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h b/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h index d41b5dfa6c5b..dd006fc52e74 100644 --- a/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h +++ b/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h @@ -22,79 +22,96 @@ namespace llvm { class ARMInstPrinter : public MCInstPrinter { bool VerboseAsm; public: - ARMInstPrinter(raw_ostream &O, const MCAsmInfo &MAI, bool verboseAsm) - : MCInstPrinter(O, MAI), VerboseAsm(verboseAsm) {} + ARMInstPrinter(const MCAsmInfo &MAI, bool verboseAsm) + : MCInstPrinter(MAI), VerboseAsm(verboseAsm) {} - virtual void printInst(const MCInst *MI); + virtual void printInst(const MCInst *MI, raw_ostream &O); // Autogenerated by tblgen. - void printInstruction(const MCInst *MI); + void printInstruction(const MCInst *MI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); - void printOperand(const MCInst *MI, unsigned OpNo, + void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, const char *Modifier = 0); - void printSOImmOperand(const MCInst *MI, unsigned OpNum); - void printSOImm2PartOperand(const MCInst *MI, unsigned OpNum); + void printSOImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printSOImm2PartOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); - void printSORegOperand(const MCInst *MI, unsigned OpNum); - void printAddrMode2Operand(const MCInst *MI, unsigned OpNum); - void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum); - void printAddrMode3Operand(const MCInst *MI, unsigned OpNum); - void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum); - void printAddrMode4Operand(const MCInst *MI, unsigned OpNum, + void printSORegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printAddrMode4Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O, const char *Modifier = 0); - void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, + void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O, const char *Modifier = 0); - void printAddrMode6Operand(const MCInst *MI, unsigned OpNum); - void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum); - void printAddrModePCOperand(const MCInst *MI, unsigned OpNum, + void printAddrMode6Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printAddrModePCOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O, const char *Modifier = 0); - void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum); + void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); - void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum); - void printThumbITMask(const MCInst *MI, unsigned OpNum); - void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum); + void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); void printThumbAddrModeRI5Operand(const MCInst *MI, unsigned OpNum, - unsigned Scale); - void printThumbAddrModeS1Operand(const MCInst *MI, unsigned OpNum); - void printThumbAddrModeS2Operand(const MCInst *MI, unsigned OpNum); - void printThumbAddrModeS4Operand(const MCInst *MI, unsigned OpNum); - void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum); + raw_ostream &O, unsigned Scale); + void printThumbAddrModeS1Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printThumbAddrModeS2Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printThumbAddrModeS4Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); - void printT2SOOperand(const MCInst *MI, unsigned OpNum); - void printT2AddrModeImm12Operand(const MCInst *MI, unsigned OpNum); - void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum); - void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum); - void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum); - void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum); - void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum); + void printT2SOOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printT2AddrModeImm12Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); - void printCPSOptionOperand(const MCInst *MI, unsigned OpNum); - void printMSRMaskOperand(const MCInst *MI, unsigned OpNum); - void printNegZeroOperand(const MCInst *MI, unsigned OpNum); - void printPredicateOperand(const MCInst *MI, unsigned OpNum); - void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum); - void printSBitModifierOperand(const MCInst *MI, unsigned OpNum); - void printRegisterList(const MCInst *MI, unsigned OpNum); - void printCPInstOperand(const MCInst *MI, unsigned OpNum, + void printCPSOptionOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printNegZeroOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printSBitModifierOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printRegisterList(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printCPInstOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O, const char *Modifier); - void printJTBlockOperand(const MCInst *MI, unsigned OpNum) {} - void printJT2BlockOperand(const MCInst *MI, unsigned OpNum) {} - void printTBAddrMode(const MCInst *MI, unsigned OpNum); - void printNoHashImmediate(const MCInst *MI, unsigned OpNum); - void printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum); - void printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum); - void printHex8ImmOperand(const MCInst *MI, int OpNum) {} - void printHex16ImmOperand(const MCInst *MI, int OpNum) {} - void printHex32ImmOperand(const MCInst *MI, int OpNum) {} - void printHex64ImmOperand(const MCInst *MI, int OpNum) {} + void printJTBlockOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {} + void printJT2BlockOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {} + void printTBAddrMode(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printNoHashImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printHex8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {} + void printHex16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {} + void printHex32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {} + void printHex64ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {} - void printPCLabel(const MCInst *MI, unsigned OpNum); + void printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O); // FIXME: Implement. - void PrintSpecial(const MCInst *MI, const char *Kind) {} + void PrintSpecial(const MCInst *MI, raw_ostream &O, const char *Kind) {} }; } diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 04313400b8d9..47c31043d9c0 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -380,11 +380,18 @@ bool ARMDisassembler::getInstruction(MCInst &MI, raw_ostream &os) const { // The machine instruction. uint32_t insn; + uint8_t bytes[4]; // We want to read exactly 4 bytes of data. - if (Region.readBytes(Address, 4, (uint8_t*)&insn, NULL) == -1) + if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) return false; + // Encoded as a small-endian 32-bit word in the stream. + insn = (bytes[3] << 24) | + (bytes[2] << 16) | + (bytes[1] << 8) | + (bytes[0] << 0); + unsigned Opcode = decodeARMInstruction(insn); ARMFormat Format = ARMFormats[Opcode]; Size = 4; @@ -414,9 +421,15 @@ bool ThumbDisassembler::getInstruction(MCInst &MI, const MemoryObject &Region, uint64_t Address, raw_ostream &os) const { - // The machine instruction. + // The Thumb instruction stream is a sequence of halhwords. + + // This represents the first halfword as well as the machine instruction + // passed to decodeThumbInstruction(). For 16-bit Thumb instruction, the top + // halfword of insn is 0x00 0x00; otherwise, the first halfword is moved to + // the top half followed by the second halfword. uint32_t insn = 0; - uint32_t insn1 = 0; + // Possible second halfword. + uint16_t insn1 = 0; // A6.1 Thumb instruction set encoding // @@ -429,9 +442,12 @@ bool ThumbDisassembler::getInstruction(MCInst &MI, // Otherwise, the halfword is a 16-bit instruction. // Read 2 bytes of data first. - if (Region.readBytes(Address, 2, (uint8_t*)&insn, NULL) == -1) + uint8_t bytes[2]; + if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) return false; + // Encoded as a small-endian 16-bit halfword in the stream. + insn = (bytes[1] << 8) | bytes[0]; unsigned bits15_11 = slice(insn, 15, 11); bool IsThumb2 = false; @@ -439,8 +455,10 @@ bool ThumbDisassembler::getInstruction(MCInst &MI, // { 0b11101 /* 0x1D */, 0b11110 /* 0x1E */, ob11111 /* 0x1F */ }. if (bits15_11 == 0x1D || bits15_11 == 0x1E || bits15_11 == 0x1F) { IsThumb2 = true; - if (Region.readBytes(Address + 2, 2, (uint8_t*)&insn1, NULL) == -1) + if (Region.readBytes(Address + 2, 2, (uint8_t*)bytes, NULL) == -1) return false; + // Encoded as a small-endian 16-bit halfword in the stream. + insn1 = (bytes[1] << 8) | bytes[0]; insn = (insn << 16 | insn1); } diff --git a/lib/Target/ARM/Disassembler/Makefile b/lib/Target/ARM/Disassembler/Makefile deleted file mode 100644 index 031b6aca5a48..000000000000 --- a/lib/Target/ARM/Disassembler/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -##===- lib/Target/ARM/Disassembler/Makefile ----------------*- Makefile -*-===## -# -# The LLVM Compiler Infrastructure -# -# This file is distributed under the University of Illinois Open Source -# License. See LICENSE.TXT for details. -# -##===----------------------------------------------------------------------===## - -LEVEL = ../../../.. -LIBRARYNAME = LLVMARMDisassembler - -# Hack: we need to include 'main' arm target directory to grab private headers -CPPFLAGS = -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. - -include $(LEVEL)/Makefile.common diff --git a/lib/Target/ARM/Makefile b/lib/Target/ARM/Makefile index b7ed14abed78..a8dd38cb362e 100644 --- a/lib/Target/ARM/Makefile +++ b/lib/Target/ARM/Makefile @@ -16,9 +16,8 @@ BUILT_SOURCES = ARMGenRegisterInfo.h.inc ARMGenRegisterNames.inc \ ARMGenRegisterInfo.inc ARMGenInstrNames.inc \ ARMGenInstrInfo.inc ARMGenAsmWriter.inc \ ARMGenDAGISel.inc ARMGenSubtarget.inc \ - ARMGenCodeEmitter.inc ARMGenCallingConv.inc \ - ARMGenDecoderTables.inc + ARMGenCodeEmitter.inc ARMGenCallingConv.inc -DIRS = AsmPrinter AsmParser Disassembler TargetInfo +DIRS = AsmPrinter AsmParser TargetInfo include $(LEVEL)/Makefile.common diff --git a/lib/Target/Alpha/Alpha.td b/lib/Target/Alpha/Alpha.td index 6efdf554e176..4508eda897d2 100644 --- a/lib/Target/Alpha/Alpha.td +++ b/lib/Target/Alpha/Alpha.td @@ -47,11 +47,7 @@ include "AlphaSchedule.td" include "AlphaInstrInfo.td" -def AlphaInstrInfo : InstrInfo { - // Define how we want to layout our target-specific information field. - // let TSFlagsFields = []; - // let TSFlagsShifts = []; -} +def AlphaInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// // Alpha Processor Definitions diff --git a/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp index 093cf0528030..2a1f5559053f 100644 --- a/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp +++ b/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp @@ -20,7 +20,6 @@ #include "llvm/Type.h" #include "llvm/Assembly/Writer.h" #include "llvm/CodeGen/AsmPrinter.h" -#include "llvm/CodeGen/DwarfWriter.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCSymbol.h" @@ -28,8 +27,8 @@ #include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegistry.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/FormattedStream.h" +#include "llvm/ADT/SmallString.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; namespace { @@ -37,40 +36,42 @@ namespace { /// Unique incrementer for label values for referencing Global values. /// - explicit AlphaAsmPrinter(formatted_raw_ostream &o, TargetMachine &tm, - MCStreamer &Streamer) - : AsmPrinter(o, tm, Streamer) {} + explicit AlphaAsmPrinter(TargetMachine &tm, MCStreamer &Streamer) + : AsmPrinter(tm, Streamer) {} virtual const char *getPassName() const { return "Alpha Assembly Printer"; } - void printInstruction(const MachineInstr *MI); + void printInstruction(const MachineInstr *MI, raw_ostream &O); void EmitInstruction(const MachineInstr *MI) { - printInstruction(MI); - OutStreamer.AddBlankLine(); + SmallString<128> Str; + raw_svector_ostream OS(Str); + printInstruction(MI, OS); + OutStreamer.EmitRawText(OS.str()); } static const char *getRegisterName(unsigned RegNo); - void printOp(const MachineOperand &MO, bool IsCallOp = false); - void printOperand(const MachineInstr *MI, int opNum); - void printBaseOffsetPair(const MachineInstr *MI, int i, bool brackets=true); + void printOp(const MachineOperand &MO, raw_ostream &O); + void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); + void printBaseOffsetPair(const MachineInstr *MI, int i, raw_ostream &O, + bool brackets=true); virtual void EmitFunctionBodyStart(); virtual void EmitFunctionBodyEnd(); void EmitStartOfAsmFile(Module &M); bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode); + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O); bool PrintAsmMemoryOperand(const MachineInstr *MI, - unsigned OpNo, - unsigned AsmVariant, - const char *ExtraCode); + unsigned OpNo, unsigned AsmVariant, + const char *ExtraCode, raw_ostream &O); }; } // end of anonymous namespace #include "AlphaGenAsmWriter.inc" -void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum) -{ +void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(opNum); if (MO.getType() == MachineOperand::MO_Register) { assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && @@ -80,12 +81,12 @@ void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum) O << MO.getImm(); assert(MO.getImm() < (1 << 30)); } else { - printOp(MO); + printOp(MO, O); } } -void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) { +void AlphaAsmPrinter::printOp(const MachineOperand &MO, raw_ostream &O) { switch (MO.getType()) { case MachineOperand::MO_Register: O << getRegisterName(MO.getReg()); @@ -126,40 +127,37 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) { /// EmitFunctionBodyStart - Targets can override this to emit stuff before /// the first basic block in the function. void AlphaAsmPrinter::EmitFunctionBodyStart() { - O << "\t.ent " << *CurrentFnSym << "\n"; + OutStreamer.EmitRawText("\t.ent " + Twine(CurrentFnSym->getName())); } /// EmitFunctionBodyEnd - Targets can override this to emit stuff after /// the last basic block in the function. void AlphaAsmPrinter::EmitFunctionBodyEnd() { - O << "\t.end " << *CurrentFnSym << "\n"; + OutStreamer.EmitRawText("\t.end " + Twine(CurrentFnSym->getName())); } void AlphaAsmPrinter::EmitStartOfAsmFile(Module &M) { - if (TM.getSubtarget<AlphaSubtarget>().hasCT()) - O << "\t.arch ev6\n"; //This might need to be ev67, so leave this test here - else - O << "\t.arch ev6\n"; - O << "\t.set noat\n"; + OutStreamer.EmitRawText(StringRef("\t.arch ev6")); + OutStreamer.EmitRawText(StringRef("\t.set noat")); } /// PrintAsmOperand - Print out an operand for an inline asm expression. /// bool AlphaAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, - const char *ExtraCode) { - printOperand(MI, OpNo); + const char *ExtraCode, raw_ostream &O) { + printOperand(MI, OpNo, O); return false; } bool AlphaAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, - unsigned OpNo, - unsigned AsmVariant, - const char *ExtraCode) { + unsigned OpNo, unsigned AsmVariant, + const char *ExtraCode, + raw_ostream &O) { if (ExtraCode && ExtraCode[0]) return true; // Unknown modifier. O << "0("; - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); O << ")"; return false; } diff --git a/lib/Target/Blackfin/AsmPrinter/BlackfinAsmPrinter.cpp b/lib/Target/Blackfin/AsmPrinter/BlackfinAsmPrinter.cpp index 1c6d841cf3eb..6ba258beb2b8 100644 --- a/lib/Target/Blackfin/AsmPrinter/BlackfinAsmPrinter.cpp +++ b/lib/Target/Blackfin/AsmPrinter/BlackfinAsmPrinter.cpp @@ -19,7 +19,6 @@ #include "llvm/DerivedTypes.h" #include "llvm/Module.h" #include "llvm/CodeGen/AsmPrinter.h" -#include "llvm/CodeGen/DwarfWriter.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineInstr.h" @@ -33,33 +32,36 @@ #include "llvm/Target/TargetRegistry.h" #include "llvm/ADT/SmallString.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/FormattedStream.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; namespace { class BlackfinAsmPrinter : public AsmPrinter { public: - BlackfinAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM, - MCStreamer &Streamer) - : AsmPrinter(O, TM, Streamer) {} + BlackfinAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) + : AsmPrinter(TM, Streamer) {} virtual const char *getPassName() const { return "Blackfin Assembly Printer"; } - void printOperand(const MachineInstr *MI, int opNum); - void printMemoryOperand(const MachineInstr *MI, int opNum); - void printInstruction(const MachineInstr *MI); // autogenerated. + void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); + void printMemoryOperand(const MachineInstr *MI, int opNum, raw_ostream &O); + void printInstruction(const MachineInstr *MI, raw_ostream &O);// autogen'd. static const char *getRegisterName(unsigned RegNo); void EmitInstruction(const MachineInstr *MI) { - printInstruction(MI); - OutStreamer.AddBlankLine(); + SmallString<128> Str; + raw_svector_ostream OS(Str); + printInstruction(MI, OS); + OutStreamer.EmitRawText(OS.str()); } bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode); + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O); bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode); + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O); }; } // end of anonymous namespace @@ -69,8 +71,9 @@ extern "C" void LLVMInitializeBlackfinAsmPrinter() { RegisterAsmPrinter<BlackfinAsmPrinter> X(TheBlackfinTarget); } -void BlackfinAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { - const MachineOperand &MO = MI->getOperand (opNum); +void BlackfinAsmPrinter::printOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { + const MachineOperand &MO = MI->getOperand(opNum); switch (MO.getType()) { case MachineOperand::MO_Register: assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && @@ -86,7 +89,7 @@ void BlackfinAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { return; case MachineOperand::MO_GlobalAddress: O << *Mang->getSymbol(MO.getGlobal()); - printOffset(MO.getOffset()); + printOffset(MO.getOffset(), O); break; case MachineOperand::MO_ExternalSymbol: O << *GetExternalSymbolSymbol(MO.getSymbolName()); @@ -105,22 +108,23 @@ void BlackfinAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { } } -void BlackfinAsmPrinter::printMemoryOperand(const MachineInstr *MI, int opNum) { - printOperand(MI, opNum); +void BlackfinAsmPrinter::printMemoryOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { + printOperand(MI, opNum, O); if (MI->getOperand(opNum+1).isImm() && MI->getOperand(opNum+1).getImm() == 0) return; O << " + "; - printOperand(MI, opNum+1); + printOperand(MI, opNum+1, O); } /// PrintAsmOperand - Print out an operand for an inline asm expression. /// bool BlackfinAsmPrinter::PrintAsmOperand(const MachineInstr *MI, - unsigned OpNo, - unsigned AsmVariant, - const char *ExtraCode) { + unsigned OpNo, unsigned AsmVariant, + const char *ExtraCode, + raw_ostream &O) { if (ExtraCode && ExtraCode[0]) { if (ExtraCode[1] != 0) return true; // Unknown modifier. @@ -131,7 +135,7 @@ bool BlackfinAsmPrinter::PrintAsmOperand(const MachineInstr *MI, } } - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); return false; } @@ -139,12 +143,13 @@ bool BlackfinAsmPrinter::PrintAsmOperand(const MachineInstr *MI, bool BlackfinAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, - const char *ExtraCode) { + const char *ExtraCode, + raw_ostream &O) { if (ExtraCode && ExtraCode[0]) return true; // Unknown modifier O << '['; - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); O << ']'; return false; diff --git a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp index 857ddcf92a5f..0ef36e550d03 100644 --- a/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp +++ b/lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp @@ -30,17 +30,17 @@ #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetRegistry.h" +#include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/FormattedStream.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; namespace { class SPUAsmPrinter : public AsmPrinter { public: - explicit SPUAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM, - MCStreamer &Streamer) : - AsmPrinter(O, TM, Streamer) {} + explicit SPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) : + AsmPrinter(TM, Streamer) {} virtual const char *getPassName() const { return "STI CBEA SPU Assembly Printer"; @@ -52,44 +52,48 @@ namespace { /// printInstruction - This method is automatically generated by tablegen /// from the instruction set description. - void printInstruction(const MachineInstr *MI); + void printInstruction(const MachineInstr *MI, raw_ostream &OS); static const char *getRegisterName(unsigned RegNo); void EmitInstruction(const MachineInstr *MI) { - printInstruction(MI); - OutStreamer.AddBlankLine(); + SmallString<128> Str; + raw_svector_ostream OS(Str); + printInstruction(MI, OS); + OutStreamer.EmitRawText(OS.str()); } - void printOp(const MachineOperand &MO); + void printOp(const MachineOperand &MO, raw_ostream &OS); /// printRegister - Print register according to target requirements. /// - void printRegister(const MachineOperand &MO, bool R0AsZero) { + void printRegister(const MachineOperand &MO, bool R0AsZero, raw_ostream &O){ unsigned RegNo = MO.getReg(); assert(TargetRegisterInfo::isPhysicalRegister(RegNo) && "Not physreg??"); O << getRegisterName(RegNo); } - void printOperand(const MachineInstr *MI, unsigned OpNo) { + void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNo); if (MO.isReg()) { O << getRegisterName(MO.getReg()); } else if (MO.isImm()) { O << MO.getImm(); } else { - printOp(MO); + printOp(MO, O); } } bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode); + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O); bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode); + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O); void - printS7ImmOperand(const MachineInstr *MI, unsigned OpNo) + printS7ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { int value = MI->getOperand(OpNo).getImm(); value = (value << (32 - 7)) >> (32 - 7); @@ -100,7 +104,7 @@ namespace { } void - printU7ImmOperand(const MachineInstr *MI, unsigned OpNo) + printU7ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { unsigned int value = MI->getOperand(OpNo).getImm(); assert(value < (1 << 8) && "Invalid u7 argument"); @@ -108,45 +112,45 @@ namespace { } void - printShufAddr(const MachineInstr *MI, unsigned OpNo) + printShufAddr(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { char value = MI->getOperand(OpNo).getImm(); O << (int) value; O << "("; - printOperand(MI, OpNo+1); + printOperand(MI, OpNo+1, O); O << ")"; } void - printS16ImmOperand(const MachineInstr *MI, unsigned OpNo) + printS16ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { O << (short) MI->getOperand(OpNo).getImm(); } void - printU16ImmOperand(const MachineInstr *MI, unsigned OpNo) + printU16ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { O << (unsigned short)MI->getOperand(OpNo).getImm(); } void - printU32ImmOperand(const MachineInstr *MI, unsigned OpNo) + printU32ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { O << (unsigned)MI->getOperand(OpNo).getImm(); } void - printMemRegReg(const MachineInstr *MI, unsigned OpNo) { + printMemRegReg(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { // When used as the base register, r0 reads constant zero rather than // the value contained in the register. For this reason, the darwin // assembler requires that we print r0 as 0 (no r) when used as the base. const MachineOperand &MO = MI->getOperand(OpNo); O << getRegisterName(MO.getReg()) << ", "; - printOperand(MI, OpNo+1); + printOperand(MI, OpNo+1, O); } void - printU18ImmOperand(const MachineInstr *MI, unsigned OpNo) + printU18ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { unsigned int value = MI->getOperand(OpNo).getImm(); assert(value <= (1 << 19) - 1 && "Invalid u18 argument"); @@ -154,7 +158,7 @@ namespace { } void - printS10ImmOperand(const MachineInstr *MI, unsigned OpNo) + printS10ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16) >> 16); @@ -164,7 +168,7 @@ namespace { } void - printU10ImmOperand(const MachineInstr *MI, unsigned OpNo) + printU10ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16) >> 16); @@ -173,7 +177,7 @@ namespace { } void - printDFormAddr(const MachineInstr *MI, unsigned OpNo) + printDFormAddr(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { assert(MI->getOperand(OpNo).isImm() && "printDFormAddr first operand is not immediate"); @@ -182,18 +186,18 @@ namespace { assert((value16 >= -(1 << (9+4)) && value16 <= (1 << (9+4)) - 1) && "Invalid dform s10 offset argument"); O << (value16 & ~0xf) << "("; - printOperand(MI, OpNo+1); + printOperand(MI, OpNo+1, O); O << ")"; } void - printAddr256K(const MachineInstr *MI, unsigned OpNo) + printAddr256K(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { /* Note: operand 1 is an offset or symbol name. */ if (MI->getOperand(OpNo).isImm()) { - printS16ImmOperand(MI, OpNo); + printS16ImmOperand(MI, OpNo, O); } else { - printOp(MI->getOperand(OpNo)); + printOp(MI->getOperand(OpNo), O); if (MI->getOperand(OpNo+1).isImm()) { int displ = int(MI->getOperand(OpNo+1).getImm()); if (displ > 0) @@ -204,50 +208,51 @@ namespace { } } - void printCallOperand(const MachineInstr *MI, unsigned OpNo) { - printOp(MI->getOperand(OpNo)); + void printCallOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { + printOp(MI->getOperand(OpNo), O); } - void printPCRelativeOperand(const MachineInstr *MI, unsigned OpNo) { + void printPCRelativeOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { // Used to generate a ".-<target>", but it turns out that the assembler // really wants the target. // // N.B.: This operand is used for call targets. Branch hints are another // animal entirely. - printOp(MI->getOperand(OpNo)); + printOp(MI->getOperand(OpNo), O); } - void printHBROperand(const MachineInstr *MI, unsigned OpNo) { + void printHBROperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { // HBR operands are generated in front of branches, hence, the // program counter plus the target. O << ".+"; - printOp(MI->getOperand(OpNo)); + printOp(MI->getOperand(OpNo), O); } - void printSymbolHi(const MachineInstr *MI, unsigned OpNo) { + void printSymbolHi(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { if (MI->getOperand(OpNo).isImm()) { - printS16ImmOperand(MI, OpNo); + printS16ImmOperand(MI, OpNo, O); } else { - printOp(MI->getOperand(OpNo)); + printOp(MI->getOperand(OpNo), O); O << "@h"; } } - void printSymbolLo(const MachineInstr *MI, unsigned OpNo) { + void printSymbolLo(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { if (MI->getOperand(OpNo).isImm()) { - printS16ImmOperand(MI, OpNo); + printS16ImmOperand(MI, OpNo, O); } else { - printOp(MI->getOperand(OpNo)); + printOp(MI->getOperand(OpNo), O); O << "@l"; } } /// Print local store address - void printSymbolLSA(const MachineInstr *MI, unsigned OpNo) { - printOp(MI->getOperand(OpNo)); + void printSymbolLSA(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { + printOp(MI->getOperand(OpNo), O); } - void printROTHNeg7Imm(const MachineInstr *MI, unsigned OpNo) { + void printROTHNeg7Imm(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { if (MI->getOperand(OpNo).isImm()) { int value = (int) MI->getOperand(OpNo).getImm(); assert((value >= 0 && value < 16) @@ -258,15 +263,13 @@ namespace { } } - void printROTNeg7Imm(const MachineInstr *MI, unsigned OpNo) { - if (MI->getOperand(OpNo).isImm()) { - int value = (int) MI->getOperand(OpNo).getImm(); - assert((value >= 0 && value <= 32) - && "Invalid negated immediate rotate 7-bit argument"); - O << -value; - } else { - llvm_unreachable("Invalid/non-immediate rotate amount in printRotateNeg7Imm"); - } + void printROTNeg7Imm(const MachineInstr *MI, unsigned OpNo, raw_ostream &O){ + assert(MI->getOperand(OpNo).isImm() && + "Invalid/non-immediate rotate amount in printRotateNeg7Imm"); + int value = (int) MI->getOperand(OpNo).getImm(); + assert((value >= 0 && value <= 32) + && "Invalid negated immediate rotate 7-bit argument"); + O << -value; } }; } // end of anonymous namespace @@ -274,7 +277,7 @@ namespace { // Include the auto-generated portion of the assembly writer #include "SPUGenAsmWriter.inc" -void SPUAsmPrinter::printOp(const MachineOperand &MO) { +void SPUAsmPrinter::printOp(const MachineOperand &MO, raw_ostream &O) { switch (MO.getType()) { case MachineOperand::MO_Immediate: llvm_report_error("printOp() does not handle immediate values"); @@ -323,7 +326,7 @@ void SPUAsmPrinter::printOp(const MachineOperand &MO) { /// bool SPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, - const char *ExtraCode) { + const char *ExtraCode, raw_ostream &O) { // Does this asm operand have a single letter operand modifier? if (ExtraCode && ExtraCode[0]) { if (ExtraCode[1] != 0) return true; // Unknown modifier. @@ -341,17 +344,17 @@ bool SPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, } } - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); return false; } bool SPUAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, - unsigned OpNo, - unsigned AsmVariant, - const char *ExtraCode) { + unsigned OpNo, unsigned AsmVariant, + const char *ExtraCode, + raw_ostream &O) { if (ExtraCode && ExtraCode[0]) return true; // Unknown modifier. - printMemRegReg(MI, OpNo); + printMemRegReg(MI, OpNo, O); return false; } diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp index ad034ebcd839..ffac58182aec 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.cpp +++ b/lib/Target/CellSPU/SPURegisterInfo.cpp @@ -451,11 +451,11 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); - MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); + MachineModuleInfo &MMI = MF.getMMI(); DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); // Prepare for debug frame info. - bool hasDebugInfo = MMI && MMI->hasDebugInfo(); + bool hasDebugInfo = MMI.hasDebugInfo(); MCSymbol *FrameLabel = 0; // Move MBBI back to the beginning of the function. @@ -473,7 +473,7 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const FrameSize = -(FrameSize + SPUFrameInfo::minStackSize()); if (hasDebugInfo) { // Mark effective beginning of when frame pointer becomes valid. - FrameLabel = MMI->getContext().CreateTempSymbol(); + FrameLabel = MMI.getContext().CreateTempSymbol(); BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addSym(FrameLabel); } @@ -516,7 +516,7 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const } if (hasDebugInfo) { - std::vector<MachineMove> &Moves = MMI->getFrameMoves(); + std::vector<MachineMove> &Moves = MMI.getFrameMoves(); // Show update of SP. MachineLocation SPDst(MachineLocation::VirtualFP); @@ -535,7 +535,7 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const } // Mark effective beginning of when frame pointer is ready. - MCSymbol *ReadyLabel = MMI->getContext().CreateTempSymbol(); + MCSymbol *ReadyLabel = MMI.getContext().CreateTempSymbol(); BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)).addSym(ReadyLabel); MachineLocation FPDst(SPU::R1); @@ -552,7 +552,7 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const // Insert terminator label BuildMI(MBB, MBBI, dl, TII.get(SPU::DBG_LABEL)) - .addSym(MMI->getContext().CreateTempSymbol()); + .addSym(MMI.getContext().CreateTempSymbol()); } } } diff --git a/lib/Target/MBlaze/AsmPrinter/MBlazeAsmPrinter.cpp b/lib/Target/MBlaze/AsmPrinter/MBlazeAsmPrinter.cpp index ee2c7c8e05fb..b1df926864e6 100644 --- a/lib/Target/MBlaze/AsmPrinter/MBlazeAsmPrinter.cpp +++ b/lib/Target/MBlaze/AsmPrinter/MBlazeAsmPrinter.cpp @@ -23,7 +23,6 @@ #include "llvm/DerivedTypes.h" #include "llvm/Module.h" #include "llvm/CodeGen/AsmPrinter.h" -#include "llvm/CodeGen/DwarfWriter.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -37,13 +36,10 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetRegistry.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/ADT/Statistic.h" +#include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/CommandLine.h" -#include "llvm/Support/FormattedStream.h" -#include "llvm/Support/MathExtras.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" #include <cctype> using namespace llvm; @@ -52,9 +48,8 @@ namespace { class MBlazeAsmPrinter : public AsmPrinter { const MBlazeSubtarget *Subtarget; public: - explicit MBlazeAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM, - MCStreamer &Streamer) - : AsmPrinter(O, TM, Streamer) { + explicit MBlazeAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) + : AsmPrinter(TM, Streamer) { Subtarget = &TM.getSubtarget<MBlazeSubtarget>(); } @@ -63,31 +58,32 @@ namespace { } bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode); - void printOperand(const MachineInstr *MI, int opNum); - void printUnsignedImm(const MachineInstr *MI, int opNum); - void printFSLImm(const MachineInstr *MI, int opNum); - void printMemOperand(const MachineInstr *MI, int opNum, + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O); + void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); + void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O); + void printFSLImm(const MachineInstr *MI, int opNum, raw_ostream &O); + void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier = 0); - void printFCCOperand(const MachineInstr *MI, int opNum, + void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier = 0); - void printSavedRegsBitmask(); - void printHex32(unsigned int Value); + void printSavedRegsBitmask(raw_ostream &OS); const char *emitCurrentABIString(); void emitFrameDirective(); - void printInstruction(const MachineInstr *MI); // autogenerated. + void printInstruction(const MachineInstr *MI, raw_ostream &O); void EmitInstruction(const MachineInstr *MI) { - printInstruction(MI); - O << '\n'; + SmallString<128> Str; + raw_svector_ostream OS(Str); + printInstruction(MI, OS); + OutStreamer.EmitRawText(OS.str()); } virtual void EmitFunctionBodyStart(); virtual void EmitFunctionBodyEnd(); static const char *getRegisterName(unsigned RegNo); virtual void EmitFunctionEntryLabel(); - void EmitStartOfAsmFile(Module &M); }; } // end of anonymous namespace @@ -128,9 +124,17 @@ namespace { // Mask directives //===----------------------------------------------------------------------===// +// Print a 32 bit hex number with all numbers. +static void printHex32(unsigned int Value, raw_ostream &O) { + O << "0x"; + for (int i = 7; i >= 0; i--) + O << utohexstr((Value & (0xF << (i*4))) >> (i*4)); +} + + // Create a bitmask with all callee saved registers for CPU or Floating Point // registers. For CPU registers consider RA, GP and FP for saving if necessary. -void MBlazeAsmPrinter::printSavedRegsBitmask() { +void MBlazeAsmPrinter::printSavedRegsBitmask(raw_ostream &O) { const TargetRegisterInfo &RI = *TM.getRegisterInfo(); const MBlazeFunctionInfo *MBlazeFI = MF->getInfo<MBlazeFunctionInfo>(); @@ -156,15 +160,8 @@ void MBlazeAsmPrinter::printSavedRegsBitmask() { getRegisterNumbering(RI.getRARegister())); // Print CPUBitmask - O << "\t.mask \t"; printHex32(CPUBitmask); O << ',' - << MBlazeFI->getCPUTopSavedRegOff() << '\n'; -} - -// Print a 32 bit hex number with all numbers. -void MBlazeAsmPrinter::printHex32(unsigned int Value) { - O << "0x"; - for (int i = 7; i >= 0; i--) - O << utohexstr( (Value & (0xF << (i*4))) >> (i*4) ); + O << "\t.mask \t"; printHex32(CPUBitmask, O); + O << ',' << MBlazeFI->getCPUTopSavedRegOff() << '\n'; } //===----------------------------------------------------------------------===// @@ -180,122 +177,127 @@ void MBlazeAsmPrinter::emitFrameDirective() { unsigned stackSize = MF->getFrameInfo()->getStackSize(); - O << "\t.frame\t" << getRegisterName(stackReg) - << ',' << stackSize << ',' - << getRegisterName(returnReg) - << '\n'; + OutStreamer.EmitRawText("\t.frame\t" + Twine(getRegisterName(stackReg)) + + "," + Twine(stackSize) + "," + + Twine(getRegisterName(returnReg))); } void MBlazeAsmPrinter::EmitFunctionEntryLabel() { - O << "\t.ent\t" << *CurrentFnSym << '\n'; - OutStreamer.EmitLabel(CurrentFnSym); + OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName())); + OutStreamer.EmitLabel(CurrentFnSym); } /// EmitFunctionBodyStart - Targets can override this to emit stuff before /// the first basic block in the function. void MBlazeAsmPrinter::EmitFunctionBodyStart() { emitFrameDirective(); - printSavedRegsBitmask(); + + SmallString<128> Str; + raw_svector_ostream OS(Str); + printSavedRegsBitmask(OS); + OutStreamer.EmitRawText(OS.str()); } /// EmitFunctionBodyEnd - Targets can override this to emit stuff after /// the last basic block in the function. void MBlazeAsmPrinter::EmitFunctionBodyEnd() { - O << "\t.end\t" << *CurrentFnSym << '\n'; + OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName())); } // Print out an operand for an inline asm expression. bool MBlazeAsmPrinter:: PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant,const char *ExtraCode){ + unsigned AsmVariant,const char *ExtraCode, raw_ostream &O) { // Does this asm operand have a single letter operand modifier? if (ExtraCode && ExtraCode[0]) return true; // Unknown modifier. - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); return false; } -void MBlazeAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { +void MBlazeAsmPrinter::printOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(opNum); switch (MO.getType()) { - case MachineOperand::MO_Register: - O << getRegisterName(MO.getReg()); - break; - - case MachineOperand::MO_Immediate: - O << (int)MO.getImm(); - break; - - case MachineOperand::MO_FPImmediate: { - const ConstantFP* fp = MO.getFPImm(); - printHex32(fp->getValueAPF().bitcastToAPInt().getZExtValue()); - O << ";\t# immediate = " << *fp; - break; - } - - case MachineOperand::MO_MachineBasicBlock: - O << *MO.getMBB()->getSymbol(); - return; - - case MachineOperand::MO_GlobalAddress: - O << *Mang->getSymbol(MO.getGlobal()); - break; - - case MachineOperand::MO_ExternalSymbol: - O << *GetExternalSymbolSymbol(MO.getSymbolName()); - break; - - case MachineOperand::MO_JumpTableIndex: - O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() - << '_' << MO.getIndex(); - break; - - case MachineOperand::MO_ConstantPoolIndex: - O << MAI->getPrivateGlobalPrefix() << "CPI" - << getFunctionNumber() << "_" << MO.getIndex(); - if (MO.getOffset()) - O << "+" << MO.getOffset(); - break; - - default: - llvm_unreachable("<unknown operand type>"); + case MachineOperand::MO_Register: + O << getRegisterName(MO.getReg()); + break; + + case MachineOperand::MO_Immediate: + O << (int)MO.getImm(); + break; + + case MachineOperand::MO_FPImmediate: { + const ConstantFP *fp = MO.getFPImm(); + printHex32(fp->getValueAPF().bitcastToAPInt().getZExtValue(), O); + O << ";\t# immediate = " << *fp; + break; + } + + case MachineOperand::MO_MachineBasicBlock: + O << *MO.getMBB()->getSymbol(); + return; + + case MachineOperand::MO_GlobalAddress: + O << *Mang->getSymbol(MO.getGlobal()); + break; + + case MachineOperand::MO_ExternalSymbol: + O << *GetExternalSymbolSymbol(MO.getSymbolName()); + break; + + case MachineOperand::MO_JumpTableIndex: + O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber() + << '_' << MO.getIndex(); + break; + + case MachineOperand::MO_ConstantPoolIndex: + O << MAI->getPrivateGlobalPrefix() << "CPI" + << getFunctionNumber() << "_" << MO.getIndex(); + if (MO.getOffset()) + O << "+" << MO.getOffset(); + break; + + default: + llvm_unreachable("<unknown operand type>"); } } -void MBlazeAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum) { +void MBlazeAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(opNum); if (MO.getType() == MachineOperand::MO_Immediate) O << (unsigned int)MO.getImm(); else - printOperand(MI, opNum); + printOperand(MI, opNum, O); } -void MBlazeAsmPrinter::printFSLImm(const MachineInstr *MI, int opNum) { +void MBlazeAsmPrinter::printFSLImm(const MachineInstr *MI, int opNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(opNum); if (MO.getType() == MachineOperand::MO_Immediate) O << "rfsl" << (unsigned int)MO.getImm(); else - printOperand(MI, opNum); + printOperand(MI, opNum, O); } void MBlazeAsmPrinter:: -printMemOperand(const MachineInstr *MI, int opNum, const char *Modifier) { - printOperand(MI, opNum+1); +printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O, + const char *Modifier) { + printOperand(MI, opNum+1, O); O << ", "; - printOperand(MI, opNum); + printOperand(MI, opNum, O); } void MBlazeAsmPrinter:: -printFCCOperand(const MachineInstr *MI, int opNum, const char *Modifier) { +printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, + const char *Modifier) { const MachineOperand& MO = MI->getOperand(opNum); O << MBlaze::MBlazeFCCToString((MBlaze::CondCode)MO.getImm()); } -void MBlazeAsmPrinter::EmitStartOfAsmFile(Module &M) { -} - // Force static initialization. extern "C" void LLVMInitializeMBlazeAsmPrinter() { RegisterAsmPrinter<MBlazeAsmPrinter> X(TheMBlazeTarget); diff --git a/lib/Target/MBlaze/MBlaze.td b/lib/Target/MBlaze/MBlaze.td index 16797529cb28..482ddd3963fb 100644 --- a/lib/Target/MBlaze/MBlaze.td +++ b/lib/Target/MBlaze/MBlaze.td @@ -25,11 +25,7 @@ include "MBlazeIntrinsics.td" include "MBlazeInstrInfo.td" include "MBlazeCallingConv.td" -def MBlazeInstrInfo : InstrInfo { - let TSFlagsFields = []; - let TSFlagsShifts = []; -} - +def MBlazeInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// // Microblaze Subtarget features // diff --git a/lib/Target/MSP430/AsmPrinter/MSP430AsmPrinter.cpp b/lib/Target/MSP430/AsmPrinter/MSP430AsmPrinter.cpp index 04ac6f1949f1..56f72bbc1474 100644 --- a/lib/Target/MSP430/AsmPrinter/MSP430AsmPrinter.cpp +++ b/lib/Target/MSP430/AsmPrinter/MSP430AsmPrinter.cpp @@ -24,7 +24,6 @@ #include "llvm/Module.h" #include "llvm/Assembly/Writer.h" #include "llvm/CodeGen/AsmPrinter.h" -#include "llvm/CodeGen/DwarfWriter.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineConstantPool.h" @@ -36,50 +35,36 @@ #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetRegistry.h" -#include "llvm/Support/FormattedStream.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; namespace { class MSP430AsmPrinter : public AsmPrinter { public: - MSP430AsmPrinter(formatted_raw_ostream &O, TargetMachine &TM, - MCStreamer &Streamer) - : AsmPrinter(O, TM, Streamer) {} + MSP430AsmPrinter(TargetMachine &TM, MCStreamer &Streamer) + : AsmPrinter(TM, Streamer) {} virtual const char *getPassName() const { return "MSP430 Assembly Printer"; } - void printMCInst(const MCInst *MI) { - MSP430InstPrinter(O, *MAI).printInstruction(MI); - } void printOperand(const MachineInstr *MI, int OpNum, - const char* Modifier = 0); - void printPCRelImmOperand(const MachineInstr *MI, int OpNum) { - printOperand(MI, OpNum); - } + raw_ostream &O, const char* Modifier = 0); void printSrcMemOperand(const MachineInstr *MI, int OpNum, - const char* Modifier = 0); - void printCCOperand(const MachineInstr *MI, int OpNum); - void printMachineInstruction(const MachineInstr * MI); + raw_ostream &O); bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, - const char *ExtraCode); + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O); bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, - const char *ExtraCode); + const char *ExtraCode, raw_ostream &O); void EmitInstruction(const MachineInstr *MI); - - void getAnalysisUsage(AnalysisUsage &AU) const { - AsmPrinter::getAnalysisUsage(AU); - AU.setPreservesAll(); - } }; } // end of anonymous namespace void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum, - const char* Modifier) { + raw_ostream &O, const char *Modifier) { const MachineOperand &MO = MI->getOperand(OpNum); switch (MO.getType()) { default: assert(0 && "Not implemented yet!"); @@ -126,7 +111,7 @@ void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum, } void MSP430AsmPrinter::printSrcMemOperand(const MachineInstr *MI, int OpNum, - const char* Modifier) { + raw_ostream &O) { const MachineOperand &Base = MI->getOperand(OpNum); const MachineOperand &Disp = MI->getOperand(OpNum+1); @@ -135,48 +120,37 @@ void MSP430AsmPrinter::printSrcMemOperand(const MachineInstr *MI, int OpNum, // Imm here is in fact global address - print extra modifier. if (Disp.isImm() && !Base.getReg()) O << '&'; - printOperand(MI, OpNum+1, "nohash"); + printOperand(MI, OpNum+1, O, "nohash"); // Print register base field if (Base.getReg()) { O << '('; - printOperand(MI, OpNum); + printOperand(MI, OpNum, O); O << ')'; } } -void MSP430AsmPrinter::printCCOperand(const MachineInstr *MI, int OpNum) { - switch (MI->getOperand(OpNum).getImm()) { - default: assert(0 && "Unknown cond"); - case MSP430CC::COND_E: O << "eq"; break; - case MSP430CC::COND_NE: O << "ne"; break; - case MSP430CC::COND_HS: O << "hs"; break; - case MSP430CC::COND_LO: O << "lo"; break; - case MSP430CC::COND_GE: O << "ge"; break; - case MSP430CC::COND_L: O << 'l'; break; - } -} - /// PrintAsmOperand - Print out an operand for an inline asm expression. /// bool MSP430AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, - const char *ExtraCode) { + const char *ExtraCode, raw_ostream &O) { // Does this asm operand have a single letter operand modifier? if (ExtraCode && ExtraCode[0]) return true; // Unknown modifier. - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); return false; } bool MSP430AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, - const char *ExtraCode) { + const char *ExtraCode, + raw_ostream &O) { if (ExtraCode && ExtraCode[0]) { return true; // Unknown modifier. } - printSrcMemOperand(MI, OpNo); + printSrcMemOperand(MI, OpNo, O); return false; } @@ -191,10 +165,9 @@ void MSP430AsmPrinter::EmitInstruction(const MachineInstr *MI) { static MCInstPrinter *createMSP430MCInstPrinter(const Target &T, unsigned SyntaxVariant, - const MCAsmInfo &MAI, - raw_ostream &O) { + const MCAsmInfo &MAI) { if (SyntaxVariant == 0) - return new MSP430InstPrinter(O, MAI); + return new MSP430InstPrinter(MAI); return 0; } diff --git a/lib/Target/MSP430/AsmPrinter/MSP430InstPrinter.cpp b/lib/Target/MSP430/AsmPrinter/MSP430InstPrinter.cpp index d7636e68a0d6..c15d4085bc8b 100644 --- a/lib/Target/MSP430/AsmPrinter/MSP430InstPrinter.cpp +++ b/lib/Target/MSP430/AsmPrinter/MSP430InstPrinter.cpp @@ -28,11 +28,12 @@ using namespace llvm; #include "MSP430GenAsmWriter.inc" #undef MachineInstr -void MSP430InstPrinter::printInst(const MCInst *MI) { - printInstruction(MI); +void MSP430InstPrinter::printInst(const MCInst *MI, raw_ostream &O) { + printInstruction(MI, O); } -void MSP430InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo) { +void MSP430InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); if (Op.isImm()) O << Op.getImm(); @@ -43,7 +44,7 @@ void MSP430InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo) { } void MSP430InstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - const char *Modifier) { + raw_ostream &O, const char *Modifier) { assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported"); const MCOperand &Op = MI->getOperand(OpNo); if (Op.isReg()) { @@ -57,6 +58,7 @@ void MSP430InstPrinter::printOperand(const MCInst *MI, unsigned OpNo, } void MSP430InstPrinter::printSrcMemOperand(const MCInst *MI, unsigned OpNo, + raw_ostream &O, const char *Modifier) { const MCOperand &Base = MI->getOperand(OpNo); const MCOperand &Disp = MI->getOperand(OpNo+1); @@ -84,7 +86,8 @@ void MSP430InstPrinter::printSrcMemOperand(const MCInst *MI, unsigned OpNo, O << '(' << getRegisterName(Base.getReg()) << ')'; } -void MSP430InstPrinter::printCCOperand(const MCInst *MI, unsigned OpNo) { +void MSP430InstPrinter::printCCOperand(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { unsigned CC = MI->getOperand(OpNo).getImm(); switch (CC) { diff --git a/lib/Target/MSP430/AsmPrinter/MSP430InstPrinter.h b/lib/Target/MSP430/AsmPrinter/MSP430InstPrinter.h index 2fac800fcd79..f0e1ce22841b 100644 --- a/lib/Target/MSP430/AsmPrinter/MSP430InstPrinter.h +++ b/lib/Target/MSP430/AsmPrinter/MSP430InstPrinter.h @@ -16,29 +16,26 @@ #include "llvm/MC/MCInstPrinter.h" -namespace llvm -{ - +namespace llvm { class MCOperand; class MSP430InstPrinter : public MCInstPrinter { public: - MSP430InstPrinter(raw_ostream &O, const MCAsmInfo &MAI) : - MCInstPrinter(O, MAI){ + MSP430InstPrinter(const MCAsmInfo &MAI) : MCInstPrinter(MAI) { } - virtual void printInst(const MCInst *MI); + virtual void printInst(const MCInst *MI, raw_ostream &O); // Autogenerated by tblgen. - void printInstruction(const MCInst *MI); + void printInstruction(const MCInst *MI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); - void printOperand(const MCInst *MI, unsigned OpNo, + void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, const char *Modifier = 0); - void printPCRelImmOperand(const MCInst *MI, unsigned OpNo); - void printSrcMemOperand(const MCInst *MI, unsigned OpNo, + void printPCRelImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printSrcMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, const char *Modifier = 0); - void printCCOperand(const MCInst *MI, unsigned OpNo); + void printCCOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); }; } diff --git a/lib/Target/MSP430/MSP430.td b/lib/Target/MSP430/MSP430.td index fe533d3d2e5c..0f08e3d8ca0f 100644 --- a/lib/Target/MSP430/MSP430.td +++ b/lib/Target/MSP430/MSP430.td @@ -48,14 +48,7 @@ include "MSP430CallingConv.td" include "MSP430InstrInfo.td" -def MSP430InstrInfo : InstrInfo { - // Define how we want to layout our TargetSpecific information field... This - // should be kept up-to-date with the fields in the MSP430InstrInfo.h file. - let TSFlagsFields = ["FormBits", - "Size"]; - let TSFlagsShifts = [0, - 2]; -} +def MSP430InstrInfo : InstrInfo; def MSP430InstPrinter : AsmWriter { string AsmWriterClassName = "InstPrinter"; diff --git a/lib/Target/MSP430/MSP430InstrFormats.td b/lib/Target/MSP430/MSP430InstrFormats.td index 4ccc7df57664..73aef1facc0f 100644 --- a/lib/Target/MSP430/MSP430InstrFormats.td +++ b/lib/Target/MSP430/MSP430InstrFormats.td @@ -61,10 +61,12 @@ class MSP430Inst<dag outs, dag ins, SizeVal sz, Format f, dag InOperandList = ins; Format Form = f; - bits<2> FormBits = Form.Value; - SizeVal Sz = sz; - bits<3> Size = Sz.Value; + + // Define how we want to layout our TargetSpecific information field... This + // should be kept up-to-date with the fields in the MSP430InstrInfo.h file. + let TSFlags{1-0} = Form.Value; + let TSFlags{4-2} = Sz.Value; let AsmString = asmstr; } diff --git a/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp b/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp index 2a2d9dcaf5a6..69743715607d 100644 --- a/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp +++ b/lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp @@ -13,17 +13,12 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "mips-asm-printer" - #include "Mips.h" #include "MipsSubtarget.h" #include "MipsInstrInfo.h" #include "MipsTargetMachine.h" #include "MipsMachineFunction.h" -#include "llvm/Constants.h" -#include "llvm/DerivedTypes.h" -#include "llvm/Module.h" #include "llvm/CodeGen/AsmPrinter.h" -#include "llvm/CodeGen/DwarfWriter.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -37,22 +32,18 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetRegistry.h" -#include "llvm/Support/ErrorHandling.h" +#include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/CommandLine.h" -#include "llvm/Support/FormattedStream.h" -#include "llvm/Support/MathExtras.h" -#include <cctype> +#include "llvm/ADT/Twine.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; namespace { class MipsAsmPrinter : public AsmPrinter { const MipsSubtarget *Subtarget; public: - explicit MipsAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM, - MCStreamer &Streamer) - : AsmPrinter(O, TM, Streamer) { + explicit MipsAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) + : AsmPrinter(TM, Streamer) { Subtarget = &TM.getSubtarget<MipsSubtarget>(); } @@ -61,23 +52,26 @@ namespace { } bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode); - void printOperand(const MachineInstr *MI, int opNum); - void printUnsignedImm(const MachineInstr *MI, int opNum); - void printMemOperand(const MachineInstr *MI, int opNum, + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O); + void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); + void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O); + void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier = 0); - void printFCCOperand(const MachineInstr *MI, int opNum, + void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier = 0); - void printSavedRegsBitmask(); - void printHex32(unsigned int Value); + void printSavedRegsBitmask(raw_ostream &O); + void printHex32(unsigned int Value, raw_ostream &O); - const char *emitCurrentABIString(); + const char *getCurrentABIString() const; void emitFrameDirective(); - void printInstruction(const MachineInstr *MI); // autogenerated. + void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen'd. void EmitInstruction(const MachineInstr *MI) { - printInstruction(MI); - OutStreamer.AddBlankLine(); + SmallString<128> Str; + raw_svector_ostream OS(Str); + printInstruction(MI, OS); + OutStreamer.EmitRawText(OS.str()); } virtual void EmitFunctionBodyStart(); virtual void EmitFunctionBodyEnd(); @@ -127,7 +121,7 @@ namespace { // Create a bitmask with all callee saved registers for CPU or Floating Point // registers. For CPU registers consider RA, GP and FP for saving if necessary. -void MipsAsmPrinter::printSavedRegsBitmask() { +void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) { const TargetRegisterInfo &RI = *TM.getRegisterInfo(); const MipsFunctionInfo *MipsFI = MF->getInfo<MipsFunctionInfo>(); @@ -156,21 +150,19 @@ void MipsAsmPrinter::printSavedRegsBitmask() { getRegisterNumbering(RI.getRARegister())); // Print CPUBitmask - O << "\t.mask \t"; printHex32(CPUBitmask); O << ',' - << MipsFI->getCPUTopSavedRegOff() << '\n'; + O << "\t.mask \t"; printHex32(CPUBitmask, O); + O << ',' << MipsFI->getCPUTopSavedRegOff() << '\n'; // Print FPUBitmask - O << "\t.fmask\t"; printHex32(FPUBitmask); O << "," + O << "\t.fmask\t"; printHex32(FPUBitmask, O); O << "," << MipsFI->getFPUTopSavedRegOff() << '\n'; } // Print a 32 bit hex number with all numbers. -void MipsAsmPrinter:: -printHex32(unsigned int Value) -{ +void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) { O << "0x"; for (int i = 7; i >= 0; i--) - O << utohexstr( (Value & (0xF << (i*4))) >> (i*4) ); + O << utohexstr((Value & (0xF << (i*4))) >> (i*4)); } //===----------------------------------------------------------------------===// @@ -185,22 +177,21 @@ void MipsAsmPrinter::emitFrameDirective() { unsigned returnReg = RI.getRARegister(); unsigned stackSize = MF->getFrameInfo()->getStackSize(); - - O << "\t.frame\t" << '$' << LowercaseString(getRegisterName(stackReg)) - << ',' << stackSize << ',' - << '$' << LowercaseString(getRegisterName(returnReg)) - << '\n'; + OutStreamer.EmitRawText("\t.frame\t$" + + Twine(LowercaseString(getRegisterName(stackReg))) + + "," + Twine(stackSize) + ",$" + + Twine(LowercaseString(getRegisterName(returnReg)))); } /// Emit Set directives. -const char *MipsAsmPrinter::emitCurrentABIString() { - switch(Subtarget->getTargetABI()) { - case MipsSubtarget::O32: return "abi32"; - case MipsSubtarget::O64: return "abiO64"; - case MipsSubtarget::N32: return "abiN32"; - case MipsSubtarget::N64: return "abi64"; - case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64 - default: break; +const char *MipsAsmPrinter::getCurrentABIString() const { + switch (Subtarget->getTargetABI()) { + case MipsSubtarget::O32: return "abi32"; + case MipsSubtarget::O64: return "abiO64"; + case MipsSubtarget::N32: return "abiN32"; + case MipsSubtarget::N64: return "abi64"; + case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64 + default: break; } llvm_unreachable("Unknown Mips ABI"); @@ -208,7 +199,7 @@ const char *MipsAsmPrinter::emitCurrentABIString() { } void MipsAsmPrinter::EmitFunctionEntryLabel() { - O << "\t.ent\t" << *CurrentFnSym << '\n'; + OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName())); OutStreamer.EmitLabel(CurrentFnSym); } @@ -216,7 +207,11 @@ void MipsAsmPrinter::EmitFunctionEntryLabel() { /// the first basic block in the function. void MipsAsmPrinter::EmitFunctionBodyStart() { emitFrameDirective(); - printSavedRegsBitmask(); + + SmallString<128> Str; + raw_svector_ostream OS(Str); + printSavedRegsBitmask(OS); + OutStreamer.EmitRawText(OS.str()); } /// EmitFunctionBodyEnd - Targets can override this to emit stuff after @@ -225,25 +220,26 @@ void MipsAsmPrinter::EmitFunctionBodyEnd() { // There are instruction for this macros, but they must // always be at the function end, and we can't emit and // break with BB logic. - O << "\t.set\tmacro\n"; - O << "\t.set\treorder\n"; - - O << "\t.end\t" << *CurrentFnSym << '\n'; + OutStreamer.EmitRawText(StringRef("\t.set\tmacro")); + OutStreamer.EmitRawText(StringRef("\t.set\treorder")); + OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName())); } // Print out an operand for an inline asm expression. bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant,const char *ExtraCode){ + unsigned AsmVariant,const char *ExtraCode, + raw_ostream &O) { // Does this asm operand have a single letter operand modifier? if (ExtraCode && ExtraCode[0]) return true; // Unknown modifier. - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); return false; } -void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { +void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(opNum); bool closeP = false; @@ -307,36 +303,39 @@ void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { if (closeP) O << ")"; } -void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum) { +void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(opNum); if (MO.getType() == MachineOperand::MO_Immediate) O << (unsigned short int)MO.getImm(); else - printOperand(MI, opNum); + printOperand(MI, opNum, O); } void MipsAsmPrinter:: -printMemOperand(const MachineInstr *MI, int opNum, const char *Modifier) { +printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O, + const char *Modifier) { // when using stack locations for not load/store instructions // print the same way as all normal 3 operand instructions. if (Modifier && !strcmp(Modifier, "stackloc")) { - printOperand(MI, opNum+1); + printOperand(MI, opNum+1, O); O << ", "; - printOperand(MI, opNum); + printOperand(MI, opNum, O); return; } // Load/Store memory operands -- imm($reg) // If PIC target the target is loaded as the // pattern lw $25,%call16($28) - printOperand(MI, opNum); + printOperand(MI, opNum, O); O << "("; - printOperand(MI, opNum+1); + printOperand(MI, opNum+1, O); O << ")"; } void MipsAsmPrinter:: -printFCCOperand(const MachineInstr *MI, int opNum, const char *Modifier) { +printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, + const char *Modifier) { const MachineOperand& MO = MI->getOperand(opNum); O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm()); } @@ -345,15 +344,18 @@ void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) { // FIXME: Use SwitchSection. // Tell the assembler which ABI we are using - O << "\t.section .mdebug." << emitCurrentABIString() << '\n'; + OutStreamer.EmitRawText("\t.section .mdebug." + Twine(getCurrentABIString())); // TODO: handle O64 ABI - if (Subtarget->isABI_EABI()) - O << "\t.section .gcc_compiled_long" << - (Subtarget->isGP32bit() ? "32" : "64") << '\n'; + if (Subtarget->isABI_EABI()) { + if (Subtarget->isGP32bit()) + OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long32")); + else + OutStreamer.EmitRawText(StringRef("\t.section .gcc_compiled_long64")); + } // return to previous section - O << "\t.previous" << '\n'; + OutStreamer.EmitRawText(StringRef("\t.previous")); } // Force static initialization. diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index 79a78d86aef7..aa036aef83d0 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -24,10 +24,7 @@ include "MipsSchedule.td" include "MipsInstrInfo.td" include "MipsCallingConv.td" -def MipsInstrInfo : InstrInfo { - let TSFlagsFields = []; - let TSFlagsShifts = []; -} +def MipsInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// // Mips Subtarget features // diff --git a/lib/Target/PIC16/AsmPrinter/PIC16AsmPrinter.cpp b/lib/Target/PIC16/AsmPrinter/PIC16AsmPrinter.cpp index 1001d29fd8a4..c46db46ea5b4 100644 --- a/lib/Target/PIC16/AsmPrinter/PIC16AsmPrinter.cpp +++ b/lib/Target/PIC16/AsmPrinter/PIC16AsmPrinter.cpp @@ -19,9 +19,7 @@ #include "llvm/DerivedTypes.h" #include "llvm/Function.h" #include "llvm/Module.h" -#include "llvm/CodeGen/DwarfWriter.h" #include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/DwarfWriter.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" @@ -29,23 +27,26 @@ #include "llvm/Target/TargetRegistry.h" #include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/FormattedStream.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/ADT/SmallString.h" #include <cstring> using namespace llvm; #include "PIC16GenAsmWriter.inc" -PIC16AsmPrinter::PIC16AsmPrinter(formatted_raw_ostream &O, TargetMachine &TM, - MCStreamer &Streamer) -: AsmPrinter(O, TM, Streamer), DbgInfo(O, TM.getMCAsmInfo()) { +PIC16AsmPrinter::PIC16AsmPrinter(TargetMachine &TM, MCStreamer &Streamer) +: AsmPrinter(TM, Streamer), DbgInfo(Streamer, TM.getMCAsmInfo()) { PTLI = static_cast<PIC16TargetLowering*>(TM.getTargetLowering()); PMAI = static_cast<const PIC16MCAsmInfo*>(TM.getMCAsmInfo()); PTOF = (PIC16TargetObjectFile *)&PTLI->getObjFileLowering(); } void PIC16AsmPrinter::EmitInstruction(const MachineInstr *MI) { - printInstruction(MI); - OutStreamer.AddBlankLine(); + SmallString<128> Str; + raw_svector_ostream OS(Str); + printInstruction(MI, OS); + + OutStreamer.EmitRawText(OS.str()); } static int getFunctionColor(const Function *F) { @@ -111,33 +112,33 @@ bool PIC16AsmPrinter::runOnMachineFunction(MachineFunction &MF) { PAN::isISR(F->getSection())); // Start the Code Section. - O << "\n"; OutStreamer.SwitchSection(fCodeSection); // Emit the frame address of the function at the beginning of code. - O << "\tretlw low(" << PAN::getFrameLabel(CurrentFnSym->getName()) << ")\n"; - O << "\tretlw high(" << PAN::getFrameLabel(CurrentFnSym->getName()) << ")\n"; + OutStreamer.EmitRawText("\tretlw low(" + + Twine(PAN::getFrameLabel(CurrentFnSym->getName())) + + ")"); + OutStreamer.EmitRawText("\tretlw high(" + + Twine(PAN::getFrameLabel(CurrentFnSym->getName())) + + ")"); // Emit function start label. - O << *CurrentFnSym << ":\n"; + OutStreamer.EmitLabel(CurrentFnSym); DebugLoc CurDL; - O << "\n"; // Print out code for the function. for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); I != E; ++I) { // Print a label for the basic block. - if (I != MF.begin()) { + if (I != MF.begin()) EmitBasicBlockStart(I); - } // Print a basic block. for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end(); II != E; ++II) { - // Emit the line directive if source line changed. - const DebugLoc DL = II->getDebugLoc(); + DebugLoc DL = II->getDebugLoc(); if (!DL.isUnknown() && DL != CurDL) { DbgInfo.ChangeDebugLoc(MF, DL); CurDL = DL; @@ -156,7 +157,8 @@ bool PIC16AsmPrinter::runOnMachineFunction(MachineFunction &MF) { // printOperand - print operand of insn. -void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int opNum) { +void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(opNum); const Function *F = MI->getParent()->getParent()->getFunction(); @@ -167,9 +169,7 @@ void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int opNum) { std::string RegName = getRegisterName(MO.getReg()); if ((MI->getOpcode() == PIC16::load_indirect) || (MI->getOpcode() == PIC16::store_indirect)) - { RegName.replace (0, 3, "INDF"); - } O << RegName; } return; @@ -216,7 +216,8 @@ void PIC16AsmPrinter::printOperand(const MachineInstr *MI, int opNum) { /// printCCOperand - Print the cond code operand. /// -void PIC16AsmPrinter::printCCOperand(const MachineInstr *MI, int opNum) { +void PIC16AsmPrinter::printCCOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { int CC = (int)MI->getOperand(opNum).getImm(); O << PIC16CondCodeToString((PIC16CC::CondCodes)CC); } @@ -228,13 +229,15 @@ void PIC16AsmPrinter::printLibcallDecls() { // If no libcalls used, return. if (LibcallDecls.empty()) return; - O << MAI->getCommentString() << "External decls for libcalls - BEGIN." <<"\n"; + OutStreamer.AddComment("External decls for libcalls - BEGIN"); + OutStreamer.AddBlankLine(); for (std::set<std::string>::const_iterator I = LibcallDecls.begin(), - E = LibcallDecls.end(); I != E; I++) { - O << MAI->getExternDirective() << *I << "\n"; - } - O << MAI->getCommentString() << "External decls for libcalls - END." <<"\n"; + E = LibcallDecls.end(); I != E; I++) + OutStreamer.EmitRawText(MAI->getExternDirective() + Twine(*I)); + + OutStreamer.AddComment("External decls for libcalls - END"); + OutStreamer.AddBlankLine(); } /// doInitialization - Perform Module level initializations here. @@ -245,8 +248,8 @@ bool PIC16AsmPrinter::doInitialization(Module &M) { bool Result = AsmPrinter::doInitialization(M); // Every asmbly contains these std headers. - O << "\n#include p16f1xxx.inc"; - O << "\n#include stdmacros.inc"; + OutStreamer.EmitRawText(StringRef("\n#include p16f1xxx.inc")); + OutStreamer.EmitRawText(StringRef("#include stdmacros.inc")); // Set the section names for all globals. for (Module::global_iterator I = M.global_begin(), E = M.global_end(); @@ -289,7 +292,8 @@ bool PIC16AsmPrinter::doInitialization(Module &M) { /// void PIC16AsmPrinter::EmitFunctionDecls(Module &M) { // Emit declarations for external functions. - O <<"\n"<<MAI->getCommentString() << "Function Declarations - BEGIN." <<"\n"; + OutStreamer.AddComment("Function Declarations - BEGIN"); + OutStreamer.AddBlankLine(); for (Module::iterator I = M.begin(), E = M.end(); I != E; I++) { if (I->isIntrinsic() || I->getName() == "@abort") continue; @@ -312,12 +316,16 @@ void PIC16AsmPrinter::EmitFunctionDecls(Module &M) { const char *directive = I->isDeclaration() ? MAI->getExternDirective() : MAI->getGlobalDirective(); - O << directive << Sym->getName() << "\n"; - O << directive << PAN::getRetvalLabel(Sym->getName()) << "\n"; - O << directive << PAN::getArgsLabel(Sym->getName()) << "\n"; + OutStreamer.EmitRawText(directive + Twine(Sym->getName())); + OutStreamer.EmitRawText(directive + + Twine(PAN::getRetvalLabel(Sym->getName()))); + OutStreamer.EmitRawText(directive + + Twine(PAN::getArgsLabel(Sym->getName()))); } - O << MAI->getCommentString() << "Function Declarations - END." <<"\n"; + OutStreamer.AddComment("Function Declarations - END"); + OutStreamer.AddBlankLine(); + } // Emit variables imported from other Modules. @@ -325,10 +333,14 @@ void PIC16AsmPrinter::EmitUndefinedVars(Module &M) { std::vector<const GlobalVariable*> Items = ExternalVarDecls; if (!Items.size()) return; - O << "\n" << MAI->getCommentString() << "Imported Variables - BEGIN" << "\n"; + OutStreamer.AddComment("Imported Variables - BEGIN"); + OutStreamer.AddBlankLine(); for (unsigned j = 0; j < Items.size(); j++) - O << MAI->getExternDirective() << *Mang->getSymbol(Items[j]) << "\n"; - O << MAI->getCommentString() << "Imported Variables - END" << "\n"; + OutStreamer.EmitRawText(MAI->getExternDirective() + + Twine(Mang->getSymbol(Items[j])->getName())); + + OutStreamer.AddComment("Imported Variables - END"); + OutStreamer.AddBlankLine(); } // Emit variables defined in this module and are available to other modules. @@ -336,10 +348,14 @@ void PIC16AsmPrinter::EmitDefinedVars(Module &M) { std::vector<const GlobalVariable*> Items = ExternalVarDefs; if (!Items.size()) return; - O << "\n" << MAI->getCommentString() << "Exported Variables - BEGIN" << "\n"; + OutStreamer.AddComment("Exported Variables - BEGIN"); + OutStreamer.AddBlankLine(); + for (unsigned j = 0; j < Items.size(); j++) - O << MAI->getGlobalDirective() << *Mang->getSymbol(Items[j]) << "\n"; - O << MAI->getCommentString() << "Exported Variables - END" << "\n"; + OutStreamer.EmitRawText(MAI->getGlobalDirective() + + Twine(Mang->getSymbol(Items[j])->getName())); + OutStreamer.AddComment("Exported Variables - END"); + OutStreamer.AddBlankLine(); } // Emit initialized data placed in ROM. @@ -356,7 +372,7 @@ bool PIC16AsmPrinter::doFinalization(Module &M) { EmitAllAutos(M); printLibcallDecls(); DbgInfo.EndModule(M); - O << "\n\t" << "END\n"; + OutStreamer.EmitRawText(StringRef("\tEND")); return AsmPrinter::doFinalization(M); } @@ -364,7 +380,6 @@ void PIC16AsmPrinter::EmitFunctionFrame(MachineFunction &MF) { const Function *F = MF.getFunction(); const TargetData *TD = TM.getTargetData(); // Emit the data section name. - O << "\n"; PIC16Section *fPDataSection = const_cast<PIC16Section *>(getObjFileLowering(). @@ -374,7 +389,8 @@ void PIC16AsmPrinter::EmitFunctionFrame(MachineFunction &MF) { OutStreamer.SwitchSection(fPDataSection); // Emit function frame label - O << PAN::getFrameLabel(CurrentFnSym->getName()) << ":\n"; + OutStreamer.EmitRawText(PAN::getFrameLabel(CurrentFnSym->getName()) + + Twine(":")); const Type *RetType = F->getReturnType(); unsigned RetSize = 0; @@ -386,10 +402,11 @@ void PIC16AsmPrinter::EmitFunctionFrame(MachineFunction &MF) { // we will need to avoid printing a global directive for Retval label // in emitExternandGloblas. if(RetSize > 0) - O << PAN::getRetvalLabel(CurrentFnSym->getName()) - << " RES " << RetSize << "\n"; + OutStreamer.EmitRawText(PAN::getRetvalLabel(CurrentFnSym->getName()) + + Twine(" RES ") + Twine(RetSize)); else - O << PAN::getRetvalLabel(CurrentFnSym->getName()) << ": \n"; + OutStreamer.EmitRawText(PAN::getRetvalLabel(CurrentFnSym->getName()) + + Twine(":")); // Emit variable to hold the space for function arguments unsigned ArgSize = 0; @@ -399,13 +416,14 @@ void PIC16AsmPrinter::EmitFunctionFrame(MachineFunction &MF) { ArgSize += TD->getTypeAllocSize(Ty); } - O << PAN::getArgsLabel(CurrentFnSym->getName()) << " RES " << ArgSize << "\n"; + OutStreamer.EmitRawText(PAN::getArgsLabel(CurrentFnSym->getName()) + + Twine(" RES ") + Twine(ArgSize)); // Emit temporary space int TempSize = PTLI->GetTmpSize(); if (TempSize > 0) - O << PAN::getTempdataLabel(CurrentFnSym->getName()) << " RES " - << TempSize << '\n'; + OutStreamer.EmitRawText(PAN::getTempdataLabel(CurrentFnSym->getName()) + + Twine(" RES ") + Twine(TempSize)); } @@ -417,7 +435,7 @@ void PIC16AsmPrinter::EmitInitializedDataSection(const PIC16Section *S) { for (unsigned j = 0; j < Items.size(); j++) { Constant *C = Items[j]->getInitializer(); int AddrSpace = Items[j]->getType()->getAddressSpace(); - O << *Mang->getSymbol(Items[j]); + OutStreamer.EmitRawText(Mang->getSymbol(Items[j])->getName()); EmitGlobalConstant(C, AddrSpace); } } @@ -436,7 +454,8 @@ EmitUninitializedDataSection(const PIC16Section *S) { Constant *C = Items[j]->getInitializer(); const Type *Ty = C->getType(); unsigned Size = TD->getTypeAllocSize(Ty); - O << *Mang->getSymbol(Items[j]) << " RES " << Size << "\n"; + OutStreamer.EmitRawText(Mang->getSymbol(Items[j])->getName() + + Twine(" RES ") + Twine(Size)); } } @@ -484,7 +503,7 @@ EmitSectionList(Module &M, const std::vector<PIC16Section *> &SList) { // Exclude llvm specific metadata sections. if (SList[i]->getName().find("llvm.") != std::string::npos) continue; - O << "\n"; + OutStreamer.AddBlankLine(); EmitSingleSection(SList[i]); } } diff --git a/lib/Target/PIC16/AsmPrinter/PIC16AsmPrinter.h b/lib/Target/PIC16/AsmPrinter/PIC16AsmPrinter.h index 8063fcc6fc93..e27778fbb070 100644 --- a/lib/Target/PIC16/AsmPrinter/PIC16AsmPrinter.h +++ b/lib/Target/PIC16/AsmPrinter/PIC16AsmPrinter.h @@ -31,8 +31,7 @@ namespace llvm { class VISIBILITY_HIDDEN PIC16AsmPrinter : public AsmPrinter { public: - explicit PIC16AsmPrinter(formatted_raw_ostream &O, TargetMachine &TM, - MCStreamer &Streamer); + explicit PIC16AsmPrinter(TargetMachine &TM, MCStreamer &Streamer); private: virtual const char *getPassName() const { return "PIC16 Assembly Printer"; @@ -43,9 +42,9 @@ namespace llvm { } bool runOnMachineFunction(MachineFunction &F); - void printOperand(const MachineInstr *MI, int opNum); - void printCCOperand(const MachineInstr *MI, int opNum); - void printInstruction(const MachineInstr *MI); // definition autogenerated. + void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); + void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O); + void printInstruction(const MachineInstr *MI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); void EmitInstruction(const MachineInstr *MI); diff --git a/lib/Target/PIC16/PIC16DebugInfo.cpp b/lib/Target/PIC16/PIC16DebugInfo.cpp index a223540170a7..5d86329e9b9b 100644 --- a/lib/Target/PIC16/PIC16DebugInfo.cpp +++ b/lib/Target/PIC16/PIC16DebugInfo.cpp @@ -18,10 +18,10 @@ #include "llvm/GlobalVariable.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCStreamer.h" #include "llvm/Support/DebugLoc.h" -#include "llvm/Support/FormattedStream.h" #include "llvm/ADT/SmallString.h" - +#include "llvm/ADT/StringExtras.h" using namespace llvm; /// PopulateDebugInfo - Populate the TypeNo, Aux[] and TagName from Ty. @@ -267,7 +267,8 @@ void PIC16DbgInfo::ChangeDebugLoc(const MachineFunction &MF, /// void PIC16DbgInfo::SwitchToLine(unsigned Line, bool IsInBeginFunction) { if (CurLine == Line) return; - if (!IsInBeginFunction) O << "\n\t.line " << Line << "\n"; + if (!IsInBeginFunction) + OS.EmitRawText("\n\t.line " + Twine(Line)); CurLine = Line; } @@ -286,7 +287,7 @@ void PIC16DbgInfo::EndFunction(const MachineFunction &MF) { void PIC16DbgInfo::EndModule(Module &M) { if (! EmitDebugDirectives) return; EmitVarDebugInfo(M); - if (CurFile != "") O << "\n\t.eof"; + if (CurFile != "") OS.EmitRawText(StringRef("\n\t.eof")); } /// EmitCompositeTypeElements - Emit debug information for members of a @@ -410,22 +411,26 @@ void PIC16DbgInfo::EmitFunctEndDI(const Function *F, unsigned Line) { /// void PIC16DbgInfo::EmitAuxEntry(const std::string VarName, int Aux[], int Num, std::string TagName) { - O << "\n\t.dim " << VarName << ", 1" ; + std::string Tmp; // TagName is emitted in case of structure/union objects. - if (TagName != "") - O << ", " << TagName; + if (!TagName.empty()) Tmp += ", " + TagName; + for (int i = 0; i<Num; i++) - O << "," << (Aux[i] && 0xff); + Tmp += "," + utostr(Aux[i] && 0xff); + + OS.EmitRawText("\n\t.dim " + Twine(VarName) + ", 1" + Tmp); } /// EmitSymbol - Emit .def for a symbol. Value is offset for the member. /// -void PIC16DbgInfo::EmitSymbol(std::string Name, short Class, unsigned short - Type, unsigned long Value) { - O << "\n\t" << ".def "<< Name << ", type = " << Type << ", class = " - << Class; +void PIC16DbgInfo::EmitSymbol(std::string Name, short Class, + unsigned short Type, unsigned long Value) { + std::string Tmp; if (Value > 0) - O << ", value = " << Value; + Tmp = ", value = " + utostr(Value); + + OS.EmitRawText("\n\t.def " + Twine(Name) + ", type = " + utostr(Type) + + ", class = " + utostr(Class) + Tmp); } /// EmitVarDebugInfo - Emit debug information for all variables. @@ -447,14 +452,13 @@ void PIC16DbgInfo::EmitVarDebugInfo(Module &M) { PopulateDebugInfo(Ty, TypeNo, HasAux, Aux, TagName); // Emit debug info only if type information is availaible. if (TypeNo != PIC16Dbg::T_NULL) { - O << "\n\t.type " << VarName << ", " << TypeNo; + OS.EmitRawText("\t.type " + Twine(VarName) + ", " + Twine(TypeNo)); short ClassNo = getStorageClass(DIGV); - O << "\n\t.class " << VarName << ", " << ClassNo; - if (HasAux) + OS.EmitRawText("\t.class " + Twine(VarName) + ", " + Twine(ClassNo)); + if (HasAux) EmitAuxEntry(VarName, Aux, PIC16Dbg::AuxSize, TagName); } } - O << "\n"; } /// SwitchToCU - Switch to a new compilation unit. @@ -470,8 +474,9 @@ void PIC16DbgInfo::SwitchToCU(MDNode *CU) { if ( FilePath == CurFile ) return; // Else, close the current one and start a new. - if (CurFile != "") O << "\n\t.eof"; - O << "\n\t.file\t\"" << FilePath << "\"\n" ; + if (CurFile != "") + OS.EmitRawText(StringRef("\t.eof")); + OS.EmitRawText("\n\t.file\t\"" + Twine(FilePath) + "\""); CurFile = FilePath; CurLine = 0; } @@ -480,6 +485,6 @@ void PIC16DbgInfo::SwitchToCU(MDNode *CU) { /// void PIC16DbgInfo::EmitEOF() { if (CurFile != "") - O << "\n\t.EOF"; + OS.EmitRawText(StringRef("\t.EOF")); } diff --git a/lib/Target/PIC16/PIC16DebugInfo.h b/lib/Target/PIC16/PIC16DebugInfo.h index 54e27c7c3377..031dcf092f04 100644 --- a/lib/Target/PIC16/PIC16DebugInfo.h +++ b/lib/Target/PIC16/PIC16DebugInfo.h @@ -20,6 +20,8 @@ namespace llvm { class MachineFunction; class DebugLoc; + class MCStreamer; + namespace PIC16Dbg { enum VarType { T_NULL, @@ -88,10 +90,8 @@ namespace llvm { }; } - class formatted_raw_ostream; - class PIC16DbgInfo { - formatted_raw_ostream &O; + MCStreamer &OS; const MCAsmInfo *MAI; std::string CurFile; unsigned CurLine; @@ -101,8 +101,7 @@ namespace llvm { bool EmitDebugDirectives; public: - PIC16DbgInfo(formatted_raw_ostream &o, const MCAsmInfo *T) - : O(o), MAI(T) { + PIC16DbgInfo(MCStreamer &os, const MCAsmInfo *T) : OS(os), MAI(T) { CurFile = ""; CurLine = 0; EmitDebugDirectives = false; diff --git a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp index 5adefd39c51b..605656493c4b 100644 --- a/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp +++ b/lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp @@ -26,7 +26,6 @@ #include "llvm/Module.h" #include "llvm/Assembly/Writer.h" #include "llvm/CodeGen/AsmPrinter.h" -#include "llvm/CodeGen/DwarfWriter.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" @@ -44,10 +43,8 @@ #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetRegistry.h" #include "llvm/Support/MathExtras.h" -#include "llvm/Support/CommandLine.h" -#include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/FormattedStream.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringSet.h" #include "llvm/ADT/SmallString.h" @@ -56,13 +53,12 @@ using namespace llvm; namespace { class PPCAsmPrinter : public AsmPrinter { protected: - DenseMap<const MCSymbol*, const MCSymbol*> TOC; + DenseMap<MCSymbol*, MCSymbol*> TOC; const PPCSubtarget &Subtarget; uint64_t LabelID; public: - explicit PPCAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM, - MCStreamer &Streamer) - : AsmPrinter(O, TM, Streamer), + explicit PPCAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) + : AsmPrinter(TM, Streamer), Subtarget(TM.getSubtarget<PPCSubtarget>()), LabelID(0) {} virtual const char *getPassName() const { @@ -92,12 +88,12 @@ namespace { /// from the instruction set description. This method returns true if the /// machine instruction was sufficiently described to print it, otherwise it /// returns false. - void printInstruction(const MachineInstr *MI); + void printInstruction(const MachineInstr *MI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); virtual void EmitInstruction(const MachineInstr *MI); - void printOp(const MachineOperand &MO); + void printOp(const MachineOperand &MO, raw_ostream &O); /// stripRegisterPrefix - This method strips the character prefix from a /// register name so that only the number is left. Used by for linux asm. @@ -114,7 +110,7 @@ namespace { /// printRegister - Print register according to target requirements. /// - void printRegister(const MachineOperand &MO, bool R0AsZero) { + void printRegister(const MachineOperand &MO, bool R0AsZero, raw_ostream &O){ unsigned RegNo = MO.getReg(); assert(TargetRegisterInfo::isPhysicalRegister(RegNo) && "Not physreg??"); @@ -131,66 +127,76 @@ namespace { O << RegName; } - void printOperand(const MachineInstr *MI, unsigned OpNo) { + void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNo); if (MO.isReg()) { - printRegister(MO, false); + printRegister(MO, false, O); } else if (MO.isImm()) { O << MO.getImm(); } else { - printOp(MO); + printOp(MO, O); } } bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode); + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O); bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode); + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O); - void printS5ImmOperand(const MachineInstr *MI, unsigned OpNo) { + void printS5ImmOperand(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { char value = MI->getOperand(OpNo).getImm(); value = (value << (32-5)) >> (32-5); O << (int)value; } - void printU5ImmOperand(const MachineInstr *MI, unsigned OpNo) { + void printU5ImmOperand(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { unsigned char value = MI->getOperand(OpNo).getImm(); assert(value <= 31 && "Invalid u5imm argument!"); O << (unsigned int)value; } - void printU6ImmOperand(const MachineInstr *MI, unsigned OpNo) { + void printU6ImmOperand(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { unsigned char value = MI->getOperand(OpNo).getImm(); assert(value <= 63 && "Invalid u6imm argument!"); O << (unsigned int)value; } - void printS16ImmOperand(const MachineInstr *MI, unsigned OpNo) { + void printS16ImmOperand(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { O << (short)MI->getOperand(OpNo).getImm(); } - void printU16ImmOperand(const MachineInstr *MI, unsigned OpNo) { + void printU16ImmOperand(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { O << (unsigned short)MI->getOperand(OpNo).getImm(); } - void printS16X4ImmOperand(const MachineInstr *MI, unsigned OpNo) { + void printS16X4ImmOperand(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { if (MI->getOperand(OpNo).isImm()) { O << (short)(MI->getOperand(OpNo).getImm()*4); } else { O << "lo16("; - printOp(MI->getOperand(OpNo)); + printOp(MI->getOperand(OpNo), O); if (TM.getRelocationModel() == Reloc::PIC_) O << "-\"L" << getFunctionNumber() << "$pb\")"; else O << ')'; } } - void printBranchOperand(const MachineInstr *MI, unsigned OpNo) { + void printBranchOperand(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { // Branches can take an immediate operand. This is used by the branch // selection pass to print $+8, an eight byte displacement from the PC. if (MI->getOperand(OpNo).isImm()) { O << "$+" << MI->getOperand(OpNo).getImm()*4; } else { - printOp(MI->getOperand(OpNo)); + printOp(MI->getOperand(OpNo), O); } } - void printCallOperand(const MachineInstr *MI, unsigned OpNo) { + void printCallOperand(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNo); if (TM.getRelocationModel() != Reloc::Static) { if (MO.getType() == MachineOperand::MO_GlobalAddress) { @@ -223,21 +229,22 @@ namespace { } } - printOp(MI->getOperand(OpNo)); + printOp(MI->getOperand(OpNo), O); } - void printAbsAddrOperand(const MachineInstr *MI, unsigned OpNo) { + void printAbsAddrOperand(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { O << (int)MI->getOperand(OpNo).getImm()*4; } - void printPICLabel(const MachineInstr *MI, unsigned OpNo) { + void printPICLabel(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { O << "\"L" << getFunctionNumber() << "$pb\"\n"; O << "\"L" << getFunctionNumber() << "$pb\":"; } - void printSymbolHi(const MachineInstr *MI, unsigned OpNo) { + void printSymbolHi(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { if (MI->getOperand(OpNo).isImm()) { - printS16ImmOperand(MI, OpNo); + printS16ImmOperand(MI, OpNo, O); } else { if (Subtarget.isDarwin()) O << "ha16("; - printOp(MI->getOperand(OpNo)); + printOp(MI->getOperand(OpNo), O); if (TM.getRelocationModel() == Reloc::PIC_) O << "-\"L" << getFunctionNumber() << "$pb\""; if (Subtarget.isDarwin()) @@ -246,12 +253,12 @@ namespace { O << "@ha"; } } - void printSymbolLo(const MachineInstr *MI, unsigned OpNo) { + void printSymbolLo(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { if (MI->getOperand(OpNo).isImm()) { - printS16ImmOperand(MI, OpNo); + printS16ImmOperand(MI, OpNo, O); } else { if (Subtarget.isDarwin()) O << "lo16("; - printOp(MI->getOperand(OpNo)); + printOp(MI->getOperand(OpNo), O); if (TM.getRelocationModel() == Reloc::PIC_) O << "-\"L" << getFunctionNumber() << "$pb\""; if (Subtarget.isDarwin()) @@ -260,53 +267,55 @@ namespace { O << "@l"; } } - void printcrbitm(const MachineInstr *MI, unsigned OpNo) { + void printcrbitm(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { unsigned CCReg = MI->getOperand(OpNo).getReg(); unsigned RegNo = enumRegToMachineReg(CCReg); O << (0x80 >> RegNo); } // The new addressing mode printers. - void printMemRegImm(const MachineInstr *MI, unsigned OpNo) { - printSymbolLo(MI, OpNo); + void printMemRegImm(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { + printSymbolLo(MI, OpNo, O); O << '('; if (MI->getOperand(OpNo+1).isReg() && MI->getOperand(OpNo+1).getReg() == PPC::R0) O << "0"; else - printOperand(MI, OpNo+1); + printOperand(MI, OpNo+1, O); O << ')'; } - void printMemRegImmShifted(const MachineInstr *MI, unsigned OpNo) { + void printMemRegImmShifted(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { if (MI->getOperand(OpNo).isImm()) - printS16X4ImmOperand(MI, OpNo); + printS16X4ImmOperand(MI, OpNo, O); else - printSymbolLo(MI, OpNo); + printSymbolLo(MI, OpNo, O); O << '('; if (MI->getOperand(OpNo+1).isReg() && MI->getOperand(OpNo+1).getReg() == PPC::R0) O << "0"; else - printOperand(MI, OpNo+1); + printOperand(MI, OpNo+1, O); O << ')'; } - void printMemRegReg(const MachineInstr *MI, unsigned OpNo) { + void printMemRegReg(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { // When used as the base register, r0 reads constant zero rather than // the value contained in the register. For this reason, the darwin // assembler requires that we print r0 as 0 (no r) when used as the base. const MachineOperand &MO = MI->getOperand(OpNo); - printRegister(MO, true); + printRegister(MO, true, O); O << ", "; - printOperand(MI, OpNo+1); + printOperand(MI, OpNo+1, O); } - void printTOCEntryLabel(const MachineInstr *MI, unsigned OpNo) { + void printTOCEntryLabel(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNo); assert(MO.getType() == MachineOperand::MO_GlobalAddress); - const MCSymbol *Sym = Mang->getSymbol(MO.getGlobal()); + MCSymbol *Sym = Mang->getSymbol(MO.getGlobal()); // Map symbol -> label of TOC entry. - const MCSymbol *&TOCEntry = TOC[Sym]; + MCSymbol *&TOCEntry = TOC[Sym]; if (TOCEntry == 0) TOCEntry = OutContext. GetOrCreateSymbol(StringRef(MAI->getPrivateGlobalPrefix()) + @@ -316,15 +325,14 @@ namespace { } void printPredicateOperand(const MachineInstr *MI, unsigned OpNo, - const char *Modifier); + raw_ostream &O, const char *Modifier); }; /// PPCLinuxAsmPrinter - PowerPC assembly printer, customized for Linux class PPCLinuxAsmPrinter : public PPCAsmPrinter { public: - explicit PPCLinuxAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM, - MCStreamer &Streamer) - : PPCAsmPrinter(O, TM, Streamer) {} + explicit PPCLinuxAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) + : PPCAsmPrinter(TM, Streamer) {} virtual const char *getPassName() const { return "Linux PPC Assembly Printer"; @@ -333,23 +341,14 @@ namespace { bool doFinalization(Module &M); virtual void EmitFunctionEntryLabel(); - - void getAnalysisUsage(AnalysisUsage &AU) const { - AU.setPreservesAll(); - AU.addRequired<MachineModuleInfo>(); - AU.addRequired<DwarfWriter>(); - PPCAsmPrinter::getAnalysisUsage(AU); - } }; /// PPCDarwinAsmPrinter - PowerPC assembly printer, customized for Darwin/Mac /// OS X class PPCDarwinAsmPrinter : public PPCAsmPrinter { - formatted_raw_ostream &OS; public: - explicit PPCDarwinAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM, - MCStreamer &Streamer) - : PPCAsmPrinter(O, TM, Streamer), OS(O) {} + explicit PPCDarwinAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) + : PPCAsmPrinter(TM, Streamer) {} virtual const char *getPassName() const { return "Darwin PPC Assembly Printer"; @@ -359,20 +358,13 @@ namespace { void EmitStartOfAsmFile(Module &M); void EmitFunctionStubs(const MachineModuleInfoMachO::SymbolListTy &Stubs); - - void getAnalysisUsage(AnalysisUsage &AU) const { - AU.setPreservesAll(); - AU.addRequired<MachineModuleInfo>(); - AU.addRequired<DwarfWriter>(); - PPCAsmPrinter::getAnalysisUsage(AU); - } }; } // end of anonymous namespace // Include the auto-generated portion of the assembly writer #include "PPCGenAsmWriter.inc" -void PPCAsmPrinter::printOp(const MachineOperand &MO) { +void PPCAsmPrinter::printOp(const MachineOperand &MO, raw_ostream &O) { switch (MO.getType()) { case MachineOperand::MO_Immediate: llvm_unreachable("printOp() does not handle immediate values"); @@ -446,7 +438,7 @@ void PPCAsmPrinter::printOp(const MachineOperand &MO) { O << *SymToPrint; - printOffset(MO.getOffset()); + printOffset(MO.getOffset(), O); return; } @@ -460,7 +452,7 @@ void PPCAsmPrinter::printOp(const MachineOperand &MO) { /// bool PPCAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, - const char *ExtraCode) { + const char *ExtraCode, raw_ostream &O) { // Does this asm operand have a single letter operand modifier? if (ExtraCode && ExtraCode[0]) { if (ExtraCode[1] != 0) return true; // Unknown modifier. @@ -469,7 +461,7 @@ bool PPCAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, default: return true; // Unknown modifier. case 'c': // Don't print "$" before a global var name or constant. // PPC never has a prefix. - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); return false; case 'L': // Write second word of DImode reference. // Verify that this operand has two consecutive registers. @@ -488,7 +480,7 @@ bool PPCAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, } } - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); return false; } @@ -498,18 +490,19 @@ bool PPCAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, bool PPCAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, - const char *ExtraCode) { + const char *ExtraCode, + raw_ostream &O) { if (ExtraCode && ExtraCode[0]) return true; // Unknown modifier. assert (MI->getOperand(OpNo).isReg()); O << "0("; - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); O << ")"; return false; } void PPCAsmPrinter::printPredicateOperand(const MachineInstr *MI, unsigned OpNo, - const char *Modifier) { + raw_ostream &O, const char *Modifier){ assert(Modifier && "Must specify 'cc' or 'reg' as predicate op modifier!"); unsigned Code = MI->getOperand(OpNo).getImm(); if (!strcmp(Modifier, "cc")) { @@ -530,7 +523,7 @@ void PPCAsmPrinter::printPredicateOperand(const MachineInstr *MI, unsigned OpNo, "Need to specify 'cc' or 'reg' as predicate op modifier!"); // Don't print the register for 'always'. if (Code == PPC::PRED_ALWAYS) return; - printOperand(MI, OpNo+1); + printOperand(MI, OpNo+1, O); } } @@ -539,6 +532,9 @@ void PPCAsmPrinter::printPredicateOperand(const MachineInstr *MI, unsigned OpNo, /// the current output stream. /// void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { + SmallString<128> Str; + raw_svector_ostream O(Str); + // Check for slwi/srwi mnemonics. if (MI->getOpcode() == PPC::RLWINM) { unsigned char SH = MI->getOperand(2).getImm(); @@ -553,11 +549,11 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { SH = 32-SH; } if (useSubstituteMnemonic) { - printOperand(MI, 0); + printOperand(MI, 0, O); O << ", "; - printOperand(MI, 1); + printOperand(MI, 1, O); O << ", " << (unsigned int)SH; - OutStreamer.AddBlankLine(); + OutStreamer.EmitRawText(O.str()); return; } } @@ -565,10 +561,10 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { O << "\tmr "; - printOperand(MI, 0); + printOperand(MI, 0, O); O << ", "; - printOperand(MI, 1); - OutStreamer.AddBlankLine(); + printOperand(MI, 1, O); + OutStreamer.EmitRawText(O.str()); return; } @@ -578,17 +574,17 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) { // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH if (63-SH == ME) { O << "\tsldi "; - printOperand(MI, 0); + printOperand(MI, 0, O); O << ", "; - printOperand(MI, 1); + printOperand(MI, 1, O); O << ", " << (unsigned int)SH; - OutStreamer.AddBlankLine(); + OutStreamer.EmitRawText(O.str()); return; } } - printInstruction(MI); - OutStreamer.AddBlankLine(); + printInstruction(MI, O); + OutStreamer.EmitRawText(O.str()); } void PPCLinuxAsmPrinter::EmitFunctionEntryLabel() { @@ -597,12 +593,13 @@ void PPCLinuxAsmPrinter::EmitFunctionEntryLabel() { // Emit an official procedure descriptor. // FIXME 64-bit SVR4: Use MCSection here! - O << "\t.section\t\".opd\",\"aw\"\n"; - O << "\t.align 3\n"; + OutStreamer.EmitRawText(StringRef("\t.section\t\".opd\",\"aw\"")); + OutStreamer.EmitRawText(StringRef("\t.align 3")); OutStreamer.EmitLabel(CurrentFnSym); - O << "\t.quad .L." << *CurrentFnSym << ",.TOC.@tocbase\n"; - O << "\t.previous\n"; - O << ".L." << *CurrentFnSym << ":\n"; + OutStreamer.EmitRawText("\t.quad .L." + Twine(CurrentFnSym->getName()) + + ",.TOC.@tocbase"); + OutStreamer.EmitRawText(StringRef("\t.previous")); + OutStreamer.EmitRawText(".L." + Twine(CurrentFnSym->getName()) + ":"); } @@ -613,13 +610,14 @@ bool PPCLinuxAsmPrinter::doFinalization(Module &M) { if (isPPC64 && !TOC.empty()) { // FIXME 64-bit SVR4: Use MCSection here? - O << "\t.section\t\".toc\",\"aw\"\n"; + OutStreamer.EmitRawText(StringRef("\t.section\t\".toc\",\"aw\"")); // FIXME: This is nondeterminstic! - for (DenseMap<const MCSymbol*, const MCSymbol*>::iterator I = TOC.begin(), + for (DenseMap<MCSymbol*, MCSymbol*>::iterator I = TOC.begin(), E = TOC.end(); I != E; ++I) { - O << *I->second << ":\n"; - O << "\t.tc " << *I->first << "[TC]," << *I->first << '\n'; + OutStreamer.EmitLabel(I->second); + OutStreamer.EmitRawText("\t.tc " + Twine(I->first->getName()) + + "[TC]," + I->first->getName()); } } @@ -647,7 +645,7 @@ void PPCDarwinAsmPrinter::EmitStartOfAsmFile(Module &M) { if (Subtarget.isPPC64() && Directive < PPC::DIR_970) Directive = PPC::DIR_64; assert(Directive <= PPC::DIR_64 && "Directive out of range."); - O << "\t.machine " << CPUDirectives[Directive] << '\n'; + OutStreamer.EmitRawText("\t.machine " + Twine(CPUDirectives[Directive])); // Prime text sections so they are adjacent. This reduces the likelihood a // large data or debug section causes a branch to exceed 16M limit. @@ -670,14 +668,14 @@ void PPCDarwinAsmPrinter::EmitStartOfAsmFile(Module &M) { OutStreamer.SwitchSection(getObjFileLowering().getTextSection()); } -static const MCSymbol *GetLazyPtr(const MCSymbol *Sym, MCContext &Ctx) { +static MCSymbol *GetLazyPtr(MCSymbol *Sym, MCContext &Ctx) { // Remove $stub suffix, add $lazy_ptr. SmallString<128> TmpStr(Sym->getName().begin(), Sym->getName().end()-5); TmpStr += "$lazy_ptr"; return Ctx.GetOrCreateSymbol(TmpStr.str()); } -static const MCSymbol *GetAnonSym(const MCSymbol *Sym, MCContext &Ctx) { +static MCSymbol *GetAnonSym(MCSymbol *Sym, MCContext &Ctx) { // Add $tmp suffix to $stub, yielding $stub$tmp. SmallString<128> TmpStr(Sym->getName().begin(), Sym->getName().end()); TmpStr += "$tmp"; @@ -705,31 +703,41 @@ EmitFunctionStubs(const MachineModuleInfoMachO::SymbolListTy &Stubs) { OutStreamer.SwitchSection(StubSection); EmitAlignment(4); - const MCSymbol *Stub = Stubs[i].first; - const MCSymbol *RawSym = Stubs[i].second.getPointer(); - const MCSymbol *LazyPtr = GetLazyPtr(Stub, OutContext); - const MCSymbol *AnonSymbol = GetAnonSym(Stub, OutContext); + MCSymbol *Stub = Stubs[i].first; + MCSymbol *RawSym = Stubs[i].second.getPointer(); + MCSymbol *LazyPtr = GetLazyPtr(Stub, OutContext); + MCSymbol *AnonSymbol = GetAnonSym(Stub, OutContext); - O << *Stub << ":\n"; - O << "\t.indirect_symbol " << *RawSym << '\n'; - O << "\tmflr r0\n"; - O << "\tbcl 20,31," << *AnonSymbol << '\n'; - O << *AnonSymbol << ":\n"; - O << "\tmflr r11\n"; - O << "\taddis r11,r11,ha16(" << *LazyPtr << '-' << *AnonSymbol - << ")\n"; - O << "\tmtlr r0\n"; - O << (isPPC64 ? "\tldu" : "\tlwzu") << " r12,lo16(" << *LazyPtr - << '-' << *AnonSymbol << ")(r11)\n"; - O << "\tmtctr r12\n"; - O << "\tbctr\n"; + OutStreamer.EmitLabel(Stub); + OutStreamer.EmitSymbolAttribute(RawSym, MCSA_IndirectSymbol); + // FIXME: MCize this. + OutStreamer.EmitRawText(StringRef("\tmflr r0")); + OutStreamer.EmitRawText("\tbcl 20,31," + Twine(AnonSymbol->getName())); + OutStreamer.EmitLabel(AnonSymbol); + OutStreamer.EmitRawText(StringRef("\tmflr r11")); + OutStreamer.EmitRawText("\taddis r11,r11,ha16("+Twine(LazyPtr->getName())+ + "-" + AnonSymbol->getName() + ")"); + OutStreamer.EmitRawText(StringRef("\tmtlr r0")); + + if (isPPC64) + OutStreamer.EmitRawText("\tldu r12,lo16(" + Twine(LazyPtr->getName()) + + "-" + AnonSymbol->getName() + ")(r11)"); + else + OutStreamer.EmitRawText("\tlwzu r12,lo16(" + Twine(LazyPtr->getName()) + + "-" + AnonSymbol->getName() + ")(r11)"); + OutStreamer.EmitRawText(StringRef("\tmtctr r12")); + OutStreamer.EmitRawText(StringRef("\tbctr")); OutStreamer.SwitchSection(LSPSection); - O << *LazyPtr << ":\n"; - O << "\t.indirect_symbol " << *RawSym << '\n'; - O << (isPPC64 ? "\t.quad" : "\t.long") << " dyld_stub_binding_helper\n"; + OutStreamer.EmitLabel(LazyPtr); + OutStreamer.EmitSymbolAttribute(RawSym, MCSA_IndirectSymbol); + + if (isPPC64) + OutStreamer.EmitRawText(StringRef("\t.quad dyld_stub_binding_helper")); + else + OutStreamer.EmitRawText(StringRef("\t.long dyld_stub_binding_helper")); } - O << '\n'; + OutStreamer.AddBlankLine(); return; } @@ -739,26 +747,34 @@ EmitFunctionStubs(const MachineModuleInfoMachO::SymbolListTy &Stubs) { MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS, 16, SectionKind::getText()); for (unsigned i = 0, e = Stubs.size(); i != e; ++i) { - const MCSymbol *Stub = Stubs[i].first; - const MCSymbol *RawSym = Stubs[i].second.getPointer(); - const MCSymbol *LazyPtr = GetLazyPtr(Stub, OutContext); + MCSymbol *Stub = Stubs[i].first; + MCSymbol *RawSym = Stubs[i].second.getPointer(); + MCSymbol *LazyPtr = GetLazyPtr(Stub, OutContext); OutStreamer.SwitchSection(StubSection); EmitAlignment(4); - O << *Stub << ":\n"; - O << "\t.indirect_symbol " << *RawSym << '\n'; - O << "\tlis r11,ha16(" << *LazyPtr << ")\n"; - O << (isPPC64 ? "\tldu" : "\tlwzu") << " r12,lo16(" << *LazyPtr - << ")(r11)\n"; - O << "\tmtctr r12\n"; - O << "\tbctr\n"; + OutStreamer.EmitLabel(Stub); + OutStreamer.EmitSymbolAttribute(RawSym, MCSA_IndirectSymbol); + OutStreamer.EmitRawText("\tlis r11,ha16(" + Twine(LazyPtr->getName()) +")"); + if (isPPC64) + OutStreamer.EmitRawText("\tldu r12,lo16(" + Twine(LazyPtr->getName()) + + ")(r11)"); + else + OutStreamer.EmitRawText("\tlwzu r12,lo16(" + Twine(LazyPtr->getName()) + + ")(r11)"); + OutStreamer.EmitRawText(StringRef("\tmtctr r12")); + OutStreamer.EmitRawText(StringRef("\tbctr")); OutStreamer.SwitchSection(LSPSection); - O << *LazyPtr << ":\n"; - O << "\t.indirect_symbol " << *RawSym << '\n'; - O << (isPPC64 ? "\t.quad" : "\t.long") << " dyld_stub_binding_helper\n"; + OutStreamer.EmitLabel(LazyPtr); + OutStreamer.EmitSymbolAttribute(RawSym, MCSA_IndirectSymbol); + + if (isPPC64) + OutStreamer.EmitRawText(StringRef("\t.quad dyld_stub_binding_helper")); + else + OutStreamer.EmitRawText(StringRef("\t.long dyld_stub_binding_helper")); } - O << '\n'; + OutStreamer.AddBlankLine(); } @@ -858,14 +874,13 @@ bool PPCDarwinAsmPrinter::doFinalization(Module &M) { /// for a MachineFunction to the given output stream, in a format that the /// Darwin assembler can deal with. /// -static AsmPrinter *createPPCAsmPrinterPass(formatted_raw_ostream &o, - TargetMachine &tm, +static AsmPrinter *createPPCAsmPrinterPass(TargetMachine &tm, MCStreamer &Streamer) { const PPCSubtarget *Subtarget = &tm.getSubtarget<PPCSubtarget>(); if (Subtarget->isDarwin()) - return new PPCDarwinAsmPrinter(o, tm, Streamer); - return new PPCLinuxAsmPrinter(o, tm, Streamer); + return new PPCDarwinAsmPrinter(tm, Streamer); + return new PPCLinuxAsmPrinter(tm, Streamer); } // Force static initialization. diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td index 08f5bb43087f..27644b2daca8 100644 --- a/lib/Target/PowerPC/PPC.td +++ b/lib/Target/PowerPC/PPC.td @@ -96,14 +96,6 @@ def : Processor<"ppc64", G5Itineraries, include "PPCCallingConv.td" def PPCInstrInfo : InstrInfo { - // Define how we want to layout our TargetSpecific information field... This - // should be kept up-to-date with the fields in the PPCInstrInfo.h file. - let TSFlagsFields = ["PPC970_First", - "PPC970_Single", - "PPC970_Cracked", - "PPC970_Unit"]; - let TSFlagsShifts = [0, 1, 2, 3]; - let isLittleEndianEncoding = 1; } diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index dda530eef434..9cd01be54e42 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -2392,7 +2392,7 @@ CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, DebugLoc dl) { SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), - false, NULL, 0, NULL, 0); + false, false, NULL, 0, NULL, 0); } /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index 54cebcdecd61..4357bdccec7b 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -23,13 +23,18 @@ class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> let InOperandList = IOL; let AsmString = asmstr; let Itinerary = itin; - - /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to - /// these must be reflected there! See comments there for what these are. + bits<1> PPC970_First = 0; bits<1> PPC970_Single = 0; bits<1> PPC970_Cracked = 0; bits<3> PPC970_Unit = 0; + + /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to + /// these must be reflected there! See comments there for what these are. + let TSFlags{0} = PPC970_First; + let TSFlags{1} = PPC970_Single; + let TSFlags{2} = PPC970_Cracked; + let TSFlags{5-3} = PPC970_Unit; } class PPC970_DGroup_First { bits<1> PPC970_First = 1; } diff --git a/lib/Target/PowerPC/PPCMCAsmInfo.cpp b/lib/Target/PowerPC/PPCMCAsmInfo.cpp index b37aee804ac2..3644c79d0410 100644 --- a/lib/Target/PowerPC/PPCMCAsmInfo.cpp +++ b/lib/Target/PowerPC/PPCMCAsmInfo.cpp @@ -38,7 +38,6 @@ PPCLinuxMCAsmInfo::PPCLinuxMCAsmInfo(bool is64Bit) { UsesELFSectionDirectiveForBSS = true; // Debug Information - AbsoluteDebugSectionOffsets = true; SupportsDebugInformation = true; PCSymbol = "."; @@ -49,7 +48,6 @@ PPCLinuxMCAsmInfo::PPCLinuxMCAsmInfo(bool is64Bit) { // Exceptions handling if (!is64Bit) ExceptionsType = ExceptionHandling::Dwarf; - AbsoluteEHSectionOffsets = false; ZeroDirective = "\t.space\t"; Data64bitsDirective = is64Bit ? "\t.quad\t" : 0; diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 9363aa8b7566..52d87cde803f 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -1280,9 +1280,9 @@ PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); - MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); + MachineModuleInfo &MMI = MF.getMMI(); DebugLoc dl; - bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) || + bool needsFrameMoves = MMI.hasDebugInfo() || !MF.getFunction()->doesNotThrow() || UnwindTablesMandatory; @@ -1442,13 +1442,13 @@ PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { } } - std::vector<MachineMove> &Moves = MMI->getFrameMoves(); + std::vector<MachineMove> &Moves = MMI.getFrameMoves(); // Add the "machine moves" for the instructions we generated above, but in // reverse order. if (needsFrameMoves) { // Mark effective beginning of when frame pointer becomes valid. - FrameLabel = MMI->getContext().CreateTempSymbol(); + FrameLabel = MMI.getContext().CreateTempSymbol(); BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addSym(FrameLabel); // Show update of SP. @@ -1489,7 +1489,7 @@ PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { } if (needsFrameMoves) { - ReadyLabel = MMI->getContext().CreateTempSymbol(); + ReadyLabel = MMI.getContext().CreateTempSymbol(); // Mark effective beginning of when frame pointer is ready. BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addSym(ReadyLabel); diff --git a/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp b/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp index 3e40dbb17f88..ab948bb37ff2 100644 --- a/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp +++ b/lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp @@ -23,39 +23,43 @@ #include "llvm/MC/MCSymbol.h" #include "llvm/Target/Mangler.h" #include "llvm/Target/TargetRegistry.h" +#include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" -#include "llvm/Support/FormattedStream.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; namespace { class SparcAsmPrinter : public AsmPrinter { public: - explicit SparcAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM, - MCStreamer &Streamer) - : AsmPrinter(O, TM, Streamer) {} + explicit SparcAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) + : AsmPrinter(TM, Streamer) {} virtual const char *getPassName() const { return "Sparc Assembly Printer"; } - void printOperand(const MachineInstr *MI, int opNum); - void printMemOperand(const MachineInstr *MI, int opNum, + void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS); + void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS, const char *Modifier = 0); - void printCCOperand(const MachineInstr *MI, int opNum); + void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &OS); virtual void EmitInstruction(const MachineInstr *MI) { - printInstruction(MI); - OutStreamer.AddBlankLine(); + SmallString<128> Str; + raw_svector_ostream OS(Str); + printInstruction(MI, OS); + OutStreamer.EmitRawText(OS.str()); } - void printInstruction(const MachineInstr *MI); // autogenerated. + void printInstruction(const MachineInstr *MI, raw_ostream &OS);// autogen'd. static const char *getRegisterName(unsigned RegNo); bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode); + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O); bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode); + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O); - bool printGetPCX(const MachineInstr *MI, unsigned OpNo); + bool printGetPCX(const MachineInstr *MI, unsigned OpNo, raw_ostream &OS); virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const; @@ -64,7 +68,8 @@ namespace { #include "SparcGenAsmWriter.inc" -void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { +void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand (opNum); bool CloseParen = false; if (MI->getOpcode() == SP::SETHIi && !MO.isReg() && !MO.isImm()) { @@ -103,13 +108,13 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { } void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum, - const char *Modifier) { - printOperand(MI, opNum); + raw_ostream &O, const char *Modifier) { + printOperand(MI, opNum, O); // If this is an ADD operand, emit it like normal operands. if (Modifier && !strcmp(Modifier, "arith")) { O << ", "; - printOperand(MI, opNum+1); + printOperand(MI, opNum+1, O); return; } @@ -124,14 +129,15 @@ void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum, if (MI->getOperand(opNum+1).isGlobal() || MI->getOperand(opNum+1).isCPI()) { O << "%lo("; - printOperand(MI, opNum+1); + printOperand(MI, opNum+1, O); O << ")"; } else { - printOperand(MI, opNum+1); + printOperand(MI, opNum+1, O); } } -bool SparcAsmPrinter::printGetPCX(const MachineInstr *MI, unsigned opNum) { +bool SparcAsmPrinter::printGetPCX(const MachineInstr *MI, unsigned opNum, + raw_ostream &O) { std::string operand = ""; const MachineOperand &MO = MI->getOperand(opNum); switch (MO.getType()) { @@ -155,14 +161,15 @@ bool SparcAsmPrinter::printGetPCX(const MachineInstr *MI, unsigned opNum) { O << ".LLGETPC" << mfNum << '_' << bbNum << ":\n" ; O << "\tor\t" << operand - << ", %lo(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum << ")), " - << operand << '\n'; + << ", %lo(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum + << ")), " << operand << '\n'; O << "\tadd\t" << operand << ", %o7, " << operand << '\n'; return true; } -void SparcAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum) { +void SparcAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { int CC = (int)MI->getOperand(opNum).getImm(); O << SPARCCondCodeToString((SPCC::CondCodes)CC); } @@ -171,7 +178,8 @@ void SparcAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum) { /// bool SparcAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, - const char *ExtraCode) { + const char *ExtraCode, + raw_ostream &O) { if (ExtraCode && ExtraCode[0]) { if (ExtraCode[1] != 0) return true; // Unknown modifier. @@ -182,20 +190,20 @@ bool SparcAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, } } - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); return false; } bool SparcAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, - unsigned OpNo, - unsigned AsmVariant, - const char *ExtraCode) { + unsigned OpNo, unsigned AsmVariant, + const char *ExtraCode, + raw_ostream &O) { if (ExtraCode && ExtraCode[0]) return true; // Unknown modifier O << '['; - printMemOperand(MI, OpNo); + printMemOperand(MI, OpNo, O); O << ']'; return false; diff --git a/lib/Target/Sparc/Sparc.td b/lib/Target/Sparc/Sparc.td index 53ea8f4a35f0..925d782d988b 100644 --- a/lib/Target/Sparc/Sparc.td +++ b/lib/Target/Sparc/Sparc.td @@ -38,11 +38,7 @@ include "SparcRegisterInfo.td" include "SparcCallingConv.td" include "SparcInstrInfo.td" -def SparcInstrInfo : InstrInfo { - // Define how we want to layout our target-specific information field. - let TSFlagsFields = []; - let TSFlagsShifts = []; -} +def SparcInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// // SPARC processors supported. diff --git a/lib/Target/Sparc/SparcMCAsmInfo.cpp b/lib/Target/Sparc/SparcMCAsmInfo.cpp index 53a9bde92526..535c6f7c8a27 100644 --- a/lib/Target/Sparc/SparcMCAsmInfo.cpp +++ b/lib/Target/Sparc/SparcMCAsmInfo.cpp @@ -22,7 +22,6 @@ SparcELFMCAsmInfo::SparcELFMCAsmInfo(const Target &T, const StringRef &TT) { ZeroDirective = "\t.skip\t"; CommentString = "!"; HasLEB128 = true; - AbsoluteDebugSectionOffsets = true; SupportsDebugInformation = true; SunStyleELFSectionSwitchSyntax = true; diff --git a/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp b/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp index b29dfcdc9846..07cfb2c83e33 100644 --- a/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp +++ b/lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp @@ -21,11 +21,9 @@ #include "llvm/Module.h" #include "llvm/Assembly/Writer.h" #include "llvm/CodeGen/AsmPrinter.h" -#include "llvm/CodeGen/DwarfWriter.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineConstantPool.h" -#include "llvm/CodeGen/MachineInstr.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCSymbol.h" @@ -33,56 +31,52 @@ #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetRegistry.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/FormattedStream.h" +#include "llvm/ADT/SmallString.h" +#include "llvm/Support/raw_ostream.h" using namespace llvm; namespace { class SystemZAsmPrinter : public AsmPrinter { public: - SystemZAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM, - MCStreamer &Streamer) - : AsmPrinter(O, TM, Streamer) {} + SystemZAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) + : AsmPrinter(TM, Streamer) {} virtual const char *getPassName() const { return "SystemZ Assembly Printer"; } - void printOperand(const MachineInstr *MI, int OpNum, + void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O, const char* Modifier = 0); - void printPCRelImmOperand(const MachineInstr *MI, int OpNum); - void printRIAddrOperand(const MachineInstr *MI, int OpNum, + void printPCRelImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O); + void printRIAddrOperand(const MachineInstr *MI, int OpNum, raw_ostream &O, const char* Modifier = 0); - void printRRIAddrOperand(const MachineInstr *MI, int OpNum, + void printRRIAddrOperand(const MachineInstr *MI, int OpNum, raw_ostream &O, const char* Modifier = 0); - void printS16ImmOperand(const MachineInstr *MI, int OpNum) { + void printS16ImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O) { O << (int16_t)MI->getOperand(OpNum).getImm(); } - void printS32ImmOperand(const MachineInstr *MI, int OpNum) { + void printS32ImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O) { O << (int32_t)MI->getOperand(OpNum).getImm(); } - void printInstruction(const MachineInstr *MI); // autogenerated. + void printInstruction(const MachineInstr *MI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); void EmitInstruction(const MachineInstr *MI); - - void getAnalysisUsage(AnalysisUsage &AU) const { - AsmPrinter::getAnalysisUsage(AU); - AU.setPreservesAll(); - } }; } // end of anonymous namespace #include "SystemZGenAsmWriter.inc" void SystemZAsmPrinter::EmitInstruction(const MachineInstr *MI) { - // Call the autogenerated instruction printer routines. - printInstruction(MI); - OutStreamer.AddBlankLine(); + SmallString<128> Str; + raw_svector_ostream OS(Str); + printInstruction(MI, OS); + OutStreamer.EmitRawText(OS.str()); } -void SystemZAsmPrinter::printPCRelImmOperand(const MachineInstr *MI, int OpNum){ +void SystemZAsmPrinter::printPCRelImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNum); switch (MO.getType()) { case MachineOperand::MO_Immediate: @@ -101,7 +95,7 @@ void SystemZAsmPrinter::printPCRelImmOperand(const MachineInstr *MI, int OpNum){ !GV->hasLocalLinkage()) O << "@PLT"; - printOffset(MO.getOffset()); + printOffset(MO.getOffset(), O); return; } case MachineOperand::MO_ExternalSymbol: { @@ -121,7 +115,7 @@ void SystemZAsmPrinter::printPCRelImmOperand(const MachineInstr *MI, int OpNum){ void SystemZAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, - const char* Modifier) { + raw_ostream &O, const char *Modifier) { const MachineOperand &MO = MI->getOperand(OpNum); switch (MO.getType()) { case MachineOperand::MO_Register: { @@ -130,9 +124,9 @@ void SystemZAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, unsigned Reg = MO.getReg(); if (Modifier && strncmp(Modifier, "subreg", 6) == 0) { if (strncmp(Modifier + 7, "even", 4) == 0) - Reg = TRI->getSubReg(Reg, SystemZ::SUBREG_EVEN); + Reg = TM.getRegisterInfo()->getSubReg(Reg, SystemZ::SUBREG_EVEN); else if (strncmp(Modifier + 7, "odd", 3) == 0) - Reg = TRI->getSubReg(Reg, SystemZ::SUBREG_ODD); + Reg = TM.getRegisterInfo()->getSubReg(Reg, SystemZ::SUBREG_ODD); else assert(0 && "Invalid subreg modifier"); } @@ -155,7 +149,7 @@ void SystemZAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << '_' << MO.getIndex(); - printOffset(MO.getOffset()); + printOffset(MO.getOffset(), O); break; case MachineOperand::MO_GlobalAddress: O << *Mang->getSymbol(MO.getGlobal()); @@ -169,47 +163,48 @@ void SystemZAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, } switch (MO.getTargetFlags()) { - default: - llvm_unreachable("Unknown target flag on GV operand"); + default: assert(0 && "Unknown target flag on GV operand"); case SystemZII::MO_NO_FLAG: break; case SystemZII::MO_GOTENT: O << "@GOTENT"; break; case SystemZII::MO_PLT: O << "@PLT"; break; } - printOffset(MO.getOffset()); + printOffset(MO.getOffset(), O); } void SystemZAsmPrinter::printRIAddrOperand(const MachineInstr *MI, int OpNum, - const char* Modifier) { + raw_ostream &O, + const char *Modifier) { const MachineOperand &Base = MI->getOperand(OpNum); // Print displacement operand. - printOperand(MI, OpNum+1); + printOperand(MI, OpNum+1, O); // Print base operand (if any) if (Base.getReg()) { O << '('; - printOperand(MI, OpNum); + printOperand(MI, OpNum, O); O << ')'; } } void SystemZAsmPrinter::printRRIAddrOperand(const MachineInstr *MI, int OpNum, - const char* Modifier) { + raw_ostream &O, + const char *Modifier) { const MachineOperand &Base = MI->getOperand(OpNum); const MachineOperand &Index = MI->getOperand(OpNum+2); // Print displacement operand. - printOperand(MI, OpNum+1); + printOperand(MI, OpNum+1, O); // Print base operand (if any) if (Base.getReg()) { O << '('; - printOperand(MI, OpNum); + printOperand(MI, OpNum, O); if (Index.getReg()) { O << ','; - printOperand(MI, OpNum+2); + printOperand(MI, OpNum+2, O); } O << ')'; } else diff --git a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp index 734a545555f9..0b64cb4f2828 100644 --- a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp @@ -29,15 +29,18 @@ using namespace llvm; #include "X86GenAsmWriter.inc" #undef MachineInstr -void X86ATTInstPrinter::printInst(const MCInst *MI) { printInstruction(MI); } +void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) { + printInstruction(MI, OS); +} StringRef X86ATTInstPrinter::getOpcodeName(unsigned Opcode) const { return getInstructionName(Opcode); } -void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op) { +void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op, + raw_ostream &O) { switch (MI->getOperand(Op).getImm()) { - default: llvm_unreachable("Invalid ssecc argument!"); + default: assert(0 && "Invalid ssecc argument!"); case 0: O << "eq"; break; case 1: O << "lt"; break; case 2: O << "le"; break; @@ -53,7 +56,8 @@ void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op) { /// being encoded as a pc-relative value (e.g. for jumps and calls). These /// print slightly differently than normal immediates. For example, a $ is not /// emitted. -void X86ATTInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo) { +void X86ATTInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); if (Op.isImm()) // Print this as a signed 32-bit value. @@ -64,8 +68,8 @@ void X86ATTInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo) { } } -void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo) { - +void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); if (Op.isReg()) { O << '%' << getRegisterName(Op.getReg()); @@ -81,7 +85,8 @@ void X86ATTInstPrinter::printOperand(const MCInst *MI, unsigned OpNo) { } } -void X86ATTInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { +void X86ATTInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op, + raw_ostream &O) { const MCOperand &BaseReg = MI->getOperand(Op); const MCOperand &IndexReg = MI->getOperand(Op+2); const MCOperand &DispSpec = MI->getOperand(Op+3); @@ -98,11 +103,11 @@ void X86ATTInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { if (IndexReg.getReg() || BaseReg.getReg()) { O << '('; if (BaseReg.getReg()) - printOperand(MI, Op); + printOperand(MI, Op, O); if (IndexReg.getReg()) { O << ','; - printOperand(MI, Op+2); + printOperand(MI, Op+2, O); unsigned ScaleVal = MI->getOperand(Op+1).getImm(); if (ScaleVal != 1) O << ',' << ScaleVal; @@ -111,11 +116,12 @@ void X86ATTInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { } } -void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op) { +void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op, + raw_ostream &O) { // If this has a segment register, print it. if (MI->getOperand(Op+4).getReg()) { - printOperand(MI, Op+4); + printOperand(MI, Op+4, O); O << ':'; } - printLeaMemReference(MI, Op); + printLeaMemReference(MI, Op, O); } diff --git a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h index d109a075b85c..8d5d50832d49 100644 --- a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h +++ b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.h @@ -21,63 +21,62 @@ namespace llvm { class X86ATTInstPrinter : public MCInstPrinter { public: - X86ATTInstPrinter(raw_ostream &O, const MCAsmInfo &MAI) - : MCInstPrinter(O, MAI) {} + X86ATTInstPrinter(const MCAsmInfo &MAI) : MCInstPrinter(MAI) {} - virtual void printInst(const MCInst *MI); + virtual void printInst(const MCInst *MI, raw_ostream &OS); virtual StringRef getOpcodeName(unsigned Opcode) const; // Autogenerated by tblgen. - void printInstruction(const MCInst *MI); + void printInstruction(const MCInst *MI, raw_ostream &OS); static const char *getRegisterName(unsigned RegNo); static const char *getInstructionName(unsigned Opcode); - void printOperand(const MCInst *MI, unsigned OpNo); - void printMemReference(const MCInst *MI, unsigned Op); - void printLeaMemReference(const MCInst *MI, unsigned Op); - void printSSECC(const MCInst *MI, unsigned Op); - void print_pcrel_imm(const MCInst *MI, unsigned OpNo); + void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS); + void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS); + void printLeaMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS); + void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &OS); + void print_pcrel_imm(const MCInst *MI, unsigned OpNo, raw_ostream &OS); - void printopaquemem(const MCInst *MI, unsigned OpNo) { - printMemReference(MI, OpNo); + void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); } - void printi8mem(const MCInst *MI, unsigned OpNo) { - printMemReference(MI, OpNo); + void printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); } - void printi16mem(const MCInst *MI, unsigned OpNo) { - printMemReference(MI, OpNo); + void printi16mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); } - void printi32mem(const MCInst *MI, unsigned OpNo) { - printMemReference(MI, OpNo); + void printi32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); } - void printi64mem(const MCInst *MI, unsigned OpNo) { - printMemReference(MI, OpNo); + void printi64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); } - void printi128mem(const MCInst *MI, unsigned OpNo) { - printMemReference(MI, OpNo); + void printi128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); } - void printf32mem(const MCInst *MI, unsigned OpNo) { - printMemReference(MI, OpNo); + void printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); } - void printf64mem(const MCInst *MI, unsigned OpNo) { - printMemReference(MI, OpNo); + void printf64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); } - void printf80mem(const MCInst *MI, unsigned OpNo) { - printMemReference(MI, OpNo); + void printf80mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); } - void printf128mem(const MCInst *MI, unsigned OpNo) { - printMemReference(MI, OpNo); + void printf128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printMemReference(MI, OpNo, O); } - void printlea32mem(const MCInst *MI, unsigned OpNo) { - printLeaMemReference(MI, OpNo); + void printlea32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printLeaMemReference(MI, OpNo, O); } - void printlea64mem(const MCInst *MI, unsigned OpNo) { - printLeaMemReference(MI, OpNo); + void printlea64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printLeaMemReference(MI, OpNo, O); } - void printlea64_32mem(const MCInst *MI, unsigned OpNo) { - printLeaMemReference(MI, OpNo); + void printlea64_32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { + printLeaMemReference(MI, OpNo, O); } }; diff --git a/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp index 66bb914edde5..f5923969361d 100644 --- a/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp @@ -36,7 +36,6 @@ #include "llvm/CodeGen/MachineModuleInfoImpls.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/FormattedStream.h" #include "llvm/Target/Mangler.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetRegistry.h" @@ -47,7 +46,7 @@ using namespace llvm; // Primitive Helper Functions. //===----------------------------------------------------------------------===// -void X86AsmPrinter::PrintPICBaseSymbol() const { +void X86AsmPrinter::PrintPICBaseSymbol(raw_ostream &O) const { const TargetLowering *TLI = TM.getTargetLowering(); O << *static_cast<const X86TargetLowering*>(TLI)->getPICBaseSymbol(MF, OutContext); @@ -60,10 +59,11 @@ bool X86AsmPrinter::runOnMachineFunction(MachineFunction &MF) { if (Subtarget->isTargetCOFF()) { const Function *F = MF.getFunction(); - O << "\t.def\t " << *CurrentFnSym << ";\t.scl\t" << - (F->hasInternalLinkage() ? COFF::C_STAT : COFF::C_EXT) - << ";\t.type\t" << (COFF::DT_FCN << COFF::N_BTSHFT) - << ";\t.endef\n"; + OutStreamer.EmitRawText("\t.def\t " + Twine(CurrentFnSym->getName()) + + ";\t.scl\t" + + Twine(F->hasInternalLinkage() ? COFF::C_STAT : COFF::C_EXT) + + ";\t.type\t" + Twine(COFF::DT_FCN << COFF::N_BTSHFT) + + ";\t.endef"); } // Have common code print out the function header with linkage info etc. @@ -79,7 +79,8 @@ bool X86AsmPrinter::runOnMachineFunction(MachineFunction &MF) { /// printSymbolOperand - Print a raw symbol reference operand. This handles /// jump tables, constant pools, global address and external symbols, all of /// which print to a label with various suffixes for relocation types etc. -void X86AsmPrinter::printSymbolOperand(const MachineOperand &MO) { +void X86AsmPrinter::printSymbolOperand(const MachineOperand &MO, + raw_ostream &O) { switch (MO.getType()) { default: llvm_unreachable("unknown symbol type!"); case MachineOperand::MO_JumpTableIndex: @@ -87,7 +88,7 @@ void X86AsmPrinter::printSymbolOperand(const MachineOperand &MO) { break; case MachineOperand::MO_ConstantPoolIndex: O << *GetCPISymbol(MO.getIndex()); - printOffset(MO.getOffset()); + printOffset(MO.getOffset(), O); break; case MachineOperand::MO_GlobalAddress: { const GlobalValue *GV = MO.getGlobal(); @@ -136,7 +137,7 @@ void X86AsmPrinter::printSymbolOperand(const MachineOperand &MO) { O << *GVSym; else O << '(' << *GVSym << ')'; - printOffset(MO.getOffset()); + printOffset(MO.getOffset(), O); break; } case MachineOperand::MO_ExternalSymbol: { @@ -182,14 +183,14 @@ void X86AsmPrinter::printSymbolOperand(const MachineOperand &MO) { break; case X86II::MO_GOT_ABSOLUTE_ADDRESS: O << " + [.-"; - PrintPICBaseSymbol(); + PrintPICBaseSymbol(O); O << ']'; break; case X86II::MO_PIC_BASE_OFFSET: case X86II::MO_DARWIN_NONLAZY_PIC_BASE: case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: O << '-'; - PrintPICBaseSymbol(); + PrintPICBaseSymbol(O); break; case X86II::MO_TLSGD: O << "@TLSGD"; break; case X86II::MO_GOTTPOFF: O << "@GOTTPOFF"; break; @@ -206,7 +207,8 @@ void X86AsmPrinter::printSymbolOperand(const MachineOperand &MO) { /// print_pcrel_imm - This is used to print an immediate value that ends up /// being encoded as a pc-relative value. These print slightly differently, for /// example, a $ is not emitted. -void X86AsmPrinter::print_pcrel_imm(const MachineInstr *MI, unsigned OpNo) { +void X86AsmPrinter::print_pcrel_imm(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNo); switch (MO.getType()) { default: llvm_unreachable("Unknown pcrel immediate operand"); @@ -218,14 +220,14 @@ void X86AsmPrinter::print_pcrel_imm(const MachineInstr *MI, unsigned OpNo) { return; case MachineOperand::MO_GlobalAddress: case MachineOperand::MO_ExternalSymbol: - printSymbolOperand(MO); + printSymbolOperand(MO, O); return; } } void X86AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo, - const char *Modifier) { + raw_ostream &O, const char *Modifier) { const MachineOperand &MO = MI->getOperand(OpNo); switch (MO.getType()) { default: llvm_unreachable("unknown operand type!"); @@ -251,13 +253,14 @@ void X86AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo, case MachineOperand::MO_GlobalAddress: case MachineOperand::MO_ExternalSymbol: { O << '$'; - printSymbolOperand(MO); + printSymbolOperand(MO, O); break; } } } -void X86AsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) { +void X86AsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op, + raw_ostream &O) { unsigned char value = MI->getOperand(Op).getImm(); assert(value <= 7 && "Invalid ssecc argument!"); switch (value) { @@ -273,7 +276,7 @@ void X86AsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) { } void X86AsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op, - const char *Modifier) { + raw_ostream &O, const char *Modifier) { const MachineOperand &BaseReg = MI->getOperand(Op); const MachineOperand &IndexReg = MI->getOperand(Op+2); const MachineOperand &DispSpec = MI->getOperand(Op+3); @@ -294,7 +297,7 @@ void X86AsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op, } else { assert(DispSpec.isGlobal() || DispSpec.isCPI() || DispSpec.isJTI() || DispSpec.isSymbol()); - printSymbolOperand(MI->getOperand(Op+3)); + printSymbolOperand(MI->getOperand(Op+3), O); } if (HasParenPart) { @@ -303,11 +306,11 @@ void X86AsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op, O << '('; if (HasBaseReg) - printOperand(MI, Op, Modifier); + printOperand(MI, Op, O, Modifier); if (IndexReg.getReg()) { O << ','; - printOperand(MI, Op+2, Modifier); + printOperand(MI, Op+2, O, Modifier); unsigned ScaleVal = MI->getOperand(Op+1).getImm(); if (ScaleVal != 1) O << ',' << ScaleVal; @@ -317,24 +320,26 @@ void X86AsmPrinter::printLeaMemReference(const MachineInstr *MI, unsigned Op, } void X86AsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op, - const char *Modifier) { + raw_ostream &O, const char *Modifier) { assert(isMem(MI, Op) && "Invalid memory reference!"); const MachineOperand &Segment = MI->getOperand(Op+4); if (Segment.getReg()) { - printOperand(MI, Op+4, Modifier); + printOperand(MI, Op+4, O, Modifier); O << ':'; } - printLeaMemReference(MI, Op, Modifier); + printLeaMemReference(MI, Op, O, Modifier); } -void X86AsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op) { - PrintPICBaseSymbol(); +void X86AsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op, + raw_ostream &O) { + PrintPICBaseSymbol(O); O << '\n'; - PrintPICBaseSymbol(); + PrintPICBaseSymbol(O); O << ':'; } -bool X86AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode) { +bool X86AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode, + raw_ostream &O) { unsigned Reg = MO.getReg(); switch (Mode) { default: return true; // Unknown mode. @@ -363,7 +368,7 @@ bool X86AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode) { /// bool X86AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, - const char *ExtraCode) { + const char *ExtraCode, raw_ostream &O) { // Does this asm operand have a single letter operand modifier? if (ExtraCode && ExtraCode[0]) { if (ExtraCode[1] != 0) return true; // Unknown modifier. @@ -378,12 +383,12 @@ bool X86AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, return false; } if (MO.isGlobal() || MO.isCPI() || MO.isJTI() || MO.isSymbol()) { - printSymbolOperand(MO); + printSymbolOperand(MO, O); return false; } if (MO.isReg()) { O << '('; - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); O << ')'; return false; } @@ -393,15 +398,15 @@ bool X86AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, if (MO.isImm()) O << MO.getImm(); else if (MO.isGlobal() || MO.isCPI() || MO.isJTI() || MO.isSymbol()) - printSymbolOperand(MO); + printSymbolOperand(MO, O); else - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); return false; case 'A': // Print '*' before a register (it must be a register) if (MO.isReg()) { O << '*'; - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); return false; } return true; @@ -412,12 +417,12 @@ bool X86AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, case 'k': // Print SImode register case 'q': // Print DImode register if (MO.isReg()) - return printAsmMRegister(MO, ExtraCode[0]); - printOperand(MI, OpNo); + return printAsmMRegister(MO, ExtraCode[0], O); + printOperand(MI, OpNo, O); return false; case 'P': // This is the operand of a call, treat specially. - print_pcrel_imm(MI, OpNo); + print_pcrel_imm(MI, OpNo, O); return false; case 'n': // Negate the immediate or print a '-' before the operand. @@ -431,13 +436,14 @@ bool X86AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, } } - printOperand(MI, OpNo); + printOperand(MI, OpNo, O); return false; } bool X86AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, - const char *ExtraCode) { + const char *ExtraCode, + raw_ostream &O) { if (ExtraCode && ExtraCode[0]) { if (ExtraCode[1] != 0) return true; // Unknown modifier. @@ -451,11 +457,11 @@ bool X86AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, // These only apply to registers, ignore on mem. break; case 'P': // Don't print @PLT, but do print as memory. - printMemReference(MI, OpNo, "no-rip"); + printMemReference(MI, OpNo, O, "no-rip"); return false; } } - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); return false; } @@ -570,10 +576,11 @@ void X86AsmPrinter::EmitEndOfAsmFile(Module &M) { // Emit type information for external functions for (X86COFFMachineModuleInfo::stub_iterator I = COFFMMI.stub_begin(), E = COFFMMI.stub_end(); I != E; ++I) { - O << "\t.def\t " << I->getKeyData() - << ";\t.scl\t" << COFF::C_EXT - << ";\t.type\t" << (COFF::DT_FCN << COFF::N_BTSHFT) - << ";\t.endef\n"; + OutStreamer.EmitRawText("\t.def\t " + Twine(I->getKeyData()) + + ";\t.scl\t" + Twine(COFF::C_EXT) + + ";\t.type\t" + + Twine(COFF::DT_FCN << COFF::N_BTSHFT) + + ";\t.endef"); } if (Subtarget->isTargetCygMing()) { @@ -598,10 +605,13 @@ void X86AsmPrinter::EmitEndOfAsmFile(Module &M) { true, SectionKind::getMetadata())); for (unsigned i = 0, e = DLLExportedGlobals.size(); i != e; ++i) - O << "\t.ascii \" -export:" << *DLLExportedGlobals[i] << ",data\"\n"; + OutStreamer.EmitRawText("\t.ascii \" -export:" + + Twine(DLLExportedGlobals[i]->getName()) + + ",data\""); for (unsigned i = 0, e = DLLExportedFns.size(); i != e; ++i) - O << "\t.ascii \" -export:" << *DLLExportedFns[i] << "\"\n"; + OutStreamer.EmitRawText("\t.ascii \" -export:" + + Twine(DLLExportedFns[i]->getName()) + "\""); } } } @@ -618,12 +628,11 @@ void X86AsmPrinter::EmitEndOfAsmFile(Module &M) { OutStreamer.SwitchSection(TLOFELF.getDataRelSection()); const TargetData *TD = TM.getTargetData(); - for (unsigned i = 0, e = Stubs.size(); i != e; ++i) - O << *Stubs[i].first << ":\n" - << (TD->getPointerSize() == 8 ? - MAI->getData64bitsDirective() : MAI->getData32bitsDirective()) - << *Stubs[i].second.getPointer() << '\n'; - + for (unsigned i = 0, e = Stubs.size(); i != e; ++i) { + OutStreamer.EmitLabel(Stubs[i].first); + OutStreamer.EmitSymbolValue(Stubs[i].second.getPointer(), + TD->getPointerSize(), 0); + } Stubs.clear(); } } @@ -636,12 +645,11 @@ void X86AsmPrinter::EmitEndOfAsmFile(Module &M) { static MCInstPrinter *createX86MCInstPrinter(const Target &T, unsigned SyntaxVariant, - const MCAsmInfo &MAI, - raw_ostream &O) { + const MCAsmInfo &MAI) { if (SyntaxVariant == 0) - return new X86ATTInstPrinter(O, MAI); + return new X86ATTInstPrinter(MAI); if (SyntaxVariant == 1) - return new X86IntelInstPrinter(O, MAI); + return new X86IntelInstPrinter(MAI); return 0; } diff --git a/lib/Target/X86/AsmPrinter/X86AsmPrinter.h b/lib/Target/X86/AsmPrinter/X86AsmPrinter.h index 28c25f9b8abe..ee59289dc572 100644 --- a/lib/Target/X86/AsmPrinter/X86AsmPrinter.h +++ b/lib/Target/X86/AsmPrinter/X86AsmPrinter.h @@ -19,7 +19,6 @@ #include "../X86TargetMachine.h" #include "llvm/ADT/StringSet.h" #include "llvm/CodeGen/AsmPrinter.h" -#include "llvm/CodeGen/DwarfWriter.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/ValueTypes.h" #include "llvm/Support/Compiler.h" @@ -35,9 +34,8 @@ class MCSymbol; class VISIBILITY_HIDDEN X86AsmPrinter : public AsmPrinter { const X86Subtarget *Subtarget; public: - explicit X86AsmPrinter(formatted_raw_ostream &O, TargetMachine &TM, - MCStreamer &Streamer) - : AsmPrinter(O, TM, Streamer) { + explicit X86AsmPrinter(TargetMachine &TM, MCStreamer &Streamer) + : AsmPrinter(TM, Streamer) { Subtarget = &TM.getSubtarget<X86Subtarget>(); } @@ -47,85 +45,41 @@ class VISIBILITY_HIDDEN X86AsmPrinter : public AsmPrinter { const X86Subtarget &getSubtarget() const { return *Subtarget; } - void getAnalysisUsage(AnalysisUsage &AU) const { - AU.setPreservesAll(); - AU.addRequired<MachineModuleInfo>(); - AU.addRequired<DwarfWriter>(); - AsmPrinter::getAnalysisUsage(AU); - } - virtual void EmitStartOfAsmFile(Module &M); virtual void EmitEndOfAsmFile(Module &M); virtual void EmitInstruction(const MachineInstr *MI); - void printSymbolOperand(const MachineOperand &MO); + void printSymbolOperand(const MachineOperand &MO, raw_ostream &O); // These methods are used by the tablegen'erated instruction printer. - void printOperand(const MachineInstr *MI, unsigned OpNo, + void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O, const char *Modifier = 0); - void print_pcrel_imm(const MachineInstr *MI, unsigned OpNo); - - void printopaquemem(const MachineInstr *MI, unsigned OpNo) { - printMemReference(MI, OpNo); - } - - void printi8mem(const MachineInstr *MI, unsigned OpNo) { - printMemReference(MI, OpNo); - } - void printi16mem(const MachineInstr *MI, unsigned OpNo) { - printMemReference(MI, OpNo); - } - void printi32mem(const MachineInstr *MI, unsigned OpNo) { - printMemReference(MI, OpNo); - } - void printi64mem(const MachineInstr *MI, unsigned OpNo) { - printMemReference(MI, OpNo); - } - void printi128mem(const MachineInstr *MI, unsigned OpNo) { - printMemReference(MI, OpNo); - } - void printf32mem(const MachineInstr *MI, unsigned OpNo) { - printMemReference(MI, OpNo); - } - void printf64mem(const MachineInstr *MI, unsigned OpNo) { - printMemReference(MI, OpNo); - } - void printf80mem(const MachineInstr *MI, unsigned OpNo) { - printMemReference(MI, OpNo); - } - void printf128mem(const MachineInstr *MI, unsigned OpNo) { - printMemReference(MI, OpNo); - } - void printlea32mem(const MachineInstr *MI, unsigned OpNo) { - printLeaMemReference(MI, OpNo); - } - void printlea64mem(const MachineInstr *MI, unsigned OpNo) { - printLeaMemReference(MI, OpNo); - } - void printlea64_32mem(const MachineInstr *MI, unsigned OpNo) { - printLeaMemReference(MI, OpNo, "subreg64"); - } + void print_pcrel_imm(const MachineInstr *MI, unsigned OpNo, raw_ostream &O); - bool printAsmMRegister(const MachineOperand &MO, char Mode); + bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O); bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode); + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &OS); bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode); + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &OS); void printMachineInstruction(const MachineInstr *MI); - void printSSECC(const MachineInstr *MI, unsigned Op); - void printMemReference(const MachineInstr *MI, unsigned Op, + void printSSECC(const MachineInstr *MI, unsigned Op, raw_ostream &O); + void printMemReference(const MachineInstr *MI, unsigned Op, raw_ostream &O, const char *Modifier=NULL); - void printLeaMemReference(const MachineInstr *MI, unsigned Op, + void printLeaMemReference(const MachineInstr *MI, unsigned Op, raw_ostream &O, const char *Modifier=NULL); - void printPICLabel(const MachineInstr *MI, unsigned Op); + void printPICLabel(const MachineInstr *MI, unsigned Op, raw_ostream &O); - void PrintPICBaseSymbol() const; + void PrintPICBaseSymbol(raw_ostream &O) const; bool runOnMachineFunction(MachineFunction &F); + + void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS); }; } // end namespace llvm diff --git a/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp b/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp index 610beb550b24..7e0a9bb891fa 100644 --- a/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.cpp @@ -28,14 +28,17 @@ using namespace llvm; #include "X86GenAsmWriter1.inc" #undef MachineInstr -void X86IntelInstPrinter::printInst(const MCInst *MI) { printInstruction(MI); } +void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) { + printInstruction(MI, OS); +} StringRef X86IntelInstPrinter::getOpcodeName(unsigned Opcode) const { return getInstructionName(Opcode); } -void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op) { +void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op, + raw_ostream &O) { switch (MI->getOperand(Op).getImm()) { - default: llvm_unreachable("Invalid ssecc argument!"); + default: assert(0 && "Invalid ssecc argument!"); case 0: O << "eq"; break; case 1: O << "lt"; break; case 2: O << "le"; break; @@ -49,7 +52,8 @@ void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op) { /// print_pcrel_imm - This is used to print an immediate value that ends up /// being encoded as a pc-relative value. -void X86IntelInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo) { +void X86IntelInstPrinter::print_pcrel_imm(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); if (Op.isImm()) O << Op.getImm(); @@ -65,9 +69,7 @@ static void PrintRegName(raw_ostream &O, StringRef RegName) { } void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - const char *Modifier) { - assert(Modifier == 0 && "Modifiers should not be used"); - + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); if (Op.isReg()) { PrintRegName(O, getRegisterName(Op.getReg())); @@ -79,7 +81,8 @@ void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, } } -void X86IntelInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { +void X86IntelInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op, + raw_ostream &O) { const MCOperand &BaseReg = MI->getOperand(Op); unsigned ScaleVal = MI->getOperand(Op+1).getImm(); const MCOperand &IndexReg = MI->getOperand(Op+2); @@ -89,7 +92,7 @@ void X86IntelInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { bool NeedPlus = false; if (BaseReg.getReg()) { - printOperand(MI, Op); + printOperand(MI, Op, O); NeedPlus = true; } @@ -97,7 +100,7 @@ void X86IntelInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { if (NeedPlus) O << " + "; if (ScaleVal != 1) O << ScaleVal << '*'; - printOperand(MI, Op+2); + printOperand(MI, Op+2, O); NeedPlus = true; } @@ -124,11 +127,12 @@ void X86IntelInstPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { O << ']'; } -void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op) { +void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op, + raw_ostream &O) { // If this has a segment register, print it. if (MI->getOperand(Op+4).getReg()) { - printOperand(MI, Op+4); + printOperand(MI, Op+4, O); O << ':'; } - printLeaMemReference(MI, Op); + printLeaMemReference(MI, Op, O); } diff --git a/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h b/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h index 545bf84b916f..a0beeb202e72 100644 --- a/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h +++ b/lib/Target/X86/AsmPrinter/X86IntelInstPrinter.h @@ -22,77 +22,76 @@ namespace llvm { class X86IntelInstPrinter : public MCInstPrinter { public: - X86IntelInstPrinter(raw_ostream &O, const MCAsmInfo &MAI) - : MCInstPrinter(O, MAI) {} + X86IntelInstPrinter(const MCAsmInfo &MAI) + : MCInstPrinter(MAI) {} - virtual void printInst(const MCInst *MI); + virtual void printInst(const MCInst *MI, raw_ostream &OS); virtual StringRef getOpcodeName(unsigned Opcode) const; // Autogenerated by tblgen. - void printInstruction(const MCInst *MI); + void printInstruction(const MCInst *MI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); static const char *getInstructionName(unsigned Opcode); - void printOperand(const MCInst *MI, unsigned OpNo, - const char *Modifier = 0); - void printMemReference(const MCInst *MI, unsigned Op); - void printLeaMemReference(const MCInst *MI, unsigned Op); - void printSSECC(const MCInst *MI, unsigned Op); - void print_pcrel_imm(const MCInst *MI, unsigned OpNo); + void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O); + void printLeaMemReference(const MCInst *MI, unsigned Op, raw_ostream &O); + void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &O); + void print_pcrel_imm(const MCInst *MI, unsigned OpNo, raw_ostream &O); - void printopaquemem(const MCInst *MI, unsigned OpNo) { + void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "OPAQUE PTR "; - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); } - void printi8mem(const MCInst *MI, unsigned OpNo) { + void printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "BYTE PTR "; - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); } - void printi16mem(const MCInst *MI, unsigned OpNo) { + void printi16mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "WORD PTR "; - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); } - void printi32mem(const MCInst *MI, unsigned OpNo) { + void printi32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "DWORD PTR "; - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); } - void printi64mem(const MCInst *MI, unsigned OpNo) { + void printi64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "QWORD PTR "; - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); } - void printi128mem(const MCInst *MI, unsigned OpNo) { + void printi128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "XMMWORD PTR "; - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); } - void printf32mem(const MCInst *MI, unsigned OpNo) { + void printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "DWORD PTR "; - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); } - void printf64mem(const MCInst *MI, unsigned OpNo) { + void printf64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "QWORD PTR "; - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); } - void printf80mem(const MCInst *MI, unsigned OpNo) { + void printf80mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "XWORD PTR "; - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); } - void printf128mem(const MCInst *MI, unsigned OpNo) { + void printf128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "XMMWORD PTR "; - printMemReference(MI, OpNo); + printMemReference(MI, OpNo, O); } - void printlea32mem(const MCInst *MI, unsigned OpNo) { + void printlea32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "DWORD PTR "; - printLeaMemReference(MI, OpNo); + printLeaMemReference(MI, OpNo, O); } - void printlea64mem(const MCInst *MI, unsigned OpNo) { + void printlea64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "QWORD PTR "; - printLeaMemReference(MI, OpNo); + printLeaMemReference(MI, OpNo, O); } - void printlea64_32mem(const MCInst *MI, unsigned OpNo) { + void printlea64_32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { O << "QWORD PTR "; - printLeaMemReference(MI, OpNo); + printLeaMemReference(MI, OpNo, O); } }; diff --git a/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp b/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp index c851ca3fc805..a290eb0f2a5f 100644 --- a/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp +++ b/lib/Target/X86/AsmPrinter/X86MCInstLower.cpp @@ -326,70 +326,76 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { } } +void X86AsmPrinter::PrintDebugValueComment(const MachineInstr *MI, + raw_ostream &O) { + // FIXME: if this is implemented for another target before it goes + // away completely, the common part should be moved into AsmPrinter. + O << '\t' << MAI->getCommentString() << "DEBUG_VALUE: "; + unsigned NOps = MI->getNumOperands(); + // cast away const; DIetc do not take const operands for some reason. + DIVariable V((MDNode*)(MI->getOperand(NOps-1).getMetadata())); + O << V.getName(); + O << " <- "; + if (NOps==3) { + // Register or immediate value. Register 0 means undef. + assert(MI->getOperand(0).isReg() || + MI->getOperand(0).isImm() || + MI->getOperand(0).isFPImm()); + if (MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == 0) { + // Suppress offset in this case, it is not meaningful. + O << "undef"; + OutStreamer.AddBlankLine(); + return; + } + + if (MI->getOperand(0).isFPImm()) { + // This is more naturally done in printOperand, but since the only use + // of such an operand is in this comment and that is temporary (and it's + // ugly), we prefer to keep this localized. + // The include of Type.h may be removable when this code is. + if (MI->getOperand(0).getFPImm()->getType()->isFloatTy() || + MI->getOperand(0).getFPImm()->getType()->isDoubleTy()) + MI->getOperand(0).print(O, &TM); + else { + // There is no good way to print long double. Convert a copy to + // double. Ah well, it's only a comment. + bool ignored; + APFloat APF = APFloat(MI->getOperand(0).getFPImm()->getValueAPF()); + APF.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, + &ignored); + O << "(long double) " << APF.convertToDouble(); + } + } else + printOperand(MI, 0, O); + } else { + if (MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == 0) { + // Suppress offset in this case, it is not meaningful. + O << "undef"; + OutStreamer.AddBlankLine(); + return; + } + // Frame address. Currently handles register +- offset only. + assert(MI->getOperand(0).isReg() && MI->getOperand(3).isImm()); + O << '['; printOperand(MI, 0, O); O << '+'; printOperand(MI, 3, O); + O << ']'; + } + O << "+"; + printOperand(MI, NOps-2, O); +} void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { X86MCInstLower MCInstLowering(OutContext, Mang, *this); switch (MI->getOpcode()) { - case TargetOpcode::DBG_VALUE: { - // FIXME: if this is implemented for another target before it goes - // away completely, the common part should be moved into AsmPrinter. - if (!VerboseAsm) - return; - O << '\t' << MAI->getCommentString() << "DEBUG_VALUE: "; - unsigned NOps = MI->getNumOperands(); - // cast away const; DIetc do not take const operands for some reason. - DIVariable V((MDNode*)(MI->getOperand(NOps-1).getMetadata())); - O << V.getName(); - O << " <- "; - if (NOps==3) { - // Register or immediate value. Register 0 means undef. - assert(MI->getOperand(0).getType()==MachineOperand::MO_Register || - MI->getOperand(0).getType()==MachineOperand::MO_Immediate || - MI->getOperand(0).getType()==MachineOperand::MO_FPImmediate); - if (MI->getOperand(0).getType()==MachineOperand::MO_Register && - MI->getOperand(0).getReg()==0) { - // Suppress offset in this case, it is not meaningful. - O << "undef"; - OutStreamer.AddBlankLine(); - return; - } else if (MI->getOperand(0).getType()==MachineOperand::MO_FPImmediate) { - // This is more naturally done in printOperand, but since the only use - // of such an operand is in this comment and that is temporary (and it's - // ugly), we prefer to keep this localized. - // The include of Type.h may be removable when this code is. - if (MI->getOperand(0).getFPImm()->getType()->isFloatTy() || - MI->getOperand(0).getFPImm()->getType()->isDoubleTy()) - MI->getOperand(0).print(O, &TM); - else { - // There is no good way to print long double. Convert a copy to - // double. Ah well, it's only a comment. - bool ignored; - APFloat APF = APFloat(MI->getOperand(0).getFPImm()->getValueAPF()); - APF.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, - &ignored); - O << "(long double) " << APF.convertToDouble(); - } - } else - printOperand(MI, 0); - } else { - if (MI->getOperand(0).getType()==MachineOperand::MO_Register && - MI->getOperand(0).getReg()==0) { - // Suppress offset in this case, it is not meaningful. - O << "undef"; - OutStreamer.AddBlankLine(); - return; - } - // Frame address. Currently handles register +- offset only. - assert(MI->getOperand(0).getType()==MachineOperand::MO_Register); - assert(MI->getOperand(3).getType()==MachineOperand::MO_Immediate); - O << '['; printOperand(MI, 0); O << '+'; printOperand(MI, 3); O << ']'; + case TargetOpcode::DBG_VALUE: + if (isVerbose() && OutStreamer.hasRawTextSupport()) { + std::string TmpStr; + raw_string_ostream OS(TmpStr); + PrintDebugValueComment(MI, OS); + OutStreamer.EmitRawText(StringRef(OS.str())); } - O << "+"; - printOperand(MI, NOps-2); - OutStreamer.AddBlankLine(); return; - } + case X86::MOVPC32r: { MCInst TmpInst; // This is a pseudo op for a two instruction sequence with a label, which diff --git a/lib/Target/X86/SSEDomainFix.cpp b/lib/Target/X86/SSEDomainFix.cpp index 395ab5705ae2..4b546768b4f1 100644 --- a/lib/Target/X86/SSEDomainFix.cpp +++ b/lib/Target/X86/SSEDomainFix.cpp @@ -23,49 +23,11 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/ADT/DepthFirstIterator.h" +#include "llvm/Support/Allocator.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; -namespace { - -/// Allocate objects from a pool, allow objects to be recycled, and provide a -/// way of deleting everything. -template<typename T, unsigned PageSize = 64> -class PoolAllocator { - std::vector<T*> Pages, Avail; -public: - ~PoolAllocator() { Clear(); } - - T* Alloc() { - if (Avail.empty()) { - T *p = new T[PageSize]; - Pages.push_back(p); - Avail.reserve(PageSize); - for (unsigned n = 0; n != PageSize; ++n) - Avail.push_back(p+n); - } - T *p = Avail.back(); - Avail.pop_back(); - return p; - } - - // Allow object to be reallocated. It won't be reconstructed. - void Recycle(T *p) { - p->clear(); - Avail.push_back(p); - } - - // Destroy all objects, make sure there are no external pointers to them. - void Clear() { - Avail.clear(); - while (!Pages.empty()) { - delete[] Pages.back(); - Pages.pop_back(); - } - } -}; - /// A DomainValue is a bit like LiveIntervals' ValNo, but it also keeps track /// of execution domains. /// @@ -81,14 +43,15 @@ public: /// domain, but if we were forced to pay the penalty of a domain crossing, we /// keep track of the fact the the register is now available in multiple /// domains. +namespace { struct DomainValue { // Basic reference counting. unsigned Refs; - // Available domains. For an open DomainValue, it is the still possible - // domains for collapsing. For a collapsed DomainValue it is the domains where - // the register is available for free. - unsigned Mask; + // Bitmask of available domains. For an open DomainValue, it is the still + // possible domains for collapsing. For a collapsed DomainValue it is the + // domains where the register is available for free. + unsigned AvailableDomains; // Position of the last defining instruction. unsigned Dist; @@ -96,38 +59,51 @@ struct DomainValue { // Twiddleable instructions using or defining these registers. SmallVector<MachineInstr*, 8> Instrs; - // Collapsed DomainValue have no instructions to twiddle - it simply keeps + // A collapsed DomainValue has no instructions to twiddle - it simply keeps // track of the domains where the registers are already available. - bool collapsed() const { return Instrs.empty(); } + bool isCollapsed() const { return Instrs.empty(); } - // Is any domain in mask available? - bool compat(unsigned mask) const { - return Mask & mask; + // Is domain available? + bool hasDomain(unsigned domain) const { + return AvailableDomains & (1u << domain); } // Mark domain as available. - void add(unsigned domain) { - Mask |= 1u << domain; + void addDomain(unsigned domain) { + AvailableDomains |= 1u << domain; + } + + // Restrict to a single domain available. + void setSingleDomain(unsigned domain) { + AvailableDomains = 1u << domain; + } + + // Return bitmask of domains that are available and in mask. + unsigned getCommonDomains(unsigned mask) const { + return AvailableDomains & mask; } - // First domain available in mask. - unsigned firstDomain() const { - return CountTrailingZeros_32(Mask); + // First domain available. + unsigned getFirstDomain() const { + return CountTrailingZeros_32(AvailableDomains); } DomainValue() { clear(); } void clear() { - Refs = Mask = Dist = 0; + Refs = AvailableDomains = Dist = 0; Instrs.clear(); } }; +} static const unsigned NumRegs = 16; +namespace { class SSEDomainFixPass : public MachineFunctionPass { static char ID; - PoolAllocator<DomainValue> Pool; + SpecificBumpPtrAllocator<DomainValue> Allocator; + SmallVector<DomainValue*,16> Avail; MachineFunction *MF; const X86InstrInfo *TII; @@ -156,6 +132,10 @@ private: // Register mapping. int RegIndex(unsigned Reg); + // DomainValue allocation. + DomainValue *Alloc(int domain = -1); + void Recycle(DomainValue*); + // LiveRegs manipulations. void SetLiveReg(int rx, DomainValue *DV); void Kill(int rx); @@ -182,17 +162,35 @@ int SSEDomainFixPass::RegIndex(unsigned reg) { return reg < NumRegs ? reg : -1; } +DomainValue *SSEDomainFixPass::Alloc(int domain) { + DomainValue *dv = Avail.empty() ? + new(Allocator.Allocate()) DomainValue : + Avail.pop_back_val(); + dv->Dist = Distance; + if (domain >= 0) + dv->addDomain(domain); + return dv; +} + +void SSEDomainFixPass::Recycle(DomainValue *dv) { + assert(dv && "Cannot recycle NULL"); + dv->clear(); + Avail.push_back(dv); +} + /// Set LiveRegs[rx] = dv, updating reference counts. void SSEDomainFixPass::SetLiveReg(int rx, DomainValue *dv) { assert(unsigned(rx) < NumRegs && "Invalid index"); - if (!LiveRegs) - LiveRegs = (DomainValue**)calloc(sizeof(DomainValue*), NumRegs); + if (!LiveRegs) { + LiveRegs = new DomainValue*[NumRegs]; + std::fill(LiveRegs, LiveRegs+NumRegs, (DomainValue*)0); + } if (LiveRegs[rx] == dv) return; if (LiveRegs[rx]) { assert(LiveRegs[rx]->Refs && "Bad refcount"); - if (--LiveRegs[rx]->Refs == 0) Pool.Recycle(LiveRegs[rx]); + if (--LiveRegs[rx]->Refs == 0) Recycle(LiveRegs[rx]); } LiveRegs[rx] = dv; if (dv) ++dv->Refs; @@ -205,8 +203,8 @@ void SSEDomainFixPass::Kill(int rx) { // Before killing the last reference to an open DomainValue, collapse it to // the first available domain. - if (LiveRegs[rx]->Refs == 1 && !LiveRegs[rx]->collapsed()) - Collapse(LiveRegs[rx], LiveRegs[rx]->firstDomain()); + if (LiveRegs[rx]->Refs == 1 && !LiveRegs[rx]->isCollapsed()) + Collapse(LiveRegs[rx], LiveRegs[rx]->getFirstDomain()); else SetLiveReg(rx, 0); } @@ -216,54 +214,45 @@ void SSEDomainFixPass::Force(int rx, unsigned domain) { assert(unsigned(rx) < NumRegs && "Invalid index"); DomainValue *dv; if (LiveRegs && (dv = LiveRegs[rx])) { - if (dv->collapsed()) - dv->add(domain); + if (dv->isCollapsed()) + dv->addDomain(domain); else Collapse(dv, domain); } else { // Set up basic collapsed DomainValue. - dv = Pool.Alloc(); - dv->Dist = Distance; - dv->add(domain); - SetLiveReg(rx, dv); + SetLiveReg(rx, Alloc(domain)); } } /// Collapse open DomainValue into given domain. If there are multiple /// registers using dv, they each get a unique collapsed DomainValue. void SSEDomainFixPass::Collapse(DomainValue *dv, unsigned domain) { - assert(dv->compat(1u << domain) && "Cannot collapse"); + assert(dv->hasDomain(domain) && "Cannot collapse"); // Collapse all the instructions. - while (!dv->Instrs.empty()) { - MachineInstr *mi = dv->Instrs.back(); - TII->SetSSEDomain(mi, domain); - dv->Instrs.pop_back(); - } - dv->Mask = 1u << domain; + while (!dv->Instrs.empty()) + TII->SetSSEDomain(dv->Instrs.pop_back_val(), domain); + dv->setSingleDomain(domain); // If there are multiple users, give them new, unique DomainValues. - if (LiveRegs && dv->Refs > 1) { + if (LiveRegs && dv->Refs > 1) for (unsigned rx = 0; rx != NumRegs; ++rx) - if (LiveRegs[rx] == dv) { - DomainValue *dv2 = Pool.Alloc(); - dv2->Dist = Distance; - dv2->add(domain); - SetLiveReg(rx, dv2); - } - } + if (LiveRegs[rx] == dv) + SetLiveReg(rx, Alloc(domain)); } /// Merge - All instructions and registers in B are moved to A, and B is /// released. bool SSEDomainFixPass::Merge(DomainValue *A, DomainValue *B) { - assert(!A->collapsed() && "Cannot merge into collapsed"); - assert(!B->collapsed() && "Cannot merge from collapsed"); + assert(!A->isCollapsed() && "Cannot merge into collapsed"); + assert(!B->isCollapsed() && "Cannot merge from collapsed"); if (A == B) return true; - if (!A->compat(B->Mask)) + // Restrict to the domains that A and B have in common. + unsigned common = A->getCommonDomains(B->AvailableDomains); + if (!common) return false; - A->Mask &= B->Mask; + A->AvailableDomains = common; A->Dist = std::max(A->Dist, B->Dist); A->Instrs.append(B->Instrs.begin(), B->Instrs.end()); for (unsigned rx = 0; rx != NumRegs; ++rx) @@ -290,18 +279,18 @@ void SSEDomainFixPass::enterBasicBlock() { } // We have a live DomainValue from more than one predecessor. - if (LiveRegs[rx]->collapsed()) { + if (LiveRegs[rx]->isCollapsed()) { // We are already collapsed, but predecessor is not. Force him. - if (!pdv->collapsed()) - Collapse(pdv, LiveRegs[rx]->firstDomain()); + if (!pdv->isCollapsed()) + Collapse(pdv, LiveRegs[rx]->getFirstDomain()); continue; } - + // Currently open, merge in predecessor. - if (!pdv->collapsed()) + if (!pdv->isCollapsed()) Merge(LiveRegs[rx], pdv); else - Collapse(LiveRegs[rx], pdv->firstDomain()); + Collapse(LiveRegs[rx], pdv->getFirstDomain()); } } } @@ -332,8 +321,11 @@ void SSEDomainFixPass::visitHardInstr(MachineInstr *mi, unsigned domain) { // A soft instruction can be changed to work in other domains given by mask. void SSEDomainFixPass::visitSoftInstr(MachineInstr *mi, unsigned mask) { + // Bitmask of available domains for this instruction after taking collapsed + // operands into account. + unsigned available = mask; + // Scan the explicit use operands for incoming domains. - unsigned collmask = mask; SmallVector<int, 4> used; if (LiveRegs) for (unsigned i = mi->getDesc().getNumDefs(), @@ -343,33 +335,40 @@ void SSEDomainFixPass::visitSoftInstr(MachineInstr *mi, unsigned mask) { int rx = RegIndex(mo.getReg()); if (rx < 0) continue; if (DomainValue *dv = LiveRegs[rx]) { + // Bitmask of domains that dv and available have in common. + unsigned common = dv->getCommonDomains(available); // Is it possible to use this collapsed register for free? - if (dv->collapsed()) { - if (unsigned m = collmask & dv->Mask) - collmask = m; - } else if (dv->compat(collmask)) + if (dv->isCollapsed()) { + // Restrict available domains to the ones in common with the operand. + // If there are no common domains, we must pay the cross-domain + // penalty for this operand. + if (common) available = common; + } else if (common) + // Open DomainValue is compatible, save it for merging. used.push_back(rx); else + // Open DomainValue is not compatible with instruction. It is useless + // now. Kill(rx); } } // If the collapsed operands force a single domain, propagate the collapse. - if (isPowerOf2_32(collmask)) { - unsigned domain = CountTrailingZeros_32(collmask); + if (isPowerOf2_32(available)) { + unsigned domain = CountTrailingZeros_32(available); TII->SetSSEDomain(mi, domain); visitHardInstr(mi, domain); return; } - // Kill off any remaining uses that don't match collmask, and build a list of - // incoming DomainValue that we want to merge. + // Kill off any remaining uses that don't match available, and build a list of + // incoming DomainValues that we want to merge. SmallVector<DomainValue*,4> doms; for (SmallVector<int, 4>::iterator i=used.begin(), e=used.end(); i!=e; ++i) { int rx = *i; DomainValue *dv = LiveRegs[rx]; // This useless DomainValue could have been missed above. - if (!dv->compat(collmask)) { + if (!dv->getCommonDomains(available)) { Kill(*i); continue; } @@ -388,28 +387,29 @@ void SSEDomainFixPass::visitSoftInstr(MachineInstr *mi, unsigned mask) { doms.push_back(dv); } - // doms are now sorted in order of appearance. Try to merge them all, giving - // priority to the latest ones. + // doms are now sorted in order of appearance. Try to merge them all, giving + // priority to the latest ones. DomainValue *dv = 0; while (!doms.empty()) { if (!dv) { dv = doms.pop_back_val(); continue; } - - DomainValue *ThisDV = doms.pop_back_val(); - if (Merge(dv, ThisDV)) continue; - + + DomainValue *latest = doms.pop_back_val(); + if (Merge(dv, latest)) continue; + + // If latest didn't merge, it is useless now. Kill all registers using it. for (SmallVector<int,4>::iterator i=used.begin(), e=used.end(); i != e; ++i) - if (LiveRegs[*i] == ThisDV) + if (LiveRegs[*i] == latest) Kill(*i); } // dv is the DomainValue we are going to use for this instruction. if (!dv) - dv = Pool.Alloc(); + dv = Alloc(); dv->Dist = Distance; - dv->Mask = collmask; + dv->AvailableDomains = available; dv->Instrs.push_back(mi); // Finally set all defs and non-collapsed uses to dv. @@ -487,9 +487,10 @@ bool SSEDomainFixPass::runOnMachineFunction(MachineFunction &mf) { // DomainValues? for (LiveOutMap::const_iterator i = LiveOuts.begin(), e = LiveOuts.end(); i != e; ++i) - free(i->second); + delete[] i->second; LiveOuts.clear(); - Pool.Clear(); + Avail.clear(); + Allocator.DestroyAll(); return false; } diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td index 89cc84ffb3c6..ec86fc248e3d 100644 --- a/lib/Target/X86/X86.td +++ b/lib/Target/X86/X86.td @@ -164,33 +164,7 @@ include "X86RegisterInfo.td" include "X86InstrInfo.td" -def X86InstrInfo : InstrInfo { - - // Define how we want to layout our TargetSpecific information field... This - // should be kept up-to-date with the fields in the X86InstrInfo.h file. - let TSFlagsFields = ["FormBits", - "hasOpSizePrefix", - "hasAdSizePrefix", - "Prefix", - "hasREX_WPrefix", - "ImmT.Value", - "FPForm.Value", - "hasLockPrefix", - "SegOvrBits", - "ExeDomain.Value", - "Opcode"]; - let TSFlagsShifts = [0, - 6, - 7, - 8, - 12, - 13, - 16, - 19, - 20, - 22, - 24]; -} +def X86InstrInfo : InstrInfo; //===----------------------------------------------------------------------===// // Calling Conventions diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp index c69eeb3e9006..7849b51accc4 100644 --- a/lib/Target/X86/X86FastISel.cpp +++ b/lib/Target/X86/X86FastISel.cpp @@ -54,8 +54,6 @@ class X86FastISel : public FastISel { public: explicit X86FastISel(MachineFunction &mf, - MachineModuleInfo *mmi, - DwarfWriter *dw, DenseMap<const Value *, unsigned> &vm, DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, DenseMap<const AllocaInst *, int> &am @@ -63,7 +61,7 @@ public: , SmallSet<Instruction*, 8> &cil #endif ) - : FastISel(mf, mmi, dw, vm, bm, am + : FastISel(mf, vm, bm, am #ifndef NDEBUG , cil #endif @@ -1753,8 +1751,6 @@ unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) { namespace llvm { llvm::FastISel *X86::createFastISel(MachineFunction &mf, - MachineModuleInfo *mmi, - DwarfWriter *dw, DenseMap<const Value *, unsigned> &vm, DenseMap<const BasicBlock *, MachineBasicBlock *> &bm, DenseMap<const AllocaInst *, int> &am @@ -1762,7 +1758,7 @@ namespace llvm { , SmallSet<Instruction*, 8> &cil #endif ) { - return new X86FastISel(mf, mmi, dw, vm, bm, am + return new X86FastISel(mf, vm, bm, am #ifndef NDEBUG , cil #endif diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 527e19b60882..64702f1d5c9f 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1434,7 +1434,8 @@ CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, DebugLoc dl) { SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), - /*AlwaysInline=*/true, NULL, 0, NULL, 0); + /*isVolatile*/false, /*AlwaysInline=*/true, + NULL, 0, NULL, 0); } /// IsTailCallConvention - Return true if the calling convention is one that @@ -2397,8 +2398,7 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, } FastISel * -X86TargetLowering::createFastISel(MachineFunction &mf, MachineModuleInfo *mmo, - DwarfWriter *dw, +X86TargetLowering::createFastISel(MachineFunction &mf, DenseMap<const Value *, unsigned> &vm, DenseMap<const BasicBlock*, MachineBasicBlock*> &bm, DenseMap<const AllocaInst *, int> &am @@ -2406,7 +2406,7 @@ X86TargetLowering::createFastISel(MachineFunction &mf, MachineModuleInfo *mmo, , SmallSet<Instruction*, 8> &cil #endif ) { - return X86::createFastISel(mf, mmo, dw, vm, bm, am + return X86::createFastISel(mf, vm, bm, am #ifndef NDEBUG , cil #endif @@ -6548,6 +6548,7 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, + bool isVolatile, const Value *DstSV, uint64_t DstSVOff) { ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); @@ -6676,7 +6677,7 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, DAG.getConstant(Offset, AddrVT)), Src, DAG.getConstant(BytesLeft, SizeVT), - Align, DstSV, DstSVOff + Offset); + Align, isVolatile, DstSV, DstSVOff + Offset); } // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain. @@ -6687,7 +6688,7 @@ SDValue X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, - bool AlwaysInline, + bool isVolatile, bool AlwaysInline, const Value *DstSV, uint64_t DstSVOff, const Value *SrcSV, uint64_t SrcSVOff) { // This requires the copy size to be a constant, preferrably @@ -6746,7 +6747,7 @@ X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, DAG.getNode(ISD::ADD, dl, SrcVT, Src, DAG.getConstant(Offset, SrcVT)), DAG.getConstant(BytesLeft, SizeVT), - Align, AlwaysInline, + Align, isVolatile, AlwaysInline, DstSV, DstSVOff + Offset, SrcSV, SrcSVOff + Offset)); } @@ -6829,8 +6830,8 @@ SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr, - DAG.getIntPtrConstant(24), 8, false, - DstSV, 0, SrcSV, 0); + DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, + false, DstSV, 0, SrcSV, 0); } SDValue diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index 2c2a5fbb8032..1026480ef0a6 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -575,7 +575,6 @@ namespace llvm { /// or null if the target does not support "fast" ISel. virtual FastISel * createFastISel(MachineFunction &mf, - MachineModuleInfo *mmi, DwarfWriter *dw, DenseMap<const Value *, unsigned> &, DenseMap<const BasicBlock *, MachineBasicBlock *> &, DenseMap<const AllocaInst *, int> & @@ -741,12 +740,13 @@ namespace llvm { SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, + bool isVolatile, const Value *DstSV, uint64_t DstSVOff); SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, - bool AlwaysInline, + bool isVolatile, bool AlwaysInline, const Value *DstSV, uint64_t DstSVOff, const Value *SrcSV, uint64_t SrcSVOff); @@ -756,7 +756,7 @@ namespace llvm { /// block, the number of args, and whether or not the second arg is /// in memory or not. MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB, - unsigned argNum, bool inMem) const; + unsigned argNum, bool inMem) const; /// Utility function to emit atomic bitwise operations (and, or, xor). /// It takes the bitwise instruction to expand, the associated machine basic @@ -815,7 +815,6 @@ namespace llvm { namespace X86 { FastISel *createFastISel(MachineFunction &mf, - MachineModuleInfo *mmi, DwarfWriter *dw, DenseMap<const Value *, unsigned> &, DenseMap<const BasicBlock *, MachineBasicBlock *> &, DenseMap<const AllocaInst *, int> & diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td index cbe4c8256299..c4522f3fd9e8 100644 --- a/lib/Target/X86/X86InstrFormats.td +++ b/lib/Target/X86/X86InstrFormats.td @@ -128,6 +128,19 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins, bit hasLockPrefix = 0; // Does this inst have a 0xF0 prefix? bits<2> SegOvrBits = 0; // Segment override prefix. Domain ExeDomain = d; + + // TSFlags layout should be kept in sync with X86InstrInfo.h. + let TSFlags{5-0} = FormBits; + let TSFlags{6} = hasOpSizePrefix; + let TSFlags{7} = hasAdSizePrefix; + let TSFlags{11-8} = Prefix; + let TSFlags{12} = hasREX_WPrefix; + let TSFlags{15-13} = ImmT.Value; + let TSFlags{18-16} = FPForm.Value; + let TSFlags{19} = hasLockPrefix; + let TSFlags{21-20} = SegOvrBits; + let TSFlags{23-22} = ExeDomain.Value; + let TSFlags{31-24} = Opcode; } class I<bits<8> o, Format f, dag outs, dag ins, string asm, @@ -314,8 +327,7 @@ class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm, // AES Instruction Templates: // // AES8I -// FIXME: Verify these, they appear to use the same encoding as the SSE4.2 T8 -// and TA encodings. +// These use the same encoding as the SSE4.2 T8 and TA encodings. class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag>pattern> : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8, diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index fcb9947423de..ccb7b055b079 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -2961,10 +2961,6 @@ X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, Load1->getOperand(2) == Load2->getOperand(2)) { if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1) return false; - SDValue Op2 = Load1->getOperand(2); - if (!isa<RegisterSDNode>(Op2) || - cast<RegisterSDNode>(Op2)->getReg() != 0) - return 0; // Now let's examine the displacements. if (isa<ConstantSDNode>(Load1->getOperand(3)) && diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 65b7ec023d81..940b439d22a9 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -2707,7 +2707,7 @@ let isCodeGenOnly = 1 in { "add{b}\t{$src2, $dst|$dst, $src2}", []>; def ADD16rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2), "add{w}\t{$src2, $dst|$dst, $src2}", []>, OpSize; - def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR16:$dst),(ins GR16:$src1, GR16:$src2), + def ADD32rr_alt: I<0x03, MRMSrcReg,(outs GR32:$dst),(ins GR32:$src1, GR32:$src2), "add{l}\t{$src2, $dst|$dst, $src2}", []>; } diff --git a/lib/Target/X86/X86MCAsmInfo.cpp b/lib/Target/X86/X86MCAsmInfo.cpp index 1afabc9d9c15..d257ee38c5c7 100644 --- a/lib/Target/X86/X86MCAsmInfo.cpp +++ b/lib/Target/X86/X86MCAsmInfo.cpp @@ -84,7 +84,6 @@ X86ELFMCAsmInfo::X86ELFMCAsmInfo(const Triple &T) { HasLEB128 = true; // Target asm supports leb128 directives (little-endian) // Debug Information - AbsoluteDebugSectionOffsets = true; SupportsDebugInformation = true; // Exceptions handling diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 3238ccebb99f..32f28a520074 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -297,9 +297,7 @@ X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { bool ghcCall = false; if (MF) { - const MachineFrameInfo *MFI = MF->getFrameInfo(); - const MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); - callsEHReturn = (MMI ? MMI->callsEHReturn() : false); + callsEHReturn = MF->getMMI().callsEHReturn(); const Function *F = MF->getFunction(); ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false); } @@ -348,12 +346,8 @@ X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { const TargetRegisterClass* const* X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { bool callsEHReturn = false; - - if (MF) { - const MachineFrameInfo *MFI = MF->getFrameInfo(); - const MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); - callsEHReturn = (MMI ? MMI->callsEHReturn() : false); - } + if (MF) + callsEHReturn = MF->getMMI().callsEHReturn(); static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = { &X86::GR32RegClass, &X86::GR32RegClass, @@ -443,14 +437,14 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const { /// or if frame pointer elimination is disabled. bool X86RegisterInfo::hasFP(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); - const MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); + const MachineModuleInfo &MMI = MF.getMMI(); return (NoFramePointerElim || needsStackRealignment(MF) || MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() || MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() || - (MMI && MMI->callsUnwindInit())); + MMI.callsUnwindInit()); } bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const { @@ -800,14 +794,13 @@ void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF, MCSymbol *Label, unsigned FramePtr) const { MachineFrameInfo *MFI = MF.getFrameInfo(); - MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); - if (!MMI) return; + MachineModuleInfo &MMI = MF.getMMI(); // Add callee saved registers to move list. const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); if (CSI.empty()) return; - std::vector<MachineMove> &Moves = MMI->getFrameMoves(); + std::vector<MachineMove> &Moves = MMI.getFrameMoves(); const TargetData *TD = MF.getTarget().getTargetData(); bool HasFP = hasFP(MF); @@ -874,9 +867,9 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { MachineFrameInfo *MFI = MF.getFrameInfo(); const Function *Fn = MF.getFunction(); const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>(); - MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); + MachineModuleInfo &MMI = MF.getMMI(); X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); - bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) || + bool needsFrameMoves = MMI.hasDebugInfo() || !Fn->doesNotThrow() || UnwindTablesMandatory; uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment. uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate. @@ -935,7 +928,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { // REG < 64 => DW_CFA_offset + Reg // ELSE => DW_CFA_offset_extended - std::vector<MachineMove> &Moves = MMI->getFrameMoves(); + std::vector<MachineMove> &Moves = MMI.getFrameMoves(); const TargetData *TD = MF.getTarget().getTargetData(); uint64_t NumBytes = 0; int stackGrowth = -TD->getPointerSize(); @@ -959,7 +952,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { if (needsFrameMoves) { // Mark the place where EBP/RBP was saved. - MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol(); + MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol(); BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(FrameLabel); // Define the current CFA rule to use the provided offset. @@ -987,7 +980,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { if (needsFrameMoves) { // Mark effective beginning of when frame pointer becomes valid. - MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol(); + MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol(); BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(FrameLabel); // Define the current CFA to use the EBP/RBP register. @@ -1027,7 +1020,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { if (!HasFP && needsFrameMoves) { // Mark callee-saved push instruction. - MCSymbol *Label = MMI->getContext().CreateTempSymbol(); + MCSymbol *Label = MMI.getContext().CreateTempSymbol(); BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(Label); // Define the current CFA rule to use the provided offset. @@ -1099,7 +1092,7 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { if ((NumBytes || PushedRegs) && needsFrameMoves) { // Mark end of stack pointer adjustment. - MCSymbol *Label = MMI->getContext().CreateTempSymbol(); + MCSymbol *Label = MMI.getContext().CreateTempSymbol(); BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(Label); if (!HasFP && NumBytes) { diff --git a/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp b/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp index c88233877903..5801b40b7e90 100644 --- a/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp +++ b/lib/Target/XCore/AsmPrinter/XCoreAsmPrinter.cpp @@ -22,7 +22,6 @@ #include "llvm/DerivedTypes.h" #include "llvm/Module.h" #include "llvm/CodeGen/AsmPrinter.h" -#include "llvm/CodeGen/DwarfWriter.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineConstantPool.h" @@ -34,11 +33,11 @@ #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetRegistry.h" +#include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/FormattedStream.h" -#include "llvm/Support/MathExtras.h" +#include "llvm/Support/raw_ostream.h" #include <algorithm> #include <cctype> using namespace llvm; @@ -53,68 +52,53 @@ namespace { class XCoreAsmPrinter : public AsmPrinter { const XCoreSubtarget &Subtarget; public: - explicit XCoreAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM, - MCStreamer &Streamer) - : AsmPrinter(O, TM, Streamer), - Subtarget(TM.getSubtarget<XCoreSubtarget>()) {} + explicit XCoreAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) + : AsmPrinter(TM, Streamer), Subtarget(TM.getSubtarget<XCoreSubtarget>()){} virtual const char *getPassName() const { return "XCore Assembly Printer"; } - void printMemOperand(const MachineInstr *MI, int opNum); - void printInlineJT(const MachineInstr *MI, int opNum, + void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O); + void printInlineJT(const MachineInstr *MI, int opNum, raw_ostream &O, const std::string &directive = ".jmptable"); - void printInlineJT32(const MachineInstr *MI, int opNum) { - printInlineJT(MI, opNum, ".jmptable32"); + void printInlineJT32(const MachineInstr *MI, int opNum, raw_ostream &O) { + printInlineJT(MI, opNum, O, ".jmptable32"); } - void printOperand(const MachineInstr *MI, int opNum); + void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, const char *ExtraCode); + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O); - void emitGlobalDirective(const MCSymbol *Sym); - - void emitArrayBound(const MCSymbol *Sym, const GlobalVariable *GV); + void emitArrayBound(MCSymbol *Sym, const GlobalVariable *GV); virtual void EmitGlobalVariable(const GlobalVariable *GV); - void emitFunctionStart(MachineFunction &MF); - - void printInstruction(const MachineInstr *MI); // autogenerated. + void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen'd. static const char *getRegisterName(unsigned RegNo); - bool runOnMachineFunction(MachineFunction &MF); + void EmitFunctionEntryLabel(); void EmitInstruction(const MachineInstr *MI); void EmitFunctionBodyEnd(); - - void getAnalysisUsage(AnalysisUsage &AU) const { - AsmPrinter::getAnalysisUsage(AU); - AU.setPreservesAll(); - AU.addRequired<MachineModuleInfo>(); - AU.addRequired<DwarfWriter>(); - } }; } // end of anonymous namespace #include "XCoreGenAsmWriter.inc" -void XCoreAsmPrinter::emitGlobalDirective(const MCSymbol *Sym) { - O << MAI->getGlobalDirective() << *Sym << "\n"; -} - -void XCoreAsmPrinter::emitArrayBound(const MCSymbol *Sym, - const GlobalVariable *GV) { +void XCoreAsmPrinter::emitArrayBound(MCSymbol *Sym, const GlobalVariable *GV) { assert(((GV->hasExternalLinkage() || GV->hasWeakLinkage()) || GV->hasLinkOnceLinkage()) && "Unexpected linkage"); if (const ArrayType *ATy = dyn_cast<ArrayType>( cast<PointerType>(GV->getType())->getElementType())) { - O << MAI->getGlobalDirective() << *Sym; - O << ".globound" << "\n"; - O << "\t.set\t" << *Sym; - O << ".globound" << "," << ATy->getNumElements() << "\n"; + OutStreamer.EmitSymbolAttribute(Sym, MCSA_Global); + // FIXME: MCStreamerize. + OutStreamer.EmitRawText(StringRef(".globound")); + OutStreamer.EmitRawText("\t.set\t" + Twine(Sym->getName())); + OutStreamer.EmitRawText(".globound," + Twine(ATy->getNumElements())); if (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage()) { // TODO Use COMDAT groups for LinkOnceLinkage - O << MAI->getWeakDefDirective() << *Sym << ".globound" << "\n"; + OutStreamer.EmitRawText(MAI->getWeakDefDirective() +Twine(Sym->getName())+ + ".globound"); } } } @@ -134,7 +118,8 @@ void XCoreAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { unsigned Align = (unsigned)TD->getPreferredTypeAlignmentShift(C->getType()); // Mark the start of the global - O << "\t.cc_top " << *GVSym << ".data," << *GVSym << "\n"; + OutStreamer.EmitRawText("\t.cc_top " + Twine(GVSym->getName()) + ".data," + + GVSym->getName()); switch (GV->getLinkage()) { case GlobalValue::AppendingLinkage: @@ -145,10 +130,11 @@ void XCoreAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { case GlobalValue::WeakODRLinkage: case GlobalValue::ExternalLinkage: emitArrayBound(GVSym, GV); - emitGlobalDirective(GVSym); + OutStreamer.EmitSymbolAttribute(GVSym, MCSA_Global); + // TODO Use COMDAT groups for LinkOnceLinkage if (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage()) - O << MAI->getWeakDefDirective() << *GVSym << "\n"; + OutStreamer.EmitSymbolAttribute(GVSym, MCSA_Weak); // FALL THROUGH case GlobalValue::InternalLinkage: case GlobalValue::PrivateLinkage: @@ -169,10 +155,11 @@ void XCoreAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { Size *= MaxThreads; } if (MAI->hasDotTypeDotSizeDirective()) { - O << "\t.type " << *GVSym << ",@object\n"; - O << "\t.size " << *GVSym << "," << Size << "\n"; + OutStreamer.EmitSymbolAttribute(GVSym, MCSA_ELF_TypeObject); + OutStreamer.EmitRawText("\t.size " + Twine(GVSym->getName()) + "," + + Twine(Size)); } - O << *GVSym << ":\n"; + OutStreamer.EmitLabel(GVSym); EmitGlobalConstant(C); if (GV->isThreadLocal()) { @@ -185,87 +172,38 @@ void XCoreAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) { OutStreamer.EmitZeros(4 - Size, 0); // Mark the end of the global - O << "\t.cc_bottom " << *GVSym << ".data\n"; + OutStreamer.EmitRawText("\t.cc_bottom " + Twine(GVSym->getName()) + ".data"); } -/// Emit the directives on the start of functions -void XCoreAsmPrinter::emitFunctionStart(MachineFunction &MF) { - // Print out the label for the function. - const Function *F = MF.getFunction(); - - OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM)); - - // Mark the start of the function - O << "\t.cc_top " << *CurrentFnSym << ".function," << *CurrentFnSym << "\n"; - - switch (F->getLinkage()) { - default: llvm_unreachable("Unknown linkage type!"); - case Function::InternalLinkage: // Symbols default to internal. - case Function::PrivateLinkage: - case Function::LinkerPrivateLinkage: - break; - case Function::ExternalLinkage: - emitGlobalDirective(CurrentFnSym); - break; - case Function::LinkOnceAnyLinkage: - case Function::LinkOnceODRLinkage: - case Function::WeakAnyLinkage: - case Function::WeakODRLinkage: - // TODO Use COMDAT groups for LinkOnceLinkage - O << MAI->getGlobalDirective() << *CurrentFnSym << "\n"; - O << MAI->getWeakDefDirective() << *CurrentFnSym << "\n"; - break; - } - // (1 << 1) byte aligned - EmitAlignment(MF.getAlignment(), F, 1); - if (MAI->hasDotTypeDotSizeDirective()) - O << "\t.type " << *CurrentFnSym << ",@function\n"; - - O << *CurrentFnSym << ":\n"; -} - - /// EmitFunctionBodyEnd - Targets can override this to emit stuff after /// the last basic block in the function. void XCoreAsmPrinter::EmitFunctionBodyEnd() { // Emit function end directives - O << "\t.cc_bottom " << *CurrentFnSym << ".function\n"; + OutStreamer.EmitRawText("\t.cc_bottom " + Twine(CurrentFnSym->getName()) + + ".function"); } -/// runOnMachineFunction - This uses the printMachineInstruction() -/// method to print assembly for each instruction. -/// -bool XCoreAsmPrinter::runOnMachineFunction(MachineFunction &MF) { - SetupMachineFunction(MF); - - // Print out constants referenced by the function - EmitConstantPool(); - - // Emit the function start directives - emitFunctionStart(MF); - - // Emit pre-function debug information. - DW->BeginFunction(&MF); - - EmitFunctionBody(); - return false; +void XCoreAsmPrinter::EmitFunctionEntryLabel() { + // Mark the start of the function + OutStreamer.EmitRawText("\t.cc_top " + Twine(CurrentFnSym->getName()) + + ".function," + CurrentFnSym->getName()); + OutStreamer.EmitLabel(CurrentFnSym); } -void XCoreAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) -{ - printOperand(MI, opNum); +void XCoreAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { + printOperand(MI, opNum, O); - if (MI->getOperand(opNum+1).isImm() - && MI->getOperand(opNum+1).getImm() == 0) + if (MI->getOperand(opNum+1).isImm() && MI->getOperand(opNum+1).getImm() == 0) return; O << "+"; - printOperand(MI, opNum+1); + printOperand(MI, opNum+1, O); } void XCoreAsmPrinter:: -printInlineJT(const MachineInstr *MI, int opNum, const std::string &directive) -{ +printInlineJT(const MachineInstr *MI, int opNum, raw_ostream &O, + const std::string &directive) { unsigned JTI = MI->getOperand(opNum).getIndex(); const MachineFunction *MF = MI->getParent()->getParent(); const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); @@ -280,7 +218,8 @@ printInlineJT(const MachineInstr *MI, int opNum, const std::string &directive) } } -void XCoreAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { +void XCoreAsmPrinter::printOperand(const MachineInstr *MI, int opNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(opNum); switch (MO.getType()) { case MachineOperand::MO_Register: @@ -317,23 +256,25 @@ void XCoreAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { /// PrintAsmOperand - Print out an operand for an inline asm expression. /// bool XCoreAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, - unsigned AsmVariant, - const char *ExtraCode) { - printOperand(MI, OpNo); + unsigned AsmVariant,const char *ExtraCode, + raw_ostream &O) { + printOperand(MI, OpNo, O); return false; } void XCoreAsmPrinter::EmitInstruction(const MachineInstr *MI) { + SmallString<128> Str; + raw_svector_ostream O(Str); + // Check for mov mnemonic unsigned src, dst, srcSR, dstSR; if (TM.getInstrInfo()->isMoveInstr(*MI, src, dst, srcSR, dstSR)) { O << "\tmov " << getRegisterName(dst) << ", "; O << getRegisterName(src); - OutStreamer.AddBlankLine(); - return; + } else { + printInstruction(MI, O); } - printInstruction(MI); - OutStreamer.AddBlankLine(); + OutStreamer.EmitRawText(O.str()); } // Force static initialization. diff --git a/lib/Target/XCore/XCore.td b/lib/Target/XCore/XCore.td index b07445dd386f..38401895e634 100644 --- a/lib/Target/XCore/XCore.td +++ b/lib/Target/XCore/XCore.td @@ -24,10 +24,7 @@ include "XCoreRegisterInfo.td" include "XCoreInstrInfo.td" include "XCoreCallingConv.td" -def XCoreInstrInfo : InstrInfo { - let TSFlagsFields = []; - let TSFlagsShifts = []; -} +def XCoreInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// // XCore processors supported. diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index bf1a45762795..27e523324664 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -1443,7 +1443,7 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, return DAG.getMemmove(Chain, dl, ST->getBasePtr(), LD->getBasePtr(), DAG.getConstant(StoreBits/8, MVT::i32), - Alignment, ST->getSrcValue(), + Alignment, false, ST->getSrcValue(), ST->getSrcValueOffset(), LD->getSrcValue(), LD->getSrcValueOffset()); } diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp index ae3f16c2dfe4..c9831128ba22 100644 --- a/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/lib/Target/XCore/XCoreInstrInfo.cpp @@ -14,12 +14,12 @@ #include "XCoreMachineFunctionInfo.h" #include "XCoreInstrInfo.h" #include "XCore.h" -#include "llvm/ADT/STLExtras.h" +#include "llvm/MC/MCContext.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineLocation.h" -#include "llvm/CodeGen/MachineModuleInfo.h" #include "XCoreGenInstrInfo.inc" +#include "llvm/ADT/STLExtras.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" @@ -419,14 +419,11 @@ void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - const std::vector<CalleeSavedInfo> &CSI) const -{ + const std::vector<CalleeSavedInfo> &CSI) const { if (CSI.empty()) { return true; } MachineFunction *MF = MBB.getParent(); - const MachineFrameInfo *MFI = MF->getFrameInfo(); - MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); XCoreFunctionInfo *XFI = MF->getInfo<XCoreFunctionInfo>(); bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF); @@ -442,7 +439,7 @@ bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, storeRegToStackSlot(MBB, MI, it->getReg(), true, it->getFrameIdx(), it->getRegClass()); if (emitFrameMoves) { - MCSymbol *SaveLabel = MMI->getContext().CreateTempSymbol(); + MCSymbol *SaveLabel = MF->getContext().CreateTempSymbol(); BuildMI(MBB, MI, DL, get(XCore::DBG_LABEL)).addSym(SaveLabel); XFI->getSpillLabels().push_back(std::make_pair(SaveLabel, *it)); } diff --git a/lib/Target/XCore/XCoreMCAsmInfo.cpp b/lib/Target/XCore/XCoreMCAsmInfo.cpp index bf785755db4e..5f6feae37235 100644 --- a/lib/Target/XCore/XCoreMCAsmInfo.cpp +++ b/lib/Target/XCore/XCoreMCAsmInfo.cpp @@ -25,6 +25,5 @@ XCoreMCAsmInfo::XCoreMCAsmInfo(const Target &T, const StringRef &TT) { // Debug HasLEB128 = true; - AbsoluteDebugSectionOffsets = true; } diff --git a/lib/Target/XCore/XCoreRegisterInfo.cpp b/lib/Target/XCore/XCoreRegisterInfo.cpp index 1631e7399922..ab71d0535444 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.cpp +++ b/lib/Target/XCore/XCoreRegisterInfo.cpp @@ -67,12 +67,8 @@ unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF) return array_lengthof(XCore_ArgRegs); } -bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) -{ - const MachineFrameInfo *MFI = MF.getFrameInfo(); - MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); - return (MMI && MMI->hasDebugInfo()) || - !MF.getFunction()->doesNotThrow() || +bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) { + return MF.getMMI().hasDebugInfo() || !MF.getFunction()->doesNotThrow() || UnwindTablesMandatory; } @@ -412,7 +408,7 @@ void XCoreRegisterInfo::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); - MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); + MachineModuleInfo *MMI = &MF.getMMI(); XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); |