diff options
Diffstat (limited to 'lib/Target/ARM/ARMBaseInstrInfo.h')
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.h | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.h b/lib/Target/ARM/ARMBaseInstrInfo.h index a13155b9fd0d..2ba377474e9e 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/lib/Target/ARM/ARMBaseInstrInfo.h @@ -131,6 +131,14 @@ namespace ARMII { Xform16Bit = 1 << 16, //===------------------------------------------------------------------===// + // Code domain. + DomainShift = 17, + DomainMask = 3 << DomainShift, + DomainGeneral = 0 << DomainShift, + DomainVFP = 1 << DomainShift, + DomainNEON = 2 << DomainShift, + + //===------------------------------------------------------------------===// // Field shifts - such shifts are used to set field while generating // machine instructions. M_BitShift = 5, @@ -157,9 +165,10 @@ namespace ARMII { } class ARMBaseInstrInfo : public TargetInstrInfoImpl { + const ARMSubtarget& Subtarget; protected: // Can be only subclassed. - explicit ARMBaseInstrInfo(); + explicit ARMBaseInstrInfo(const ARMSubtarget &STI); public: // Return the non-pre/post incrementing version of 'Opc'. Return 0 // if there is not such an opcode. @@ -173,6 +182,7 @@ public: LiveVariables *LV) const; virtual const ARMBaseRegisterInfo &getRegisterInfo() const =0; + const ARMSubtarget &getSubtarget() const { return Subtarget; } // Branch analysis. virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, @@ -293,6 +303,11 @@ bool isJumpTableBranchOpcode(int Opc) { Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT; } +static inline +bool isIndirectBranchOpcode(int Opc) { + return Opc == ARM::BRIND || Opc == ARM::tBRIND; +} + /// getInstrPredicate - If instruction is predicated, returns its predicate /// condition, otherwise returns AL. It also returns the condition code /// register by reference. |