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-rw-r--r--contrib/llvm/tools/clang/lib/Basic/Targets.cpp815
1 files changed, 586 insertions, 229 deletions
diff --git a/contrib/llvm/tools/clang/lib/Basic/Targets.cpp b/contrib/llvm/tools/clang/lib/Basic/Targets.cpp
index a7a00570d127..a768081e70e0 100644
--- a/contrib/llvm/tools/clang/lib/Basic/Targets.cpp
+++ b/contrib/llvm/tools/clang/lib/Basic/Targets.cpp
@@ -25,9 +25,9 @@
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Triple.h"
-#include "llvm/IR/Type.h"
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/TargetParser.h"
#include <algorithm>
#include <memory>
using namespace clang;
@@ -185,6 +185,28 @@ static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
}
namespace {
+// CloudABI Target
+template <typename Target>
+class CloudABITargetInfo : public OSTargetInfo<Target> {
+protected:
+ void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
+ MacroBuilder &Builder) const override {
+ Builder.defineMacro("__CloudABI__");
+ Builder.defineMacro("__ELF__");
+
+ // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
+ Builder.defineMacro("__STDC_ISO_10646__", "201206L");
+ Builder.defineMacro("__STDC_UTF_16__");
+ Builder.defineMacro("__STDC_UTF_32__");
+ }
+
+public:
+ CloudABITargetInfo(const llvm::Triple &Triple)
+ : OSTargetInfo<Target>(Triple) {
+ this->UserLabelPrefix = "";
+ }
+};
+
template<typename Target>
class DarwinTargetInfo : public OSTargetInfo<Target> {
protected:
@@ -364,8 +386,13 @@ protected:
DefineStd(Builder, "linux", Opts);
Builder.defineMacro("__gnu_linux__");
Builder.defineMacro("__ELF__");
- if (Triple.getEnvironment() == llvm::Triple::Android)
+ if (Triple.getEnvironment() == llvm::Triple::Android) {
Builder.defineMacro("__ANDROID__", "1");
+ unsigned Maj, Min, Rev;
+ Triple.getOSVersion(Maj, Min, Rev);
+ this->PlatformName = "android";
+ this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
+ }
if (Opts.POSIXThreads)
Builder.defineMacro("_REENTRANT");
if (Opts.CPlusPlus)
@@ -473,6 +500,17 @@ protected:
Builder.defineMacro("__ELF__");
if (Opts.POSIXThreads)
Builder.defineMacro("_REENTRANT");
+
+ switch (Triple.getArch()) {
+ default:
+ break;
+ case llvm::Triple::arm:
+ case llvm::Triple::armeb:
+ case llvm::Triple::thumb:
+ case llvm::Triple::thumbeb:
+ Builder.defineMacro("__ARM_DWARF_EH__");
+ break;
+ }
}
public:
BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
@@ -526,6 +564,33 @@ public:
}
};
+template <typename Target>
+class PS4OSTargetInfo : public OSTargetInfo<Target> {
+protected:
+ void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
+ MacroBuilder &Builder) const override {
+ Builder.defineMacro("__FreeBSD__", "9");
+ Builder.defineMacro("__FreeBSD_cc_version", "900001");
+ Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
+ DefineStd(Builder, "unix", Opts);
+ Builder.defineMacro("__ELF__");
+ Builder.defineMacro("__PS4__");
+ }
+public:
+ PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
+ this->WCharType = this->UnsignedShort;
+
+ this->UserLabelPrefix = "";
+
+ switch (Triple.getArch()) {
+ default:
+ case llvm::Triple::x86_64:
+ this->MCountName = ".mcount";
+ break;
+ }
+ }
+};
+
// Solaris target
template<typename Target>
class SolarisTargetInfo : public OSTargetInfo<Target> {
@@ -574,7 +639,7 @@ protected:
if (Opts.RTTIData)
Builder.defineMacro("_CPPRTTI");
- if (Opts.Exceptions)
+ if (Opts.CXXExceptions)
Builder.defineMacro("_CPPUNWIND");
}
@@ -592,6 +657,9 @@ protected:
Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
// FIXME We cannot encode the revision information into 32-bits
Builder.defineMacro("_MSC_BUILD", Twine(1));
+
+ if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
+ Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
}
if (Opts.MicrosoftExt) {
@@ -647,8 +715,7 @@ public:
// RegParmMax is inherited from the underlying architecture
this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
if (Triple.getArch() == llvm::Triple::arm) {
- this->DescriptionString =
- "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
+ // Handled in ARM's setABI().
} else if (Triple.getArch() == llvm::Triple::x86) {
this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
} else if (Triple.getArch() == llvm::Triple::x86_64) {
@@ -660,19 +727,12 @@ public:
this->DescriptionString = "e-p:32:32-i64:64";
}
}
- typename Target::CallingConvCheckResult checkCallingConvention(
- CallingConv CC) const override {
- return CC == CC_PnaclCall ? Target::CCCR_OK :
- Target::checkCallingConvention(CC);
- }
};
-} // end anonymous namespace.
//===----------------------------------------------------------------------===//
// Specific target implementations.
//===----------------------------------------------------------------------===//
-namespace {
// PPC abstract base class
class PPCTargetInfo : public TargetInfo {
static const Builtin::Info BuiltinInfo[];
@@ -683,13 +743,21 @@ class PPCTargetInfo : public TargetInfo {
// Target cpu features.
bool HasVSX;
bool HasP8Vector;
+ bool HasP8Crypto;
+ bool HasDirectMove;
+ bool HasQPX;
+ bool HasHTM;
+ bool HasBPERMD;
+ bool HasExtDiv;
protected:
std::string ABI;
public:
PPCTargetInfo(const llvm::Triple &Triple)
- : TargetInfo(Triple), HasVSX(false), HasP8Vector(false) {
+ : TargetInfo(Triple), HasVSX(false), HasP8Vector(false),
+ HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
+ HasBPERMD(false), HasExtDiv(false) {
BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
LongDoubleWidth = LongDoubleAlign = 128;
LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
@@ -949,8 +1017,40 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
continue;
}
+ if (Feature == "bpermd") {
+ HasBPERMD = true;
+ continue;
+ }
+
+ if (Feature == "extdiv") {
+ HasExtDiv = true;
+ continue;
+ }
+
if (Feature == "power8-vector") {
HasP8Vector = true;
+ HasVSX = true;
+ continue;
+ }
+
+ if (Feature == "crypto") {
+ HasP8Crypto = true;
+ continue;
+ }
+
+ if (Feature == "direct-move") {
+ HasDirectMove = true;
+ HasVSX = true;
+ continue;
+ }
+
+ if (Feature == "qpx") {
+ HasQPX = true;
+ continue;
+ }
+
+ if (Feature == "htm") {
+ HasHTM = true;
continue;
}
@@ -988,7 +1088,7 @@ void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
}
// ABI options.
- if (ABI == "elfv1")
+ if (ABI == "elfv1" || ABI == "elfv1-qpx")
Builder.defineMacro("_CALL_ELF", "1");
if (ABI == "elfv2")
Builder.defineMacro("_CALL_ELF", "2");
@@ -1106,6 +1206,18 @@ void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__VSX__");
if (HasP8Vector)
Builder.defineMacro("__POWER8_VECTOR__");
+ if (HasP8Crypto)
+ Builder.defineMacro("__CRYPTO__");
+ if (HasHTM)
+ Builder.defineMacro("__HTM__");
+ if (getTriple().getArch() == llvm::Triple::ppc64le ||
+ (defs & ArchDefinePwr8) || (CPU == "pwr8")) {
+ Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
+ Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
+ Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
+ if (PointerWidth == 64)
+ Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
+ }
// FIXME: The following are not yet generated here by Clang, but are
// generated by GCC:
@@ -1144,9 +1256,28 @@ void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
.Default(false);
Features["qpx"] = (CPU == "a2q");
-
- if (!ABI.empty())
- Features[ABI] = true;
+ Features["crypto"] = llvm::StringSwitch<bool>(CPU)
+ .Case("ppc64le", true)
+ .Case("pwr8", true)
+ .Default(false);
+ Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
+ .Case("ppc64le", true)
+ .Case("pwr8", true)
+ .Default(false);
+ Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
+ .Case("ppc64le", true)
+ .Case("pwr8", true)
+ .Case("pwr7", true)
+ .Default(false);
+ Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
+ .Case("ppc64le", true)
+ .Case("pwr8", true)
+ .Case("pwr7", true)
+ .Default(false);
+ Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
+ .Case("ppc64le", true)
+ .Case("pwr8", true)
+ .Default(false);
}
bool PPCTargetInfo::hasFeature(StringRef Feature) const {
@@ -1154,6 +1285,12 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const {
.Case("powerpc", true)
.Case("vsx", HasVSX)
.Case("power8-vector", HasP8Vector)
+ .Case("crypto", HasP8Crypto)
+ .Case("direct-move", HasDirectMove)
+ .Case("qpx", HasQPX)
+ .Case("htm", HasHTM)
+ .Case("bpermd", HasBPERMD)
+ .Case("extdiv", HasExtDiv)
.Default(false);
}
@@ -1259,9 +1396,7 @@ void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
Aliases = GCCRegAliases;
NumAliases = llvm::array_lengthof(GCCRegAliases);
}
-} // end anonymous namespace.
-namespace {
class PPC32TargetInfo : public PPCTargetInfo {
public:
PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
@@ -1293,11 +1428,9 @@ public:
return TargetInfo::PowerABIBuiltinVaList;
}
};
-} // end anonymous namespace.
// Note: ABI differences may eventually require us to have a separate
// TargetInfo for little endian.
-namespace {
class PPC64TargetInfo : public PPCTargetInfo {
public:
PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
@@ -1334,17 +1467,14 @@ public:
}
// PPC64 Linux-specifc ABI options.
bool setABI(const std::string &Name) override {
- if (Name == "elfv1" || Name == "elfv2") {
+ if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
ABI = Name;
return true;
}
return false;
}
};
-} // end anonymous namespace.
-
-namespace {
class DarwinPPC32TargetInfo :
public DarwinTargetInfo<PPC32TargetInfo> {
public:
@@ -1372,9 +1502,7 @@ public:
DescriptionString = "E-m:o-i64:64-n32:64";
}
};
-} // end anonymous namespace.
-namespace {
static const unsigned NVPTXAddrSpaceMap[] = {
1, // opencl_global
3, // opencl_local
@@ -1396,6 +1524,7 @@ namespace {
GK_SM21,
GK_SM30,
GK_SM35,
+ GK_SM37,
} GPU;
public:
@@ -1431,6 +1560,9 @@ namespace {
case GK_SM35:
CUDAArchCode = "350";
break;
+ case GK_SM37:
+ CUDAArchCode = "370";
+ break;
default:
llvm_unreachable("Unhandled target CPU");
}
@@ -1483,6 +1615,7 @@ namespace {
.Case("sm_21", GK_SM21)
.Case("sm_30", GK_SM30)
.Case("sm_35", GK_SM35)
+ .Case("sm_37", GK_SM37)
.Default(GK_NONE);
return GPU != GK_NONE;
@@ -1510,24 +1643,23 @@ namespace {
public:
NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
PointerWidth = PointerAlign = 32;
- SizeType = PtrDiffType = TargetInfo::UnsignedInt;
+ SizeType = TargetInfo::UnsignedInt;
+ PtrDiffType = TargetInfo::SignedInt;
IntPtrType = TargetInfo::SignedInt;
DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
- }
+ }
};
class NVPTX64TargetInfo : public NVPTXTargetInfo {
public:
NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
PointerWidth = PointerAlign = 64;
- SizeType = PtrDiffType = TargetInfo::UnsignedLongLong;
- IntPtrType = TargetInfo::SignedLongLong;
+ SizeType = TargetInfo::UnsignedLong;
+ PtrDiffType = TargetInfo::SignedLong;
+ IntPtrType = TargetInfo::SignedLong;
DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
- }
+ }
};
-}
-
-namespace {
static const unsigned R600AddrSpaceMap[] = {
1, // opencl_global
@@ -1557,6 +1689,7 @@ static const char *DescriptionStringSI =
class R600TargetInfo : public TargetInfo {
static const Builtin::Info BuiltinInfo[];
+ static const char * const GCCRegNames[];
/// \brief The GPU profiles supported by the R600 target.
enum GPUKind {
@@ -1573,10 +1706,27 @@ class R600TargetInfo : public TargetInfo {
GK_SEA_ISLANDS
} GPU;
+ bool hasFP64:1;
+ bool hasFMAF:1;
+ bool hasLDEXPF:1;
+
public:
R600TargetInfo(const llvm::Triple &Triple)
- : TargetInfo(Triple), GPU(GK_R600) {
- DescriptionString = DescriptionStringR600;
+ : TargetInfo(Triple) {
+
+ if (Triple.getArch() == llvm::Triple::amdgcn) {
+ DescriptionString = DescriptionStringSI;
+ GPU = GK_SOUTHERN_ISLANDS;
+ hasFP64 = true;
+ hasFMAF = true;
+ hasLDEXPF = true;
+ } else {
+ DescriptionString = DescriptionStringR600;
+ GPU = GK_R600;
+ hasFP64 = false;
+ hasFMAF = false;
+ hasLDEXPF = false;
+ }
AddrSpaceMap = &R600AddrSpaceMap;
UseAddrSpaceMapMangling = true;
}
@@ -1600,10 +1750,7 @@ public:
}
void getGCCRegNames(const char * const *&Names,
- unsigned &numNames) const override {
- Names = nullptr;
- numNames = 0;
- }
+ unsigned &NumNames) const override;
void getGCCRegAliases(const GCCRegAlias *&Aliases,
unsigned &NumAliases) const override {
@@ -1625,6 +1772,13 @@ public:
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override {
Builder.defineMacro("__R600__");
+ if (hasFMAF)
+ Builder.defineMacro("__HAS_FMAF__");
+ if (hasLDEXPF)
+ Builder.defineMacro("__HAS_LDEXPF__");
+ if (hasFP64 && Opts.OpenCL) {
+ Builder.defineMacro("cl_khr_fp64");
+ }
}
BuiltinVaListKind getBuiltinVaListKind() const override {
@@ -1682,16 +1836,25 @@ public:
case GK_EVERGREEN:
case GK_NORTHERN_ISLANDS:
DescriptionString = DescriptionStringR600;
+ hasFP64 = false;
+ hasFMAF = false;
+ hasLDEXPF = false;
break;
case GK_R600_DOUBLE_OPS:
case GK_R700_DOUBLE_OPS:
case GK_EVERGREEN_DOUBLE_OPS:
case GK_CAYMAN:
DescriptionString = DescriptionStringR600DoubleOps;
+ hasFP64 = true;
+ hasFMAF = true;
+ hasLDEXPF = false;
break;
case GK_SOUTHERN_ISLANDS:
case GK_SEA_ISLANDS:
DescriptionString = DescriptionStringSI;
+ hasFP64 = true;
+ hasFMAF = true;
+ hasLDEXPF = true;
break;
}
@@ -1704,10 +1867,65 @@ const Builtin::Info R600TargetInfo::BuiltinInfo[] = {
{ #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
#include "clang/Basic/BuiltinsR600.def"
};
+const char * const R600TargetInfo::GCCRegNames[] = {
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
+ "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
+ "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+ "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
+ "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
+ "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
+ "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
+ "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
+ "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
+ "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
+ "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
+ "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
+ "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
+ "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
+ "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
+ "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
+ "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
+ "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
+ "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
+ "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
+ "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
+ "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
+ "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
+ "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
+ "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
+ "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
+ "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
+ "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
+ "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
+ "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
+ "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
+ "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
+ "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
+ "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
+ "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
+ "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
+ "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
+ "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
+ "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
+ "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
+ "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
+ "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
+ "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
+ "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
+ "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
+ "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
+ "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
+ "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127"
+ "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi",
+ "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi"
+};
-} // end anonymous namespace
+void R600TargetInfo::getGCCRegNames(const char * const *&Names,
+ unsigned &NumNames) const {
+ Names = GCCRegNames;
+ NumNames = llvm::array_lengthof(GCCRegNames);
+}
-namespace {
// Namespace for x86 abstract base class
const Builtin::Info BuiltinInfo[] = {
#define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
@@ -2496,11 +2714,6 @@ void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
StringRef Name, bool Enabled) {
- // FIXME: This *really* should not be here. We need some way of translating
- // options into llvm subtarget features.
- if (Name == "sse4")
- Name = "sse4.2";
-
Features[Name] = Enabled;
if (Name == "mmx") {
@@ -3236,9 +3449,7 @@ X86TargetInfo::convertConstraint(const char *&Constraint) const {
return std::string(1, *Constraint);
}
}
-} // end anonymous namespace
-namespace {
// X86-32 generic target
class X86_32TargetInfo : public X86TargetInfo {
public:
@@ -3293,9 +3504,7 @@ public:
return X86TargetInfo::validateOperandSize(Constraint, Size);
}
};
-} // end anonymous namespace
-namespace {
class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
public:
NetBSDI386TargetInfo(const llvm::Triple &Triple)
@@ -3311,9 +3520,7 @@ public:
return 1;
}
};
-} // end anonymous namespace
-namespace {
class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
public:
OpenBSDI386TargetInfo(const llvm::Triple &Triple)
@@ -3323,9 +3530,7 @@ public:
PtrDiffType = SignedLong;
}
};
-} // end anonymous namespace
-namespace {
class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
public:
BitrigI386TargetInfo(const llvm::Triple &Triple)
@@ -3335,9 +3540,7 @@ public:
PtrDiffType = SignedLong;
}
};
-} // end anonymous namespace
-namespace {
class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
public:
DarwinI386TargetInfo(const llvm::Triple &Triple)
@@ -3353,9 +3556,7 @@ public:
}
};
-} // end anonymous namespace
-namespace {
// x86-32 Windows target
class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
public:
@@ -3365,8 +3566,9 @@ public:
DoubleAlign = LongLongAlign = 64;
bool IsWinCOFF =
getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
- DescriptionString = IsWinCOFF ? "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"
- : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-S32";
+ DescriptionString = IsWinCOFF
+ ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
+ : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
}
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override {
@@ -3436,9 +3638,7 @@ public:
addMinGWDefines(Opts, Builder);
}
};
-} // end anonymous namespace
-namespace {
// x86-32 Cygwin target
class CygwinX86_32TargetInfo : public X86_32TargetInfo {
public:
@@ -3447,7 +3647,7 @@ public:
TLSSupported = false;
WCharType = UnsignedShort;
DoubleAlign = LongLongAlign = 64;
- DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
+ DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
}
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override {
@@ -3460,9 +3660,7 @@ public:
Builder.defineMacro("_GNU_SOURCE");
}
};
-} // end anonymous namespace
-namespace {
// x86-32 Haiku target
class HaikuX86_32TargetInfo : public X86_32TargetInfo {
public:
@@ -3481,7 +3679,6 @@ public:
Builder.defineMacro("__HAIKU__");
}
};
-} // end anonymous namespace
// RTEMS Target
template<typename Target>
@@ -3518,7 +3715,6 @@ public:
}
};
-namespace {
// x86-32 RTEMS target
class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
public:
@@ -3535,14 +3731,14 @@ public:
Builder.defineMacro("__rtems__");
}
};
-} // end anonymous namespace
-namespace {
// x86-64 generic target
class X86_64TargetInfo : public X86TargetInfo {
public:
X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
+ bool IsWinCOFF =
+ getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
LongDoubleWidth = 128;
LongDoubleAlign = 128;
@@ -3557,9 +3753,10 @@ public:
RegParmMax = 6;
// Pointers are 32-bit in x32.
- DescriptionString = (IsX32)
- ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
- : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
+ DescriptionString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
+ : IsWinCOFF
+ ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
+ : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
// Use fpret only for long double.
RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
@@ -3595,9 +3792,7 @@ public:
// for x32 we need it here explicitly
bool hasInt128Type() const override { return true; }
};
-} // end anonymous namespace
-namespace {
// x86-64 Windows target
class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
public:
@@ -3613,24 +3808,34 @@ public:
IntPtrType = SignedLongLong;
this->UserLabelPrefix = "";
}
+
void getTargetDefines(const LangOptions &Opts,
MacroBuilder &Builder) const override {
WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
Builder.defineMacro("_WIN64");
}
+
BuiltinVaListKind getBuiltinVaListKind() const override {
return TargetInfo::CharPtrBuiltinVaList;
}
+
CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
- return (CC == CC_C ||
- CC == CC_X86VectorCall ||
- CC == CC_IntelOclBicc ||
- CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning;
+ switch (CC) {
+ case CC_X86StdCall:
+ case CC_X86ThisCall:
+ case CC_X86FastCall:
+ return CCCR_Ignore;
+ case CC_C:
+ case CC_X86VectorCall:
+ case CC_IntelOclBicc:
+ case CC_X86_64SysV:
+ return CCCR_OK;
+ default:
+ return CCCR_Warning;
+ }
}
};
-} // end anonymous namespace
-namespace {
// x86-64 Windows Visual Studio target
class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
public:
@@ -3647,9 +3852,7 @@ public:
Builder.defineMacro("_M_AMD64");
}
};
-} // end anonymous namespace
-namespace {
// x86-64 MinGW target
class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
public:
@@ -3667,9 +3870,7 @@ public:
Builder.defineMacro("__SEH__");
}
};
-} // end anonymous namespace
-namespace {
class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
public:
DarwinX86_64TargetInfo(const llvm::Triple &Triple)
@@ -3683,9 +3884,7 @@ public:
DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
}
};
-} // end anonymous namespace
-namespace {
class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
public:
OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
@@ -3694,9 +3893,7 @@ public:
Int64Type = SignedLongLong;
}
};
-} // end anonymous namespace
-namespace {
class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
public:
BitrigX86_64TargetInfo(const llvm::Triple &Triple)
@@ -3705,10 +3902,7 @@ public:
Int64Type = SignedLongLong;
}
};
-}
-
-namespace {
class ARMTargetInfo : public TargetInfo {
// Possible FPU choices.
enum FPUMode {
@@ -3800,8 +3994,9 @@ class ARMTargetInfo : public TargetInfo {
DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
const llvm::Triple &T = getTriple();
- // size_t is unsigned long on MachO-derived environments and NetBSD.
- if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD)
+ // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig.
+ if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
+ T.getOS() == llvm::Triple::Bitrig)
SizeType = UnsignedLong;
else
SizeType = UnsignedInt;
@@ -3831,16 +4026,18 @@ class ARMTargetInfo : public TargetInfo {
BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
: "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
} else if (T.isOSWindows()) {
- // FIXME: this is invalid for WindowsCE
assert(!BigEndian && "Windows on ARM does not support big endian");
DescriptionString = "e"
- "-m:e"
+ "-m:w"
"-p:32:32"
"-i64:64"
"-v128:64:128"
"-a:0:32"
"-n32"
"-S64";
+ } else if (T.isOSNaCl()) {
+ assert(!BigEndian && "NaCl on ARM does not support big endian");
+ DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
} else {
DescriptionString =
BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
@@ -3984,8 +4181,15 @@ public:
return false;
}
+ // FIXME: This should be based on Arch attributes, not CPU names.
void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
StringRef ArchName = getTriple().getArchName();
+ unsigned ArchKind =
+ llvm::ARMTargetParser::parseArch(
+ llvm::ARMTargetParser::getCanonicalArchName(ArchName));
+ bool IsV8 = (ArchKind == llvm::ARM::AK_ARMV8A ||
+ ArchKind == llvm::ARM::AK_ARMV8_1A);
+
if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
Features["vfp2"] = true;
else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
@@ -4002,28 +4206,19 @@ public:
Features["neon"] = true;
Features["hwdiv"] = true;
Features["hwdiv-arm"] = true;
- } else if (CPU == "cyclone") {
- Features["v8fp"] = true;
- Features["neon"] = true;
- Features["hwdiv"] = true;
- Features["hwdiv-arm"] = true;
- } else if (CPU == "cortex-a53" || CPU == "cortex-a57") {
+ } else if (CPU == "cyclone" || CPU == "cortex-a53" || CPU == "cortex-a57" ||
+ CPU == "cortex-a72") {
Features["fp-armv8"] = true;
Features["neon"] = true;
Features["hwdiv"] = true;
Features["hwdiv-arm"] = true;
Features["crc"] = true;
Features["crypto"] = true;
- } else if (CPU == "cortex-r5" ||
- // Enable the hwdiv extension for all v8a AArch32 cores by
- // default.
- ArchName == "armv8a" || ArchName == "armv8" ||
- ArchName == "armebv8a" || ArchName == "armebv8" ||
- ArchName == "thumbv8a" || ArchName == "thumbv8" ||
- ArchName == "thumbebv8a" || ArchName == "thumbebv8") {
+ } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || IsV8) {
Features["hwdiv"] = true;
Features["hwdiv-arm"] = true;
- } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7") {
+ } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" ||
+ CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") {
Features["hwdiv"] = true;
}
}
@@ -4080,12 +4275,10 @@ public:
Features.push_back("-neonfp");
// Remove front-end specific options which the backend handles differently.
- const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" };
- for (const auto &FEFeature : FrontEndFeatures) {
- auto Feature = std::find(Features.begin(), Features.end(), FEFeature);
- if (Feature != Features.end())
- Features.erase(Feature);
- }
+ auto Feature =
+ std::find(Features.begin(), Features.end(), "+soft-float-abi");
+ if (Feature != Features.end())
+ Features.erase(Feature);
return true;
}
@@ -4101,7 +4294,18 @@ public:
.Default(false);
}
// FIXME: Should we actually have some table instead of these switches?
- static const char *getCPUDefineSuffix(StringRef Name) {
+ const char *getCPUDefineSuffix(StringRef Name) const {
+ // FIXME: Use ARMTargetParser
+ if(Name == "generic") {
+ auto subarch = getTriple().getSubArch();
+ switch (subarch) {
+ case llvm::Triple::SubArchType::ARMSubArch_v8_1a:
+ return "8_1A";
+ default:
+ break;
+ }
+ }
+
return llvm::StringSwitch<const char *>(Name)
.Cases("arm8", "arm810", "4")
.Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110",
@@ -4115,30 +4319,48 @@ public:
.Cases("arm10e", "arm1020e", "arm1022e", "5TE")
.Cases("xscale", "iwmmxt", "5TE")
.Case("arm1136j-s", "6J")
- .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
- .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
+ .Case("arm1136jf-s", "6")
+ .Cases("mpcorenovfp", "mpcore", "6K")
+ .Cases("arm1176jz-s", "arm1176jzf-s", "6K")
.Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
.Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
.Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
"7A")
- .Cases("cortex-r4", "cortex-r5", "7R")
+ .Cases("cortex-r4", "cortex-r4f", "cortex-r5", "cortex-r7", "7R")
.Case("swift", "7S")
.Case("cyclone", "8A")
- .Case("cortex-m3", "7M")
+ .Cases("sc300", "cortex-m3", "7M")
.Cases("cortex-m4", "cortex-m7", "7EM")
- .Case("cortex-m0", "6M")
- .Cases("cortex-a53", "cortex-a57", "8A")
+ .Cases("sc000", "cortex-m0", "cortex-m0plus", "cortex-m1", "6M")
+ .Cases("cortex-a53", "cortex-a57", "cortex-a72", "8A")
.Default(nullptr);
}
- static const char *getCPUProfile(StringRef Name) {
- return llvm::StringSwitch<const char *>(Name)
- .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
- .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
- "A")
- .Cases("cortex-a53", "cortex-a57", "A")
- .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m7", "M")
- .Cases("cortex-r4", "cortex-r5", "R")
- .Default("");
+ const char *getCPUProfile(StringRef Name) const {
+ if(Name == "generic") {
+ auto subarch = getTriple().getSubArch();
+ switch (subarch) {
+ case llvm::Triple::SubArchType::ARMSubArch_v8_1a:
+ return "A";
+ default:
+ break;
+ }
+ }
+
+ unsigned CPUArch = llvm::ARMTargetParser::parseCPUArch(Name);
+ if (CPUArch == llvm::ARM::AK_INVALID)
+ return "";
+
+ StringRef ArchName = llvm::ARMTargetParser::getArchName(CPUArch);
+ switch(llvm::ARMTargetParser::parseArchProfile(ArchName)) {
+ case llvm::ARM::PK_A:
+ return "A";
+ case llvm::ARM::PK_R:
+ return "R";
+ case llvm::ARM::PK_M:
+ return "M";
+ default:
+ return "";
+ }
}
bool setCPU(const std::string &Name) override {
if (!getCPUDefineSuffix(Name))
@@ -4165,6 +4387,7 @@ public:
// We check both CPUArchVer and ArchName because when only triple is
// specified, the default CPU is arm1136j-s.
return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
+ ArchName.endswith("v8.1a") ||
ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
}
void getTargetDefines(const LangOptions &Opts,
@@ -4499,8 +4722,8 @@ class ARMleTargetInfo : public ARMTargetInfo {
public:
ARMleTargetInfo(const llvm::Triple &Triple)
: ARMTargetInfo(Triple, false) { }
- virtual void getTargetDefines(const LangOptions &Opts,
- MacroBuilder &Builder) const {
+ void getTargetDefines(const LangOptions &Opts,
+ MacroBuilder &Builder) const override {
Builder.defineMacro("__ARMEL__");
ARMTargetInfo::getTargetDefines(Opts, Builder);
}
@@ -4510,16 +4733,14 @@ class ARMbeTargetInfo : public ARMTargetInfo {
public:
ARMbeTargetInfo(const llvm::Triple &Triple)
: ARMTargetInfo(Triple, true) { }
- virtual void getTargetDefines(const LangOptions &Opts,
- MacroBuilder &Builder) const {
+ void getTargetDefines(const LangOptions &Opts,
+ MacroBuilder &Builder) const override {
Builder.defineMacro("__ARMEB__");
Builder.defineMacro("__ARM_BIG_ENDIAN");
ARMTargetInfo::getTargetDefines(Opts, Builder);
}
};
-} // end anonymous namespace.
-namespace {
class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
const llvm::Triple Triple;
public:
@@ -4585,10 +4806,7 @@ public:
WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
}
};
-}
-
-namespace {
class DarwinARMTargetInfo :
public DarwinTargetInfo<ARMleTargetInfo> {
protected:
@@ -4610,10 +4828,7 @@ public:
TheCXXABI.set(TargetCXXABI::iOS);
}
};
-} // end anonymous namespace.
-
-namespace {
class AArch64TargetInfo : public TargetInfo {
virtual void setDescriptionString() = 0;
static const TargetInfo::GCCRegAlias GCCRegAliases[];
@@ -4655,13 +4870,20 @@ public:
MaxAtomicInlineWidth = 128;
MaxAtomicPromoteWidth = 128;
- LongDoubleWidth = LongDoubleAlign = 128;
+ LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
LongDoubleFormat = &llvm::APFloat::IEEEquad;
// {} in inline assembly are neon specifiers, not assembly variant
// specifiers.
NoAsmVariants = true;
+ // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
+ // contributes to the alignment of the containing aggregate in the same way
+ // a plain (non bit-field) member of that type would, without exception for
+ // zero-sized or anonymous bit-fields."
+ UseBitFieldTypeAlignment = true;
+ UseZeroLengthBitfieldAlignment = true;
+
// AArch64 targets default to using the ARM C++ ABI.
TheCXXABI.set(TargetCXXABI::GenericAArch64);
}
@@ -4678,14 +4900,14 @@ public:
bool setCPU(const std::string &Name) override {
bool CPUKnown = llvm::StringSwitch<bool>(Name)
.Case("generic", true)
- .Cases("cortex-a53", "cortex-a57", true)
+ .Cases("cortex-a53", "cortex-a57", "cortex-a72", true)
.Case("cyclone", true)
.Default(false);
return CPUKnown;
}
- virtual void getTargetDefines(const LangOptions &Opts,
- MacroBuilder &Builder) const override {
+ void getTargetDefines(const LangOptions &Opts,
+ MacroBuilder &Builder) const override {
// Target identification.
Builder.defineMacro("__aarch64__");
@@ -4742,10 +4964,16 @@ public:
if (Crypto)
Builder.defineMacro("__ARM_FEATURE_CRYPTO");
+
+ // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
+ Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
+ Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
+ Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
+ Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
}
- virtual void getTargetBuiltins(const Builtin::Info *&Records,
- unsigned &NumRecords) const override {
+ void getTargetBuiltins(const Builtin::Info *&Records,
+ unsigned &NumRecords) const override {
Records = BuiltinInfo;
NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
}
@@ -4781,14 +5009,13 @@ public:
return TargetInfo::AArch64ABIBuiltinVaList;
}
- virtual void getGCCRegNames(const char *const *&Names,
- unsigned &NumNames) const override;
- virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
- unsigned &NumAliases) const override;
+ void getGCCRegNames(const char *const *&Names,
+ unsigned &NumNames) const override;
+ void getGCCRegAliases(const GCCRegAlias *&Aliases,
+ unsigned &NumAliases) const override;
- virtual bool
- validateAsmConstraint(const char *&Name,
- TargetInfo::ConstraintInfo &Info) const override {
+ bool validateAsmConstraint(const char *&Name,
+ TargetInfo::ConstraintInfo &Info) const override {
switch (*Name) {
default:
return false;
@@ -4963,9 +5190,7 @@ public:
AArch64TargetInfo::getTargetDefines(Opts, Builder);
}
};
-} // end anonymous namespace.
-namespace {
class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
protected:
void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
@@ -4988,7 +5213,7 @@ public:
WCharType = SignedInt;
UseSignedCharForObjCBool = false;
- LongDoubleWidth = LongDoubleAlign = 64;
+ LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
LongDoubleFormat = &llvm::APFloat::IEEEdouble;
TheCXXABI.set(TargetCXXABI::iOS64);
@@ -4998,9 +5223,7 @@ public:
return TargetInfo::CharPtrBuiltinVaList;
}
};
-} // end anonymous namespace
-namespace {
// Hexagon abstract base class
class HexagonTargetInfo : public TargetInfo {
static const Builtin::Info BuiltinInfo[];
@@ -5149,24 +5372,25 @@ const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
ALL_LANGUAGES },
#include "clang/Basic/BuiltinsHexagon.def"
};
-}
-
-namespace {
// Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
class SparcTargetInfo : public TargetInfo {
static const TargetInfo::GCCRegAlias GCCRegAliases[];
static const char * const GCCRegNames[];
bool SoftFloat;
public:
- SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
+ SparcTargetInfo(const llvm::Triple &Triple)
+ : TargetInfo(Triple), SoftFloat(false) {}
bool handleTargetFeatures(std::vector<std::string> &Features,
DiagnosticsEngine &Diags) override {
- SoftFloat = false;
- for (unsigned i = 0, e = Features.size(); i != e; ++i)
- if (Features[i] == "+soft-float")
- SoftFloat = true;
+ // The backend doesn't actually handle soft float yet, but in case someone
+ // is using the support for the front end continue to support it.
+ auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
+ if (Feature != Features.end()) {
+ SoftFloat = true;
+ Features.erase(Feature);
+ }
return true;
}
void getTargetDefines(const LangOptions &Opts,
@@ -5285,6 +5509,15 @@ public:
}
};
+// SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
+class SparcV8elTargetInfo : public SparcV8TargetInfo {
+ public:
+ SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) {
+ DescriptionString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64";
+ BigEndian = false;
+ }
+};
+
// SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
class SparcV9TargetInfo : public SparcTargetInfo {
public:
@@ -5339,9 +5572,6 @@ public:
}
};
-} // end anonymous namespace.
-
-namespace {
class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
public:
SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
@@ -5350,14 +5580,19 @@ public:
PtrDiffType = SignedInt;
}
};
-} // end anonymous namespace.
-namespace {
class SystemZTargetInfo : public TargetInfo {
+ static const Builtin::Info BuiltinInfo[];
static const char *const GCCRegNames[];
+ std::string CPU;
+ bool HasTransactionalExecution;
+ bool HasVector;
public:
- SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
+ SystemZTargetInfo(const llvm::Triple &Triple)
+ : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) {
+ IntMaxType = SignedLong;
+ Int64Type = SignedLong;
TLSSupported = true;
IntWidth = IntAlign = 32;
LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
@@ -5365,6 +5600,7 @@ public:
LongDoubleWidth = 128;
LongDoubleAlign = 64;
LongDoubleFormat = &llvm::APFloat::IEEEquad;
+ DefaultAlignForAttributeAligned = 64;
MinGlobalAlign = 16;
DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
@@ -5375,12 +5611,13 @@ public:
Builder.defineMacro("__s390x__");
Builder.defineMacro("__zarch__");
Builder.defineMacro("__LONG_DOUBLE_128__");
+ if (HasTransactionalExecution)
+ Builder.defineMacro("__HTM__");
}
void getTargetBuiltins(const Builtin::Info *&Records,
unsigned &NumRecords) const override {
- // FIXME: Implement.
- Records = nullptr;
- NumRecords = 0;
+ Records = BuiltinInfo;
+ NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin;
}
void getGCCRegNames(const char *const *&Names,
@@ -5401,16 +5638,62 @@ public:
return TargetInfo::SystemZBuiltinVaList;
}
bool setCPU(const std::string &Name) override {
+ CPU = Name;
bool CPUKnown = llvm::StringSwitch<bool>(Name)
.Case("z10", true)
.Case("z196", true)
.Case("zEC12", true)
+ .Case("z13", true)
.Default(false);
- // No need to store the CPU yet. There aren't any CPU-specific
- // macros to define.
return CPUKnown;
}
+ void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
+ if (CPU == "zEC12")
+ Features["transactional-execution"] = true;
+ if (CPU == "z13") {
+ Features["transactional-execution"] = true;
+ Features["vector"] = true;
+ }
+ }
+
+ bool handleTargetFeatures(std::vector<std::string> &Features,
+ DiagnosticsEngine &Diags) override {
+ HasTransactionalExecution = false;
+ for (unsigned i = 0, e = Features.size(); i != e; ++i) {
+ if (Features[i] == "+transactional-execution")
+ HasTransactionalExecution = true;
+ if (Features[i] == "+vector")
+ HasVector = true;
+ }
+ // If we use the vector ABI, vector types are 64-bit aligned.
+ if (HasVector) {
+ MaxVectorAlign = 64;
+ DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
+ "-v128:64-a:8:16-n32:64";
+ }
+ return true;
+ }
+
+ bool hasFeature(StringRef Feature) const override {
+ return llvm::StringSwitch<bool>(Feature)
+ .Case("systemz", true)
+ .Case("htm", HasTransactionalExecution)
+ .Case("vx", HasVector)
+ .Default(false);
+ }
+
+ StringRef getABI() const override {
+ if (HasVector)
+ return "vector";
+ return "";
+ }
+};
+
+const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS) \
+ { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
+#include "clang/Basic/BuiltinsSystemZ.def"
};
const char *const SystemZTargetInfo::GCCRegNames[] = {
@@ -5454,9 +5737,7 @@ validateAsmConstraint(const char *&Name,
return true;
}
}
-}
-namespace {
class MSP430TargetInfo : public TargetInfo {
static const char * const GCCRegNames[];
public:
@@ -5531,9 +5812,6 @@ namespace {
Names = GCCRegNames;
NumNames = llvm::array_lengthof(GCCRegNames);
}
-}
-
-namespace {
// LLVM and Clang cannot be used directly to output native binaries for
// target, but is used to compile C code to llvm bitcode with correct
@@ -5611,9 +5889,7 @@ namespace {
void getGCCRegAliases(const GCCRegAlias *&Aliases,
unsigned &NumAliases) const override {}
};
-}
-namespace {
class MipsTargetInfoBase : public TargetInfo {
virtual void setDescriptionString() = 0;
@@ -5652,6 +5928,10 @@ public:
return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
}
+ bool isNan2008() const override {
+ return IsNan2008;
+ }
+
StringRef getABI() const override { return ABI; }
bool setCPU(const std::string &Name) override {
bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
@@ -5665,23 +5945,19 @@ public:
.Case("mips5", true)
.Case("mips32", IsMips32)
.Case("mips32r2", IsMips32)
+ .Case("mips32r3", IsMips32)
+ .Case("mips32r5", IsMips32)
.Case("mips32r6", IsMips32)
.Case("mips64", true)
.Case("mips64r2", true)
+ .Case("mips64r3", true)
+ .Case("mips64r5", true)
.Case("mips64r6", true)
.Case("octeon", true)
.Default(false);
}
const std::string& getCPU() const { return CPU; }
void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
- // The backend enables certain ABI's by default according to the
- // architecture.
- // Disable both possible defaults so that we don't end up with multiple
- // ABI's selected and trigger an assertion.
- Features["o32"] = false;
- Features["n64"] = false;
-
- Features[ABI] = true;
if (CPU == "octeon")
Features["mips64r2"] = Features["cnmips"] = true;
else
@@ -5818,7 +6094,28 @@ public:
case 'R': // An address that can be used in a non-macro load or store
Info.setAllowsMemory();
return true;
+ case 'Z':
+ if (Name[1] == 'C') { // An address usable by ll, and sc.
+ Info.setAllowsMemory();
+ Name++; // Skip over 'Z'.
+ return true;
+ }
+ return false;
+ }
+ }
+
+ std::string convertConstraint(const char *&Constraint) const override {
+ std::string R;
+ switch (*Constraint) {
+ case 'Z': // Two-character constraint; add "^" hint for later parsing.
+ if (Constraint[1] == 'C') {
+ R = std::string("^") + std::string(Constraint, 2);
+ Constraint++;
+ return R;
+ }
+ break;
}
+ return TargetInfo::convertConstraint(Constraint);
}
const char *getClobbers() const override {
@@ -5882,12 +6179,6 @@ public:
IsNan2008 = false;
}
- // Remove front-end specific options.
- std::vector<std::string>::iterator it =
- std::find(Features.begin(), Features.end(), "+soft-float");
- if (it != Features.end())
- Features.erase(it);
-
setDescriptionString();
return true;
@@ -5938,6 +6229,10 @@ public:
Builder.defineMacro("__mips_isa_rev", "1");
else if (CPUStr == "mips32r2")
Builder.defineMacro("__mips_isa_rev", "2");
+ else if (CPUStr == "mips32r3")
+ Builder.defineMacro("__mips_isa_rev", "3");
+ else if (CPUStr == "mips32r5")
+ Builder.defineMacro("__mips_isa_rev", "5");
else if (CPUStr == "mips32r6")
Builder.defineMacro("__mips_isa_rev", "6");
@@ -6087,6 +6382,10 @@ public:
Builder.defineMacro("__mips_isa_rev", "1");
else if (CPUStr == "mips64r2")
Builder.defineMacro("__mips_isa_rev", "2");
+ else if (CPUStr == "mips64r3")
+ Builder.defineMacro("__mips_isa_rev", "3");
+ else if (CPUStr == "mips64r5")
+ Builder.defineMacro("__mips_isa_rev", "5");
else if (CPUStr == "mips64r6")
Builder.defineMacro("__mips_isa_rev", "6");
@@ -6185,9 +6484,7 @@ public:
Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
}
};
-} // end anonymous namespace.
-namespace {
class PNaClTargetInfo : public TargetInfo {
public:
PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
@@ -6252,9 +6549,7 @@ void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
Aliases = nullptr;
NumAliases = 0;
}
-} // end anonymous namespace.
-namespace {
class Le64TargetInfo : public TargetInfo {
static const Builtin::Info BuiltinInfo[];
@@ -6359,6 +6654,15 @@ namespace {
BuiltinVaListKind getBuiltinVaListKind() const override {
return TargetInfo::VoidPtrBuiltinVaList;
}
+
+ CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
+ return (CC == CC_SpirFunction ||
+ CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning;
+ }
+
+ CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
+ return CC_SpirFunction;
+ }
};
@@ -6392,9 +6696,7 @@ namespace {
DefineStd(Builder, "SPIR64", Opts);
}
};
-}
-namespace {
class XCoreTargetInfo : public TargetInfo {
static const Builtin::Info BuiltinInfo[];
public:
@@ -6460,6 +6762,30 @@ const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
};
} // end anonymous namespace.
+namespace {
+// x86_32 Android target
+class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
+public:
+ AndroidX86_32TargetInfo(const llvm::Triple &Triple)
+ : LinuxTargetInfo<X86_32TargetInfo>(Triple) {
+ SuitableAlign = 32;
+ LongDoubleWidth = 64;
+ LongDoubleFormat = &llvm::APFloat::IEEEdouble;
+ }
+};
+} // end anonymous namespace
+
+namespace {
+// x86_64 Android target
+class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
+public:
+ AndroidX86_64TargetInfo(const llvm::Triple &Triple)
+ : LinuxTargetInfo<X86_64TargetInfo>(Triple) {
+ LongDoubleFormat = &llvm::APFloat::IEEEquad;
+ }
+};
+} // end anonymous namespace
+
//===----------------------------------------------------------------------===//
// Driver code
@@ -6629,10 +6955,10 @@ static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
case llvm::Triple::le32:
switch (os) {
- case llvm::Triple::NaCl:
- return new NaClTargetInfo<PNaClTargetInfo>(Triple);
- default:
- return nullptr;
+ case llvm::Triple::NaCl:
+ return new NaClTargetInfo<PNaClTargetInfo>(Triple);
+ default:
+ return nullptr;
}
case llvm::Triple::le64:
@@ -6707,6 +7033,21 @@ static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
return new SparcV8TargetInfo(Triple);
}
+ // The 'sparcel' architecture copies all the above cases except for Solaris.
+ case llvm::Triple::sparcel:
+ switch (os) {
+ case llvm::Triple::Linux:
+ return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple);
+ case llvm::Triple::NetBSD:
+ return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple);
+ case llvm::Triple::OpenBSD:
+ return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple);
+ case llvm::Triple::RTEMS:
+ return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple);
+ default:
+ return new SparcV8elTargetInfo(Triple);
+ }
+
case llvm::Triple::sparcv9:
switch (os) {
case llvm::Triple::Linux:
@@ -6739,8 +7080,14 @@ static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
return new DarwinI386TargetInfo(Triple);
switch (os) {
- case llvm::Triple::Linux:
- return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
+ case llvm::Triple::Linux: {
+ switch (Triple.getEnvironment()) {
+ default:
+ return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
+ case llvm::Triple::Android:
+ return new AndroidX86_32TargetInfo(Triple);
+ }
+ }
case llvm::Triple::DragonFly:
return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
case llvm::Triple::NetBSD:
@@ -6785,8 +7132,16 @@ static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
return new DarwinX86_64TargetInfo(Triple);
switch (os) {
- case llvm::Triple::Linux:
- return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
+ case llvm::Triple::CloudABI:
+ return new CloudABITargetInfo<X86_64TargetInfo>(Triple);
+ case llvm::Triple::Linux: {
+ switch (Triple.getEnvironment()) {
+ default:
+ return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
+ case llvm::Triple::Android:
+ return new AndroidX86_64TargetInfo(Triple);
+ }
+ }
case llvm::Triple::DragonFly:
return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
case llvm::Triple::NetBSD:
@@ -6813,22 +7168,24 @@ static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
}
case llvm::Triple::NaCl:
return new NaClTargetInfo<X86_64TargetInfo>(Triple);
+ case llvm::Triple::PS4:
+ return new PS4OSTargetInfo<X86_64TargetInfo>(Triple);
default:
return new X86_64TargetInfo(Triple);
}
- case llvm::Triple::spir: {
- if (Triple.getOS() != llvm::Triple::UnknownOS ||
- Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
- return nullptr;
- return new SPIR32TargetInfo(Triple);
- }
- case llvm::Triple::spir64: {
- if (Triple.getOS() != llvm::Triple::UnknownOS ||
- Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
- return nullptr;
- return new SPIR64TargetInfo(Triple);
- }
+ case llvm::Triple::spir: {
+ if (Triple.getOS() != llvm::Triple::UnknownOS ||
+ Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
+ return nullptr;
+ return new SPIR32TargetInfo(Triple);
+ }
+ case llvm::Triple::spir64: {
+ if (Triple.getOS() != llvm::Triple::UnknownOS ||
+ Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
+ return nullptr;
+ return new SPIR64TargetInfo(Triple);
+ }
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-01 14:12:27 +0000