diff options
Diffstat (limited to 'contrib/llvm/lib/Target/X86/X86InstrControl.td')
| -rw-r--r-- | contrib/llvm/lib/Target/X86/X86InstrControl.td | 262 |
1 files changed, 145 insertions, 117 deletions
diff --git a/contrib/llvm/lib/Target/X86/X86InstrControl.td b/contrib/llvm/lib/Target/X86/X86InstrControl.td index 7932686ebc87..650bce74dcf2 100644 --- a/contrib/llvm/lib/Target/X86/X86InstrControl.td +++ b/contrib/llvm/lib/Target/X86/X86InstrControl.td @@ -22,47 +22,37 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in { def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops), - "ret{l}", [], IIC_RET>, OpSize32, - Requires<[Not64BitMode]>; + "ret{l}", []>, OpSize32, Requires<[Not64BitMode]>; def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops), - "ret{q}", [], IIC_RET>, OpSize32, - Requires<[In64BitMode]>; + "ret{q}", []>, OpSize32, Requires<[In64BitMode]>; def RETW : I <0xC3, RawFrm, (outs), (ins), - "ret{w}", - [], IIC_RET>, OpSize16; + "ret{w}", []>, OpSize16; def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), - "ret{l}\t$amt", - [], IIC_RET_IMM>, OpSize32, - Requires<[Not64BitMode]>; + "ret{l}\t$amt", []>, OpSize32, Requires<[Not64BitMode]>; def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops), - "ret{q}\t$amt", - [], IIC_RET_IMM>, OpSize32, - Requires<[In64BitMode]>; + "ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>; def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), - "ret{w}\t$amt", - [], IIC_RET_IMM>, OpSize16; + "ret{w}\t$amt", []>, OpSize16; def LRETL : I <0xCB, RawFrm, (outs), (ins), - "{l}ret{l|f}", [], IIC_RET>, OpSize32; + "{l}ret{l|f}", []>, OpSize32; def LRETQ : RI <0xCB, RawFrm, (outs), (ins), - "{l}ret{|f}q", [], IIC_RET>, Requires<[In64BitMode]>; + "{l}ret{|f}q", []>, Requires<[In64BitMode]>; def LRETW : I <0xCB, RawFrm, (outs), (ins), - "{l}ret{w|f}", [], IIC_RET>, OpSize16; + "{l}ret{w|f}", []>, OpSize16; def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), - "{l}ret{l|f}\t$amt", [], IIC_RET>, OpSize32; + "{l}ret{l|f}\t$amt", []>, OpSize32; def LRETIQ : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt), - "{l}ret{|f}q\t$amt", [], IIC_RET>, Requires<[In64BitMode]>; + "{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>; def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt), - "{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize16; + "{l}ret{w|f}\t$amt", []>, OpSize16; // The machine return from interrupt instruction, but sometimes we need to // perform a post-epilogue stack adjustment. Codegen emits the pseudo form // which expands to include an SP adjustment if necessary. - def IRET16 : I <0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, + def IRET16 : I <0xcf, RawFrm, (outs), (ins), "iret{w}", []>, OpSize16; - def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], - IIC_IRET>, OpSize32; - def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", [], - IIC_IRET>, Requires<[In64BitMode]>; + def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>, OpSize32; + def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>; let isCodeGenOnly = 1 in def IRET : PseudoI<(outs), (ins i32imm:$adj), [(X86iret timm:$adj)]>; def RET : PseudoI<(outs), (ins i32imm:$adj, variable_ops), [(X86retflag timm:$adj)]>; @@ -71,12 +61,12 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1, // Unconditional branches. let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in { def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst), - "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>; + "jmp\t$dst", [(br bb:$dst)]>; let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget16:$dst), - "jmp\t$dst", [], IIC_JMP_REL>, OpSize16; + "jmp\t$dst", []>, OpSize16; def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget32:$dst), - "jmp\t$dst", [], IIC_JMP_REL>, OpSize32; + "jmp\t$dst", []>, OpSize32; } } @@ -84,12 +74,12 @@ let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in { let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in { multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> { def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, - [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>; + [(X86brcond bb:$dst, Cond, EFLAGS)]>; let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in { def _2 : Ii16PCRel<opc4, RawFrm, (outs), (ins brtarget16:$dst), asm, - [], IIC_Jcc>, OpSize16, TB; + []>, OpSize16, TB; def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget32:$dst), asm, - [], IIC_Jcc>, TB, OpSize32; + []>, TB, OpSize32; } } } @@ -118,69 +108,91 @@ let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in // jecxz. let Uses = [CX] in def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), - "jcxz\t$dst", [], IIC_JCXZ>, AdSize16, - Requires<[Not64BitMode]>; + "jcxz\t$dst", []>, AdSize16, Requires<[Not64BitMode]>; let Uses = [ECX] in def JECXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), - "jecxz\t$dst", [], IIC_JCXZ>, AdSize32; + "jecxz\t$dst", []>, AdSize32; let Uses = [RCX] in def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins brtarget8:$dst), - "jrcxz\t$dst", [], IIC_JCXZ>, AdSize64, - Requires<[In64BitMode]>; + "jrcxz\t$dst", []>, AdSize64, Requires<[In64BitMode]>; } // Indirect branches let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst", - [(brind GR16:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>, - OpSize16, Sched<[WriteJump]>; + [(brind GR16:$dst)]>, Requires<[Not64BitMode]>, + OpSize16, Sched<[WriteJump]>; def JMP16m : I<0xFF, MRM4m, (outs), (ins i16mem:$dst), "jmp{w}\t{*}$dst", - [(brind (loadi16 addr:$dst))], IIC_JMP_MEM>, - Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>; + [(brind (loadi16 addr:$dst))]>, Requires<[Not64BitMode]>, + OpSize16, Sched<[WriteJumpLd]>; def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst", - [(brind GR32:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>, - OpSize32, Sched<[WriteJump]>; + [(brind GR32:$dst)]>, Requires<[Not64BitMode]>, + OpSize32, Sched<[WriteJump]>; def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst", - [(brind (loadi32 addr:$dst))], IIC_JMP_MEM>, - Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>; + [(brind (loadi32 addr:$dst))]>, Requires<[Not64BitMode]>, + OpSize32, Sched<[WriteJumpLd]>; def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst", - [(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>, - Sched<[WriteJump]>; + [(brind GR64:$dst)]>, Requires<[In64BitMode]>, + Sched<[WriteJump]>; def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst", - [(brind (loadi64 addr:$dst))], IIC_JMP_MEM>, - Requires<[In64BitMode]>, Sched<[WriteJumpLd]>; + [(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>, + Sched<[WriteJumpLd]>; + + // Non-tracking jumps for IBT, use with caution. + let isCodeGenOnly = 1 in { + def JMP16r_NT : I<0xFF, MRM4r, (outs), (ins GR16 : $dst), "jmp{w}\t{*}$dst", + [(X86NoTrackBrind GR16 : $dst)]>, Requires<[Not64BitMode]>, + OpSize16, Sched<[WriteJump]>, NOTRACK; + + def JMP16m_NT : I<0xFF, MRM4m, (outs), (ins i16mem : $dst), "jmp{w}\t{*}$dst", + [(X86NoTrackBrind (loadi16 addr : $dst))]>, + Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>, + NOTRACK; + + def JMP32r_NT : I<0xFF, MRM4r, (outs), (ins GR32 : $dst), "jmp{l}\t{*}$dst", + [(X86NoTrackBrind GR32 : $dst)]>, Requires<[Not64BitMode]>, + OpSize32, Sched<[WriteJump]>, NOTRACK; + def JMP32m_NT : I<0xFF, MRM4m, (outs), (ins i32mem : $dst), "jmp{l}\t{*}$dst", + [(X86NoTrackBrind (loadi32 addr : $dst))]>, + Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>, + NOTRACK; + + def JMP64r_NT : I<0xFF, MRM4r, (outs), (ins GR64 : $dst), "jmp{q}\t{*}$dst", + [(X86NoTrackBrind GR64 : $dst)]>, Requires<[In64BitMode]>, + Sched<[WriteJump]>, NOTRACK; + def JMP64m_NT : I<0xFF, MRM4m, (outs), (ins i64mem : $dst), "jmp{q}\t{*}$dst", + [(X86NoTrackBrind(loadi64 addr : $dst))]>, + Requires<[In64BitMode]>, Sched<[WriteJumpLd]>, NOTRACK; + } - let Predicates = [Not64BitMode] in { + let Predicates = [Not64BitMode], AsmVariantName = "att" in { def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs), (ins i16imm:$off, i16imm:$seg), - "ljmp{w}\t$seg, $off", [], - IIC_JMP_FAR_PTR>, OpSize16, Sched<[WriteJump]>; + "ljmp{w}\t$seg, $off", []>, + OpSize16, Sched<[WriteJump]>; def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs), (ins i32imm:$off, i16imm:$seg), - "ljmp{l}\t$seg, $off", [], - IIC_JMP_FAR_PTR>, OpSize32, Sched<[WriteJump]>; + "ljmp{l}\t$seg, $off", []>, + OpSize32, Sched<[WriteJump]>; } - def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst), - "ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>, - Sched<[WriteJump]>; - - def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst), - "ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize16, - Sched<[WriteJumpLd]>; - def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst), - "{l}jmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize32, - Sched<[WriteJumpLd]>; + def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaquemem:$dst), + "ljmp{q}\t{*}$dst", []>, Sched<[WriteJump]>, Requires<[In64BitMode]>; + + let AsmVariantName = "att" in + def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst), + "ljmp{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>; + def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst), + "{l}jmp{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>; } - // Loop instructions let SchedRW = [WriteJump] in { -def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", [], IIC_LOOP>; -def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", [], IIC_LOOPE>; -def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", [], IIC_LOOPNE>; +def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins brtarget8:$dst), "loop\t$dst", []>; +def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins brtarget8:$dst), "loope\t$dst", []>; +def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins brtarget8:$dst), "loopne\t$dst", []>; } //===----------------------------------------------------------------------===// @@ -194,48 +206,62 @@ let isCall = 1 in let Uses = [ESP, SSP] in { def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm, (outs), (ins i32imm_pcrel:$dst), - "call{l}\t$dst", [], IIC_CALL_RI>, OpSize32, + "call{l}\t$dst", []>, OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>; let hasSideEffects = 0 in def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm, (outs), (ins i16imm_pcrel:$dst), - "call{w}\t$dst", [], IIC_CALL_RI>, OpSize16, + "call{w}\t$dst", []>, OpSize16, Sched<[WriteJump]>; def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst), - "call{w}\t{*}$dst", [(X86call GR16:$dst)], IIC_CALL_RI>, + "call{w}\t{*}$dst", [(X86call GR16:$dst)]>, OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>; def CALL16m : I<0xFF, MRM2m, (outs), (ins i16mem:$dst), - "call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))], - IIC_CALL_MEM>, OpSize16, - Requires<[Not64BitMode,FavorMemIndirectCall]>, - Sched<[WriteJumpLd]>; + "call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))]>, + OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>, + Sched<[WriteJumpLd]>; def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst), - "call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>, - OpSize32, Requires<[Not64BitMode,NotUseRetpoline]>, - Sched<[WriteJump]>; + "call{l}\t{*}$dst", [(X86call GR32:$dst)]>, OpSize32, + Requires<[Not64BitMode,NotUseRetpoline]>, Sched<[WriteJump]>; def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst), - "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))], - IIC_CALL_MEM>, OpSize32, - Requires<[Not64BitMode,FavorMemIndirectCall,NotUseRetpoline]>, - Sched<[WriteJumpLd]>; + "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))]>, + OpSize32, + Requires<[Not64BitMode,FavorMemIndirectCall,NotUseRetpoline]>, + Sched<[WriteJumpLd]>; + + // Non-tracking calls for IBT, use with caution. + let isCodeGenOnly = 1 in { + def CALL16r_NT : I<0xFF, MRM2r, (outs), (ins GR16 : $dst), + "call{w}\t{*}$dst",[(X86NoTrackCall GR16 : $dst)]>, + OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK; + def CALL16m_NT : I<0xFF, MRM2m, (outs), (ins i16mem : $dst), + "call{w}\t{*}$dst",[(X86NoTrackCall(loadi16 addr : $dst))]>, + OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>, + Sched<[WriteJumpLd]>, NOTRACK; + def CALL32r_NT : I<0xFF, MRM2r, (outs), (ins GR32 : $dst), + "call{l}\t{*}$dst",[(X86NoTrackCall GR32 : $dst)]>, + OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK; + def CALL32m_NT : I<0xFF, MRM2m, (outs), (ins i32mem : $dst), + "call{l}\t{*}$dst",[(X86NoTrackCall(loadi32 addr : $dst))]>, + OpSize32, Requires<[Not64BitMode,FavorMemIndirectCall]>, + Sched<[WriteJumpLd]>, NOTRACK; + } - let Predicates = [Not64BitMode] in { + let Predicates = [Not64BitMode], AsmVariantName = "att" in { def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs), (ins i16imm:$off, i16imm:$seg), - "lcall{w}\t$seg, $off", [], - IIC_CALL_FAR_PTR>, OpSize16, Sched<[WriteJump]>; + "lcall{w}\t$seg, $off", []>, + OpSize16, Sched<[WriteJump]>; def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs), (ins i32imm:$off, i16imm:$seg), - "lcall{l}\t$seg, $off", [], - IIC_CALL_FAR_PTR>, OpSize32, Sched<[WriteJump]>; + "lcall{l}\t$seg, $off", []>, + OpSize32, Sched<[WriteJump]>; } - def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst), - "lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize16, - Sched<[WriteJumpLd]>; - def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst), - "{l}call{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize32, - Sched<[WriteJumpLd]>; + def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst), + "lcall{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>; + def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst), + "{l}call{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>; } @@ -254,15 +280,13 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, // FIXME: The should be pseudo instructions that are lowered when going to // mcinst. def TAILJMPd : Ii32PCRel<0xE9, RawFrm, (outs), - (ins i32imm_pcrel:$dst), - "jmp\t$dst", - [], IIC_JMP_REL>; + (ins i32imm_pcrel:$dst), "jmp\t$dst", []>; def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), - "", [], IIC_JMP_REG>; // FIXME: Remove encoding when JIT is dead. + "", []>; // FIXME: Remove encoding when JIT is dead. let mayLoad = 1 in def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst), - "jmp{l}\t{*}$dst", [], IIC_JMP_MEM>; + "jmp{l}\t{*}$dst", []>; } // Conditional tail calls are similar to the above, but they are branches @@ -275,9 +299,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1, // This gets substituted to a conditional jump instruction in MC lowering. def TAILJMPd_CC : Ii32PCRel<0x80, RawFrm, (outs), - (ins i32imm_pcrel:$dst, i32imm:$cond), - "", - [], IIC_JMP_REL>; + (ins i32imm_pcrel:$dst, i32imm:$cond), "", []>; } @@ -294,25 +316,33 @@ let isCall = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in { // the 32-bit pcrel field that we have. def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm, (outs), (ins i64i32imm_pcrel:$dst), - "call{q}\t$dst", [], IIC_CALL_RI>, OpSize32, + "call{q}\t$dst", []>, OpSize32, Requires<[In64BitMode]>; def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst), - "call{q}\t{*}$dst", [(X86call GR64:$dst)], - IIC_CALL_RI>, + "call{q}\t{*}$dst", [(X86call GR64:$dst)]>, Requires<[In64BitMode,NotUseRetpoline]>; def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst), - "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))], - IIC_CALL_MEM>, + "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>, Requires<[In64BitMode,FavorMemIndirectCall, NotUseRetpoline]>; - def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst), - "lcall{q}\t{*}$dst", [], IIC_CALL_FAR_MEM>; + // Non-tracking calls for IBT, use with caution. + let isCodeGenOnly = 1 in { + def CALL64r_NT : I<0xFF, MRM2r, (outs), (ins GR64 : $dst), + "call{q}\t{*}$dst",[(X86NoTrackCall GR64 : $dst)]>, + Requires<[In64BitMode]>, NOTRACK; + def CALL64m_NT : I<0xFF, MRM2m, (outs), (ins i64mem : $dst), + "call{q}\t{*}$dst", + [(X86NoTrackCall(loadi64 addr : $dst))]>, + Requires<[In64BitMode,FavorMemIndirectCall]>, NOTRACK; + } + + def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaquemem:$dst), + "lcall{q}\t{*}$dst", []>; } let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, - isCodeGenOnly = 1, Uses = [RSP, SSP], usesCustomInserter = 1, - SchedRW = [WriteJump] in { + isCodeGenOnly = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in { def TCRETURNdi64 : PseudoI<(outs), (ins i64i32imm_pcrel:$dst, i32imm:$offset), []>; @@ -323,23 +353,23 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, (ins i64mem_TC:$dst, i32imm:$offset), []>, NotMemoryFoldable; def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs), (ins i64i32imm_pcrel:$dst), - "jmp\t$dst", [], IIC_JMP_REL>; + "jmp\t$dst", []>; def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), - "jmp{q}\t{*}$dst", [], IIC_JMP_MEM>; + "jmp{q}\t{*}$dst", []>; let mayLoad = 1 in def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst), - "jmp{q}\t{*}$dst", [], IIC_JMP_MEM>; + "jmp{q}\t{*}$dst", []>; // Win64 wants indirect jumps leaving the function to have a REX_W prefix. let hasREX_WPrefix = 1 in { def TAILJMPr64_REX : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst), - "rex64 jmp{q}\t{*}$dst", [], IIC_JMP_MEM>; + "rex64 jmp{q}\t{*}$dst", []>; let mayLoad = 1 in def TAILJMPm64_REX : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst), - "rex64 jmp{q}\t{*}$dst", [], IIC_JMP_MEM>; + "rex64 jmp{q}\t{*}$dst", []>; } } @@ -375,7 +405,5 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1, // This gets substituted to a conditional jump instruction in MC lowering. def TAILJMPd64_CC : Ii32PCRel<0x80, RawFrm, (outs), - (ins i64i32imm_pcrel:$dst, i32imm:$cond), - "", - [], IIC_JMP_REL>; + (ins i64i32imm_pcrel:$dst, i32imm:$cond), "", []>; } |