diff options
Diffstat (limited to 'contrib/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp')
-rw-r--r-- | contrib/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp | 101 |
1 files changed, 53 insertions, 48 deletions
diff --git a/contrib/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp b/contrib/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp index 53a6550acdd5..311a8d677eea 100644 --- a/contrib/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ b/contrib/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -16,7 +16,6 @@ #include "InstPrinter/X86IntelInstPrinter.h" #include "X86MCAsmInfo.h" #include "llvm/ADT/Triple.h" -#include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrAnalysis.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" @@ -66,12 +65,59 @@ unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) { return DWARFFlavour::X86_32_Generic; } -void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) { +void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) { // FIXME: TableGen these. - for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) { + for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { unsigned SEH = MRI->getEncodingValue(Reg); MRI->mapLLVMRegToSEHReg(Reg, SEH); } + + // These CodeView registers are numbered sequentially starting at value 1. + static const MCPhysReg LowCVRegs[] = { + X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, + X86::DH, X86::BH, X86::AX, X86::CX, X86::DX, X86::BX, + X86::SP, X86::BP, X86::SI, X86::DI, X86::EAX, X86::ECX, + X86::EDX, X86::EBX, X86::ESP, X86::EBP, X86::ESI, X86::EDI, + }; + unsigned CVLowRegStart = 1; + for (unsigned I = 0; I < array_lengthof(LowCVRegs); ++I) + MRI->mapLLVMRegToCVReg(LowCVRegs[I], I + CVLowRegStart); + + MRI->mapLLVMRegToCVReg(X86::EFLAGS, 34); + + // The x87 registers start at 128 and are numbered sequentially. + unsigned FP0Start = 128; + for (unsigned I = 0; I < 8; ++I) + MRI->mapLLVMRegToCVReg(X86::FP0 + I, FP0Start + I); + + // The low 8 XMM registers start at 154 and are numbered sequentially. + unsigned CVXMM0Start = 154; + for (unsigned I = 0; I < 8; ++I) + MRI->mapLLVMRegToCVReg(X86::XMM0 + I, CVXMM0Start + I); + + // The high 8 XMM registers start at 252 and are numbered sequentially. + unsigned CVXMM8Start = 252; + for (unsigned I = 0; I < 8; ++I) + MRI->mapLLVMRegToCVReg(X86::XMM8 + I, CVXMM8Start + I); + + // FIXME: XMM16 and above from AVX512 not yet documented. + + // AMD64 registers start at 324 and count up. + unsigned CVX64RegStart = 324; + static const MCPhysReg CVX64Regs[] = { + X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::RAX, X86::RBX, + X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBP, X86::RSP, + X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, + X86::R14, X86::R15, X86::R8B, X86::R9B, X86::R10B, X86::R11B, + X86::R12B, X86::R13B, X86::R14B, X86::R15B, X86::R8W, X86::R9W, + X86::R10W, X86::R11W, X86::R12W, X86::R13W, X86::R14W, X86::R15W, + X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R13D, + X86::R14D, X86::R15D, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, + X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, + X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, + }; + for (unsigned I = 0; I < array_lengthof(CVX64Regs); ++I) + MRI->mapLLVMRegToCVReg(CVX64Regs[I], CVX64RegStart + I); } MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, @@ -105,7 +151,7 @@ static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) { MCRegisterInfo *X = new MCRegisterInfo(); InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false), X86_MC::getDwarfRegFlavour(TT, true), RA); - X86_MC::InitLLVM2SEHRegisterMapping(X); + X86_MC::initLLVMToSEHAndCVRegMapping(X); return X; } @@ -152,53 +198,16 @@ static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static MCCodeGenInfo *createX86MCCodeGenInfo(const Triple &TT, Reloc::Model RM, - CodeModel::Model CM, - CodeGenOpt::Level OL) { - MCCodeGenInfo *X = new MCCodeGenInfo(); - +static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM, + CodeModel::Model &CM) { bool is64Bit = TT.getArch() == Triple::x86_64; - if (RM == Reloc::Default) { - // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode. - // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we - // use static relocation model by default. - if (TT.isOSDarwin()) { - if (is64Bit) - RM = Reloc::PIC_; - else - RM = Reloc::DynamicNoPIC; - } else if (TT.isOSWindows() && is64Bit) - RM = Reloc::PIC_; - else - RM = Reloc::Static; - } - - // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC - // is defined as a model for code which may be used in static or dynamic - // executables but not necessarily a shared library. On X86-32 we just - // compile in -static mode, in x86-64 we use PIC. - if (RM == Reloc::DynamicNoPIC) { - if (is64Bit) - RM = Reloc::PIC_; - else if (!TT.isOSDarwin()) - RM = Reloc::Static; - } - - // If we are on Darwin, disallow static relocation model in X86-64 mode, since - // the Mach-O file format doesn't support it. - if (RM == Reloc::Static && TT.isOSDarwin() && is64Bit) - RM = Reloc::PIC_; - // For static codegen, if we're not already set, use Small codegen. if (CM == CodeModel::Default) CM = CodeModel::Small; else if (CM == CodeModel::JITDefault) // 64-bit JIT places everything in the same buffer except external funcs. CM = is64Bit ? CodeModel::Large : CodeModel::Small; - - X->initMCCodeGenInfo(RM, CM, OL); - return X; } static MCInstPrinter *createX86MCInstPrinter(const Triple &T, @@ -215,10 +224,6 @@ static MCInstPrinter *createX86MCInstPrinter(const Triple &T, static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple, MCContext &Ctx) { - if (TheTriple.isOSBinFormatMachO() && TheTriple.getArch() == Triple::x86_64) - return createX86_64MachORelocationInfo(Ctx); - else if (TheTriple.isOSBinFormatELF()) - return createX86_64ELFRelocationInfo(Ctx); // Default to the stock relocation info. return llvm::createMCRelocationInfo(TheTriple, Ctx); } @@ -234,7 +239,7 @@ extern "C" void LLVMInitializeX86TargetMC() { RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo); // Register the MC codegen info. - RegisterMCCodeGenInfoFn Y(*T, createX86MCCodeGenInfo); + RegisterMCAdjustCodeGenOptsFn Y(*T, adjustCodeGenOpts); // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo); |