diff options
Diffstat (limited to 'contrib/llvm/lib/Target/SystemZ/MCTargetDesc')
8 files changed, 128 insertions, 146 deletions
diff --git a/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp b/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp index 26a8faeea10b..6e7268de55c1 100644 --- a/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp +++ b/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp @@ -43,37 +43,27 @@ public: : OSABI(osABI) {} // Override MCAsmBackend - virtual unsigned getNumFixupKinds() const LLVM_OVERRIDE { + unsigned getNumFixupKinds() const override { return SystemZ::NumTargetFixupKinds; } - virtual const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const - LLVM_OVERRIDE; - virtual void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, - uint64_t Value) const LLVM_OVERRIDE; - virtual bool mayNeedRelaxation(const MCInst &Inst) const LLVM_OVERRIDE { + const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override; + void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, + uint64_t Value, bool IsPCRel) const override; + bool mayNeedRelaxation(const MCInst &Inst) const override { return false; } - virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, - uint64_t Value, - const MCRelaxableFragment *Fragment, - const MCAsmLayout &Layout) const - LLVM_OVERRIDE { + bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, + const MCRelaxableFragment *Fragment, + const MCAsmLayout &Layout) const override { return false; } - virtual void relaxInstruction(const MCInst &Inst, - MCInst &Res) const LLVM_OVERRIDE { + void relaxInstruction(const MCInst &Inst, MCInst &Res) const override { llvm_unreachable("SystemZ does do not have assembler relaxation"); } - virtual bool writeNopData(uint64_t Count, - MCObjectWriter *OW) const LLVM_OVERRIDE; - virtual MCObjectWriter *createObjectWriter(raw_ostream &OS) const - LLVM_OVERRIDE { + bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override; + MCObjectWriter *createObjectWriter(raw_ostream &OS) const override { return createSystemZObjectWriter(OS, OSABI); } - virtual bool doesSectionRequireSymbols(const MCSection &Section) const - LLVM_OVERRIDE { - return false; - } }; } // end anonymous namespace @@ -95,7 +85,8 @@ SystemZMCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { } void SystemZMCAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, - unsigned DataSize, uint64_t Value) const { + unsigned DataSize, uint64_t Value, + bool IsPCRel) const { MCFixupKind Kind = Fixup.getKind(); unsigned Offset = Fixup.getOffset(); unsigned Size = (getFixupKindInfo(Kind).TargetSize + 7) / 8; diff --git a/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp b/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp index 965c41e2d151..c46a36bdd23d 100644 --- a/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp +++ b/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp @@ -19,8 +19,6 @@ SystemZMCAsmInfo::SystemZMCAsmInfo(StringRef TT) { IsLittleEndian = false; CommentString = "#"; - GlobalPrefix = ""; - PrivateGlobalPrefix = ".L"; ZeroDirective = "\t.space\t"; Data64bitsDirective = "\t.quad\t"; UsesELFSectionDirectiveForBSS = true; diff --git a/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h b/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h index b9ac92a6934f..1de97afbfe0a 100644 --- a/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h +++ b/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h @@ -21,10 +21,9 @@ public: explicit SystemZMCAsmInfo(StringRef TT); // Override MCAsmInfo; - virtual const MCSection *getNonexecutableStackSection(MCContext &Ctx) const - LLVM_OVERRIDE; + const MCSection *getNonexecutableStackSection(MCContext &Ctx) const override; }; -} // namespace llvm +} // end namespace llvm #endif diff --git a/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp b/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp index f07ea7b31e6a..27b4bd855b3e 100644 --- a/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp +++ b/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp @@ -11,7 +11,6 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "mccodeemitter" #include "MCTargetDesc/SystemZMCTargetDesc.h" #include "MCTargetDesc/SystemZMCFixups.h" #include "llvm/MC/MCCodeEmitter.h" @@ -21,6 +20,8 @@ using namespace llvm; +#define DEBUG_TYPE "mccodeemitter" + namespace { class SystemZMCCodeEmitter : public MCCodeEmitter { const MCInstrInfo &MCII; @@ -34,34 +35,41 @@ public: ~SystemZMCCodeEmitter() {} // OVerride MCCodeEmitter. - virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS, - SmallVectorImpl<MCFixup> &Fixups) const - LLVM_OVERRIDE; + void EncodeInstruction(const MCInst &MI, raw_ostream &OS, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const override; private: // Automatically generated by TableGen. uint64_t getBinaryCodeForInstr(const MCInst &MI, - SmallVectorImpl<MCFixup> &Fixups) const; + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; // Called by the TableGen code to get the binary encoding of operand // MO in MI. Fixups is the list of fixups against MI. uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, - SmallVectorImpl<MCFixup> &Fixups) const; + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; // Called by the TableGen code to get the binary encoding of an address. // The index or length, if any, is encoded first, followed by the base, // followed by the displacement. In a 20-bit displacement, // the low 12 bits are encoded before the high 8 bits. uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl<MCFixup> &Fixups) const; + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl<MCFixup> &Fixups) const; + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl<MCFixup> &Fixups) const; + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl<MCFixup> &Fixups) const; + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl<MCFixup> &Fixups) const; + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; // Operand OpNum of MI needs a PC-relative fixup of kind Kind at // Offset bytes from the start of MI. Add the fixup to Fixups @@ -72,15 +80,17 @@ private: unsigned Kind, int64_t Offset) const; uint64_t getPC16DBLEncoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl<MCFixup> &Fixups) const { + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC16DBL, 2); } uint64_t getPC32DBLEncoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl<MCFixup> &Fixups) const { + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC32DBL, 2); } }; -} +} // end anonymous namespace MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, @@ -91,8 +101,9 @@ MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII, void SystemZMCCodeEmitter:: EncodeInstruction(const MCInst &MI, raw_ostream &OS, - SmallVectorImpl<MCFixup> &Fixups) const { - uint64_t Bits = getBinaryCodeForInstr(MI, Fixups); + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { + uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); unsigned Size = MCII.get(MI.getOpcode()).getSize(); // Big-endian insertion of Size bytes. unsigned ShiftValue = (Size * 8) - 8; @@ -104,7 +115,8 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, uint64_t SystemZMCCodeEmitter:: getMachineOpValue(const MCInst &MI, const MCOperand &MO, - SmallVectorImpl<MCFixup> &Fixups) const { + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { if (MO.isReg()) return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); if (MO.isImm()) @@ -114,38 +126,42 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO, uint64_t SystemZMCCodeEmitter:: getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl<MCFixup> &Fixups) const { - uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); - uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { + uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); + uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); assert(isUInt<4>(Base) && isUInt<12>(Disp)); return (Base << 12) | Disp; } uint64_t SystemZMCCodeEmitter:: getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl<MCFixup> &Fixups) const { - uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); - uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { + uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); + uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); assert(isUInt<4>(Base) && isInt<20>(Disp)); return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12); } uint64_t SystemZMCCodeEmitter:: getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl<MCFixup> &Fixups) const { - uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); - uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); - uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups); + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { + uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); + uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); + uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index)); return (Index << 16) | (Base << 12) | Disp; } uint64_t SystemZMCCodeEmitter:: getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl<MCFixup> &Fixups) const { - uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); - uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); - uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups); + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { + uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); + uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); + uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index)); return (Index << 24) | (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12); @@ -153,10 +169,11 @@ getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, uint64_t SystemZMCCodeEmitter:: getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl<MCFixup> &Fixups) const { - uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); - uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); - uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups) - 1; + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { + uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); + uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); + uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI) - 1; assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<8>(Len)); return (Len << 16) | (Base << 12) | Disp; } diff --git a/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h b/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h index 9c94ebbaac78..a3aab712c08c 100644 --- a/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h +++ b/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h @@ -14,18 +14,18 @@ namespace llvm { namespace SystemZ { - enum FixupKind { - // These correspond directly to R_390_* relocations. - FK_390_PC16DBL = FirstTargetFixupKind, - FK_390_PC32DBL, - FK_390_PLT16DBL, - FK_390_PLT32DBL, +enum FixupKind { + // These correspond directly to R_390_* relocations. + FK_390_PC16DBL = FirstTargetFixupKind, + FK_390_PC32DBL, + FK_390_PLT16DBL, + FK_390_PLT32DBL, - // Marker - LastTargetFixupKind, - NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind - }; -} + // Marker + LastTargetFixupKind, + NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind +}; +} // end namespace SystemZ } // end namespace llvm #endif diff --git a/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp b/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp index 36e3d83d4d59..c6a181658896 100644 --- a/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp +++ b/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCObjectWriter.cpp @@ -24,16 +24,10 @@ public: protected: // Override MCELFObjectTargetWriter. - virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, - bool IsPCRel, bool IsRelocWithSymbol, - int64_t Addend) const LLVM_OVERRIDE; - virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, - const MCValue &Target, - const MCFragment &F, - const MCFixup &Fixup, - bool IsPCRel) const LLVM_OVERRIDE; + unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, + bool IsPCRel) const override; }; -} // end anonymouse namespace +} // end anonymous namespace SystemZObjectWriter::SystemZObjectWriter(uint8_t OSABI) : MCELFObjectTargetWriter(/*Is64Bit=*/true, OSABI, ELF::EM_S390, @@ -87,12 +81,8 @@ static unsigned getPLTReloc(unsigned Kind) { unsigned SystemZObjectWriter::GetRelocType(const MCValue &Target, const MCFixup &Fixup, - bool IsPCRel, - bool IsRelocWithSymbol, - int64_t Addend) const { - MCSymbolRefExpr::VariantKind Modifier = (Target.isAbsolute() ? - MCSymbolRefExpr::VK_None : - Target.getSymA()->getKind()); + bool IsPCRel) const { + MCSymbolRefExpr::VariantKind Modifier = Target.getAccessVariant(); unsigned Kind = Fixup.getKind(); switch (Modifier) { case MCSymbolRefExpr::VK_None: @@ -118,21 +108,6 @@ unsigned SystemZObjectWriter::GetRelocType(const MCValue &Target, } } -const MCSymbol *SystemZObjectWriter::ExplicitRelSym(const MCAssembler &Asm, - const MCValue &Target, - const MCFragment &F, - const MCFixup &Fixup, - bool IsPCRel) const { - // The addend in a PC-relative R_390_* relocation is always applied to - // the PC-relative part of the address. If some kind of indirection - // is applied to the symbol first, we can't use an addend there too. - if (!Target.isAbsolute() && - Target.getSymA()->getKind() != MCSymbolRefExpr::VK_None && - IsPCRel) - return &Target.getSymA()->getSymbol().AliasedSymbol(); - return NULL; -} - MCObjectWriter *llvm::createSystemZObjectWriter(raw_ostream &OS, uint8_t OSABI) { MCELFObjectTargetWriter *MOTW = new SystemZObjectWriter(OSABI); diff --git a/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp b/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp index 9e1296b912a0..cc94869eb5fc 100644 --- a/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp +++ b/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp @@ -16,6 +16,8 @@ #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/TargetRegistry.h" +using namespace llvm; + #define GET_INSTRINFO_MC_DESC #include "SystemZGenInstrInfo.inc" @@ -25,8 +27,6 @@ #define GET_REGINFO_MC_DESC #include "SystemZGenRegisterInfo.inc" -using namespace llvm; - const unsigned SystemZMC::GR32Regs[16] = { SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, @@ -98,7 +98,8 @@ static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) { MCAsmInfo *MAI = new SystemZMCAsmInfo(TT); MCCFIInstruction Inst = - MCCFIInstruction::createDefCfa(0, MRI.getDwarfRegNum(SystemZ::R15D, true), + MCCFIInstruction::createDefCfa(nullptr, + MRI.getDwarfRegNum(SystemZ::R15D, true), SystemZMC::CFAOffsetFromInitialSP); MAI->addInitialFrameState(Inst); return MAI; @@ -185,9 +186,10 @@ static MCStreamer *createSystemZMCObjectStreamer(const Target &T, StringRef TT, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, + const MCSubtargetInfo &STI, bool RelaxAll, bool NoExecStack) { - return createELFStreamer(Ctx, 0, MAB, OS, Emitter, RelaxAll, NoExecStack); + return createELFStreamer(Ctx, MAB, OS, Emitter, RelaxAll, NoExecStack); } extern "C" void LLVMInitializeSystemZTargetMC() { diff --git a/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h b/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h index 97e325b984f6..cbaf9a83b80f 100644 --- a/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h +++ b/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h @@ -28,47 +28,47 @@ class raw_ostream; extern Target TheSystemZTarget; namespace SystemZMC { - // How many bytes are in the ABI-defined, caller-allocated part of - // a stack frame. - const int64_t CallFrameSize = 160; - - // The offset of the DWARF CFA from the incoming stack pointer. - const int64_t CFAOffsetFromInitialSP = CallFrameSize; - - // Maps of asm register numbers to LLVM register numbers, with 0 indicating - // an invalid register. In principle we could use 32-bit and 64-bit register - // classes directly, provided that we relegated the GPR allocation order - // in SystemZRegisterInfo.td to an AltOrder and left the default order - // as %r0-%r15. It seems better to provide the same interface for - // all classes though. - extern const unsigned GR32Regs[16]; - extern const unsigned GRH32Regs[16]; - extern const unsigned GR64Regs[16]; - extern const unsigned GR128Regs[16]; - extern const unsigned FP32Regs[16]; - extern const unsigned FP64Regs[16]; - extern const unsigned FP128Regs[16]; - - // Return the 0-based number of the first architectural register that - // contains the given LLVM register. E.g. R1D -> 1. - unsigned getFirstReg(unsigned Reg); - - // Return the given register as a GR64. - inline unsigned getRegAsGR64(unsigned Reg) { - return GR64Regs[getFirstReg(Reg)]; - } - - // Return the given register as a low GR32. - inline unsigned getRegAsGR32(unsigned Reg) { - return GR32Regs[getFirstReg(Reg)]; - } - - // Return the given register as a high GR32. - inline unsigned getRegAsGRH32(unsigned Reg) { - return GRH32Regs[getFirstReg(Reg)]; - } +// How many bytes are in the ABI-defined, caller-allocated part of +// a stack frame. +const int64_t CallFrameSize = 160; + +// The offset of the DWARF CFA from the incoming stack pointer. +const int64_t CFAOffsetFromInitialSP = CallFrameSize; + +// Maps of asm register numbers to LLVM register numbers, with 0 indicating +// an invalid register. In principle we could use 32-bit and 64-bit register +// classes directly, provided that we relegated the GPR allocation order +// in SystemZRegisterInfo.td to an AltOrder and left the default order +// as %r0-%r15. It seems better to provide the same interface for +// all classes though. +extern const unsigned GR32Regs[16]; +extern const unsigned GRH32Regs[16]; +extern const unsigned GR64Regs[16]; +extern const unsigned GR128Regs[16]; +extern const unsigned FP32Regs[16]; +extern const unsigned FP64Regs[16]; +extern const unsigned FP128Regs[16]; + +// Return the 0-based number of the first architectural register that +// contains the given LLVM register. E.g. R1D -> 1. +unsigned getFirstReg(unsigned Reg); + +// Return the given register as a GR64. +inline unsigned getRegAsGR64(unsigned Reg) { + return GR64Regs[getFirstReg(Reg)]; } +// Return the given register as a low GR32. +inline unsigned getRegAsGR32(unsigned Reg) { + return GR32Regs[getFirstReg(Reg)]; +} + +// Return the given register as a high GR32. +inline unsigned getRegAsGRH32(unsigned Reg) { + return GRH32Regs[getFirstReg(Reg)]; +} +} // end namespace SystemZMC + MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, |