diff options
Diffstat (limited to 'contrib/llvm/lib/Target/PowerPC/PPCScheduleG3.td')
| -rw-r--r-- | contrib/llvm/lib/Target/PowerPC/PPCScheduleG3.td | 119 |
1 files changed, 64 insertions, 55 deletions
diff --git a/contrib/llvm/lib/Target/PowerPC/PPCScheduleG3.td b/contrib/llvm/lib/Target/PowerPC/PPCScheduleG3.td index 72a0a392631a..21efd8f8f6c9 100644 --- a/contrib/llvm/lib/Target/PowerPC/PPCScheduleG3.td +++ b/contrib/llvm/lib/Target/PowerPC/PPCScheduleG3.td @@ -11,61 +11,70 @@ // //===----------------------------------------------------------------------===// +def G3_BPU : FuncUnit; // Branch unit +def G3_SLU : FuncUnit; // Store/load unit +def G3_SRU : FuncUnit; // special register unit +def G3_IU1 : FuncUnit; // integer unit 1 (simple) +def G3_IU2 : FuncUnit; // integer unit 2 (complex) +def G3_FPU1 : FuncUnit; // floating point unit 1 def G3Itineraries : ProcessorItineraries< - [IU1, IU2, FPU1, BPU, SRU, SLU], [], [ - InstrItinData<IntSimple , [InstrStage<1, [IU1, IU2]>]>, - InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>, - InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>, - InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>, - InstrItinData<IntMFFS , [InstrStage<1, [FPU1]>]>, - InstrItinData<IntMTFSB0 , [InstrStage<3, [FPU1]>]>, - InstrItinData<IntMulHW , [InstrStage<5, [IU1]>]>, - InstrItinData<IntMulHWU , [InstrStage<6, [IU1]>]>, - InstrItinData<IntMulLI , [InstrStage<3, [IU1]>]>, - InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2]>]>, - InstrItinData<IntShift , [InstrStage<1, [IU1, IU2]>]>, - InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2]>]>, - InstrItinData<BrB , [InstrStage<1, [BPU]>]>, - InstrItinData<BrCR , [InstrStage<1, [SRU]>]>, - InstrItinData<BrMCR , [InstrStage<1, [SRU]>]>, - InstrItinData<BrMCRX , [InstrStage<1, [SRU]>]>, - InstrItinData<LdStDCBA , [InstrStage<2, [SLU]>]>, - InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>, - InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>, - InstrItinData<LdStLoad , [InstrStage<2, [SLU]>]>, - InstrItinData<LdStLoadUpd , [InstrStage<2, [SLU]>]>, - InstrItinData<LdStStore , [InstrStage<2, [SLU]>]>, - InstrItinData<LdStStoreUpd, [InstrStage<2, [SLU]>]>, - InstrItinData<LdStICBI , [InstrStage<3, [SLU]>]>, - InstrItinData<LdStSTFD , [InstrStage<2, [SLU]>]>, - InstrItinData<LdStSTFDU , [InstrStage<2, [SLU]>]>, - InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>, - InstrItinData<LdStLFDU , [InstrStage<2, [SLU]>]>, - InstrItinData<LdStLHA , [InstrStage<2, [SLU]>]>, - InstrItinData<LdStLHAU , [InstrStage<2, [SLU]>]>, - InstrItinData<LdStLMW , [InstrStage<34, [SLU]>]>, - InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>, - InstrItinData<LdStSTWCX , [InstrStage<8, [SLU]>]>, - InstrItinData<LdStSync , [InstrStage<3, [SLU]>]>, - InstrItinData<SprISYNC , [InstrStage<2, [SRU]>]>, - InstrItinData<SprMFSR , [InstrStage<3, [SRU]>]>, - InstrItinData<SprMTMSR , [InstrStage<1, [SRU]>]>, - InstrItinData<SprMTSR , [InstrStage<2, [SRU]>]>, - InstrItinData<SprTLBSYNC , [InstrStage<3, [SRU]>]>, - InstrItinData<SprMFCR , [InstrStage<1, [SRU]>]>, - InstrItinData<SprMFMSR , [InstrStage<1, [SRU]>]>, - InstrItinData<SprMFSPR , [InstrStage<3, [SRU]>]>, - InstrItinData<SprMFTB , [InstrStage<3, [SRU]>]>, - InstrItinData<SprMTSPR , [InstrStage<2, [SRU]>]>, - InstrItinData<SprMTSRIN , [InstrStage<2, [SRU]>]>, - InstrItinData<SprRFI , [InstrStage<2, [SRU]>]>, - InstrItinData<SprSC , [InstrStage<2, [SRU]>]>, - InstrItinData<FPGeneral , [InstrStage<1, [FPU1]>]>, - InstrItinData<FPAddSub , [InstrStage<1, [FPU1]>]>, - InstrItinData<FPCompare , [InstrStage<1, [FPU1]>]>, - InstrItinData<FPDivD , [InstrStage<31, [FPU1]>]>, - InstrItinData<FPDivS , [InstrStage<17, [FPU1]>]>, - InstrItinData<FPFused , [InstrStage<2, [FPU1]>]>, - InstrItinData<FPRes , [InstrStage<10, [FPU1]>]> + [G3_IU1, G3_IU2, G3_FPU1, G3_BPU, G3_SRU, G3_SLU], [], [ + InstrItinData<IIC_IntSimple , [InstrStage<1, [G3_IU1, G3_IU2]>]>, + InstrItinData<IIC_IntGeneral , [InstrStage<1, [G3_IU1, G3_IU2]>]>, + InstrItinData<IIC_IntCompare , [InstrStage<1, [G3_IU1, G3_IU2]>]>, + InstrItinData<IIC_IntDivW , [InstrStage<19, [G3_IU1]>]>, + InstrItinData<IIC_IntMFFS , [InstrStage<1, [G3_FPU1]>]>, + InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [G3_FPU1]>]>, + InstrItinData<IIC_IntMulHW , [InstrStage<5, [G3_IU1]>]>, + InstrItinData<IIC_IntMulHWU , [InstrStage<6, [G3_IU1]>]>, + InstrItinData<IIC_IntMulLI , [InstrStage<3, [G3_IU1]>]>, + InstrItinData<IIC_IntRotate , [InstrStage<1, [G3_IU1, G3_IU2]>]>, + InstrItinData<IIC_IntShift , [InstrStage<1, [G3_IU1, G3_IU2]>]>, + InstrItinData<IIC_IntTrapW , [InstrStage<2, [G3_IU1, G3_IU2]>]>, + InstrItinData<IIC_BrB , [InstrStage<1, [G3_BPU]>]>, + InstrItinData<IIC_BrCR , [InstrStage<1, [G3_SRU]>]>, + InstrItinData<IIC_BrMCR , [InstrStage<1, [G3_SRU]>]>, + InstrItinData<IIC_BrMCRX , [InstrStage<1, [G3_SRU]>]>, + InstrItinData<IIC_LdStDCBA , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStDCBF , [InstrStage<3, [G3_SLU]>]>, + InstrItinData<IIC_LdStDCBI , [InstrStage<3, [G3_SLU]>]>, + InstrItinData<IIC_LdStLoad , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStLoadUpd , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStLoadUpdX, [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStStore , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStStoreUpd, [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStICBI , [InstrStage<3, [G3_SLU]>]>, + InstrItinData<IIC_LdStSTFD , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStSTFDU , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStLFD , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStLFDU , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStLFDUX , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStLHA , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStLHAU , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStLHAUX , [InstrStage<2, [G3_SLU]>]>, + InstrItinData<IIC_LdStLMW , [InstrStage<34, [G3_SLU]>]>, + InstrItinData<IIC_LdStLWARX , [InstrStage<3, [G3_SLU]>]>, + InstrItinData<IIC_LdStSTWCX , [InstrStage<8, [G3_SLU]>]>, + InstrItinData<IIC_LdStSync , [InstrStage<3, [G3_SLU]>]>, + InstrItinData<IIC_SprISYNC , [InstrStage<2, [G3_SRU]>]>, + InstrItinData<IIC_SprMFSR , [InstrStage<3, [G3_SRU]>]>, + InstrItinData<IIC_SprMTMSR , [InstrStage<1, [G3_SRU]>]>, + InstrItinData<IIC_SprMTSR , [InstrStage<2, [G3_SRU]>]>, + InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [G3_SRU]>]>, + InstrItinData<IIC_SprMFCR , [InstrStage<1, [G3_SRU]>]>, + InstrItinData<IIC_SprMFMSR , [InstrStage<1, [G3_SRU]>]>, + InstrItinData<IIC_SprMFSPR , [InstrStage<3, [G3_SRU]>]>, + InstrItinData<IIC_SprMFTB , [InstrStage<3, [G3_SRU]>]>, + InstrItinData<IIC_SprMTSPR , [InstrStage<2, [G3_SRU]>]>, + InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [G3_SRU]>]>, + InstrItinData<IIC_SprRFI , [InstrStage<2, [G3_SRU]>]>, + InstrItinData<IIC_SprSC , [InstrStage<2, [G3_SRU]>]>, + InstrItinData<IIC_FPGeneral , [InstrStage<1, [G3_FPU1]>]>, + InstrItinData<IIC_FPAddSub , [InstrStage<1, [G3_FPU1]>]>, + InstrItinData<IIC_FPCompare , [InstrStage<1, [G3_FPU1]>]>, + InstrItinData<IIC_FPDivD , [InstrStage<31, [G3_FPU1]>]>, + InstrItinData<IIC_FPDivS , [InstrStage<17, [G3_FPU1]>]>, + InstrItinData<IIC_FPFused , [InstrStage<2, [G3_FPU1]>]>, + InstrItinData<IIC_FPRes , [InstrStage<10, [G3_FPU1]>]> ]>; |