diff options
Diffstat (limited to 'contrib/llvm/lib/Target/MSP430')
32 files changed, 6206 insertions, 0 deletions
diff --git a/contrib/llvm/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.cpp b/contrib/llvm/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.cpp new file mode 100644 index 000000000000..be6d1a84a377 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.cpp @@ -0,0 +1,116 @@ +//===-- MSP430InstPrinter.cpp - Convert MSP430 MCInst to assembly syntax --===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This class prints an MSP430 MCInst to a .s file. +// +//===----------------------------------------------------------------------===// + +#include "MSP430InstPrinter.h" +#include "MSP430.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCInst.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/FormattedStream.h" +using namespace llvm; + +#define DEBUG_TYPE "asm-printer" + + +// Include the auto-generated portion of the assembly writer. +#include "MSP430GenAsmWriter.inc" + +void MSP430InstPrinter::printInst(const MCInst *MI, raw_ostream &O, + StringRef Annot, const MCSubtargetInfo &STI) { + printInstruction(MI, O); + printAnnotation(O, Annot); +} + +void MSP430InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { + const MCOperand &Op = MI->getOperand(OpNo); + if (Op.isImm()) + O << Op.getImm(); + else { + assert(Op.isExpr() && "unknown pcrel immediate operand"); + Op.getExpr()->print(O, &MAI); + } +} + +void MSP430InstPrinter::printOperand(const MCInst *MI, unsigned OpNo, + raw_ostream &O, const char *Modifier) { + assert((Modifier == nullptr || Modifier[0] == 0) && "No modifiers supported"); + const MCOperand &Op = MI->getOperand(OpNo); + if (Op.isReg()) { + O << getRegisterName(Op.getReg()); + } else if (Op.isImm()) { + O << '#' << Op.getImm(); + } else { + assert(Op.isExpr() && "unknown operand kind in printOperand"); + O << '#'; + Op.getExpr()->print(O, &MAI); + } +} + +void MSP430InstPrinter::printSrcMemOperand(const MCInst *MI, unsigned OpNo, + raw_ostream &O, + const char *Modifier) { + const MCOperand &Base = MI->getOperand(OpNo); + const MCOperand &Disp = MI->getOperand(OpNo+1); + + // Print displacement first + + // If the global address expression is a part of displacement field with a + // register base, we should not emit any prefix symbol here, e.g. + // mov.w &foo, r1 + // vs + // mov.w glb(r1), r2 + // Otherwise (!) msp430-as will silently miscompile the output :( + if (!Base.getReg()) + O << '&'; + + if (Disp.isExpr()) + Disp.getExpr()->print(O, &MAI); + else { + assert(Disp.isImm() && "Expected immediate in displacement field"); + O << Disp.getImm(); + } + + // Print register base field + if (Base.getReg()) + O << '(' << getRegisterName(Base.getReg()) << ')'; +} + +void MSP430InstPrinter::printCCOperand(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { + unsigned CC = MI->getOperand(OpNo).getImm(); + + switch (CC) { + default: + llvm_unreachable("Unsupported CC code"); + case MSP430CC::COND_E: + O << "eq"; + break; + case MSP430CC::COND_NE: + O << "ne"; + break; + case MSP430CC::COND_HS: + O << "hs"; + break; + case MSP430CC::COND_LO: + O << "lo"; + break; + case MSP430CC::COND_GE: + O << "ge"; + break; + case MSP430CC::COND_L: + O << 'l'; + break; + } +} diff --git a/contrib/llvm/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h b/contrib/llvm/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h new file mode 100644 index 000000000000..72afec18becb --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/InstPrinter/MSP430InstPrinter.h @@ -0,0 +1,43 @@ +//= MSP430InstPrinter.h - Convert MSP430 MCInst to assembly syntax -*- C++ -*-// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This class prints a MSP430 MCInst to a .s file. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_MSP430_INSTPRINTER_MSP430INSTPRINTER_H +#define LLVM_LIB_TARGET_MSP430_INSTPRINTER_MSP430INSTPRINTER_H + +#include "llvm/MC/MCInstPrinter.h" + +namespace llvm { + class MSP430InstPrinter : public MCInstPrinter { + public: + MSP430InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, + const MCRegisterInfo &MRI) + : MCInstPrinter(MAI, MII, MRI) {} + + void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, + const MCSubtargetInfo &STI) override; + + // Autogenerated by tblgen. + void printInstruction(const MCInst *MI, raw_ostream &O); + static const char *getRegisterName(unsigned RegNo); + + void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, + const char *Modifier = nullptr); + void printPCRelImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); + void printSrcMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, + const char *Modifier = nullptr); + void printCCOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); + + }; +} + +#endif diff --git a/contrib/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp b/contrib/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp new file mode 100644 index 000000000000..82e6731ecd78 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp @@ -0,0 +1,26 @@ +//===-- MSP430MCAsmInfo.cpp - MSP430 asm properties -----------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declarations of the MSP430MCAsmInfo properties. +// +//===----------------------------------------------------------------------===// + +#include "MSP430MCAsmInfo.h" +using namespace llvm; + +void MSP430MCAsmInfo::anchor() { } + +MSP430MCAsmInfo::MSP430MCAsmInfo(const Triple &TT) { + CodePointerSize = CalleeSaveStackSlotSize = 2; + + CommentString = ";"; + + AlignmentIsInBytes = false; + UsesELFSectionDirectiveForBSS = true; +} diff --git a/contrib/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h b/contrib/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h new file mode 100644 index 000000000000..183dee36a047 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h @@ -0,0 +1,31 @@ +//===-- MSP430MCAsmInfo.h - MSP430 asm properties --------------*- C++ -*--===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the declaration of the MSP430MCAsmInfo class. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430MCASMINFO_H +#define LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430MCASMINFO_H + +#include "llvm/MC/MCAsmInfoELF.h" + +namespace llvm { +class Triple; + +class MSP430MCAsmInfo : public MCAsmInfoELF { + void anchor() override; + +public: + explicit MSP430MCAsmInfo(const Triple &TT); +}; + +} // namespace llvm + +#endif diff --git a/contrib/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp b/contrib/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp new file mode 100644 index 000000000000..8c715500f38b --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp @@ -0,0 +1,79 @@ +//===-- MSP430MCTargetDesc.cpp - MSP430 Target Descriptions ---------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides MSP430 specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#include "MSP430MCTargetDesc.h" +#include "InstPrinter/MSP430InstPrinter.h" +#include "MSP430MCAsmInfo.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/TargetRegistry.h" + +using namespace llvm; + +#define GET_INSTRINFO_MC_DESC +#include "MSP430GenInstrInfo.inc" + +#define GET_SUBTARGETINFO_MC_DESC +#include "MSP430GenSubtargetInfo.inc" + +#define GET_REGINFO_MC_DESC +#include "MSP430GenRegisterInfo.inc" + +static MCInstrInfo *createMSP430MCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitMSP430MCInstrInfo(X); + return X; +} + +static MCRegisterInfo *createMSP430MCRegisterInfo(const Triple &TT) { + MCRegisterInfo *X = new MCRegisterInfo(); + InitMSP430MCRegisterInfo(X, MSP430::PC); + return X; +} + +static MCSubtargetInfo * +createMSP430MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { + return createMSP430MCSubtargetInfoImpl(TT, CPU, FS); +} + +static MCInstPrinter *createMSP430MCInstPrinter(const Triple &T, + unsigned SyntaxVariant, + const MCAsmInfo &MAI, + const MCInstrInfo &MII, + const MCRegisterInfo &MRI) { + if (SyntaxVariant == 0) + return new MSP430InstPrinter(MAI, MII, MRI); + return nullptr; +} + +extern "C" void LLVMInitializeMSP430TargetMC() { + // Register the MC asm info. + RegisterMCAsmInfo<MSP430MCAsmInfo> X(getTheMSP430Target()); + + // Register the MC instruction info. + TargetRegistry::RegisterMCInstrInfo(getTheMSP430Target(), + createMSP430MCInstrInfo); + + // Register the MC register info. + TargetRegistry::RegisterMCRegInfo(getTheMSP430Target(), + createMSP430MCRegisterInfo); + + // Register the MC subtarget info. + TargetRegistry::RegisterMCSubtargetInfo(getTheMSP430Target(), + createMSP430MCSubtargetInfo); + + // Register the MCInstPrinter. + TargetRegistry::RegisterMCInstPrinter(getTheMSP430Target(), + createMSP430MCInstPrinter); +} diff --git a/contrib/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h b/contrib/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h new file mode 100644 index 000000000000..b901c5f09794 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h @@ -0,0 +1,38 @@ +//===-- MSP430MCTargetDesc.h - MSP430 Target Descriptions -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides MSP430 specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430MCTARGETDESC_H +#define LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430MCTARGETDESC_H + +#include "llvm/Support/DataTypes.h" + +namespace llvm { +class Target; + +Target &getTheMSP430Target(); + +} // End llvm namespace + +// Defines symbolic names for MSP430 registers. +// This defines a mapping from register name to register number. +#define GET_REGINFO_ENUM +#include "MSP430GenRegisterInfo.inc" + +// Defines symbolic names for the MSP430 instructions. +#define GET_INSTRINFO_ENUM +#include "MSP430GenInstrInfo.inc" + +#define GET_SUBTARGETINFO_ENUM +#include "MSP430GenSubtargetInfo.inc" + +#endif diff --git a/contrib/llvm/lib/Target/MSP430/MSP430.h b/contrib/llvm/lib/Target/MSP430/MSP430.h new file mode 100644 index 000000000000..796f25233123 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430.h @@ -0,0 +1,47 @@ +//==-- MSP430.h - Top-level interface for MSP430 representation --*- C++ -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the entry points for global functions defined in +// the LLVM MSP430 backend. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_MSP430_MSP430_H +#define LLVM_LIB_TARGET_MSP430_MSP430_H + +#include "MCTargetDesc/MSP430MCTargetDesc.h" +#include "llvm/Target/TargetMachine.h" + +namespace MSP430CC { + // MSP430 specific condition code. + enum CondCodes { + COND_E = 0, // aka COND_Z + COND_NE = 1, // aka COND_NZ + COND_HS = 2, // aka COND_C + COND_LO = 3, // aka COND_NC + COND_GE = 4, + COND_L = 5, + + COND_INVALID = -1 + }; +} + +namespace llvm { + class MSP430TargetMachine; + class FunctionPass; + class formatted_raw_ostream; + + FunctionPass *createMSP430ISelDag(MSP430TargetMachine &TM, + CodeGenOpt::Level OptLevel); + + FunctionPass *createMSP430BranchSelectionPass(); + +} // end namespace llvm; + +#endif diff --git a/contrib/llvm/lib/Target/MSP430/MSP430.td b/contrib/llvm/lib/Target/MSP430/MSP430.td new file mode 100644 index 000000000000..203864dd4065 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430.td @@ -0,0 +1,74 @@ +//===-- MSP430.td - Describe the MSP430 Target Machine -----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// This is the top level entry point for the MSP430 target. +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Target-independent interfaces +//===----------------------------------------------------------------------===// + +include "llvm/Target/Target.td" + +//===----------------------------------------------------------------------===// +// Subtarget Features. +//===----------------------------------------------------------------------===// +def FeatureX + : SubtargetFeature<"ext", "ExtendedInsts", "true", + "Enable MSP430-X extensions">; + +def FeatureHWMult16 + : SubtargetFeature<"hwmult16", "HWMultMode", "HWMult16", + "Enable 16-bit hardware multiplier">; + +def FeatureHWMult32 + : SubtargetFeature<"hwmult32", "HWMultMode", "HWMult32", + "Enable 32-bit hardware multiplier">; + +def FeatureHWMultF5 + : SubtargetFeature<"hwmultf5", "HWMultMode", "HWMultF5", + "Enable F5 series hardware multiplier">; + +//===----------------------------------------------------------------------===// +// MSP430 supported processors. +//===----------------------------------------------------------------------===// +class Proc<string Name, list<SubtargetFeature> Features> + : Processor<Name, NoItineraries, Features>; + +def : Proc<"generic", []>; +def : Proc<"msp430", []>; +def : Proc<"msp430x", [FeatureX]>; + +//===----------------------------------------------------------------------===// +// Register File Description +//===----------------------------------------------------------------------===// + +include "MSP430RegisterInfo.td" + +//===----------------------------------------------------------------------===// +// Calling Convention Description +//===----------------------------------------------------------------------===// + +include "MSP430CallingConv.td" + +//===----------------------------------------------------------------------===// +// Instruction Descriptions +//===----------------------------------------------------------------------===// + +include "MSP430InstrInfo.td" + +def MSP430InstrInfo : InstrInfo; + +//===----------------------------------------------------------------------===// +// Target Declaration +//===----------------------------------------------------------------------===// + +def MSP430 : Target { + let InstructionSet = MSP430InstrInfo; +} + diff --git a/contrib/llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp b/contrib/llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp new file mode 100644 index 000000000000..f39c21fc8aa2 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp @@ -0,0 +1,159 @@ +//===-- MSP430AsmPrinter.cpp - MSP430 LLVM assembly writer ----------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains a printer that converts from our internal representation +// of machine-dependent LLVM code to the MSP430 assembly language. +// +//===----------------------------------------------------------------------===// + +#include "InstPrinter/MSP430InstPrinter.h" +#include "MSP430.h" +#include "MSP430InstrInfo.h" +#include "MSP430MCInstLower.h" +#include "MSP430TargetMachine.h" +#include "llvm/CodeGen/AsmPrinter.h" +#include "llvm/CodeGen/MachineConstantPool.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/DerivedTypes.h" +#include "llvm/IR/Mangler.h" +#include "llvm/IR/Module.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCSymbol.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/raw_ostream.h" +using namespace llvm; + +#define DEBUG_TYPE "asm-printer" + +namespace { + class MSP430AsmPrinter : public AsmPrinter { + public: + MSP430AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer) + : AsmPrinter(TM, std::move(Streamer)) {} + + StringRef getPassName() const override { return "MSP430 Assembly Printer"; } + + void printOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O, const char* Modifier = nullptr); + void printSrcMemOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O) override; + bool PrintAsmMemoryOperand(const MachineInstr *MI, + unsigned OpNo, unsigned AsmVariant, + const char *ExtraCode, raw_ostream &O) override; + void EmitInstruction(const MachineInstr *MI) override; + }; +} // end of anonymous namespace + + +void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O, const char *Modifier) { + const MachineOperand &MO = MI->getOperand(OpNum); + switch (MO.getType()) { + default: llvm_unreachable("Not implemented yet!"); + case MachineOperand::MO_Register: + O << MSP430InstPrinter::getRegisterName(MO.getReg()); + return; + case MachineOperand::MO_Immediate: + if (!Modifier || strcmp(Modifier, "nohash")) + O << '#'; + O << MO.getImm(); + return; + case MachineOperand::MO_MachineBasicBlock: + MO.getMBB()->getSymbol()->print(O, MAI); + return; + case MachineOperand::MO_GlobalAddress: { + bool isMemOp = Modifier && !strcmp(Modifier, "mem"); + uint64_t Offset = MO.getOffset(); + + // If the global address expression is a part of displacement field with a + // register base, we should not emit any prefix symbol here, e.g. + // mov.w &foo, r1 + // vs + // mov.w glb(r1), r2 + // Otherwise (!) msp430-as will silently miscompile the output :( + if (!Modifier || strcmp(Modifier, "nohash")) + O << (isMemOp ? '&' : '#'); + if (Offset) + O << '(' << Offset << '+'; + + getSymbol(MO.getGlobal())->print(O, MAI); + + if (Offset) + O << ')'; + + return; + } + } +} + +void MSP430AsmPrinter::printSrcMemOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { + const MachineOperand &Base = MI->getOperand(OpNum); + const MachineOperand &Disp = MI->getOperand(OpNum+1); + + // Print displacement first + + // Imm here is in fact global address - print extra modifier. + if (Disp.isImm() && !Base.getReg()) + O << '&'; + printOperand(MI, OpNum+1, O, "nohash"); + + // Print register base field + if (Base.getReg()) { + O << '('; + printOperand(MI, OpNum, O); + O << ')'; + } +} + +/// PrintAsmOperand - Print out an operand for an inline asm expression. +/// +bool MSP430AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, + unsigned AsmVariant, + const char *ExtraCode, raw_ostream &O) { + // Does this asm operand have a single letter operand modifier? + if (ExtraCode && ExtraCode[0]) + return true; // Unknown modifier. + + printOperand(MI, OpNo, O); + return false; +} + +bool MSP430AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, + unsigned OpNo, unsigned AsmVariant, + const char *ExtraCode, + raw_ostream &O) { + if (ExtraCode && ExtraCode[0]) { + return true; // Unknown modifier. + } + printSrcMemOperand(MI, OpNo, O); + return false; +} + +//===----------------------------------------------------------------------===// +void MSP430AsmPrinter::EmitInstruction(const MachineInstr *MI) { + MSP430MCInstLower MCInstLowering(OutContext, *this); + + MCInst TmpInst; + MCInstLowering.Lower(MI, TmpInst); + EmitToStreamer(*OutStreamer, TmpInst); +} + +// Force static initialization. +extern "C" void LLVMInitializeMSP430AsmPrinter() { + RegisterAsmPrinter<MSP430AsmPrinter> X(getTheMSP430Target()); +} diff --git a/contrib/llvm/lib/Target/MSP430/MSP430BranchSelector.cpp b/contrib/llvm/lib/Target/MSP430/MSP430BranchSelector.cpp new file mode 100644 index 000000000000..424b5ae418f7 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430BranchSelector.cpp @@ -0,0 +1,257 @@ +//===-- MSP430BranchSelector.cpp - Emit long conditional branches ---------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains a pass that scans a machine function to determine which +// conditional branches need more than 10 bits of displacement to reach their +// target basic block. It does this in two passes; a calculation of basic block +// positions pass, and a branch pseudo op to machine branch opcode pass. This +// pass should be run last, just before the assembly printer. +// +//===----------------------------------------------------------------------===// + +#include "MSP430.h" +#include "MSP430InstrInfo.h" +#include "MSP430Subtarget.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/Support/MathExtras.h" +#include "llvm/Target/TargetMachine.h" +using namespace llvm; + +#define DEBUG_TYPE "msp430-branch-select" + +static cl::opt<bool> + BranchSelectEnabled("msp430-branch-select", cl::Hidden, cl::init(true), + cl::desc("Expand out of range branches")); + +STATISTIC(NumSplit, "Number of machine basic blocks split"); +STATISTIC(NumExpanded, "Number of branches expanded to long format"); + +namespace { +class MSP430BSel : public MachineFunctionPass { + + typedef SmallVector<int, 16> OffsetVector; + + MachineFunction *MF; + const MSP430InstrInfo *TII; + + unsigned measureFunction(OffsetVector &BlockOffsets, + MachineBasicBlock *FromBB = nullptr); + bool expandBranches(OffsetVector &BlockOffsets); + +public: + static char ID; + MSP430BSel() : MachineFunctionPass(ID) {} + + bool runOnMachineFunction(MachineFunction &MF) override; + + MachineFunctionProperties getRequiredProperties() const override { + return MachineFunctionProperties().set( + MachineFunctionProperties::Property::NoVRegs); + } + + StringRef getPassName() const override { return "MSP430 Branch Selector"; } +}; +char MSP430BSel::ID = 0; +} + +static bool isInRage(int DistanceInBytes) { + // According to CC430 Family User's Guide, Section 4.5.1.3, branch + // instructions have the signed 10-bit word offset field, so first we need to + // convert the distance from bytes to words, then check if it fits in 10-bit + // signed integer. + const int WordSize = 2; + + assert((DistanceInBytes % WordSize == 0) && + "Branch offset should be word aligned!"); + + int Words = DistanceInBytes / WordSize; + return isInt<10>(Words); +} + +/// Measure each basic block, fill the BlockOffsets, and return the size of +/// the function, starting with BB +unsigned MSP430BSel::measureFunction(OffsetVector &BlockOffsets, + MachineBasicBlock *FromBB) { + // Give the blocks of the function a dense, in-order, numbering. + MF->RenumberBlocks(FromBB); + + MachineFunction::iterator Begin; + if (FromBB == nullptr) { + Begin = MF->begin(); + } else { + Begin = FromBB->getIterator(); + } + + BlockOffsets.resize(MF->getNumBlockIDs()); + + unsigned TotalSize = BlockOffsets[Begin->getNumber()]; + for (auto &MBB : make_range(Begin, MF->end())) { + BlockOffsets[MBB.getNumber()] = TotalSize; + for (MachineInstr &MI : MBB) { + TotalSize += TII->getInstSizeInBytes(MI); + } + } + return TotalSize; +} + +/// Do expand branches and split the basic blocks if necessary. +/// Returns true if made any change. +bool MSP430BSel::expandBranches(OffsetVector &BlockOffsets) { + // For each conditional branch, if the offset to its destination is larger + // than the offset field allows, transform it into a long branch sequence + // like this: + // short branch: + // bCC MBB + // long branch: + // b!CC $PC+6 + // b MBB + // + bool MadeChange = false; + for (auto MBB = MF->begin(), E = MF->end(); MBB != E; ++MBB) { + unsigned MBBStartOffset = 0; + for (auto MI = MBB->begin(), EE = MBB->end(); MI != EE; ++MI) { + MBBStartOffset += TII->getInstSizeInBytes(*MI); + + // If this instruction is not a short branch then skip it. + if (MI->getOpcode() != MSP430::JCC && MI->getOpcode() != MSP430::JMP) { + continue; + } + + MachineBasicBlock *DestBB = MI->getOperand(0).getMBB(); + // Determine the distance from the current branch to the destination + // block. MBBStartOffset already includes the size of the current branch + // instruction. + int BlockDistance = + BlockOffsets[DestBB->getNumber()] - BlockOffsets[MBB->getNumber()]; + int BranchDistance = BlockDistance - MBBStartOffset; + + // If this branch is in range, ignore it. + if (isInRage(BranchDistance)) { + continue; + } + + DEBUG(dbgs() << " Found a branch that needs expanding, BB#" + << DestBB->getNumber() << ", Distance " << BranchDistance + << "\n"); + + // If JCC is not the last instruction we need to split the MBB. + if (MI->getOpcode() == MSP430::JCC && std::next(MI) != EE) { + + DEBUG(dbgs() << " Found a basic block that needs to be split, BB#" + << MBB->getNumber() << "\n"); + + // Create a new basic block. + MachineBasicBlock *NewBB = + MF->CreateMachineBasicBlock(MBB->getBasicBlock()); + MF->insert(std::next(MBB), NewBB); + + // Splice the instructions following MI over to the NewBB. + NewBB->splice(NewBB->end(), &*MBB, std::next(MI), MBB->end()); + + // Update the successor lists. + for (MachineBasicBlock *Succ : MBB->successors()) { + if (Succ == DestBB) { + continue; + } + MBB->replaceSuccessor(Succ, NewBB); + NewBB->addSuccessor(Succ); + } + + // We introduced a new MBB so all following blocks should be numbered + // and measured again. + measureFunction(BlockOffsets, &*MBB); + + ++NumSplit; + + // It may be not necessary to start all over at this point, but it's + // safer do this anyway. + return true; + } + + MachineInstr &OldBranch = *MI; + DebugLoc dl = OldBranch.getDebugLoc(); + int InstrSizeDiff = -TII->getInstSizeInBytes(OldBranch); + + if (MI->getOpcode() == MSP430::JCC) { + MachineBasicBlock *NextMBB = &*std::next(MBB); + assert(MBB->isSuccessor(NextMBB) && + "This block must have a layout successor!"); + + // The BCC operands are: + // 0. Target MBB + // 1. MSP430 branch predicate + SmallVector<MachineOperand, 1> Cond; + Cond.push_back(MI->getOperand(1)); + + // Jump over the long branch on the opposite condition + TII->reverseBranchCondition(Cond); + MI = BuildMI(*MBB, MI, dl, TII->get(MSP430::JCC)) + .addMBB(NextMBB) + .add(Cond[0]); + InstrSizeDiff += TII->getInstSizeInBytes(*MI); + ++MI; + } + + // Unconditional branch to the real destination. + MI = BuildMI(*MBB, MI, dl, TII->get(MSP430::Bi)).addMBB(DestBB); + InstrSizeDiff += TII->getInstSizeInBytes(*MI); + + // Remove the old branch from the function. + OldBranch.eraseFromParent(); + + // The size of a new instruction is different from the old one, so we need + // to correct all block offsets. + for (int i = MBB->getNumber() + 1, e = BlockOffsets.size(); i < e; ++i) { + BlockOffsets[i] += InstrSizeDiff; + } + MBBStartOffset += InstrSizeDiff; + + ++NumExpanded; + MadeChange = true; + } + } + return MadeChange; +} + +bool MSP430BSel::runOnMachineFunction(MachineFunction &mf) { + MF = &mf; + TII = static_cast<const MSP430InstrInfo *>(MF->getSubtarget().getInstrInfo()); + + // If the pass is disabled, just bail early. + if (!BranchSelectEnabled) + return false; + + DEBUG(dbgs() << "\n********** " << getPassName() << " **********\n"); + + // BlockOffsets - Contains the distance from the beginning of the function to + // the beginning of each basic block. + OffsetVector BlockOffsets; + + unsigned FunctionSize = measureFunction(BlockOffsets); + // If the entire function is smaller than the displacement of a branch field, + // we know we don't need to expand any branches in this + // function. This is a common case. + if (isInRage(FunctionSize)) { + return false; + } + + // Iteratively expand branches until we reach a fixed point. + bool MadeChange = false; + while (expandBranches(BlockOffsets)) + MadeChange = true; + + return MadeChange; +} + +/// Returns an instance of the Branch Selection Pass +FunctionPass *llvm::createMSP430BranchSelectionPass() { + return new MSP430BSel(); +} diff --git a/contrib/llvm/lib/Target/MSP430/MSP430CallingConv.td b/contrib/llvm/lib/Target/MSP430/MSP430CallingConv.td new file mode 100644 index 000000000000..0434f8abfbf4 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430CallingConv.td @@ -0,0 +1,37 @@ +//==- MSP430CallingConv.td - Calling Conventions for MSP430 -*- tablegen -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// This describes the calling conventions for MSP430 architecture. +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// MSP430 Return Value Calling Convention +//===----------------------------------------------------------------------===// +def RetCC_MSP430 : CallingConv<[ + // i8 are returned in registers R12B, R13B, R14B, R15B + CCIfType<[i8], CCAssignToReg<[R12B, R13B, R14B, R15B]>>, + + // i16 are returned in registers R12, R13, R14, R15 + CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>> +]>; + +//===----------------------------------------------------------------------===// +// MSP430 Argument Calling Conventions +//===----------------------------------------------------------------------===// +def CC_MSP430_AssignStack : CallingConv<[ + // Pass by value if the byval attribute is given + CCIfByVal<CCPassByVal<2, 2>>, + + // Promote i8 arguments to i16. + CCIfType<[i8], CCPromoteToType<i16>>, + + // Integer values get stored in stack slots that are 2 bytes in + // size and 2-byte aligned. + CCIfType<[i16], CCAssignToStack<2, 2>> +]>; + diff --git a/contrib/llvm/lib/Target/MSP430/MSP430FrameLowering.cpp b/contrib/llvm/lib/Target/MSP430/MSP430FrameLowering.cpp new file mode 100644 index 000000000000..b4ff8f66c55f --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430FrameLowering.cpp @@ -0,0 +1,300 @@ +//===-- MSP430FrameLowering.cpp - MSP430 Frame Information ----------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the MSP430 implementation of TargetFrameLowering class. +// +//===----------------------------------------------------------------------===// + +#include "MSP430FrameLowering.h" +#include "MSP430InstrInfo.h" +#include "MSP430MachineFunctionInfo.h" +#include "MSP430Subtarget.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/IR/Function.h" +#include "llvm/Target/TargetOptions.h" + +using namespace llvm; + +bool MSP430FrameLowering::hasFP(const MachineFunction &MF) const { + const MachineFrameInfo &MFI = MF.getFrameInfo(); + + return (MF.getTarget().Options.DisableFramePointerElim(MF) || + MF.getFrameInfo().hasVarSizedObjects() || + MFI.isFrameAddressTaken()); +} + +bool MSP430FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { + return !MF.getFrameInfo().hasVarSizedObjects(); +} + +void MSP430FrameLowering::emitPrologue(MachineFunction &MF, + MachineBasicBlock &MBB) const { + assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported"); + MachineFrameInfo &MFI = MF.getFrameInfo(); + MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>(); + const MSP430InstrInfo &TII = + *static_cast<const MSP430InstrInfo *>(MF.getSubtarget().getInstrInfo()); + + MachineBasicBlock::iterator MBBI = MBB.begin(); + DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); + + // Get the number of bytes to allocate from the FrameInfo. + uint64_t StackSize = MFI.getStackSize(); + + uint64_t NumBytes = 0; + if (hasFP(MF)) { + // Calculate required stack adjustment + uint64_t FrameSize = StackSize - 2; + NumBytes = FrameSize - MSP430FI->getCalleeSavedFrameSize(); + + // Get the offset of the stack slot for the EBP register... which is + // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. + // Update the frame offset adjustment. + MFI.setOffsetAdjustment(-NumBytes); + + // Save FP into the appropriate stack slot... + BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) + .addReg(MSP430::FP, RegState::Kill); + + // Update FP with the new base value... + BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP) + .addReg(MSP430::SP); + + // Mark the FramePtr as live-in in every block except the entry. + for (MachineFunction::iterator I = std::next(MF.begin()), E = MF.end(); + I != E; ++I) + I->addLiveIn(MSP430::FP); + + } else + NumBytes = StackSize - MSP430FI->getCalleeSavedFrameSize(); + + // Skip the callee-saved push instructions. + while (MBBI != MBB.end() && (MBBI->getOpcode() == MSP430::PUSH16r)) + ++MBBI; + + if (MBBI != MBB.end()) + DL = MBBI->getDebugLoc(); + + if (NumBytes) { // adjust stack pointer: SP -= numbytes + // If there is an SUB16ri of SP immediately before this instruction, merge + // the two. + //NumBytes -= mergeSPUpdates(MBB, MBBI, true); + // If there is an ADD16ri or SUB16ri of SP immediately after this + // instruction, merge the two instructions. + // mergeSPUpdatesDown(MBB, MBBI, &NumBytes); + + if (NumBytes) { + MachineInstr *MI = + BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP) + .addReg(MSP430::SP).addImm(NumBytes); + // The SRW implicit def is dead. + MI->getOperand(3).setIsDead(); + } + } +} + +void MSP430FrameLowering::emitEpilogue(MachineFunction &MF, + MachineBasicBlock &MBB) const { + const MachineFrameInfo &MFI = MF.getFrameInfo(); + MSP430MachineFunctionInfo *MSP430FI = MF.getInfo<MSP430MachineFunctionInfo>(); + const MSP430InstrInfo &TII = + *static_cast<const MSP430InstrInfo *>(MF.getSubtarget().getInstrInfo()); + + MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); + unsigned RetOpcode = MBBI->getOpcode(); + DebugLoc DL = MBBI->getDebugLoc(); + + switch (RetOpcode) { + case MSP430::RET: + case MSP430::RETI: break; // These are ok + default: + llvm_unreachable("Can only insert epilog into returning blocks"); + } + + // Get the number of bytes to allocate from the FrameInfo + uint64_t StackSize = MFI.getStackSize(); + unsigned CSSize = MSP430FI->getCalleeSavedFrameSize(); + uint64_t NumBytes = 0; + + if (hasFP(MF)) { + // Calculate required stack adjustment + uint64_t FrameSize = StackSize - 2; + NumBytes = FrameSize - CSSize; + + // pop FP. + BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP); + } else + NumBytes = StackSize - CSSize; + + // Skip the callee-saved pop instructions. + while (MBBI != MBB.begin()) { + MachineBasicBlock::iterator PI = std::prev(MBBI); + unsigned Opc = PI->getOpcode(); + if (Opc != MSP430::POP16r && !PI->isTerminator()) + break; + --MBBI; + } + + DL = MBBI->getDebugLoc(); + + // If there is an ADD16ri or SUB16ri of SP immediately before this + // instruction, merge the two instructions. + //if (NumBytes || MFI.hasVarSizedObjects()) + // mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes); + + if (MFI.hasVarSizedObjects()) { + BuildMI(MBB, MBBI, DL, + TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::FP); + if (CSSize) { + MachineInstr *MI = + BuildMI(MBB, MBBI, DL, + TII.get(MSP430::SUB16ri), MSP430::SP) + .addReg(MSP430::SP).addImm(CSSize); + // The SRW implicit def is dead. + MI->getOperand(3).setIsDead(); + } + } else { + // adjust stack pointer back: SP += numbytes + if (NumBytes) { + MachineInstr *MI = + BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP) + .addReg(MSP430::SP).addImm(NumBytes); + // The SRW implicit def is dead. + MI->getOperand(3).setIsDead(); + } + } +} + +// FIXME: Can we eleminate these in favour of generic code? +bool +MSP430FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector<CalleeSavedInfo> &CSI, + const TargetRegisterInfo *TRI) const { + if (CSI.empty()) + return false; + + DebugLoc DL; + if (MI != MBB.end()) DL = MI->getDebugLoc(); + + MachineFunction &MF = *MBB.getParent(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); + MSP430MachineFunctionInfo *MFI = MF.getInfo<MSP430MachineFunctionInfo>(); + MFI->setCalleeSavedFrameSize(CSI.size() * 2); + + for (unsigned i = CSI.size(); i != 0; --i) { + unsigned Reg = CSI[i-1].getReg(); + // Add the callee-saved register as live-in. It's killed at the spill. + MBB.addLiveIn(Reg); + BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r)) + .addReg(Reg, RegState::Kill); + } + return true; +} + +bool +MSP430FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector<CalleeSavedInfo> &CSI, + const TargetRegisterInfo *TRI) const { + if (CSI.empty()) + return false; + + DebugLoc DL; + if (MI != MBB.end()) DL = MI->getDebugLoc(); + + MachineFunction &MF = *MBB.getParent(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); + + for (unsigned i = 0, e = CSI.size(); i != e; ++i) + BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg()); + + return true; +} + +MachineBasicBlock::iterator MSP430FrameLowering::eliminateCallFramePseudoInstr( + MachineFunction &MF, MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const { + const MSP430InstrInfo &TII = + *static_cast<const MSP430InstrInfo *>(MF.getSubtarget().getInstrInfo()); + unsigned StackAlign = getStackAlignment(); + + if (!hasReservedCallFrame(MF)) { + // If the stack pointer can be changed after prologue, turn the + // adjcallstackup instruction into a 'sub SP, <amt>' and the + // adjcallstackdown instruction into 'add SP, <amt>' + // TODO: consider using push / pop instead of sub + store / add + MachineInstr &Old = *I; + uint64_t Amount = TII.getFrameSize(Old); + if (Amount != 0) { + // We need to keep the stack aligned properly. To do this, we round the + // amount of space needed for the outgoing arguments up to the next + // alignment boundary. + Amount = (Amount+StackAlign-1)/StackAlign*StackAlign; + + MachineInstr *New = nullptr; + if (Old.getOpcode() == TII.getCallFrameSetupOpcode()) { + New = + BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::SUB16ri), MSP430::SP) + .addReg(MSP430::SP) + .addImm(Amount); + } else { + assert(Old.getOpcode() == TII.getCallFrameDestroyOpcode()); + // factor out the amount the callee already popped. + Amount -= TII.getFramePoppedByCallee(Old); + if (Amount) + New = BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::ADD16ri), + MSP430::SP) + .addReg(MSP430::SP) + .addImm(Amount); + } + + if (New) { + // The SRW implicit def is dead. + New->getOperand(3).setIsDead(); + + // Replace the pseudo instruction with a new instruction... + MBB.insert(I, New); + } + } + } else if (I->getOpcode() == TII.getCallFrameDestroyOpcode()) { + // If we are performing frame pointer elimination and if the callee pops + // something off the stack pointer, add it back. + if (uint64_t CalleeAmt = TII.getFramePoppedByCallee(*I)) { + MachineInstr &Old = *I; + MachineInstr *New = + BuildMI(MF, Old.getDebugLoc(), TII.get(MSP430::SUB16ri), MSP430::SP) + .addReg(MSP430::SP) + .addImm(CalleeAmt); + // The SRW implicit def is dead. + New->getOperand(3).setIsDead(); + + MBB.insert(I, New); + } + } + + return MBB.erase(I); +} + +void +MSP430FrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, + RegScavenger *) const { + // Create a frame entry for the FP register that must be saved. + if (hasFP(MF)) { + int FrameIdx = MF.getFrameInfo().CreateFixedObject(2, -4, true); + (void)FrameIdx; + assert(FrameIdx == MF.getFrameInfo().getObjectIndexBegin() && + "Slot for FP register must be last in order to be found!"); + } +} diff --git a/contrib/llvm/lib/Target/MSP430/MSP430FrameLowering.h b/contrib/llvm/lib/Target/MSP430/MSP430FrameLowering.h new file mode 100644 index 000000000000..f77de18b4d16 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430FrameLowering.h @@ -0,0 +1,54 @@ +//==- MSP430FrameLowering.h - Define frame lowering for MSP430 --*- C++ -*--==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_MSP430_MSP430FRAMELOWERING_H +#define LLVM_LIB_TARGET_MSP430_MSP430FRAMELOWERING_H + +#include "MSP430.h" +#include "llvm/Target/TargetFrameLowering.h" + +namespace llvm { +class MSP430FrameLowering : public TargetFrameLowering { +protected: + +public: + explicit MSP430FrameLowering() + : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 2, -2, 2) {} + + /// emitProlog/emitEpilog - These methods insert prolog and epilog code into + /// the function. + void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override; + void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; + + MachineBasicBlock::iterator + eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const override; + + bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector<CalleeSavedInfo> &CSI, + const TargetRegisterInfo *TRI) const override; + bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + const std::vector<CalleeSavedInfo> &CSI, + const TargetRegisterInfo *TRI) const override; + + bool hasFP(const MachineFunction &MF) const override; + bool hasReservedCallFrame(const MachineFunction &MF) const override; + void processFunctionBeforeFrameFinalized(MachineFunction &MF, + RegScavenger *RS = nullptr) const override; +}; + +} // End llvm namespace + +#endif diff --git a/contrib/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/contrib/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp new file mode 100644 index 000000000000..0b02f79f472a --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp @@ -0,0 +1,471 @@ +//===-- MSP430ISelDAGToDAG.cpp - A dag to dag inst selector for MSP430 ----===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines an instruction selector for the MSP430 target. +// +//===----------------------------------------------------------------------===// + +#include "MSP430.h" +#include "MSP430TargetMachine.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/SelectionDAG.h" +#include "llvm/CodeGen/SelectionDAGISel.h" +#include "llvm/IR/CallingConv.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/DerivedTypes.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/Intrinsics.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetLowering.h" +using namespace llvm; + +#define DEBUG_TYPE "msp430-isel" + +namespace { + struct MSP430ISelAddressMode { + enum { + RegBase, + FrameIndexBase + } BaseType; + + struct { // This is really a union, discriminated by BaseType! + SDValue Reg; + int FrameIndex; + } Base; + + int16_t Disp; + const GlobalValue *GV; + const Constant *CP; + const BlockAddress *BlockAddr; + const char *ES; + int JT; + unsigned Align; // CP alignment. + + MSP430ISelAddressMode() + : BaseType(RegBase), Disp(0), GV(nullptr), CP(nullptr), + BlockAddr(nullptr), ES(nullptr), JT(-1), Align(0) { + } + + bool hasSymbolicDisplacement() const { + return GV != nullptr || CP != nullptr || ES != nullptr || JT != -1; + } + +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) + LLVM_DUMP_METHOD void dump() { + errs() << "MSP430ISelAddressMode " << this << '\n'; + if (BaseType == RegBase && Base.Reg.getNode() != nullptr) { + errs() << "Base.Reg "; + Base.Reg.getNode()->dump(); + } else if (BaseType == FrameIndexBase) { + errs() << " Base.FrameIndex " << Base.FrameIndex << '\n'; + } + errs() << " Disp " << Disp << '\n'; + if (GV) { + errs() << "GV "; + GV->dump(); + } else if (CP) { + errs() << " CP "; + CP->dump(); + errs() << " Align" << Align << '\n'; + } else if (ES) { + errs() << "ES "; + errs() << ES << '\n'; + } else if (JT != -1) + errs() << " JT" << JT << " Align" << Align << '\n'; + } +#endif + }; +} + +/// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine +/// instructions for SelectionDAG operations. +/// +namespace { + class MSP430DAGToDAGISel : public SelectionDAGISel { + public: + MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel) + : SelectionDAGISel(TM, OptLevel) {} + + StringRef getPassName() const override { + return "MSP430 DAG->DAG Pattern Instruction Selection"; + } + + bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM); + bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM); + bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM); + + bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, + std::vector<SDValue> &OutOps) override; + + // Include the pieces autogenerated from the target description. + #include "MSP430GenDAGISel.inc" + + private: + void Select(SDNode *N) override; + bool tryIndexedLoad(SDNode *Op); + bool tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, unsigned Opc8, + unsigned Opc16); + + bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp); + }; +} // end anonymous namespace + +/// createMSP430ISelDag - This pass converts a legalized DAG into a +/// MSP430-specific DAG, ready for instruction scheduling. +/// +FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM, + CodeGenOpt::Level OptLevel) { + return new MSP430DAGToDAGISel(TM, OptLevel); +} + + +/// MatchWrapper - Try to match MSP430ISD::Wrapper node into an addressing mode. +/// These wrap things that will resolve down into a symbol reference. If no +/// match is possible, this returns true, otherwise it returns false. +bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) { + // If the addressing mode already has a symbol as the displacement, we can + // never match another symbol. + if (AM.hasSymbolicDisplacement()) + return true; + + SDValue N0 = N.getOperand(0); + + if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) { + AM.GV = G->getGlobal(); + AM.Disp += G->getOffset(); + //AM.SymbolFlags = G->getTargetFlags(); + } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) { + AM.CP = CP->getConstVal(); + AM.Align = CP->getAlignment(); + AM.Disp += CP->getOffset(); + //AM.SymbolFlags = CP->getTargetFlags(); + } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) { + AM.ES = S->getSymbol(); + //AM.SymbolFlags = S->getTargetFlags(); + } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) { + AM.JT = J->getIndex(); + //AM.SymbolFlags = J->getTargetFlags(); + } else { + AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress(); + //AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags(); + } + return false; +} + +/// MatchAddressBase - Helper for MatchAddress. Add the specified node to the +/// specified addressing mode without any further recursion. +bool MSP430DAGToDAGISel::MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) { + // Is the base register already occupied? + if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) { + // If so, we cannot select it. + return true; + } + + // Default, generate it as a register. + AM.BaseType = MSP430ISelAddressMode::RegBase; + AM.Base.Reg = N; + return false; +} + +bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) { + DEBUG(errs() << "MatchAddress: "; AM.dump()); + + switch (N.getOpcode()) { + default: break; + case ISD::Constant: { + uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue(); + AM.Disp += Val; + return false; + } + + case MSP430ISD::Wrapper: + if (!MatchWrapper(N, AM)) + return false; + break; + + case ISD::FrameIndex: + if (AM.BaseType == MSP430ISelAddressMode::RegBase + && AM.Base.Reg.getNode() == nullptr) { + AM.BaseType = MSP430ISelAddressMode::FrameIndexBase; + AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex(); + return false; + } + break; + + case ISD::ADD: { + MSP430ISelAddressMode Backup = AM; + if (!MatchAddress(N.getNode()->getOperand(0), AM) && + !MatchAddress(N.getNode()->getOperand(1), AM)) + return false; + AM = Backup; + if (!MatchAddress(N.getNode()->getOperand(1), AM) && + !MatchAddress(N.getNode()->getOperand(0), AM)) + return false; + AM = Backup; + + break; + } + + case ISD::OR: + // Handle "X | C" as "X + C" iff X is known to have C bits clear. + if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) { + MSP430ISelAddressMode Backup = AM; + uint64_t Offset = CN->getSExtValue(); + // Start with the LHS as an addr mode. + if (!MatchAddress(N.getOperand(0), AM) && + // Address could not have picked a GV address for the displacement. + AM.GV == nullptr && + // Check to see if the LHS & C is zero. + CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) { + AM.Disp += Offset; + return false; + } + AM = Backup; + } + break; + } + + return MatchAddressBase(N, AM); +} + +/// SelectAddr - returns true if it is able pattern match an addressing mode. +/// It returns the operands which make up the maximal addressing mode it can +/// match by reference. +bool MSP430DAGToDAGISel::SelectAddr(SDValue N, + SDValue &Base, SDValue &Disp) { + MSP430ISelAddressMode AM; + + if (MatchAddress(N, AM)) + return false; + + EVT VT = N.getValueType(); + if (AM.BaseType == MSP430ISelAddressMode::RegBase) { + if (!AM.Base.Reg.getNode()) + AM.Base.Reg = CurDAG->getRegister(0, VT); + } + + Base = (AM.BaseType == MSP430ISelAddressMode::FrameIndexBase) + ? CurDAG->getTargetFrameIndex( + AM.Base.FrameIndex, + getTargetLowering()->getPointerTy(CurDAG->getDataLayout())) + : AM.Base.Reg; + + if (AM.GV) + Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(N), + MVT::i16, AM.Disp, + 0/*AM.SymbolFlags*/); + else if (AM.CP) + Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16, + AM.Align, AM.Disp, 0/*AM.SymbolFlags*/); + else if (AM.ES) + Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/); + else if (AM.JT != -1) + Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/); + else if (AM.BlockAddr) + Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, 0, + 0/*AM.SymbolFlags*/); + else + Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(N), MVT::i16); + + return true; +} + +bool MSP430DAGToDAGISel:: +SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, + std::vector<SDValue> &OutOps) { + SDValue Op0, Op1; + switch (ConstraintID) { + default: return true; + case InlineAsm::Constraint_m: // memory + if (!SelectAddr(Op, Op0, Op1)) + return true; + break; + } + + OutOps.push_back(Op0); + OutOps.push_back(Op1); + return false; +} + +static bool isValidIndexedLoad(const LoadSDNode *LD) { + ISD::MemIndexedMode AM = LD->getAddressingMode(); + if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD) + return false; + + EVT VT = LD->getMemoryVT(); + + switch (VT.getSimpleVT().SimpleTy) { + case MVT::i8: + // Sanity check + if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 1) + return false; + + break; + case MVT::i16: + // Sanity check + if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 2) + return false; + + break; + default: + return false; + } + + return true; +} + +bool MSP430DAGToDAGISel::tryIndexedLoad(SDNode *N) { + LoadSDNode *LD = cast<LoadSDNode>(N); + if (!isValidIndexedLoad(LD)) + return false; + + MVT VT = LD->getMemoryVT().getSimpleVT(); + + unsigned Opcode = 0; + switch (VT.SimpleTy) { + case MVT::i8: + Opcode = MSP430::MOV8rm_POST; + break; + case MVT::i16: + Opcode = MSP430::MOV16rm_POST; + break; + default: + return false; + } + + ReplaceNode(N, + CurDAG->getMachineNode(Opcode, SDLoc(N), VT, MVT::i16, MVT::Other, + LD->getBasePtr(), LD->getChain())); + return true; +} + +bool MSP430DAGToDAGISel::tryIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, + unsigned Opc8, unsigned Opc16) { + if (N1.getOpcode() == ISD::LOAD && + N1.hasOneUse() && + IsLegalToFold(N1, Op, Op, OptLevel)) { + LoadSDNode *LD = cast<LoadSDNode>(N1); + if (!isValidIndexedLoad(LD)) + return false; + + MVT VT = LD->getMemoryVT().getSimpleVT(); + unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8); + MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1); + MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand(); + SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() }; + SDNode *ResNode = + CurDAG->SelectNodeTo(Op, Opc, VT, MVT::i16, MVT::Other, Ops0); + cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1); + // Transfer chain. + ReplaceUses(SDValue(N1.getNode(), 2), SDValue(ResNode, 2)); + // Transfer writeback. + ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1)); + return true; + } + + return false; +} + + +void MSP430DAGToDAGISel::Select(SDNode *Node) { + SDLoc dl(Node); + + // Dump information about the Node being selected + DEBUG(errs() << "Selecting: "); + DEBUG(Node->dump(CurDAG)); + DEBUG(errs() << "\n"); + + // If we have a custom node, we already have selected! + if (Node->isMachineOpcode()) { + DEBUG(errs() << "== "; + Node->dump(CurDAG); + errs() << "\n"); + Node->setNodeId(-1); + return; + } + + // Few custom selection stuff. + switch (Node->getOpcode()) { + default: break; + case ISD::FrameIndex: { + assert(Node->getValueType(0) == MVT::i16); + int FI = cast<FrameIndexSDNode>(Node)->getIndex(); + SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16); + if (Node->hasOneUse()) { + CurDAG->SelectNodeTo(Node, MSP430::ADDframe, MVT::i16, TFI, + CurDAG->getTargetConstant(0, dl, MVT::i16)); + return; + } + ReplaceNode(Node, CurDAG->getMachineNode( + MSP430::ADDframe, dl, MVT::i16, TFI, + CurDAG->getTargetConstant(0, dl, MVT::i16))); + return; + } + case ISD::LOAD: + if (tryIndexedLoad(Node)) + return; + // Other cases are autogenerated. + break; + case ISD::ADD: + if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1), + MSP430::ADD8rm_POST, MSP430::ADD16rm_POST)) + return; + else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0), + MSP430::ADD8rm_POST, MSP430::ADD16rm_POST)) + return; + + // Other cases are autogenerated. + break; + case ISD::SUB: + if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1), + MSP430::SUB8rm_POST, MSP430::SUB16rm_POST)) + return; + + // Other cases are autogenerated. + break; + case ISD::AND: + if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1), + MSP430::AND8rm_POST, MSP430::AND16rm_POST)) + return; + else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0), + MSP430::AND8rm_POST, MSP430::AND16rm_POST)) + return; + + // Other cases are autogenerated. + break; + case ISD::OR: + if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1), + MSP430::OR8rm_POST, MSP430::OR16rm_POST)) + return; + else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0), + MSP430::OR8rm_POST, MSP430::OR16rm_POST)) + return; + + // Other cases are autogenerated. + break; + case ISD::XOR: + if (tryIndexedBinOp(Node, Node->getOperand(0), Node->getOperand(1), + MSP430::XOR8rm_POST, MSP430::XOR16rm_POST)) + return; + else if (tryIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0), + MSP430::XOR8rm_POST, MSP430::XOR16rm_POST)) + return; + + // Other cases are autogenerated. + break; + } + + // Select the default instruction + SelectCode(Node); +} diff --git a/contrib/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/contrib/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp new file mode 100644 index 000000000000..dae14fd301ee --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -0,0 +1,1565 @@ +//===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the MSP430TargetLowering class. +// +//===----------------------------------------------------------------------===// + +#include "MSP430ISelLowering.h" +#include "MSP430.h" +#include "MSP430MachineFunctionInfo.h" +#include "MSP430Subtarget.h" +#include "MSP430TargetMachine.h" +#include "llvm/CodeGen/CallingConvLower.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/SelectionDAGISel.h" +#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" +#include "llvm/CodeGen/ValueTypes.h" +#include "llvm/IR/CallingConv.h" +#include "llvm/IR/DerivedTypes.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/GlobalAlias.h" +#include "llvm/IR/GlobalVariable.h" +#include "llvm/IR/Intrinsics.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" +using namespace llvm; + +#define DEBUG_TYPE "msp430-lower" + +MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM, + const MSP430Subtarget &STI) + : TargetLowering(TM) { + + // Set up the register classes. + addRegisterClass(MVT::i8, &MSP430::GR8RegClass); + addRegisterClass(MVT::i16, &MSP430::GR16RegClass); + + // Compute derived properties from the register classes + computeRegisterProperties(STI.getRegisterInfo()); + + // Provide all sorts of operation actions + setStackPointerRegisterToSaveRestore(MSP430::SP); + setBooleanContents(ZeroOrOneBooleanContent); + setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? + + // We have post-incremented loads / stores. + setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); + setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); + + for (MVT VT : MVT::integer_valuetypes()) { + setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); + setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); + } + + // We don't have any truncstores + setTruncStoreAction(MVT::i16, MVT::i8, Expand); + + setOperationAction(ISD::SRA, MVT::i8, Custom); + setOperationAction(ISD::SHL, MVT::i8, Custom); + setOperationAction(ISD::SRL, MVT::i8, Custom); + setOperationAction(ISD::SRA, MVT::i16, Custom); + setOperationAction(ISD::SHL, MVT::i16, Custom); + setOperationAction(ISD::SRL, MVT::i16, Custom); + setOperationAction(ISD::ROTL, MVT::i8, Expand); + setOperationAction(ISD::ROTR, MVT::i8, Expand); + setOperationAction(ISD::ROTL, MVT::i16, Expand); + setOperationAction(ISD::ROTR, MVT::i16, Expand); + setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); + setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom); + setOperationAction(ISD::BlockAddress, MVT::i16, Custom); + setOperationAction(ISD::BR_JT, MVT::Other, Expand); + setOperationAction(ISD::BR_CC, MVT::i8, Custom); + setOperationAction(ISD::BR_CC, MVT::i16, Custom); + setOperationAction(ISD::BRCOND, MVT::Other, Expand); + setOperationAction(ISD::SETCC, MVT::i8, Custom); + setOperationAction(ISD::SETCC, MVT::i16, Custom); + setOperationAction(ISD::SELECT, MVT::i8, Expand); + setOperationAction(ISD::SELECT, MVT::i16, Expand); + setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); + setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); + setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom); + setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand); + + setOperationAction(ISD::CTTZ, MVT::i8, Expand); + setOperationAction(ISD::CTTZ, MVT::i16, Expand); + setOperationAction(ISD::CTLZ, MVT::i8, Expand); + setOperationAction(ISD::CTLZ, MVT::i16, Expand); + setOperationAction(ISD::CTPOP, MVT::i8, Expand); + setOperationAction(ISD::CTPOP, MVT::i16, Expand); + + setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand); + setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand); + setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand); + setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand); + setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand); + setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand); + + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); + + // FIXME: Implement efficiently multiplication by a constant + setOperationAction(ISD::MUL, MVT::i8, Promote); + setOperationAction(ISD::MULHS, MVT::i8, Promote); + setOperationAction(ISD::MULHU, MVT::i8, Promote); + setOperationAction(ISD::SMUL_LOHI, MVT::i8, Promote); + setOperationAction(ISD::UMUL_LOHI, MVT::i8, Promote); + setOperationAction(ISD::MUL, MVT::i16, LibCall); + setOperationAction(ISD::MULHS, MVT::i16, Expand); + setOperationAction(ISD::MULHU, MVT::i16, Expand); + setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand); + setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand); + + setOperationAction(ISD::UDIV, MVT::i8, Promote); + setOperationAction(ISD::UDIVREM, MVT::i8, Promote); + setOperationAction(ISD::UREM, MVT::i8, Promote); + setOperationAction(ISD::SDIV, MVT::i8, Promote); + setOperationAction(ISD::SDIVREM, MVT::i8, Promote); + setOperationAction(ISD::SREM, MVT::i8, Promote); + setOperationAction(ISD::UDIV, MVT::i16, LibCall); + setOperationAction(ISD::UDIVREM, MVT::i16, Expand); + setOperationAction(ISD::UREM, MVT::i16, LibCall); + setOperationAction(ISD::SDIV, MVT::i16, LibCall); + setOperationAction(ISD::SDIVREM, MVT::i16, Expand); + setOperationAction(ISD::SREM, MVT::i16, LibCall); + + // varargs support + setOperationAction(ISD::VASTART, MVT::Other, Custom); + setOperationAction(ISD::VAARG, MVT::Other, Expand); + setOperationAction(ISD::VAEND, MVT::Other, Expand); + setOperationAction(ISD::VACOPY, MVT::Other, Expand); + setOperationAction(ISD::JumpTable, MVT::i16, Custom); + + // EABI Libcalls - EABI Section 6.2 + const struct { + const RTLIB::Libcall Op; + const char * const Name; + const ISD::CondCode Cond; + } LibraryCalls[] = { + // Floating point conversions - EABI Table 6 + { RTLIB::FPROUND_F64_F32, "__mspabi_cvtdf", ISD::SETCC_INVALID }, + { RTLIB::FPEXT_F32_F64, "__mspabi_cvtfd", ISD::SETCC_INVALID }, + // The following is NOT implemented in libgcc + //{ RTLIB::FPTOSINT_F64_I16, "__mspabi_fixdi", ISD::SETCC_INVALID }, + { RTLIB::FPTOSINT_F64_I32, "__mspabi_fixdli", ISD::SETCC_INVALID }, + { RTLIB::FPTOSINT_F64_I64, "__mspabi_fixdlli", ISD::SETCC_INVALID }, + // The following is NOT implemented in libgcc + //{ RTLIB::FPTOUINT_F64_I16, "__mspabi_fixdu", ISD::SETCC_INVALID }, + { RTLIB::FPTOUINT_F64_I32, "__mspabi_fixdul", ISD::SETCC_INVALID }, + { RTLIB::FPTOUINT_F64_I64, "__mspabi_fixdull", ISD::SETCC_INVALID }, + // The following is NOT implemented in libgcc + //{ RTLIB::FPTOSINT_F32_I16, "__mspabi_fixfi", ISD::SETCC_INVALID }, + { RTLIB::FPTOSINT_F32_I32, "__mspabi_fixfli", ISD::SETCC_INVALID }, + { RTLIB::FPTOSINT_F32_I64, "__mspabi_fixflli", ISD::SETCC_INVALID }, + // The following is NOT implemented in libgcc + //{ RTLIB::FPTOUINT_F32_I16, "__mspabi_fixfu", ISD::SETCC_INVALID }, + { RTLIB::FPTOUINT_F32_I32, "__mspabi_fixful", ISD::SETCC_INVALID }, + { RTLIB::FPTOUINT_F32_I64, "__mspabi_fixfull", ISD::SETCC_INVALID }, + // TODO The following IS implemented in libgcc + //{ RTLIB::SINTTOFP_I16_F64, "__mspabi_fltid", ISD::SETCC_INVALID }, + { RTLIB::SINTTOFP_I32_F64, "__mspabi_fltlid", ISD::SETCC_INVALID }, + // TODO The following IS implemented in libgcc but is not in the EABI + { RTLIB::SINTTOFP_I64_F64, "__mspabi_fltllid", ISD::SETCC_INVALID }, + // TODO The following IS implemented in libgcc + //{ RTLIB::UINTTOFP_I16_F64, "__mspabi_fltud", ISD::SETCC_INVALID }, + { RTLIB::UINTTOFP_I32_F64, "__mspabi_fltuld", ISD::SETCC_INVALID }, + // The following IS implemented in libgcc but is not in the EABI + { RTLIB::UINTTOFP_I64_F64, "__mspabi_fltulld", ISD::SETCC_INVALID }, + // TODO The following IS implemented in libgcc + //{ RTLIB::SINTTOFP_I16_F32, "__mspabi_fltif", ISD::SETCC_INVALID }, + { RTLIB::SINTTOFP_I32_F32, "__mspabi_fltlif", ISD::SETCC_INVALID }, + // TODO The following IS implemented in libgcc but is not in the EABI + { RTLIB::SINTTOFP_I64_F32, "__mspabi_fltllif", ISD::SETCC_INVALID }, + // TODO The following IS implemented in libgcc + //{ RTLIB::UINTTOFP_I16_F32, "__mspabi_fltuf", ISD::SETCC_INVALID }, + { RTLIB::UINTTOFP_I32_F32, "__mspabi_fltulf", ISD::SETCC_INVALID }, + // The following IS implemented in libgcc but is not in the EABI + { RTLIB::UINTTOFP_I64_F32, "__mspabi_fltullf", ISD::SETCC_INVALID }, + + // Floating point comparisons - EABI Table 7 + { RTLIB::OEQ_F64, "__mspabi_cmpd", ISD::SETEQ }, + { RTLIB::UNE_F64, "__mspabi_cmpd", ISD::SETNE }, + { RTLIB::OGE_F64, "__mspabi_cmpd", ISD::SETGE }, + { RTLIB::OLT_F64, "__mspabi_cmpd", ISD::SETLT }, + { RTLIB::OLE_F64, "__mspabi_cmpd", ISD::SETLE }, + { RTLIB::OGT_F64, "__mspabi_cmpd", ISD::SETGT }, + { RTLIB::OEQ_F32, "__mspabi_cmpf", ISD::SETEQ }, + { RTLIB::UNE_F32, "__mspabi_cmpf", ISD::SETNE }, + { RTLIB::OGE_F32, "__mspabi_cmpf", ISD::SETGE }, + { RTLIB::OLT_F32, "__mspabi_cmpf", ISD::SETLT }, + { RTLIB::OLE_F32, "__mspabi_cmpf", ISD::SETLE }, + { RTLIB::OGT_F32, "__mspabi_cmpf", ISD::SETGT }, + + // Floating point arithmetic - EABI Table 8 + { RTLIB::ADD_F64, "__mspabi_addd", ISD::SETCC_INVALID }, + { RTLIB::ADD_F32, "__mspabi_addf", ISD::SETCC_INVALID }, + { RTLIB::DIV_F64, "__mspabi_divd", ISD::SETCC_INVALID }, + { RTLIB::DIV_F32, "__mspabi_divf", ISD::SETCC_INVALID }, + { RTLIB::MUL_F64, "__mspabi_mpyd", ISD::SETCC_INVALID }, + { RTLIB::MUL_F32, "__mspabi_mpyf", ISD::SETCC_INVALID }, + { RTLIB::SUB_F64, "__mspabi_subd", ISD::SETCC_INVALID }, + { RTLIB::SUB_F32, "__mspabi_subf", ISD::SETCC_INVALID }, + // The following are NOT implemented in libgcc + // { RTLIB::NEG_F64, "__mspabi_negd", ISD::SETCC_INVALID }, + // { RTLIB::NEG_F32, "__mspabi_negf", ISD::SETCC_INVALID }, + + // TODO: SLL/SRA/SRL are in libgcc, RLL isn't + + // Universal Integer Operations - EABI Table 9 + { RTLIB::SDIV_I16, "__mspabi_divi", ISD::SETCC_INVALID }, + { RTLIB::SDIV_I32, "__mspabi_divli", ISD::SETCC_INVALID }, + { RTLIB::SDIV_I64, "__mspabi_divlli", ISD::SETCC_INVALID }, + { RTLIB::UDIV_I16, "__mspabi_divu", ISD::SETCC_INVALID }, + { RTLIB::UDIV_I32, "__mspabi_divul", ISD::SETCC_INVALID }, + { RTLIB::UDIV_I64, "__mspabi_divull", ISD::SETCC_INVALID }, + { RTLIB::SREM_I16, "__mspabi_remi", ISD::SETCC_INVALID }, + { RTLIB::SREM_I32, "__mspabi_remli", ISD::SETCC_INVALID }, + { RTLIB::SREM_I64, "__mspabi_remlli", ISD::SETCC_INVALID }, + { RTLIB::UREM_I16, "__mspabi_remu", ISD::SETCC_INVALID }, + { RTLIB::UREM_I32, "__mspabi_remul", ISD::SETCC_INVALID }, + { RTLIB::UREM_I64, "__mspabi_remull", ISD::SETCC_INVALID }, + + }; + + for (const auto &LC : LibraryCalls) { + setLibcallName(LC.Op, LC.Name); + if (LC.Cond != ISD::SETCC_INVALID) + setCmpLibcallCC(LC.Op, LC.Cond); + } + + if (STI.hasHWMult16()) { + const struct { + const RTLIB::Libcall Op; + const char * const Name; + } LibraryCalls[] = { + // Integer Multiply - EABI Table 9 + { RTLIB::MUL_I16, "__mspabi_mpyi_hw" }, + { RTLIB::MUL_I32, "__mspabi_mpyl_hw" }, + { RTLIB::MUL_I64, "__mspabi_mpyll_hw" }, + // TODO The __mspabi_mpysl*_hw functions ARE implemented in libgcc + // TODO The __mspabi_mpyul*_hw functions ARE implemented in libgcc + }; + for (const auto &LC : LibraryCalls) { + setLibcallName(LC.Op, LC.Name); + } + } else if (STI.hasHWMult32()) { + const struct { + const RTLIB::Libcall Op; + const char * const Name; + } LibraryCalls[] = { + // Integer Multiply - EABI Table 9 + { RTLIB::MUL_I16, "__mspabi_mpyi_hw" }, + { RTLIB::MUL_I32, "__mspabi_mpyl_hw32" }, + { RTLIB::MUL_I64, "__mspabi_mpyll_hw32" }, + // TODO The __mspabi_mpysl*_hw32 functions ARE implemented in libgcc + // TODO The __mspabi_mpyul*_hw32 functions ARE implemented in libgcc + }; + for (const auto &LC : LibraryCalls) { + setLibcallName(LC.Op, LC.Name); + } + } else if (STI.hasHWMultF5()) { + const struct { + const RTLIB::Libcall Op; + const char * const Name; + } LibraryCalls[] = { + // Integer Multiply - EABI Table 9 + { RTLIB::MUL_I16, "__mspabi_mpyi_f5hw" }, + { RTLIB::MUL_I32, "__mspabi_mpyl_f5hw" }, + { RTLIB::MUL_I64, "__mspabi_mpyll_f5hw" }, + // TODO The __mspabi_mpysl*_f5hw functions ARE implemented in libgcc + // TODO The __mspabi_mpyul*_f5hw functions ARE implemented in libgcc + }; + for (const auto &LC : LibraryCalls) { + setLibcallName(LC.Op, LC.Name); + } + } else { // NoHWMult + const struct { + const RTLIB::Libcall Op; + const char * const Name; + } LibraryCalls[] = { + // Integer Multiply - EABI Table 9 + { RTLIB::MUL_I16, "__mspabi_mpyi" }, + { RTLIB::MUL_I32, "__mspabi_mpyl" }, + { RTLIB::MUL_I64, "__mspabi_mpyll" }, + // The __mspabi_mpysl* functions are NOT implemented in libgcc + // The __mspabi_mpyul* functions are NOT implemented in libgcc + }; + for (const auto &LC : LibraryCalls) { + setLibcallName(LC.Op, LC.Name); + } + setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::MSP430_BUILTIN); + } + + // Several of the runtime library functions use a special calling conv + setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::MSP430_BUILTIN); + setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::MSP430_BUILTIN); + setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::MSP430_BUILTIN); + setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::MSP430_BUILTIN); + setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::MSP430_BUILTIN); + setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::MSP430_BUILTIN); + setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::MSP430_BUILTIN); + setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::MSP430_BUILTIN); + setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::MSP430_BUILTIN); + setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::MSP430_BUILTIN); + setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::MSP430_BUILTIN); + setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::MSP430_BUILTIN); + setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::MSP430_BUILTIN); + setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::MSP430_BUILTIN); + // TODO: __mspabi_srall, __mspabi_srlll, __mspabi_sllll + + setMinFunctionAlignment(1); + setPrefFunctionAlignment(2); +} + +SDValue MSP430TargetLowering::LowerOperation(SDValue Op, + SelectionDAG &DAG) const { + switch (Op.getOpcode()) { + case ISD::SHL: // FALLTHROUGH + case ISD::SRL: + case ISD::SRA: return LowerShifts(Op, DAG); + case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); + case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); + case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); + case ISD::SETCC: return LowerSETCC(Op, DAG); + case ISD::BR_CC: return LowerBR_CC(Op, DAG); + case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); + case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); + case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); + case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); + case ISD::VASTART: return LowerVASTART(Op, DAG); + case ISD::JumpTable: return LowerJumpTable(Op, DAG); + default: + llvm_unreachable("unimplemented operand"); + } +} + +//===----------------------------------------------------------------------===// +// MSP430 Inline Assembly Support +//===----------------------------------------------------------------------===// + +/// getConstraintType - Given a constraint letter, return the type of +/// constraint it is for this target. +TargetLowering::ConstraintType +MSP430TargetLowering::getConstraintType(StringRef Constraint) const { + if (Constraint.size() == 1) { + switch (Constraint[0]) { + case 'r': + return C_RegisterClass; + default: + break; + } + } + return TargetLowering::getConstraintType(Constraint); +} + +std::pair<unsigned, const TargetRegisterClass *> +MSP430TargetLowering::getRegForInlineAsmConstraint( + const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { + if (Constraint.size() == 1) { + // GCC Constraint Letters + switch (Constraint[0]) { + default: break; + case 'r': // GENERAL_REGS + if (VT == MVT::i8) + return std::make_pair(0U, &MSP430::GR8RegClass); + + return std::make_pair(0U, &MSP430::GR16RegClass); + } + } + + return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); +} + +//===----------------------------------------------------------------------===// +// Calling Convention Implementation +//===----------------------------------------------------------------------===// + +#include "MSP430GenCallingConv.inc" + +/// For each argument in a function store the number of pieces it is composed +/// of. +template<typename ArgT> +static void ParseFunctionArgs(const SmallVectorImpl<ArgT> &Args, + SmallVectorImpl<unsigned> &Out) { + unsigned CurrentArgIndex; + + if (Args.empty()) + return; + + CurrentArgIndex = Args[0].OrigArgIndex; + Out.push_back(0); + + for (auto &Arg : Args) { + if (CurrentArgIndex == Arg.OrigArgIndex) { + Out.back() += 1; + } else { + Out.push_back(1); + CurrentArgIndex = Arg.OrigArgIndex; + } + } +} + +static void AnalyzeVarArgs(CCState &State, + const SmallVectorImpl<ISD::OutputArg> &Outs) { + State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack); +} + +static void AnalyzeVarArgs(CCState &State, + const SmallVectorImpl<ISD::InputArg> &Ins) { + State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack); +} + +/// Analyze incoming and outgoing function arguments. We need custom C++ code +/// to handle special constraints in the ABI like reversing the order of the +/// pieces of splitted arguments. In addition, all pieces of a certain argument +/// have to be passed either using registers or the stack but never mixing both. +template<typename ArgT> +static void AnalyzeArguments(CCState &State, + SmallVectorImpl<CCValAssign> &ArgLocs, + const SmallVectorImpl<ArgT> &Args) { + static const MCPhysReg CRegList[] = { + MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15 + }; + static const unsigned CNbRegs = array_lengthof(CRegList); + static const MCPhysReg BuiltinRegList[] = { + MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, + MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15 + }; + static const unsigned BuiltinNbRegs = array_lengthof(BuiltinRegList); + + ArrayRef<MCPhysReg> RegList; + unsigned NbRegs; + + bool Builtin = (State.getCallingConv() == CallingConv::MSP430_BUILTIN); + if (Builtin) { + RegList = BuiltinRegList; + NbRegs = BuiltinNbRegs; + } else { + RegList = CRegList; + NbRegs = CNbRegs; + } + + if (State.isVarArg()) { + AnalyzeVarArgs(State, Args); + return; + } + + SmallVector<unsigned, 4> ArgsParts; + ParseFunctionArgs(Args, ArgsParts); + + if (Builtin) { + assert(ArgsParts.size() == 2 && + "Builtin calling convention requires two arguments"); + } + + unsigned RegsLeft = NbRegs; + bool UsedStack = false; + unsigned ValNo = 0; + + for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) { + MVT ArgVT = Args[ValNo].VT; + ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags; + MVT LocVT = ArgVT; + CCValAssign::LocInfo LocInfo = CCValAssign::Full; + + // Promote i8 to i16 + if (LocVT == MVT::i8) { + LocVT = MVT::i16; + if (ArgFlags.isSExt()) + LocInfo = CCValAssign::SExt; + else if (ArgFlags.isZExt()) + LocInfo = CCValAssign::ZExt; + else + LocInfo = CCValAssign::AExt; + } + + // Handle byval arguments + if (ArgFlags.isByVal()) { + State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags); + continue; + } + + unsigned Parts = ArgsParts[i]; + + if (Builtin) { + assert(Parts == 4 && + "Builtin calling convention requires 64-bit arguments"); + } + + if (!UsedStack && Parts == 2 && RegsLeft == 1) { + // Special case for 32-bit register split, see EABI section 3.3.3 + unsigned Reg = State.AllocateReg(RegList); + State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo)); + RegsLeft -= 1; + + UsedStack = true; + CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State); + } else if (Parts <= RegsLeft) { + for (unsigned j = 0; j < Parts; j++) { + unsigned Reg = State.AllocateReg(RegList); + State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo)); + RegsLeft--; + } + } else { + UsedStack = true; + for (unsigned j = 0; j < Parts; j++) + CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State); + } + } +} + +static void AnalyzeRetResult(CCState &State, + const SmallVectorImpl<ISD::InputArg> &Ins) { + State.AnalyzeCallResult(Ins, RetCC_MSP430); +} + +static void AnalyzeRetResult(CCState &State, + const SmallVectorImpl<ISD::OutputArg> &Outs) { + State.AnalyzeReturn(Outs, RetCC_MSP430); +} + +template<typename ArgT> +static void AnalyzeReturnValues(CCState &State, + SmallVectorImpl<CCValAssign> &RVLocs, + const SmallVectorImpl<ArgT> &Args) { + AnalyzeRetResult(State, Args); +} + +SDValue MSP430TargetLowering::LowerFormalArguments( + SDValue Chain, CallingConv::ID CallConv, bool isVarArg, + const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, + SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { + + switch (CallConv) { + default: + llvm_unreachable("Unsupported calling convention"); + case CallingConv::C: + case CallingConv::Fast: + return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals); + case CallingConv::MSP430_INTR: + if (Ins.empty()) + return Chain; + report_fatal_error("ISRs cannot have arguments"); + } +} + +SDValue +MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, + SmallVectorImpl<SDValue> &InVals) const { + SelectionDAG &DAG = CLI.DAG; + SDLoc &dl = CLI.DL; + SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; + SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; + SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; + SDValue Chain = CLI.Chain; + SDValue Callee = CLI.Callee; + bool &isTailCall = CLI.IsTailCall; + CallingConv::ID CallConv = CLI.CallConv; + bool isVarArg = CLI.IsVarArg; + + // MSP430 target does not yet support tail call optimization. + isTailCall = false; + + switch (CallConv) { + default: + llvm_unreachable("Unsupported calling convention"); + case CallingConv::MSP430_BUILTIN: + case CallingConv::Fast: + case CallingConv::C: + return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall, + Outs, OutVals, Ins, dl, DAG, InVals); + case CallingConv::MSP430_INTR: + report_fatal_error("ISRs cannot be called directly"); + } +} + +/// LowerCCCArguments - transform physical registers into virtual registers and +/// generate load operations for arguments places on the stack. +// FIXME: struct return stuff +SDValue MSP430TargetLowering::LowerCCCArguments( + SDValue Chain, CallingConv::ID CallConv, bool isVarArg, + const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, + SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + MachineRegisterInfo &RegInfo = MF.getRegInfo(); + MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>(); + + // Assign locations to all of the incoming arguments. + SmallVector<CCValAssign, 16> ArgLocs; + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, + *DAG.getContext()); + AnalyzeArguments(CCInfo, ArgLocs, Ins); + + // Create frame index for the start of the first vararg value + if (isVarArg) { + unsigned Offset = CCInfo.getNextStackOffset(); + FuncInfo->setVarArgsFrameIndex(MFI.CreateFixedObject(1, Offset, true)); + } + + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &VA = ArgLocs[i]; + if (VA.isRegLoc()) { + // Arguments passed in registers + EVT RegVT = VA.getLocVT(); + switch (RegVT.getSimpleVT().SimpleTy) { + default: + { +#ifndef NDEBUG + errs() << "LowerFormalArguments Unhandled argument type: " + << RegVT.getEVTString() << "\n"; +#endif + llvm_unreachable(nullptr); + } + case MVT::i16: + unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass); + RegInfo.addLiveIn(VA.getLocReg(), VReg); + SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); + + // If this is an 8-bit value, it is really passed promoted to 16 + // bits. Insert an assert[sz]ext to capture this, then truncate to the + // right size. + if (VA.getLocInfo() == CCValAssign::SExt) + ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, + DAG.getValueType(VA.getValVT())); + else if (VA.getLocInfo() == CCValAssign::ZExt) + ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, + DAG.getValueType(VA.getValVT())); + + if (VA.getLocInfo() != CCValAssign::Full) + ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); + + InVals.push_back(ArgValue); + } + } else { + // Sanity check + assert(VA.isMemLoc()); + + SDValue InVal; + ISD::ArgFlagsTy Flags = Ins[i].Flags; + + if (Flags.isByVal()) { + int FI = MFI.CreateFixedObject(Flags.getByValSize(), + VA.getLocMemOffset(), true); + InVal = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); + } else { + // Load the argument to a virtual register + unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; + if (ObjSize > 2) { + errs() << "LowerFormalArguments Unhandled argument type: " + << EVT(VA.getLocVT()).getEVTString() + << "\n"; + } + // Create the frame index object for this incoming parameter... + int FI = MFI.CreateFixedObject(ObjSize, VA.getLocMemOffset(), true); + + // Create the SelectionDAG nodes corresponding to a load + //from this parameter + SDValue FIN = DAG.getFrameIndex(FI, MVT::i16); + InVal = DAG.getLoad( + VA.getLocVT(), dl, Chain, FIN, + MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI)); + } + + InVals.push_back(InVal); + } + } + + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + if (Ins[i].Flags.isSRet()) { + unsigned Reg = FuncInfo->getSRetReturnReg(); + if (!Reg) { + Reg = MF.getRegInfo().createVirtualRegister( + getRegClassFor(MVT::i16)); + FuncInfo->setSRetReturnReg(Reg); + } + SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]); + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); + } + } + + return Chain; +} + +bool +MSP430TargetLowering::CanLowerReturn(CallingConv::ID CallConv, + MachineFunction &MF, + bool IsVarArg, + const SmallVectorImpl<ISD::OutputArg> &Outs, + LLVMContext &Context) const { + SmallVector<CCValAssign, 16> RVLocs; + CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); + return CCInfo.CheckReturn(Outs, RetCC_MSP430); +} + +SDValue +MSP430TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, + bool isVarArg, + const SmallVectorImpl<ISD::OutputArg> &Outs, + const SmallVectorImpl<SDValue> &OutVals, + const SDLoc &dl, SelectionDAG &DAG) const { + + MachineFunction &MF = DAG.getMachineFunction(); + + // CCValAssign - represent the assignment of the return value to a location + SmallVector<CCValAssign, 16> RVLocs; + + // ISRs cannot return any value. + if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) + report_fatal_error("ISRs cannot return any value"); + + // CCState - Info about the registers and stack slot. + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, + *DAG.getContext()); + + // Analize return values. + AnalyzeReturnValues(CCInfo, RVLocs, Outs); + + SDValue Flag; + SmallVector<SDValue, 4> RetOps(1, Chain); + + // Copy the result values into the output registers. + for (unsigned i = 0; i != RVLocs.size(); ++i) { + CCValAssign &VA = RVLocs[i]; + assert(VA.isRegLoc() && "Can only return in registers!"); + + Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), + OutVals[i], Flag); + + // Guarantee that all emitted copies are stuck together, + // avoiding something bad. + Flag = Chain.getValue(1); + RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); + } + + if (MF.getFunction()->hasStructRetAttr()) { + MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>(); + unsigned Reg = FuncInfo->getSRetReturnReg(); + + if (!Reg) + llvm_unreachable("sret virtual register not created in entry block"); + + SDValue Val = + DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy(DAG.getDataLayout())); + unsigned R12 = MSP430::R12; + + Chain = DAG.getCopyToReg(Chain, dl, R12, Val, Flag); + Flag = Chain.getValue(1); + RetOps.push_back(DAG.getRegister(R12, getPointerTy(DAG.getDataLayout()))); + } + + unsigned Opc = (CallConv == CallingConv::MSP430_INTR ? + MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG); + + RetOps[0] = Chain; // Update chain. + + // Add the flag if we have it. + if (Flag.getNode()) + RetOps.push_back(Flag); + + return DAG.getNode(Opc, dl, MVT::Other, RetOps); +} + +/// LowerCCCCallTo - functions arguments are copied from virtual regs to +/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. +SDValue MSP430TargetLowering::LowerCCCCallTo( + SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, + bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, + const SmallVectorImpl<SDValue> &OutVals, + const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, + SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { + // Analyze operands of the call, assigning locations to each operand. + SmallVector<CCValAssign, 16> ArgLocs; + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, + *DAG.getContext()); + AnalyzeArguments(CCInfo, ArgLocs, Outs); + + // Get a count of how many bytes are to be pushed on the stack. + unsigned NumBytes = CCInfo.getNextStackOffset(); + auto PtrVT = getPointerTy(DAG.getDataLayout()); + + Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl); + + SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; + SmallVector<SDValue, 12> MemOpChains; + SDValue StackPtr; + + // Walk the register/memloc assignments, inserting copies/loads. + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &VA = ArgLocs[i]; + + SDValue Arg = OutVals[i]; + + // Promote the value if needed. + switch (VA.getLocInfo()) { + default: llvm_unreachable("Unknown loc info!"); + case CCValAssign::Full: break; + case CCValAssign::SExt: + Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); + break; + case CCValAssign::ZExt: + Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); + break; + case CCValAssign::AExt: + Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); + break; + } + + // Arguments that can be passed on register must be kept at RegsToPass + // vector + if (VA.isRegLoc()) { + RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); + } else { + assert(VA.isMemLoc()); + + if (!StackPtr.getNode()) + StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, PtrVT); + + SDValue PtrOff = + DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, + DAG.getIntPtrConstant(VA.getLocMemOffset(), dl)); + + SDValue MemOp; + ISD::ArgFlagsTy Flags = Outs[i].Flags; + + if (Flags.isByVal()) { + SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16); + MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode, + Flags.getByValAlign(), + /*isVolatile*/false, + /*AlwaysInline=*/true, + /*isTailCall=*/false, + MachinePointerInfo(), + MachinePointerInfo()); + } else { + MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()); + } + + MemOpChains.push_back(MemOp); + } + } + + // Transform all store nodes into one single node because all store nodes are + // independent of each other. + if (!MemOpChains.empty()) + Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); + + // Build a sequence of copy-to-reg nodes chained together with token chain and + // flag operands which copy the outgoing args into registers. The InFlag in + // necessary since all emitted instructions must be stuck together. + SDValue InFlag; + for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { + Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, + RegsToPass[i].second, InFlag); + InFlag = Chain.getValue(1); + } + + // If the callee is a GlobalAddress node (quite common, every direct call is) + // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. + // Likewise ExternalSymbol -> TargetExternalSymbol. + if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) + Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16); + else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) + Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16); + + // Returns a chain & a flag for retval copy to use. + SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); + SmallVector<SDValue, 8> Ops; + Ops.push_back(Chain); + Ops.push_back(Callee); + + // Add argument registers to the end of the list so that they are + // known live into the call. + for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) + Ops.push_back(DAG.getRegister(RegsToPass[i].first, + RegsToPass[i].second.getValueType())); + + if (InFlag.getNode()) + Ops.push_back(InFlag); + + Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops); + InFlag = Chain.getValue(1); + + // Create the CALLSEQ_END node. + Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, dl, PtrVT, true), + DAG.getConstant(0, dl, PtrVT, true), InFlag, dl); + InFlag = Chain.getValue(1); + + // Handle result values, copying them out of physregs into vregs that we + // return. + return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, + DAG, InVals); +} + +/// LowerCallResult - Lower the result values of a call into the +/// appropriate copies out of appropriate physical registers. +/// +SDValue MSP430TargetLowering::LowerCallResult( + SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, + const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, + SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { + + // Assign locations to each value returned by this call. + SmallVector<CCValAssign, 16> RVLocs; + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, + *DAG.getContext()); + + AnalyzeReturnValues(CCInfo, RVLocs, Ins); + + // Copy all of the result registers out of their specified physreg. + for (unsigned i = 0; i != RVLocs.size(); ++i) { + Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), + RVLocs[i].getValVT(), InFlag).getValue(1); + InFlag = Chain.getValue(2); + InVals.push_back(Chain.getValue(0)); + } + + return Chain; +} + +SDValue MSP430TargetLowering::LowerShifts(SDValue Op, + SelectionDAG &DAG) const { + unsigned Opc = Op.getOpcode(); + SDNode* N = Op.getNode(); + EVT VT = Op.getValueType(); + SDLoc dl(N); + + // Expand non-constant shifts to loops: + if (!isa<ConstantSDNode>(N->getOperand(1))) + switch (Opc) { + default: llvm_unreachable("Invalid shift opcode!"); + case ISD::SHL: + return DAG.getNode(MSP430ISD::SHL, dl, + VT, N->getOperand(0), N->getOperand(1)); + case ISD::SRA: + return DAG.getNode(MSP430ISD::SRA, dl, + VT, N->getOperand(0), N->getOperand(1)); + case ISD::SRL: + return DAG.getNode(MSP430ISD::SRL, dl, + VT, N->getOperand(0), N->getOperand(1)); + } + + uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); + + // Expand the stuff into sequence of shifts. + // FIXME: for some shift amounts this might be done better! + // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N + SDValue Victim = N->getOperand(0); + + if (Opc == ISD::SRL && ShiftAmount) { + // Emit a special goodness here: + // srl A, 1 => clrc; rrc A + Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim); + ShiftAmount -= 1; + } + + while (ShiftAmount--) + Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA), + dl, VT, Victim); + + return Victim; +} + +SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op, + SelectionDAG &DAG) const { + const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); + int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); + auto PtrVT = getPointerTy(DAG.getDataLayout()); + + // Create the TargetGlobalAddress node, folding in the constant offset. + SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op), PtrVT, Offset); + return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op), PtrVT, Result); +} + +SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op, + SelectionDAG &DAG) const { + SDLoc dl(Op); + const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); + auto PtrVT = getPointerTy(DAG.getDataLayout()); + SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT); + + return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result); +} + +SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op, + SelectionDAG &DAG) const { + SDLoc dl(Op); + auto PtrVT = getPointerTy(DAG.getDataLayout()); + const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); + SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT); + + return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result); +} + +static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC, + ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG) { + // FIXME: Handle bittests someday + assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet"); + + // FIXME: Handle jump negative someday + MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID; + switch (CC) { + default: llvm_unreachable("Invalid integer condition!"); + case ISD::SETEQ: + TCC = MSP430CC::COND_E; // aka COND_Z + // Minor optimization: if LHS is a constant, swap operands, then the + // constant can be folded into comparison. + if (LHS.getOpcode() == ISD::Constant) + std::swap(LHS, RHS); + break; + case ISD::SETNE: + TCC = MSP430CC::COND_NE; // aka COND_NZ + // Minor optimization: if LHS is a constant, swap operands, then the + // constant can be folded into comparison. + if (LHS.getOpcode() == ISD::Constant) + std::swap(LHS, RHS); + break; + case ISD::SETULE: + std::swap(LHS, RHS); + LLVM_FALLTHROUGH; + case ISD::SETUGE: + // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to + // fold constant into instruction. + if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { + LHS = RHS; + RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); + TCC = MSP430CC::COND_LO; + break; + } + TCC = MSP430CC::COND_HS; // aka COND_C + break; + case ISD::SETUGT: + std::swap(LHS, RHS); + LLVM_FALLTHROUGH; + case ISD::SETULT: + // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to + // fold constant into instruction. + if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { + LHS = RHS; + RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); + TCC = MSP430CC::COND_HS; + break; + } + TCC = MSP430CC::COND_LO; // aka COND_NC + break; + case ISD::SETLE: + std::swap(LHS, RHS); + LLVM_FALLTHROUGH; + case ISD::SETGE: + // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to + // fold constant into instruction. + if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { + LHS = RHS; + RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); + TCC = MSP430CC::COND_L; + break; + } + TCC = MSP430CC::COND_GE; + break; + case ISD::SETGT: + std::swap(LHS, RHS); + LLVM_FALLTHROUGH; + case ISD::SETLT: + // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to + // fold constant into instruction. + if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) { + LHS = RHS; + RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0)); + TCC = MSP430CC::COND_GE; + break; + } + TCC = MSP430CC::COND_L; + break; + } + + TargetCC = DAG.getConstant(TCC, dl, MVT::i8); + return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS); +} + + +SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { + SDValue Chain = Op.getOperand(0); + ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); + SDValue LHS = Op.getOperand(2); + SDValue RHS = Op.getOperand(3); + SDValue Dest = Op.getOperand(4); + SDLoc dl (Op); + + SDValue TargetCC; + SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); + + return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(), + Chain, Dest, TargetCC, Flag); +} + +SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { + SDValue LHS = Op.getOperand(0); + SDValue RHS = Op.getOperand(1); + SDLoc dl (Op); + + // If we are doing an AND and testing against zero, then the CMP + // will not be generated. The AND (or BIT) will generate the condition codes, + // but they are different from CMP. + // FIXME: since we're doing a post-processing, use a pseudoinstr here, so + // lowering & isel wouldn't diverge. + bool andCC = false; + if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { + if (RHSC->isNullValue() && LHS.hasOneUse() && + (LHS.getOpcode() == ISD::AND || + (LHS.getOpcode() == ISD::TRUNCATE && + LHS.getOperand(0).getOpcode() == ISD::AND))) { + andCC = true; + } + } + ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); + SDValue TargetCC; + SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); + + // Get the condition codes directly from the status register, if its easy. + // Otherwise a branch will be generated. Note that the AND and BIT + // instructions generate different flags than CMP, the carry bit can be used + // for NE/EQ. + bool Invert = false; + bool Shift = false; + bool Convert = true; + switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) { + default: + Convert = false; + break; + case MSP430CC::COND_HS: + // Res = SR & 1, no processing is required + break; + case MSP430CC::COND_LO: + // Res = ~(SR & 1) + Invert = true; + break; + case MSP430CC::COND_NE: + if (andCC) { + // C = ~Z, thus Res = SR & 1, no processing is required + } else { + // Res = ~((SR >> 1) & 1) + Shift = true; + Invert = true; + } + break; + case MSP430CC::COND_E: + Shift = true; + // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however, + // Res = (SR >> 1) & 1 is 1 word shorter. + break; + } + EVT VT = Op.getValueType(); + SDValue One = DAG.getConstant(1, dl, VT); + if (Convert) { + SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR, + MVT::i16, Flag); + if (Shift) + // FIXME: somewhere this is turned into a SRL, lower it MSP specific? + SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); + SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One); + if (Invert) + SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One); + return SR; + } else { + SDValue Zero = DAG.getConstant(0, dl, VT); + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); + SDValue Ops[] = {One, Zero, TargetCC, Flag}; + return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); + } +} + +SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, + SelectionDAG &DAG) const { + SDValue LHS = Op.getOperand(0); + SDValue RHS = Op.getOperand(1); + SDValue TrueV = Op.getOperand(2); + SDValue FalseV = Op.getOperand(3); + ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); + SDLoc dl (Op); + + SDValue TargetCC; + SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); + + SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); + SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag}; + + return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); +} + +SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op, + SelectionDAG &DAG) const { + SDValue Val = Op.getOperand(0); + EVT VT = Op.getValueType(); + SDLoc dl(Op); + + assert(VT == MVT::i16 && "Only support i16 for now!"); + + return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, + DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val), + DAG.getValueType(Val.getValueType())); +} + +SDValue +MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { + MachineFunction &MF = DAG.getMachineFunction(); + MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>(); + int ReturnAddrIndex = FuncInfo->getRAIndex(); + auto PtrVT = getPointerTy(MF.getDataLayout()); + + if (ReturnAddrIndex == 0) { + // Set up a frame object for the return address. + uint64_t SlotSize = MF.getDataLayout().getPointerSize(); + ReturnAddrIndex = MF.getFrameInfo().CreateFixedObject(SlotSize, -SlotSize, + true); + FuncInfo->setRAIndex(ReturnAddrIndex); + } + + return DAG.getFrameIndex(ReturnAddrIndex, PtrVT); +} + +SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op, + SelectionDAG &DAG) const { + MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); + MFI.setReturnAddressIsTaken(true); + + if (verifyReturnAddressArgumentIsConstant(Op, DAG)) + return SDValue(); + + unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); + SDLoc dl(Op); + auto PtrVT = getPointerTy(DAG.getDataLayout()); + + if (Depth > 0) { + SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); + SDValue Offset = + DAG.getConstant(DAG.getDataLayout().getPointerSize(), dl, MVT::i16); + return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), + DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset), + MachinePointerInfo()); + } + + // Just load the return address. + SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); + return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI, + MachinePointerInfo()); +} + +SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op, + SelectionDAG &DAG) const { + MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); + MFI.setFrameAddressIsTaken(true); + + EVT VT = Op.getValueType(); + SDLoc dl(Op); // FIXME probably not meaningful + unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); + SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, + MSP430::FP, VT); + while (Depth--) + FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, + MachinePointerInfo()); + return FrameAddr; +} + +SDValue MSP430TargetLowering::LowerVASTART(SDValue Op, + SelectionDAG &DAG) const { + MachineFunction &MF = DAG.getMachineFunction(); + MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>(); + auto PtrVT = getPointerTy(DAG.getDataLayout()); + + // Frame index of first vararg argument + SDValue FrameIndex = + DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); + const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); + + // Create a store of the frame index to the location operand + return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex, Op.getOperand(1), + MachinePointerInfo(SV)); +} + +SDValue MSP430TargetLowering::LowerJumpTable(SDValue Op, + SelectionDAG &DAG) const { + JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); + auto PtrVT = getPointerTy(DAG.getDataLayout()); + SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); + return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT), PtrVT, Result); +} + +/// getPostIndexedAddressParts - returns true by value, base pointer and +/// offset pointer and addressing mode by reference if this node can be +/// combined with a load / store to form a post-indexed load / store. +bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, + SDValue &Base, + SDValue &Offset, + ISD::MemIndexedMode &AM, + SelectionDAG &DAG) const { + + LoadSDNode *LD = cast<LoadSDNode>(N); + if (LD->getExtensionType() != ISD::NON_EXTLOAD) + return false; + + EVT VT = LD->getMemoryVT(); + if (VT != MVT::i8 && VT != MVT::i16) + return false; + + if (Op->getOpcode() != ISD::ADD) + return false; + + if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) { + uint64_t RHSC = RHS->getZExtValue(); + if ((VT == MVT::i16 && RHSC != 2) || + (VT == MVT::i8 && RHSC != 1)) + return false; + + Base = Op->getOperand(0); + Offset = DAG.getConstant(RHSC, SDLoc(N), VT); + AM = ISD::POST_INC; + return true; + } + + return false; +} + + +const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const { + switch ((MSP430ISD::NodeType)Opcode) { + case MSP430ISD::FIRST_NUMBER: break; + case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG"; + case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG"; + case MSP430ISD::RRA: return "MSP430ISD::RRA"; + case MSP430ISD::RLA: return "MSP430ISD::RLA"; + case MSP430ISD::RRC: return "MSP430ISD::RRC"; + case MSP430ISD::CALL: return "MSP430ISD::CALL"; + case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper"; + case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC"; + case MSP430ISD::CMP: return "MSP430ISD::CMP"; + case MSP430ISD::SETCC: return "MSP430ISD::SETCC"; + case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC"; + case MSP430ISD::SHL: return "MSP430ISD::SHL"; + case MSP430ISD::SRA: return "MSP430ISD::SRA"; + case MSP430ISD::SRL: return "MSP430ISD::SRL"; + } + return nullptr; +} + +bool MSP430TargetLowering::isTruncateFree(Type *Ty1, + Type *Ty2) const { + if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) + return false; + + return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits()); +} + +bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { + if (!VT1.isInteger() || !VT2.isInteger()) + return false; + + return (VT1.getSizeInBits() > VT2.getSizeInBits()); +} + +bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { + // MSP430 implicitly zero-extends 8-bit results in 16-bit registers. + return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16); +} + +bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { + // MSP430 implicitly zero-extends 8-bit results in 16-bit registers. + return 0 && VT1 == MVT::i8 && VT2 == MVT::i16; +} + +bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const { + return isZExtFree(Val.getValueType(), VT2); +} + +//===----------------------------------------------------------------------===// +// Other Lowering Code +//===----------------------------------------------------------------------===// + +MachineBasicBlock * +MSP430TargetLowering::EmitShiftInstr(MachineInstr &MI, + MachineBasicBlock *BB) const { + MachineFunction *F = BB->getParent(); + MachineRegisterInfo &RI = F->getRegInfo(); + DebugLoc dl = MI.getDebugLoc(); + const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo(); + + unsigned Opc; + const TargetRegisterClass * RC; + switch (MI.getOpcode()) { + default: llvm_unreachable("Invalid shift opcode!"); + case MSP430::Shl8: + Opc = MSP430::SHL8r1; + RC = &MSP430::GR8RegClass; + break; + case MSP430::Shl16: + Opc = MSP430::SHL16r1; + RC = &MSP430::GR16RegClass; + break; + case MSP430::Sra8: + Opc = MSP430::SAR8r1; + RC = &MSP430::GR8RegClass; + break; + case MSP430::Sra16: + Opc = MSP430::SAR16r1; + RC = &MSP430::GR16RegClass; + break; + case MSP430::Srl8: + Opc = MSP430::SAR8r1c; + RC = &MSP430::GR8RegClass; + break; + case MSP430::Srl16: + Opc = MSP430::SAR16r1c; + RC = &MSP430::GR16RegClass; + break; + } + + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineFunction::iterator I = ++BB->getIterator(); + + // Create loop block + MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB); + + F->insert(I, LoopBB); + F->insert(I, RemBB); + + // Update machine-CFG edges by transferring all successors of the current + // block to the block containing instructions after shift. + RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)), + BB->end()); + RemBB->transferSuccessorsAndUpdatePHIs(BB); + + // Add edges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB + BB->addSuccessor(LoopBB); + BB->addSuccessor(RemBB); + LoopBB->addSuccessor(RemBB); + LoopBB->addSuccessor(LoopBB); + + unsigned ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass); + unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass); + unsigned ShiftReg = RI.createVirtualRegister(RC); + unsigned ShiftReg2 = RI.createVirtualRegister(RC); + unsigned ShiftAmtSrcReg = MI.getOperand(2).getReg(); + unsigned SrcReg = MI.getOperand(1).getReg(); + unsigned DstReg = MI.getOperand(0).getReg(); + + // BB: + // cmp 0, N + // je RemBB + BuildMI(BB, dl, TII.get(MSP430::CMP8ri)) + .addReg(ShiftAmtSrcReg).addImm(0); + BuildMI(BB, dl, TII.get(MSP430::JCC)) + .addMBB(RemBB) + .addImm(MSP430CC::COND_E); + + // LoopBB: + // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB] + // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB] + // ShiftReg2 = shift ShiftReg + // ShiftAmt2 = ShiftAmt - 1; + BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg) + .addReg(SrcReg).addMBB(BB) + .addReg(ShiftReg2).addMBB(LoopBB); + BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg) + .addReg(ShiftAmtSrcReg).addMBB(BB) + .addReg(ShiftAmtReg2).addMBB(LoopBB); + BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2) + .addReg(ShiftReg); + BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2) + .addReg(ShiftAmtReg).addImm(1); + BuildMI(LoopBB, dl, TII.get(MSP430::JCC)) + .addMBB(LoopBB) + .addImm(MSP430CC::COND_NE); + + // RemBB: + // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB] + BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg) + .addReg(SrcReg).addMBB(BB) + .addReg(ShiftReg2).addMBB(LoopBB); + + MI.eraseFromParent(); // The pseudo instruction is gone now. + return RemBB; +} + +MachineBasicBlock * +MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, + MachineBasicBlock *BB) const { + unsigned Opc = MI.getOpcode(); + + if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 || + Opc == MSP430::Sra8 || Opc == MSP430::Sra16 || + Opc == MSP430::Srl8 || Opc == MSP430::Srl16) + return EmitShiftInstr(MI, BB); + + const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); + DebugLoc dl = MI.getDebugLoc(); + + assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) && + "Unexpected instr type to insert"); + + // To "insert" a SELECT instruction, we actually have to insert the diamond + // control-flow pattern. The incoming instruction knows the destination vreg + // to set, the condition code register to branch on, the true/false values to + // select between, and a branch opcode to use. + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineFunction::iterator I = ++BB->getIterator(); + + // thisMBB: + // ... + // TrueVal = ... + // cmpTY ccX, r1, r2 + // jCC copy1MBB + // fallthrough --> copy0MBB + MachineBasicBlock *thisMBB = BB; + MachineFunction *F = BB->getParent(); + MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); + F->insert(I, copy0MBB); + F->insert(I, copy1MBB); + // Update machine-CFG edges by transferring all successors of the current + // block to the new block which will contain the Phi node for the select. + copy1MBB->splice(copy1MBB->begin(), BB, + std::next(MachineBasicBlock::iterator(MI)), BB->end()); + copy1MBB->transferSuccessorsAndUpdatePHIs(BB); + // Next, add the true and fallthrough blocks as its successors. + BB->addSuccessor(copy0MBB); + BB->addSuccessor(copy1MBB); + + BuildMI(BB, dl, TII.get(MSP430::JCC)) + .addMBB(copy1MBB) + .addImm(MI.getOperand(3).getImm()); + + // copy0MBB: + // %FalseValue = ... + // # fallthrough to copy1MBB + BB = copy0MBB; + + // Update machine-CFG edges + BB->addSuccessor(copy1MBB); + + // copy1MBB: + // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] + // ... + BB = copy1MBB; + BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg()) + .addReg(MI.getOperand(2).getReg()) + .addMBB(copy0MBB) + .addReg(MI.getOperand(1).getReg()) + .addMBB(thisMBB); + + MI.eraseFromParent(); // The pseudo instruction is gone now. + return BB; +} diff --git a/contrib/llvm/lib/Target/MSP430/MSP430ISelLowering.h b/contrib/llvm/lib/Target/MSP430/MSP430ISelLowering.h new file mode 100644 index 000000000000..3a729623c99a --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430ISelLowering.h @@ -0,0 +1,180 @@ +//===-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the interfaces that MSP430 uses to lower LLVM code into a +// selection DAG. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H +#define LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H + +#include "MSP430.h" +#include "llvm/CodeGen/SelectionDAG.h" +#include "llvm/Target/TargetLowering.h" + +namespace llvm { + namespace MSP430ISD { + enum NodeType : unsigned { + FIRST_NUMBER = ISD::BUILTIN_OP_END, + + /// Return with a flag operand. Operand 0 is the chain operand. + RET_FLAG, + + /// Same as RET_FLAG, but used for returning from ISRs. + RETI_FLAG, + + /// Y = R{R,L}A X, rotate right (left) arithmetically + RRA, RLA, + + /// Y = RRC X, rotate right via carry + RRC, + + /// CALL - These operations represent an abstract call + /// instruction, which includes a bunch of information. + CALL, + + /// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, + /// and TargetGlobalAddress. + Wrapper, + + /// CMP - Compare instruction. + CMP, + + /// SetCC - Operand 0 is condition code, and operand 1 is the flag + /// operand produced by a CMP instruction. + SETCC, + + /// MSP430 conditional branches. Operand 0 is the chain operand, operand 1 + /// is the block to branch if condition is true, operand 2 is the + /// condition code, and operand 3 is the flag operand produced by a CMP + /// instruction. + BR_CC, + + /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 + /// is condition code and operand 4 is flag operand. + SELECT_CC, + + /// SHL, SRA, SRL - Non-constant shifts. + SHL, SRA, SRL + }; + } + + class MSP430Subtarget; + class MSP430TargetLowering : public TargetLowering { + public: + explicit MSP430TargetLowering(const TargetMachine &TM, + const MSP430Subtarget &STI); + + MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { + return MVT::i8; + } + + /// LowerOperation - Provide custom lowering hooks for some operations. + SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; + + /// getTargetNodeName - This method returns the name of a target specific + /// DAG node. + const char *getTargetNodeName(unsigned Opcode) const override; + + SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; + SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; + + TargetLowering::ConstraintType + getConstraintType(StringRef Constraint) const override; + std::pair<unsigned, const TargetRegisterClass *> + getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, + StringRef Constraint, MVT VT) const override; + + /// isTruncateFree - Return true if it's free to truncate a value of type + /// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in + /// register R15W to i8 by referencing its sub-register R15B. + bool isTruncateFree(Type *Ty1, Type *Ty2) const override; + bool isTruncateFree(EVT VT1, EVT VT2) const override; + + /// isZExtFree - Return true if any actual instruction that defines a value + /// of type Ty1 implicit zero-extends the value to Ty2 in the result + /// register. This does not necessarily include registers defined in unknown + /// ways, such as incoming arguments, or copies from unknown virtual + /// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not + /// necessarily apply to truncate instructions. e.g. on msp430, all + /// instructions that define 8-bit values implicit zero-extend the result + /// out to 16 bits. + bool isZExtFree(Type *Ty1, Type *Ty2) const override; + bool isZExtFree(EVT VT1, EVT VT2) const override; + bool isZExtFree(SDValue Val, EVT VT2) const override; + + MachineBasicBlock * + EmitInstrWithCustomInserter(MachineInstr &MI, + MachineBasicBlock *BB) const override; + MachineBasicBlock *EmitShiftInstr(MachineInstr &MI, + MachineBasicBlock *BB) const; + + private: + SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee, + CallingConv::ID CallConv, bool isVarArg, + bool isTailCall, + const SmallVectorImpl<ISD::OutputArg> &Outs, + const SmallVectorImpl<SDValue> &OutVals, + const SmallVectorImpl<ISD::InputArg> &Ins, + const SDLoc &dl, SelectionDAG &DAG, + SmallVectorImpl<SDValue> &InVals) const; + + SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, + bool isVarArg, + const SmallVectorImpl<ISD::InputArg> &Ins, + const SDLoc &dl, SelectionDAG &DAG, + SmallVectorImpl<SDValue> &InVals) const; + + SDValue LowerCallResult(SDValue Chain, SDValue InFlag, + CallingConv::ID CallConv, bool isVarArg, + const SmallVectorImpl<ISD::InputArg> &Ins, + const SDLoc &dl, SelectionDAG &DAG, + SmallVectorImpl<SDValue> &InVals) const; + + SDValue + LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, + const SmallVectorImpl<ISD::InputArg> &Ins, + const SDLoc &dl, SelectionDAG &DAG, + SmallVectorImpl<SDValue> &InVals) const override; + SDValue + LowerCall(TargetLowering::CallLoweringInfo &CLI, + SmallVectorImpl<SDValue> &InVals) const override; + + bool CanLowerReturn(CallingConv::ID CallConv, + MachineFunction &MF, + bool IsVarArg, + const SmallVectorImpl<ISD::OutputArg> &Outs, + LLVMContext &Context) const override; + + SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, + const SmallVectorImpl<ISD::OutputArg> &Outs, + const SmallVectorImpl<SDValue> &OutVals, + const SDLoc &dl, SelectionDAG &DAG) const override; + + bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, + SDValue &Base, + SDValue &Offset, + ISD::MemIndexedMode &AM, + SelectionDAG &DAG) const override; + }; +} // namespace llvm + +#endif diff --git a/contrib/llvm/lib/Target/MSP430/MSP430InstrFormats.td b/contrib/llvm/lib/Target/MSP430/MSP430InstrFormats.td new file mode 100644 index 000000000000..a9e87dad0cd8 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430InstrFormats.td @@ -0,0 +1,211 @@ +//===-- MSP430InstrFormats.td - MSP430 Instruction Formats -*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Describe MSP430 instructions format here +// + +// Format specifies the encoding used by the instruction. This is part of the +// ad-hoc solution used to emit machine instruction encodings by our machine +// code emitter. +class Format<bits<2> val> { + bits<2> Value = val; +} + +def PseudoFrm : Format<0>; +def SingleOpFrm : Format<1>; +def DoubleOpFrm : Format<2>; +def CondJumpFrm : Format<3>; + +class SourceMode<bits<2> val> { + bits<2> Value = val; +} + +def SrcReg : SourceMode<0>; +def SrcMem : SourceMode<1>; +def SrcIndReg : SourceMode<2>; +def SrcPostInc : SourceMode<3>; +def SrcImm : SourceMode<3>; + +class DestMode<bit val> { + bit Value = val; +} + +def DstReg : DestMode<0>; +def DstMem : DestMode<1>; + +class SizeVal<bits<3> val> { + bits<3> Value = val; +} + +def SizeUnknown : SizeVal<0>; // Unknown / unset size +def SizeSpecial : SizeVal<1>; // Special instruction, e.g. pseudo +def Size2Bytes : SizeVal<2>; +def Size4Bytes : SizeVal<3>; +def Size6Bytes : SizeVal<4>; + +// Generic MSP430 Format +class MSP430Inst<dag outs, dag ins, SizeVal sz, Format f, + string asmstr> : Instruction { + field bits<16> Inst; + + let Namespace = "MSP430"; + + dag OutOperandList = outs; + dag InOperandList = ins; + + Format Form = f; + SizeVal Sz = sz; + + // Define how we want to layout our TargetSpecific information field... This + // should be kept up-to-date with the fields in the MSP430InstrInfo.h file. + let TSFlags{1-0} = Form.Value; + let TSFlags{4-2} = Sz.Value; + + let AsmString = asmstr; +} + +// FIXME: Create different classes for different addressing modes. + +// MSP430 Double Operand (Format I) Instructions +class IForm<bits<4> opcode, DestMode dest, bit bw, SourceMode src, SizeVal sz, + dag outs, dag ins, string asmstr, list<dag> pattern> + : MSP430Inst<outs, ins, sz, DoubleOpFrm, asmstr> { + let Pattern = pattern; + + DestMode ad = dest; + SourceMode as = src; + + let Inst{12-15} = opcode; + let Inst{7} = ad.Value; + let Inst{6} = bw; + let Inst{4-5} = as.Value; +} + +// 8 bit IForm instructions +class IForm8<bits<4> opcode, DestMode dest, SourceMode src, SizeVal sz, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IForm<opcode, dest, 1, src, sz, outs, ins, asmstr, pattern>; + +class I8rr<bits<4> opcode, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IForm8<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>; + +class I8ri<bits<4> opcode, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IForm8<opcode, DstReg, SrcImm, Size4Bytes, outs, ins, asmstr, pattern>; + +class I8rm<bits<4> opcode, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IForm8<opcode, DstReg, SrcMem, Size4Bytes, outs, ins, asmstr, pattern>; + +class I8mr<bits<4> opcode, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IForm8<opcode, DstMem, SrcReg, Size4Bytes, outs, ins, asmstr, pattern>; + +class I8mi<bits<4> opcode, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IForm8<opcode, DstMem, SrcImm, Size6Bytes, outs, ins, asmstr, pattern>; + +class I8mm<bits<4> opcode, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IForm8<opcode, DstMem, SrcMem, Size6Bytes, outs, ins, asmstr, pattern>; + +// 16 bit IForm instructions +class IForm16<bits<4> opcode, DestMode dest, SourceMode src, SizeVal sz, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IForm<opcode, dest, 0, src, sz, outs, ins, asmstr, pattern>; + +class I16rr<bits<4> opcode, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IForm16<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>; + +class I16ri<bits<4> opcode, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IForm16<opcode, DstReg, SrcImm, Size4Bytes, outs, ins, asmstr, pattern>; + +class I16rm<bits<4> opcode, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IForm16<opcode, DstReg, SrcMem, Size4Bytes, outs, ins, asmstr, pattern>; + +class I16mr<bits<4> opcode, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IForm16<opcode, DstMem, SrcReg, Size4Bytes, outs, ins, asmstr, pattern>; + +class I16mi<bits<4> opcode, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IForm16<opcode, DstMem, SrcImm, Size6Bytes, outs, ins, asmstr, pattern>; + +class I16mm<bits<4> opcode, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IForm16<opcode, DstMem, SrcMem, Size6Bytes, outs, ins, asmstr, pattern>; + +// MSP430 Single Operand (Format II) Instructions +class IIForm<bits<9> opcode, bit bw, SourceMode src, SizeVal sz, + dag outs, dag ins, string asmstr, list<dag> pattern> + : MSP430Inst<outs, ins, sz, SingleOpFrm, asmstr> { + let Pattern = pattern; + + SourceMode as = src; + + let Inst{7-15} = opcode; + let Inst{6} = bw; + let Inst{4-5} = as.Value; +} + +// 8 bit IIForm instructions +class IIForm8<bits<9> opcode, SourceMode src, SizeVal sz, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IIForm<opcode, 1, src, sz, outs, ins, asmstr, pattern>; + +class II8r<bits<9> opcode, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IIForm8<opcode, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>; + +class II8m<bits<9> opcode, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IIForm8<opcode, SrcMem, Size4Bytes, outs, ins, asmstr, pattern>; + +class II8i<bits<9> opcode, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IIForm8<opcode, SrcImm, Size4Bytes, outs, ins, asmstr, pattern>; + +// 16 bit IIForm instructions +class IIForm16<bits<9> opcode, SourceMode src, SizeVal sz, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IIForm<opcode, 0, src, sz, outs, ins, asmstr, pattern>; + +class II16r<bits<9> opcode, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IIForm16<opcode, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>; + +class II16m<bits<9> opcode, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IIForm16<opcode, SrcMem, Size4Bytes, outs, ins, asmstr, pattern>; + +class II16i<bits<9> opcode, + dag outs, dag ins, string asmstr, list<dag> pattern> + : IIForm16<opcode, SrcImm, Size4Bytes, outs, ins, asmstr, pattern>; + +// MSP430 Conditional Jumps Instructions +class CJForm<bits<3> opcode, bits<3> cond, + dag outs, dag ins, string asmstr, list<dag> pattern> + : MSP430Inst<outs, ins, Size2Bytes, CondJumpFrm, asmstr> { + let Pattern = pattern; + + let Inst{13-15} = opcode; + let Inst{10-12} = cond; +} + +// Pseudo instructions +class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> + : MSP430Inst<outs, ins, SizeSpecial, PseudoFrm, asmstr> { + let Pattern = pattern; + let Inst{15-0} = 0; +} diff --git a/contrib/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp b/contrib/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp new file mode 100644 index 000000000000..6135ce080920 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -0,0 +1,335 @@ +//===-- MSP430InstrInfo.cpp - MSP430 Instruction Information --------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the MSP430 implementation of the TargetInstrInfo class. +// +//===----------------------------------------------------------------------===// + +#include "MSP430InstrInfo.h" +#include "MSP430.h" +#include "MSP430MachineFunctionInfo.h" +#include "MSP430TargetMachine.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/IR/Function.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" + +using namespace llvm; + +#define GET_INSTRINFO_CTOR_DTOR +#include "MSP430GenInstrInfo.inc" + +// Pin the vtable to this file. +void MSP430InstrInfo::anchor() {} + +MSP430InstrInfo::MSP430InstrInfo(MSP430Subtarget &STI) + : MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP), + RI() {} + +void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned SrcReg, bool isKill, int FrameIdx, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI) const { + DebugLoc DL; + if (MI != MBB.end()) DL = MI->getDebugLoc(); + MachineFunction &MF = *MBB.getParent(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + + MachineMemOperand *MMO = MF.getMachineMemOperand( + MachinePointerInfo::getFixedStack(MF, FrameIdx), + MachineMemOperand::MOStore, MFI.getObjectSize(FrameIdx), + MFI.getObjectAlignment(FrameIdx)); + + if (RC == &MSP430::GR16RegClass) + BuildMI(MBB, MI, DL, get(MSP430::MOV16mr)) + .addFrameIndex(FrameIdx).addImm(0) + .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); + else if (RC == &MSP430::GR8RegClass) + BuildMI(MBB, MI, DL, get(MSP430::MOV8mr)) + .addFrameIndex(FrameIdx).addImm(0) + .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); + else + llvm_unreachable("Cannot store this register to stack slot!"); +} + +void MSP430InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, int FrameIdx, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI) const{ + DebugLoc DL; + if (MI != MBB.end()) DL = MI->getDebugLoc(); + MachineFunction &MF = *MBB.getParent(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + + MachineMemOperand *MMO = MF.getMachineMemOperand( + MachinePointerInfo::getFixedStack(MF, FrameIdx), + MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIdx), + MFI.getObjectAlignment(FrameIdx)); + + if (RC == &MSP430::GR16RegClass) + BuildMI(MBB, MI, DL, get(MSP430::MOV16rm)) + .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) + .addImm(0).addMemOperand(MMO); + else if (RC == &MSP430::GR8RegClass) + BuildMI(MBB, MI, DL, get(MSP430::MOV8rm)) + .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) + .addImm(0).addMemOperand(MMO); + else + llvm_unreachable("Cannot store this register to stack slot!"); +} + +void MSP430InstrInfo::copyPhysReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + const DebugLoc &DL, unsigned DestReg, + unsigned SrcReg, bool KillSrc) const { + unsigned Opc; + if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) + Opc = MSP430::MOV16rr; + else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) + Opc = MSP430::MOV8rr; + else + llvm_unreachable("Impossible reg-to-reg copy"); + + BuildMI(MBB, I, DL, get(Opc), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)); +} + +unsigned MSP430InstrInfo::removeBranch(MachineBasicBlock &MBB, + int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); + + MachineBasicBlock::iterator I = MBB.end(); + unsigned Count = 0; + + while (I != MBB.begin()) { + --I; + if (I->isDebugValue()) + continue; + if (I->getOpcode() != MSP430::JMP && + I->getOpcode() != MSP430::JCC && + I->getOpcode() != MSP430::Br && + I->getOpcode() != MSP430::Bm) + break; + // Remove the branch. + I->eraseFromParent(); + I = MBB.end(); + ++Count; + } + + return Count; +} + +bool MSP430InstrInfo:: +reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { + assert(Cond.size() == 1 && "Invalid Xbranch condition!"); + + MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); + + switch (CC) { + default: llvm_unreachable("Invalid branch condition!"); + case MSP430CC::COND_E: + CC = MSP430CC::COND_NE; + break; + case MSP430CC::COND_NE: + CC = MSP430CC::COND_E; + break; + case MSP430CC::COND_L: + CC = MSP430CC::COND_GE; + break; + case MSP430CC::COND_GE: + CC = MSP430CC::COND_L; + break; + case MSP430CC::COND_HS: + CC = MSP430CC::COND_LO; + break; + case MSP430CC::COND_LO: + CC = MSP430CC::COND_HS; + break; + } + + Cond[0].setImm(CC); + return false; +} + +bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const { + if (!MI.isTerminator()) + return false; + + // Conditional branch is a special case. + if (MI.isBranch() && !MI.isBarrier()) + return true; + if (!MI.isPredicable()) + return true; + return !isPredicated(MI); +} + +bool MSP430InstrInfo::analyzeBranch(MachineBasicBlock &MBB, + MachineBasicBlock *&TBB, + MachineBasicBlock *&FBB, + SmallVectorImpl<MachineOperand> &Cond, + bool AllowModify) const { + // Start from the bottom of the block and work up, examining the + // terminator instructions. + MachineBasicBlock::iterator I = MBB.end(); + while (I != MBB.begin()) { + --I; + if (I->isDebugValue()) + continue; + + // Working from the bottom, when we see a non-terminator + // instruction, we're done. + if (!isUnpredicatedTerminator(*I)) + break; + + // A terminator that isn't a branch can't easily be handled + // by this analysis. + if (!I->isBranch()) + return true; + + // Cannot handle indirect branches. + if (I->getOpcode() == MSP430::Br || + I->getOpcode() == MSP430::Bm) + return true; + + // Handle unconditional branches. + if (I->getOpcode() == MSP430::JMP) { + if (!AllowModify) { + TBB = I->getOperand(0).getMBB(); + continue; + } + + // If the block has any instructions after a JMP, delete them. + while (std::next(I) != MBB.end()) + std::next(I)->eraseFromParent(); + Cond.clear(); + FBB = nullptr; + + // Delete the JMP if it's equivalent to a fall-through. + if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { + TBB = nullptr; + I->eraseFromParent(); + I = MBB.end(); + continue; + } + + // TBB is used to indicate the unconditinal destination. + TBB = I->getOperand(0).getMBB(); + continue; + } + + // Handle conditional branches. + assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch"); + MSP430CC::CondCodes BranchCode = + static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm()); + if (BranchCode == MSP430CC::COND_INVALID) + return true; // Can't handle weird stuff. + + // Working from the bottom, handle the first conditional branch. + if (Cond.empty()) { + FBB = TBB; + TBB = I->getOperand(0).getMBB(); + Cond.push_back(MachineOperand::CreateImm(BranchCode)); + continue; + } + + // Handle subsequent conditional branches. Only handle the case where all + // conditional branches branch to the same destination. + assert(Cond.size() == 1); + assert(TBB); + + // Only handle the case where all conditional branches branch to + // the same destination. + if (TBB != I->getOperand(0).getMBB()) + return true; + + MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); + // If the conditions are the same, we can leave them alone. + if (OldBranchCode == BranchCode) + continue; + + return true; + } + + return false; +} + +unsigned MSP430InstrInfo::insertBranch(MachineBasicBlock &MBB, + MachineBasicBlock *TBB, + MachineBasicBlock *FBB, + ArrayRef<MachineOperand> Cond, + const DebugLoc &DL, + int *BytesAdded) const { + // Shouldn't be a fall through. + assert(TBB && "insertBranch must not be told to insert a fallthrough"); + assert((Cond.size() == 1 || Cond.size() == 0) && + "MSP430 branch conditions have one component!"); + assert(!BytesAdded && "code size not handled"); + + if (Cond.empty()) { + // Unconditional branch? + assert(!FBB && "Unconditional branch with multiple successors!"); + BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB); + return 1; + } + + // Conditional branch. + unsigned Count = 0; + BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm()); + ++Count; + + if (FBB) { + // Two-way Conditional branch. Insert the second branch. + BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB); + ++Count; + } + return Count; +} + +/// GetInstSize - Return the number of bytes of code the specified +/// instruction may be. This returns the maximum number of bytes. +/// +unsigned MSP430InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { + const MCInstrDesc &Desc = MI.getDesc(); + + switch (Desc.TSFlags & MSP430II::SizeMask) { + default: + switch (Desc.getOpcode()) { + default: llvm_unreachable("Unknown instruction size!"); + case TargetOpcode::CFI_INSTRUCTION: + case TargetOpcode::EH_LABEL: + case TargetOpcode::IMPLICIT_DEF: + case TargetOpcode::KILL: + case TargetOpcode::DBG_VALUE: + return 0; + case TargetOpcode::INLINEASM: { + const MachineFunction *MF = MI.getParent()->getParent(); + const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); + return TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(), + *MF->getTarget().getMCAsmInfo()); + } + } + case MSP430II::SizeSpecial: + switch (MI.getOpcode()) { + default: llvm_unreachable("Unknown instruction size!"); + case MSP430::SAR8r1c: + case MSP430::SAR16r1c: + return 4; + } + case MSP430II::Size2Bytes: + return 2; + case MSP430II::Size4Bytes: + return 4; + case MSP430II::Size6Bytes: + return 6; + } +} diff --git a/contrib/llvm/lib/Target/MSP430/MSP430InstrInfo.h b/contrib/llvm/lib/Target/MSP430/MSP430InstrInfo.h new file mode 100644 index 000000000000..d81f17e753c5 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430InstrInfo.h @@ -0,0 +1,98 @@ +//===-- MSP430InstrInfo.h - MSP430 Instruction Information ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the MSP430 implementation of the TargetInstrInfo class. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H +#define LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H + +#include "MSP430RegisterInfo.h" +#include "llvm/Target/TargetInstrInfo.h" + +#define GET_INSTRINFO_HEADER +#include "MSP430GenInstrInfo.inc" + +namespace llvm { + +class MSP430Subtarget; + +/// MSP430II - This namespace holds all of the target specific flags that +/// instruction info tracks. +/// +namespace MSP430II { + enum { + SizeShift = 2, + SizeMask = 7 << SizeShift, + + SizeUnknown = 0 << SizeShift, + SizeSpecial = 1 << SizeShift, + Size2Bytes = 2 << SizeShift, + Size4Bytes = 3 << SizeShift, + Size6Bytes = 4 << SizeShift + }; +} + +class MSP430InstrInfo : public MSP430GenInstrInfo { + const MSP430RegisterInfo RI; + virtual void anchor(); +public: + explicit MSP430InstrInfo(MSP430Subtarget &STI); + + /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As + /// such, whenever a client has an instance of instruction info, it should + /// always be able to get register info as well (through this method). + /// + const TargetRegisterInfo &getRegisterInfo() const { return RI; } + + void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, + const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, + bool KillSrc) const override; + + void storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned SrcReg, bool isKill, + int FrameIndex, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI) const override; + void loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + unsigned DestReg, int FrameIdx, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI) const override; + + unsigned getInstSizeInBytes(const MachineInstr &MI) const override; + + // Branch folding goodness + bool + reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; + bool isUnpredicatedTerminator(const MachineInstr &MI) const override; + bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + MachineBasicBlock *&FBB, + SmallVectorImpl<MachineOperand> &Cond, + bool AllowModify) const override; + + unsigned removeBranch(MachineBasicBlock &MBB, + int *BytesRemoved = nullptr) const override; + unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, + MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, + const DebugLoc &DL, + int *BytesAdded = nullptr) const override; + + int64_t getFramePoppedByCallee(const MachineInstr &I) const { + assert(isFrameInstr(I) && "Not a frame instruction"); + assert(I.getOperand(1).getImm() >= 0 && "Size must not be negative"); + return I.getOperand(1).getImm(); + } +}; + +} + +#endif diff --git a/contrib/llvm/lib/Target/MSP430/MSP430InstrInfo.td b/contrib/llvm/lib/Target/MSP430/MSP430InstrInfo.td new file mode 100644 index 000000000000..cec43040f60d --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430InstrInfo.td @@ -0,0 +1,1219 @@ +//===-- MSP430InstrInfo.td - MSP430 Instruction defs -------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the MSP430 instructions in TableGen format. +// +//===----------------------------------------------------------------------===// + +include "MSP430InstrFormats.td" + +//===----------------------------------------------------------------------===// +// Type Constraints. +//===----------------------------------------------------------------------===// +class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>; +class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>; + +//===----------------------------------------------------------------------===// +// Type Profiles. +//===----------------------------------------------------------------------===// +def SDT_MSP430Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; +def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>, + SDTCisVT<1, i16>]>; +def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>; +def SDT_MSP430Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, + SDTCisPtrTy<0>]>; +def SDT_MSP430Cmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>; +def SDT_MSP430BrCC : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, + SDTCisVT<1, i8>]>; +def SDT_MSP430SelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, + SDTCisSameAs<1, 2>, + SDTCisVT<3, i8>]>; +def SDT_MSP430Shift : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, + SDTCisI8<2>]>; + +//===----------------------------------------------------------------------===// +// MSP430 Specific Node Definitions. +//===----------------------------------------------------------------------===// +def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone, + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; +def MSP430retiflag : SDNode<"MSP430ISD::RETI_FLAG", SDTNone, + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; + +def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>; +def MSP430rla : SDNode<"MSP430ISD::RLA", SDTIntUnaryOp, []>; +def MSP430rrc : SDNode<"MSP430ISD::RRC", SDTIntUnaryOp, []>; + +def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call, + [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>; +def MSP430callseq_start : + SDNode<"ISD::CALLSEQ_START", SDT_MSP430CallSeqStart, + [SDNPHasChain, SDNPOutGlue]>; +def MSP430callseq_end : + SDNode<"ISD::CALLSEQ_END", SDT_MSP430CallSeqEnd, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; +def MSP430Wrapper : SDNode<"MSP430ISD::Wrapper", SDT_MSP430Wrapper>; +def MSP430cmp : SDNode<"MSP430ISD::CMP", SDT_MSP430Cmp, [SDNPOutGlue]>; +def MSP430brcc : SDNode<"MSP430ISD::BR_CC", SDT_MSP430BrCC, + [SDNPHasChain, SDNPInGlue]>; +def MSP430selectcc: SDNode<"MSP430ISD::SELECT_CC", SDT_MSP430SelectCC, + [SDNPInGlue]>; +def MSP430shl : SDNode<"MSP430ISD::SHL", SDT_MSP430Shift, []>; +def MSP430sra : SDNode<"MSP430ISD::SRA", SDT_MSP430Shift, []>; +def MSP430srl : SDNode<"MSP430ISD::SRL", SDT_MSP430Shift, []>; + +//===----------------------------------------------------------------------===// +// MSP430 Operand Definitions. +//===----------------------------------------------------------------------===// + +// Address operands +def memsrc : Operand<i16> { + let PrintMethod = "printSrcMemOperand"; + let MIOperandInfo = (ops GR16, i16imm); +} + +def memdst : Operand<i16> { + let PrintMethod = "printSrcMemOperand"; + let MIOperandInfo = (ops GR16, i16imm); +} + +// Short jump targets have OtherVT type and are printed as pcrel imm values. +def jmptarget : Operand<OtherVT> { + let PrintMethod = "printPCRelImmOperand"; +} + +// Operand for printing out a condition code. +def cc : Operand<i8> { + let PrintMethod = "printCCOperand"; +} + +//===----------------------------------------------------------------------===// +// MSP430 Complex Pattern Definitions. +//===----------------------------------------------------------------------===// + +def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>; + +//===----------------------------------------------------------------------===// +// Pattern Fragments +def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; +def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>; +def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ + return N->hasOneUse(); +}]>; +//===----------------------------------------------------------------------===// +// Instruction list.. + +// ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into +// a stack adjustment and the codegen must know that they may modify the stack +// pointer before prolog-epilog rewriting occurs. +// Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become +// sub / add which can clobber SR. +let Defs = [SP, SR], Uses = [SP] in { +def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2), + "#ADJCALLSTACKDOWN", + [(MSP430callseq_start timm:$amt1, timm:$amt2)]>; +def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2), + "#ADJCALLSTACKUP", + [(MSP430callseq_end timm:$amt1, timm:$amt2)]>; +} + +let Defs = [SR], Uses = [SP] in { +def ADDframe : Pseudo<(outs GR16:$dst), (ins i16imm:$base, i16imm:$offset), + "# ADDframe PSEUDO", []>; +} + +let usesCustomInserter = 1 in { + let Uses = [SR] in { + def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$src2, i8imm:$cc), + "# Select8 PSEUDO", + [(set GR8:$dst, + (MSP430selectcc GR8:$src, GR8:$src2, imm:$cc))]>; + def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR16:$src2, i8imm:$cc), + "# Select16 PSEUDO", + [(set GR16:$dst, + (MSP430selectcc GR16:$src, GR16:$src2, imm:$cc))]>; + } + let Defs = [SR] in { + def Shl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt), + "# Shl8 PSEUDO", + [(set GR8:$dst, (MSP430shl GR8:$src, GR8:$cnt))]>; + def Shl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt), + "# Shl16 PSEUDO", + [(set GR16:$dst, (MSP430shl GR16:$src, GR8:$cnt))]>; + def Sra8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt), + "# Sra8 PSEUDO", + [(set GR8:$dst, (MSP430sra GR8:$src, GR8:$cnt))]>; + def Sra16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt), + "# Sra16 PSEUDO", + [(set GR16:$dst, (MSP430sra GR16:$src, GR8:$cnt))]>; + def Srl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt), + "# Srl8 PSEUDO", + [(set GR8:$dst, (MSP430srl GR8:$src, GR8:$cnt))]>; + def Srl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt), + "# Srl16 PSEUDO", + [(set GR16:$dst, (MSP430srl GR16:$src, GR8:$cnt))]>; + + } +} + +let hasSideEffects = 0 in +def NOP : Pseudo<(outs), (ins), "nop", []>; + +//===----------------------------------------------------------------------===// +// Control Flow Instructions... +// + +// FIXME: Provide proper encoding! +let isReturn = 1, isTerminator = 1, isBarrier = 1 in { + def RET : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes, + (outs), (ins), "ret", [(MSP430retflag)]>; + def RETI : II16r<0x0, (outs), (ins), "reti", [(MSP430retiflag)]>; +} + +let isBranch = 1, isTerminator = 1 in { + +// FIXME: expand opcode & cond field for branches! + +// Direct branch +let isBarrier = 1 in { + // Short branch + def JMP : CJForm<0, 0, (outs), (ins jmptarget:$dst), + "jmp\t$dst", + [(br bb:$dst)]>; + let isIndirectBranch = 1 in { + // Long branches + def Bi : I16ri<0, (outs), (ins i16imm:$brdst), + "br\t$brdst", + [(brind tblockaddress:$brdst)]>; + def Br : I16rr<0, (outs), (ins GR16:$brdst), + "br\t$brdst", + [(brind GR16:$brdst)]>; + def Bm : I16rm<0, (outs), (ins memsrc:$brdst), + "br\t$brdst", + [(brind (load addr:$brdst))]>; + } +} + +// Conditional branches +let Uses = [SR] in + def JCC : CJForm<0, 0, + (outs), (ins jmptarget:$dst, cc:$cc), + "j$cc\t$dst", + [(MSP430brcc bb:$dst, imm:$cc)]>; +} // isBranch, isTerminator + +//===----------------------------------------------------------------------===// +// Call Instructions... +// +let isCall = 1 in + // All calls clobber the non-callee saved registers. SPW is marked as + // a use to prevent stack-pointer assignments that appear immediately + // before calls from potentially appearing dead. Uses for argument + // registers are added manually. + let Defs = [R11, R12, R13, R14, R15, SR], + Uses = [SP] in { + def CALLi : II16i<0x0, + (outs), (ins i16imm:$dst), + "call\t$dst", [(MSP430call imm:$dst)]>; + def CALLr : II16r<0x0, + (outs), (ins GR16:$dst), + "call\t$dst", [(MSP430call GR16:$dst)]>; + def CALLm : II16m<0x0, + (outs), (ins memsrc:$dst), + "call\t${dst:mem}", [(MSP430call (load addr:$dst))]>; + } + + +//===----------------------------------------------------------------------===// +// Miscellaneous Instructions... +// +let Defs = [SP], Uses = [SP], hasSideEffects=0 in { +let mayLoad = 1 in +def POP16r : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes, + (outs GR16:$reg), (ins), "pop.w\t$reg", []>; + +let mayStore = 1 in +def PUSH16r : II16r<0x0, + (outs), (ins GR16:$reg), "push.w\t$reg",[]>; +} + +//===----------------------------------------------------------------------===// +// Move Instructions + +// FIXME: Provide proper encoding! +let hasSideEffects = 0 in { +def MOV8rr : I8rr<0x0, + (outs GR8:$dst), (ins GR8:$src), + "mov.b\t{$src, $dst}", + []>; +def MOV16rr : I16rr<0x0, + (outs GR16:$dst), (ins GR16:$src), + "mov.w\t{$src, $dst}", + []>; +} + +// FIXME: Provide proper encoding! +let isReMaterializable = 1, isAsCheapAsAMove = 1 in { +def MOV8ri : I8ri<0x0, + (outs GR8:$dst), (ins i8imm:$src), + "mov.b\t{$src, $dst}", + [(set GR8:$dst, imm:$src)]>; +def MOV16ri : I16ri<0x0, + (outs GR16:$dst), (ins i16imm:$src), + "mov.w\t{$src, $dst}", + [(set GR16:$dst, imm:$src)]>; +} + +let canFoldAsLoad = 1, isReMaterializable = 1 in { +def MOV8rm : I8rm<0x0, + (outs GR8:$dst), (ins memsrc:$src), + "mov.b\t{$src, $dst}", + [(set GR8:$dst, (load addr:$src))]>; +def MOV16rm : I16rm<0x0, + (outs GR16:$dst), (ins memsrc:$src), + "mov.w\t{$src, $dst}", + [(set GR16:$dst, (load addr:$src))]>; +} + +def MOVZX16rr8 : I8rr<0x0, + (outs GR16:$dst), (ins GR8:$src), + "mov.b\t{$src, $dst}", + [(set GR16:$dst, (zext GR8:$src))]>; +def MOVZX16rm8 : I8rm<0x0, + (outs GR16:$dst), (ins memsrc:$src), + "mov.b\t{$src, $dst}", + [(set GR16:$dst, (zextloadi16i8 addr:$src))]>; + +let mayLoad = 1, hasExtraDefRegAllocReq = 1, Constraints = "$base = $base_wb" in { +def MOV8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes, + (outs GR8:$dst, GR16:$base_wb), (ins GR16:$base), + "mov.b\t{@$base+, $dst}", []>; +def MOV16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes, + (outs GR16:$dst, GR16:$base_wb), (ins GR16:$base), + "mov.w\t{@$base+, $dst}", []>; +} + +// Any instruction that defines a 8-bit result leaves the high half of the +// register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may +// be copying from a truncate, but any other 8-bit operation will zero-extend +// up to 16 bits. +def def8 : PatLeaf<(i8 GR8:$src), [{ + return N->getOpcode() != ISD::TRUNCATE && + N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && + N->getOpcode() != ISD::CopyFromReg; +}]>; + +// In the case of a 8-bit def that is known to implicitly zero-extend, +// we can use a SUBREG_TO_REG. +def : Pat<(i16 (zext def8:$src)), + (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>; + +def MOV8mi : I8mi<0x0, + (outs), (ins memdst:$dst, i8imm:$src), + "mov.b\t{$src, $dst}", + [(store (i8 imm:$src), addr:$dst)]>; +def MOV16mi : I16mi<0x0, + (outs), (ins memdst:$dst, i16imm:$src), + "mov.w\t{$src, $dst}", + [(store (i16 imm:$src), addr:$dst)]>; + +def MOV8mr : I8mr<0x0, + (outs), (ins memdst:$dst, GR8:$src), + "mov.b\t{$src, $dst}", + [(store GR8:$src, addr:$dst)]>; +def MOV16mr : I16mr<0x0, + (outs), (ins memdst:$dst, GR16:$src), + "mov.w\t{$src, $dst}", + [(store GR16:$src, addr:$dst)]>; + +def MOV8mm : I8mm<0x0, + (outs), (ins memdst:$dst, memsrc:$src), + "mov.b\t{$src, $dst}", + [(store (i8 (load addr:$src)), addr:$dst)]>; +def MOV16mm : I16mm<0x0, + (outs), (ins memdst:$dst, memsrc:$src), + "mov.w\t{$src, $dst}", + [(store (i16 (load addr:$src)), addr:$dst)]>; + +//===----------------------------------------------------------------------===// +// Arithmetic Instructions + +let Constraints = "$src = $dst" in { + +let Defs = [SR] in { + +let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y + +def ADD8rr : I8rr<0x0, + (outs GR8:$dst), (ins GR8:$src, GR8:$src2), + "add.b\t{$src2, $dst}", + [(set GR8:$dst, (add GR8:$src, GR8:$src2)), + (implicit SR)]>; +def ADD16rr : I16rr<0x0, + (outs GR16:$dst), (ins GR16:$src, GR16:$src2), + "add.w\t{$src2, $dst}", + [(set GR16:$dst, (add GR16:$src, GR16:$src2)), + (implicit SR)]>; +} + +def ADD8rm : I8rm<0x0, + (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), + "add.b\t{$src2, $dst}", + [(set GR8:$dst, (add GR8:$src, (load addr:$src2))), + (implicit SR)]>; +def ADD16rm : I16rm<0x0, + (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), + "add.w\t{$src2, $dst}", + [(set GR16:$dst, (add GR16:$src, (load addr:$src2))), + (implicit SR)]>; + +let mayLoad = 1, hasExtraDefRegAllocReq = 1, +Constraints = "$base = $base_wb, $src = $dst" in { +def ADD8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes, + (outs GR8:$dst, GR16:$base_wb), + (ins GR8:$src, GR16:$base), + "add.b\t{@$base+, $dst}", []>; +def ADD16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes, + (outs GR16:$dst, GR16:$base_wb), + (ins GR16:$src, GR16:$base), + "add.w\t{@$base+, $dst}", []>; +} + + +def ADD8ri : I8ri<0x0, + (outs GR8:$dst), (ins GR8:$src, i8imm:$src2), + "add.b\t{$src2, $dst}", + [(set GR8:$dst, (add GR8:$src, imm:$src2)), + (implicit SR)]>; +def ADD16ri : I16ri<0x0, + (outs GR16:$dst), (ins GR16:$src, i16imm:$src2), + "add.w\t{$src2, $dst}", + [(set GR16:$dst, (add GR16:$src, imm:$src2)), + (implicit SR)]>; + +let Constraints = "" in { +def ADD8mr : I8mr<0x0, + (outs), (ins memdst:$dst, GR8:$src), + "add.b\t{$src, $dst}", + [(store (add (load addr:$dst), GR8:$src), addr:$dst), + (implicit SR)]>; +def ADD16mr : I16mr<0x0, + (outs), (ins memdst:$dst, GR16:$src), + "add.w\t{$src, $dst}", + [(store (add (load addr:$dst), GR16:$src), addr:$dst), + (implicit SR)]>; + +def ADD8mi : I8mi<0x0, + (outs), (ins memdst:$dst, i8imm:$src), + "add.b\t{$src, $dst}", + [(store (add (load addr:$dst), (i8 imm:$src)), addr:$dst), + (implicit SR)]>; +def ADD16mi : I16mi<0x0, + (outs), (ins memdst:$dst, i16imm:$src), + "add.w\t{$src, $dst}", + [(store (add (load addr:$dst), (i16 imm:$src)), addr:$dst), + (implicit SR)]>; + +def ADD8mm : I8mm<0x0, + (outs), (ins memdst:$dst, memsrc:$src), + "add.b\t{$src, $dst}", + [(store (add (load addr:$dst), + (i8 (load addr:$src))), addr:$dst), + (implicit SR)]>; +def ADD16mm : I16mm<0x0, + (outs), (ins memdst:$dst, memsrc:$src), + "add.w\t{$src, $dst}", + [(store (add (load addr:$dst), + (i16 (load addr:$src))), addr:$dst), + (implicit SR)]>; +} + +let Uses = [SR] in { + +let isCommutable = 1 in { // X = ADDC Y, Z == X = ADDC Z, Y +def ADC8rr : I8rr<0x0, + (outs GR8:$dst), (ins GR8:$src, GR8:$src2), + "addc.b\t{$src2, $dst}", + [(set GR8:$dst, (adde GR8:$src, GR8:$src2)), + (implicit SR)]>; +def ADC16rr : I16rr<0x0, + (outs GR16:$dst), (ins GR16:$src, GR16:$src2), + "addc.w\t{$src2, $dst}", + [(set GR16:$dst, (adde GR16:$src, GR16:$src2)), + (implicit SR)]>; +} // isCommutable + +def ADC8ri : I8ri<0x0, + (outs GR8:$dst), (ins GR8:$src, i8imm:$src2), + "addc.b\t{$src2, $dst}", + [(set GR8:$dst, (adde GR8:$src, imm:$src2)), + (implicit SR)]>; +def ADC16ri : I16ri<0x0, + (outs GR16:$dst), (ins GR16:$src, i16imm:$src2), + "addc.w\t{$src2, $dst}", + [(set GR16:$dst, (adde GR16:$src, imm:$src2)), + (implicit SR)]>; + +def ADC8rm : I8rm<0x0, + (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), + "addc.b\t{$src2, $dst}", + [(set GR8:$dst, (adde GR8:$src, (load addr:$src2))), + (implicit SR)]>; +def ADC16rm : I16rm<0x0, + (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), + "addc.w\t{$src2, $dst}", + [(set GR16:$dst, (adde GR16:$src, (load addr:$src2))), + (implicit SR)]>; + +let Constraints = "" in { +def ADC8mr : I8mr<0x0, + (outs), (ins memdst:$dst, GR8:$src), + "addc.b\t{$src, $dst}", + [(store (adde (load addr:$dst), GR8:$src), addr:$dst), + (implicit SR)]>; +def ADC16mr : I16mr<0x0, + (outs), (ins memdst:$dst, GR16:$src), + "addc.w\t{$src, $dst}", + [(store (adde (load addr:$dst), GR16:$src), addr:$dst), + (implicit SR)]>; + +def ADC8mi : I8mi<0x0, + (outs), (ins memdst:$dst, i8imm:$src), + "addc.b\t{$src, $dst}", + [(store (adde (load addr:$dst), (i8 imm:$src)), addr:$dst), + (implicit SR)]>; +def ADC16mi : I16mi<0x0, + (outs), (ins memdst:$dst, i16imm:$src), + "addc.w\t{$src, $dst}", + [(store (adde (load addr:$dst), (i16 imm:$src)), addr:$dst), + (implicit SR)]>; + +def ADC8mm : I8mm<0x0, + (outs), (ins memdst:$dst, memsrc:$src), + "addc.b\t{$src, $dst}", + [(store (adde (load addr:$dst), + (i8 (load addr:$src))), addr:$dst), + (implicit SR)]>; +def ADC16mm : I8mm<0x0, + (outs), (ins memdst:$dst, memsrc:$src), + "addc.w\t{$src, $dst}", + [(store (adde (load addr:$dst), + (i16 (load addr:$src))), addr:$dst), + (implicit SR)]>; +} + +} // Uses = [SR] + +let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y +def AND8rr : I8rr<0x0, + (outs GR8:$dst), (ins GR8:$src, GR8:$src2), + "and.b\t{$src2, $dst}", + [(set GR8:$dst, (and GR8:$src, GR8:$src2)), + (implicit SR)]>; +def AND16rr : I16rr<0x0, + (outs GR16:$dst), (ins GR16:$src, GR16:$src2), + "and.w\t{$src2, $dst}", + [(set GR16:$dst, (and GR16:$src, GR16:$src2)), + (implicit SR)]>; +} + +def AND8ri : I8ri<0x0, + (outs GR8:$dst), (ins GR8:$src, i8imm:$src2), + "and.b\t{$src2, $dst}", + [(set GR8:$dst, (and GR8:$src, imm:$src2)), + (implicit SR)]>; +def AND16ri : I16ri<0x0, + (outs GR16:$dst), (ins GR16:$src, i16imm:$src2), + "and.w\t{$src2, $dst}", + [(set GR16:$dst, (and GR16:$src, imm:$src2)), + (implicit SR)]>; + +def AND8rm : I8rm<0x0, + (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), + "and.b\t{$src2, $dst}", + [(set GR8:$dst, (and GR8:$src, (load addr:$src2))), + (implicit SR)]>; +def AND16rm : I16rm<0x0, + (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), + "and.w\t{$src2, $dst}", + [(set GR16:$dst, (and GR16:$src, (load addr:$src2))), + (implicit SR)]>; + +let mayLoad = 1, hasExtraDefRegAllocReq = 1, +Constraints = "$base = $base_wb, $src = $dst" in { +def AND8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes, + (outs GR8:$dst, GR16:$base_wb), + (ins GR8:$src, GR16:$base), + "and.b\t{@$base+, $dst}", []>; +def AND16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes, + (outs GR16:$dst, GR16:$base_wb), + (ins GR16:$src, GR16:$base), + "and.w\t{@$base+, $dst}", []>; +} + +let Constraints = "" in { +def AND8mr : I8mr<0x0, + (outs), (ins memdst:$dst, GR8:$src), + "and.b\t{$src, $dst}", + [(store (and (load addr:$dst), GR8:$src), addr:$dst), + (implicit SR)]>; +def AND16mr : I16mr<0x0, + (outs), (ins memdst:$dst, GR16:$src), + "and.w\t{$src, $dst}", + [(store (and (load addr:$dst), GR16:$src), addr:$dst), + (implicit SR)]>; + +def AND8mi : I8mi<0x0, + (outs), (ins memdst:$dst, i8imm:$src), + "and.b\t{$src, $dst}", + [(store (and (load addr:$dst), (i8 imm:$src)), addr:$dst), + (implicit SR)]>; +def AND16mi : I16mi<0x0, + (outs), (ins memdst:$dst, i16imm:$src), + "and.w\t{$src, $dst}", + [(store (and (load addr:$dst), (i16 imm:$src)), addr:$dst), + (implicit SR)]>; + +def AND8mm : I8mm<0x0, + (outs), (ins memdst:$dst, memsrc:$src), + "and.b\t{$src, $dst}", + [(store (and (load addr:$dst), + (i8 (load addr:$src))), addr:$dst), + (implicit SR)]>; +def AND16mm : I16mm<0x0, + (outs), (ins memdst:$dst, memsrc:$src), + "and.w\t{$src, $dst}", + [(store (and (load addr:$dst), + (i16 (load addr:$src))), addr:$dst), + (implicit SR)]>; +} + +let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y +def OR8rr : I8rr<0x0, + (outs GR8:$dst), (ins GR8:$src, GR8:$src2), + "bis.b\t{$src2, $dst}", + [(set GR8:$dst, (or GR8:$src, GR8:$src2))]>; +def OR16rr : I16rr<0x0, + (outs GR16:$dst), (ins GR16:$src, GR16:$src2), + "bis.w\t{$src2, $dst}", + [(set GR16:$dst, (or GR16:$src, GR16:$src2))]>; +} + +def OR8ri : I8ri<0x0, + (outs GR8:$dst), (ins GR8:$src, i8imm:$src2), + "bis.b\t{$src2, $dst}", + [(set GR8:$dst, (or GR8:$src, imm:$src2))]>; +def OR16ri : I16ri<0x0, + (outs GR16:$dst), (ins GR16:$src, i16imm:$src2), + "bis.w\t{$src2, $dst}", + [(set GR16:$dst, (or GR16:$src, imm:$src2))]>; + +def OR8rm : I8rm<0x0, + (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), + "bis.b\t{$src2, $dst}", + [(set GR8:$dst, (or GR8:$src, (load addr:$src2)))]>; +def OR16rm : I16rm<0x0, + (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), + "bis.w\t{$src2, $dst}", + [(set GR16:$dst, (or GR16:$src, (load addr:$src2)))]>; + +let mayLoad = 1, hasExtraDefRegAllocReq = 1, +Constraints = "$base = $base_wb, $src = $dst" in { +def OR8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes, + (outs GR8:$dst, GR16:$base_wb), + (ins GR8:$src, GR16:$base), + "bis.b\t{@$base+, $dst}", []>; +def OR16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes, + (outs GR16:$dst, GR16:$base_wb), + (ins GR16:$src, GR16:$base), + "bis.w\t{@$base+, $dst}", []>; +} + +let Constraints = "" in { +def OR8mr : I8mr<0x0, + (outs), (ins memdst:$dst, GR8:$src), + "bis.b\t{$src, $dst}", + [(store (or (load addr:$dst), GR8:$src), addr:$dst)]>; +def OR16mr : I16mr<0x0, + (outs), (ins memdst:$dst, GR16:$src), + "bis.w\t{$src, $dst}", + [(store (or (load addr:$dst), GR16:$src), addr:$dst)]>; + +def OR8mi : I8mi<0x0, + (outs), (ins memdst:$dst, i8imm:$src), + "bis.b\t{$src, $dst}", + [(store (or (load addr:$dst), (i8 imm:$src)), addr:$dst)]>; +def OR16mi : I16mi<0x0, + (outs), (ins memdst:$dst, i16imm:$src), + "bis.w\t{$src, $dst}", + [(store (or (load addr:$dst), (i16 imm:$src)), addr:$dst)]>; + +def OR8mm : I8mm<0x0, + (outs), (ins memdst:$dst, memsrc:$src), + "bis.b\t{$src, $dst}", + [(store (or (i8 (load addr:$dst)), + (i8 (load addr:$src))), addr:$dst)]>; +def OR16mm : I16mm<0x0, + (outs), (ins memdst:$dst, memsrc:$src), + "bis.w\t{$src, $dst}", + [(store (or (i16 (load addr:$dst)), + (i16 (load addr:$src))), addr:$dst)]>; +} + +// bic does not modify condition codes +def BIC8rr : I8rr<0x0, + (outs GR8:$dst), (ins GR8:$src, GR8:$src2), + "bic.b\t{$src2, $dst}", + [(set GR8:$dst, (and GR8:$src, (not GR8:$src2)))]>; +def BIC16rr : I16rr<0x0, + (outs GR16:$dst), (ins GR16:$src, GR16:$src2), + "bic.w\t{$src2, $dst}", + [(set GR16:$dst, (and GR16:$src, (not GR16:$src2)))]>; + +def BIC8rm : I8rm<0x0, + (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), + "bic.b\t{$src2, $dst}", + [(set GR8:$dst, (and GR8:$src, (not (i8 (load addr:$src2)))))]>; +def BIC16rm : I16rm<0x0, + (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), + "bic.w\t{$src2, $dst}", + [(set GR16:$dst, (and GR16:$src, (not (i16 (load addr:$src2)))))]>; + +let Constraints = "" in { +def BIC8mr : I8mr<0x0, + (outs), (ins memdst:$dst, GR8:$src), + "bic.b\t{$src, $dst}", + [(store (and (load addr:$dst), (not GR8:$src)), addr:$dst)]>; +def BIC16mr : I16mr<0x0, + (outs), (ins memdst:$dst, GR16:$src), + "bic.w\t{$src, $dst}", + [(store (and (load addr:$dst), (not GR16:$src)), addr:$dst)]>; + +def BIC8mm : I8mm<0x0, + (outs), (ins memdst:$dst, memsrc:$src), + "bic.b\t{$src, $dst}", + [(store (and (load addr:$dst), + (not (i8 (load addr:$src)))), addr:$dst)]>; +def BIC16mm : I16mm<0x0, + (outs), (ins memdst:$dst, memsrc:$src), + "bic.w\t{$src, $dst}", + [(store (and (load addr:$dst), + (not (i16 (load addr:$src)))), addr:$dst)]>; +} + +let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y +def XOR8rr : I8rr<0x0, + (outs GR8:$dst), (ins GR8:$src, GR8:$src2), + "xor.b\t{$src2, $dst}", + [(set GR8:$dst, (xor GR8:$src, GR8:$src2)), + (implicit SR)]>; +def XOR16rr : I16rr<0x0, + (outs GR16:$dst), (ins GR16:$src, GR16:$src2), + "xor.w\t{$src2, $dst}", + [(set GR16:$dst, (xor GR16:$src, GR16:$src2)), + (implicit SR)]>; +} + +def XOR8ri : I8ri<0x0, + (outs GR8:$dst), (ins GR8:$src, i8imm:$src2), + "xor.b\t{$src2, $dst}", + [(set GR8:$dst, (xor GR8:$src, imm:$src2)), + (implicit SR)]>; +def XOR16ri : I16ri<0x0, + (outs GR16:$dst), (ins GR16:$src, i16imm:$src2), + "xor.w\t{$src2, $dst}", + [(set GR16:$dst, (xor GR16:$src, imm:$src2)), + (implicit SR)]>; + +def XOR8rm : I8rm<0x0, + (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), + "xor.b\t{$src2, $dst}", + [(set GR8:$dst, (xor GR8:$src, (load addr:$src2))), + (implicit SR)]>; +def XOR16rm : I16rm<0x0, + (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), + "xor.w\t{$src2, $dst}", + [(set GR16:$dst, (xor GR16:$src, (load addr:$src2))), + (implicit SR)]>; + +let mayLoad = 1, hasExtraDefRegAllocReq = 1, +Constraints = "$base = $base_wb, $src = $dst" in { +def XOR8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes, + (outs GR8:$dst, GR16:$base_wb), + (ins GR8:$src, GR16:$base), + "xor.b\t{@$base+, $dst}", []>; +def XOR16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes, + (outs GR16:$dst, GR16:$base_wb), + (ins GR16:$src, GR16:$base), + "xor.w\t{@$base+, $dst}", []>; +} + +let Constraints = "" in { +def XOR8mr : I8mr<0x0, + (outs), (ins memdst:$dst, GR8:$src), + "xor.b\t{$src, $dst}", + [(store (xor (load addr:$dst), GR8:$src), addr:$dst), + (implicit SR)]>; +def XOR16mr : I16mr<0x0, + (outs), (ins memdst:$dst, GR16:$src), + "xor.w\t{$src, $dst}", + [(store (xor (load addr:$dst), GR16:$src), addr:$dst), + (implicit SR)]>; + +def XOR8mi : I8mi<0x0, + (outs), (ins memdst:$dst, i8imm:$src), + "xor.b\t{$src, $dst}", + [(store (xor (load addr:$dst), (i8 imm:$src)), addr:$dst), + (implicit SR)]>; +def XOR16mi : I16mi<0x0, + (outs), (ins memdst:$dst, i16imm:$src), + "xor.w\t{$src, $dst}", + [(store (xor (load addr:$dst), (i16 imm:$src)), addr:$dst), + (implicit SR)]>; + +def XOR8mm : I8mm<0x0, + (outs), (ins memdst:$dst, memsrc:$src), + "xor.b\t{$src, $dst}", + [(store (xor (load addr:$dst), (i8 (load addr:$src))), addr:$dst), + (implicit SR)]>; +def XOR16mm : I16mm<0x0, + (outs), (ins memdst:$dst, memsrc:$src), + "xor.w\t{$src, $dst}", + [(store (xor (load addr:$dst), (i16 (load addr:$src))), addr:$dst), + (implicit SR)]>; +} + + +def SUB8rr : I8rr<0x0, + (outs GR8:$dst), (ins GR8:$src, GR8:$src2), + "sub.b\t{$src2, $dst}", + [(set GR8:$dst, (sub GR8:$src, GR8:$src2)), + (implicit SR)]>; +def SUB16rr : I16rr<0x0, + (outs GR16:$dst), (ins GR16:$src, GR16:$src2), + "sub.w\t{$src2, $dst}", + [(set GR16:$dst, (sub GR16:$src, GR16:$src2)), + (implicit SR)]>; + +def SUB8ri : I8ri<0x0, + (outs GR8:$dst), (ins GR8:$src, i8imm:$src2), + "sub.b\t{$src2, $dst}", + [(set GR8:$dst, (sub GR8:$src, imm:$src2)), + (implicit SR)]>; +def SUB16ri : I16ri<0x0, + (outs GR16:$dst), (ins GR16:$src, i16imm:$src2), + "sub.w\t{$src2, $dst}", + [(set GR16:$dst, (sub GR16:$src, imm:$src2)), + (implicit SR)]>; + +def SUB8rm : I8rm<0x0, + (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), + "sub.b\t{$src2, $dst}", + [(set GR8:$dst, (sub GR8:$src, (load addr:$src2))), + (implicit SR)]>; +def SUB16rm : I16rm<0x0, + (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), + "sub.w\t{$src2, $dst}", + [(set GR16:$dst, (sub GR16:$src, (load addr:$src2))), + (implicit SR)]>; + +let mayLoad = 1, hasExtraDefRegAllocReq = 1, +Constraints = "$base = $base_wb, $src = $dst" in { +def SUB8rm_POST : IForm8<0x0, DstReg, SrcPostInc, Size2Bytes, + (outs GR8:$dst, GR16:$base_wb), + (ins GR8:$src, GR16:$base), + "sub.b\t{@$base+, $dst}", []>; +def SUB16rm_POST : IForm16<0x0, DstReg, SrcPostInc, Size2Bytes, + (outs GR16:$dst, GR16:$base_wb), + (ins GR16:$src, GR16:$base), + "sub.w\t{@$base+, $dst}", []>; +} + +let Constraints = "" in { +def SUB8mr : I8mr<0x0, + (outs), (ins memdst:$dst, GR8:$src), + "sub.b\t{$src, $dst}", + [(store (sub (load addr:$dst), GR8:$src), addr:$dst), + (implicit SR)]>; +def SUB16mr : I16mr<0x0, + (outs), (ins memdst:$dst, GR16:$src), + "sub.w\t{$src, $dst}", + [(store (sub (load addr:$dst), GR16:$src), addr:$dst), + (implicit SR)]>; + +def SUB8mi : I8mi<0x0, + (outs), (ins memdst:$dst, i8imm:$src), + "sub.b\t{$src, $dst}", + [(store (sub (load addr:$dst), (i8 imm:$src)), addr:$dst), + (implicit SR)]>; +def SUB16mi : I16mi<0x0, + (outs), (ins memdst:$dst, i16imm:$src), + "sub.w\t{$src, $dst}", + [(store (sub (load addr:$dst), (i16 imm:$src)), addr:$dst), + (implicit SR)]>; + +def SUB8mm : I8mm<0x0, + (outs), (ins memdst:$dst, memsrc:$src), + "sub.b\t{$src, $dst}", + [(store (sub (load addr:$dst), + (i8 (load addr:$src))), addr:$dst), + (implicit SR)]>; +def SUB16mm : I16mm<0x0, + (outs), (ins memdst:$dst, memsrc:$src), + "sub.w\t{$src, $dst}", + [(store (sub (load addr:$dst), + (i16 (load addr:$src))), addr:$dst), + (implicit SR)]>; +} + +let Uses = [SR] in { +def SBC8rr : I8rr<0x0, + (outs GR8:$dst), (ins GR8:$src, GR8:$src2), + "subc.b\t{$src2, $dst}", + [(set GR8:$dst, (sube GR8:$src, GR8:$src2)), + (implicit SR)]>; +def SBC16rr : I16rr<0x0, + (outs GR16:$dst), (ins GR16:$src, GR16:$src2), + "subc.w\t{$src2, $dst}", + [(set GR16:$dst, (sube GR16:$src, GR16:$src2)), + (implicit SR)]>; + +def SBC8ri : I8ri<0x0, + (outs GR8:$dst), (ins GR8:$src, i8imm:$src2), + "subc.b\t{$src2, $dst}", + [(set GR8:$dst, (sube GR8:$src, imm:$src2)), + (implicit SR)]>; +def SBC16ri : I16ri<0x0, + (outs GR16:$dst), (ins GR16:$src, i16imm:$src2), + "subc.w\t{$src2, $dst}", + [(set GR16:$dst, (sube GR16:$src, imm:$src2)), + (implicit SR)]>; + +def SBC8rm : I8rm<0x0, + (outs GR8:$dst), (ins GR8:$src, memsrc:$src2), + "subc.b\t{$src2, $dst}", + [(set GR8:$dst, (sube GR8:$src, (load addr:$src2))), + (implicit SR)]>; +def SBC16rm : I16rm<0x0, + (outs GR16:$dst), (ins GR16:$src, memsrc:$src2), + "subc.w\t{$src2, $dst}", + [(set GR16:$dst, (sube GR16:$src, (load addr:$src2))), + (implicit SR)]>; + +let Constraints = "" in { +def SBC8mr : I8mr<0x0, + (outs), (ins memdst:$dst, GR8:$src), + "subc.b\t{$src, $dst}", + [(store (sube (load addr:$dst), GR8:$src), addr:$dst), + (implicit SR)]>; +def SBC16mr : I16mr<0x0, + (outs), (ins memdst:$dst, GR16:$src), + "subc.w\t{$src, $dst}", + [(store (sube (load addr:$dst), GR16:$src), addr:$dst), + (implicit SR)]>; + +def SBC8mi : I8mi<0x0, + (outs), (ins memdst:$dst, i8imm:$src), + "subc.b\t{$src, $dst}", + [(store (sube (load addr:$dst), (i8 imm:$src)), addr:$dst), + (implicit SR)]>; +def SBC16mi : I16mi<0x0, + (outs), (ins memdst:$dst, i16imm:$src), + "subc.w\t{$src, $dst}", + [(store (sube (load addr:$dst), (i16 imm:$src)), addr:$dst), + (implicit SR)]>; + +def SBC8mm : I8mm<0x0, + (outs), (ins memdst:$dst, memsrc:$src), + "subc.b\t{$src, $dst}", + [(store (sube (load addr:$dst), + (i8 (load addr:$src))), addr:$dst), + (implicit SR)]>; +def SBC16mm : I16mm<0x0, + (outs), (ins memdst:$dst, memsrc:$src), + "subc.w\t{$src, $dst}", + [(store (sube (load addr:$dst), + (i16 (load addr:$src))), addr:$dst), + (implicit SR)]>; +} + +} // Uses = [SR] + +// FIXME: memory variant! +def SAR8r1 : II8r<0x0, + (outs GR8:$dst), (ins GR8:$src), + "rra.b\t$dst", + [(set GR8:$dst, (MSP430rra GR8:$src)), + (implicit SR)]>; +def SAR16r1 : II16r<0x0, + (outs GR16:$dst), (ins GR16:$src), + "rra.w\t$dst", + [(set GR16:$dst, (MSP430rra GR16:$src)), + (implicit SR)]>; + +def SHL8r1 : I8rr<0x0, + (outs GR8:$dst), (ins GR8:$src), + "rla.b\t$dst", + [(set GR8:$dst, (MSP430rla GR8:$src)), + (implicit SR)]>; +def SHL16r1 : I16rr<0x0, + (outs GR16:$dst), (ins GR16:$src), + "rla.w\t$dst", + [(set GR16:$dst, (MSP430rla GR16:$src)), + (implicit SR)]>; + +def SAR8r1c : Pseudo<(outs GR8:$dst), (ins GR8:$src), + "clrc\n\t" + "rrc.b\t$dst", + [(set GR8:$dst, (MSP430rrc GR8:$src)), + (implicit SR)]>; +def SAR16r1c : Pseudo<(outs GR16:$dst), (ins GR16:$src), + "clrc\n\t" + "rrc.w\t$dst", + [(set GR16:$dst, (MSP430rrc GR16:$src)), + (implicit SR)]>; + +// FIXME: Memory sext's ? +def SEXT16r : II16r<0x0, + (outs GR16:$dst), (ins GR16:$src), + "sxt\t$dst", + [(set GR16:$dst, (sext_inreg GR16:$src, i8)), + (implicit SR)]>; + +} // Defs = [SR] + +def ZEXT16r : I8rr<0x0, + (outs GR16:$dst), (ins GR16:$src), + "mov.b\t{$src, $dst}", + [(set GR16:$dst, (zext (trunc GR16:$src)))]>; + +// FIXME: Memory bitswaps? +def SWPB16r : II16r<0x0, + (outs GR16:$dst), (ins GR16:$src), + "swpb\t$dst", + [(set GR16:$dst, (bswap GR16:$src))]>; + +} // Constraints = "$src = $dst" + +// Integer comparisons +let Defs = [SR] in { +def CMP8rr : I8rr<0x0, + (outs), (ins GR8:$src, GR8:$src2), + "cmp.b\t{$src2, $src}", + [(MSP430cmp GR8:$src, GR8:$src2), (implicit SR)]>; +def CMP16rr : I16rr<0x0, + (outs), (ins GR16:$src, GR16:$src2), + "cmp.w\t{$src2, $src}", + [(MSP430cmp GR16:$src, GR16:$src2), (implicit SR)]>; + +def CMP8ri : I8ri<0x0, + (outs), (ins GR8:$src, i8imm:$src2), + "cmp.b\t{$src2, $src}", + [(MSP430cmp GR8:$src, imm:$src2), (implicit SR)]>; +def CMP16ri : I16ri<0x0, + (outs), (ins GR16:$src, i16imm:$src2), + "cmp.w\t{$src2, $src}", + [(MSP430cmp GR16:$src, imm:$src2), (implicit SR)]>; + +def CMP8mi : I8mi<0x0, + (outs), (ins memsrc:$src, i8imm:$src2), + "cmp.b\t{$src2, $src}", + [(MSP430cmp (load addr:$src), + (i8 imm:$src2)), (implicit SR)]>; +def CMP16mi : I16mi<0x0, + (outs), (ins memsrc:$src, i16imm:$src2), + "cmp.w\t{$src2, $src}", + [(MSP430cmp (load addr:$src), + (i16 imm:$src2)), (implicit SR)]>; + +def CMP8rm : I8rm<0x0, + (outs), (ins GR8:$src, memsrc:$src2), + "cmp.b\t{$src2, $src}", + [(MSP430cmp GR8:$src, (load addr:$src2)), + (implicit SR)]>; +def CMP16rm : I16rm<0x0, + (outs), (ins GR16:$src, memsrc:$src2), + "cmp.w\t{$src2, $src}", + [(MSP430cmp GR16:$src, (load addr:$src2)), + (implicit SR)]>; + +def CMP8mr : I8mr<0x0, + (outs), (ins memsrc:$src, GR8:$src2), + "cmp.b\t{$src2, $src}", + [(MSP430cmp (load addr:$src), GR8:$src2), + (implicit SR)]>; +def CMP16mr : I16mr<0x0, + (outs), (ins memsrc:$src, GR16:$src2), + "cmp.w\t{$src2, $src}", + [(MSP430cmp (load addr:$src), GR16:$src2), + (implicit SR)]>; + + +// BIT TESTS, just sets condition codes +// Note that the C condition is set differently than when using CMP. +let isCommutable = 1 in { +def BIT8rr : I8rr<0x0, + (outs), (ins GR8:$src, GR8:$src2), + "bit.b\t{$src2, $src}", + [(MSP430cmp (and_su GR8:$src, GR8:$src2), 0), + (implicit SR)]>; +def BIT16rr : I16rr<0x0, + (outs), (ins GR16:$src, GR16:$src2), + "bit.w\t{$src2, $src}", + [(MSP430cmp (and_su GR16:$src, GR16:$src2), 0), + (implicit SR)]>; +} +def BIT8ri : I8ri<0x0, + (outs), (ins GR8:$src, i8imm:$src2), + "bit.b\t{$src2, $src}", + [(MSP430cmp (and_su GR8:$src, imm:$src2), 0), + (implicit SR)]>; +def BIT16ri : I16ri<0x0, + (outs), (ins GR16:$src, i16imm:$src2), + "bit.w\t{$src2, $src}", + [(MSP430cmp (and_su GR16:$src, imm:$src2), 0), + (implicit SR)]>; + +def BIT8rm : I8rm<0x0, + (outs), (ins GR8:$src, memdst:$src2), + "bit.b\t{$src2, $src}", + [(MSP430cmp (and_su GR8:$src, (load addr:$src2)), 0), + (implicit SR)]>; +def BIT16rm : I16rm<0x0, + (outs), (ins GR16:$src, memdst:$src2), + "bit.w\t{$src2, $src}", + [(MSP430cmp (and_su GR16:$src, (load addr:$src2)), 0), + (implicit SR)]>; + +def BIT8mr : I8mr<0x0, + (outs), (ins memsrc:$src, GR8:$src2), + "bit.b\t{$src2, $src}", + [(MSP430cmp (and_su (load addr:$src), GR8:$src2), 0), + (implicit SR)]>; +def BIT16mr : I16mr<0x0, + (outs), (ins memsrc:$src, GR16:$src2), + "bit.w\t{$src2, $src}", + [(MSP430cmp (and_su (load addr:$src), GR16:$src2), 0), + (implicit SR)]>; + +def BIT8mi : I8mi<0x0, + (outs), (ins memsrc:$src, i8imm:$src2), + "bit.b\t{$src2, $src}", + [(MSP430cmp (and_su (load addr:$src), (i8 imm:$src2)), 0), + (implicit SR)]>; +def BIT16mi : I16mi<0x0, + (outs), (ins memsrc:$src, i16imm:$src2), + "bit.w\t{$src2, $src}", + [(MSP430cmp (and_su (load addr:$src), (i16 imm:$src2)), 0), + (implicit SR)]>; + +def BIT8mm : I8mm<0x0, + (outs), (ins memsrc:$src, memsrc:$src2), + "bit.b\t{$src2, $src}", + [(MSP430cmp (and_su (i8 (load addr:$src)), + (load addr:$src2)), + 0), + (implicit SR)]>; +def BIT16mm : I16mm<0x0, + (outs), (ins memsrc:$src, memsrc:$src2), + "bit.w\t{$src2, $src}", + [(MSP430cmp (and_su (i16 (load addr:$src)), + (load addr:$src2)), + 0), + (implicit SR)]>; +} // Defs = [SR] + +//===----------------------------------------------------------------------===// +// Non-Instruction Patterns + +// extload +def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; + +// anyext +def : Pat<(i16 (anyext GR8:$src)), + (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>; + +// truncs +def : Pat<(i8 (trunc GR16:$src)), + (EXTRACT_SUBREG GR16:$src, subreg_8bit)>; + +// GlobalAddress, ExternalSymbol +def : Pat<(i16 (MSP430Wrapper tglobaladdr:$dst)), (MOV16ri tglobaladdr:$dst)>; +def : Pat<(i16 (MSP430Wrapper texternalsym:$dst)), (MOV16ri texternalsym:$dst)>; +def : Pat<(i16 (MSP430Wrapper tblockaddress:$dst)), (MOV16ri tblockaddress:$dst)>; + +def : Pat<(add GR16:$src, (MSP430Wrapper tglobaladdr :$src2)), + (ADD16ri GR16:$src, tglobaladdr:$src2)>; +def : Pat<(add GR16:$src, (MSP430Wrapper texternalsym:$src2)), + (ADD16ri GR16:$src, texternalsym:$src2)>; +def : Pat<(add GR16:$src, (MSP430Wrapper tblockaddress:$src2)), + (ADD16ri GR16:$src, tblockaddress:$src2)>; + +def : Pat<(store (i16 (MSP430Wrapper tglobaladdr:$src)), addr:$dst), + (MOV16mi addr:$dst, tglobaladdr:$src)>; +def : Pat<(store (i16 (MSP430Wrapper texternalsym:$src)), addr:$dst), + (MOV16mi addr:$dst, texternalsym:$src)>; +def : Pat<(store (i16 (MSP430Wrapper tblockaddress:$src)), addr:$dst), + (MOV16mi addr:$dst, tblockaddress:$src)>; + +// calls +def : Pat<(MSP430call (i16 tglobaladdr:$dst)), + (CALLi tglobaladdr:$dst)>; +def : Pat<(MSP430call (i16 texternalsym:$dst)), + (CALLi texternalsym:$dst)>; + +// add and sub always produce carry +def : Pat<(addc GR16:$src, GR16:$src2), + (ADD16rr GR16:$src, GR16:$src2)>; +def : Pat<(addc GR16:$src, (load addr:$src2)), + (ADD16rm GR16:$src, addr:$src2)>; +def : Pat<(addc GR16:$src, imm:$src2), + (ADD16ri GR16:$src, imm:$src2)>; +def : Pat<(store (addc (load addr:$dst), GR16:$src), addr:$dst), + (ADD16mr addr:$dst, GR16:$src)>; +def : Pat<(store (addc (load addr:$dst), (i16 (load addr:$src))), addr:$dst), + (ADD16mm addr:$dst, addr:$src)>; + +def : Pat<(addc GR8:$src, GR8:$src2), + (ADD8rr GR8:$src, GR8:$src2)>; +def : Pat<(addc GR8:$src, (load addr:$src2)), + (ADD8rm GR8:$src, addr:$src2)>; +def : Pat<(addc GR8:$src, imm:$src2), + (ADD8ri GR8:$src, imm:$src2)>; +def : Pat<(store (addc (load addr:$dst), GR8:$src), addr:$dst), + (ADD8mr addr:$dst, GR8:$src)>; +def : Pat<(store (addc (load addr:$dst), (i8 (load addr:$src))), addr:$dst), + (ADD8mm addr:$dst, addr:$src)>; + +def : Pat<(subc GR16:$src, GR16:$src2), + (SUB16rr GR16:$src, GR16:$src2)>; +def : Pat<(subc GR16:$src, (load addr:$src2)), + (SUB16rm GR16:$src, addr:$src2)>; +def : Pat<(subc GR16:$src, imm:$src2), + (SUB16ri GR16:$src, imm:$src2)>; +def : Pat<(store (subc (load addr:$dst), GR16:$src), addr:$dst), + (SUB16mr addr:$dst, GR16:$src)>; +def : Pat<(store (subc (load addr:$dst), (i16 (load addr:$src))), addr:$dst), + (SUB16mm addr:$dst, addr:$src)>; + +def : Pat<(subc GR8:$src, GR8:$src2), + (SUB8rr GR8:$src, GR8:$src2)>; +def : Pat<(subc GR8:$src, (load addr:$src2)), + (SUB8rm GR8:$src, addr:$src2)>; +def : Pat<(subc GR8:$src, imm:$src2), + (SUB8ri GR8:$src, imm:$src2)>; +def : Pat<(store (subc (load addr:$dst), GR8:$src), addr:$dst), + (SUB8mr addr:$dst, GR8:$src)>; +def : Pat<(store (subc (load addr:$dst), (i8 (load addr:$src))), addr:$dst), + (SUB8mm addr:$dst, addr:$src)>; + +// peephole patterns +def : Pat<(and GR16:$src, 255), (ZEXT16r GR16:$src)>; +def : Pat<(MSP430cmp (trunc (and_su GR16:$src, GR16:$src2)), 0), + (BIT8rr (EXTRACT_SUBREG GR16:$src, subreg_8bit), + (EXTRACT_SUBREG GR16:$src2, subreg_8bit))>; diff --git a/contrib/llvm/lib/Target/MSP430/MSP430MCInstLower.cpp b/contrib/llvm/lib/Target/MSP430/MSP430MCInstLower.cpp new file mode 100644 index 000000000000..e7716382b222 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430MCInstLower.cpp @@ -0,0 +1,157 @@ +//===-- MSP430MCInstLower.cpp - Convert MSP430 MachineInstr to an MCInst --===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains code to lower MSP430 MachineInstrs to their corresponding +// MCInst records. +// +//===----------------------------------------------------------------------===// + +#include "MSP430MCInstLower.h" +#include "llvm/ADT/SmallString.h" +#include "llvm/CodeGen/AsmPrinter.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineInstr.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/IR/Mangler.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCInst.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetMachine.h" +using namespace llvm; + +MCSymbol *MSP430MCInstLower:: +GetGlobalAddressSymbol(const MachineOperand &MO) const { + switch (MO.getTargetFlags()) { + default: llvm_unreachable("Unknown target flag on GV operand"); + case 0: break; + } + + return Printer.getSymbol(MO.getGlobal()); +} + +MCSymbol *MSP430MCInstLower:: +GetExternalSymbolSymbol(const MachineOperand &MO) const { + switch (MO.getTargetFlags()) { + default: llvm_unreachable("Unknown target flag on GV operand"); + case 0: break; + } + + return Printer.GetExternalSymbolSymbol(MO.getSymbolName()); +} + +MCSymbol *MSP430MCInstLower:: +GetJumpTableSymbol(const MachineOperand &MO) const { + const DataLayout &DL = Printer.getDataLayout(); + SmallString<256> Name; + raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "JTI" + << Printer.getFunctionNumber() << '_' + << MO.getIndex(); + + switch (MO.getTargetFlags()) { + default: llvm_unreachable("Unknown target flag on GV operand"); + case 0: break; + } + + // Create a symbol for the name. + return Ctx.getOrCreateSymbol(Name); +} + +MCSymbol *MSP430MCInstLower:: +GetConstantPoolIndexSymbol(const MachineOperand &MO) const { + const DataLayout &DL = Printer.getDataLayout(); + SmallString<256> Name; + raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "CPI" + << Printer.getFunctionNumber() << '_' + << MO.getIndex(); + + switch (MO.getTargetFlags()) { + default: llvm_unreachable("Unknown target flag on GV operand"); + case 0: break; + } + + // Create a symbol for the name. + return Ctx.getOrCreateSymbol(Name); +} + +MCSymbol *MSP430MCInstLower:: +GetBlockAddressSymbol(const MachineOperand &MO) const { + switch (MO.getTargetFlags()) { + default: llvm_unreachable("Unknown target flag on GV operand"); + case 0: break; + } + + return Printer.GetBlockAddressSymbol(MO.getBlockAddress()); +} + +MCOperand MSP430MCInstLower:: +LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const { + // FIXME: We would like an efficient form for this, so we don't have to do a + // lot of extra uniquing. + const MCExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx); + + switch (MO.getTargetFlags()) { + default: llvm_unreachable("Unknown target flag on GV operand"); + case 0: break; + } + + if (!MO.isJTI() && MO.getOffset()) + Expr = MCBinaryExpr::createAdd(Expr, + MCConstantExpr::create(MO.getOffset(), Ctx), + Ctx); + return MCOperand::createExpr(Expr); +} + +void MSP430MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { + OutMI.setOpcode(MI->getOpcode()); + + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI->getOperand(i); + + MCOperand MCOp; + switch (MO.getType()) { + default: + MI->print(errs()); + llvm_unreachable("unknown operand type"); + case MachineOperand::MO_Register: + // Ignore all implicit register operands. + if (MO.isImplicit()) continue; + MCOp = MCOperand::createReg(MO.getReg()); + break; + case MachineOperand::MO_Immediate: + MCOp = MCOperand::createImm(MO.getImm()); + break; + case MachineOperand::MO_MachineBasicBlock: + MCOp = MCOperand::createExpr(MCSymbolRefExpr::create( + MO.getMBB()->getSymbol(), Ctx)); + break; + case MachineOperand::MO_GlobalAddress: + MCOp = LowerSymbolOperand(MO, GetGlobalAddressSymbol(MO)); + break; + case MachineOperand::MO_ExternalSymbol: + MCOp = LowerSymbolOperand(MO, GetExternalSymbolSymbol(MO)); + break; + case MachineOperand::MO_JumpTableIndex: + MCOp = LowerSymbolOperand(MO, GetJumpTableSymbol(MO)); + break; + case MachineOperand::MO_ConstantPoolIndex: + MCOp = LowerSymbolOperand(MO, GetConstantPoolIndexSymbol(MO)); + break; + case MachineOperand::MO_BlockAddress: + MCOp = LowerSymbolOperand(MO, GetBlockAddressSymbol(MO)); + break; + case MachineOperand::MO_RegisterMask: + continue; + } + + OutMI.addOperand(MCOp); + } +} diff --git a/contrib/llvm/lib/Target/MSP430/MSP430MCInstLower.h b/contrib/llvm/lib/Target/MSP430/MSP430MCInstLower.h new file mode 100644 index 000000000000..ebd639744bcc --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430MCInstLower.h @@ -0,0 +1,47 @@ +//===-- MSP430MCInstLower.h - Lower MachineInstr to MCInst ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_MSP430_MSP430MCINSTLOWER_H +#define LLVM_LIB_TARGET_MSP430_MSP430MCINSTLOWER_H + +#include "llvm/Support/Compiler.h" + +namespace llvm { + class AsmPrinter; + class MCContext; + class MCInst; + class MCOperand; + class MCSymbol; + class MachineInstr; + class MachineModuleInfoMachO; + class MachineOperand; + + /// MSP430MCInstLower - This class is used to lower an MachineInstr + /// into an MCInst. +class LLVM_LIBRARY_VISIBILITY MSP430MCInstLower { + MCContext &Ctx; + + AsmPrinter &Printer; +public: + MSP430MCInstLower(MCContext &ctx, AsmPrinter &printer) + : Ctx(ctx), Printer(printer) {} + void Lower(const MachineInstr *MI, MCInst &OutMI) const; + + MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const; + + MCSymbol *GetGlobalAddressSymbol(const MachineOperand &MO) const; + MCSymbol *GetExternalSymbolSymbol(const MachineOperand &MO) const; + MCSymbol *GetJumpTableSymbol(const MachineOperand &MO) const; + MCSymbol *GetConstantPoolIndexSymbol(const MachineOperand &MO) const; + MCSymbol *GetBlockAddressSymbol(const MachineOperand &MO) const; +}; + +} + +#endif diff --git a/contrib/llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.cpp b/contrib/llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.cpp new file mode 100644 index 000000000000..b442fc03b257 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.cpp @@ -0,0 +1,14 @@ +//===-- MSP430MachineFunctionInfo.cpp - MSP430 machine function info ------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "MSP430MachineFunctionInfo.h" + +using namespace llvm; + +void MSP430MachineFunctionInfo::anchor() { } diff --git a/contrib/llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h b/contrib/llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h new file mode 100644 index 000000000000..fcaa8a1d6c72 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h @@ -0,0 +1,62 @@ +//=== MSP430MachineFunctionInfo.h - MSP430 machine function info -*- C++ -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares MSP430-specific per-machine-function information. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_MSP430_MSP430MACHINEFUNCTIONINFO_H +#define LLVM_LIB_TARGET_MSP430_MSP430MACHINEFUNCTIONINFO_H + +#include "llvm/CodeGen/MachineFunction.h" + +namespace llvm { + +/// MSP430MachineFunctionInfo - This class is derived from MachineFunction and +/// contains private MSP430 target-specific information for each MachineFunction. +class MSP430MachineFunctionInfo : public MachineFunctionInfo { + virtual void anchor(); + + /// CalleeSavedFrameSize - Size of the callee-saved register portion of the + /// stack frame in bytes. + unsigned CalleeSavedFrameSize; + + /// ReturnAddrIndex - FrameIndex for return slot. + int ReturnAddrIndex; + + /// VarArgsFrameIndex - FrameIndex for start of varargs area. + int VarArgsFrameIndex; + + /// SRetReturnReg - Some subtargets require that sret lowering includes + /// returning the value of the returned struct in a register. This field + /// holds the virtual register into which the sret argument is passed. + unsigned SRetReturnReg; + +public: + MSP430MachineFunctionInfo() : CalleeSavedFrameSize(0) {} + + explicit MSP430MachineFunctionInfo(MachineFunction &MF) + : CalleeSavedFrameSize(0), ReturnAddrIndex(0), SRetReturnReg(0) {} + + unsigned getCalleeSavedFrameSize() const { return CalleeSavedFrameSize; } + void setCalleeSavedFrameSize(unsigned bytes) { CalleeSavedFrameSize = bytes; } + + unsigned getSRetReturnReg() const { return SRetReturnReg; } + void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } + + int getRAIndex() const { return ReturnAddrIndex; } + void setRAIndex(int Index) { ReturnAddrIndex = Index; } + + int getVarArgsFrameIndex() const { return VarArgsFrameIndex;} + void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; } +}; + +} // End llvm namespace + +#endif diff --git a/contrib/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp b/contrib/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp new file mode 100644 index 000000000000..7a3b7a8bd5ff --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp @@ -0,0 +1,161 @@ +//===-- MSP430RegisterInfo.cpp - MSP430 Register Information --------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the MSP430 implementation of the TargetRegisterInfo class. +// +//===----------------------------------------------------------------------===// + +#include "MSP430RegisterInfo.h" +#include "MSP430.h" +#include "MSP430MachineFunctionInfo.h" +#include "MSP430TargetMachine.h" +#include "llvm/ADT/BitVector.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/IR/Function.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetOptions.h" + +using namespace llvm; + +#define DEBUG_TYPE "msp430-reg-info" + +#define GET_REGINFO_TARGET_DESC +#include "MSP430GenRegisterInfo.inc" + +// FIXME: Provide proper call frame setup / destroy opcodes. +MSP430RegisterInfo::MSP430RegisterInfo() + : MSP430GenRegisterInfo(MSP430::PC) {} + +const MCPhysReg* +MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { + const MSP430FrameLowering *TFI = getFrameLowering(*MF); + const Function* F = MF->getFunction(); + static const MCPhysReg CalleeSavedRegs[] = { + MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, + MSP430::R8, MSP430::R9, MSP430::R10, + 0 + }; + static const MCPhysReg CalleeSavedRegsFP[] = { + MSP430::R5, MSP430::R6, MSP430::R7, + MSP430::R8, MSP430::R9, MSP430::R10, + 0 + }; + static const MCPhysReg CalleeSavedRegsIntr[] = { + MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7, + MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, + MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, + 0 + }; + static const MCPhysReg CalleeSavedRegsIntrFP[] = { + MSP430::R5, MSP430::R6, MSP430::R7, + MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11, + MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, + 0 + }; + + if (TFI->hasFP(*MF)) + return (F->getCallingConv() == CallingConv::MSP430_INTR ? + CalleeSavedRegsIntrFP : CalleeSavedRegsFP); + else + return (F->getCallingConv() == CallingConv::MSP430_INTR ? + CalleeSavedRegsIntr : CalleeSavedRegs); + +} + +BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const { + BitVector Reserved(getNumRegs()); + const MSP430FrameLowering *TFI = getFrameLowering(MF); + + // Mark 4 special registers with subregisters as reserved. + Reserved.set(MSP430::PCB); + Reserved.set(MSP430::SPB); + Reserved.set(MSP430::SRB); + Reserved.set(MSP430::CGB); + Reserved.set(MSP430::PC); + Reserved.set(MSP430::SP); + Reserved.set(MSP430::SR); + Reserved.set(MSP430::CG); + + // Mark frame pointer as reserved if needed. + if (TFI->hasFP(MF)) { + Reserved.set(MSP430::FPB); + Reserved.set(MSP430::FP); + } + + return Reserved; +} + +const TargetRegisterClass * +MSP430RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) + const { + return &MSP430::GR16RegClass; +} + +void +MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, + int SPAdj, unsigned FIOperandNum, + RegScavenger *RS) const { + assert(SPAdj == 0 && "Unexpected"); + + MachineInstr &MI = *II; + MachineBasicBlock &MBB = *MI.getParent(); + MachineFunction &MF = *MBB.getParent(); + const MSP430FrameLowering *TFI = getFrameLowering(MF); + DebugLoc dl = MI.getDebugLoc(); + int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); + + unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FP : MSP430::SP); + int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex); + + // Skip the saved PC + Offset += 2; + + if (!TFI->hasFP(MF)) + Offset += MF.getFrameInfo().getStackSize(); + else + Offset += 2; // Skip the saved FP + + // Fold imm into offset + Offset += MI.getOperand(FIOperandNum + 1).getImm(); + + if (MI.getOpcode() == MSP430::ADDframe) { + // This is actually "load effective address" of the stack slot + // instruction. We have only two-address instructions, thus we need to + // expand it into mov + add + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); + + MI.setDesc(TII.get(MSP430::MOV16rr)); + MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false); + + if (Offset == 0) + return; + + // We need to materialize the offset via add instruction. + unsigned DstReg = MI.getOperand(0).getReg(); + if (Offset < 0) + BuildMI(MBB, std::next(II), dl, TII.get(MSP430::SUB16ri), DstReg) + .addReg(DstReg).addImm(-Offset); + else + BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg) + .addReg(DstReg).addImm(Offset); + + return; + } + + MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false); + MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); +} + +unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const { + const MSP430FrameLowering *TFI = getFrameLowering(MF); + return TFI->hasFP(MF) ? MSP430::FP : MSP430::SP; +} diff --git a/contrib/llvm/lib/Target/MSP430/MSP430RegisterInfo.h b/contrib/llvm/lib/Target/MSP430/MSP430RegisterInfo.h new file mode 100644 index 000000000000..0cfa4a42bfe4 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430RegisterInfo.h @@ -0,0 +1,46 @@ +//===-- MSP430RegisterInfo.h - MSP430 Register Information Impl -*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the MSP430 implementation of the MRegisterInfo class. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_MSP430_MSP430REGISTERINFO_H +#define LLVM_LIB_TARGET_MSP430_MSP430REGISTERINFO_H + +#include "llvm/Target/TargetRegisterInfo.h" + +#define GET_REGINFO_HEADER +#include "MSP430GenRegisterInfo.inc" + +namespace llvm { + +struct MSP430RegisterInfo : public MSP430GenRegisterInfo { +public: + MSP430RegisterInfo(); + + /// Code Generation virtual methods... + const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override; + + BitVector getReservedRegs(const MachineFunction &MF) const override; + const TargetRegisterClass* + getPointerRegClass(const MachineFunction &MF, + unsigned Kind = 0) const override; + + void eliminateFrameIndex(MachineBasicBlock::iterator II, + int SPAdj, unsigned FIOperandNum, + RegScavenger *RS = nullptr) const override; + + // Debug information queries. + unsigned getFrameRegister(const MachineFunction &MF) const override; +}; + +} // end namespace llvm + +#endif diff --git a/contrib/llvm/lib/Target/MSP430/MSP430RegisterInfo.td b/contrib/llvm/lib/Target/MSP430/MSP430RegisterInfo.td new file mode 100644 index 000000000000..b5a6ed0f0a56 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430RegisterInfo.td @@ -0,0 +1,81 @@ +//===-- MSP430RegisterInfo.td - MSP430 Register defs -------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Declarations that describe the MSP430 register file +//===----------------------------------------------------------------------===// + +class MSP430Reg<bits<4> num, string n> : Register<n> { + field bits<4> Num = num; + let Namespace = "MSP430"; +} + +class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs> + : RegisterWithSubRegs<n, subregs> { + field bits<4> Num = num; + let Namespace = "MSP430"; +} + +//===----------------------------------------------------------------------===// +// Registers +//===----------------------------------------------------------------------===// + +def PCB : MSP430Reg<0, "r0">; +def SPB : MSP430Reg<1, "r1">; +def SRB : MSP430Reg<2, "r2">; +def CGB : MSP430Reg<3, "r3">; +def FPB : MSP430Reg<4, "r4">; +def R5B : MSP430Reg<5, "r5">; +def R6B : MSP430Reg<6, "r6">; +def R7B : MSP430Reg<7, "r7">; +def R8B : MSP430Reg<8, "r8">; +def R9B : MSP430Reg<9, "r9">; +def R10B : MSP430Reg<10, "r10">; +def R11B : MSP430Reg<11, "r11">; +def R12B : MSP430Reg<12, "r12">; +def R13B : MSP430Reg<13, "r13">; +def R14B : MSP430Reg<14, "r14">; +def R15B : MSP430Reg<15, "r15">; + +def subreg_8bit : SubRegIndex<8> { let Namespace = "MSP430"; } + +let SubRegIndices = [subreg_8bit] in { +def PC : MSP430RegWithSubregs<0, "r0", [PCB]>; +def SP : MSP430RegWithSubregs<1, "r1", [SPB]>; +def SR : MSP430RegWithSubregs<2, "r2", [SRB]>; +def CG : MSP430RegWithSubregs<3, "r3", [CGB]>; +def FP : MSP430RegWithSubregs<4, "r4", [FPB]>; +def R5 : MSP430RegWithSubregs<5, "r5", [R5B]>; +def R6 : MSP430RegWithSubregs<6, "r6", [R6B]>; +def R7 : MSP430RegWithSubregs<7, "r7", [R7B]>; +def R8 : MSP430RegWithSubregs<8, "r8", [R8B]>; +def R9 : MSP430RegWithSubregs<9, "r9", [R9B]>; +def R10 : MSP430RegWithSubregs<10, "r10", [R10B]>; +def R11 : MSP430RegWithSubregs<11, "r11", [R11B]>; +def R12 : MSP430RegWithSubregs<12, "r12", [R12B]>; +def R13 : MSP430RegWithSubregs<13, "r13", [R13B]>; +def R14 : MSP430RegWithSubregs<14, "r14", [R14B]>; +def R15 : MSP430RegWithSubregs<15, "r15", [R15B]>; +} + +def GR8 : RegisterClass<"MSP430", [i8], 8, + // Volatile registers + (add R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B, + // Frame pointer, sometimes allocable + FPB, + // Volatile, but not allocable + PCB, SPB, SRB, CGB)>; + +def GR16 : RegisterClass<"MSP430", [i16], 16, + // Volatile registers + (add R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5, + // Frame pointer, sometimes allocable + FP, + // Volatile, but not allocable + PC, SP, SR, CG)>; diff --git a/contrib/llvm/lib/Target/MSP430/MSP430Subtarget.cpp b/contrib/llvm/lib/Target/MSP430/MSP430Subtarget.cpp new file mode 100644 index 000000000000..776a9dcb11d4 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430Subtarget.cpp @@ -0,0 +1,62 @@ +//===-- MSP430Subtarget.cpp - MSP430 Subtarget Information ----------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the MSP430 specific subclass of TargetSubtargetInfo. +// +//===----------------------------------------------------------------------===// + +#include "MSP430Subtarget.h" +#include "MSP430.h" +#include "llvm/Support/TargetRegistry.h" + +using namespace llvm; + +#define DEBUG_TYPE "msp430-subtarget" + +static cl::opt<MSP430Subtarget::HWMultEnum> +HWMultModeOption("mhwmult", cl::Hidden, + cl::desc("Hardware multiplier use mode for MSP430"), + cl::init(MSP430Subtarget::NoHWMult), + cl::values( + clEnumValN(MSP430Subtarget::NoHWMult, "none", + "Do not use hardware multiplier"), + clEnumValN(MSP430Subtarget::HWMult16, "16bit", + "Use 16-bit hardware multiplier"), + clEnumValN(MSP430Subtarget::HWMult32, "32bit", + "Use 32-bit hardware multiplier"), + clEnumValN(MSP430Subtarget::HWMultF5, "f5series", + "Use F5 series hardware multiplier"))); + +#define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR +#include "MSP430GenSubtargetInfo.inc" + +void MSP430Subtarget::anchor() { } + +MSP430Subtarget & +MSP430Subtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { + ExtendedInsts = false; + HWMultMode = NoHWMult; + + std::string CPUName = CPU; + if (CPUName.empty()) + CPUName = "msp430"; + + ParseSubtargetFeatures(CPUName, FS); + + if (HWMultModeOption != NoHWMult) + HWMultMode = HWMultModeOption; + + return *this; +} + +MSP430Subtarget::MSP430Subtarget(const Triple &TT, const std::string &CPU, + const std::string &FS, const TargetMachine &TM) + : MSP430GenSubtargetInfo(TT, CPU, FS), FrameLowering(), + InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this) {} diff --git a/contrib/llvm/lib/Target/MSP430/MSP430Subtarget.h b/contrib/llvm/lib/Target/MSP430/MSP430Subtarget.h new file mode 100644 index 000000000000..8828dfd65878 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430Subtarget.h @@ -0,0 +1,80 @@ +//===-- MSP430Subtarget.h - Define Subtarget for the MSP430 ----*- C++ -*--===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the MSP430 specific subclass of TargetSubtargetInfo. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_MSP430_MSP430SUBTARGET_H +#define LLVM_LIB_TARGET_MSP430_MSP430SUBTARGET_H + +#include "MSP430FrameLowering.h" +#include "MSP430ISelLowering.h" +#include "MSP430InstrInfo.h" +#include "MSP430RegisterInfo.h" +#include "llvm/CodeGen/SelectionDAGTargetInfo.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/Target/TargetSubtargetInfo.h" +#include <string> + +#define GET_SUBTARGETINFO_HEADER +#include "MSP430GenSubtargetInfo.inc" + +namespace llvm { +class StringRef; + +class MSP430Subtarget : public MSP430GenSubtargetInfo { +public: + enum HWMultEnum { + NoHWMult, HWMult16, HWMult32, HWMultF5 + }; + +private: + virtual void anchor(); + bool ExtendedInsts; + HWMultEnum HWMultMode; + MSP430FrameLowering FrameLowering; + MSP430InstrInfo InstrInfo; + MSP430TargetLowering TLInfo; + SelectionDAGTargetInfo TSInfo; + +public: + /// This constructor initializes the data members to match that + /// of the specified triple. + /// + MSP430Subtarget(const Triple &TT, const std::string &CPU, + const std::string &FS, const TargetMachine &TM); + + MSP430Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); + + /// ParseSubtargetFeatures - Parses features string setting specified + /// subtarget options. Definition of function is auto generated by tblgen. + void ParseSubtargetFeatures(StringRef CPU, StringRef FS); + + bool hasHWMult16() const { return HWMultMode == HWMult16; } + bool hasHWMult32() const { return HWMultMode == HWMult32; } + bool hasHWMultF5() const { return HWMultMode == HWMultF5; } + + const TargetFrameLowering *getFrameLowering() const override { + return &FrameLowering; + } + const MSP430InstrInfo *getInstrInfo() const override { return &InstrInfo; } + const TargetRegisterInfo *getRegisterInfo() const override { + return &InstrInfo.getRegisterInfo(); + } + const MSP430TargetLowering *getTargetLowering() const override { + return &TLInfo; + } + const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { + return &TSInfo; + } +}; +} // End llvm namespace + +#endif // LLVM_TARGET_MSP430_SUBTARGET_H diff --git a/contrib/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp b/contrib/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp new file mode 100644 index 000000000000..982c6fea62d4 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430TargetMachine.cpp @@ -0,0 +1,84 @@ +//===-- MSP430TargetMachine.cpp - Define TargetMachine for MSP430 ---------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Top-level implementation for the MSP430 target. +// +//===----------------------------------------------------------------------===// + +#include "MSP430TargetMachine.h" +#include "MSP430.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" +#include "llvm/CodeGen/TargetPassConfig.h" +#include "llvm/IR/LegacyPassManager.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/Support/TargetRegistry.h" +using namespace llvm; + +extern "C" void LLVMInitializeMSP430Target() { + // Register the target. + RegisterTargetMachine<MSP430TargetMachine> X(getTheMSP430Target()); +} + +static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { + if (!RM.hasValue()) + return Reloc::Static; + return *RM; +} + +static std::string computeDataLayout(const Triple &TT, StringRef CPU, + const TargetOptions &Options) { + return "e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16"; +} + +MSP430TargetMachine::MSP430TargetMachine(const Target &T, const Triple &TT, + StringRef CPU, StringRef FS, + const TargetOptions &Options, + Optional<Reloc::Model> RM, + CodeModel::Model CM, + CodeGenOpt::Level OL) + : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options), TT, CPU, FS, + Options, getEffectiveRelocModel(RM), CM, OL), + TLOF(make_unique<TargetLoweringObjectFileELF>()), + Subtarget(TT, CPU, FS, *this) { + initAsmInfo(); +} + +MSP430TargetMachine::~MSP430TargetMachine() {} + +namespace { +/// MSP430 Code Generator Pass Configuration Options. +class MSP430PassConfig : public TargetPassConfig { +public: + MSP430PassConfig(MSP430TargetMachine &TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} + + MSP430TargetMachine &getMSP430TargetMachine() const { + return getTM<MSP430TargetMachine>(); + } + + bool addInstSelector() override; + void addPreEmitPass() override; +}; +} // namespace + +TargetPassConfig *MSP430TargetMachine::createPassConfig(PassManagerBase &PM) { + return new MSP430PassConfig(*this, PM); +} + +bool MSP430PassConfig::addInstSelector() { + // Install an instruction selector. + addPass(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel())); + return false; +} + +void MSP430PassConfig::addPreEmitPass() { + // Must run branch selection immediately preceding the asm printer. + addPass(createMSP430BranchSelectionPass(), false); +} diff --git a/contrib/llvm/lib/Target/MSP430/MSP430TargetMachine.h b/contrib/llvm/lib/Target/MSP430/MSP430TargetMachine.h new file mode 100644 index 000000000000..de8f06e71dee --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/MSP430TargetMachine.h @@ -0,0 +1,49 @@ +//===-- MSP430TargetMachine.h - Define TargetMachine for MSP430 -*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the MSP430 specific subclass of TargetMachine. +// +//===----------------------------------------------------------------------===// + + +#ifndef LLVM_LIB_TARGET_MSP430_MSP430TARGETMACHINE_H +#define LLVM_LIB_TARGET_MSP430_MSP430TARGETMACHINE_H + +#include "MSP430Subtarget.h" +#include "llvm/Target/TargetFrameLowering.h" +#include "llvm/Target/TargetMachine.h" + +namespace llvm { + +/// MSP430TargetMachine +/// +class MSP430TargetMachine : public LLVMTargetMachine { + std::unique_ptr<TargetLoweringObjectFile> TLOF; + MSP430Subtarget Subtarget; + +public: + MSP430TargetMachine(const Target &T, const Triple &TT, StringRef CPU, + StringRef FS, const TargetOptions &Options, + Optional<Reloc::Model> RM, CodeModel::Model CM, + CodeGenOpt::Level OL); + ~MSP430TargetMachine() override; + + const MSP430Subtarget *getSubtargetImpl(const Function &F) const override { + return &Subtarget; + } + TargetPassConfig *createPassConfig(PassManagerBase &PM) override; + + TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF.get(); + } +}; // MSP430TargetMachine. + +} // end namespace llvm + +#endif diff --git a/contrib/llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp b/contrib/llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp new file mode 100644 index 000000000000..62f52a193674 --- /dev/null +++ b/contrib/llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.cpp @@ -0,0 +1,23 @@ +//===-- MSP430TargetInfo.cpp - MSP430 Target Implementation ---------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "MSP430.h" +#include "llvm/IR/Module.h" +#include "llvm/Support/TargetRegistry.h" +using namespace llvm; + +Target &llvm::getTheMSP430Target() { + static Target TheMSP430Target; + return TheMSP430Target; +} + +extern "C" void LLVMInitializeMSP430TargetInfo() { + RegisterTarget<Triple::msp430> X(getTheMSP430Target(), "msp430", + "MSP430 [experimental]"); +} |