diff options
Diffstat (limited to 'contrib/llvm/lib/Target/Hexagon')
108 files changed, 58737 insertions, 17444 deletions
diff --git a/contrib/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/contrib/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp index becc086c81b0..4bbc36a86e5b 100644 --- a/contrib/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp +++ b/contrib/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp @@ -63,21 +63,25 @@ using namespace llvm; static cl::opt<bool> EnableFutureRegs("mfuture-regs", cl::desc("Enable future registers")); -static cl::opt<bool> WarnMissingParenthesis("mwarn-missing-parenthesis", -cl::desc("Warn for missing parenthesis around predicate registers"), -cl::init(true)); -static cl::opt<bool> ErrorMissingParenthesis("merror-missing-parenthesis", -cl::desc("Error for missing parenthesis around predicate registers"), -cl::init(false)); -static cl::opt<bool> WarnSignedMismatch("mwarn-sign-mismatch", -cl::desc("Warn for mismatching a signed and unsigned value"), -cl::init(true)); -static cl::opt<bool> WarnNoncontigiousRegister("mwarn-noncontigious-register", -cl::desc("Warn for register names that arent contigious"), -cl::init(true)); -static cl::opt<bool> ErrorNoncontigiousRegister("merror-noncontigious-register", -cl::desc("Error for register names that aren't contigious"), -cl::init(false)); +static cl::opt<bool> WarnMissingParenthesis( + "mwarn-missing-parenthesis", + cl::desc("Warn for missing parenthesis around predicate registers"), + cl::init(true)); +static cl::opt<bool> ErrorMissingParenthesis( + "merror-missing-parenthesis", + cl::desc("Error for missing parenthesis around predicate registers"), + cl::init(false)); +static cl::opt<bool> WarnSignedMismatch( + "mwarn-sign-mismatch", + cl::desc("Warn for mismatching a signed and unsigned value"), + cl::init(true)); +static cl::opt<bool> WarnNoncontigiousRegister( + "mwarn-noncontigious-register", + cl::desc("Warn for register names that arent contigious"), cl::init(true)); +static cl::opt<bool> ErrorNoncontigiousRegister( + "merror-noncontigious-register", + cl::desc("Error for register names that aren't contigious"), + cl::init(false)); namespace { @@ -123,9 +127,11 @@ class HexagonAsmParser : public MCTargetAsmParser { bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, - uint64_t &ErrorInfo, bool MatchingInlineAsm) override; + uint64_t &ErrorInfo, + bool MatchingInlineAsm) override; - unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override; + unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, + unsigned Kind) override; bool OutOfRange(SMLoc IDLoc, long long Val, long long Max); int processInstruction(MCInst &Inst, OperandVector const &Operands, SMLoc IDLoc); @@ -168,11 +174,10 @@ public: bool parseInstruction(OperandVector &Operands); bool implicitExpressionLocation(OperandVector &Operands); bool parseExpressionOrOperand(OperandVector &Operands); - bool parseExpression(MCExpr const *& Expr); + bool parseExpression(MCExpr const *&Expr); bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, - SMLoc NameLoc, OperandVector &Operands) override - { + SMLoc NameLoc, OperandVector &Operands) override { llvm_unreachable("Unimplemented"); } @@ -289,45 +294,63 @@ public: return false; } - bool isf32Ext() const { return false; } - bool iss32_0Imm() const { return CheckImmRange(32, 0, true, true, false); } + bool isa30_2Imm() const { return CheckImmRange(30, 2, true, true, true); } + bool isb30_2Imm() const { return CheckImmRange(30, 2, true, true, true); } + bool isb15_2Imm() const { return CheckImmRange(15, 2, true, true, false); } + bool isb13_2Imm() const { return CheckImmRange(13, 2, true, true, false); } + + bool ism32_0Imm() const { return true; } + + bool isf32Imm() const { return false; } + bool isf64Imm() const { return false; } + bool iss32_0Imm() const { return true; } + bool iss31_1Imm() const { return true; } + bool iss30_2Imm() const { return true; } + bool iss29_3Imm() const { return true; } bool iss23_2Imm() const { return CheckImmRange(23, 2, true, true, false); } + bool iss10_0Imm() const { return CheckImmRange(10, 0, true, false, false); } + bool iss10_6Imm() const { return CheckImmRange(10, 6, true, false, false); } + bool iss9_0Imm() const { return CheckImmRange(9, 0, true, false, false); } bool iss8_0Imm() const { return CheckImmRange(8, 0, true, false, false); } bool iss8_0Imm64() const { return CheckImmRange(8, 0, true, true, false); } bool iss7_0Imm() const { return CheckImmRange(7, 0, true, false, false); } bool iss6_0Imm() const { return CheckImmRange(6, 0, true, false, false); } + bool iss6_3Imm() const { return CheckImmRange(6, 3, true, false, false); } bool iss4_0Imm() const { return CheckImmRange(4, 0, true, false, false); } bool iss4_1Imm() const { return CheckImmRange(4, 1, true, false, false); } bool iss4_2Imm() const { return CheckImmRange(4, 2, true, false, false); } bool iss4_3Imm() const { return CheckImmRange(4, 3, true, false, false); } - bool iss4_6Imm() const { return CheckImmRange(4, 0, true, false, false); } - bool iss3_6Imm() const { return CheckImmRange(3, 0, true, false, false); } bool iss3_0Imm() const { return CheckImmRange(3, 0, true, false, false); } bool isu64_0Imm() const { return CheckImmRange(64, 0, false, true, true); } - bool isu32_0Imm() const { return CheckImmRange(32, 0, false, true, false); } + bool isu32_0Imm() const { return true; } + bool isu31_1Imm() const { return true; } + bool isu30_2Imm() const { return true; } + bool isu29_3Imm() const { return true; } bool isu26_6Imm() const { return CheckImmRange(26, 6, false, true, false); } bool isu16_0Imm() const { return CheckImmRange(16, 0, false, true, false); } bool isu16_1Imm() const { return CheckImmRange(16, 1, false, true, false); } bool isu16_2Imm() const { return CheckImmRange(16, 2, false, true, false); } bool isu16_3Imm() const { return CheckImmRange(16, 3, false, true, false); } bool isu11_3Imm() const { return CheckImmRange(11, 3, false, false, false); } - bool isu6_1Imm() const { return CheckImmRange(6, 1, false, false, false); } - bool isu6_2Imm() const { return CheckImmRange(6, 2, false, false, false); } - bool isu6_3Imm() const { return CheckImmRange(6, 3, false, false, false); } bool isu10_0Imm() const { return CheckImmRange(10, 0, false, false, false); } bool isu9_0Imm() const { return CheckImmRange(9, 0, false, false, false); } bool isu8_0Imm() const { return CheckImmRange(8, 0, false, false, false); } bool isu7_0Imm() const { return CheckImmRange(7, 0, false, false, false); } bool isu6_0Imm() const { return CheckImmRange(6, 0, false, false, false); } + bool isu6_1Imm() const { return CheckImmRange(6, 1, false, false, false); } + bool isu6_2Imm() const { return CheckImmRange(6, 2, false, false, false); } + bool isu6_3Imm() const { return CheckImmRange(6, 3, false, false, false); } bool isu5_0Imm() const { return CheckImmRange(5, 0, false, false, false); } + bool isu5_2Imm() const { return CheckImmRange(5, 2, false, false, false); } + bool isu5_3Imm() const { return CheckImmRange(5, 3, false, false, false); } bool isu4_0Imm() const { return CheckImmRange(4, 0, false, false, false); } + bool isu4_2Imm() const { return CheckImmRange(4, 2, false, false, false); } bool isu3_0Imm() const { return CheckImmRange(3, 0, false, false, false); } + bool isu3_1Imm() const { return CheckImmRange(3, 1, false, false, false); } bool isu2_0Imm() const { return CheckImmRange(2, 0, false, false, false); } bool isu1_0Imm() const { return CheckImmRange(1, 0, false, false, false); } - bool ism6_0Imm() const { return CheckImmRange(6, 0, false, false, false); } - bool isn8_0Imm() const { return CheckImmRange(8, 0, false, false, false); } bool isn1Const() const { if (!isImm()) return false; @@ -336,35 +359,18 @@ public: return false; return Value == -1; } - - bool iss16_0Ext() const { return CheckImmRange(16 + 26, 0, true, true, true); } - bool iss12_0Ext() const { return CheckImmRange(12 + 26, 0, true, true, true); } - bool iss10_0Ext() const { return CheckImmRange(10 + 26, 0, true, true, true); } - bool iss9_0Ext() const { return CheckImmRange(9 + 26, 0, true, true, true); } - bool iss8_0Ext() const { return CheckImmRange(8 + 26, 0, true, true, true); } - bool iss7_0Ext() const { return CheckImmRange(7 + 26, 0, true, true, true); } - bool iss6_0Ext() const { return CheckImmRange(6 + 26, 0, true, true, true); } - bool iss11_0Ext() const { + bool iss11_0Imm() const { return CheckImmRange(11 + 26, 0, true, true, true); } - bool iss11_1Ext() const { + bool iss11_1Imm() const { return CheckImmRange(11 + 26, 1, true, true, true); } - bool iss11_2Ext() const { + bool iss11_2Imm() const { return CheckImmRange(11 + 26, 2, true, true, true); } - bool iss11_3Ext() const { + bool iss11_3Imm() const { return CheckImmRange(11 + 26, 3, true, true, true); } - - bool isu7_0Ext() const { return CheckImmRange(7 + 26, 0, false, true, true); } - bool isu8_0Ext() const { return CheckImmRange(8 + 26, 0, false, true, true); } - bool isu9_0Ext() const { return CheckImmRange(9 + 26, 0, false, true, true); } - bool isu10_0Ext() const { return CheckImmRange(10 + 26, 0, false, true, true); } - bool isu6_0Ext() const { return CheckImmRange(6 + 26, 0, false, true, true); } - bool isu6_1Ext() const { return CheckImmRange(6 + 26, 1, false, true, true); } - bool isu6_2Ext() const { return CheckImmRange(6 + 26, 2, false, true, true); } - bool isu6_3Ext() const { return CheckImmRange(6 + 26, 3, false, true, true); } bool isu32_0MustExt() const { return isImm(); } void addRegOperands(MCInst &Inst, unsigned N) const { @@ -392,188 +398,10 @@ public: Inst.addOperand(MCOperand::createExpr(Expr)); } - void addf32ExtOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - - void adds32_0ImmOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds23_2ImmOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds8_0ImmOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds8_0Imm64Operands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds6_0ImmOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds4_0ImmOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds4_1ImmOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds4_2ImmOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds4_3ImmOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds3_0ImmOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - - void addu64_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu32_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu26_6ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu16_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu16_1ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu16_2ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu16_3ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu11_3ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu10_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu9_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu8_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu7_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu6_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu6_1ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu6_2ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu6_3ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu5_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu4_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu3_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu2_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu1_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - - void addm6_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addn8_0ImmOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - - void adds16_0ExtOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds12_0ExtOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds10_0ExtOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds9_0ExtOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds8_0ExtOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds6_0ExtOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds11_0ExtOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds11_1ExtOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds11_2ExtOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } - void adds11_3ExtOperands(MCInst &Inst, unsigned N) const { - addSignedImmOperands(Inst, N); - } void addn1ConstOperands(MCInst &Inst, unsigned N) const { addImmOperands(Inst, N); } - void addu7_0ExtOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu8_0ExtOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu9_0ExtOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu10_0ExtOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu6_0ExtOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu6_1ExtOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu6_2ExtOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu6_3ExtOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - void addu32_0MustExtOperands(MCInst &Inst, unsigned N) const { - addImmOperands(Inst, N); - } - - void adds4_6ImmOperands(MCInst &Inst, unsigned N) const { - assert(N == 1 && "Invalid number of operands!"); - const MCConstantExpr *CE = - dyn_cast<MCConstantExpr>(&HexagonMCInstrInfo::getExpr(*getImm())); - Inst.addOperand(MCOperand::createImm(CE->getValue() * 64)); - } - - void adds3_6ImmOperands(MCInst &Inst, unsigned N) const { - assert(N == 1 && "Invalid number of operands!"); - const MCConstantExpr *CE = - dyn_cast<MCConstantExpr>(&HexagonMCInstrInfo::getExpr(*getImm())); - Inst.addOperand(MCOperand::createImm(CE->getValue() * 64)); - } - StringRef getToken() const { assert(Kind == Token && "Invalid access!"); return StringRef(Tok.Data, Tok.Length); @@ -749,10 +577,6 @@ bool HexagonAsmParser::matchBundleOptions() { HexagonMCInstrInfo::setInnerLoop(MCB); else if (Option.compare_lower("endloop1") == 0) HexagonMCInstrInfo::setOuterLoop(MCB); - else if (Option.compare_lower("mem_noshuf") == 0) - HexagonMCInstrInfo::setMemReorderDisabled(MCB); - else if (Option.compare_lower("mem_shuf") == 0) - HexagonMCInstrInfo::setMemStoreReorderEnabled(MCB); else return true; Lex(); @@ -770,8 +594,7 @@ void HexagonAsmParser::canonicalizeImmediates(MCInst &MCI) { int64_t Value (I.getImm()); NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( MCConstantExpr::create(Value, getContext()), getContext()))); - } - else { + } else { if (I.isExpr() && cast<HexagonMCExpr>(I.getExpr())->signMismatch() && WarnSignedMismatch) Warning (MCI.getLoc(), "Signed/Unsigned mismatch"); @@ -1066,6 +889,9 @@ bool HexagonAsmParser::ParseDirectiveComm(bool IsLocal, SMLoc Loc) { // validate register against architecture bool HexagonAsmParser::RegisterMatchesArch(unsigned MatchNum) const { + if (HexagonMCRegisterClasses[Hexagon::V62RegsRegClassID].contains(MatchNum)) + if (!getSTI().getFeatureBits()[Hexagon::ArchV62]) + return false; return true; } @@ -1171,11 +997,15 @@ bool HexagonAsmParser::parseOperand(OperandVector &Operands) { bool HexagonAsmParser::isLabel(AsmToken &Token) { MCAsmLexer &Lexer = getLexer(); AsmToken const &Second = Lexer.getTok(); - AsmToken Third = Lexer.peekTok(); + AsmToken Third = Lexer.peekTok(); StringRef String = Token.getString(); if (Token.is(AsmToken::TokenKind::LCurly) || Token.is(AsmToken::TokenKind::RCurly)) return false; + // special case for parsing vwhist256:sat + if (String.lower() == "vwhist256" && Second.is(AsmToken::Colon) && + Third.getString().lower() == "sat") + return false; if (!Token.is(AsmToken::TokenKind::Identifier)) return true; if (!matchRegister(String.lower())) @@ -1756,8 +1586,8 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, TmpInst.setOpcode(Hexagon::L2_loadrdgp); TmpInst.addOperand(MO_0); - TmpInst.addOperand( - MCOperand::createExpr(MCSymbolRefExpr::create(Sym, getContext()))); + TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( + MCSymbolRefExpr::create(Sym, getContext()), getContext()))); Inst = TmpInst; } } @@ -2142,6 +1972,67 @@ int HexagonAsmParser::processInstruction(MCInst &Inst, Inst = TmpInst; break; } + case Hexagon::PS_loadrubabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr())) + Inst.setOpcode(Hexagon::L2_loadrubgp); + break; + case Hexagon::PS_loadrbabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr())) + Inst.setOpcode(Hexagon::L2_loadrbgp); + break; + case Hexagon::PS_loadruhabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr())) + Inst.setOpcode(Hexagon::L2_loadruhgp); + break; + case Hexagon::PS_loadrhabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr())) + Inst.setOpcode(Hexagon::L2_loadrhgp); + break; + case Hexagon::PS_loadriabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr())) + Inst.setOpcode(Hexagon::L2_loadrigp); + break; + case Hexagon::PS_loadrdabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(1).getExpr())) + Inst.setOpcode(Hexagon::L2_loadrdgp); + break; + case Hexagon::PS_storerbabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) + Inst.setOpcode(Hexagon::S2_storerbgp); + break; + case Hexagon::PS_storerhabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) + Inst.setOpcode(Hexagon::S2_storerhgp); + break; + case Hexagon::PS_storerfabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) + Inst.setOpcode(Hexagon::S2_storerfgp); + break; + case Hexagon::PS_storeriabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) + Inst.setOpcode(Hexagon::S2_storerigp); + break; + case Hexagon::PS_storerdabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) + Inst.setOpcode(Hexagon::S2_storerdgp); + break; + case Hexagon::PS_storerbnewabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) + Inst.setOpcode(Hexagon::S2_storerbnewgp); + break; + case Hexagon::PS_storerhnewabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) + Inst.setOpcode(Hexagon::S2_storerhnewgp); + break; + case Hexagon::PS_storerinewabs: + if (!HexagonMCInstrInfo::mustExtend(*Inst.getOperand(0).getExpr())) + Inst.setOpcode(Hexagon::S2_storerinewgp); + break; + case Hexagon::A2_zxtb: { + Inst.setOpcode(Hexagon::A2_andir); + Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(255, Context))); + break; + } } // switch return Match_Success; diff --git a/contrib/llvm/lib/Target/Hexagon/BitTracker.cpp b/contrib/llvm/lib/Target/Hexagon/BitTracker.cpp index 963fb99ce09b..61d3630ac095 100644 --- a/contrib/llvm/lib/Target/Hexagon/BitTracker.cpp +++ b/contrib/llvm/lib/Target/Hexagon/BitTracker.cpp @@ -317,6 +317,15 @@ bool BT::RegisterCell::operator== (const RegisterCell &RC) const { return true; } +BT::RegisterCell &BT::RegisterCell::regify(unsigned R) { + for (unsigned i = 0, n = width(); i < n; ++i) { + const BitValue &V = Bits[i]; + if (V.Type == BitValue::Ref && V.RefI.Reg == 0) + Bits[i].RefI = BitRef(R, i); + } + return *this; +} + uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const { // The general problem is with finding a register class that corresponds // to a given reference reg:sub. There can be several such classes, and @@ -378,12 +387,7 @@ void BT::MachineEvaluator::putCell(const RegisterRef &RR, RegisterCell RC, return; assert(RR.Sub == 0 && "Unexpected sub-register in definition"); // Eliminate all ref-to-reg-0 bit values: replace them with "self". - for (unsigned i = 0, n = RC.width(); i < n; ++i) { - const BitValue &V = RC[i]; - if (V.Type == BitValue::Ref && V.RefI.Reg == 0) - RC[i].RefI = BitRef(RR.Reg, i); - } - M[RR.Reg] = RC; + M[RR.Reg] = RC.regify(RR.Reg); } // Check if the cell represents a compile-time integer value. diff --git a/contrib/llvm/lib/Target/Hexagon/BitTracker.h b/contrib/llvm/lib/Target/Hexagon/BitTracker.h index 48c5f2266acf..a547b34e852f 100644 --- a/contrib/llvm/lib/Target/Hexagon/BitTracker.h +++ b/contrib/llvm/lib/Target/Hexagon/BitTracker.h @@ -283,6 +283,9 @@ struct BitTracker::RegisterCell { return !operator==(RC); } + // Replace the ref-to-reg-0 bit values with the given register. + RegisterCell ®ify(unsigned R); + // Generate a "ref" cell for the corresponding register. In the resulting // cell each bit will be described as being the same as the corresponding // bit in register Reg (i.e. the cell is "defined" by register Reg). diff --git a/contrib/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/contrib/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp index c05fbc1d7756..ae15ed0e9240 100644 --- a/contrib/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/contrib/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -57,11 +57,38 @@ public: ArrayRef<uint8_t> Bytes, uint64_t Address, raw_ostream &VStream, raw_ostream &CStream) const override; - - void adjustExtendedInstructions(MCInst &MCI, MCInst const &MCB) const; void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const; }; +namespace { + uint32_t fullValue(MCInstrInfo const &MCII, MCInst &MCB, MCInst &MI, + int64_t Value) { + MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( + MCB, HexagonMCInstrInfo::bundleSize(MCB)); + if (!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) + return Value; + unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); + uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; + int64_t Bits; + bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits); + assert(Success); (void)Success; + uint32_t Upper26 = static_cast<uint32_t>(Bits); + uint32_t Operand = Upper26 | Lower6; + return Operand; + } + HexagonDisassembler const &disassembler(void const *Decoder) { + return *static_cast<HexagonDisassembler const *>(Decoder); + } + template <size_t T> + void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { + HexagonDisassembler const &Disassembler = disassembler(Decoder); + int64_t FullValue = + fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, + SignExtend64<T>(tmp)); + int64_t Extended = SignExtend64<32>(FullValue); + HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); + } +} } // end anonymous namespace // Forward declare these because the auto-generated code will reference them. @@ -70,6 +97,10 @@ public: static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); @@ -79,6 +110,9 @@ static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); +static DecodeStatus +DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, const void *Decoder); static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); @@ -98,31 +132,10 @@ static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); -static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn); -static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn, - void const *Decoder); - -static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, - raw_ostream &os); - -static unsigned getRegFromSubinstEncoding(unsigned encoded_reg); - static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder); -static DecodeStatus s16_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, - const void *Decoder); -static DecodeStatus s12_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, - const void *Decoder); -static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, - const void *Decoder); -static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, - const void *Decoder); -static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, - const void *Decoder); -static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, - const void *Decoder); -static DecodeStatus s10_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, - const void *Decoder); +static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t /*Address*/, const void *Decoder); static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder); static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, @@ -135,13 +148,12 @@ static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder); static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder); -static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, - const void *Decoder); -static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, +static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder); static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, const void *Decoder); +#include "HexagonDepDecoders.h" #include "HexagonGenDisassemblerTables.inc" static MCDisassembler *createHexagonDisassembler(const Target &T, @@ -175,20 +187,31 @@ DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, Size += HEXAGON_INSTR_SIZE; Bytes = Bytes.slice(HEXAGON_INSTR_SIZE); } - if(Result == MCDisassembler::Fail) + if (Result == MCDisassembler::Fail) return Result; - HexagonMCChecker Checker (*MCII, STI, MI, MI, *getContext().getRegisterInfo()); - if(!Checker.check()) + if (Size > HEXAGON_MAX_PACKET_SIZE) + return MCDisassembler::Fail; + HexagonMCChecker Checker(*MCII, STI, MI, MI, *getContext().getRegisterInfo()); + if (!Checker.check()) return MCDisassembler::Fail; return MCDisassembler::Success; } -static HexagonDisassembler const &disassembler(void const *Decoder) { - return *static_cast<HexagonDisassembler const *>(Decoder); +namespace { +void adjustDuplex(MCInst &MI, MCContext &Context) { + switch (MI.getOpcode()) { + case Hexagon::SA1_setin1: + MI.insert(MI.begin() + 1, + MCOperand::createExpr(MCConstantExpr::create(-1, Context))); + break; + case Hexagon::SA1_dec: + MI.insert(MI.begin() + 2, + MCOperand::createExpr(MCConstantExpr::create(-1, Context))); + break; + default: + break; + } } - -static MCContext &contextFromDecoder(void const *Decoder) { - return disassembler(Decoder).getContext(); } DecodeStatus HexagonDisassembler::getSingleInstruction( @@ -196,8 +219,7 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( raw_ostream &os, raw_ostream &cs, bool &Complete) const { assert(Bytes.size() >= HEXAGON_INSTR_SIZE); - uint32_t Instruction = - (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); + uint32_t Instruction = support::endian::read32le(Bytes.data()); auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB); if ((Instruction & HexagonII::INST_PARSE_MASK) == @@ -210,103 +232,92 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( return DecodeStatus::Fail; } - DecodeStatus Result = DecodeStatus::Success; + MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( + MCB, HexagonMCInstrInfo::bundleSize(MCB)); + + DecodeStatus Result = DecodeStatus::Fail; if ((Instruction & HexagonII::INST_PARSE_MASK) == HexagonII::INST_PARSE_DUPLEX) { - // Determine the instruction class of each instruction in the duplex. - unsigned duplexIClass, IClassLow, IClassHigh; - + unsigned duplexIClass; + uint8_t const *DecodeLow, *DecodeHigh; duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1); switch (duplexIClass) { default: return MCDisassembler::Fail; case 0: - IClassLow = HexagonII::HSIG_L1; - IClassHigh = HexagonII::HSIG_L1; + DecodeLow = DecoderTableSUBINSN_L132; + DecodeHigh = DecoderTableSUBINSN_L132; break; case 1: - IClassLow = HexagonII::HSIG_L2; - IClassHigh = HexagonII::HSIG_L1; + DecodeLow = DecoderTableSUBINSN_L232; + DecodeHigh = DecoderTableSUBINSN_L132; break; case 2: - IClassLow = HexagonII::HSIG_L2; - IClassHigh = HexagonII::HSIG_L2; + DecodeLow = DecoderTableSUBINSN_L232; + DecodeHigh = DecoderTableSUBINSN_L232; break; case 3: - IClassLow = HexagonII::HSIG_A; - IClassHigh = HexagonII::HSIG_A; + DecodeLow = DecoderTableSUBINSN_A32; + DecodeHigh = DecoderTableSUBINSN_A32; break; case 4: - IClassLow = HexagonII::HSIG_L1; - IClassHigh = HexagonII::HSIG_A; + DecodeLow = DecoderTableSUBINSN_L132; + DecodeHigh = DecoderTableSUBINSN_A32; break; case 5: - IClassLow = HexagonII::HSIG_L2; - IClassHigh = HexagonII::HSIG_A; + DecodeLow = DecoderTableSUBINSN_L232; + DecodeHigh = DecoderTableSUBINSN_A32; break; case 6: - IClassLow = HexagonII::HSIG_S1; - IClassHigh = HexagonII::HSIG_A; + DecodeLow = DecoderTableSUBINSN_S132; + DecodeHigh = DecoderTableSUBINSN_A32; break; case 7: - IClassLow = HexagonII::HSIG_S2; - IClassHigh = HexagonII::HSIG_A; + DecodeLow = DecoderTableSUBINSN_S232; + DecodeHigh = DecoderTableSUBINSN_A32; break; case 8: - IClassLow = HexagonII::HSIG_S1; - IClassHigh = HexagonII::HSIG_L1; + DecodeLow = DecoderTableSUBINSN_S132; + DecodeHigh = DecoderTableSUBINSN_L132; break; case 9: - IClassLow = HexagonII::HSIG_S1; - IClassHigh = HexagonII::HSIG_L2; + DecodeLow = DecoderTableSUBINSN_S132; + DecodeHigh = DecoderTableSUBINSN_L232; break; case 10: - IClassLow = HexagonII::HSIG_S1; - IClassHigh = HexagonII::HSIG_S1; + DecodeLow = DecoderTableSUBINSN_S132; + DecodeHigh = DecoderTableSUBINSN_S132; break; case 11: - IClassLow = HexagonII::HSIG_S2; - IClassHigh = HexagonII::HSIG_S1; + DecodeLow = DecoderTableSUBINSN_S232; + DecodeHigh = DecoderTableSUBINSN_S132; break; case 12: - IClassLow = HexagonII::HSIG_S2; - IClassHigh = HexagonII::HSIG_L1; + DecodeLow = DecoderTableSUBINSN_S232; + DecodeHigh = DecoderTableSUBINSN_L132; break; case 13: - IClassLow = HexagonII::HSIG_S2; - IClassHigh = HexagonII::HSIG_L2; + DecodeLow = DecoderTableSUBINSN_S232; + DecodeHigh = DecoderTableSUBINSN_L232; break; case 14: - IClassLow = HexagonII::HSIG_S2; - IClassHigh = HexagonII::HSIG_S2; + DecodeLow = DecoderTableSUBINSN_S232; + DecodeHigh = DecoderTableSUBINSN_S232; break; } - - // Set the MCInst to be a duplex instruction. Which one doesn't matter. - MI.setOpcode(Hexagon::DuplexIClass0); - - // Decode each instruction in the duplex. - // Create an MCInst for each instruction. - unsigned instLow = Instruction & 0x1fff; - unsigned instHigh = (Instruction >> 16) & 0x1fff; - unsigned opLow; - if (GetSubinstOpcode(IClassLow, instLow, opLow, os) != - MCDisassembler::Success) - return MCDisassembler::Fail; - unsigned opHigh; - if (GetSubinstOpcode(IClassHigh, instHigh, opHigh, os) != - MCDisassembler::Success) - return MCDisassembler::Fail; + MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass); MCInst *MILow = new (getContext()) MCInst; - MILow->setOpcode(opLow); MCInst *MIHigh = new (getContext()) MCInst; - MIHigh->setOpcode(opHigh); - addSubinstOperands(MILow, opLow, instLow); - addSubinstOperands(MIHigh, opHigh, instHigh); - // see ConvertToSubInst() in - // lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp - - // Add the duplex instruction MCInsts as operands to the passed in MCInst. + Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address, + this, STI); + if (Result != DecodeStatus::Success) + return DecodeStatus::Fail; + adjustDuplex(*MILow, getContext()); + Result = decodeInstruction( + DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI); + if (Result != DecodeStatus::Success) + return DecodeStatus::Fail; + adjustDuplex(*MIHigh, getContext()); MCOperand OPLow = MCOperand::createInst(MILow); MCOperand OPHigh = MCOperand::createInst(MIHigh); MI.addOperand(OPLow); @@ -316,34 +327,23 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( if ((Instruction & HexagonII::INST_PARSE_MASK) == HexagonII::INST_PARSE_PACKET_END) Complete = true; - // Calling the auto-generated decoder function. - Result = - decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI); - // If a, "standard" insn isn't found check special cases. - if (MCDisassembler::Success != Result || - MI.getOpcode() == Hexagon::A4_ext) { - Result = decodeImmext(MI, Instruction, this); - if (MCDisassembler::Success != Result) { - Result = decodeSpecial(MI, Instruction); - } - } else { - // If the instruction is a compound instruction, register values will - // follow the duplex model, so the register values in the MCInst are - // incorrect. If the instruction is a compound, loop through the - // operands and change registers appropriately. - if (HexagonMCInstrInfo::getType(*MCII, MI) == HexagonII::TypeCOMPOUND) { - for (MCInst::iterator i = MI.begin(), last = MI.end(); i < last; ++i) { - if (i->isReg()) { - unsigned reg = i->getReg() - Hexagon::R0; - i->setReg(getRegFromSubinstEncoding(reg)); - } - } - } - } + if (Extender != nullptr) + Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction, + Address, this, STI); + + if (Result != MCDisassembler::Success) + Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this, + STI); + + if (Result != MCDisassembler::Success && + STI.getFeatureBits()[Hexagon::ExtensionHVX]) + Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction, + Address, this, STI); + } - switch(MI.getOpcode()) { + switch (MI.getOpcode()) { case Hexagon::J4_cmpeqn1_f_jumpnv_nt: case Hexagon::J4_cmpeqn1_f_jumpnv_t: case Hexagon::J4_cmpeqn1_fp0_jump_nt: @@ -368,7 +368,8 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( case Hexagon::J4_cmpgtn1_tp0_jump_t: case Hexagon::J4_cmpgtn1_tp1_jump_nt: case Hexagon::J4_cmpgtn1_tp1_jump_t: - MI.insert(MI.begin() + 1, MCOperand::createExpr(MCConstantExpr::create(-1, getContext()))); + MI.insert(MI.begin() + 1, + MCOperand::createExpr(MCConstantExpr::create(-1, getContext()))); break; default: break; @@ -423,13 +424,10 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( return MCDisassembler::Fail; } - adjustExtendedInstructions(MI, MCB); - MCInst const *Extender = - HexagonMCInstrInfo::extenderForIndex(MCB, - HexagonMCInstrInfo::bundleSize(MCB)); - if(Extender != nullptr) { - MCInst const & Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) ? - *MI.getOperand(1).getInst() : MI; + if (Extender != nullptr) { + MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) + ? *MI.getOperand(1).getInst() + : MI; if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) && !HexagonMCInstrInfo::isExtended(*MCII, Inst)) return MCDisassembler::Fail; @@ -437,68 +435,6 @@ DecodeStatus HexagonDisassembler::getSingleInstruction( return Result; } -void HexagonDisassembler::adjustExtendedInstructions(MCInst &MCI, - MCInst const &MCB) const { - if (!HexagonMCInstrInfo::hasExtenderForIndex( - MCB, HexagonMCInstrInfo::bundleSize(MCB))) { - unsigned opcode; - // This code is used by the disassembler to disambiguate between GP - // relative and absolute addressing instructions since they both have - // same encoding bits. However, an absolute addressing instruction must - // follow an immediate extender. Disassembler alwaus select absolute - // addressing instructions first and uses this code to change them into - // GP relative instruction in the absence of the corresponding immediate - // extender. - switch (MCI.getOpcode()) { - case Hexagon::PS_storerbabs: - opcode = Hexagon::S2_storerbgp; - break; - case Hexagon::PS_storerhabs: - opcode = Hexagon::S2_storerhgp; - break; - case Hexagon::PS_storerfabs: - opcode = Hexagon::S2_storerfgp; - break; - case Hexagon::PS_storeriabs: - opcode = Hexagon::S2_storerigp; - break; - case Hexagon::PS_storerbnewabs: - opcode = Hexagon::S2_storerbnewgp; - break; - case Hexagon::PS_storerhnewabs: - opcode = Hexagon::S2_storerhnewgp; - break; - case Hexagon::PS_storerinewabs: - opcode = Hexagon::S2_storerinewgp; - break; - case Hexagon::PS_storerdabs: - opcode = Hexagon::S2_storerdgp; - break; - case Hexagon::PS_loadrbabs: - opcode = Hexagon::L2_loadrbgp; - break; - case Hexagon::PS_loadrubabs: - opcode = Hexagon::L2_loadrubgp; - break; - case Hexagon::PS_loadrhabs: - opcode = Hexagon::L2_loadrhgp; - break; - case Hexagon::PS_loadruhabs: - opcode = Hexagon::L2_loadruhgp; - break; - case Hexagon::PS_loadriabs: - opcode = Hexagon::L2_loadrigp; - break; - case Hexagon::PS_loadrdabs: - opcode = Hexagon::L2_loadrdgp; - break; - default: - opcode = MCI.getOpcode(); - } - MCI.setOpcode(opcode); - } -} - static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, ArrayRef<MCPhysReg> Table) { if (RegNo < Table.size()) { @@ -530,6 +466,20 @@ static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable); } +static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder) { + static const MCPhysReg GeneralSubRegDecoderTable[] = { + Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, + Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7, + Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, + Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, + }; + + return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable); +} + static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { @@ -557,6 +507,15 @@ static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable); } +static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass( + MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { + static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = { + Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, + Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11}; + + return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable); +} + static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { @@ -590,17 +549,23 @@ static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { + using namespace Hexagon; static const MCPhysReg CtrlRegDecoderTable[] = { - Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1, - Hexagon::P3_0, Hexagon::C5, Hexagon::C6, Hexagon::C7, - Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP, - Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPC + /* 0 */ SA0, LC0, SA1, LC1, + /* 4 */ P3_0, C5, C6, C7, + /* 8 */ USR, PC, UGP, GP, + /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI, + /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI, + /* 20 */ 0, 0, 0, 0, + /* 24 */ 0, 0, 0, 0, + /* 28 */ 0, 0, UTIMERLO, UTIMERHI }; if (RegNo >= array_lengthof(CtrlRegDecoderTable)) return MCDisassembler::Fail; - if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister) + static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); + if (CtrlRegDecoderTable[RegNo] == NoRegister) return MCDisassembler::Fail; unsigned Register = CtrlRegDecoderTable[RegNo]; @@ -611,20 +576,23 @@ static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) { + using namespace Hexagon; static const MCPhysReg CtrlReg64DecoderTable[] = { - Hexagon::C1_0, Hexagon::NoRegister, - Hexagon::C3_2, Hexagon::NoRegister, - Hexagon::C7_6, Hexagon::NoRegister, - Hexagon::C9_8, Hexagon::NoRegister, - Hexagon::C11_10, Hexagon::NoRegister, - Hexagon::CS, Hexagon::NoRegister, - Hexagon::UPC, Hexagon::NoRegister + /* 0 */ C1_0, 0, C3_2, 0, + /* 4 */ C5_4, 0, C7_6, 0, + /* 8 */ C9_8, 0, C11_10, 0, + /* 12 */ CS, 0, UPCYCLE, 0, + /* 16 */ C17_16, 0, PKTCOUNT, 0, + /* 20 */ 0, 0, 0, 0, + /* 24 */ 0, 0, 0, 0, + /* 28 */ 0, 0, UTIMER, 0 }; if (RegNo >= array_lengthof(CtrlReg64DecoderTable)) return MCDisassembler::Fail; - if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister) + static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); + if (CtrlReg64DecoderTable[RegNo] == NoRegister) return MCDisassembler::Fail; unsigned Register = CtrlReg64DecoderTable[RegNo]; @@ -650,132 +618,23 @@ static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, return MCDisassembler::Success; } -static uint32_t fullValue(MCInstrInfo const &MCII, MCInst &MCB, MCInst &MI, - int64_t Value) { - MCInst const *Extender = HexagonMCInstrInfo::extenderForIndex( - MCB, HexagonMCInstrInfo::bundleSize(MCB)); - if(!Extender || MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) - return Value; - unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); - uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f; - int64_t Bits; - bool Success = Extender->getOperand(0).getExpr()->evaluateAsAbsolute(Bits); - assert(Success);(void)Success; - uint32_t Upper26 = static_cast<uint32_t>(Bits); - uint32_t Operand = Upper26 | Lower6; - return Operand; -} - -template <size_t T> -static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) { - HexagonDisassembler const &Disassembler = disassembler(Decoder); - int64_t FullValue = fullValue(*Disassembler.MCII, - **Disassembler.CurrentBundle, - MI, SignExtend64<T>(tmp)); - int64_t Extended = SignExtend64<32>(FullValue); - HexagonMCInstrInfo::addConstant(MI, Extended, - Disassembler.getContext()); -} - static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/, const void *Decoder) { HexagonDisassembler const &Disassembler = disassembler(Decoder); - int64_t FullValue = fullValue(*Disassembler.MCII, - **Disassembler.CurrentBundle, - MI, tmp); + int64_t FullValue = + fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, tmp); assert(FullValue >= 0 && "Negative in unsigned decoder"); HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext()); return MCDisassembler::Success; } -static DecodeStatus s16_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<16>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s12_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<12>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<11>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s11_1ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - HexagonMCInstrInfo::addConstant(MI, SignExtend64<12>(tmp), contextFromDecoder(Decoder)); - return MCDisassembler::Success; -} - -static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, +static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/, const void *Decoder) { - signedDecoder<13>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<14>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s10_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<10>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/, - const void *Decoder) { - signedDecoder<8>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<6>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<4>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<5>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<6>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<7>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s4_6ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<10>(MI, tmp, Decoder); - return MCDisassembler::Success; -} - -static DecodeStatus s3_6ImmDecoder(MCInst &MI, unsigned tmp, - uint64_t /*Address*/, const void *Decoder) { - signedDecoder<19>(MI, tmp, Decoder); + HexagonDisassembler const &Disassembler = disassembler(Decoder); + unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI); + tmp = SignExtend64(tmp, Bits); + signedDecoder<32>(MI, tmp, Decoder); return MCDisassembler::Success; } @@ -787,838 +646,13 @@ static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address, // r13_2 is not extendable, so if there are no extent bits, it's r13_2 if (Bits == 0) Bits = 15; - uint32_t FullValue = fullValue(*Disassembler.MCII, - **Disassembler.CurrentBundle, - MI, SignExtend64(tmp, Bits)); + uint32_t FullValue = + fullValue(*Disassembler.MCII, **Disassembler.CurrentBundle, MI, + SignExtend64(tmp, Bits)); int64_t Extended = SignExtend64<32>(FullValue) + Address; - if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, - 0, 4)) + if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4)) HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext()); return MCDisassembler::Success; } -// Addressing mode dependent load store opcode map. -// - If an insn is preceded by an extender the address is absolute. -// - memw(##symbol) = r0 -// - If an insn is not preceded by an extender the address is GP relative. -// - memw(gp + #symbol) = r0 -// Please note that the instructions must be ordered in the descending order -// of their opcode. -// HexagonII::INST_ICLASS_ST -static const unsigned int StoreConditionalOpcodeData[][2] = { - {S4_pstorerdfnew_abs, 0xafc02084}, - {S4_pstorerdtnew_abs, 0xafc02080}, - {S4_pstorerdf_abs, 0xafc00084}, - {S4_pstorerdt_abs, 0xafc00080}, - {S4_pstorerinewfnew_abs, 0xafa03084}, - {S4_pstorerinewtnew_abs, 0xafa03080}, - {S4_pstorerhnewfnew_abs, 0xafa02884}, - {S4_pstorerhnewtnew_abs, 0xafa02880}, - {S4_pstorerbnewfnew_abs, 0xafa02084}, - {S4_pstorerbnewtnew_abs, 0xafa02080}, - {S4_pstorerinewf_abs, 0xafa01084}, - {S4_pstorerinewt_abs, 0xafa01080}, - {S4_pstorerhnewf_abs, 0xafa00884}, - {S4_pstorerhnewt_abs, 0xafa00880}, - {S4_pstorerbnewf_abs, 0xafa00084}, - {S4_pstorerbnewt_abs, 0xafa00080}, - {S4_pstorerifnew_abs, 0xaf802084}, - {S4_pstoreritnew_abs, 0xaf802080}, - {S4_pstorerif_abs, 0xaf800084}, - {S4_pstorerit_abs, 0xaf800080}, - {S4_pstorerhfnew_abs, 0xaf402084}, - {S4_pstorerhtnew_abs, 0xaf402080}, - {S4_pstorerhf_abs, 0xaf400084}, - {S4_pstorerht_abs, 0xaf400080}, - {S4_pstorerbfnew_abs, 0xaf002084}, - {S4_pstorerbtnew_abs, 0xaf002080}, - {S4_pstorerbf_abs, 0xaf000084}, - {S4_pstorerbt_abs, 0xaf000080}}; -// HexagonII::INST_ICLASS_LD - -// HexagonII::INST_ICLASS_LD_ST_2 -static unsigned int LoadStoreOpcodeData[][2] = {{PS_loadrdabs, 0x49c00000}, - {PS_loadriabs, 0x49800000}, - {PS_loadruhabs, 0x49600000}, - {PS_loadrhabs, 0x49400000}, - {PS_loadrubabs, 0x49200000}, - {PS_loadrbabs, 0x49000000}, - {PS_storerdabs, 0x48c00000}, - {PS_storerinewabs, 0x48a01000}, - {PS_storerhnewabs, 0x48a00800}, - {PS_storerbnewabs, 0x48a00000}, - {PS_storeriabs, 0x48800000}, - {PS_storerfabs, 0x48600000}, - {PS_storerhabs, 0x48400000}, - {PS_storerbabs, 0x48000000}}; -static const size_t NumCondS = array_lengthof(StoreConditionalOpcodeData); -static const size_t NumLS = array_lengthof(LoadStoreOpcodeData); - -static DecodeStatus decodeSpecial(MCInst &MI, uint32_t insn) { - unsigned MachineOpcode = 0; - unsigned LLVMOpcode = 0; - - if ((insn & HexagonII::INST_ICLASS_MASK) == HexagonII::INST_ICLASS_ST) { - for (size_t i = 0; i < NumCondS; ++i) { - if ((insn & StoreConditionalOpcodeData[i][1]) == - StoreConditionalOpcodeData[i][1]) { - MachineOpcode = StoreConditionalOpcodeData[i][1]; - LLVMOpcode = StoreConditionalOpcodeData[i][0]; - break; - } - } - } - if ((insn & HexagonII::INST_ICLASS_MASK) == HexagonII::INST_ICLASS_LD_ST_2) { - for (size_t i = 0; i < NumLS; ++i) { - if ((insn & LoadStoreOpcodeData[i][1]) == LoadStoreOpcodeData[i][1]) { - MachineOpcode = LoadStoreOpcodeData[i][1]; - LLVMOpcode = LoadStoreOpcodeData[i][0]; - break; - } - } - } - - if (MachineOpcode) { - unsigned Value = 0; - unsigned shift = 0; - MI.setOpcode(LLVMOpcode); - // Remove the parse bits from the insn. - insn &= ~HexagonII::INST_PARSE_MASK; - - switch (LLVMOpcode) { - default: - return MCDisassembler::Fail; - break; - - case Hexagon::S4_pstorerdf_abs: - case Hexagon::S4_pstorerdt_abs: - case Hexagon::S4_pstorerdfnew_abs: - case Hexagon::S4_pstorerdtnew_abs: - // op: Pv - Value = insn & UINT64_C(3); - DecodePredRegsRegisterClass(MI, Value, 0, nullptr); - // op: u6 - Value = (insn >> 12) & UINT64_C(48); - Value |= (insn >> 3) & UINT64_C(15); - MI.addOperand(MCOperand::createImm(Value)); - // op: Rtt - Value = (insn >> 8) & UINT64_C(31); - DecodeDoubleRegsRegisterClass(MI, Value, 0, nullptr); - break; - - case Hexagon::S4_pstorerbnewf_abs: - case Hexagon::S4_pstorerbnewt_abs: - case Hexagon::S4_pstorerbnewfnew_abs: - case Hexagon::S4_pstorerbnewtnew_abs: - case Hexagon::S4_pstorerhnewf_abs: - case Hexagon::S4_pstorerhnewt_abs: - case Hexagon::S4_pstorerhnewfnew_abs: - case Hexagon::S4_pstorerhnewtnew_abs: - case Hexagon::S4_pstorerinewf_abs: - case Hexagon::S4_pstorerinewt_abs: - case Hexagon::S4_pstorerinewfnew_abs: - case Hexagon::S4_pstorerinewtnew_abs: - // op: Pv - Value = insn & UINT64_C(3); - DecodePredRegsRegisterClass(MI, Value, 0, nullptr); - // op: u6 - Value = (insn >> 12) & UINT64_C(48); - Value |= (insn >> 3) & UINT64_C(15); - MI.addOperand(MCOperand::createImm(Value)); - // op: Nt - Value = (insn >> 8) & UINT64_C(7); - DecodeIntRegsRegisterClass(MI, Value, 0, nullptr); - break; - - case Hexagon::S4_pstorerbf_abs: - case Hexagon::S4_pstorerbt_abs: - case Hexagon::S4_pstorerbfnew_abs: - case Hexagon::S4_pstorerbtnew_abs: - case Hexagon::S4_pstorerhf_abs: - case Hexagon::S4_pstorerht_abs: - case Hexagon::S4_pstorerhfnew_abs: - case Hexagon::S4_pstorerhtnew_abs: - case Hexagon::S4_pstorerif_abs: - case Hexagon::S4_pstorerit_abs: - case Hexagon::S4_pstorerifnew_abs: - case Hexagon::S4_pstoreritnew_abs: - // op: Pv - Value = insn & UINT64_C(3); - DecodePredRegsRegisterClass(MI, Value, 0, nullptr); - // op: u6 - Value = (insn >> 12) & UINT64_C(48); - Value |= (insn >> 3) & UINT64_C(15); - MI.addOperand(MCOperand::createImm(Value)); - // op: Rt - Value = (insn >> 8) & UINT64_C(31); - DecodeIntRegsRegisterClass(MI, Value, 0, nullptr); - break; - - case Hexagon::L4_ploadrdf_abs: - case Hexagon::L4_ploadrdt_abs: - case Hexagon::L4_ploadrdfnew_abs: - case Hexagon::L4_ploadrdtnew_abs: - // op: Rdd - Value = insn & UINT64_C(31); - DecodeDoubleRegsRegisterClass(MI, Value, 0, nullptr); - // op: Pt - Value = ((insn >> 9) & UINT64_C(3)); - DecodePredRegsRegisterClass(MI, Value, 0, nullptr); - // op: u6 - Value = ((insn >> 15) & UINT64_C(62)); - Value |= ((insn >> 8) & UINT64_C(1)); - MI.addOperand(MCOperand::createImm(Value)); - break; - - case Hexagon::L4_ploadrbf_abs: - case Hexagon::L4_ploadrbt_abs: - case Hexagon::L4_ploadrbfnew_abs: - case Hexagon::L4_ploadrbtnew_abs: - case Hexagon::L4_ploadrhf_abs: - case Hexagon::L4_ploadrht_abs: - case Hexagon::L4_ploadrhfnew_abs: - case Hexagon::L4_ploadrhtnew_abs: - case Hexagon::L4_ploadrubf_abs: - case Hexagon::L4_ploadrubt_abs: - case Hexagon::L4_ploadrubfnew_abs: - case Hexagon::L4_ploadrubtnew_abs: - case Hexagon::L4_ploadruhf_abs: - case Hexagon::L4_ploadruht_abs: - case Hexagon::L4_ploadruhfnew_abs: - case Hexagon::L4_ploadruhtnew_abs: - case Hexagon::L4_ploadrif_abs: - case Hexagon::L4_ploadrit_abs: - case Hexagon::L4_ploadrifnew_abs: - case Hexagon::L4_ploadritnew_abs: - // op: Rd - Value = insn & UINT64_C(31); - DecodeIntRegsRegisterClass(MI, Value, 0, nullptr); - // op: Pt - Value = (insn >> 9) & UINT64_C(3); - DecodePredRegsRegisterClass(MI, Value, 0, nullptr); - // op: u6 - Value = (insn >> 15) & UINT64_C(62); - Value |= (insn >> 8) & UINT64_C(1); - MI.addOperand(MCOperand::createImm(Value)); - break; - - // op: g16_2 - case (Hexagon::PS_loadriabs): - ++shift; - // op: g16_1 - case Hexagon::PS_loadrhabs: - case Hexagon::PS_loadruhabs: - ++shift; - // op: g16_0 - case Hexagon::PS_loadrbabs: - case Hexagon::PS_loadrubabs: - // op: Rd - Value |= insn & UINT64_C(31); - DecodeIntRegsRegisterClass(MI, Value, 0, nullptr); - Value = (insn >> 11) & UINT64_C(49152); - Value |= (insn >> 7) & UINT64_C(15872); - Value |= (insn >> 5) & UINT64_C(511); - MI.addOperand(MCOperand::createImm(Value << shift)); - break; - - case Hexagon::PS_loadrdabs: - Value = insn & UINT64_C(31); - DecodeDoubleRegsRegisterClass(MI, Value, 0, nullptr); - Value = (insn >> 11) & UINT64_C(49152); - Value |= (insn >> 7) & UINT64_C(15872); - Value |= (insn >> 5) & UINT64_C(511); - MI.addOperand(MCOperand::createImm(Value << 3)); - break; - - case Hexagon::PS_storerdabs: - // op: g16_3 - Value = (insn >> 11) & UINT64_C(49152); - Value |= (insn >> 7) & UINT64_C(15872); - Value |= (insn >> 5) & UINT64_C(256); - Value |= insn & UINT64_C(255); - MI.addOperand(MCOperand::createImm(Value << 3)); - // op: Rtt - Value = (insn >> 8) & UINT64_C(31); - DecodeDoubleRegsRegisterClass(MI, Value, 0, nullptr); - break; - - // op: g16_2 - case Hexagon::PS_storerinewabs: - ++shift; - // op: g16_1 - case Hexagon::PS_storerhnewabs: - ++shift; - // op: g16_0 - case Hexagon::PS_storerbnewabs: - Value = (insn >> 11) & UINT64_C(49152); - Value |= (insn >> 7) & UINT64_C(15872); - Value |= (insn >> 5) & UINT64_C(256); - Value |= insn & UINT64_C(255); - MI.addOperand(MCOperand::createImm(Value << shift)); - // op: Nt - Value = (insn >> 8) & UINT64_C(7); - DecodeIntRegsRegisterClass(MI, Value, 0, nullptr); - break; - - // op: g16_2 - case Hexagon::PS_storeriabs: - ++shift; - // op: g16_1 - case Hexagon::PS_storerhabs: - case Hexagon::PS_storerfabs: - ++shift; - // op: g16_0 - case Hexagon::PS_storerbabs: - Value = (insn >> 11) & UINT64_C(49152); - Value |= (insn >> 7) & UINT64_C(15872); - Value |= (insn >> 5) & UINT64_C(256); - Value |= insn & UINT64_C(255); - MI.addOperand(MCOperand::createImm(Value << shift)); - // op: Rt - Value = (insn >> 8) & UINT64_C(31); - DecodeIntRegsRegisterClass(MI, Value, 0, nullptr); - break; - } - return MCDisassembler::Success; - } - return MCDisassembler::Fail; -} - -static DecodeStatus decodeImmext(MCInst &MI, uint32_t insn, - void const *Decoder) { - // Instruction Class for a constant a extender: bits 31:28 = 0x0000 - if ((~insn & 0xf0000000) == 0xf0000000) { - unsigned Value; - // 27:16 High 12 bits of 26-bit extender. - Value = (insn & 0x0fff0000) << 4; - // 13:0 Low 14 bits of 26-bit extender. - Value |= ((insn & 0x3fff) << 6); - MI.setOpcode(Hexagon::A4_ext); - HexagonMCInstrInfo::addConstant(MI, Value, contextFromDecoder(Decoder)); - return MCDisassembler::Success; - } - return MCDisassembler::Fail; -} - -// These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td -enum subInstBinaryValues { - SA1_addi_BITS = 0x0000, - SA1_addi_MASK = 0x1800, - SA1_addrx_BITS = 0x1800, - SA1_addrx_MASK = 0x1f00, - SA1_addsp_BITS = 0x0c00, - SA1_addsp_MASK = 0x1c00, - SA1_and1_BITS = 0x1200, - SA1_and1_MASK = 0x1f00, - SA1_clrf_BITS = 0x1a70, - SA1_clrf_MASK = 0x1e70, - SA1_clrfnew_BITS = 0x1a50, - SA1_clrfnew_MASK = 0x1e70, - SA1_clrt_BITS = 0x1a60, - SA1_clrt_MASK = 0x1e70, - SA1_clrtnew_BITS = 0x1a40, - SA1_clrtnew_MASK = 0x1e70, - SA1_cmpeqi_BITS = 0x1900, - SA1_cmpeqi_MASK = 0x1f00, - SA1_combine0i_BITS = 0x1c00, - SA1_combine0i_MASK = 0x1d18, - SA1_combine1i_BITS = 0x1c08, - SA1_combine1i_MASK = 0x1d18, - SA1_combine2i_BITS = 0x1c10, - SA1_combine2i_MASK = 0x1d18, - SA1_combine3i_BITS = 0x1c18, - SA1_combine3i_MASK = 0x1d18, - SA1_combinerz_BITS = 0x1d08, - SA1_combinerz_MASK = 0x1d08, - SA1_combinezr_BITS = 0x1d00, - SA1_combinezr_MASK = 0x1d08, - SA1_dec_BITS = 0x1300, - SA1_dec_MASK = 0x1f00, - SA1_inc_BITS = 0x1100, - SA1_inc_MASK = 0x1f00, - SA1_seti_BITS = 0x0800, - SA1_seti_MASK = 0x1c00, - SA1_setin1_BITS = 0x1a00, - SA1_setin1_MASK = 0x1e40, - SA1_sxtb_BITS = 0x1500, - SA1_sxtb_MASK = 0x1f00, - SA1_sxth_BITS = 0x1400, - SA1_sxth_MASK = 0x1f00, - SA1_tfr_BITS = 0x1000, - SA1_tfr_MASK = 0x1f00, - SA1_zxtb_BITS = 0x1700, - SA1_zxtb_MASK = 0x1f00, - SA1_zxth_BITS = 0x1600, - SA1_zxth_MASK = 0x1f00, - SL1_loadri_io_BITS = 0x0000, - SL1_loadri_io_MASK = 0x1000, - SL1_loadrub_io_BITS = 0x1000, - SL1_loadrub_io_MASK = 0x1000, - SL2_deallocframe_BITS = 0x1f00, - SL2_deallocframe_MASK = 0x1fc0, - SL2_jumpr31_BITS = 0x1fc0, - SL2_jumpr31_MASK = 0x1fc4, - SL2_jumpr31_f_BITS = 0x1fc5, - SL2_jumpr31_f_MASK = 0x1fc7, - SL2_jumpr31_fnew_BITS = 0x1fc7, - SL2_jumpr31_fnew_MASK = 0x1fc7, - SL2_jumpr31_t_BITS = 0x1fc4, - SL2_jumpr31_t_MASK = 0x1fc7, - SL2_jumpr31_tnew_BITS = 0x1fc6, - SL2_jumpr31_tnew_MASK = 0x1fc7, - SL2_loadrb_io_BITS = 0x1000, - SL2_loadrb_io_MASK = 0x1800, - SL2_loadrd_sp_BITS = 0x1e00, - SL2_loadrd_sp_MASK = 0x1f00, - SL2_loadrh_io_BITS = 0x0000, - SL2_loadrh_io_MASK = 0x1800, - SL2_loadri_sp_BITS = 0x1c00, - SL2_loadri_sp_MASK = 0x1e00, - SL2_loadruh_io_BITS = 0x0800, - SL2_loadruh_io_MASK = 0x1800, - SL2_return_BITS = 0x1f40, - SL2_return_MASK = 0x1fc4, - SL2_return_f_BITS = 0x1f45, - SL2_return_f_MASK = 0x1fc7, - SL2_return_fnew_BITS = 0x1f47, - SL2_return_fnew_MASK = 0x1fc7, - SL2_return_t_BITS = 0x1f44, - SL2_return_t_MASK = 0x1fc7, - SL2_return_tnew_BITS = 0x1f46, - SL2_return_tnew_MASK = 0x1fc7, - SS1_storeb_io_BITS = 0x1000, - SS1_storeb_io_MASK = 0x1000, - SS1_storew_io_BITS = 0x0000, - SS1_storew_io_MASK = 0x1000, - SS2_allocframe_BITS = 0x1c00, - SS2_allocframe_MASK = 0x1e00, - SS2_storebi0_BITS = 0x1200, - SS2_storebi0_MASK = 0x1f00, - SS2_storebi1_BITS = 0x1300, - SS2_storebi1_MASK = 0x1f00, - SS2_stored_sp_BITS = 0x0a00, - SS2_stored_sp_MASK = 0x1e00, - SS2_storeh_io_BITS = 0x0000, - SS2_storeh_io_MASK = 0x1800, - SS2_storew_sp_BITS = 0x0800, - SS2_storew_sp_MASK = 0x1e00, - SS2_storewi0_BITS = 0x1000, - SS2_storewi0_MASK = 0x1f00, - SS2_storewi1_BITS = 0x1100, - SS2_storewi1_MASK = 0x1f00 -}; -static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op, - raw_ostream &os) { - switch (IClass) { - case HexagonII::HSIG_L1: - if ((inst & SL1_loadri_io_MASK) == SL1_loadri_io_BITS) - op = Hexagon::SL1_loadri_io; - else if ((inst & SL1_loadrub_io_MASK) == SL1_loadrub_io_BITS) - op = Hexagon::SL1_loadrub_io; - else { - os << "<unknown subinstruction>"; - return MCDisassembler::Fail; - } - break; - case HexagonII::HSIG_L2: - if ((inst & SL2_deallocframe_MASK) == SL2_deallocframe_BITS) - op = Hexagon::SL2_deallocframe; - else if ((inst & SL2_jumpr31_MASK) == SL2_jumpr31_BITS) - op = Hexagon::SL2_jumpr31; - else if ((inst & SL2_jumpr31_f_MASK) == SL2_jumpr31_f_BITS) - op = Hexagon::SL2_jumpr31_f; - else if ((inst & SL2_jumpr31_fnew_MASK) == SL2_jumpr31_fnew_BITS) - op = Hexagon::SL2_jumpr31_fnew; - else if ((inst & SL2_jumpr31_t_MASK) == SL2_jumpr31_t_BITS) - op = Hexagon::SL2_jumpr31_t; - else if ((inst & SL2_jumpr31_tnew_MASK) == SL2_jumpr31_tnew_BITS) - op = Hexagon::SL2_jumpr31_tnew; - else if ((inst & SL2_loadrb_io_MASK) == SL2_loadrb_io_BITS) - op = Hexagon::SL2_loadrb_io; - else if ((inst & SL2_loadrd_sp_MASK) == SL2_loadrd_sp_BITS) - op = Hexagon::SL2_loadrd_sp; - else if ((inst & SL2_loadrh_io_MASK) == SL2_loadrh_io_BITS) - op = Hexagon::SL2_loadrh_io; - else if ((inst & SL2_loadri_sp_MASK) == SL2_loadri_sp_BITS) - op = Hexagon::SL2_loadri_sp; - else if ((inst & SL2_loadruh_io_MASK) == SL2_loadruh_io_BITS) - op = Hexagon::SL2_loadruh_io; - else if ((inst & SL2_return_MASK) == SL2_return_BITS) - op = Hexagon::SL2_return; - else if ((inst & SL2_return_f_MASK) == SL2_return_f_BITS) - op = Hexagon::SL2_return_f; - else if ((inst & SL2_return_fnew_MASK) == SL2_return_fnew_BITS) - op = Hexagon::SL2_return_fnew; - else if ((inst & SL2_return_t_MASK) == SL2_return_t_BITS) - op = Hexagon::SL2_return_t; - else if ((inst & SL2_return_tnew_MASK) == SL2_return_tnew_BITS) - op = Hexagon::SL2_return_tnew; - else { - os << "<unknown subinstruction>"; - return MCDisassembler::Fail; - } - break; - case HexagonII::HSIG_A: - if ((inst & SA1_addi_MASK) == SA1_addi_BITS) - op = Hexagon::SA1_addi; - else if ((inst & SA1_addrx_MASK) == SA1_addrx_BITS) - op = Hexagon::SA1_addrx; - else if ((inst & SA1_addsp_MASK) == SA1_addsp_BITS) - op = Hexagon::SA1_addsp; - else if ((inst & SA1_and1_MASK) == SA1_and1_BITS) - op = Hexagon::SA1_and1; - else if ((inst & SA1_clrf_MASK) == SA1_clrf_BITS) - op = Hexagon::SA1_clrf; - else if ((inst & SA1_clrfnew_MASK) == SA1_clrfnew_BITS) - op = Hexagon::SA1_clrfnew; - else if ((inst & SA1_clrt_MASK) == SA1_clrt_BITS) - op = Hexagon::SA1_clrt; - else if ((inst & SA1_clrtnew_MASK) == SA1_clrtnew_BITS) - op = Hexagon::SA1_clrtnew; - else if ((inst & SA1_cmpeqi_MASK) == SA1_cmpeqi_BITS) - op = Hexagon::SA1_cmpeqi; - else if ((inst & SA1_combine0i_MASK) == SA1_combine0i_BITS) - op = Hexagon::SA1_combine0i; - else if ((inst & SA1_combine1i_MASK) == SA1_combine1i_BITS) - op = Hexagon::SA1_combine1i; - else if ((inst & SA1_combine2i_MASK) == SA1_combine2i_BITS) - op = Hexagon::SA1_combine2i; - else if ((inst & SA1_combine3i_MASK) == SA1_combine3i_BITS) - op = Hexagon::SA1_combine3i; - else if ((inst & SA1_combinerz_MASK) == SA1_combinerz_BITS) - op = Hexagon::SA1_combinerz; - else if ((inst & SA1_combinezr_MASK) == SA1_combinezr_BITS) - op = Hexagon::SA1_combinezr; - else if ((inst & SA1_dec_MASK) == SA1_dec_BITS) - op = Hexagon::SA1_dec; - else if ((inst & SA1_inc_MASK) == SA1_inc_BITS) - op = Hexagon::SA1_inc; - else if ((inst & SA1_seti_MASK) == SA1_seti_BITS) - op = Hexagon::SA1_seti; - else if ((inst & SA1_setin1_MASK) == SA1_setin1_BITS) - op = Hexagon::SA1_setin1; - else if ((inst & SA1_sxtb_MASK) == SA1_sxtb_BITS) - op = Hexagon::SA1_sxtb; - else if ((inst & SA1_sxth_MASK) == SA1_sxth_BITS) - op = Hexagon::SA1_sxth; - else if ((inst & SA1_tfr_MASK) == SA1_tfr_BITS) - op = Hexagon::SA1_tfr; - else if ((inst & SA1_zxtb_MASK) == SA1_zxtb_BITS) - op = Hexagon::SA1_zxtb; - else if ((inst & SA1_zxth_MASK) == SA1_zxth_BITS) - op = Hexagon::SA1_zxth; - else { - os << "<unknown subinstruction>"; - return MCDisassembler::Fail; - } - break; - case HexagonII::HSIG_S1: - if ((inst & SS1_storeb_io_MASK) == SS1_storeb_io_BITS) - op = Hexagon::SS1_storeb_io; - else if ((inst & SS1_storew_io_MASK) == SS1_storew_io_BITS) - op = Hexagon::SS1_storew_io; - else { - os << "<unknown subinstruction>"; - return MCDisassembler::Fail; - } - break; - case HexagonII::HSIG_S2: - if ((inst & SS2_allocframe_MASK) == SS2_allocframe_BITS) - op = Hexagon::SS2_allocframe; - else if ((inst & SS2_storebi0_MASK) == SS2_storebi0_BITS) - op = Hexagon::SS2_storebi0; - else if ((inst & SS2_storebi1_MASK) == SS2_storebi1_BITS) - op = Hexagon::SS2_storebi1; - else if ((inst & SS2_stored_sp_MASK) == SS2_stored_sp_BITS) - op = Hexagon::SS2_stored_sp; - else if ((inst & SS2_storeh_io_MASK) == SS2_storeh_io_BITS) - op = Hexagon::SS2_storeh_io; - else if ((inst & SS2_storew_sp_MASK) == SS2_storew_sp_BITS) - op = Hexagon::SS2_storew_sp; - else if ((inst & SS2_storewi0_MASK) == SS2_storewi0_BITS) - op = Hexagon::SS2_storewi0; - else if ((inst & SS2_storewi1_MASK) == SS2_storewi1_BITS) - op = Hexagon::SS2_storewi1; - else { - os << "<unknown subinstruction>"; - return MCDisassembler::Fail; - } - break; - default: - os << "<unknown>"; - return MCDisassembler::Fail; - } - return MCDisassembler::Success; -} - -static unsigned getRegFromSubinstEncoding(unsigned encoded_reg) { - if (encoded_reg < 8) - return Hexagon::R0 + encoded_reg; - else if (encoded_reg < 16) - return Hexagon::R0 + encoded_reg + 8; - - // patently false value - return Hexagon::NoRegister; -} - -static unsigned getDRegFromSubinstEncoding(unsigned encoded_dreg) { - if (encoded_dreg < 4) - return Hexagon::D0 + encoded_dreg; - else if (encoded_dreg < 8) - return Hexagon::D0 + encoded_dreg + 4; - - // patently false value - return Hexagon::NoRegister; -} - -void HexagonDisassembler::addSubinstOperands(MCInst *MI, unsigned opcode, - unsigned inst) const { - int64_t operand; - MCOperand Op; - switch (opcode) { - case Hexagon::SL2_deallocframe: - case Hexagon::SL2_jumpr31: - case Hexagon::SL2_jumpr31_f: - case Hexagon::SL2_jumpr31_fnew: - case Hexagon::SL2_jumpr31_t: - case Hexagon::SL2_jumpr31_tnew: - case Hexagon::SL2_return: - case Hexagon::SL2_return_f: - case Hexagon::SL2_return_fnew: - case Hexagon::SL2_return_t: - case Hexagon::SL2_return_tnew: - // no operands for these instructions - break; - case Hexagon::SS2_allocframe: - // u 8-4{5_3} - operand = ((inst & 0x1f0) >> 4) << 3; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SL1_loadri_io: - // Rd 3-0, Rs 7-4, u 11-8{4_2} - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0xf00) >> 6; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SL1_loadrub_io: - // Rd 3-0, Rs 7-4, u 11-8 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0xf00) >> 8; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SL2_loadrb_io: - // Rd 3-0, Rs 7-4, u 10-8 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0x700) >> 8; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SL2_loadrh_io: - case Hexagon::SL2_loadruh_io: - // Rd 3-0, Rs 7-4, u 10-8{3_1} - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = ((inst & 0x700) >> 8) << 1; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SL2_loadrd_sp: - // Rdd 2-0, u 7-3{5_3} - operand = getDRegFromSubinstEncoding(inst & 0x7); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = ((inst & 0x0f8) >> 3) << 3; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SL2_loadri_sp: - // Rd 3-0, u 8-4{5_2} - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = ((inst & 0x1f0) >> 4) << 2; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SA1_addi: - // Rx 3-0 (x2), s7 10-4 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - MI->addOperand(Op); - operand = SignExtend64<7>((inst & 0x7f0) >> 4); - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SA1_addrx: - // Rx 3-0 (x2), Rs 7-4 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - case Hexagon::SA1_and1: - case Hexagon::SA1_dec: - case Hexagon::SA1_inc: - case Hexagon::SA1_sxtb: - case Hexagon::SA1_sxth: - case Hexagon::SA1_tfr: - case Hexagon::SA1_zxtb: - case Hexagon::SA1_zxth: - // Rd 3-0, Rs 7-4 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - case Hexagon::SA1_addsp: - // Rd 3-0, u 9-4{6_2} - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = ((inst & 0x3f0) >> 4) << 2; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SA1_seti: - // Rd 3-0, u 9-4 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0x3f0) >> 4; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SA1_clrf: - case Hexagon::SA1_clrfnew: - case Hexagon::SA1_clrt: - case Hexagon::SA1_clrtnew: - case Hexagon::SA1_setin1: - // Rd 3-0 - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - if (opcode == Hexagon::SA1_setin1) - break; - MI->addOperand(MCOperand::createReg(Hexagon::P0)); - break; - case Hexagon::SA1_cmpeqi: - // Rs 7-4, u 1-0 - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = inst & 0x3; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SA1_combine0i: - case Hexagon::SA1_combine1i: - case Hexagon::SA1_combine2i: - case Hexagon::SA1_combine3i: - // Rdd 2-0, u 6-5 - operand = getDRegFromSubinstEncoding(inst & 0x7); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0x060) >> 5; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SA1_combinerz: - case Hexagon::SA1_combinezr: - // Rdd 2-0, Rs 7-4 - operand = getDRegFromSubinstEncoding(inst & 0x7); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - case Hexagon::SS1_storeb_io: - // Rs 7-4, u 11-8, Rt 3-0 - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0xf00) >> 8; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - case Hexagon::SS1_storew_io: - // Rs 7-4, u 11-8{4_2}, Rt 3-0 - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = ((inst & 0xf00) >> 8) << 2; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - case Hexagon::SS2_storebi0: - case Hexagon::SS2_storebi1: - // Rs 7-4, u 3-0 - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = inst & 0xf; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SS2_storewi0: - case Hexagon::SS2_storewi1: - // Rs 7-4, u 3-0{4_2} - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = (inst & 0xf) << 2; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - break; - case Hexagon::SS2_stored_sp: - // s 8-3{6_3}, Rtt 2-0 - operand = SignExtend64<9>(((inst & 0x1f8) >> 3) << 3); - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - operand = getDRegFromSubinstEncoding(inst & 0x7); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - case Hexagon::SS2_storeh_io: - // Rs 7-4, u 10-8{3_1}, Rt 3-0 - operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - operand = ((inst & 0x700) >> 8) << 1; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - case Hexagon::SS2_storew_sp: - // u 8-4{5_2}, Rd 3-0 - operand = ((inst & 0x1f0) >> 4) << 2; - HexagonMCInstrInfo::addConstant(*MI, operand, getContext()); - operand = getRegFromSubinstEncoding(inst & 0xf); - Op = MCOperand::createReg(operand); - MI->addOperand(Op); - break; - default: - // don't crash with an invalid subinstruction - // llvm_unreachable("Invalid subinstruction in duplex instruction"); - break; - } -} diff --git a/contrib/llvm/lib/Target/Hexagon/Hexagon.td b/contrib/llvm/lib/Target/Hexagon/Hexagon.td index 0b2b46387b6a..4767165141a3 100644 --- a/contrib/llvm/lib/Target/Hexagon/Hexagon.td +++ b/contrib/llvm/lib/Target/Hexagon/Hexagon.td @@ -22,14 +22,12 @@ include "llvm/Target/Target.td" //===----------------------------------------------------------------------===// // Hexagon Architectures -def ArchV4: SubtargetFeature<"v4", "HexagonArchVersion", "V4", "Hexagon V4">; -def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "V5", "Hexagon V5">; -def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "V55", "Hexagon V55">; -def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "V60", "Hexagon V60">; +include "HexagonDepArch.td" -def FeatureHVX: SubtargetFeature<"hvx", "UseHVXOps", "true", +// Hexagon ISA Extensions +def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps", "true", "Hexagon HVX instructions">; -def FeatureHVXDbl: SubtargetFeature<"hvx-double", "UseHVXDblOps", "true", +def ExtensionHVXDbl: SubtargetFeature<"hvx-double", "UseHVXDblOps", "true", "Hexagon HVX Double instructions">; def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true", "Use constant-extended calls">; @@ -37,19 +35,14 @@ def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true", //===----------------------------------------------------------------------===// // Hexagon Instruction Predicate Definitions. //===----------------------------------------------------------------------===// -def HasV5T : Predicate<"HST->hasV5TOps()">; -def NoV5T : Predicate<"!HST->hasV5TOps()">; -def HasV55T : Predicate<"HST->hasV55TOps()">, - AssemblerPredicate<"ArchV55">; -def HasV60T : Predicate<"HST->hasV60TOps()">, - AssemblerPredicate<"ArchV60">; + def UseMEMOP : Predicate<"HST->useMemOps()">; def IEEERndNearV5T : Predicate<"HST->modeIEEERndNear()">; def UseHVXDbl : Predicate<"HST->useHVXDblOps()">, - AssemblerPredicate<"FeatureHVXDbl">; + AssemblerPredicate<"ExtensionHVXDbl">; def UseHVXSgl : Predicate<"HST->useHVXSglOps()">; def UseHVX : Predicate<"HST->useHVXSglOps() ||HST->useHVXDblOps()">, - AssemblerPredicate<"FeatureHVX">; + AssemblerPredicate<"ExtensionHVX">; //===----------------------------------------------------------------------===// // Classes used for relation maps. @@ -81,7 +74,7 @@ class IntrinsicsRel; def getPredOpcode : InstrMapping { let FilterClass = "PredRel"; // Instructions with the same BaseOpcode and isNVStore values form a row. - let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isNT"]; + let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"]; // Instructions with the same predicate sense form a column. let ColFields = ["PredSense"]; // The key column is the unpredicated instructions. @@ -132,7 +125,7 @@ def getPredNewOpcode : InstrMapping { // def getPredOldOpcode : InstrMapping { let FilterClass = "PredNewRel"; - let RowFields = ["BaseOpcode", "PredSense", "isNVStore"]; + let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"]; let ColFields = ["PNewValue"]; let KeyCol = ["new"]; let ValueCols = [[""]]; @@ -248,11 +241,18 @@ def getRealHWInstr : InstrMapping { //===----------------------------------------------------------------------===// include "HexagonSchedule.td" include "HexagonRegisterInfo.td" -include "HexagonCallingConv.td" -include "HexagonInstrInfo.td" +include "HexagonOperands.td" +include "HexagonDepOperands.td" +include "HexagonDepITypes.td" +include "HexagonInstrFormats.td" +include "HexagonDepInstrFormats.td" +include "HexagonDepInstrInfo.td" +include "HexagonPseudo.td" include "HexagonPatterns.td" +include "HexagonDepMappings.td" include "HexagonIntrinsics.td" include "HexagonIntrinsicsDerived.td" +include "HexagonMapAsm2IntrinV62.gen.td" def HexagonInstrInfo : InstrInfo; @@ -271,7 +271,9 @@ def : Proc<"hexagonv5", HexagonModelV4, def : Proc<"hexagonv55", HexagonModelV55, [ArchV4, ArchV5, ArchV55]>; def : Proc<"hexagonv60", HexagonModelV60, - [ArchV4, ArchV5, ArchV55, ArchV60, FeatureHVX]>; + [ArchV4, ArchV5, ArchV55, ArchV60, ExtensionHVX]>; +def : Proc<"hexagonv62", HexagonModelV62, + [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, ExtensionHVX]>; //===----------------------------------------------------------------------===// // Declare the target which we are implementing diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp index 54db5ad4374b..fda23f8f6b05 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -261,10 +261,34 @@ static MCSymbol *smallData(AsmPrinter &AP, const MachineInstr &MI, return Sym; } +static MCInst ScaleVectorOffset(MCInst &Inst, unsigned OpNo, + unsigned VectorSize, MCContext &Ctx) { + MCInst T; + T.setOpcode(Inst.getOpcode()); + for (unsigned i = 0, n = Inst.getNumOperands(); i != n; ++i) { + if (i != OpNo) { + T.addOperand(Inst.getOperand(i)); + continue; + } + MCOperand &ImmOp = Inst.getOperand(i); + const auto *HE = static_cast<const HexagonMCExpr*>(ImmOp.getExpr()); + int32_t V = cast<MCConstantExpr>(HE->getExpr())->getValue(); + auto *NewCE = MCConstantExpr::create(V / int32_t(VectorSize), Ctx); + auto *NewHE = HexagonMCExpr::create(NewCE, Ctx); + T.addOperand(MCOperand::createExpr(NewHE)); + } + return T; +} + void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, const MachineInstr &MI) { MCInst &MappedInst = static_cast <MCInst &>(Inst); const MCRegisterInfo *RI = OutStreamer->getContext().getRegisterInfo(); + const MachineFunction &MF = *MI.getParent()->getParent(); + const auto &HST = MF.getSubtarget<HexagonSubtarget>(); + unsigned VectorSize = HST.useHVXSglOps() + ? Hexagon::VectorRegsRegClass.getSize() + : Hexagon::VectorRegs128BRegClass.getSize(); switch (Inst.getOpcode()) { default: return; @@ -282,6 +306,36 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, break; } + case Hexagon::A2_tfrf: { + Inst.setOpcode(Hexagon::A2_paddif); + Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext))); + break; + } + + case Hexagon::A2_tfrt: { + Inst.setOpcode(Hexagon::A2_paddit); + Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext))); + break; + } + + case Hexagon::A2_tfrfnew: { + Inst.setOpcode(Hexagon::A2_paddifnew); + Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext))); + break; + } + + case Hexagon::A2_tfrtnew: { + Inst.setOpcode(Hexagon::A2_padditnew); + Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext))); + break; + } + + case Hexagon::A2_zxtb: { + Inst.setOpcode(Hexagon::A2_andir); + Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(255, OutContext))); + break; + } + // "$dst = CONST64(#$src1)", case Hexagon::CONST64: if (!OutStreamer->hasRawTextSupport()) { @@ -376,6 +430,9 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI)); return; } + case Hexagon::PS_call_nr: + Inst.setOpcode(Hexagon::J2_call); + break; case Hexagon::S5_asrhub_rnd_sat_goodsyntax: { MCOperand &MO = MappedInst.getOperand(2); int64_t Imm; @@ -564,6 +621,181 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst, return; } + case Hexagon::V6_vL32Ub_pi: + case Hexagon::V6_vL32b_cur_pi: + case Hexagon::V6_vL32b_nt_cur_pi: + case Hexagon::V6_vL32b_pi: + case Hexagon::V6_vL32b_nt_pi: + case Hexagon::V6_vL32b_nt_tmp_pi: + case Hexagon::V6_vL32b_tmp_pi: + case Hexagon::V6_vL32Ub_pi_128B: + case Hexagon::V6_vL32b_cur_pi_128B: + case Hexagon::V6_vL32b_nt_cur_pi_128B: + case Hexagon::V6_vL32b_pi_128B: + case Hexagon::V6_vL32b_nt_pi_128B: + case Hexagon::V6_vL32b_nt_tmp_pi_128B: + case Hexagon::V6_vL32b_tmp_pi_128B: + MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext); + return; + + case Hexagon::V6_vL32Ub_ai: + case Hexagon::V6_vL32b_ai: + case Hexagon::V6_vL32b_cur_ai: + case Hexagon::V6_vL32b_nt_ai: + case Hexagon::V6_vL32b_nt_cur_ai: + case Hexagon::V6_vL32b_nt_tmp_ai: + case Hexagon::V6_vL32b_tmp_ai: + case Hexagon::V6_vL32Ub_ai_128B: + case Hexagon::V6_vL32b_ai_128B: + case Hexagon::V6_vL32b_cur_ai_128B: + case Hexagon::V6_vL32b_nt_ai_128B: + case Hexagon::V6_vL32b_nt_cur_ai_128B: + case Hexagon::V6_vL32b_nt_tmp_ai_128B: + case Hexagon::V6_vL32b_tmp_ai_128B: + MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext); + return; + + case Hexagon::V6_vS32Ub_pi: + case Hexagon::V6_vS32b_new_pi: + case Hexagon::V6_vS32b_nt_new_pi: + case Hexagon::V6_vS32b_nt_pi: + case Hexagon::V6_vS32b_pi: + case Hexagon::V6_vS32Ub_pi_128B: + case Hexagon::V6_vS32b_new_pi_128B: + case Hexagon::V6_vS32b_nt_new_pi_128B: + case Hexagon::V6_vS32b_nt_pi_128B: + case Hexagon::V6_vS32b_pi_128B: + MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext); + return; + + case Hexagon::V6_vS32Ub_ai: + case Hexagon::V6_vS32b_ai: + case Hexagon::V6_vS32b_new_ai: + case Hexagon::V6_vS32b_nt_ai: + case Hexagon::V6_vS32b_nt_new_ai: + case Hexagon::V6_vS32Ub_ai_128B: + case Hexagon::V6_vS32b_ai_128B: + case Hexagon::V6_vS32b_new_ai_128B: + case Hexagon::V6_vS32b_nt_ai_128B: + case Hexagon::V6_vS32b_nt_new_ai_128B: + MappedInst = ScaleVectorOffset(Inst, 1, VectorSize, OutContext); + return; + + case Hexagon::V6_vL32b_cur_npred_pi: + case Hexagon::V6_vL32b_cur_pred_pi: + case Hexagon::V6_vL32b_npred_pi: + case Hexagon::V6_vL32b_nt_cur_npred_pi: + case Hexagon::V6_vL32b_nt_cur_pred_pi: + case Hexagon::V6_vL32b_nt_npred_pi: + case Hexagon::V6_vL32b_nt_pred_pi: + case Hexagon::V6_vL32b_nt_tmp_npred_pi: + case Hexagon::V6_vL32b_nt_tmp_pred_pi: + case Hexagon::V6_vL32b_pred_pi: + case Hexagon::V6_vL32b_tmp_npred_pi: + case Hexagon::V6_vL32b_tmp_pred_pi: + case Hexagon::V6_vL32b_cur_npred_pi_128B: + case Hexagon::V6_vL32b_cur_pred_pi_128B: + case Hexagon::V6_vL32b_npred_pi_128B: + case Hexagon::V6_vL32b_nt_cur_npred_pi_128B: + case Hexagon::V6_vL32b_nt_cur_pred_pi_128B: + case Hexagon::V6_vL32b_nt_npred_pi_128B: + case Hexagon::V6_vL32b_nt_pred_pi_128B: + case Hexagon::V6_vL32b_nt_tmp_npred_pi_128B: + case Hexagon::V6_vL32b_nt_tmp_pred_pi_128B: + case Hexagon::V6_vL32b_pred_pi_128B: + case Hexagon::V6_vL32b_tmp_npred_pi_128B: + case Hexagon::V6_vL32b_tmp_pred_pi_128B: + MappedInst = ScaleVectorOffset(Inst, 4, VectorSize, OutContext); + return; + + case Hexagon::V6_vL32b_cur_npred_ai: + case Hexagon::V6_vL32b_cur_pred_ai: + case Hexagon::V6_vL32b_npred_ai: + case Hexagon::V6_vL32b_nt_cur_npred_ai: + case Hexagon::V6_vL32b_nt_cur_pred_ai: + case Hexagon::V6_vL32b_nt_npred_ai: + case Hexagon::V6_vL32b_nt_pred_ai: + case Hexagon::V6_vL32b_nt_tmp_npred_ai: + case Hexagon::V6_vL32b_nt_tmp_pred_ai: + case Hexagon::V6_vL32b_pred_ai: + case Hexagon::V6_vL32b_tmp_npred_ai: + case Hexagon::V6_vL32b_tmp_pred_ai: + case Hexagon::V6_vL32b_cur_npred_ai_128B: + case Hexagon::V6_vL32b_cur_pred_ai_128B: + case Hexagon::V6_vL32b_npred_ai_128B: + case Hexagon::V6_vL32b_nt_cur_npred_ai_128B: + case Hexagon::V6_vL32b_nt_cur_pred_ai_128B: + case Hexagon::V6_vL32b_nt_npred_ai_128B: + case Hexagon::V6_vL32b_nt_pred_ai_128B: + case Hexagon::V6_vL32b_nt_tmp_npred_ai_128B: + case Hexagon::V6_vL32b_nt_tmp_pred_ai_128B: + case Hexagon::V6_vL32b_pred_ai_128B: + case Hexagon::V6_vL32b_tmp_npred_ai_128B: + case Hexagon::V6_vL32b_tmp_pred_ai_128B: + MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext); + return; + + case Hexagon::V6_vS32Ub_npred_pi: + case Hexagon::V6_vS32Ub_pred_pi: + case Hexagon::V6_vS32b_new_npred_pi: + case Hexagon::V6_vS32b_new_pred_pi: + case Hexagon::V6_vS32b_npred_pi: + case Hexagon::V6_vS32b_nqpred_pi: + case Hexagon::V6_vS32b_nt_new_npred_pi: + case Hexagon::V6_vS32b_nt_new_pred_pi: + case Hexagon::V6_vS32b_nt_npred_pi: + case Hexagon::V6_vS32b_nt_nqpred_pi: + case Hexagon::V6_vS32b_nt_pred_pi: + case Hexagon::V6_vS32b_nt_qpred_pi: + case Hexagon::V6_vS32b_pred_pi: + case Hexagon::V6_vS32b_qpred_pi: + case Hexagon::V6_vS32Ub_npred_pi_128B: + case Hexagon::V6_vS32Ub_pred_pi_128B: + case Hexagon::V6_vS32b_new_npred_pi_128B: + case Hexagon::V6_vS32b_new_pred_pi_128B: + case Hexagon::V6_vS32b_npred_pi_128B: + case Hexagon::V6_vS32b_nqpred_pi_128B: + case Hexagon::V6_vS32b_nt_new_npred_pi_128B: + case Hexagon::V6_vS32b_nt_new_pred_pi_128B: + case Hexagon::V6_vS32b_nt_npred_pi_128B: + case Hexagon::V6_vS32b_nt_nqpred_pi_128B: + case Hexagon::V6_vS32b_nt_pred_pi_128B: + case Hexagon::V6_vS32b_nt_qpred_pi_128B: + case Hexagon::V6_vS32b_pred_pi_128B: + case Hexagon::V6_vS32b_qpred_pi_128B: + MappedInst = ScaleVectorOffset(Inst, 3, VectorSize, OutContext); + return; + + case Hexagon::V6_vS32Ub_npred_ai: + case Hexagon::V6_vS32Ub_pred_ai: + case Hexagon::V6_vS32b_new_npred_ai: + case Hexagon::V6_vS32b_new_pred_ai: + case Hexagon::V6_vS32b_npred_ai: + case Hexagon::V6_vS32b_nqpred_ai: + case Hexagon::V6_vS32b_nt_new_npred_ai: + case Hexagon::V6_vS32b_nt_new_pred_ai: + case Hexagon::V6_vS32b_nt_npred_ai: + case Hexagon::V6_vS32b_nt_nqpred_ai: + case Hexagon::V6_vS32b_nt_pred_ai: + case Hexagon::V6_vS32b_nt_qpred_ai: + case Hexagon::V6_vS32b_pred_ai: + case Hexagon::V6_vS32b_qpred_ai: + case Hexagon::V6_vS32Ub_npred_ai_128B: + case Hexagon::V6_vS32Ub_pred_ai_128B: + case Hexagon::V6_vS32b_new_npred_ai_128B: + case Hexagon::V6_vS32b_new_pred_ai_128B: + case Hexagon::V6_vS32b_npred_ai_128B: + case Hexagon::V6_vS32b_nqpred_ai_128B: + case Hexagon::V6_vS32b_nt_new_npred_ai_128B: + case Hexagon::V6_vS32b_nt_new_pred_ai_128B: + case Hexagon::V6_vS32b_nt_npred_ai_128B: + case Hexagon::V6_vS32b_nt_nqpred_ai_128B: + case Hexagon::V6_vS32b_nt_pred_ai_128B: + case Hexagon::V6_vS32b_nt_qpred_ai_128B: + case Hexagon::V6_vS32b_pred_ai_128B: + case Hexagon::V6_vS32b_qpred_ai_128B: + MappedInst = ScaleVectorOffset(Inst, 2, VectorSize, OutContext); + return; } } @@ -578,13 +810,9 @@ void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) { if (MI->isBundle()) { const MachineBasicBlock* MBB = MI->getParent(); MachineBasicBlock::const_instr_iterator MII = MI->getIterator(); - unsigned IgnoreCount = 0; for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII) - if (MII->getOpcode() == TargetOpcode::DBG_VALUE || - MII->getOpcode() == TargetOpcode::IMPLICIT_DEF) - ++IgnoreCount; - else + if (!MII->isDebugValue() && !MII->isImplicitDef()) HexagonLowerToMC(MCII, &*MII, MCB, *this); } else diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp index fe7278fde1b1..61f290ca98d7 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -46,6 +46,17 @@ using namespace llvm; static cl::opt<bool> PreserveTiedOps("hexbit-keep-tied", cl::Hidden, cl::init(true), cl::desc("Preserve subregisters in tied operands")); +static cl::opt<bool> GenExtract("hexbit-extract", cl::Hidden, + cl::init(true), cl::desc("Generate extract instructions")); +static cl::opt<bool> GenBitSplit("hexbit-bitsplit", cl::Hidden, + cl::init(true), cl::desc("Generate bitsplit instructions")); + +static cl::opt<unsigned> MaxExtract("hexbit-max-extract", cl::Hidden, + cl::init(UINT_MAX)); +static unsigned CountExtract = 0; +static cl::opt<unsigned> MaxBitSplit("hexbit-max-bitsplit", cl::Hidden, + cl::init(UINT_MAX)); +static unsigned CountBitSplit = 0; namespace llvm { @@ -249,8 +260,6 @@ INITIALIZE_PASS_END(HexagonBitSimplify, "hexbit", bool HexagonBitSimplify::visitBlock(MachineBasicBlock &B, Transformation &T, RegisterSet &AVs) { - MachineDomTreeNode *N = MDT->getNode(&B); - typedef GraphTraits<MachineDomTreeNode*> GTN; bool Changed = false; if (T.TopDown) @@ -262,10 +271,9 @@ bool HexagonBitSimplify::visitBlock(MachineBasicBlock &B, Transformation &T, RegisterSet NewAVs = AVs; NewAVs.insert(Defs); - for (auto I = GTN::child_begin(N), E = GTN::child_end(N); I != E; ++I) { - MachineBasicBlock *SB = (*I)->getBlock(); - Changed |= visitBlock(*SB, T, NewAVs); - } + for (auto *DTN : children<MachineDomTreeNode*>(MDT->getNode(&B))) + Changed |= visitBlock(*(DTN->getBlock()), T, NewAVs); + if (!T.TopDown) Changed |= T.processBlock(B, AVs); @@ -896,6 +904,7 @@ const TargetRegisterClass *HexagonBitSimplify::getFinalVRegClass( *MRI.getTargetRegisterInfo()); auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void { + (void)HRI; assert(Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo) || Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi)); }; @@ -983,9 +992,9 @@ bool DeadCodeElimination::isDead(unsigned R) const { bool DeadCodeElimination::runOnNode(MachineDomTreeNode *N) { bool Changed = false; - typedef GraphTraits<MachineDomTreeNode*> GTN; - for (auto I = GTN::child_begin(N), E = GTN::child_end(N); I != E; ++I) - Changed |= runOnNode(*I); + + for (auto *DTN : children<MachineDomTreeNode*>(N)) + Changed |= runOnNode(DTN); MachineBasicBlock *B = N->getBlock(); std::vector<MachineInstr*> Instrs; @@ -1735,10 +1744,11 @@ namespace { // This is by no means complete class BitSimplification : public Transformation { public: - BitSimplification(BitTracker &bt, const HexagonInstrInfo &hii, - const HexagonRegisterInfo &hri, MachineRegisterInfo &mri, - MachineFunction &mf) - : Transformation(true), HII(hii), HRI(hri), MRI(mri), MF(mf), BT(bt) {} + BitSimplification(BitTracker &bt, const MachineDominatorTree &mdt, + const HexagonInstrInfo &hii, const HexagonRegisterInfo &hri, + MachineRegisterInfo &mri, MachineFunction &mf) + : Transformation(true), MDT(mdt), HII(hii), HRI(hri), MRI(mri), + MF(mf), BT(bt) {} bool processBlock(MachineBasicBlock &B, const RegisterSet &AVs) override; @@ -1765,9 +1775,18 @@ namespace { const BitTracker::RegisterCell &RC); bool genExtractLow(MachineInstr *MI, BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC); + bool genBitSplit(MachineInstr *MI, BitTracker::RegisterRef RD, + const BitTracker::RegisterCell &RC, const RegisterSet &AVs); bool simplifyTstbit(MachineInstr *MI, BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC); + bool simplifyExtractLow(MachineInstr *MI, BitTracker::RegisterRef RD, + const BitTracker::RegisterCell &RC, const RegisterSet &AVs); + + // Cache of created instructions to avoid creating duplicates. + // XXX Currently only used by genBitSplit. + std::vector<MachineInstr*> NewMIs; + const MachineDominatorTree &MDT; const HexagonInstrInfo &HII; const HexagonRegisterInfo &HRI; MachineRegisterInfo &MRI; @@ -2149,6 +2168,146 @@ bool BitSimplification::genExtractLow(MachineInstr *MI, return false; } +bool BitSimplification::genBitSplit(MachineInstr *MI, + BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC, + const RegisterSet &AVs) { + if (!GenBitSplit) + return false; + if (CountBitSplit >= MaxBitSplit) + return false; + + unsigned Opc = MI->getOpcode(); + switch (Opc) { + case Hexagon::A4_bitsplit: + case Hexagon::A4_bitspliti: + return false; + } + + unsigned W = RC.width(); + if (W != 32) + return false; + + auto ctlz = [] (const BitTracker::RegisterCell &C) -> unsigned { + unsigned Z = C.width(); + while (Z > 0 && C[Z-1].is(0)) + --Z; + return C.width() - Z; + }; + + // Count the number of leading zeros in the target RC. + unsigned Z = ctlz(RC); + if (Z == 0 || Z == W) + return false; + + // A simplistic analysis: assume the source register (the one being split) + // is fully unknown, and that all its bits are self-references. + const BitTracker::BitValue &B0 = RC[0]; + if (B0.Type != BitTracker::BitValue::Ref) + return false; + + unsigned SrcR = B0.RefI.Reg; + unsigned SrcSR = 0; + unsigned Pos = B0.RefI.Pos; + + // All the non-zero bits should be consecutive bits from the same register. + for (unsigned i = 1; i < W-Z; ++i) { + const BitTracker::BitValue &V = RC[i]; + if (V.Type != BitTracker::BitValue::Ref) + return false; + if (V.RefI.Reg != SrcR || V.RefI.Pos != Pos+i) + return false; + } + + // Now, find the other bitfield among AVs. + for (unsigned S = AVs.find_first(); S; S = AVs.find_next(S)) { + // The number of leading zeros here should be the number of trailing + // non-zeros in RC. + if (!BT.has(S)) + continue; + const BitTracker::RegisterCell &SC = BT.lookup(S); + if (SC.width() != W || ctlz(SC) != W-Z) + continue; + // The Z lower bits should now match SrcR. + const BitTracker::BitValue &S0 = SC[0]; + if (S0.Type != BitTracker::BitValue::Ref || S0.RefI.Reg != SrcR) + continue; + unsigned P = S0.RefI.Pos; + + if (Pos <= P && (Pos + W-Z) != P) + continue; + if (P < Pos && (P + Z) != Pos) + continue; + // The starting bitfield position must be at a subregister boundary. + if (std::min(P, Pos) != 0 && std::min(P, Pos) != 32) + continue; + + unsigned I; + for (I = 1; I < Z; ++I) { + const BitTracker::BitValue &V = SC[I]; + if (V.Type != BitTracker::BitValue::Ref) + break; + if (V.RefI.Reg != SrcR || V.RefI.Pos != P+I) + break; + } + if (I != Z) + continue; + + // Generate bitsplit where S is defined. + CountBitSplit++; + MachineInstr *DefS = MRI.getVRegDef(S); + assert(DefS != nullptr); + DebugLoc DL = DefS->getDebugLoc(); + MachineBasicBlock &B = *DefS->getParent(); + auto At = DefS->isPHI() ? B.getFirstNonPHI() + : MachineBasicBlock::iterator(DefS); + if (MRI.getRegClass(SrcR)->getID() == Hexagon::DoubleRegsRegClassID) + SrcSR = (std::min(Pos, P) == 32) ? Hexagon::isub_hi : Hexagon::isub_lo; + if (!validateReg({SrcR,SrcSR}, Hexagon::A4_bitspliti, 1)) + continue; + unsigned ImmOp = Pos <= P ? W-Z : Z; + + // Find an existing bitsplit instruction if one already exists. + unsigned NewR = 0; + for (MachineInstr *In : NewMIs) { + if (In->getOpcode() != Hexagon::A4_bitspliti) + continue; + MachineOperand &Op1 = In->getOperand(1); + if (Op1.getReg() != SrcR || Op1.getSubReg() != SrcSR) + continue; + if (In->getOperand(2).getImm() != ImmOp) + continue; + // Check if the target register is available here. + MachineOperand &Op0 = In->getOperand(0); + MachineInstr *DefI = MRI.getVRegDef(Op0.getReg()); + assert(DefI != nullptr); + if (!MDT.dominates(DefI, &*At)) + continue; + + // Found one that can be reused. + assert(Op0.getSubReg() == 0); + NewR = Op0.getReg(); + break; + } + if (!NewR) { + NewR = MRI.createVirtualRegister(&Hexagon::DoubleRegsRegClass); + auto NewBS = BuildMI(B, At, DL, HII.get(Hexagon::A4_bitspliti), NewR) + .addReg(SrcR, 0, SrcSR) + .addImm(ImmOp); + NewMIs.push_back(NewBS); + } + if (Pos <= P) { + HBS::replaceRegWithSub(RD.Reg, NewR, Hexagon::isub_lo, MRI); + HBS::replaceRegWithSub(S, NewR, Hexagon::isub_hi, MRI); + } else { + HBS::replaceRegWithSub(S, NewR, Hexagon::isub_lo, MRI); + HBS::replaceRegWithSub(RD.Reg, NewR, Hexagon::isub_hi, MRI); + } + return true; + } + + return false; +} + // Check for tstbit simplification opportunity, where the bit being checked // can be tracked back to another register. For example: // vreg2 = S2_lsr_i_r vreg1, 5 @@ -2210,6 +2369,201 @@ bool BitSimplification::simplifyTstbit(MachineInstr *MI, return false; } +// Detect whether RD is a bitfield extract (sign- or zero-extended) of +// some register from the AVs set. Create a new corresponding instruction +// at the location of MI. The intent is to recognize situations where +// a sequence of instructions performs an operation that is equivalent to +// an extract operation, such as a shift left followed by a shift right. +bool BitSimplification::simplifyExtractLow(MachineInstr *MI, + BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC, + const RegisterSet &AVs) { + if (!GenExtract) + return false; + if (CountExtract >= MaxExtract) + return false; + CountExtract++; + + unsigned W = RC.width(); + unsigned RW = W; + unsigned Len; + bool Signed; + + // The code is mostly class-independent, except for the part that generates + // the extract instruction, and establishes the source register (in case it + // needs to use a subregister). + const TargetRegisterClass *FRC = HBS::getFinalVRegClass(RD, MRI); + if (FRC != &Hexagon::IntRegsRegClass && FRC != &Hexagon::DoubleRegsRegClass) + return false; + assert(RD.Sub == 0); + + // Observation: + // If the cell has a form of 00..0xx..x with k zeros and n remaining + // bits, this could be an extractu of the n bits, but it could also be + // an extractu of a longer field which happens to have 0s in the top + // bit positions. + // The same logic applies to sign-extended fields. + // + // Do not check for the extended extracts, since it would expand the + // search space quite a bit. The search may be expensive as it is. + + const BitTracker::BitValue &TopV = RC[W-1]; + + // Eliminate candidates that have self-referential bits, since they + // cannot be extracts from other registers. Also, skip registers that + // have compile-time constant values. + bool IsConst = true; + for (unsigned I = 0; I != W; ++I) { + const BitTracker::BitValue &V = RC[I]; + if (V.Type == BitTracker::BitValue::Ref && V.RefI.Reg == RD.Reg) + return false; + IsConst = IsConst && (V.is(0) || V.is(1)); + } + if (IsConst) + return false; + + if (TopV.is(0) || TopV.is(1)) { + bool S = TopV.is(1); + for (--W; W > 0 && RC[W-1].is(S); --W) + ; + Len = W; + Signed = S; + // The sign bit must be a part of the field being extended. + if (Signed) + ++Len; + } else { + // This could still be a sign-extended extract. + assert(TopV.Type == BitTracker::BitValue::Ref); + if (TopV.RefI.Reg == RD.Reg || TopV.RefI.Pos == W-1) + return false; + for (--W; W > 0 && RC[W-1] == TopV; --W) + ; + // The top bits of RC are copies of TopV. One occurrence of TopV will + // be a part of the field. + Len = W + 1; + Signed = true; + } + + // This would be just a copy. It should be handled elsewhere. + if (Len == RW) + return false; + + DEBUG({ + dbgs() << __func__ << " on reg: " << PrintReg(RD.Reg, &HRI, RD.Sub) + << ", MI: " << *MI; + dbgs() << "Cell: " << RC << '\n'; + dbgs() << "Expected bitfield size: " << Len << " bits, " + << (Signed ? "sign" : "zero") << "-extended\n"; + }); + + bool Changed = false; + + for (unsigned R = AVs.find_first(); R != 0; R = AVs.find_next(R)) { + if (!BT.has(R)) + continue; + const BitTracker::RegisterCell &SC = BT.lookup(R); + unsigned SW = SC.width(); + + // The source can be longer than the destination, as long as its size is + // a multiple of the size of the destination. Also, we would need to be + // able to refer to the subregister in the source that would be of the + // same size as the destination, but only check the sizes here. + if (SW < RW || (SW % RW) != 0) + continue; + + // The field can start at any offset in SC as long as it contains Len + // bits and does not cross subregister boundary (if the source register + // is longer than the destination). + unsigned Off = 0; + while (Off <= SW-Len) { + unsigned OE = (Off+Len)/RW; + if (OE != Off/RW) { + // The assumption here is that if the source (R) is longer than the + // destination, then the destination is a sequence of words of + // size RW, and each such word in R can be accessed via a subregister. + // + // If the beginning and the end of the field cross the subregister + // boundary, advance to the next subregister. + Off = OE*RW; + continue; + } + if (HBS::isEqual(RC, 0, SC, Off, Len)) + break; + ++Off; + } + + if (Off > SW-Len) + continue; + + // Found match. + unsigned ExtOpc = 0; + if (Off == 0) { + if (Len == 8) + ExtOpc = Signed ? Hexagon::A2_sxtb : Hexagon::A2_zxtb; + else if (Len == 16) + ExtOpc = Signed ? Hexagon::A2_sxth : Hexagon::A2_zxth; + else if (Len < 10 && !Signed) + ExtOpc = Hexagon::A2_andir; + } + if (ExtOpc == 0) { + ExtOpc = + Signed ? (RW == 32 ? Hexagon::S4_extract : Hexagon::S4_extractp) + : (RW == 32 ? Hexagon::S2_extractu : Hexagon::S2_extractup); + } + unsigned SR = 0; + // This only recognizes isub_lo and isub_hi. + if (RW != SW && RW*2 != SW) + continue; + if (RW != SW) + SR = (Off/RW == 0) ? Hexagon::isub_lo : Hexagon::isub_hi; + Off = Off % RW; + + if (!validateReg({R,SR}, ExtOpc, 1)) + continue; + + // Don't generate the same instruction as the one being optimized. + if (MI->getOpcode() == ExtOpc) { + // All possible ExtOpc's have the source in operand(1). + const MachineOperand &SrcOp = MI->getOperand(1); + if (SrcOp.getReg() == R) + continue; + } + + DebugLoc DL = MI->getDebugLoc(); + MachineBasicBlock &B = *MI->getParent(); + unsigned NewR = MRI.createVirtualRegister(FRC); + auto At = MI->isPHI() ? B.getFirstNonPHI() + : MachineBasicBlock::iterator(MI); + auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR) + .addReg(R, 0, SR); + switch (ExtOpc) { + case Hexagon::A2_sxtb: + case Hexagon::A2_zxtb: + case Hexagon::A2_sxth: + case Hexagon::A2_zxth: + break; + case Hexagon::A2_andir: + MIB.addImm((1u << Len) - 1); + break; + case Hexagon::S4_extract: + case Hexagon::S2_extractu: + case Hexagon::S4_extractp: + case Hexagon::S2_extractup: + MIB.addImm(Len) + .addImm(Off); + break; + default: + llvm_unreachable("Unexpected opcode"); + } + + HBS::replaceReg(RD.Reg, NewR, MRI); + BT.put(BitTracker::RegisterRef(NewR), RC); + Changed = true; + break; + } + + return Changed; +} + bool BitSimplification::processBlock(MachineBasicBlock &B, const RegisterSet &AVs) { if (!BT.reached(&B)) @@ -2247,12 +2601,15 @@ bool BitSimplification::processBlock(MachineBasicBlock &B, if (FRC->getID() == Hexagon::DoubleRegsRegClassID) { bool T = genPackhl(MI, RD, RC); + T = T || simplifyExtractLow(MI, RD, RC, AVB); Changed |= T; continue; } if (FRC->getID() == Hexagon::IntRegsRegClassID) { - bool T = genExtractHalf(MI, RD, RC); + bool T = genBitSplit(MI, RD, RC, AVB); + T = T || simplifyExtractLow(MI, RD, RC, AVB); + T = T || genExtractHalf(MI, RD, RC); T = T || genCombineHalf(MI, RD, RC); T = T || genExtractLow(MI, RD, RC); Changed |= T; @@ -2313,7 +2670,7 @@ bool HexagonBitSimplify::runOnMachineFunction(MachineFunction &MF) { BT.run(); RegisterSet ABS; // Available registers for BS. - BitSimplification BitS(BT, HII, HRI, MRI, MF); + BitSimplification BitS(BT, *MDT, HII, HRI, MRI, MF); Changed |= visitBlock(Entry, BitS, ABS); Changed = DeadCodeElimination(MF, *MDT).run() || Changed; @@ -2599,7 +2956,7 @@ void HexagonLoopRescheduling::moveGroup(InstrGroup &G, MachineBasicBlock &LB, for (unsigned j = 0, m = SI->getNumOperands(); j < m; ++j) { const MachineOperand &Op = SI->getOperand(j); if (!Op.isReg()) { - MIB.addOperand(Op); + MIB.add(Op); continue; } if (!Op.isUse()) diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp index 436f88dcd450..90ccecb6629a 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp @@ -74,7 +74,7 @@ HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri, // Module::AnyPointerSize. if (Width == 0 || Width > 64) break; - AttributeSet Attrs = F.getAttributes(); + AttributeList Attrs = F.getAttributes(); if (Attrs.hasAttribute(AttrIdx, Attribute::ByVal)) continue; InPhysReg = getNextPhysReg(InPhysReg, Width); @@ -272,6 +272,9 @@ bool HexagonEvaluator::evaluate(const MachineInstr &MI, // cases below. uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0; + // Register id of the 0th operand. It can be 0. + unsigned Reg0 = Reg[0].Reg; + switch (Opc) { // Transfer immediate: @@ -792,6 +795,17 @@ bool HexagonEvaluator::evaluate(const MachineInstr &MI, case A2_zxth: return rr0(eZXT(rc(1), 16), Outputs); + // Saturations + + case A2_satb: + return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs); + case A2_sath: + return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs); + case A2_satub: + return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs); + case A2_satuh: + return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs); + // Bit count: case S2_cl0: diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp index adc213c3d438..1640b40c164f 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp @@ -219,8 +219,7 @@ HexagonBlockRanges::HexagonBlockRanges(MachineFunction &mf) TII(*HST.getInstrInfo()), TRI(*HST.getRegisterInfo()), Reserved(TRI.getReservedRegs(mf)) { // Consider all non-allocatable registers as reserved. - for (auto I = TRI.regclass_begin(), E = TRI.regclass_end(); I != E; ++I) { - auto *RC = *I; + for (const TargetRegisterClass *RC : TRI.regclasses()) { if (RC->isAllocatable()) continue; for (unsigned R : *RC) @@ -233,14 +232,16 @@ HexagonBlockRanges::RegisterSet HexagonBlockRanges::getLiveIns( const TargetRegisterInfo &TRI) { RegisterSet LiveIns; RegisterSet Tmp; + for (auto I : B.liveins()) { - if (I.LaneMask.all()) { - Tmp.insert({I.PhysReg,0}); + MCSubRegIndexIterator S(I.PhysReg, &TRI); + if (I.LaneMask.all() || (I.LaneMask.any() && !S.isValid())) { + Tmp.insert({I.PhysReg, 0}); continue; } - for (MCSubRegIndexIterator S(I.PhysReg, &TRI); S.isValid(); ++S) { - LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex()); - if ((M & I.LaneMask).any()) + for (; S.isValid(); ++S) { + unsigned SI = S.getSubRegIndex(); + if ((I.LaneMask & TRI.getSubRegIndexLaneMask(SI)).any()) Tmp.insert({S.getSubReg(), 0}); } } @@ -307,6 +308,8 @@ void HexagonBlockRanges::computeInitialLiveRanges(InstrIndexMap &IndexMap, LastUse[R] = LastDef[R] = IndexType::None; }; + RegisterSet Defs, Clobbers; + for (auto &In : B) { if (In.isDebugValue()) continue; @@ -325,19 +328,67 @@ void HexagonBlockRanges::computeInitialLiveRanges(InstrIndexMap &IndexMap, closeRange(S); } } - // Process defs. + // Process defs and clobbers. + Defs.clear(); + Clobbers.clear(); for (auto &Op : In.operands()) { if (!Op.isReg() || !Op.isDef() || Op.isUndef()) continue; RegisterRef R = { Op.getReg(), Op.getSubReg() }; - if (TargetRegisterInfo::isPhysicalRegister(R.Reg) && Reserved[R.Reg]) - continue; for (auto S : expandToSubRegs(R, MRI, TRI)) { - if (LastDef[S] != IndexType::None || LastUse[S] != IndexType::None) - closeRange(S); - LastDef[S] = Index; + if (TargetRegisterInfo::isPhysicalRegister(S.Reg) && Reserved[S.Reg]) + continue; + if (Op.isDead()) + Clobbers.insert(S); + else + Defs.insert(S); + } + } + + for (auto &Op : In.operands()) { + if (!Op.isRegMask()) + continue; + const uint32_t *BM = Op.getRegMask(); + for (unsigned PR = 1, N = TRI.getNumRegs(); PR != N; ++PR) { + // Skip registers that have subregisters. A register is preserved + // iff its bit is set in the regmask, so if R1:0 was preserved, both + // R1 and R0 would also be present. + if (MCSubRegIterator(PR, &TRI, false).isValid()) + continue; + if (Reserved[PR]) + continue; + if (BM[PR/32] & (1u << (PR%32))) + continue; + RegisterRef R = { PR, 0 }; + if (!Defs.count(R)) + Clobbers.insert(R); } } + // Defs and clobbers can overlap, e.g. + // %D0<def,dead> = COPY %vreg5, %R0<imp-def>, %R1<imp-def> + for (RegisterRef R : Defs) + Clobbers.erase(R); + + // Update maps for defs. + for (RegisterRef S : Defs) { + // Defs should already be expanded into subregs. + assert(!TargetRegisterInfo::isPhysicalRegister(S.Reg) || + !MCSubRegIterator(S.Reg, &TRI, false).isValid()); + if (LastDef[S] != IndexType::None || LastUse[S] != IndexType::None) + closeRange(S); + LastDef[S] = Index; + } + // Update maps for clobbers. + for (RegisterRef S : Clobbers) { + // Clobbers should already be expanded into subregs. + assert(!TargetRegisterInfo::isPhysicalRegister(S.Reg) || + !MCSubRegIterator(S.Reg, &TRI, false).isValid()); + if (LastDef[S] != IndexType::None || LastUse[S] != IndexType::None) + closeRange(S); + // Create a single-instruction range. + LastDef[S] = LastUse[S] = Index; + closeRange(S); + } } // Collect live-on-exit. diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonCallingConv.td b/contrib/llvm/lib/Target/Hexagon/HexagonCallingConv.td deleted file mode 100644 index e61b2a7a58ac..000000000000 --- a/contrib/llvm/lib/Target/Hexagon/HexagonCallingConv.td +++ /dev/null @@ -1,35 +0,0 @@ -//===- HexagonCallingConv.td - Calling Conventions Hexagon -*- tablegen -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This describes the calling conventions for the Hexagon architectures. -// -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// Return Value Calling Conventions -//===----------------------------------------------------------------------===// - -// Hexagon 32-bit C return-value convention. -def RetCC_Hexagon32 : CallingConv<[ - CCIfType<[i32, f32], CCAssignToReg<[R0, R1, R2, R3, R4, R5]>>, - CCIfType<[i64, f64], CCAssignToReg<[D0, D1, D2]>>, - - // Alternatively, they are assigned to the stack in 4-byte aligned units. - CCAssignToStack<4, 4> -]>; - -// Hexagon 32-bit C Calling convention. -def CC_Hexagon32 : CallingConv<[ - // All arguments get passed in integer registers if there is space. - CCIfType<[f32, i32, i16, i8], CCAssignToReg<[R0, R1, R2, R3, R4, R5]>>, - CCIfType<[f64, i64], CCAssignToReg<[D0, D1, D2]>>, - - // Alternatively, they are assigned to the stack in 4-byte aligned units. - CCAssignToStack<4, 4> -]>; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp index 489da6be923d..a07ba77e6f3e 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp @@ -315,11 +315,8 @@ void HexagonCommonGEP::getBlockTraversalOrder(BasicBlock *Root, // visited". Order.push_back(Root); - DomTreeNode *DTN = DT->getNode(Root); - typedef GraphTraits<DomTreeNode*> GTN; - typedef GTN::ChildIteratorType Iter; - for (Iter I = GTN::child_begin(DTN), E = GTN::child_end(DTN); I != E; ++I) - getBlockTraversalOrder((*I)->getBlock(), Order); + for (auto *DTN : children<DomTreeNode*>(DT->getNode(Root))) + getBlockTraversalOrder(DTN->getBlock(), Order); } bool HexagonCommonGEP::isHandledGepForm(GetElementPtrInst *GepI) { @@ -1235,11 +1232,8 @@ void HexagonCommonGEP::removeDeadCode() { for (unsigned i = 0; i < BO.size(); ++i) { BasicBlock *B = cast<BasicBlock>(BO[i]); - DomTreeNode *N = DT->getNode(B); - typedef GraphTraits<DomTreeNode*> GTN; - typedef GTN::ChildIteratorType Iter; - for (Iter I = GTN::child_begin(N), E = GTN::child_end(N); I != E; ++I) - BO.push_back((*I)->getBlock()); + for (auto DTN : children<DomTreeNode*>(DT->getNode(B))) + BO.push_back(DTN->getBlock()); } for (unsigned i = BO.size(); i > 0; --i) { diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp index 36080997ec6b..8118c8eb149d 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -440,22 +440,28 @@ HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) { // Put instructions that last defined integer or double registers into the // map. - for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) { - MachineOperand &Op = MI.getOperand(I); - if (!Op.isReg() || !Op.isDef() || !Op.getReg()) - continue; - unsigned Reg = Op.getReg(); - if (Hexagon::DoubleRegsRegClass.contains(Reg)) { - for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { - LastDef[*SubRegs] = &MI; - } - } else if (Hexagon::IntRegsRegClass.contains(Reg)) - LastDef[Reg] = &MI; + for (MachineOperand &Op : MI.operands()) { + if (Op.isReg()) { + if (!Op.isDef() || !Op.getReg()) + continue; + unsigned Reg = Op.getReg(); + if (Hexagon::DoubleRegsRegClass.contains(Reg)) { + for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) + LastDef[*SubRegs] = &MI; + } else if (Hexagon::IntRegsRegClass.contains(Reg)) + LastDef[Reg] = &MI; + } else if (Op.isRegMask()) { + for (unsigned Reg : Hexagon::IntRegsRegClass) + if (Op.clobbersPhysReg(Reg)) + LastDef[Reg] = &MI; + } } } } bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) { + if (skipFunction(*MF.getFunction())) + return false; if (IsCombinesDisabled) return false; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonDepArch.h b/contrib/llvm/lib/Target/Hexagon/HexagonDepArch.h new file mode 100644 index 000000000000..1009aa39cefb --- /dev/null +++ b/contrib/llvm/lib/Target/Hexagon/HexagonDepArch.h @@ -0,0 +1,10 @@ +//===--- HexagonDepArch.h -------------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +enum HexagonArchEnum { V4,V5,V55,V60,V62 }; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonDepArch.td b/contrib/llvm/lib/Target/Hexagon/HexagonDepArch.td new file mode 100644 index 000000000000..5b1d02c136f0 --- /dev/null +++ b/contrib/llvm/lib/Target/Hexagon/HexagonDepArch.td @@ -0,0 +1,19 @@ +//===--- HexagonDepArch.td ------------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +def ArchV62: SubtargetFeature<"v62", "HexagonArchVersion", "V62", "Enable Hexagon V62 architecture">; +def HasV62T : Predicate<"HST->hasV62TOps()">, AssemblerPredicate<"ArchV62">; +def ArchV60: SubtargetFeature<"v60", "HexagonArchVersion", "V60", "Enable Hexagon V60 architecture">; +def HasV60T : Predicate<"HST->hasV60TOps()">, AssemblerPredicate<"ArchV60">; +def ArchV55: SubtargetFeature<"v55", "HexagonArchVersion", "V55", "Enable Hexagon V55 architecture">; +def HasV55T : Predicate<"HST->hasV55TOps()">, AssemblerPredicate<"ArchV55">; +def ArchV4: SubtargetFeature<"v4", "HexagonArchVersion", "V4", "Enable Hexagon V4 architecture">; +def HasV4T : Predicate<"HST->hasV4TOps()">, AssemblerPredicate<"ArchV4">; +def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "V5", "Enable Hexagon V5 architecture">; +def HasV5T : Predicate<"HST->hasV5TOps()">, AssemblerPredicate<"ArchV5">; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonDepDecoders.h b/contrib/llvm/lib/Target/Hexagon/HexagonDepDecoders.h new file mode 100644 index 000000000000..aa9787ecf0c8 --- /dev/null +++ b/contrib/llvm/lib/Target/Hexagon/HexagonDepDecoders.h @@ -0,0 +1,64 @@ +//===--- HexagonDepDecoders.h ---------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<4>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<14>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<8>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<7>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<12>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<3>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<13>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<6>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<9>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<5>(MI, tmp, Decoder); + return MCDisassembler::Success; +} +static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, + uint64_t, const void *Decoder) { + signedDecoder<6>(MI, tmp, Decoder); + return MCDisassembler::Success; +} diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonDepITypes.h b/contrib/llvm/lib/Target/Hexagon/HexagonDepITypes.h new file mode 100644 index 000000000000..f8ae39a37994 --- /dev/null +++ b/contrib/llvm/lib/Target/Hexagon/HexagonDepITypes.h @@ -0,0 +1,53 @@ +//===--- HexagonDepITypes.h -----------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +namespace llvm { +namespace HexagonII { +enum Type { + TypeALU32_2op = 0, + TypeALU32_3op = 1, + TypeALU32_ADDI = 2, + TypeALU64 = 3, + TypeCJ = 4, + TypeCOPROC_VMEM = 5, + TypeCR = 7, + TypeCVI_HIST = 10, + TypeCVI_VA = 16, + TypeCVI_VA_DV = 17, + TypeCVI_VINLANESAT = 18, + TypeCVI_VM_CUR_LD = 19, + TypeCVI_VM_LD = 20, + TypeCVI_VM_NEW_ST = 21, + TypeCVI_VM_ST = 22, + TypeCVI_VM_STU = 23, + TypeCVI_VM_TMP_LD = 24, + TypeCVI_VM_VP_LDU = 25, + TypeCVI_VP = 26, + TypeCVI_VP_VS = 27, + TypeCVI_VS = 28, + TypeCVI_VX = 30, + TypeCVI_VX_DV = 31, + TypeDUPLEX = 32, + TypeENDLOOP = 33, + TypeEXTENDER = 34, + TypeJ = 35, + TypeLD = 36, + TypeM = 37, + TypeMAPPING = 38, + TypeNCJ = 39, + TypePSEUDO = 40, + TypeST = 41, + TypeSUBINSN = 42, + TypeS_2op = 43, + TypeS_3op = 44, + TypeV2LDST = 47, + TypeV4LDST = 48 +}; +} +} diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonDepITypes.td b/contrib/llvm/lib/Target/Hexagon/HexagonDepITypes.td new file mode 100644 index 000000000000..f1d689ce12f4 --- /dev/null +++ b/contrib/llvm/lib/Target/Hexagon/HexagonDepITypes.td @@ -0,0 +1,48 @@ +//===--- HexagonDepITypes.td ----------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +class IType<bits<6> t> { bits<6> Value = t; } +def TypeALU32_2op : IType<0>; +def TypeALU32_3op : IType<1>; +def TypeALU32_ADDI : IType<2>; +def TypeALU64 : IType<3>; +def TypeCJ : IType<4>; +def TypeCOPROC_VMEM : IType<5>; +def TypeCR : IType<7>; +def TypeCVI_HIST : IType<10>; +def TypeCVI_VA : IType<16>; +def TypeCVI_VA_DV : IType<17>; +def TypeCVI_VINLANESAT : IType<18>; +def TypeCVI_VM_CUR_LD : IType<19>; +def TypeCVI_VM_LD : IType<20>; +def TypeCVI_VM_NEW_ST : IType<21>; +def TypeCVI_VM_ST : IType<22>; +def TypeCVI_VM_STU : IType<23>; +def TypeCVI_VM_TMP_LD : IType<24>; +def TypeCVI_VM_VP_LDU : IType<25>; +def TypeCVI_VP : IType<26>; +def TypeCVI_VP_VS : IType<27>; +def TypeCVI_VS : IType<28>; +def TypeCVI_VX : IType<30>; +def TypeCVI_VX_DV : IType<31>; +def TypeDUPLEX : IType<32>; +def TypeENDLOOP : IType<33>; +def TypeEXTENDER : IType<34>; +def TypeJ : IType<35>; +def TypeLD : IType<36>; +def TypeM : IType<37>; +def TypeMAPPING : IType<38>; +def TypeNCJ : IType<39>; +def TypePSEUDO : IType<40>; +def TypeST : IType<41>; +def TypeSUBINSN : IType<42>; +def TypeS_2op : IType<43>; +def TypeS_3op : IType<44>; +def TypeV2LDST : IType<47>; +def TypeV4LDST : IType<48>; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td b/contrib/llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td new file mode 100644 index 000000000000..d7a99f48803b --- /dev/null +++ b/contrib/llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td @@ -0,0 +1,4182 @@ +//===--- HexagonDepInstrFormats.td ----------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +class Enc_12122225 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; + bits <3> Qd8; + let Inst{2-0} = Qd8{2-0}; +} +class Enc_16626097 : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} +class Enc_13397056 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <2> Qv4; + let Inst{12-11} = Qv4{1-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_7315939 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <6> n1; + let Inst{28-28} = n1{5-5}; + let Inst{24-22} = n1{4-2}; + let Inst{13-13} = n1{1-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_15275738 : OpcodeHexagon { + bits <12> Ii; + let Inst{26-25} = Ii{11-10}; + let Inst{13-5} = Ii{9-1}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_12822813 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; + bits <2> Pe4; + let Inst{6-5} = Pe4{1-0}; +} +class Enc_10282127 : OpcodeHexagon { + bits <7> Ii; + let Inst{12-7} = Ii{6-1}; + bits <8> II; + let Inst{13-13} = II{7-7}; + let Inst{6-0} = II{6-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_14264243 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> Rt16; + let Inst{11-8} = Rt16{3-0}; +} +class Enc_6778937 : OpcodeHexagon { + bits <5> Rxx32; + let Inst{20-16} = Rxx32{4-0}; + bits <0> sgp10; +} +class Enc_5480539 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; +} +class Enc_11422009 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_16357011 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{8-4} = Vv32{4-0}; + bits <5> Vt32; + let Inst{13-9} = Vt32{4-0}; + bits <4> Vdd16; + let Inst{3-0} = Vdd16{3-0}; +} +class Enc_4975051 : OpcodeHexagon { + bits <19> Ii; + let Inst{26-25} = Ii{18-17}; + let Inst{20-16} = Ii{16-12}; + let Inst{13-5} = Ii{11-3}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_14786238 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} +class Enc_15472748 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_6773159 : OpcodeHexagon { + bits <6> Ii; + let Inst{12-7} = Ii{5-0}; + bits <5> II; + let Inst{4-0} = II{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_12535811 : OpcodeHexagon { + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_14007201 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <8> II; + let Inst{22-16} = II{7-1}; + let Inst{13-13} = II{0-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_2577026 : OpcodeHexagon { + bits <3> Qt8; + let Inst{2-0} = Qt8{2-0}; + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_7305764 : OpcodeHexagon { + bits <5> II; + let Inst{12-8} = II{4-0}; + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; +} +class Enc_11682941 : OpcodeHexagon { + bits <19> Ii; + let Inst{26-25} = Ii{18-17}; + let Inst{20-16} = Ii{16-12}; + let Inst{13-13} = Ii{11-11}; + let Inst{7-0} = Ii{10-3}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_16376009 : OpcodeHexagon { + bits <6> Ii; + let Inst{8-5} = Ii{5-2}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_13249928 : OpcodeHexagon { + bits <9> Ii; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_1971351 : OpcodeHexagon { + bits <5> Ii; + let Inst{8-5} = Ii{4-1}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_13715847 : OpcodeHexagon { + bits <6> Ii; + let Inst{17-16} = Ii{5-4}; + let Inst{6-3} = Ii{3-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_13303422 : OpcodeHexagon { + bits <5> Ii; + let Inst{8-5} = Ii{4-1}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_14574598 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_13094118 : OpcodeHexagon { + bits <5> Css32; + let Inst{20-16} = Css32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_4231995 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_844699 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> n1; + let Inst{28-28} = n1{3-3}; + let Inst{24-22} = n1{2-0}; +} +class Enc_8752140 : OpcodeHexagon { + bits <6> Ii; + let Inst{8-5} = Ii{5-2}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_7978128 : OpcodeHexagon { + bits <1> Ii; + let Inst{8-8} = Ii{0-0}; + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; +} +class Enc_10492541 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_0 : OpcodeHexagon { +} +class Enc_15733946 : OpcodeHexagon { + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_738356 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_14400220 : OpcodeHexagon { + bits <5> Ii; + let Inst{9-5} = Ii{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_15194851 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_14172170 : OpcodeHexagon { + bits <1> Ii; + let Inst{5-5} = Ii{0-0}; + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_10065510 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_14998517 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <3> n1; + let Inst{29-29} = n1{2-2}; + let Inst{26-25} = n1{1-0}; +} +class Enc_16657398 : OpcodeHexagon { + bits <6> Ii; + let Inst{17-16} = Ii{5-4}; + let Inst{6-3} = Ii{3-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_14620934 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_10075393 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; +} +class Enc_8638014 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Vss32; + let Inst{7-3} = Vss32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_13261538 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_8990840 : OpcodeHexagon { + bits <13> Ii; + let Inst{26-25} = Ii{12-11}; + let Inst{13-5} = Ii{10-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_5974204 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_4711514 : OpcodeHexagon { + bits <2> Qu4; + let Inst{9-8} = Qu4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_11492529 : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_9277990 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_6690615 : OpcodeHexagon { + bits <7> Ii; + let Inst{8-4} = Ii{6-2}; + bits <4> Rt16; + let Inst{3-0} = Rt16{3-0}; +} +class Enc_1220199 : OpcodeHexagon { + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_7785569 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <6> n1; + let Inst{28-28} = n1{5-5}; + let Inst{25-22} = n1{4-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_2880796 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> II; + let Inst{22-21} = II{4-3}; + let Inst{7-5} = II{2-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_6858527 : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{4-0} = Vv32{4-0}; +} +class Enc_11863656 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_151014 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <2> Px4; + let Inst{6-5} = Px4{1-0}; +} +class Enc_10333841 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_14044877 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-13} = Ii{5-5}; + let Inst{7-3} = Ii{4-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_13691337 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <2> Qx4; + let Inst{6-5} = Qx4{1-0}; +} +class Enc_3817033 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <3> Qt8; + let Inst{10-8} = Qt8{2-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_3540372 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_5200852 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_15949334 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_3831744 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_8280533 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_10969213 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} +class Enc_3974695 : OpcodeHexagon { + bits <7> Ii; + let Inst{10-4} = Ii{6-0}; + bits <4> Rx16; + let Inst{3-0} = Rx16{3-0}; +} +class Enc_7255914 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_7212930 : OpcodeHexagon { + bits <5> Ii; + let Inst{8-5} = Ii{4-1}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_12781442 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <2> Qd4; + let Inst{1-0} = Qd4{1-0}; +} +class Enc_799555 : OpcodeHexagon { + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_11083408 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{23-19} = Vv32{4-0}; + bits <3> Rt8; + let Inst{18-16} = Rt8{2-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_900013 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_9487067 : OpcodeHexagon { + bits <12> Ii; + let Inst{19-16} = Ii{11-8}; + let Inst{12-5} = Ii{7-0}; + bits <2> Pu4; + let Inst{22-21} = Pu4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_16014536 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_12419313 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> n1; + let Inst{28-28} = n1{3-3}; + let Inst{24-23} = n1{2-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_5503430 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_14767681 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{23-19} = Vv32{4-0}; + bits <3> Rt8; + let Inst{18-16} = Rt8{2-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_9093094 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <8> II; + let Inst{22-16} = II{7-1}; + let Inst{13-13} = II{0-0}; + bits <2> Pu4; + let Inst{24-23} = Pu4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_11542684 : OpcodeHexagon { + bits <16> Ii; + let Inst{27-21} = Ii{15-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_8877260 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{23-19} = Vv32{4-0}; + bits <3> Rt8; + let Inst{18-16} = Rt8{2-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_1737833 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-13} = Ii{5-5}; + let Inst{7-3} = Ii{4-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_255516 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_10721363 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_7076358 : OpcodeHexagon { + bits <5> Zdd8; + let Inst{4-0} = Zdd8{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_11930928 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> II; + let Inst{22-21} = II{4-3}; + let Inst{7-5} = II{2-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_2410156 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_6735062 : OpcodeHexagon { + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_7965855 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_5202340 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vyy32; + let Inst{4-0} = Vyy32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_10568534 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <2> Pu4; + let Inst{22-21} = Pu4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_16730127 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_11224149 : OpcodeHexagon { + bits <8> Ii; + let Inst{13-13} = Ii{7-7}; + let Inst{7-3} = Ii{6-2}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_9772987 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; + bits <5> Rtt32; + let Inst{4-0} = Rtt32{4-0}; +} +class Enc_9238139 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Zdd8; + let Inst{4-0} = Zdd8{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_2082775 : OpcodeHexagon { + bits <4> Ii; + let Inst{11-8} = Ii{3-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_5790679 : OpcodeHexagon { + bits <9> Ii; + let Inst{12-8} = Ii{8-4}; + let Inst{4-3} = Ii{3-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_9305257 : OpcodeHexagon { + bits <5> Zu8; + let Inst{12-8} = Zu8{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_3735566 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_12654528 : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{4-0} = Vvv32{4-0}; +} +class Enc_15290236 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_11139981 : OpcodeHexagon { + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_15546666 : OpcodeHexagon { + bits <9> Ii; + let Inst{10-8} = Ii{8-6}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_486163 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_2079016 : OpcodeHexagon { + bits <2> Ii; + let Inst{1-0} = Ii{1-0}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; +} +class Enc_10095813 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_13133322 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} +class Enc_9422954 : OpcodeHexagon { + bits <2> Pu4; + let Inst{9-8} = Pu4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_10642833 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_14989332 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{4-0} = Vv32{4-0}; +} +class Enc_10263630 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} +class Enc_13937564 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; +} +class Enc_7171569 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_2702036 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_1928953 : OpcodeHexagon { + bits <2> Pu4; + let Inst{9-8} = Pu4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_5853469 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <2> Pe4; + let Inst{6-5} = Pe4{1-0}; +} +class Enc_7692963 : OpcodeHexagon { + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_15140689 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_748676 : OpcodeHexagon { + bits <12> Ii; + let Inst{26-25} = Ii{11-10}; + let Inst{13-13} = Ii{9-9}; + let Inst{7-0} = Ii{8-1}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_3372766 : OpcodeHexagon { + bits <5> Ii; + let Inst{8-5} = Ii{4-1}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_7900405 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_11930027 : OpcodeHexagon { + bits <12> Ii; + let Inst{26-25} = Ii{11-10}; + let Inst{13-5} = Ii{9-1}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; +} +class Enc_971574 : OpcodeHexagon { + bits <6> Ii; + let Inst{22-21} = Ii{5-4}; + let Inst{13-13} = Ii{3-3}; + let Inst{7-5} = Ii{2-0}; + bits <6> II; + let Inst{23-23} = II{5-5}; + let Inst{4-0} = II{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{12-8} = Rd32{4-0}; +} +class Enc_13453446 : OpcodeHexagon { + bits <24> Ii; + let Inst{24-16} = Ii{23-15}; + let Inst{13-1} = Ii{14-2}; +} +class Enc_6356866 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_16246706 : OpcodeHexagon { + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_5326450 : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_11687333 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_2771456 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_11282123 : OpcodeHexagon { + bits <6> Ii; + let Inst{12-7} = Ii{5-0}; + bits <8> II; + let Inst{13-13} = II{7-7}; + let Inst{6-0} = II{6-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_518319 : OpcodeHexagon { + bits <6> Ii; + let Inst{20-16} = Ii{5-1}; + let Inst{5-5} = Ii{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_16104442 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_7912540 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; +} +class Enc_15560488 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_7581852 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_10030031 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_3915770 : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_4075554 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_11326438 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_4050532 : OpcodeHexagon { + bits <16> Ii; + let Inst{26-25} = Ii{15-14}; + let Inst{20-16} = Ii{13-9}; + let Inst{13-13} = Ii{8-8}; + let Inst{7-0} = Ii{7-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_14461004 : OpcodeHexagon { + bits <11> Ii; + let Inst{26-25} = Ii{10-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_13344657 : OpcodeHexagon { + bits <6> Ii; + let Inst{20-16} = Ii{5-1}; + let Inst{8-8} = Ii{0-0}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_13114546 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{5-5} = Ii{0-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; +} +class Enc_14530015 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <6> n1; + let Inst{28-28} = n1{5-5}; + let Inst{25-23} = n1{4-2}; + let Inst{13-13} = n1{1-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_5967898 : OpcodeHexagon { + bits <6> Ii; + let Inst{12-7} = Ii{5-0}; + bits <6> II; + let Inst{13-13} = II{5-5}; + let Inst{4-0} = II{4-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_15450971 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <6> n1; + let Inst{28-28} = n1{5-5}; + let Inst{25-22} = n1{4-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_15536400 : OpcodeHexagon { + bits <6> Ii; + let Inst{3-0} = Ii{5-2}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; +} +class Enc_1291652 : OpcodeHexagon { + bits <1> Ii; + let Inst{8-8} = Ii{0-0}; +} +class Enc_5636753 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; +} +class Enc_5757366 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; +} +class Enc_9752128 : OpcodeHexagon { + bits <7> Ii; + let Inst{8-5} = Ii{6-3}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_13618890 : OpcodeHexagon { + bits <17> Ii; + let Inst{26-25} = Ii{16-15}; + let Inst{20-16} = Ii{14-10}; + let Inst{13-13} = Ii{9-9}; + let Inst{7-0} = Ii{8-1}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_5890213 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_5582416 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_13536408 : OpcodeHexagon { + bits <4> Ii; + let Inst{3-0} = Ii{3-0}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; +} +class Enc_9773189 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rxx32; + let Inst{12-8} = Rxx32{4-0}; +} +class Enc_2152247 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; +} +class Enc_12848507 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{6-6} = Ii{0-0}; + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <5> Ru32; + let Inst{20-16} = Ru32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_16279406 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <2> Qv4; + let Inst{12-11} = Qv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; +} +class Enc_1734121 : OpcodeHexagon { + bits <4> Ii; + let Inst{10-8} = Ii{3-1}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rt16; + let Inst{3-0} = Rt16{3-0}; +} +class Enc_766909 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <2> Pe4; + let Inst{6-5} = Pe4{1-0}; +} +class Enc_4527648 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_8849208 : OpcodeHexagon { + bits <7> Ii; + let Inst{12-7} = Ii{6-1}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{4-0} = Rt32{4-0}; +} +class Enc_9894557 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <6> II; + let Inst{23-21} = II{5-3}; + let Inst{7-5} = II{2-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_4109168 : OpcodeHexagon { + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; +} +class Enc_14560494 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_9773167 : OpcodeHexagon { + bits <7> Ii; + let Inst{12-7} = Ii{6-1}; + bits <5> II; + let Inst{4-0} = II{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_1898420 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; +} +class Enc_11498120 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <2> Qd4; + let Inst{1-0} = Qd4{1-0}; +} +class Enc_15459921 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_10058269 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_10197700 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_12608570 : OpcodeHexagon { + bits <17> Ii; + let Inst{26-25} = Ii{16-15}; + let Inst{20-16} = Ii{14-10}; + let Inst{13-5} = Ii{9-1}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_4804090 : OpcodeHexagon { + bits <6> Ss64; + let Inst{21-16} = Ss64{5-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_14973146 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Qd8; + let Inst{5-3} = Qd8{2-0}; +} +class Enc_5718302 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <2> Pe4; + let Inst{6-5} = Pe4{1-0}; +} +class Enc_2103742 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_7564330 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_2176383 : OpcodeHexagon { + bits <6> Ii; + let Inst{9-4} = Ii{5-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_7736768 : OpcodeHexagon { + bits <12> Ii; + let Inst{26-25} = Ii{11-10}; + let Inst{13-13} = Ii{9-9}; + let Inst{7-0} = Ii{8-1}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_13189194 : OpcodeHexagon { + bits <1> Ii; + let Inst{5-5} = Ii{0-0}; + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_5154851 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_1329520 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Cdd32; + let Inst{4-0} = Cdd32{4-0}; +} +class Enc_14057553 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_9223889 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_10979813 : OpcodeHexagon { + bits <7> Ii; + let Inst{13-13} = Ii{6-6}; + let Inst{7-3} = Ii{5-1}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_13490067 : OpcodeHexagon { + bits <3> Qt8; + let Inst{2-0} = Qt8{2-0}; + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_10076500 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{6-6} = Ii{0-0}; + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <5> Ru32; + let Inst{20-16} = Ru32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_163381 : OpcodeHexagon { + bits <14> Ii; + let Inst{26-25} = Ii{13-12}; + let Inst{13-5} = Ii{11-3}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_10328975 : OpcodeHexagon { + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_14939491 : OpcodeHexagon { + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_8891794 : OpcodeHexagon { + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_7723767 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_2639299 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> Rd16; + let Inst{11-8} = Rd16{3-0}; +} +class Enc_11552785 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_11849200 : OpcodeHexagon { + bits <6> Ii; + let Inst{12-7} = Ii{5-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{4-0} = Rt32{4-0}; +} +class Enc_14868535 : OpcodeHexagon { + bits <17> Ii; + let Inst{23-22} = Ii{16-15}; + let Inst{20-16} = Ii{14-10}; + let Inst{13-13} = Ii{9-9}; + let Inst{7-1} = Ii{8-2}; + bits <2> Pu4; + let Inst{9-8} = Pu4{1-0}; +} +class Enc_48594 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_6608821 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; +} +class Enc_11049656 : OpcodeHexagon { + bits <9> Ii; + let Inst{13-13} = Ii{8-8}; + let Inst{7-3} = Ii{7-3}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_117962 : OpcodeHexagon { + bits <8> Ii; + let Inst{23-21} = Ii{7-5}; + let Inst{13-13} = Ii{4-4}; + let Inst{7-5} = Ii{3-1}; + let Inst{3-3} = Ii{0-0}; + bits <5> II; + let Inst{12-8} = II{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_5900401 : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_36641 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_9626139 : OpcodeHexagon { + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_11971407 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_9852473 : OpcodeHexagon { + bits <13> Ii; + let Inst{26-25} = Ii{12-11}; + let Inst{13-5} = Ii{10-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_6495334 : OpcodeHexagon { + bits <6> Ii; + let Inst{22-21} = Ii{5-4}; + let Inst{13-13} = Ii{3-3}; + let Inst{7-5} = Ii{2-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rd32; + let Inst{12-8} = Rd32{4-0}; +} +class Enc_1186018 : OpcodeHexagon { + bits <17> Ii; + let Inst{26-25} = Ii{16-15}; + let Inst{20-16} = Ii{14-10}; + let Inst{13-13} = Ii{9-9}; + let Inst{7-0} = Ii{8-1}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_15999208 : OpcodeHexagon { + bits <18> Ii; + let Inst{26-25} = Ii{17-16}; + let Inst{20-16} = Ii{15-11}; + let Inst{13-13} = Ii{10-10}; + let Inst{7-0} = Ii{9-2}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_11477246 : OpcodeHexagon { + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; +} +class Enc_7971062 : OpcodeHexagon { + bits <16> Ii; + let Inst{23-22} = Ii{15-14}; + let Inst{20-16} = Ii{13-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_4327792 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_10326434 : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_1572239 : OpcodeHexagon { + bits <2> Qt4; + let Inst{6-5} = Qt4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_6372758 : OpcodeHexagon { + bits <4> Ii; + let Inst{8-5} = Ii{3-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_15793331 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} +class Enc_11424254 : OpcodeHexagon { + bits <2> Qt4; + let Inst{6-5} = Qt4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_4983213 : OpcodeHexagon { + bits <14> Ii; + let Inst{10-0} = Ii{13-3}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_16035138 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; +} +class Enc_8225953 : OpcodeHexagon { + bits <8> Ii; + let Inst{13-13} = Ii{7-7}; + let Inst{7-3} = Ii{6-2}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_4397470 : OpcodeHexagon { + bits <5> II; + let Inst{12-8} = II{4-0}; + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; +} +class Enc_1004392 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; +} +class Enc_16319737 : OpcodeHexagon { + bits <14> Ii; + let Inst{26-25} = Ii{13-12}; + let Inst{13-13} = Ii{11-11}; + let Inst{7-0} = Ii{10-3}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_2296022 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_9664427 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <3> Qss8; + let Inst{2-0} = Qss8{2-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_877823 : OpcodeHexagon { + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; +} +class Enc_1589406 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_6900405 : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_14150875 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{25-22} = n1{3-0}; +} +class Enc_15707793 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Gd32; + let Inst{4-0} = Gd32{4-0}; +} +class Enc_14689096 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{6-6} = Ii{0-0}; + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <5> Ru32; + let Inst{20-16} = Ru32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_9915754 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_7470998 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <2> Qx4; + let Inst{1-0} = Qx4{1-0}; +} +class Enc_11471622 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_14363183 : OpcodeHexagon { + bits <2> Qv4; + let Inst{23-22} = Qv4{1-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_15816255 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_5321335 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <4> Vdd16; + let Inst{7-4} = Vdd16{3-0}; +} +class Enc_12702821 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; +} +class Enc_449439 : OpcodeHexagon { + bits <11> Ii; + let Inst{26-25} = Ii{10-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; +} +class Enc_2054304 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <6> Sd64; + let Inst{5-0} = Sd64{5-0}; +} +class Enc_236434 : OpcodeHexagon { + bits <6> Ii; + let Inst{22-21} = Ii{5-4}; + let Inst{13-13} = Ii{3-3}; + let Inst{7-5} = Ii{2-0}; + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{12-8} = Rd32{4-0}; +} +class Enc_5598813 : OpcodeHexagon { + bits <4> Ii; + let Inst{8-5} = Ii{3-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_8409782 : OpcodeHexagon { + bits <13> Ii; + let Inst{26-25} = Ii{12-11}; + let Inst{13-13} = Ii{10-10}; + let Inst{7-0} = Ii{9-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_15182416 : OpcodeHexagon { + bits <6> Ii; + let Inst{20-16} = Ii{5-1}; + let Inst{8-8} = Ii{0-0}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_4501395 : OpcodeHexagon { + bits <7> Ii; + let Inst{6-3} = Ii{6-3}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_6039436 : OpcodeHexagon { + bits <3> Qtt8; + let Inst{2-0} = Qtt8{2-0}; + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_476163 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; +} +class Enc_11281763 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_9929262 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; +} +class Enc_13174858 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_8437395 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_16578332 : OpcodeHexagon { + bits <9> Ii; + let Inst{10-8} = Ii{8-6}; + bits <5> Zdd8; + let Inst{4-0} = Zdd8{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_12829314 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; +} +class Enc_9744403 : OpcodeHexagon { + bits <5> Vu32; + let Inst{13-9} = Vu32{4-0}; + bits <5> Vv32; + let Inst{8-4} = Vv32{4-0}; + bits <4> Vdd16; + let Inst{3-0} = Vdd16{3-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_10968391 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <7> n1; + let Inst{28-28} = n1{6-6}; + let Inst{25-22} = n1{5-2}; + let Inst{13-13} = n1{1-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_64199 : OpcodeHexagon { + bits <7> Ii; + let Inst{8-4} = Ii{6-2}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_11039423 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_6730375 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; +} +class Enc_16213761 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{23-19} = Vv32{4-0}; + bits <3> Rt8; + let Inst{18-16} = Rt8{2-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_13204995 : OpcodeHexagon { + bits <4> Ii; + let Inst{11-8} = Ii{3-0}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rt16; + let Inst{3-0} = Rt16{3-0}; +} +class Enc_13338314 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_9920336 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; + bits <5> Rtt32; + let Inst{4-0} = Rtt32{4-0}; +} +class Enc_15380240 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; +} +class Enc_3296020 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_2428539 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> n1; + let Inst{28-28} = n1{3-3}; + let Inst{24-23} = n1{2-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_10039393 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_9372046 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; +} +class Enc_2901241 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_16145290 : OpcodeHexagon { + bits <2> Ps4; + let Inst{6-5} = Ps4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_13783220 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_12261611 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_6135183 : OpcodeHexagon { + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rx16; + let Inst{3-0} = Rx16{3-0}; +} +class Enc_5523416 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_13472494 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_16303398 : OpcodeHexagon { + bits <4> Ii; + let Inst{8-5} = Ii{3-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_3494181 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_13983714 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <2> Qd4; + let Inst{1-0} = Qd4{1-0}; +} +class Enc_931653 : OpcodeHexagon { + bits <7> Ii; + let Inst{8-5} = Ii{6-3}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_7622936 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; +} +class Enc_8773155 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-7} = Ii{7-2}; + bits <5> II; + let Inst{4-0} = II{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_5401217 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <3> n1; + let Inst{28-28} = n1{2-2}; + let Inst{24-23} = n1{1-0}; +} +class Enc_6736678 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_3457570 : OpcodeHexagon { + bits <3> Ii; + let Inst{7-5} = Ii{2-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_3813442 : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_3135259 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_5486172 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; + bits <3> Nt8; + let Inst{2-0} = Nt8{2-0}; +} +class Enc_11081334 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vss32; + let Inst{7-3} = Vss32{4-0}; +} +class Enc_9470751 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; +} +class Enc_2683366 : OpcodeHexagon { + bits <3> Quu8; + let Inst{10-8} = Quu8{2-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <3> Qdd8; + let Inst{5-3} = Qdd8{2-0}; +} +class Enc_15830826 : OpcodeHexagon { + bits <14> Ii; + let Inst{10-0} = Ii{13-3}; +} +class Enc_4967902 : OpcodeHexagon { + bits <7> Ii; + let Inst{12-7} = Ii{6-1}; + bits <6> II; + let Inst{13-13} = II{5-5}; + let Inst{4-0} = II{4-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_14287645 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_8324216 : OpcodeHexagon { + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_913538 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <3> Qd8; + let Inst{5-3} = Qd8{2-0}; +} +class Enc_16311032 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_9864697 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <6> II; + let Inst{20-16} = II{5-1}; + let Inst{13-13} = II{0-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_11205051 : OpcodeHexagon { + bits <6> Ii; + let Inst{11-8} = Ii{5-2}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rt16; + let Inst{3-0} = Rt16{3-0}; +} +class Enc_5611087 : OpcodeHexagon { + bits <7> Ii; + let Inst{8-5} = Ii{6-3}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_10915758 : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_8943121 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; +} +class Enc_1539665 : OpcodeHexagon { + bits <5> Cs32; + let Inst{20-16} = Cs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_8479583 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <5> n1; + let Inst{29-29} = n1{4-4}; + let Inst{26-25} = n1{3-2}; + let Inst{23-23} = n1{1-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_313333 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_11544269 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <4> n1; + let Inst{29-29} = n1{3-3}; + let Inst{26-25} = n1{2-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_9018141 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Cd32; + let Inst{4-0} = Cd32{4-0}; +} +class Enc_6152036 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Gdd32; + let Inst{4-0} = Gdd32{4-0}; +} +class Enc_1954437 : OpcodeHexagon { + bits <6> Sss64; + let Inst{21-16} = Sss64{5-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_3742184 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_1835415 : OpcodeHexagon { + bits <7> Ii; + let Inst{10-5} = Ii{6-1}; + bits <2> Pt4; + let Inst{12-11} = Pt4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_1085466 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_13150110 : OpcodeHexagon { + bits <11> Ii; + let Inst{26-25} = Ii{10-9}; + let Inst{13-13} = Ii{8-8}; + let Inst{7-0} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_6772177 : OpcodeHexagon { + bits <5> Zu8; + let Inst{12-8} = Zu8{4-0}; + bits <5> Zd8; + let Inst{4-0} = Zd8{4-0}; +} +class Enc_6616512 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_1886960 : OpcodeHexagon { + bits <16> Ii; + let Inst{26-25} = Ii{15-14}; + let Inst{20-16} = Ii{13-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_2835415 : OpcodeHexagon { + bits <8> Ii; + let Inst{10-5} = Ii{7-2}; + bits <2> Pt4; + let Inst{12-11} = Pt4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_14024197 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_12297800 : OpcodeHexagon { + bits <18> Ii; + let Inst{26-25} = Ii{17-16}; + let Inst{20-16} = Ii{15-11}; + let Inst{13-13} = Ii{10-10}; + let Inst{7-0} = Ii{9-2}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_7254313 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_677558 : OpcodeHexagon { + bits <9> Ii; + let Inst{10-5} = Ii{8-3}; + bits <2> Pt4; + let Inst{12-11} = Pt4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_6223403 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_674613 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_16479122 : OpcodeHexagon { + bits <8> Ii; + let Inst{7-3} = Ii{7-3}; + bits <3> Rdd8; + let Inst{2-0} = Rdd8{2-0}; +} +class Enc_11704059 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_9165078 : OpcodeHexagon { + bits <9> Ii; + let Inst{8-3} = Ii{8-3}; + bits <3> Rtt8; + let Inst{2-0} = Rtt8{2-0}; +} +class Enc_15376009 : OpcodeHexagon { + bits <5> Ii; + let Inst{8-5} = Ii{4-1}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_8838398 : OpcodeHexagon { + bits <4> Ii; + let Inst{21-21} = Ii{3-3}; + let Inst{7-5} = Ii{2-0}; + bits <6> II; + let Inst{13-8} = II{5-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_2328527 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_1451363 : OpcodeHexagon { + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_4030179 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_13770697 : OpcodeHexagon { + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ry32; + let Inst{12-8} = Ry32{4-0}; +} +class Enc_12212978 : OpcodeHexagon { + bits <4> Ii; + let Inst{8-5} = Ii{3-0}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_12665927 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_2082956 : OpcodeHexagon { + bits <32> Ii; + let Inst{27-16} = Ii{31-20}; + let Inst{13-0} = Ii{19-6}; +} +class Enc_220949 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{25-23} = n1{3-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_9939385 : OpcodeHexagon { + bits <9> Ii; + let Inst{12-8} = Ii{8-4}; + let Inst{4-3} = Ii{3-2}; + bits <10> II; + let Inst{20-16} = II{9-5}; + let Inst{7-5} = II{4-2}; + let Inst{1-0} = II{1-0}; +} +class Enc_2117024 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-8} = Ii{7-3}; + let Inst{4-2} = Ii{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_8390029 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_10989558 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_5972412 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vv32; + let Inst{20-16} = Vv32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_12851489 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vss32; + let Inst{7-3} = Vss32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_9554661 : OpcodeHexagon { + bits <6> Ii; + let Inst{12-7} = Ii{5-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_4202401 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_6091631 : OpcodeHexagon { + bits <2> Qs4; + let Inst{9-8} = Qs4{1-0}; + bits <2> Qt4; + let Inst{23-22} = Qt4{1-0}; + bits <2> Qd4; + let Inst{1-0} = Qd4{1-0}; +} +class Enc_10157519 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_4835423 : OpcodeHexagon { + bits <6> Ii; + let Inst{10-5} = Ii{5-0}; + bits <2> Pt4; + let Inst{12-11} = Pt4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_14046916 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; + bits <5> Rt32; + let Inst{4-0} = Rt32{4-0}; +} +class Enc_2921694 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_8732960 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-8} = Ii{7-3}; + let Inst{4-2} = Ii{2-0}; +} +class Enc_5338033 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{24-22} = n1{3-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_6956613 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_2153798 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_16210172 : OpcodeHexagon { + bits <3> Qt8; + let Inst{10-8} = Qt8{2-0}; + bits <3> Qd8; + let Inst{5-3} = Qd8{2-0}; +} +class Enc_5023792 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_1244745 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_10002182 : OpcodeHexagon { + bits <11> Ii; + let Inst{26-25} = Ii{10-9}; + let Inst{13-13} = Ii{8-8}; + let Inst{7-0} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_12492533 : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_1774350 : OpcodeHexagon { + bits <6> Ii; + let Inst{17-16} = Ii{5-4}; + let Inst{6-3} = Ii{3-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_2703240 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <2> Qv4; + let Inst{12-11} = Qv4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; +} +class Enc_6975103 : OpcodeHexagon { + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_9789480 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_12244921 : OpcodeHexagon { + bits <6> Ii; + let Inst{10-8} = Ii{2-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_8674673 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <5> n1; + let Inst{29-29} = n1{4-4}; + let Inst{26-25} = n1{3-2}; + let Inst{23-22} = n1{1-0}; +} +class Enc_8514936 : OpcodeHexagon { + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_13455308 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_10188026 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_3158657 : OpcodeHexagon { + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_10597934 : OpcodeHexagon { + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; + bits <2> n1; + let Inst{9-8} = n1{1-0}; +} +class Enc_10612292 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <2> Qx4; + let Inst{1-0} = Qx4{1-0}; +} +class Enc_5178985 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_3967902 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-7} = Ii{7-2}; + bits <6> II; + let Inst{13-13} = II{5-5}; + let Inst{4-0} = II{4-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_2462143 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_9849208 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-7} = Ii{7-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{4-0} = Rt32{4-0}; +} +class Enc_12618352 : OpcodeHexagon { + bits <5> Rtt32; + let Inst{20-16} = Rtt32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; +} +class Enc_7303598 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; +} +class Enc_13823098 : OpcodeHexagon { + bits <5> Gss32; + let Inst{20-16} = Gss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_16388420 : OpcodeHexagon { + bits <2> Qs4; + let Inst{6-5} = Qs4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} +class Enc_8328140 : OpcodeHexagon { + bits <16> Ii; + let Inst{21-21} = Ii{15-15}; + let Inst{13-8} = Ii{14-9}; + let Inst{2-0} = Ii{8-6}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_1793896 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_4944558 : OpcodeHexagon { + bits <2> Qu4; + let Inst{9-8} = Qu4{1-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{4-0} = Vx32{4-0}; +} +class Enc_13211717 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{20-16} = Vvv32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_8170340 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; + bits <3> Qdd8; + let Inst{2-0} = Qdd8{2-0}; +} +class Enc_14071773 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_8605375 : OpcodeHexagon { + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_12711252 : OpcodeHexagon { + bits <2> Pv4; + let Inst{9-8} = Pv4{1-0}; +} +class Enc_8202458 : OpcodeHexagon { + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_8577055 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{25-23} = n1{3-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_1409050 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; +} +class Enc_7466005 : OpcodeHexagon { + bits <5> Gs32; + let Inst{20-16} = Gs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_2380082 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_10067774 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_11000933 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; + bits <3> Nt8; + let Inst{2-0} = Nt8{2-0}; +} +class Enc_13201267 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_1989309 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vvv32; + let Inst{4-0} = Vvv32{4-0}; +} +class Enc_9082775 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_8065534 : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_4631106 : OpcodeHexagon { + bits <2> Ps4; + let Inst{17-16} = Ps4{1-0}; + bits <2> Pt4; + let Inst{9-8} = Pt4{1-0}; + bits <2> Pu4; + let Inst{7-6} = Pu4{1-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_11065510 : OpcodeHexagon { + bits <5> Ii; + let Inst{6-3} = Ii{4-1}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_6673186 : OpcodeHexagon { + bits <13> Ii; + let Inst{26-25} = Ii{12-11}; + let Inst{13-13} = Ii{10-10}; + let Inst{7-0} = Ii{9-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_8498433 : OpcodeHexagon { + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_4395009 : OpcodeHexagon { + bits <7> Ii; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_10926598 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{12-8} = Vuu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vxx32; + let Inst{7-3} = Vxx32{4-0}; +} +class Enc_7606379 : OpcodeHexagon { + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_8131399 : OpcodeHexagon { + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; +} +class Enc_11522288 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rx32; + let Inst{4-0} = Rx32{4-0}; +} +class Enc_114098 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{5-5} = Ii{0-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_5654851 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_12023037 : OpcodeHexagon { + bits <2> Ps4; + let Inst{6-5} = Ps4{1-0}; + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_176263 : OpcodeHexagon { + bits <8> Ii; + let Inst{9-4} = Ii{7-2}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_6130414 : OpcodeHexagon { + bits <16> Ii; + let Inst{23-22} = Ii{15-14}; + let Inst{13-0} = Ii{13-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_631197 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <6> II; + let Inst{23-21} = II{5-3}; + let Inst{7-5} = II{2-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; +} +class Enc_16214129 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_8333157 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_4834775 : OpcodeHexagon { + bits <6> II; + let Inst{13-8} = II{5-0}; + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rd16; + let Inst{19-16} = Rd16{3-0}; +} +class Enc_16601956 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_15946706 : OpcodeHexagon { + bits <2> Ii; + let Inst{6-5} = Ii{1-0}; + bits <3> Rdd8; + let Inst{2-0} = Rdd8{2-0}; +} +class Enc_6923828 : OpcodeHexagon { + bits <4> Ii; + let Inst{13-13} = Ii{3-3}; + let Inst{10-8} = Ii{2-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; +} +class Enc_1332717 : OpcodeHexagon { + bits <2> Pu4; + let Inst{6-5} = Pu4{1-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_1786883 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <6> Sdd64; + let Inst{5-0} = Sdd64{5-0}; +} +class Enc_14303394 : OpcodeHexagon { + bits <6> Ii; + let Inst{8-5} = Ii{5-2}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_9282127 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-7} = Ii{7-2}; + bits <8> II; + let Inst{13-13} = II{7-7}; + let Inst{6-0} = II{6-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_2813446 : OpcodeHexagon { + bits <4> Ii; + let Inst{6-3} = Ii{3-0}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_364753 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <4> n1; + let Inst{29-29} = n1{3-3}; + let Inst{26-25} = n1{2-1}; + let Inst{23-23} = n1{0-0}; +} +class Enc_12477789 : OpcodeHexagon { + bits <15> Ii; + let Inst{21-21} = Ii{14-14}; + let Inst{13-13} = Ii{13-13}; + let Inst{11-1} = Ii{12-2}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; +} +class Enc_44555 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_8497723 : OpcodeHexagon { + bits <6> Ii; + let Inst{13-8} = Ii{5-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rxx32; + let Inst{4-0} = Rxx32{4-0}; +} +class Enc_4359901 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <4> n1; + let Inst{29-29} = n1{3-3}; + let Inst{26-25} = n1{2-1}; + let Inst{22-22} = n1{0-0}; +} +class Enc_11271630 : OpcodeHexagon { + bits <7> Ii; + let Inst{6-3} = Ii{6-3}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_10501894 : OpcodeHexagon { + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <3> Rdd8; + let Inst{2-0} = Rdd8{2-0}; +} +class Enc_9768377 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{4-0} = Vd32{4-0}; +} +class Enc_16268019 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vvv32; + let Inst{12-8} = Vvv32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_8814718 : OpcodeHexagon { + bits <18> Ii; + let Inst{26-25} = Ii{17-16}; + let Inst{20-16} = Ii{15-11}; + let Inst{13-5} = Ii{10-2}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_6212930 : OpcodeHexagon { + bits <6> Ii; + let Inst{8-5} = Ii{5-2}; + bits <2> Pt4; + let Inst{10-9} = Pt4{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_5462762 : OpcodeHexagon { + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vv32; + let Inst{12-8} = Vv32{4-0}; + bits <5> Vw32; + let Inst{4-0} = Vw32{4-0}; +} +class Enc_6154421 : OpcodeHexagon { + bits <7> Ii; + let Inst{13-13} = Ii{6-6}; + let Inst{7-3} = Ii{5-1}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; +} +class Enc_8940892 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_3531000 : OpcodeHexagon { + bits <7> Ii; + let Inst{11-5} = Ii{6-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_14311138 : OpcodeHexagon { + bits <5> Vuu32; + let Inst{20-16} = Vuu32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; +} +class Enc_2216485 : OpcodeHexagon { + bits <6> Ii; + let Inst{22-21} = Ii{5-4}; + let Inst{13-13} = Ii{3-3}; + let Inst{7-5} = Ii{2-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_12395768 : OpcodeHexagon { + bits <16> Ii; + let Inst{26-25} = Ii{15-14}; + let Inst{20-16} = Ii{13-9}; + let Inst{13-13} = Ii{8-8}; + let Inst{7-0} = Ii{7-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; +} +class Enc_11047413 : OpcodeHexagon { + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; +} +class Enc_1256611 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_7884306 : OpcodeHexagon { + bits <8> Ii; + let Inst{8-4} = Ii{7-3}; +} +class Enc_11244923 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_8612939 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <5> n1; + let Inst{29-29} = n1{4-4}; + let Inst{26-25} = n1{3-2}; + let Inst{22-22} = n1{1-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_16355964 : OpcodeHexagon { + bits <8> Ii; + let Inst{12-5} = Ii{7-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_12616482 : OpcodeHexagon { + bits <6> II; + let Inst{11-8} = II{5-2}; + let Inst{6-5} = II{1-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; +} +class Enc_5915771 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{24-22} = n1{3-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_14459927 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_7504828 : OpcodeHexagon { + bits <10> Ii; + let Inst{21-21} = Ii{9-9}; + let Inst{13-5} = Ii{8-0}; + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_14209223 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_3931661 : OpcodeHexagon { + bits <6> Ii; + let Inst{8-5} = Ii{5-2}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_13606251 : OpcodeHexagon { + bits <6> Ii; + let Inst{11-8} = Ii{5-2}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_11475992 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vdd32; + let Inst{7-3} = Vdd32{4-0}; +} +class Enc_13133231 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_9959498 : OpcodeHexagon { + bits <8> Ii; + let Inst{22-21} = Ii{7-6}; + let Inst{13-13} = Ii{5-5}; + let Inst{7-5} = Ii{4-2}; + bits <5> Ru32; + let Inst{4-0} = Ru32{4-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rd32; + let Inst{12-8} = Rd32{4-0}; +} +class Enc_8919369 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <5> n1; + let Inst{28-28} = n1{4-4}; + let Inst{24-23} = n1{3-2}; + let Inst{13-13} = n1{1-1}; + let Inst{8-8} = n1{0-0}; +} +class Enc_2968094 : OpcodeHexagon { + bits <7> Ii; + let Inst{11-5} = Ii{6-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_4813442 : OpcodeHexagon { + bits <6> Ii; + let Inst{6-3} = Ii{5-2}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_4684887 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <4> Rs16; + let Inst{19-16} = Rs16{3-0}; + bits <4> n1; + let Inst{28-28} = n1{3-3}; + let Inst{25-23} = n1{2-0}; +} +class Enc_15606259 : OpcodeHexagon { + bits <4> Ii; + let Inst{11-8} = Ii{3-0}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_2268028 : OpcodeHexagon { + bits <3> Qtt8; + let Inst{10-8} = Qtt8{2-0}; + bits <3> Qdd8; + let Inst{5-3} = Qdd8{2-0}; +} +class Enc_13430430 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Rt32; + let Inst{20-16} = Rt32{4-0}; + bits <5> Vd32; + let Inst{7-3} = Vd32{4-0}; + bits <3> Qxx8; + let Inst{2-0} = Qxx8{2-0}; +} +class Enc_13336212 : OpcodeHexagon { + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; + bits <1> n1; + let Inst{9-9} = n1{0-0}; +} +class Enc_15008287 : OpcodeHexagon { + bits <5> Vu32; + let Inst{20-16} = Vu32{4-0}; + bits <3> Rt8; + let Inst{2-0} = Rt8{2-0}; + bits <5> Vx32; + let Inst{7-3} = Vx32{4-0}; + bits <5> Vy32; + let Inst{12-8} = Vy32{4-0}; +} +class Enc_4897205 : OpcodeHexagon { + bits <2> Qs4; + let Inst{9-8} = Qs4{1-0}; + bits <2> Qd4; + let Inst{1-0} = Qd4{1-0}; +} +class Enc_8038806 : OpcodeHexagon { + bits <4> Ii; + let Inst{11-8} = Ii{3-0}; + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_12669374 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vxx32; + let Inst{4-0} = Vxx32{4-0}; +} +class Enc_971347 : OpcodeHexagon { + bits <4> Ii; + let Inst{8-5} = Ii{3-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Ryy32; + let Inst{4-0} = Ryy32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_1997594 : OpcodeHexagon { + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Rdd32; + let Inst{4-0} = Rdd32{4-0}; +} +class Enc_11940513 : OpcodeHexagon { + bits <2> Ii; + let Inst{13-13} = Ii{1-1}; + let Inst{7-7} = Ii{0-0}; + bits <2> Pv4; + let Inst{6-5} = Pv4{1-0}; + bits <5> Rs32; + let Inst{20-16} = Rs32{4-0}; + bits <5> Ru32; + let Inst{12-8} = Ru32{4-0}; + bits <5> Rt32; + let Inst{4-0} = Rt32{4-0}; +} +class Enc_2735552 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <2> Pv4; + let Inst{12-11} = Pv4{1-0}; + bits <3> Os8; + let Inst{2-0} = Os8{2-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_16410950 : OpcodeHexagon { + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <5> Vs32; + let Inst{7-3} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_6226085 : OpcodeHexagon { + bits <5> Ii; + let Inst{12-8} = Ii{4-0}; + bits <5> II; + let Inst{22-21} = II{4-3}; + let Inst{7-5} = II{2-0}; + bits <5> Rd32; + let Inst{4-0} = Rd32{4-0}; +} +class Enc_14193700 : OpcodeHexagon { + bits <6> II; + let Inst{5-0} = II{5-0}; + bits <3> Nt8; + let Inst{10-8} = Nt8{2-0}; + bits <5> Re32; + let Inst{20-16} = Re32{4-0}; +} +class Enc_15763937 : OpcodeHexagon { + bits <11> Ii; + let Inst{21-20} = Ii{10-9}; + let Inst{7-1} = Ii{8-2}; + bits <3> Ns8; + let Inst{18-16} = Ns8{2-0}; + bits <6> n1; + let Inst{29-29} = n1{5-5}; + let Inst{26-25} = n1{4-3}; + let Inst{23-22} = n1{2-1}; + let Inst{13-13} = n1{0-0}; +} +class Enc_2492727 : OpcodeHexagon { + bits <5> Rss32; + let Inst{20-16} = Rss32{4-0}; + bits <5> Rt32; + let Inst{12-8} = Rt32{4-0}; + bits <2> Pd4; + let Inst{1-0} = Pd4{1-0}; +} +class Enc_13425035 : OpcodeHexagon { + bits <2> Qv4; + let Inst{12-11} = Qv4{1-0}; + bits <1> Mu2; + let Inst{13-13} = Mu2{0-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_4135257 : OpcodeHexagon { + bits <4> Ii; + let Inst{10-8} = Ii{3-1}; + bits <4> Rs16; + let Inst{7-4} = Rs16{3-0}; + bits <4> Rd16; + let Inst{3-0} = Rd16{3-0}; +} +class Enc_14631806 : OpcodeHexagon { + bits <5> Vu32; + let Inst{12-8} = Vu32{4-0}; + bits <5> Vdd32; + let Inst{4-0} = Vdd32{4-0}; +} +class Enc_12397062 : OpcodeHexagon { + bits <3> Ii; + let Inst{10-8} = Ii{2-0}; + bits <2> Qv4; + let Inst{12-11} = Qv4{1-0}; + bits <5> Vs32; + let Inst{4-0} = Vs32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} +class Enc_11959851 : OpcodeHexagon { + bits <7> Ii; + let Inst{6-3} = Ii{6-3}; + bits <2> Pv4; + let Inst{1-0} = Pv4{1-0}; + bits <5> Rtt32; + let Inst{12-8} = Rtt32{4-0}; + bits <5> Rx32; + let Inst{20-16} = Rx32{4-0}; +} diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td b/contrib/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td new file mode 100644 index 000000000000..2bfde9acaea9 --- /dev/null +++ b/contrib/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td @@ -0,0 +1,45573 @@ +//===--- HexagonDepInstrInfo.td -------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +def A2_abs : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = abs($Rs32)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10001100100; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_absp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = abs($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10000000100; +} +def A2_abssat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = abs($Rs32):sat", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000101; +let Inst{31-21} = 0b10001100100; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_add : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = add($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_14071773, PredNewRel, ImmRegRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110011000; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_add"; +let InputType = "reg"; +let BaseOpcode = "A2_add"; +let isCommutable = 1; +let isPredicable = 1; +} +def A2_addh_h16_hh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.h,$Rs32.h):<<16", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101010; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_addh_h16_hl : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.h,$Rs32.l):<<16", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101010; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_addh_h16_lh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.l,$Rs32.h):<<16", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101010; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_addh_h16_ll : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.l,$Rs32.l):<<16", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101010; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_addh_h16_sat_hh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.h,$Rs32.h):sat:<<16", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101010; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_addh_h16_sat_hl : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.h,$Rs32.l):sat:<<16", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101010; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_addh_h16_sat_lh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.l,$Rs32.h):sat:<<16", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101010; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_addh_h16_sat_ll : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.l,$Rs32.l):sat:<<16", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101010; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_addh_l16_hl : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.l,$Rs32.h)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101000; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_addh_l16_ll : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.l,$Rs32.l)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101000; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_addh_l16_sat_hl : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.l,$Rs32.h):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101000; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_addh_l16_sat_ll : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = add($Rt32.l,$Rs32.l):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101000; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_addi : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = add($Rs32,#$Ii)", +ALU32_ADDI_tc_1_SLOT0123, TypeALU32_ADDI>, Enc_11542684, PredNewRel, ImmRegRel { +let Inst{31-28} = 0b1011; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_add"; +let InputType = "imm"; +let BaseOpcode = "A2_addi"; +let isPredicable = 1; +let isAdd = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 16; +let opExtentAlign = 0; +} +def A2_addp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = add($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011000; +let isCommutable = 1; +let isAdd = 1; +} +def A2_addpsat : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = add($Rss32,$Rtt32):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011011; +let Defs = [USR_OVF]; +let isCommutable = 1; +} +def A2_addsat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = add($Rs32,$Rt32):sat", +ALU32_3op_tc_2_SLOT0123, TypeALU32_3op>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110110010; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +let InputType = "reg"; +let isCommutable = 1; +} +def A2_addsp : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), +"$Rdd32 = add($Rs32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64> { +let isPseudo = 1; +} +def A2_addsph : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = add($Rss32,$Rtt32):raw:hi", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011011; +} +def A2_addspl : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = add($Rss32,$Rtt32):raw:lo", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011011; +} +def A2_and : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = and($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_14071773, PredNewRel, ImmRegRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110001000; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_and"; +let InputType = "reg"; +let BaseOpcode = "A2_and"; +let isCommutable = 1; +let isPredicable = 1; +} +def A2_andir : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = and($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_13472494, ImmRegRel { +let Inst{31-22} = 0b0111011000; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_and"; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +} +def A2_andp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = and($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011111; +let isCommutable = 1; +} +def A2_aslh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = aslh($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_4075554, PredNewRel { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b01110000000; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_aslh"; +let isPredicable = 1; +} +def A2_asrh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = asrh($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_4075554, PredNewRel { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b01110000001; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_asrh"; +let isPredicable = 1; +} +def A2_combine_hh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = combine($Rt32.h,$Rs32.h)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110011100; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +} +def A2_combine_hl : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = combine($Rt32.h,$Rs32.l)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110011101; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +} +def A2_combine_lh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = combine($Rt32.l,$Rs32.h)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110011110; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +} +def A2_combine_ll : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = combine($Rt32.l,$Rs32.l)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110011111; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +} +def A2_combineii : HInst< +(outs DoubleRegs:$Rdd32), +(ins s32_0Imm:$Ii, s8_0Imm:$II), +"$Rdd32 = combine(#$Ii,#$II)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_14007201 { +let Inst{31-23} = 0b011111000; +let isReMaterializable = 1; +let isAsCheapAsAMove = 1; +let isMoveImm = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A2_combinew : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = combine($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_1997594, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110101000; +let InputType = "reg"; +let BaseOpcode = "A2_combinew"; +let isPredicable = 1; +} +def A2_max : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = max($Rs32,$Rt32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101110; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_maxp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = max($Rss32,$Rtt32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011110; +} +def A2_maxu : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = maxu($Rs32,$Rt32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101110; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_maxup : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = maxu($Rss32,$Rtt32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011110; +} +def A2_min : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = min($Rt32,$Rs32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101101; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_minp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = min($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011101; +} +def A2_minu : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = minu($Rt32,$Rs32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101101; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_minup : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = minu($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011101; +} +def A2_neg : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = neg($Rs32)", +PSEUDO, TypeALU32_2op> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def A2_negp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = neg($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000101; +let Inst{31-21} = 0b10000000100; +} +def A2_negsat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = neg($Rs32):sat", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10001100100; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_nop : HInst< +(outs), +(ins), +"nop", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_0 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-16} = 0b0111111100000000; +} +def A2_not : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = not($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def A2_notp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = not($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10000000100; +} +def A2_or : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = or($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_14071773, PredNewRel, ImmRegRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110001001; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_or"; +let InputType = "reg"; +let BaseOpcode = "A2_or"; +let isCommutable = 1; +let isPredicable = 1; +} +def A2_orir : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = or($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_13472494, ImmRegRel { +let Inst{31-22} = 0b0111011010; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_or"; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +} +def A2_orp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = or($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011111; +let isCommutable = 1; +} +def A2_paddf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pu4) $Rd32 = add($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel, ImmRegRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111011000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_add"; +let InputType = "reg"; +let BaseOpcode = "A2_add"; +} +def A2_paddfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pu4.new) $Rd32 = add($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel, ImmRegRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111011000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let CextOpcode = "A2_add"; +let InputType = "reg"; +let BaseOpcode = "A2_add"; +} +def A2_paddif : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), +"if (!$Pu4) $Rd32 = add($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_10568534, PredNewRel, ImmRegRel { +let Inst{13-13} = 0b0; +let Inst{31-23} = 0b011101001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_add"; +let InputType = "imm"; +let BaseOpcode = "A2_addi"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A2_paddifnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), +"if (!$Pu4.new) $Rd32 = add($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_10568534, PredNewRel, ImmRegRel { +let Inst{13-13} = 0b1; +let Inst{31-23} = 0b011101001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let CextOpcode = "A2_add"; +let InputType = "imm"; +let BaseOpcode = "A2_addi"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A2_paddit : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), +"if ($Pu4) $Rd32 = add($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_10568534, PredNewRel, ImmRegRel { +let Inst{13-13} = 0b0; +let Inst{31-23} = 0b011101000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_add"; +let InputType = "imm"; +let BaseOpcode = "A2_addi"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A2_padditnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), +"if ($Pu4.new) $Rd32 = add($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_10568534, PredNewRel, ImmRegRel { +let Inst{13-13} = 0b1; +let Inst{31-23} = 0b011101000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let CextOpcode = "A2_add"; +let InputType = "imm"; +let BaseOpcode = "A2_addi"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A2_paddt : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pu4) $Rd32 = add($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel, ImmRegRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111011000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_add"; +let InputType = "reg"; +let BaseOpcode = "A2_add"; +} +def A2_paddtnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pu4.new) $Rd32 = add($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel, ImmRegRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111011000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let CextOpcode = "A2_add"; +let InputType = "reg"; +let BaseOpcode = "A2_add"; +} +def A2_pandf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pu4) $Rd32 = and($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111001000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_and"; +} +def A2_pandfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pu4.new) $Rd32 = and($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111001000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_and"; +} +def A2_pandt : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pu4) $Rd32 = and($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111001000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_and"; +} +def A2_pandtnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pu4.new) $Rd32 = and($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111001000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_and"; +} +def A2_porf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pu4) $Rd32 = or($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111001001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_or"; +} +def A2_porfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pu4.new) $Rd32 = or($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111001001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_or"; +} +def A2_port : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pu4) $Rd32 = or($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111001001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_or"; +} +def A2_portnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pu4.new) $Rd32 = or($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111001001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_or"; +} +def A2_psubf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), +"if (!$Pu4) $Rd32 = sub($Rt32,$Rs32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_1332717, PredNewRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111011001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_sub"; +} +def A2_psubfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), +"if (!$Pu4.new) $Rd32 = sub($Rt32,$Rs32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_1332717, PredNewRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111011001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_sub"; +} +def A2_psubt : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), +"if ($Pu4) $Rd32 = sub($Rt32,$Rs32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_1332717, PredNewRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111011001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_sub"; +} +def A2_psubtnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), +"if ($Pu4.new) $Rd32 = sub($Rt32,$Rs32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_1332717, PredNewRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111011001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_sub"; +} +def A2_pxorf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pu4) $Rd32 = xor($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111001011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_xor"; +} +def A2_pxorfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pu4.new) $Rd32 = xor($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111001011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_xor"; +} +def A2_pxort : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pu4) $Rd32 = xor($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111001011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_xor"; +} +def A2_pxortnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pu4.new) $Rd32 = xor($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139, PredNewRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111001011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_xor"; +} +def A2_roundsat : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = round($Rss32):sat", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10001000110; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_sat : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = sat($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001000110; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_satb : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = satb($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000111; +let Inst{31-21} = 0b10001100110; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_sath : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = sath($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10001100110; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_satub : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = satub($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10001100110; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_satuh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = satuh($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000101; +let Inst{31-21} = 0b10001100110; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_sub : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32,$Rs32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8605375, PredNewRel, ImmRegRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110011001; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_sub"; +let InputType = "reg"; +let BaseOpcode = "A2_sub"; +let isPredicable = 1; +} +def A2_subh_h16_hh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.h,$Rs32.h):<<16", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101011; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_subh_h16_hl : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.h,$Rs32.l):<<16", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101011; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_subh_h16_lh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.l,$Rs32.h):<<16", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101011; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_subh_h16_ll : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.l,$Rs32.l):<<16", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101011; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_subh_h16_sat_hh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.h,$Rs32.h):sat:<<16", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101011; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_subh_h16_sat_hl : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.h,$Rs32.l):sat:<<16", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101011; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_subh_h16_sat_lh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.l,$Rs32.h):sat:<<16", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101011; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_subh_h16_sat_ll : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.l,$Rs32.l):sat:<<16", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101011; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_subh_l16_hl : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.l,$Rs32.h)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101001; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_subh_l16_ll : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.l,$Rs32.l)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101001; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_subh_l16_sat_hl : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.l,$Rs32.h):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101001; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_subh_l16_sat_ll : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32.l,$Rs32.l):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101001; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def A2_subp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = sub($Rtt32,$Rss32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011001; +} +def A2_subri : HInst< +(outs IntRegs:$Rd32), +(ins s32_0Imm:$Ii, IntRegs:$Rs32), +"$Rd32 = sub(#$Ii,$Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_13472494, PredNewRel, ImmRegRel { +let Inst{31-22} = 0b0111011001; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_sub"; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +} +def A2_subsat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32,$Rs32):sat", +ALU32_3op_tc_2_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110110110; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +let InputType = "reg"; +} +def A2_svaddh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = vaddh($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110110000; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +let isCommutable = 1; +} +def A2_svaddhs : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = vaddh($Rs32,$Rt32):sat", +ALU32_3op_tc_2_SLOT0123, TypeALU32_3op>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110110001; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +let InputType = "reg"; +let isCommutable = 1; +} +def A2_svadduhs : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = vadduh($Rs32,$Rt32):sat", +ALU32_3op_tc_2_SLOT0123, TypeALU32_3op>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110110011; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +let InputType = "reg"; +let isCommutable = 1; +} +def A2_svavgh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = vavgh($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110111000; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +let isCommutable = 1; +} +def A2_svavghs : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = vavgh($Rs32,$Rt32):rnd", +ALU32_3op_tc_2_SLOT0123, TypeALU32_3op>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110111001; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +let isCommutable = 1; +} +def A2_svnavgh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = vnavgh($Rt32,$Rs32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110111011; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +} +def A2_svsubh : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = vsubh($Rt32,$Rs32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110110100; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +} +def A2_svsubhs : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = vsubh($Rt32,$Rs32):sat", +ALU32_3op_tc_2_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110110101; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +let InputType = "reg"; +} +def A2_svsubuhs : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = vsubuh($Rt32,$Rs32):sat", +ALU32_3op_tc_2_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110110111; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +let InputType = "reg"; +} +def A2_swiz : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = swiz($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000111; +let Inst{31-21} = 0b10001100100; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_sxtb : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = sxtb($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_4075554, PredNewRel { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b01110000101; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_sxtb"; +let isPredicable = 1; +} +def A2_sxth : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = sxth($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_4075554, PredNewRel { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b01110000111; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_sxth"; +let isPredicable = 1; +} +def A2_sxtw : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = sxtw($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4030179 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10000100010; +} +def A2_tfr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = $Rs32", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_4075554, PredNewRel { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b01110000011; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +let BaseOpcode = "A2_tfr"; +let isPredicable = 1; +} +def A2_tfrcrr : HInst< +(outs IntRegs:$Rd32), +(ins CtrRegs:$Cs32), +"$Rd32 = $Cs32", +CR_tc_3x_SLOT3, TypeCR>, Enc_1539665 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b01101010000; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_tfrf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) $Rd32 = $Rs32", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, PredNewRel, ImmRegRel { +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_tfr"; +let InputType = "reg"; +let BaseOpcode = "A2_tfr"; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def A2_tfrfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4.new) $Rd32 = $Rs32", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, PredNewRel, ImmRegRel { +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let CextOpcode = "A2_tfr"; +let InputType = "reg"; +let BaseOpcode = "A2_tfr"; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def A2_tfrih : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, u16_0Imm:$Ii), +"$Rx32.h = #$Ii", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_6130414 { +let Inst{21-21} = 0b1; +let Inst{31-24} = 0b01110010; +let hasNewValue = 1; +let opNewValue = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def A2_tfril : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, u16_0Imm:$Ii), +"$Rx32.l = #$Ii", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_6130414 { +let Inst{21-21} = 0b1; +let Inst{31-24} = 0b01110001; +let hasNewValue = 1; +let opNewValue = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def A2_tfrp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = $Rss32", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, PredNewRel { +let BaseOpcode = "A2_tfrp"; +let isPredicable = 1; +let isPseudo = 1; +} +def A2_tfrpf : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pu4, DoubleRegs:$Rss32), +"if (!$Pu4) $Rdd32 = $Rss32", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, PredNewRel { +let isPredicated = 1; +let isPredicatedFalse = 1; +let BaseOpcode = "A2_tfrp"; +let isPseudo = 1; +} +def A2_tfrpfnew : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pu4, DoubleRegs:$Rss32), +"if (!$Pu4.new) $Rdd32 = $Rss32", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, PredNewRel { +let isPredicated = 1; +let isPredicatedFalse = 1; +let isPredicatedNew = 1; +let BaseOpcode = "A2_tfrp"; +let isPseudo = 1; +} +def A2_tfrpi : HInst< +(outs DoubleRegs:$Rdd32), +(ins s8_0Imm:$Ii), +"$Rdd32 = #$Ii", +ALU64_tc_1_SLOT23, TypeALU64> { +let isReMaterializable = 1; +let isAsCheapAsAMove = 1; +let isMoveImm = 1; +let isPseudo = 1; +} +def A2_tfrpt : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pu4, DoubleRegs:$Rss32), +"if ($Pu4) $Rdd32 = $Rss32", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, PredNewRel { +let isPredicated = 1; +let BaseOpcode = "A2_tfrp"; +let isPseudo = 1; +} +def A2_tfrptnew : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pu4, DoubleRegs:$Rss32), +"if ($Pu4.new) $Rdd32 = $Rss32", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, PredNewRel { +let isPredicated = 1; +let isPredicatedNew = 1; +let BaseOpcode = "A2_tfrp"; +let isPseudo = 1; +} +def A2_tfrrcr : HInst< +(outs CtrRegs:$Cd32), +(ins IntRegs:$Rs32), +"$Cd32 = $Rs32", +CR_tc_3x_SLOT3, TypeCR>, Enc_9018141 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b01100010001; +let hasNewValue = 1; +let opNewValue = 0; +} +def A2_tfrsi : HInst< +(outs IntRegs:$Rd32), +(ins s32_0Imm:$Ii), +"$Rd32 = #$Ii", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_7971062, PredNewRel, ImmRegRel { +let Inst{21-21} = 0b0; +let Inst{31-24} = 0b01111000; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_tfr"; +let InputType = "imm"; +let BaseOpcode = "A2_tfrsi"; +let isPredicable = 1; +let isReMaterializable = 1; +let isAsCheapAsAMove = 1; +let isMoveImm = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 16; +let opExtentAlign = 0; +} +def A2_tfrt : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) $Rd32 = $Rs32", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, PredNewRel, ImmRegRel { +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_tfr"; +let InputType = "reg"; +let BaseOpcode = "A2_tfr"; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def A2_tfrtnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4.new) $Rd32 = $Rs32", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, PredNewRel, ImmRegRel { +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let CextOpcode = "A2_tfr"; +let InputType = "reg"; +let BaseOpcode = "A2_tfr"; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def A2_vabsh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = vabsh($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10000000010; +} +def A2_vabshsat : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = vabsh($Rss32):sat", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000101; +let Inst{31-21} = 0b10000000010; +let Defs = [USR_OVF]; +} +def A2_vabsw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = vabsw($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10000000010; +} +def A2_vabswsat : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = vabsw($Rss32):sat", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000111; +let Inst{31-21} = 0b10000000010; +let Defs = [USR_OVF]; +} +def A2_vaddb_map : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vaddb($Rss32,$Rtt32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def A2_vaddh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vaddh($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011000; +} +def A2_vaddhs : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vaddh($Rss32,$Rtt32):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011000; +let Defs = [USR_OVF]; +} +def A2_vaddub : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vaddub($Rss32,$Rtt32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011000; +} +def A2_vaddubs : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vaddub($Rss32,$Rtt32):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011000; +let Defs = [USR_OVF]; +} +def A2_vadduhs : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vadduh($Rss32,$Rtt32):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011000; +let Defs = [USR_OVF]; +} +def A2_vaddw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vaddw($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011000; +} +def A2_vaddws : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vaddw($Rss32,$Rtt32):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011000; +let Defs = [USR_OVF]; +} +def A2_vavgh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavgh($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011010; +} +def A2_vavghcr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavgh($Rss32,$Rtt32):crnd", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011010; +let prefersSlot3 = 1; +} +def A2_vavghr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavgh($Rss32,$Rtt32):rnd", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011010; +} +def A2_vavgub : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavgub($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011010; +} +def A2_vavgubr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavgub($Rss32,$Rtt32):rnd", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011010; +} +def A2_vavguh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavguh($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011010; +} +def A2_vavguhr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavguh($Rss32,$Rtt32):rnd", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011010; +} +def A2_vavguw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavguw($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011011; +} +def A2_vavguwr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavguw($Rss32,$Rtt32):rnd", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011011; +} +def A2_vavgw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavgw($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011011; +} +def A2_vavgwcr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavgw($Rss32,$Rtt32):crnd", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011011; +let prefersSlot3 = 1; +} +def A2_vavgwr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vavgw($Rss32,$Rtt32):rnd", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011011; +} +def A2_vcmpbeq : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = vcmpb.eq($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b110000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010000; +} +def A2_vcmpbgtu : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = vcmpb.gtu($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b111000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010000; +} +def A2_vcmpheq : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = vcmph.eq($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b011000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010000; +} +def A2_vcmphgt : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = vcmph.gt($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b100000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010000; +} +def A2_vcmphgtu : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = vcmph.gtu($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b101000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010000; +} +def A2_vcmpweq : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = vcmpw.eq($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010000; +} +def A2_vcmpwgt : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = vcmpw.gt($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b001000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010000; +} +def A2_vcmpwgtu : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = vcmpw.gtu($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b010000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010000; +} +def A2_vconj : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = vconj($Rss32):sat", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000111; +let Inst{31-21} = 0b10000000100; +let Defs = [USR_OVF]; +} +def A2_vmaxb : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vmaxb($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011110; +} +def A2_vmaxh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vmaxh($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011110; +} +def A2_vmaxub : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vmaxub($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011110; +} +def A2_vmaxuh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vmaxuh($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011110; +} +def A2_vmaxuw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vmaxuw($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011101; +} +def A2_vmaxw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vmaxw($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011110; +} +def A2_vminb : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vminb($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011110; +} +def A2_vminh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vminh($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011101; +} +def A2_vminub : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vminub($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011101; +} +def A2_vminuh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vminuh($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011101; +} +def A2_vminuw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vminuw($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011101; +} +def A2_vminw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vminw($Rtt32,$Rss32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011101; +} +def A2_vnavgh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vnavgh($Rtt32,$Rss32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011100; +} +def A2_vnavghcr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vnavgh($Rtt32,$Rss32):crnd:sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def A2_vnavghr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vnavgh($Rtt32,$Rss32):rnd:sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def A2_vnavgw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vnavgw($Rtt32,$Rss32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011100; +} +def A2_vnavgwcr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vnavgw($Rtt32,$Rss32):crnd:sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def A2_vnavgwr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vnavgw($Rtt32,$Rss32):rnd:sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def A2_vraddub : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vraddub($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000010; +let prefersSlot3 = 1; +} +def A2_vraddub_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vraddub($Rss32,$Rtt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A2_vrsadub : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrsadub($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000010; +let prefersSlot3 = 1; +} +def A2_vrsadub_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrsadub($Rss32,$Rtt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A2_vsubb_map : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vsubb($Rss32,$Rtt32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def A2_vsubh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vsubh($Rtt32,$Rss32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011001; +} +def A2_vsubhs : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vsubh($Rtt32,$Rss32):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011001; +let Defs = [USR_OVF]; +} +def A2_vsubub : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vsubub($Rtt32,$Rss32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011001; +} +def A2_vsububs : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vsubub($Rtt32,$Rss32):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011001; +let Defs = [USR_OVF]; +} +def A2_vsubuhs : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vsubuh($Rtt32,$Rss32):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011001; +let Defs = [USR_OVF]; +} +def A2_vsubw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vsubw($Rtt32,$Rss32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011001; +} +def A2_vsubws : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vsubw($Rtt32,$Rss32):sat", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011001; +let Defs = [USR_OVF]; +} +def A2_xor : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = xor($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_14071773, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110001011; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +let BaseOpcode = "A2_xor"; +let isCommutable = 1; +let isPredicable = 1; +} +def A2_xorp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = xor($Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011111; +let isCommutable = 1; +} +def A2_zxtb : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = zxtb($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, PredNewRel { +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_zxtb"; +let isPredicable = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def A2_zxth : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = zxth($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_4075554, PredNewRel { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b01110000110; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_zxth"; +let isPredicable = 1; +} +def A4_addp_c : HInst< +(outs DoubleRegs:$Rdd32, PredRegs:$Px4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in), +"$Rdd32 = add($Rss32,$Rtt32,$Px4):carry", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_151014 { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000010110; +let isPredicateLate = 1; +let Constraints = "$Px4 = $Px4in"; +} +def A4_andn : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = and($Rt32,~$Rs32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110001100; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +} +def A4_andnp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = and($Rtt32,~$Rss32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011111; +} +def A4_bitsplit : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = bitsplit($Rs32,$Rt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010100001; +} +def A4_bitspliti : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rdd32 = bitsplit($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_5654851 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001000110; +} +def A4_boundscheck : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), +"$Pd4 = boundscheck($Rs32,$Rtt32)", +M_tc_3x_SLOT23, TypeALU64> { +let isPseudo = 1; +} +def A4_boundscheck_hi : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = boundscheck($Rss32,$Rtt32):raw:hi", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b101000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11010010000; +} +def A4_boundscheck_lo : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = boundscheck($Rss32,$Rtt32):raw:lo", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b100000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11010010000; +} +def A4_cmpbeq : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmpb.eq($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b110000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111110; +let CextOpcode = "A4_cmpbeq"; +let InputType = "reg"; +let isCommutable = 1; +let isCompare = 1; +} +def A4_cmpbeqi : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u8_0Imm:$Ii), +"$Pd4 = cmpb.eq($Rs32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_6736678, ImmRegRel { +let Inst{4-2} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11011101000; +let CextOpcode = "A4_cmpbeq"; +let InputType = "imm"; +let isCommutable = 1; +let isCompare = 1; +} +def A4_cmpbgt : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmpb.gt($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b010000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111110; +let CextOpcode = "A4_cmpbgt"; +let InputType = "reg"; +let isCompare = 1; +} +def A4_cmpbgti : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, s8_0Imm:$Ii), +"$Pd4 = cmpb.gt($Rs32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_6736678, ImmRegRel { +let Inst{4-2} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11011101001; +let CextOpcode = "A4_cmpbgt"; +let InputType = "imm"; +let isCompare = 1; +} +def A4_cmpbgtu : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmpb.gtu($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b111000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111110; +let CextOpcode = "A4_cmpbgtu"; +let InputType = "reg"; +let isCompare = 1; +} +def A4_cmpbgtui : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u32_0Imm:$Ii), +"$Pd4 = cmpb.gtu($Rs32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3531000, ImmRegRel { +let Inst{4-2} = 0b000; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b11011101010; +let CextOpcode = "A4_cmpbgtu"; +let InputType = "imm"; +let isCompare = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 0; +} +def A4_cmpheq : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmph.eq($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b011000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111110; +let CextOpcode = "A4_cmpheq"; +let InputType = "reg"; +let isCommutable = 1; +let isCompare = 1; +} +def A4_cmpheqi : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Pd4 = cmph.eq($Rs32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_6736678, ImmRegRel { +let Inst{4-2} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11011101000; +let CextOpcode = "A4_cmpheq"; +let InputType = "imm"; +let isCommutable = 1; +let isCompare = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A4_cmphgt : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmph.gt($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b100000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111110; +let CextOpcode = "A4_cmphgt"; +let InputType = "reg"; +let isCompare = 1; +} +def A4_cmphgti : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Pd4 = cmph.gt($Rs32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_6736678, ImmRegRel { +let Inst{4-2} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11011101001; +let CextOpcode = "A4_cmphgt"; +let InputType = "imm"; +let isCompare = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A4_cmphgtu : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmph.gtu($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b101000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111110; +let CextOpcode = "A4_cmphgtu"; +let InputType = "reg"; +let isCompare = 1; +} +def A4_cmphgtui : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u32_0Imm:$Ii), +"$Pd4 = cmph.gtu($Rs32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3531000, ImmRegRel { +let Inst{4-2} = 0b010; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b11011101010; +let CextOpcode = "A4_cmphgtu"; +let InputType = "imm"; +let isCompare = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 0; +} +def A4_combineii : HInst< +(outs DoubleRegs:$Rdd32), +(ins s8_0Imm:$Ii, u32_0Imm:$II), +"$Rdd32 = combine(#$Ii,#$II)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9864697 { +let Inst{31-21} = 0b01111100100; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def A4_combineir : HInst< +(outs DoubleRegs:$Rdd32), +(ins s32_0Imm:$Ii, IntRegs:$Rs32), +"$Rdd32 = combine(#$Ii,$Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_2462143 { +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b01110011001; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A4_combineri : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rdd32 = combine($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_2462143 { +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b01110011000; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A4_cround_ri : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = cround($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def A4_cround_rr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = cround($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def A4_ext : HInst< +(outs), +(ins u26_6Imm:$Ii), +"immext(#$Ii)", +EXTENDER_tc_1_SLOT0123, TypeEXTENDER>, Enc_2082956 { +let Inst{31-28} = 0b0000; +} +def A4_modwrapu : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = modwrap($Rs32,$Rt32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_14071773 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def A4_orn : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = or($Rt32,~$Rs32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8605375 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110001101; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +} +def A4_ornp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = or($Rtt32,~$Rss32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_11687333 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010011111; +} +def A4_paslhf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) $Rd32 = aslh($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1010; +let Inst{31-21} = 0b01110000000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_aslh"; +} +def A4_paslhfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4.new) $Rd32 = aslh($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1011; +let Inst{31-21} = 0b01110000000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_aslh"; +} +def A4_paslht : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) $Rd32 = aslh($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1000; +let Inst{31-21} = 0b01110000000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_aslh"; +} +def A4_paslhtnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4.new) $Rd32 = aslh($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1001; +let Inst{31-21} = 0b01110000000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_aslh"; +} +def A4_pasrhf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) $Rd32 = asrh($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1010; +let Inst{31-21} = 0b01110000001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_asrh"; +} +def A4_pasrhfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4.new) $Rd32 = asrh($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1011; +let Inst{31-21} = 0b01110000001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_asrh"; +} +def A4_pasrht : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) $Rd32 = asrh($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1000; +let Inst{31-21} = 0b01110000001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_asrh"; +} +def A4_pasrhtnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4.new) $Rd32 = asrh($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1001; +let Inst{31-21} = 0b01110000001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_asrh"; +} +def A4_psxtbf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) $Rd32 = sxtb($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1010; +let Inst{31-21} = 0b01110000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_sxtb"; +} +def A4_psxtbfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4.new) $Rd32 = sxtb($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1011; +let Inst{31-21} = 0b01110000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_sxtb"; +} +def A4_psxtbt : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) $Rd32 = sxtb($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1000; +let Inst{31-21} = 0b01110000101; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_sxtb"; +} +def A4_psxtbtnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4.new) $Rd32 = sxtb($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1001; +let Inst{31-21} = 0b01110000101; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_sxtb"; +} +def A4_psxthf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) $Rd32 = sxth($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1010; +let Inst{31-21} = 0b01110000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_sxth"; +} +def A4_psxthfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4.new) $Rd32 = sxth($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1011; +let Inst{31-21} = 0b01110000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_sxth"; +} +def A4_psxtht : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) $Rd32 = sxth($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1000; +let Inst{31-21} = 0b01110000111; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_sxth"; +} +def A4_psxthtnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4.new) $Rd32 = sxth($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1001; +let Inst{31-21} = 0b01110000111; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_sxth"; +} +def A4_pzxtbf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) $Rd32 = zxtb($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1010; +let Inst{31-21} = 0b01110000100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_zxtb"; +} +def A4_pzxtbfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4.new) $Rd32 = zxtb($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1011; +let Inst{31-21} = 0b01110000100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_zxtb"; +} +def A4_pzxtbt : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) $Rd32 = zxtb($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1000; +let Inst{31-21} = 0b01110000100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_zxtb"; +} +def A4_pzxtbtnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4.new) $Rd32 = zxtb($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1001; +let Inst{31-21} = 0b01110000100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_zxtb"; +} +def A4_pzxthf : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) $Rd32 = zxth($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1010; +let Inst{31-21} = 0b01110000110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_zxth"; +} +def A4_pzxthfnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4.new) $Rd32 = zxth($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1011; +let Inst{31-21} = 0b01110000110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_zxth"; +} +def A4_pzxtht : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) $Rd32 = zxth($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1000; +let Inst{31-21} = 0b01110000110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let BaseOpcode = "A2_zxth"; +} +def A4_pzxthtnew : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4.new) $Rd32 = zxth($Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9422954, PredNewRel { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1001; +let Inst{31-21} = 0b01110000110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let BaseOpcode = "A2_zxth"; +} +def A4_rcmpeq : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = cmp.eq($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_14071773, ImmRegRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110011010; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A4_rcmpeq"; +let InputType = "reg"; +let isCommutable = 1; +} +def A4_rcmpeqi : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = cmp.eq($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_16355964, ImmRegRel { +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b01110011010; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A4_rcmpeqi"; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A4_rcmpneq : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = !cmp.eq($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_14071773, ImmRegRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110011011; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A4_rcmpneq"; +let InputType = "reg"; +let isCommutable = 1; +} +def A4_rcmpneqi : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = !cmp.eq($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_16355964, ImmRegRel { +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b01110011011; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A4_rcmpeqi"; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def A4_round_ri : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = round($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def A4_round_ri_sat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = round($Rs32,#$Ii):sat", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def A4_round_rr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = round($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def A4_round_rr_sat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = round($Rs32,$Rt32):sat", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def A4_subp_c : HInst< +(outs DoubleRegs:$Rdd32, PredRegs:$Px4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in), +"$Rdd32 = sub($Rss32,$Rtt32,$Px4):carry", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_151014 { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000010111; +let isPredicateLate = 1; +let Constraints = "$Px4 = $Px4in"; +} +def A4_tfrcpp : HInst< +(outs DoubleRegs:$Rdd32), +(ins CtrRegs64:$Css32), +"$Rdd32 = $Css32", +CR_tc_3x_SLOT3, TypeCR>, Enc_13094118 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b01101000000; +} +def A4_tfrpcp : HInst< +(outs CtrRegs64:$Cdd32), +(ins DoubleRegs:$Rss32), +"$Cdd32 = $Rss32", +CR_tc_3x_SLOT3, TypeCR>, Enc_1329520 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b01100011001; +} +def A4_tlbmatch : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Pd4 = tlbmatch($Rss32,$Rt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_2492727 { +let Inst{7-2} = 0b011000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11010010000; +let isPredicateLate = 1; +} +def A4_vcmpbeq_any : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = any8(vcmpb.eq($Rss32,$Rtt32))", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11010010000; +} +def A4_vcmpbeqi : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, u8_0Imm:$Ii), +"$Pd4 = vcmpb.eq($Rss32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_13455308 { +let Inst{4-2} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11011100000; +} +def A4_vcmpbgt : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = vcmpb.gt($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b010000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11010010000; +} +def A4_vcmpbgti : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, s8_0Imm:$Ii), +"$Pd4 = vcmpb.gt($Rss32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_13455308 { +let Inst{4-2} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11011100001; +} +def A4_vcmpbgtui : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, u7_0Imm:$Ii), +"$Pd4 = vcmpb.gtu($Rss32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_2968094 { +let Inst{4-2} = 0b000; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b11011100010; +} +def A4_vcmpheqi : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, s8_0Imm:$Ii), +"$Pd4 = vcmph.eq($Rss32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_13455308 { +let Inst{4-2} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11011100000; +} +def A4_vcmphgti : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, s8_0Imm:$Ii), +"$Pd4 = vcmph.gt($Rss32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_13455308 { +let Inst{4-2} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11011100001; +} +def A4_vcmphgtui : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, u7_0Imm:$Ii), +"$Pd4 = vcmph.gtu($Rss32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_2968094 { +let Inst{4-2} = 0b010; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b11011100010; +} +def A4_vcmpweqi : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, s8_0Imm:$Ii), +"$Pd4 = vcmpw.eq($Rss32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_13455308 { +let Inst{4-2} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11011100000; +} +def A4_vcmpwgti : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, s8_0Imm:$Ii), +"$Pd4 = vcmpw.gt($Rss32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_13455308 { +let Inst{4-2} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11011100001; +} +def A4_vcmpwgtui : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, u7_0Imm:$Ii), +"$Pd4 = vcmpw.gtu($Rss32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_2968094 { +let Inst{4-2} = 0b100; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b11011100010; +} +def A4_vrmaxh : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), +"$Rxx32 = vrmaxh($Rss32,$Ru32)", +S_3op_tc_3_SLOT23, TypeS_3op>, Enc_9773189 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A4_vrmaxuh : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), +"$Rxx32 = vrmaxuh($Rss32,$Ru32)", +S_3op_tc_3_SLOT23, TypeS_3op>, Enc_9773189 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11001011001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A4_vrmaxuw : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), +"$Rxx32 = vrmaxuw($Rss32,$Ru32)", +S_3op_tc_3_SLOT23, TypeS_3op>, Enc_9773189 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11001011001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A4_vrmaxw : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), +"$Rxx32 = vrmaxw($Rss32,$Ru32)", +S_3op_tc_3_SLOT23, TypeS_3op>, Enc_9773189 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A4_vrminh : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), +"$Rxx32 = vrminh($Rss32,$Ru32)", +S_3op_tc_3_SLOT23, TypeS_3op>, Enc_9773189 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A4_vrminuh : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), +"$Rxx32 = vrminuh($Rss32,$Ru32)", +S_3op_tc_3_SLOT23, TypeS_3op>, Enc_9773189 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11001011001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A4_vrminuw : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), +"$Rxx32 = vrminuw($Rss32,$Ru32)", +S_3op_tc_3_SLOT23, TypeS_3op>, Enc_9773189 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11001011001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A4_vrminw : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Ru32), +"$Rxx32 = vrminw($Rss32,$Ru32)", +S_3op_tc_3_SLOT23, TypeS_3op>, Enc_9773189 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A5_ACS : HInst< +(outs DoubleRegs:$Rxx32, PredRegs:$Pe4), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32,$Pe4 = vacsh($Rss32,$Rtt32)", +M_tc_3stall_SLOT23, TypeM>, Enc_12822813, Requires<[HasV55T]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010101; +let isPredicateLate = 1; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def A5_vaddhubs : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = vaddhub($Rss32,$Rtt32):sat", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9277990, Requires<[HasV5T]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def A6_vminub_RdP : HInst< +(outs DoubleRegs:$Rdd32, PredRegs:$Pe4), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32,$Pe4 = vminub($Rtt32,$Rss32)", +M_tc_2_SLOT23, TypeM>, Enc_766909, Requires<[HasV62T]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010111; +let isPredicateLate = 1; +let prefersSlot3 = 1; +} +def C2_all8 : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4), +"$Pd4 = all8($Ps4)", +CR_tc_2early_SLOT23, TypeCR>, Enc_6975103 { +let Inst{13-2} = 0b000000000000; +let Inst{31-18} = 0b01101011101000; +} +def C2_and : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Pt4, PredRegs:$Ps4), +"$Pd4 = and($Pt4,$Ps4)", +CR_tc_2early_SLOT23, TypeCR>, Enc_8891794 { +let Inst{7-2} = 0b000000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011000000; +} +def C2_andn : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Pt4, PredRegs:$Ps4), +"$Pd4 = and($Pt4,!$Ps4)", +CR_tc_2early_SLOT23, TypeCR>, Enc_8891794 { +let Inst{7-2} = 0b000000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011011000; +} +def C2_any8 : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4), +"$Pd4 = any8($Ps4)", +CR_tc_2early_SLOT23, TypeCR>, Enc_6975103 { +let Inst{13-2} = 0b000000000000; +let Inst{31-18} = 0b01101011100000; +} +def C2_bitsclr : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = bitsclr($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111100; +} +def C2_bitsclri : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u6_0Imm:$Ii), +"$Pd4 = bitsclr($Rs32,#$Ii)", +S_2op_tc_2early_SLOT23, TypeS_2op>, Enc_14574598 { +let Inst{7-2} = 0b000000; +let Inst{31-21} = 0b10000101100; +} +def C2_bitsset : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = bitsset($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111010; +} +def C2_ccombinewf : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pu4) $Rdd32 = combine($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8202458, PredNewRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111101000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let BaseOpcode = "A2_combinew"; +} +def C2_ccombinewnewf : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pu4.new) $Rdd32 = combine($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8202458, PredNewRel { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111101000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isPredicatedNew = 1; +let BaseOpcode = "A2_combinew"; +} +def C2_ccombinewnewt : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pu4.new) $Rdd32 = combine($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8202458, PredNewRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11111101000; +let isPredicated = 1; +let isPredicatedNew = 1; +let BaseOpcode = "A2_combinew"; +} +def C2_ccombinewt : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pu4) $Rdd32 = combine($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_8202458, PredNewRel { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11111101000; +let isPredicated = 1; +let BaseOpcode = "A2_combinew"; +} +def C2_cmoveif : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, s32_0Imm:$Ii), +"if (!$Pu4) $Rd32 = #$Ii", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9487067, PredNewRel, ImmRegRel { +let Inst{13-13} = 0b0; +let Inst{20-20} = 0b0; +let Inst{31-23} = 0b011111101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_tfr"; +let InputType = "imm"; +let BaseOpcode = "A2_tfrsi"; +let isMoveImm = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 0; +} +def C2_cmoveit : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, s32_0Imm:$Ii), +"if ($Pu4) $Rd32 = #$Ii", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9487067, PredNewRel, ImmRegRel { +let Inst{13-13} = 0b0; +let Inst{20-20} = 0b0; +let Inst{31-23} = 0b011111100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "A2_tfr"; +let InputType = "imm"; +let BaseOpcode = "A2_tfrsi"; +let isMoveImm = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 0; +} +def C2_cmovenewif : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, s32_0Imm:$Ii), +"if (!$Pu4.new) $Rd32 = #$Ii", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9487067, PredNewRel, ImmRegRel { +let Inst{13-13} = 0b1; +let Inst{20-20} = 0b0; +let Inst{31-23} = 0b011111101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let CextOpcode = "A2_tfr"; +let InputType = "imm"; +let BaseOpcode = "A2_tfrsi"; +let isMoveImm = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 0; +} +def C2_cmovenewit : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, s32_0Imm:$Ii), +"if ($Pu4.new) $Rd32 = #$Ii", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9487067, PredNewRel, ImmRegRel { +let Inst{13-13} = 0b1; +let Inst{20-20} = 0b0; +let Inst{31-23} = 0b011111100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let isPredicatedNew = 1; +let CextOpcode = "A2_tfr"; +let InputType = "imm"; +let BaseOpcode = "A2_tfrsi"; +let isMoveImm = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 0; +} +def C2_cmpeq : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmp.eq($Rs32,$Rt32)", +ALU32_3op_tc_2early_SLOT0123, TypeALU32_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110010000; +let CextOpcode = "C2_cmpeq"; +let InputType = "reg"; +let isCommutable = 1; +let isCompare = 1; +} +def C2_cmpeqi : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Pd4 = cmp.eq($Rs32,#$Ii)", +ALU32_2op_tc_2early_SLOT0123, TypeALU32_2op>, Enc_16014536, ImmRegRel { +let Inst{4-2} = 0b000; +let Inst{31-22} = 0b0111010100; +let CextOpcode = "C2_cmpeq"; +let InputType = "imm"; +let isCompare = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +} +def C2_cmpeqp : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = cmp.eq($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010100; +let isCommutable = 1; +let isCompare = 1; +} +def C2_cmpgei : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, s8_0Imm:$Ii), +"$Pd4 = cmp.ge($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op> { +let isCompare = 1; +let isPseudo = 1; +} +def C2_cmpgeui : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u8_0Imm:$Ii), +"$Pd4 = cmp.geu($Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op> { +let isCompare = 1; +let isPseudo = 1; +} +def C2_cmpgt : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmp.gt($Rs32,$Rt32)", +ALU32_3op_tc_2early_SLOT0123, TypeALU32_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110010010; +let CextOpcode = "C2_cmpgt"; +let InputType = "reg"; +let isCompare = 1; +} +def C2_cmpgti : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Pd4 = cmp.gt($Rs32,#$Ii)", +ALU32_2op_tc_2early_SLOT0123, TypeALU32_2op>, Enc_16014536, ImmRegRel { +let Inst{4-2} = 0b000; +let Inst{31-22} = 0b0111010101; +let CextOpcode = "C2_cmpgt"; +let InputType = "imm"; +let isCompare = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +} +def C2_cmpgtp : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = cmp.gt($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b010000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010100; +let isCompare = 1; +} +def C2_cmpgtu : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmp.gtu($Rs32,$Rt32)", +ALU32_3op_tc_2early_SLOT0123, TypeALU32_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110010011; +let CextOpcode = "C2_cmpgtu"; +let InputType = "reg"; +let isCompare = 1; +} +def C2_cmpgtui : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u32_0Imm:$Ii), +"$Pd4 = cmp.gtu($Rs32,#$Ii)", +ALU32_2op_tc_2early_SLOT0123, TypeALU32_2op>, Enc_13249928, ImmRegRel { +let Inst{4-2} = 0b000; +let Inst{31-21} = 0b01110101100; +let CextOpcode = "C2_cmpgtu"; +let InputType = "imm"; +let isCompare = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 9; +let opExtentAlign = 0; +} +def C2_cmpgtup : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = cmp.gtu($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744 { +let Inst{7-2} = 0b100000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010100; +let isCompare = 1; +} +def C2_cmplt : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmp.lt($Rs32,$Rt32)", +PSEUDO, TypeALU32_3op> { +let isCompare = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def C2_cmpltu : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = cmp.ltu($Rs32,$Rt32)", +PSEUDO, TypeALU32_3op> { +let isCompare = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def C2_mask : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4), +"$Rdd32 = mask($Pt4)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_10328975 { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b0000; +let Inst{31-16} = 0b1000011000000000; +} +def C2_mux : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mux($Pu4,$Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_9626139 { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110100000; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "reg"; +} +def C2_muxii : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, s32_0Imm:$Ii, s8_0Imm:$II), +"$Rd32 = mux($Pu4,#$Ii,#$II)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_9093094 { +let Inst{31-25} = 0b0111101; +let hasNewValue = 1; +let opNewValue = 0; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def C2_muxir : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = mux($Pu4,$Rs32,#$Ii)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_10568534 { +let Inst{13-13} = 0b0; +let Inst{31-23} = 0b011100110; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def C2_muxri : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pu4, s32_0Imm:$Ii, IntRegs:$Rs32), +"$Rd32 = mux($Pu4,#$Ii,$Rs32)", +ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, Enc_10568534 { +let Inst{13-13} = 0b0; +let Inst{31-23} = 0b011100111; +let hasNewValue = 1; +let opNewValue = 0; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def C2_not : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4), +"$Pd4 = not($Ps4)", +CR_tc_2early_SLOT23, TypeCR>, Enc_6975103 { +let Inst{13-2} = 0b000000000000; +let Inst{31-18} = 0b01101011110000; +} +def C2_or : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Pt4, PredRegs:$Ps4), +"$Pd4 = or($Pt4,$Ps4)", +CR_tc_2early_SLOT23, TypeCR>, Enc_8891794 { +let Inst{7-2} = 0b000000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011001000; +} +def C2_orn : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Pt4, PredRegs:$Ps4), +"$Pd4 = or($Pt4,!$Ps4)", +CR_tc_2early_SLOT23, TypeCR>, Enc_8891794 { +let Inst{7-2} = 0b000000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011111000; +} +def C2_pxfer_map : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4), +"$Pd4 = $Ps4", +S_2op_tc_1_SLOT23, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def C2_tfrpr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Ps4), +"$Rd32 = $Ps4", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_11139981 { +let Inst{13-5} = 0b000000000; +let Inst{31-18} = 0b10001001010000; +let hasNewValue = 1; +let opNewValue = 0; +} +def C2_tfrrp : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32), +"$Pd4 = $Rs32", +S_2op_tc_2early_SLOT23, TypeS_2op>, Enc_4527648 { +let Inst{13-2} = 0b000000000000; +let Inst{31-21} = 0b10000101010; +} +def C2_vitpack : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Ps4, PredRegs:$Pt4), +"$Rd32 = vitpack($Ps4,$Pt4)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_6735062 { +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b10001001000000; +let hasNewValue = 1; +let opNewValue = 0; +} +def C2_vmux : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pu4, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmux($Pu4,$Rss32,$Rtt32)", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_7606379 { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010001000; +} +def C2_xor : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4), +"$Pd4 = xor($Ps4,$Pt4)", +CR_tc_2early_SLOT23, TypeCR>, Enc_8324216 { +let Inst{7-2} = 0b000000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011010000; +} +def C4_addipc : HInst< +(outs IntRegs:$Rd32), +(ins u32_0Imm:$Ii), +"$Rd32 = add(pc,#$Ii)", +CR_tc_2_SLOT3, TypeCR>, Enc_9554661 { +let Inst{6-5} = 0b00; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0110101001001001; +let hasNewValue = 1; +let opNewValue = 0; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def C4_and_and : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), +"$Pd4 = and($Ps4,and($Pt4,$Pu4))", +CR_tc_2early_SLOT23, TypeCR>, Enc_4631106 { +let Inst{5-2} = 0b0000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011000100; +} +def C4_and_andn : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), +"$Pd4 = and($Ps4,and($Pt4,!$Pu4))", +CR_tc_2early_SLOT23, TypeCR>, Enc_4631106 { +let Inst{5-2} = 0b0000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011100100; +} +def C4_and_or : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), +"$Pd4 = and($Ps4,or($Pt4,$Pu4))", +CR_tc_2early_SLOT23, TypeCR>, Enc_4631106 { +let Inst{5-2} = 0b0000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011001100; +} +def C4_and_orn : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), +"$Pd4 = and($Ps4,or($Pt4,!$Pu4))", +CR_tc_2early_SLOT23, TypeCR>, Enc_4631106 { +let Inst{5-2} = 0b0000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011101100; +} +def C4_cmplte : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = !cmp.gt($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b000100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110010010; +let CextOpcode = "C4_cmplte"; +let InputType = "reg"; +let isCompare = 1; +} +def C4_cmpltei : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Pd4 = !cmp.gt($Rs32,#$Ii)", +ALU32_2op_tc_2early_SLOT0123, TypeALU32_2op>, Enc_16014536, ImmRegRel { +let Inst{4-2} = 0b100; +let Inst{31-22} = 0b0111010101; +let CextOpcode = "C4_cmplte"; +let InputType = "imm"; +let isCompare = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +} +def C4_cmplteu : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = !cmp.gtu($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b000100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110010011; +let CextOpcode = "C4_cmplteu"; +let InputType = "reg"; +let isCompare = 1; +} +def C4_cmplteui : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u32_0Imm:$Ii), +"$Pd4 = !cmp.gtu($Rs32,#$Ii)", +ALU32_2op_tc_2early_SLOT0123, TypeALU32_2op>, Enc_13249928, ImmRegRel { +let Inst{4-2} = 0b100; +let Inst{31-21} = 0b01110101100; +let CextOpcode = "C4_cmplteu"; +let InputType = "imm"; +let isCompare = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 9; +let opExtentAlign = 0; +} +def C4_cmpneq : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = !cmp.eq($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_10157519, ImmRegRel { +let Inst{7-2} = 0b000100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110010000; +let CextOpcode = "C4_cmpneq"; +let InputType = "reg"; +let isCommutable = 1; +let isCompare = 1; +} +def C4_cmpneqi : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Pd4 = !cmp.eq($Rs32,#$Ii)", +ALU32_2op_tc_2early_SLOT0123, TypeALU32_2op>, Enc_16014536, ImmRegRel { +let Inst{4-2} = 0b100; +let Inst{31-22} = 0b0111010100; +let CextOpcode = "C4_cmpneq"; +let InputType = "imm"; +let isCompare = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +} +def C4_fastcorner9 : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4), +"$Pd4 = fastcorner9($Ps4,$Pt4)", +CR_tc_2early_SLOT23, TypeCR>, Enc_8324216 { +let Inst{7-2} = 0b100100; +let Inst{13-10} = 0b1000; +let Inst{31-18} = 0b01101011000000; +} +def C4_fastcorner9_not : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4), +"$Pd4 = !fastcorner9($Ps4,$Pt4)", +CR_tc_2early_SLOT23, TypeCR>, Enc_8324216 { +let Inst{7-2} = 0b100100; +let Inst{13-10} = 0b1000; +let Inst{31-18} = 0b01101011000100; +} +def C4_nbitsclr : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = !bitsclr($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111101; +} +def C4_nbitsclri : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u6_0Imm:$Ii), +"$Pd4 = !bitsclr($Rs32,#$Ii)", +S_2op_tc_2early_SLOT23, TypeS_2op>, Enc_14574598 { +let Inst{7-2} = 0b000000; +let Inst{31-21} = 0b10000101101; +} +def C4_nbitsset : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = !bitsset($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111011; +} +def C4_or_and : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), +"$Pd4 = or($Ps4,and($Pt4,$Pu4))", +CR_tc_2early_SLOT23, TypeCR>, Enc_4631106 { +let Inst{5-2} = 0b0000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011010100; +} +def C4_or_andn : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), +"$Pd4 = or($Ps4,and($Pt4,!$Pu4))", +CR_tc_2early_SLOT23, TypeCR>, Enc_4631106 { +let Inst{5-2} = 0b0000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011110100; +} +def C4_or_or : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), +"$Pd4 = or($Ps4,or($Pt4,$Pu4))", +CR_tc_2early_SLOT23, TypeCR>, Enc_4631106 { +let Inst{5-2} = 0b0000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011011100; +} +def C4_or_orn : HInst< +(outs PredRegs:$Pd4), +(ins PredRegs:$Ps4, PredRegs:$Pt4, PredRegs:$Pu4), +"$Pd4 = or($Ps4,or($Pt4,!$Pu4))", +CR_tc_2early_SLOT23, TypeCR>, Enc_4631106 { +let Inst{5-2} = 0b0000; +let Inst{13-10} = 0b0000; +let Inst{31-18} = 0b01101011111100; +} +def F2_conv_d2df : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = convert_d2df($Rss32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_13133231, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000011; +let Inst{31-21} = 0b10000000111; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_d2sf : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = convert_d2sf($Rss32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_3742184, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10001000010; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_df2d : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = convert_df2d($Rss32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_13133231, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10000000111; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_df2d_chop : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = convert_df2d($Rss32):chop", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_13133231, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10000000111; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_df2sf : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = convert_df2sf($Rss32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_3742184, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10001000000; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_df2ud : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = convert_df2ud($Rss32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_13133231, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10000000111; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_df2ud_chop : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = convert_df2ud($Rss32):chop", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_13133231, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000111; +let Inst{31-21} = 0b10000000111; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_df2uw : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = convert_df2uw($Rss32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_3742184, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10001000011; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_df2uw_chop : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = convert_df2uw($Rss32):chop", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_3742184, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10001000101; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_df2w : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = convert_df2w($Rss32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_3742184, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10001000100; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_df2w_chop : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = convert_df2w($Rss32):chop", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_3742184, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10001000111; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_sf2d : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = convert_sf2d($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4030179, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10000100100; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_sf2d_chop : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = convert_sf2d($Rs32):chop", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4030179, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10000100100; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_sf2df : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = convert_sf2df($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4030179, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10000100100; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_sf2ud : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = convert_sf2ud($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4030179, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000011; +let Inst{31-21} = 0b10000100100; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_sf2ud_chop : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = convert_sf2ud($Rs32):chop", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4030179, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000101; +let Inst{31-21} = 0b10000100100; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_sf2uw : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = convert_sf2uw($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4075554, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001011011; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_sf2uw_chop : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = convert_sf2uw($Rs32):chop", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4075554, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10001011011; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_sf2w : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = convert_sf2w($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4075554, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001011100; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_sf2w_chop : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = convert_sf2w($Rs32):chop", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4075554, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10001011100; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_ud2df : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = convert_ud2df($Rss32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_13133231, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000010; +let Inst{31-21} = 0b10000000111; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_ud2sf : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = convert_ud2sf($Rss32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_3742184, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10001000001; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_uw2df : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = convert_uw2df($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4030179, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b10000100100; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_uw2sf : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = convert_uw2sf($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4075554, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001011001; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_w2df : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = convert_w2df($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4030179, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000010; +let Inst{31-21} = 0b10000100100; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_conv_w2sf : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = convert_w2sf($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4075554, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001011010; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_dfclass : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, u5_0Imm:$Ii), +"$Pd4 = dfclass($Rss32,#$Ii)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_14400220, Requires<[HasV5T]> { +let Inst{4-2} = 0b100; +let Inst{13-10} = 0b0000; +let Inst{31-21} = 0b11011100100; +let isFP = 1; +let Uses = [USR]; +} +def F2_dfcmpeq : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = dfcmp.eq($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744, Requires<[HasV5T]> { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010111; +let isFP = 1; +let Uses = [USR]; +let isCompare = 1; +} +def F2_dfcmpge : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = dfcmp.ge($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744, Requires<[HasV5T]> { +let Inst{7-2} = 0b010000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010111; +let isFP = 1; +let Uses = [USR]; +let isCompare = 1; +} +def F2_dfcmpgt : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = dfcmp.gt($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744, Requires<[HasV5T]> { +let Inst{7-2} = 0b001000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010111; +let isFP = 1; +let Uses = [USR]; +let isCompare = 1; +} +def F2_dfcmpuo : HInst< +(outs PredRegs:$Pd4), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Pd4 = dfcmp.uo($Rss32,$Rtt32)", +ALU64_tc_2early_SLOT23, TypeALU64>, Enc_3831744, Requires<[HasV5T]> { +let Inst{7-2} = 0b011000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010010111; +let isFP = 1; +let Uses = [USR]; +let isCompare = 1; +} +def F2_dfimm_n : HInst< +(outs DoubleRegs:$Rdd32), +(ins u10_0Imm:$Ii), +"$Rdd32 = dfmake(#$Ii):neg", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_2702036, Requires<[HasV5T]> { +let Inst{20-16} = 0b00000; +let Inst{31-22} = 0b1101100101; +let prefersSlot3 = 1; +} +def F2_dfimm_p : HInst< +(outs DoubleRegs:$Rdd32), +(ins u10_0Imm:$Ii), +"$Rdd32 = dfmake(#$Ii):pos", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_2702036, Requires<[HasV5T]> { +let Inst{20-16} = 0b00000; +let Inst{31-22} = 0b1101100100; +let prefersSlot3 = 1; +} +def F2_sfadd : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = sfadd($Rs32,$Rt32)", +M_tc_3or4x_SLOT23, TypeM>, Enc_14071773, Requires<[HasV5T]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101011000; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +let isCommutable = 1; +} +def F2_sfclass : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Pd4 = sfclass($Rs32,#$Ii)", +S_2op_tc_2early_SLOT23, TypeS_2op>, Enc_2103742, Requires<[HasV5T]> { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10000101111; +let isFP = 1; +let Uses = [USR]; +} +def F2_sfcmpeq : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = sfcmp.eq($Rs32,$Rt32)", +ALU64_tc_2early_SLOT23, TypeS_3op>, Enc_10157519, Requires<[HasV5T]> { +let Inst{7-2} = 0b011000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111111; +let isFP = 1; +let Uses = [USR]; +let isCompare = 1; +} +def F2_sfcmpge : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = sfcmp.ge($Rs32,$Rt32)", +ALU64_tc_2early_SLOT23, TypeS_3op>, Enc_10157519, Requires<[HasV5T]> { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111111; +let isFP = 1; +let Uses = [USR]; +let isCompare = 1; +} +def F2_sfcmpgt : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = sfcmp.gt($Rs32,$Rt32)", +ALU64_tc_2early_SLOT23, TypeS_3op>, Enc_10157519, Requires<[HasV5T]> { +let Inst{7-2} = 0b100000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111111; +let isFP = 1; +let Uses = [USR]; +let isCompare = 1; +} +def F2_sfcmpuo : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = sfcmp.uo($Rs32,$Rt32)", +ALU64_tc_2early_SLOT23, TypeS_3op>, Enc_10157519, Requires<[HasV5T]> { +let Inst{7-2} = 0b001000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111111; +let isFP = 1; +let Uses = [USR]; +let isCompare = 1; +} +def F2_sffixupd : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = sffixupd($Rs32,$Rt32)", +M_tc_3or4x_SLOT23, TypeM>, Enc_14071773, Requires<[HasV5T]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101011110; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +} +def F2_sffixupn : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = sffixupn($Rs32,$Rt32)", +M_tc_3or4x_SLOT23, TypeM>, Enc_14071773, Requires<[HasV5T]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101011110; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +} +def F2_sffixupr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = sffixupr($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_4075554, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001011101; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +} +def F2_sffma : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += sfmpy($Rs32,$Rt32)", +M_tc_3or4x_acc_SLOT23, TypeM>, Enc_9223889, Requires<[HasV5T]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111000; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +let Constraints = "$Rx32 = $Rx32in"; +} +def F2_sffma_lib : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += sfmpy($Rs32,$Rt32):lib", +M_tc_3or4x_acc_SLOT23, TypeM>, Enc_9223889, Requires<[HasV5T]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111000; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +let Constraints = "$Rx32 = $Rx32in"; +} +def F2_sffma_sc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32, PredRegs:$Pu4), +"$Rx32 += sfmpy($Rs32,$Rt32,$Pu4):scale", +M_tc_3or4x_acc_SLOT23, TypeM>, Enc_15194851, Requires<[HasV5T]> { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111011; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +let Constraints = "$Rx32 = $Rx32in"; +} +def F2_sffms : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= sfmpy($Rs32,$Rt32)", +M_tc_3or4x_acc_SLOT23, TypeM>, Enc_9223889, Requires<[HasV5T]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111000; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +let Constraints = "$Rx32 = $Rx32in"; +} +def F2_sffms_lib : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= sfmpy($Rs32,$Rt32):lib", +M_tc_3or4x_acc_SLOT23, TypeM>, Enc_9223889, Requires<[HasV5T]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111000; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +let Constraints = "$Rx32 = $Rx32in"; +} +def F2_sfimm_n : HInst< +(outs IntRegs:$Rd32), +(ins u10_0Imm:$Ii), +"$Rd32 = sfmake(#$Ii):neg", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_9082775, Requires<[HasV5T]> { +let Inst{20-16} = 0b00000; +let Inst{31-22} = 0b1101011001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def F2_sfimm_p : HInst< +(outs IntRegs:$Rd32), +(ins u10_0Imm:$Ii), +"$Rd32 = sfmake(#$Ii):pos", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_9082775, Requires<[HasV5T]> { +let Inst{20-16} = 0b00000; +let Inst{31-22} = 0b1101011000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def F2_sfinvsqrta : HInst< +(outs IntRegs:$Rd32, PredRegs:$Pe4), +(ins IntRegs:$Rs32), +"$Rd32,$Pe4 = sfinvsqrta($Rs32)", +S_2op_tc_3or4x_SLOT23, TypeS_2op>, Enc_5718302, Requires<[HasV5T]> { +let Inst{13-7} = 0b0000000; +let Inst{31-21} = 0b10001011111; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let isPredicateLate = 1; +let prefersSlot3 = 1; +} +def F2_sfmax : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = sfmax($Rs32,$Rt32)", +M_tc_2_SLOT23, TypeM>, Enc_14071773, Requires<[HasV5T]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101011100; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_sfmin : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = sfmin($Rs32,$Rt32)", +M_tc_2_SLOT23, TypeM>, Enc_14071773, Requires<[HasV5T]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101011100; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def F2_sfmpy : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = sfmpy($Rs32,$Rt32)", +M_tc_3or4x_SLOT23, TypeM>, Enc_14071773, Requires<[HasV5T]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101011010; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +let isCommutable = 1; +} +def F2_sfrecipa : HInst< +(outs IntRegs:$Rd32, PredRegs:$Pe4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32,$Pe4 = sfrecipa($Rs32,$Rt32)", +M_tc_3or4x_SLOT23, TypeM>, Enc_5853469, Requires<[HasV5T]> { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101011111; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let isPredicateLate = 1; +let prefersSlot3 = 1; +} +def F2_sfsub : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = sfsub($Rs32,$Rt32)", +M_tc_3or4x_SLOT23, TypeM>, Enc_14071773, Requires<[HasV5T]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101011000; +let hasNewValue = 1; +let opNewValue = 0; +let isFP = 1; +let prefersSlot3 = 1; +let Uses = [USR]; +} +def J2_call : HInst< +(outs), +(ins a30_2Imm:$Ii), +"call $Ii", +J_tc_2early_SLOT23, TypeJ>, Enc_13453446, PredRel { +let Inst{0-0} = 0b0; +let Inst{31-25} = 0b0101101; +let isCall = 1; +let prefersSlot3 = 1; +let Uses = [R29]; +let Defs = [PC, R31]; +let BaseOpcode = "J2_call"; +let isPredicable = 1; +let hasSideEffects = 1; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 24; +let opExtentAlign = 2; +} +def J2_callf : HInst< +(outs), +(ins PredRegs:$Pu4, a30_2Imm:$Ii), +"if (!$Pu4) call $Ii", +J_tc_2early_SLOT23, TypeJ>, Enc_14868535, PredRel { +let Inst{0-0} = 0b0; +let Inst{12-10} = 0b000; +let Inst{21-21} = 0b1; +let Inst{31-24} = 0b01011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isCall = 1; +let prefersSlot3 = 1; +let Uses = [R29]; +let Defs = [PC, R31]; +let BaseOpcode = "J2_call"; +let hasSideEffects = 1; +let isTaken = Inst{12}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 17; +let opExtentAlign = 2; +} +def J2_callr : HInst< +(outs), +(ins IntRegs:$Rs32), +"callr $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_11704059 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-21} = 0b01010000101; +let cofMax1 = 1; +let isCall = 1; +let prefersSlot3 = 1; +let Uses = [R29]; +let Defs = [PC, R31]; +let hasSideEffects = 1; +} +def J2_callrf : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) callr $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_1928953 { +let Inst{7-0} = 0b00000000; +let Inst{13-10} = 0b0000; +let Inst{31-21} = 0b01010001001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let cofMax1 = 1; +let isCall = 1; +let prefersSlot3 = 1; +let Uses = [R29]; +let Defs = [PC, R31]; +let hasSideEffects = 1; +let isTaken = Inst{12}; +} +def J2_callrt : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) callr $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_1928953 { +let Inst{7-0} = 0b00000000; +let Inst{13-10} = 0b0000; +let Inst{31-21} = 0b01010001000; +let isPredicated = 1; +let cofMax1 = 1; +let isCall = 1; +let prefersSlot3 = 1; +let Uses = [R29]; +let Defs = [PC, R31]; +let hasSideEffects = 1; +let isTaken = Inst{12}; +} +def J2_callt : HInst< +(outs), +(ins PredRegs:$Pu4, a30_2Imm:$Ii), +"if ($Pu4) call $Ii", +J_tc_2early_SLOT23, TypeJ>, Enc_14868535, PredRel { +let Inst{0-0} = 0b0; +let Inst{12-10} = 0b000; +let Inst{21-21} = 0b0; +let Inst{31-24} = 0b01011101; +let isPredicated = 1; +let isCall = 1; +let prefersSlot3 = 1; +let Uses = [R29]; +let Defs = [PC, R31]; +let BaseOpcode = "J2_call"; +let hasSideEffects = 1; +let isTaken = Inst{12}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 17; +let opExtentAlign = 2; +} +def J2_endloop0 : HInst< +(outs), +(ins), +"endloop0", +PSEUDO, TypeJ> { +let Uses = [LC0, SA0]; +let Defs = [LC0, P3, PC, USR]; +let isPseudo = 1; +} +def J2_endloop01 : HInst< +(outs), +(ins), +"endloop01", +PSEUDO, TypeJ> { +let Uses = [LC0, LC1, SA0, SA1]; +let Defs = [LC0, LC1, P3, PC, USR]; +let isPseudo = 1; +} +def J2_endloop1 : HInst< +(outs), +(ins), +"endloop1", +PSEUDO, TypeJ> { +let Uses = [LC1, SA1]; +let Defs = [LC1, PC]; +let isPseudo = 1; +} +def J2_jump : HInst< +(outs), +(ins b30_2Imm:$Ii), +"jump $Ii", +J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, TypeJ>, Enc_13453446, PredNewRel { +let Inst{0-0} = 0b0; +let Inst{31-25} = 0b0101100; +let isTerminator = 1; +let isBranch = 1; +let Defs = [PC]; +let InputType = "imm"; +let BaseOpcode = "J2_jump"; +let isBarrier = 1; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 24; +let opExtentAlign = 2; +} +def J2_jumpf : HInst< +(outs), +(ins PredRegs:$Pu4, b30_2Imm:$Ii), +"if (!$Pu4) jump:nt $Ii", +J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, TypeJ>, Enc_14868535, PredNewRel { +let Inst{0-0} = 0b0; +let Inst{12-10} = 0b000; +let Inst{21-21} = 0b1; +let Inst{31-24} = 0b01011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let Defs = [PC]; +let InputType = "imm"; +let BaseOpcode = "J2_jump"; +let isTaken = Inst{12}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 17; +let opExtentAlign = 2; +} +def J2_jumpf_nopred_map : HInst< +(outs), +(ins PredRegs:$Pu4, b15_2Imm:$Ii), +"if (!$Pu4) jump $Ii", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def J2_jumpfnew : HInst< +(outs), +(ins PredRegs:$Pu4, b30_2Imm:$Ii), +"if (!$Pu4.new) jump:nt $Ii", +J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, TypeJ>, Enc_14868535, PredNewRel { +let Inst{0-0} = 0b0; +let Inst{12-10} = 0b010; +let Inst{21-21} = 0b1; +let Inst{31-24} = 0b01011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let InputType = "imm"; +let BaseOpcode = "J2_jump"; +let isTaken = Inst{12}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 17; +let opExtentAlign = 2; +} +def J2_jumpfnewpt : HInst< +(outs), +(ins PredRegs:$Pu4, b30_2Imm:$Ii), +"if (!$Pu4.new) jump:t $Ii", +J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, TypeJ>, Enc_14868535, PredNewRel { +let Inst{0-0} = 0b0; +let Inst{12-10} = 0b110; +let Inst{21-21} = 0b1; +let Inst{31-24} = 0b01011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let InputType = "imm"; +let BaseOpcode = "J2_jump"; +let isTaken = Inst{12}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 17; +let opExtentAlign = 2; +} +def J2_jumpfpt : HInst< +(outs), +(ins PredRegs:$Pu4, b30_2Imm:$Ii), +"if (!$Pu4) jump:t $Ii", +J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, TypeJ>, Enc_14868535, Requires<[HasV60T]>, PredNewRel { +let Inst{0-0} = 0b0; +let Inst{12-10} = 0b100; +let Inst{21-21} = 0b1; +let Inst{31-24} = 0b01011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let Defs = [PC]; +let InputType = "imm"; +let BaseOpcode = "J2_jump"; +let isTaken = Inst{12}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 17; +let opExtentAlign = 2; +} +def J2_jumpr : HInst< +(outs), +(ins IntRegs:$Rs32), +"jumpr $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_11704059, PredNewRel { +let Inst{13-0} = 0b00000000000000; +let Inst{31-21} = 0b01010010100; +let isTerminator = 1; +let isIndirectBranch = 1; +let isBranch = 1; +let cofMax1 = 1; +let Defs = [PC]; +let InputType = "reg"; +let BaseOpcode = "J2_jumpr"; +let isBarrier = 1; +let isPredicable = 1; +} +def J2_jumprf : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) jumpr:nt $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_1928953, PredNewRel { +let Inst{7-0} = 0b00000000; +let Inst{13-10} = 0b0000; +let Inst{31-21} = 0b01010011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let isBranch = 1; +let cofMax1 = 1; +let Defs = [PC]; +let InputType = "reg"; +let BaseOpcode = "J2_jumpr"; +let isTaken = Inst{12}; +} +def J2_jumprf_nopred_map : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) jumpr $Rs32", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def J2_jumprfnew : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4.new) jumpr:nt $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_1928953, PredNewRel { +let Inst{7-0} = 0b00000000; +let Inst{13-10} = 0b0010; +let Inst{31-21} = 0b01010011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let isBranch = 1; +let cofMax1 = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let InputType = "reg"; +let BaseOpcode = "J2_jumpr"; +let isTaken = Inst{12}; +} +def J2_jumprfnewpt : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4.new) jumpr:t $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_1928953, PredNewRel { +let Inst{7-0} = 0b00000000; +let Inst{13-10} = 0b0110; +let Inst{31-21} = 0b01010011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let isBranch = 1; +let cofMax1 = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let InputType = "reg"; +let BaseOpcode = "J2_jumpr"; +let isTaken = Inst{12}; +} +def J2_jumprfpt : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if (!$Pu4) jumpr:t $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_1928953, Requires<[HasV60T]>, PredNewRel { +let Inst{7-0} = 0b00000000; +let Inst{13-10} = 0b0100; +let Inst{31-21} = 0b01010011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let isBranch = 1; +let cofMax1 = 1; +let Defs = [PC]; +let InputType = "reg"; +let BaseOpcode = "J2_jumpr"; +let isTaken = Inst{12}; +} +def J2_jumprgtez : HInst< +(outs), +(ins IntRegs:$Rs32, b13_2Imm:$Ii), +"if ($Rs32>=#0) jump:nt $Ii", +CR_tc_2early_SLOT3, TypeCR>, Enc_12477789 { +let Inst{0-0} = 0b0; +let Inst{12-12} = 0b0; +let Inst{31-22} = 0b0110000101; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let isTaken = Inst{12}; +} +def J2_jumprgtezpt : HInst< +(outs), +(ins IntRegs:$Rs32, b13_2Imm:$Ii), +"if ($Rs32>=#0) jump:t $Ii", +CR_tc_2early_SLOT3, TypeCR>, Enc_12477789 { +let Inst{0-0} = 0b0; +let Inst{12-12} = 0b1; +let Inst{31-22} = 0b0110000101; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let isTaken = Inst{12}; +} +def J2_jumprltez : HInst< +(outs), +(ins IntRegs:$Rs32, b13_2Imm:$Ii), +"if ($Rs32<=#0) jump:nt $Ii", +CR_tc_2early_SLOT3, TypeCR>, Enc_12477789 { +let Inst{0-0} = 0b0; +let Inst{12-12} = 0b0; +let Inst{31-22} = 0b0110000111; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let isTaken = Inst{12}; +} +def J2_jumprltezpt : HInst< +(outs), +(ins IntRegs:$Rs32, b13_2Imm:$Ii), +"if ($Rs32<=#0) jump:t $Ii", +CR_tc_2early_SLOT3, TypeCR>, Enc_12477789 { +let Inst{0-0} = 0b0; +let Inst{12-12} = 0b1; +let Inst{31-22} = 0b0110000111; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let isTaken = Inst{12}; +} +def J2_jumprnz : HInst< +(outs), +(ins IntRegs:$Rs32, b13_2Imm:$Ii), +"if ($Rs32==#0) jump:nt $Ii", +CR_tc_2early_SLOT3, TypeCR>, Enc_12477789 { +let Inst{0-0} = 0b0; +let Inst{12-12} = 0b0; +let Inst{31-22} = 0b0110000110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let isTaken = Inst{12}; +} +def J2_jumprnzpt : HInst< +(outs), +(ins IntRegs:$Rs32, b13_2Imm:$Ii), +"if ($Rs32==#0) jump:t $Ii", +CR_tc_2early_SLOT3, TypeCR>, Enc_12477789 { +let Inst{0-0} = 0b0; +let Inst{12-12} = 0b1; +let Inst{31-22} = 0b0110000110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let isTaken = Inst{12}; +} +def J2_jumprt : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) jumpr:nt $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_1928953, PredNewRel { +let Inst{7-0} = 0b00000000; +let Inst{13-10} = 0b0000; +let Inst{31-21} = 0b01010011010; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let isBranch = 1; +let cofMax1 = 1; +let Defs = [PC]; +let InputType = "reg"; +let BaseOpcode = "J2_jumpr"; +let isTaken = Inst{12}; +} +def J2_jumprt_nopred_map : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) jumpr $Rs32", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def J2_jumprtnew : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4.new) jumpr:nt $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_1928953, PredNewRel { +let Inst{7-0} = 0b00000000; +let Inst{13-10} = 0b0010; +let Inst{31-21} = 0b01010011010; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let isBranch = 1; +let cofMax1 = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let InputType = "reg"; +let BaseOpcode = "J2_jumpr"; +let isTaken = Inst{12}; +} +def J2_jumprtnewpt : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4.new) jumpr:t $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_1928953, PredNewRel { +let Inst{7-0} = 0b00000000; +let Inst{13-10} = 0b0110; +let Inst{31-21} = 0b01010011010; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let isBranch = 1; +let cofMax1 = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let InputType = "reg"; +let BaseOpcode = "J2_jumpr"; +let isTaken = Inst{12}; +} +def J2_jumprtpt : HInst< +(outs), +(ins PredRegs:$Pu4, IntRegs:$Rs32), +"if ($Pu4) jumpr:t $Rs32", +J_tc_2early_SLOT2, TypeJ>, Enc_1928953, Requires<[HasV60T]>, PredNewRel { +let Inst{7-0} = 0b00000000; +let Inst{13-10} = 0b0100; +let Inst{31-21} = 0b01010011010; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let isBranch = 1; +let cofMax1 = 1; +let Defs = [PC]; +let InputType = "reg"; +let BaseOpcode = "J2_jumpr"; +let isTaken = Inst{12}; +} +def J2_jumprz : HInst< +(outs), +(ins IntRegs:$Rs32, b13_2Imm:$Ii), +"if ($Rs32!=#0) jump:nt $Ii", +CR_tc_2early_SLOT3, TypeCR>, Enc_12477789 { +let Inst{0-0} = 0b0; +let Inst{12-12} = 0b0; +let Inst{31-22} = 0b0110000100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let isTaken = Inst{12}; +} +def J2_jumprzpt : HInst< +(outs), +(ins IntRegs:$Rs32, b13_2Imm:$Ii), +"if ($Rs32!=#0) jump:t $Ii", +CR_tc_2early_SLOT3, TypeCR>, Enc_12477789 { +let Inst{0-0} = 0b0; +let Inst{12-12} = 0b1; +let Inst{31-22} = 0b0110000100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let isTaken = Inst{12}; +} +def J2_jumpt : HInst< +(outs), +(ins PredRegs:$Pu4, b30_2Imm:$Ii), +"if ($Pu4) jump:nt $Ii", +J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, TypeJ>, Enc_14868535, PredNewRel { +let Inst{0-0} = 0b0; +let Inst{12-10} = 0b000; +let Inst{21-21} = 0b0; +let Inst{31-24} = 0b01011100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let Defs = [PC]; +let InputType = "imm"; +let BaseOpcode = "J2_jump"; +let isTaken = Inst{12}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 17; +let opExtentAlign = 2; +} +def J2_jumpt_nopred_map : HInst< +(outs), +(ins PredRegs:$Pu4, b15_2Imm:$Ii), +"if ($Pu4) jump $Ii", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def J2_jumptnew : HInst< +(outs), +(ins PredRegs:$Pu4, b30_2Imm:$Ii), +"if ($Pu4.new) jump:nt $Ii", +J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, TypeJ>, Enc_14868535, PredNewRel { +let Inst{0-0} = 0b0; +let Inst{12-10} = 0b010; +let Inst{21-21} = 0b0; +let Inst{31-24} = 0b01011100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let InputType = "imm"; +let BaseOpcode = "J2_jump"; +let isTaken = Inst{12}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 17; +let opExtentAlign = 2; +} +def J2_jumptnewpt : HInst< +(outs), +(ins PredRegs:$Pu4, b30_2Imm:$Ii), +"if ($Pu4.new) jump:t $Ii", +J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, TypeJ>, Enc_14868535, PredNewRel { +let Inst{0-0} = 0b0; +let Inst{12-10} = 0b110; +let Inst{21-21} = 0b0; +let Inst{31-24} = 0b01011100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Defs = [PC]; +let InputType = "imm"; +let BaseOpcode = "J2_jump"; +let isTaken = Inst{12}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 17; +let opExtentAlign = 2; +} +def J2_jumptpt : HInst< +(outs), +(ins PredRegs:$Pu4, b30_2Imm:$Ii), +"if ($Pu4) jump:t $Ii", +J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, TypeJ>, Enc_14868535, Requires<[HasV60T]>, PredNewRel { +let Inst{0-0} = 0b0; +let Inst{12-10} = 0b100; +let Inst{21-21} = 0b0; +let Inst{31-24} = 0b01011100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let Defs = [PC]; +let InputType = "imm"; +let BaseOpcode = "J2_jump"; +let isTaken = Inst{12}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 17; +let opExtentAlign = 2; +} +def J2_loop0i : HInst< +(outs), +(ins b30_2Imm:$Ii, u10_0Imm:$II), +"loop0($Ii,#$II)", +CR_tc_3x_SLOT3, TypeCR>, Enc_9939385 { +let Inst{2-2} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01101001000; +let Defs = [LC0, SA0, USR]; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 2; +} +def J2_loop0r : HInst< +(outs), +(ins b30_2Imm:$Ii, IntRegs:$Rs32), +"loop0($Ii,$Rs32)", +CR_tc_3x_SLOT3, TypeCR>, Enc_5790679 { +let Inst{2-0} = 0b000; +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01100000000; +let Defs = [LC0, SA0, USR]; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 2; +} +def J2_loop1i : HInst< +(outs), +(ins b30_2Imm:$Ii, u10_0Imm:$II), +"loop1($Ii,#$II)", +CR_tc_3x_SLOT3, TypeCR>, Enc_9939385 { +let Inst{2-2} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01101001001; +let Defs = [LC1, SA1]; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 2; +} +def J2_loop1r : HInst< +(outs), +(ins b30_2Imm:$Ii, IntRegs:$Rs32), +"loop1($Ii,$Rs32)", +CR_tc_3x_SLOT3, TypeCR>, Enc_5790679 { +let Inst{2-0} = 0b000; +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01100000001; +let Defs = [LC1, SA1]; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 2; +} +def J2_pause : HInst< +(outs), +(ins u8_0Imm:$Ii), +"pause(#$Ii)", +J_tc_2early_SLOT2, TypeJ>, Enc_8732960 { +let Inst{1-0} = 0b00; +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0101010001000000; +let isSolo = 1; +} +def J2_ploop1si : HInst< +(outs), +(ins b30_2Imm:$Ii, u10_0Imm:$II), +"p3 = sp1loop0($Ii,#$II)", +CR_tc_2early_SLOT3, TypeCR>, Enc_9939385 { +let Inst{2-2} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01101001101; +let isPredicateLate = 1; +let Defs = [LC0, P3, SA0, USR]; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 2; +} +def J2_ploop1sr : HInst< +(outs), +(ins b30_2Imm:$Ii, IntRegs:$Rs32), +"p3 = sp1loop0($Ii,$Rs32)", +CR_tc_2early_SLOT3, TypeCR>, Enc_5790679 { +let Inst{2-0} = 0b000; +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01100000101; +let isPredicateLate = 1; +let Defs = [LC0, P3, SA0, USR]; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 2; +} +def J2_ploop2si : HInst< +(outs), +(ins b30_2Imm:$Ii, u10_0Imm:$II), +"p3 = sp2loop0($Ii,#$II)", +CR_tc_2early_SLOT3, TypeCR>, Enc_9939385 { +let Inst{2-2} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01101001110; +let isPredicateLate = 1; +let Defs = [LC0, P3, SA0, USR]; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 2; +} +def J2_ploop2sr : HInst< +(outs), +(ins b30_2Imm:$Ii, IntRegs:$Rs32), +"p3 = sp2loop0($Ii,$Rs32)", +CR_tc_2early_SLOT3, TypeCR>, Enc_5790679 { +let Inst{2-0} = 0b000; +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01100000110; +let isPredicateLate = 1; +let Defs = [LC0, P3, SA0, USR]; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 2; +} +def J2_ploop3si : HInst< +(outs), +(ins b30_2Imm:$Ii, u10_0Imm:$II), +"p3 = sp3loop0($Ii,#$II)", +CR_tc_2early_SLOT3, TypeCR>, Enc_9939385 { +let Inst{2-2} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01101001111; +let isPredicateLate = 1; +let Defs = [LC0, P3, SA0, USR]; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 2; +} +def J2_ploop3sr : HInst< +(outs), +(ins b30_2Imm:$Ii, IntRegs:$Rs32), +"p3 = sp3loop0($Ii,$Rs32)", +CR_tc_2early_SLOT3, TypeCR>, Enc_5790679 { +let Inst{2-0} = 0b000; +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01100000111; +let isPredicateLate = 1; +let Defs = [LC0, P3, SA0, USR]; +let isExtendable = 1; +let opExtendable = 0; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 2; +} +def J2_trap0 : HInst< +(outs), +(ins u8_0Imm:$Ii), +"trap0(#$Ii)", +J_tc_2early_SLOT2, TypeJ>, Enc_8732960 { +let Inst{1-0} = 0b00; +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0101010000000000; +let isSolo = 1; +} +def J4_cmpeq_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (!cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeq_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (!cmp.eq($Ns8.new,$Rt32)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeq_fp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b00; +let Inst{31-22} = 0b0001010001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqp0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeq_fp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,$Rt16); if (!p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b10; +let Inst{31-22} = 0b0001010001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqp0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeq_fp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-22} = 0b0001010001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqp1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeq_fp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,$Rt16); if (!p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b11; +let Inst{31-22} = 0b0001010001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqp1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeq_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (cmp.eq($Ns8.new,$Rt32)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeq_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (cmp.eq($Ns8.new,$Rt32)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeq_tp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b00; +let Inst{31-22} = 0b0001010000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqp0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeq_tp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,$Rt16); if (p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b10; +let Inst{31-22} = 0b0001010000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqp0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeq_tp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-22} = 0b0001010000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqp1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeq_tp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,$Rt16); if (p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b11; +let Inst{31-22} = 0b0001010000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqp1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqi_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (!cmp.eq($Ns8.new,#$II)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqi"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeqi_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (!cmp.eq($Ns8.new,#$II)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqi"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeqi_fp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001000001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqi_fp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,#$II); if (!p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001000001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqi_fp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001001001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqi_fp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,#$II); if (!p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001001001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqi_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (cmp.eq($Ns8.new,#$II)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqi"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeqi_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (cmp.eq($Ns8.new,#$II)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqi"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeqi_tp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001000000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqi_tp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,#$II); if (p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001000000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqi_tp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001001000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqi_tp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,#$II); if (p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001001000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqn1_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), +"if (!cmp.eq($Ns8.new,#$n1)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4359901, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010011001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqn1r"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeqn1_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), +"if (!cmp.eq($Ns8.new,#$n1)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_8612939, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010011001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqn1r"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeqn1_fp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_844699, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000000; +let Inst{31-22} = 0b0001000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqn1p0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqn1_fp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,#$n1); if (!p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_5338033, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100000; +let Inst{31-22} = 0b0001000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqn1p0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqn1_fp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14150875, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000000; +let Inst{31-22} = 0b0001001111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqn1p1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqn1_fp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,#$n1); if (!p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_15450971, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100000; +let Inst{31-22} = 0b0001001111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqn1p1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqn1_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), +"if (cmp.eq($Ns8.new,#$n1)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_14998517, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010011000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqn1r"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeqn1_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), +"if (cmp.eq($Ns8.new,#$n1)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_11544269, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010011000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpeqn1r"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpeqn1_tp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_5401217, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000000; +let Inst{31-22} = 0b0001000110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqn1p0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqn1_tp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p0 = cmp.eq($Rs16,#$n1); if (p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_12419313, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100000; +let Inst{31-22} = 0b0001000110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpeqn1p0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqn1_tp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_4684887, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000000; +let Inst{31-22} = 0b0001001110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqn1p1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpeqn1_tp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p1 = cmp.eq($Rs16,#$n1); if (p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_220949, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100000; +let Inst{31-22} = 0b0001001110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpeqn1p1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgt_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (!cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgt_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (!cmp.gt($Ns8.new,$Rt32)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgt_fp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b00; +let Inst{31-22} = 0b0001010011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtp0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgt_fp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,$Rt16); if (!p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b10; +let Inst{31-22} = 0b0001010011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtp0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgt_fp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-22} = 0b0001010011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtp1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgt_fp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,$Rt16); if (!p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b11; +let Inst{31-22} = 0b0001010011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtp1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgt_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (cmp.gt($Ns8.new,$Rt32)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgt_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (cmp.gt($Ns8.new,$Rt32)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgt_tp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b00; +let Inst{31-22} = 0b0001010010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtp0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgt_tp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,$Rt16); if (p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b10; +let Inst{31-22} = 0b0001010010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtp0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgt_tp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-22} = 0b0001010010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtp1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgt_tp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,$Rt16); if (p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b11; +let Inst{31-22} = 0b0001010010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtp1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgti_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (!cmp.gt($Ns8.new,#$II)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtir"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgti_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (!cmp.gt($Ns8.new,#$II)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtir"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgti_fp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001000011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgti_fp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,#$II); if (!p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001000011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgti_fp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001001011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgti_fp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,#$II); if (!p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001001011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgti_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (cmp.gt($Ns8.new,#$II)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtir"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgti_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (cmp.gt($Ns8.new,#$II)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtir"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgti_tp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001000010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgti_tp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,#$II); if (p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001000010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgti_tp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001001010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgti_tp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,#$II); if (p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001001010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtn1_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), +"if (!cmp.gt($Ns8.new,#$n1)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_8674673, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtn1r"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtn1_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), +"if (!cmp.gt($Ns8.new,#$n1)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15763937, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtn1r"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtn1_fp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_5915771, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000001; +let Inst{31-22} = 0b0001000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtn1p0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtn1_fp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,#$n1); if (!p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7315939, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100001; +let Inst{31-22} = 0b0001000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtn1p0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtn1_fp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7785569, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000001; +let Inst{31-22} = 0b0001001111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtn1p1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtn1_fp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,#$n1); if (!p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_10968391, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100001; +let Inst{31-22} = 0b0001001111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtn1p1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtn1_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), +"if (cmp.gt($Ns8.new,#$n1)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_364753, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010011010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtn1r"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtn1_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, n1Const:$n1, b30_2Imm:$Ii), +"if (cmp.gt($Ns8.new,#$n1)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_8479583, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010011010; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtn1r"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtn1_tp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_2428539, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000001; +let Inst{31-22} = 0b0001000110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtn1p0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtn1_tp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p0 = cmp.gt($Rs16,#$n1); if (p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_8919369, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100001; +let Inst{31-22} = 0b0001000110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtn1p0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtn1_tp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_8577055, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000001; +let Inst{31-22} = 0b0001001110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtn1p1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtn1_tp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, n1Const:$n1, b30_2Imm:$Ii), +"p1 = cmp.gt($Rs16,#$n1); if (p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14530015, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100001; +let Inst{31-22} = 0b0001001110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtn1p1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtu_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (!cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtur"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtu_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (!cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtur"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtu_fp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b00; +let Inst{31-22} = 0b0001010101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtup0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtu_fp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.gtu($Rs16,$Rt16); if (!p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b10; +let Inst{31-22} = 0b0001010101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtup0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtu_fp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-22} = 0b0001010101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtup1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtu_fp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.gtu($Rs16,$Rt16); if (!p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b11; +let Inst{31-22} = 0b0001010101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtup1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtu_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (cmp.gtu($Ns8.new,$Rt32)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtur"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtu_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, IntRegs:$Rt32, b30_2Imm:$Ii), +"if (cmp.gtu($Ns8.new,$Rt32)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_15140689, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtur"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtu_tp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b00; +let Inst{31-22} = 0b0001010100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtup0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtu_tp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p0 = cmp.gtu($Rs16,$Rt16); if (p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b10; +let Inst{31-22} = 0b0001010100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtup0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtu_tp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-22} = 0b0001010100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtup1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtu_tp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, GeneralSubRegs:$Rt16, b30_2Imm:$Ii), +"p1 = cmp.gtu($Rs16,$Rt16); if (p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_14264243, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b11; +let Inst{31-22} = 0b0001010100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtup1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtui_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (!cmp.gtu($Ns8.new,#$II)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtuir"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtui_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (!cmp.gtu($Ns8.new,#$II)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtuir"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtui_fp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtuip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtui_fp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.gtu($Rs16,#$II); if (!p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtuip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtui_fp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001001101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtuip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtui_fp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.gtu($Rs16,#$II); if (!p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001001101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtuip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtui_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (cmp.gtu($Ns8.new,#$II)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtuir"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtui_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, u5_0Imm:$II, b30_2Imm:$Ii), +"if (cmp.gtu($Ns8.new,#$II)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_4397470, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpgtuir"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_cmpgtui_tp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001000100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtuip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtui_tp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p0 = cmp.gtu($Rs16,#$II); if (p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001000100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let BaseOpcode = "J4_cmpgtuip0"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtui_tp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-22} = 0b0001001100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtuip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmpgtui_tp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u5_0Imm:$II, b30_2Imm:$Ii), +"p1 = cmp.gtu($Rs16,#$II); if (p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_7305764, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-22} = 0b0001001100; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let BaseOpcode = "J4_cmpgtuip1"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_cmplt_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), +"if (!cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_6730375, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpltr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 1; +} +def J4_cmplt_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), +"if (!cmp.gt($Rt32,$Ns8.new)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_6730375, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpltr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 1; +} +def J4_cmplt_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), +"if (cmp.gt($Rt32,$Ns8.new)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_6730375, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpltr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 1; +} +def J4_cmplt_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), +"if (cmp.gt($Rt32,$Ns8.new)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_6730375, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010000110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpltr"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 1; +} +def J4_cmpltu_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), +"if (!cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_6730375, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010001001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpltur"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 1; +} +def J4_cmpltu_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), +"if (!cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_6730375, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010001001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpltur"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 1; +} +def J4_cmpltu_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), +"if (cmp.gtu($Rt32,$Ns8.new)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_6730375, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b0; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010001000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpltur"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 1; +} +def J4_cmpltu_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Rt32, IntRegs:$Ns8, b30_2Imm:$Ii), +"if (cmp.gtu($Rt32,$Ns8.new)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_6730375, PredRel { +let Inst{0-0} = 0b0; +let Inst{13-13} = 0b1; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010001000; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let BaseOpcode = "J4_cmpltur"; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 1; +} +def J4_hintjumpr : HInst< +(outs), +(ins IntRegs:$Rs32), +"hintjr($Rs32)", +J_tc_2early_SLOT2, TypeJ>, Enc_11704059 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-21} = 0b01010010101; +let isTerminator = 1; +let isIndirectBranch = 1; +let isBranch = 1; +let cofMax1 = 1; +} +def J4_jumpseti : HInst< +(outs GeneralSubRegs:$Rd16), +(ins u6_0Imm:$II, b30_2Imm:$Ii), +"$Rd16 = #$II ; jump $Ii", +COMPOUND, TypeCJ>, Enc_4834775 { +let Inst{0-0} = 0b0; +let Inst{31-22} = 0b0001011000; +let hasNewValue = 1; +let opNewValue = 0; +let isTerminator = 1; +let isBranch = 1; +let Defs = [PC]; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_jumpsetr : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), +"$Rd16 = $Rs16 ; jump $Ii", +COMPOUND, TypeCJ>, Enc_2639299 { +let Inst{0-0} = 0b0; +let Inst{13-12} = 0b00; +let Inst{31-22} = 0b0001011100; +let hasNewValue = 1; +let opNewValue = 0; +let isTerminator = 1; +let isBranch = 1; +let Defs = [PC]; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_tstbit0_f_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, b30_2Imm:$Ii), +"if (!tstbit($Ns8.new,#0)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_1898420 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_tstbit0_f_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, b30_2Imm:$Ii), +"if (!tstbit($Ns8.new,#0)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_1898420 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_tstbit0_fp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), +"p0 = tstbit($Rs16,#0); if (!p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_12829314 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000011; +let Inst{31-22} = 0b0001000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_tstbit0_fp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), +"p0 = tstbit($Rs16,#0); if (!p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_12829314 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100011; +let Inst{31-22} = 0b0001000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_tstbit0_fp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), +"p1 = tstbit($Rs16,#0); if (!p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_12829314 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000011; +let Inst{31-22} = 0b0001001111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_tstbit0_fp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), +"p1 = tstbit($Rs16,#0); if (!p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_12829314 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100011; +let Inst{31-22} = 0b0001001111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_tstbit0_t_jumpnv_nt : HInst< +(outs), +(ins IntRegs:$Ns8, b30_2Imm:$Ii), +"if (tstbit($Ns8.new,#0)) jump:nt $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_1898420 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_tstbit0_t_jumpnv_t : HInst< +(outs), +(ins IntRegs:$Ns8, b30_2Imm:$Ii), +"if (tstbit($Ns8.new,#0)) jump:t $Ii", +NCJ_tc_3or4stall_SLOT0, TypeNCJ>, Enc_1898420 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100000; +let Inst{19-19} = 0b0; +let Inst{31-22} = 0b0010010110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let cofMax1 = 1; +let isNewValue = 1; +let Defs = [PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +let opNewValue = 0; +} +def J4_tstbit0_tp0_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), +"p0 = tstbit($Rs16,#0); if (p0.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_12829314 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000011; +let Inst{31-22} = 0b0001000110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_tstbit0_tp0_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), +"p0 = tstbit($Rs16,#0); if (p0.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_12829314 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100011; +let Inst{31-22} = 0b0001000110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P0]; +let Defs = [P0, PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_tstbit0_tp1_jump_nt : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), +"p1 = tstbit($Rs16,#0); if (p1.new) jump:nt $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_12829314 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b000011; +let Inst{31-22} = 0b0001001110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def J4_tstbit0_tp1_jump_t : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, b30_2Imm:$Ii), +"p1 = tstbit($Rs16,#0); if (p1.new) jump:t $Ii", +COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, Enc_12829314 { +let Inst{0-0} = 0b0; +let Inst{13-8} = 0b100011; +let Inst{31-22} = 0b0001001110; +let isPredicated = 1; +let isTerminator = 1; +let isBranch = 1; +let isPredicatedNew = 1; +let Uses = [P1]; +let Defs = [P1, PC]; +let isTaken = Inst{13}; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 2; +} +def L2_deallocframe : HInst< +(outs), +(ins), +"deallocframe", +LD_tc_ld_SLOT01, TypeLD>, Enc_0 { +let Inst{4-0} = 0b11110; +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10010000000; +let Inst{20-16} = 0b11110; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let Uses = [R30]; +let Defs = [R29, R30, R31]; +} +def L2_loadalignb_io : HInst< +(outs DoubleRegs:$Ryy32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s32_0Imm:$Ii), +"$Ryy32 = memb_fifo($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_449439 { +let Inst{24-21} = 0b0100; +let Inst{31-27} = 0b10010; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 0; +let Constraints = "$Ryy32 = $Ryy32in"; +} +def L2_loadalignb_pbr : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), +"$Ryy32 = memb_fifo($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12261611 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011110100; +let accessSize = ByteAccess; +let mayLoad = 1; +let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; +} +def L2_loadalignb_pci : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), +"$Ryy32 = memb_fifo($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_971347 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011000100; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; +} +def L2_loadalignb_pcr : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), +"$Ryy32 = memb_fifo($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_12261611 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011000100; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; +} +def L2_loadalignb_pi : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_0Imm:$Ii), +"$Ryy32 = memb_fifo($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_6372758 { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011010100; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; +} +def L2_loadalignb_pr : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), +"$Ryy32 = memb_fifo($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12261611 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011100100; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; +} +def L2_loadalignb_zomap : HInst< +(outs DoubleRegs:$Ryy32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32), +"$Ryy32 = memb_fifo($Rs32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let Constraints = "$Ryy32 = $Ryy32in"; +} +def L2_loadalignh_io : HInst< +(outs DoubleRegs:$Ryy32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32, s31_1Imm:$Ii), +"$Ryy32 = memh_fifo($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_11930027 { +let Inst{24-21} = 0b0010; +let Inst{31-27} = 0b10010; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +let Constraints = "$Ryy32 = $Ryy32in"; +} +def L2_loadalignh_pbr : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), +"$Ryy32 = memh_fifo($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12261611 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011110010; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; +} +def L2_loadalignh_pci : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), +"$Ryy32 = memh_fifo($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_1971351 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011000010; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; +} +def L2_loadalignh_pcr : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), +"$Ryy32 = memh_fifo($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_12261611 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011000010; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; +} +def L2_loadalignh_pi : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, s4_1Imm:$Ii), +"$Ryy32 = memh_fifo($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_3372766 { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011010010; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; +} +def L2_loadalignh_pr : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Rx32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rx32in, ModRegs:$Mu2), +"$Ryy32 = memh_fifo($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12261611 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011100010; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Ryy32 = $Ryy32in, $Rx32 = $Rx32in"; +} +def L2_loadalignh_zomap : HInst< +(outs DoubleRegs:$Ryy32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rs32), +"$Ryy32 = memh_fifo($Rs32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let Constraints = "$Ryy32 = $Ryy32in"; +} +def L2_loadbsw2_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s31_1Imm:$Ii), +"$Rd32 = membh($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_15275738 { +let Inst{24-21} = 0b0001; +let Inst{31-27} = 0b10010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +} +def L2_loadbsw2_pbr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = membh($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011110001; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbsw2_pci : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), +"$Rd32 = membh($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_13303422 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011000001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbsw2_pcr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = membh($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011000001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbsw2_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii), +"$Rd32 = membh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_15376009 { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011010001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbsw2_pr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = membh($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011100001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbsw2_zomap : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = membh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_loadbsw4_io : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, s30_2Imm:$Ii), +"$Rdd32 = membh($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_9852473 { +let Inst{24-21} = 0b0111; +let Inst{31-27} = 0b10010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 13; +let opExtentAlign = 2; +} +def L2_loadbsw4_pbr : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rdd32 = membh($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_2901241 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011110111; +let accessSize = WordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbsw4_pci : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), +"$Rdd32 = membh($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_3931661 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011000111; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbsw4_pcr : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rdd32 = membh($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_2901241 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011000111; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbsw4_pi : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_2Imm:$Ii), +"$Rdd32 = membh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_8752140 { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011010111; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbsw4_pr : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rdd32 = membh($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_2901241 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011100111; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbsw4_zomap : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = membh($Rs32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_loadbzw2_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s31_1Imm:$Ii), +"$Rd32 = memubh($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_15275738 { +let Inst{24-21} = 0b0011; +let Inst{31-27} = 0b10010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +} +def L2_loadbzw2_pbr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memubh($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011110011; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbzw2_pci : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), +"$Rd32 = memubh($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_13303422 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011000011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbzw2_pcr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memubh($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011000011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbzw2_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii), +"$Rd32 = memubh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_15376009 { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011010011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbzw2_pr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memubh($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011100011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbzw2_zomap : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = memubh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_loadbzw4_io : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, s30_2Imm:$Ii), +"$Rdd32 = memubh($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_9852473 { +let Inst{24-21} = 0b0101; +let Inst{31-27} = 0b10010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 13; +let opExtentAlign = 2; +} +def L2_loadbzw4_pbr : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rdd32 = memubh($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_2901241 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011110101; +let accessSize = WordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbzw4_pci : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), +"$Rdd32 = memubh($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_3931661 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011000101; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbzw4_pcr : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rdd32 = memubh($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_2901241 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011000101; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbzw4_pi : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_2Imm:$Ii), +"$Rdd32 = memubh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_8752140 { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011010101; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbzw4_pr : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rdd32 = memubh($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_2901241 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011100101; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadbzw4_zomap : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = memubh($Rs32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_loadrb_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = memb($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_14461004, AddrModeRel { +let Inst{24-21} = 0b1000; +let Inst{31-27} = 0b10010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let BaseOpcode = "L2_loadrb_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 0; +} +def L2_loadrb_pbr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memb($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011111000; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = ByteAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrb_pci : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), +"$Rd32 = memb($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_16303398 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011001000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrb_pcr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memb($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011001000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrb_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_0Imm:$Ii), +"$Rd32 = memb($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_5598813, PredNewRel { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011011000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrb_pi"; +let isPredicable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrb_pr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memb($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011101000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrb_zomap : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = memb($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_loadrbgp : HInst< +(outs IntRegs:$Rd32), +(ins u32_0Imm:$Ii), +"$Rd32 = memb(gp+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1886960, AddrModeRel { +let Inst{24-21} = 0b1000; +let Inst{31-27} = 0b01001; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = ByteAccess; +let mayLoad = 1; +let Uses = [GP]; +let BaseOpcode = "L4_loadrb_abs"; +let isPredicable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 16; +let opExtentAlign = 0; +} +def L2_loadrd_io : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, s29_3Imm:$Ii), +"$Rdd32 = memd($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_163381, AddrModeRel { +let Inst{24-21} = 0b1110; +let Inst{31-27} = 0b10010; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let BaseOpcode = "L2_loadrd_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 14; +let opExtentAlign = 3; +} +def L2_loadrd_pbr : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rdd32 = memd($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_2901241 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011111110; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrd_pci : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2), +"$Rdd32 = memd($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_931653 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011001110; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrd_pcr : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rdd32 = memd($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_2901241 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011001110; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrd_pi : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_3Imm:$Ii), +"$Rdd32 = memd($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_9752128, PredNewRel { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011011110; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrd_pi"; +let isPredicable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrd_pr : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rdd32 = memd($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_2901241 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011101110; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrd_zomap : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = memd($Rs32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_loadrdgp : HInst< +(outs DoubleRegs:$Rdd32), +(ins u29_3Imm:$Ii), +"$Rdd32 = memd(gp+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_4975051, AddrModeRel { +let Inst{24-21} = 0b1110; +let Inst{31-27} = 0b01001; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let Uses = [GP]; +let BaseOpcode = "L4_loadrd_abs"; +let isPredicable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 19; +let opExtentAlign = 3; +} +def L2_loadrh_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s31_1Imm:$Ii), +"$Rd32 = memh($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_15275738, AddrModeRel { +let Inst{24-21} = 0b1010; +let Inst{31-27} = 0b10010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let BaseOpcode = "L2_loadrh_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +} +def L2_loadrh_pbr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memh($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011111010; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrh_pci : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), +"$Rd32 = memh($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_13303422 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011001010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrh_pcr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memh($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011001010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrh_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii), +"$Rd32 = memh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_15376009, PredNewRel { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011011010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrh_pi"; +let isPredicable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrh_pr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memh($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011101010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrh_zomap : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = memh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_loadrhgp : HInst< +(outs IntRegs:$Rd32), +(ins u31_1Imm:$Ii), +"$Rd32 = memh(gp+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_12608570, AddrModeRel { +let Inst{24-21} = 0b1010; +let Inst{31-27} = 0b01001; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [GP]; +let BaseOpcode = "L4_loadrh_abs"; +let isPredicable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 17; +let opExtentAlign = 1; +} +def L2_loadri_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s30_2Imm:$Ii), +"$Rd32 = memw($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_8990840, AddrModeRel { +let Inst{24-21} = 0b1100; +let Inst{31-27} = 0b10010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let BaseOpcode = "L2_loadri_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 13; +let opExtentAlign = 2; +} +def L2_loadri_pbr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memw($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011111100; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = WordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadri_pci : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2), +"$Rd32 = memw($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_14303394 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011001100; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadri_pcr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memw($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011001100; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadri_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_2Imm:$Ii), +"$Rd32 = memw($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_16376009, PredNewRel { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011011100; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadri_pi"; +let isPredicable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadri_pr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memw($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011101100; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadri_zomap : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = memw($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_loadrigp : HInst< +(outs IntRegs:$Rd32), +(ins u30_2Imm:$Ii), +"$Rd32 = memw(gp+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_8814718, AddrModeRel { +let Inst{24-21} = 0b1100; +let Inst{31-27} = 0b01001; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = WordAccess; +let mayLoad = 1; +let Uses = [GP]; +let BaseOpcode = "L4_loadri_abs"; +let isPredicable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 18; +let opExtentAlign = 2; +} +def L2_loadrub_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rd32 = memub($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_14461004, AddrModeRel { +let Inst{24-21} = 0b1001; +let Inst{31-27} = 0b10010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let BaseOpcode = "L2_loadrub_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 0; +} +def L2_loadrub_pbr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memub($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011111001; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = ByteAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrub_pci : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2), +"$Rd32 = memub($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_16303398 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011001001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrub_pcr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memub($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011001001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrub_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_0Imm:$Ii), +"$Rd32 = memub($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_5598813, PredNewRel { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011011001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrub_pi"; +let isPredicable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrub_pr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memub($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011101001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadrub_zomap : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = memub($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_loadrubgp : HInst< +(outs IntRegs:$Rd32), +(ins u32_0Imm:$Ii), +"$Rd32 = memub(gp+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1886960, AddrModeRel { +let Inst{24-21} = 0b1001; +let Inst{31-27} = 0b01001; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = ByteAccess; +let mayLoad = 1; +let Uses = [GP]; +let BaseOpcode = "L4_loadrub_abs"; +let isPredicable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 16; +let opExtentAlign = 0; +} +def L2_loadruh_io : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s31_1Imm:$Ii), +"$Rd32 = memuh($Rs32+#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_15275738, AddrModeRel { +let Inst{24-21} = 0b1011; +let Inst{31-27} = 0b10010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let BaseOpcode = "L2_loadruh_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +} +def L2_loadruh_pbr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memuh($Rx32++$Mu2:brev)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011111011; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadruh_pci : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2), +"$Rd32 = memuh($Rx32++#$Ii:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_13303422 { +let Inst{12-9} = 0b0000; +let Inst{31-21} = 0b10011001011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadruh_pcr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memuh($Rx32++I:circ($Mu2))", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00010000; +let Inst{31-21} = 0b10011001011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadruh_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii), +"$Rd32 = memuh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_15376009, PredNewRel { +let Inst{13-9} = 0b00000; +let Inst{31-21} = 0b10011011011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadruh_pi"; +let isPredicable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadruh_pr : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Rd32 = memuh($Rx32++$Mu2)", +LD_tc_ld_SLOT01, TypeLD>, Enc_48594 { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b10011101011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_loadruh_zomap : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = memuh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_loadruhgp : HInst< +(outs IntRegs:$Rd32), +(ins u31_1Imm:$Ii), +"$Rd32 = memuh(gp+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_12608570, AddrModeRel { +let Inst{24-21} = 0b1011; +let Inst{31-27} = 0b01001; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let Uses = [GP]; +let BaseOpcode = "L4_loadruh_abs"; +let isPredicable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 17; +let opExtentAlign = 1; +} +def L2_loadw_locked : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = memw_locked($Rs32)", +LD_tc_ld_SLOT0, TypeLD>, Enc_4075554 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10010010000; +let hasNewValue = 1; +let opNewValue = 0; +let accessSize = WordAccess; +let isSoloAX = 1; +let mayLoad = 1; +} +def L2_ploadrbf_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), +"if (!$Pt4) $Rd32 = memb($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_4835423, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000101000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let BaseOpcode = "L2_loadrb_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L2_ploadrbf_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), +"if (!$Pt4) $Rd32 = memb($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_12212978, PredNewRel { +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011011000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrb_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrbf_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4) $Rd32 = memb($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrbfnew_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memb($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_4835423, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000111000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let BaseOpcode = "L2_loadrb_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L2_ploadrbfnew_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memb($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_12212978, PredNewRel { +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011011000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadrb_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrbfnew_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4.new) $Rd32 = memb($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrbt_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), +"if ($Pt4) $Rd32 = memb($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_4835423, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000001000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let BaseOpcode = "L2_loadrb_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L2_ploadrbt_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), +"if ($Pt4) $Rd32 = memb($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_12212978, PredNewRel { +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011011000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrb_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrbt_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4) $Rd32 = memb($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrbtnew_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), +"if ($Pt4.new) $Rd32 = memb($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_4835423, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000011000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let BaseOpcode = "L2_loadrb_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L2_ploadrbtnew_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), +"if ($Pt4.new) $Rd32 = memb($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_12212978, PredNewRel { +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011011000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadrb_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrbtnew_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4.new) $Rd32 = memb($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrdf_io : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), +"if (!$Pt4) $Rdd32 = memd($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_677558, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000101110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let BaseOpcode = "L2_loadrd_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 9; +let opExtentAlign = 3; +} +def L2_ploadrdf_pi : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), +"if (!$Pt4) $Rdd32 = memd($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_5611087, PredNewRel { +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011011110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrd_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrdf_zomap : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4) $Rdd32 = memd($Rs32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrdfnew_io : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), +"if (!$Pt4.new) $Rdd32 = memd($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_677558, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000111110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let BaseOpcode = "L2_loadrd_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 9; +let opExtentAlign = 3; +} +def L2_ploadrdfnew_pi : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), +"if (!$Pt4.new) $Rdd32 = memd($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_5611087, PredNewRel { +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011011110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadrd_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrdfnew_zomap : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4.new) $Rdd32 = memd($Rs32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrdt_io : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), +"if ($Pt4) $Rdd32 = memd($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_677558, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000001110; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let BaseOpcode = "L2_loadrd_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 9; +let opExtentAlign = 3; +} +def L2_ploadrdt_pi : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), +"if ($Pt4) $Rdd32 = memd($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_5611087, PredNewRel { +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011011110; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrd_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrdt_zomap : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4) $Rdd32 = memd($Rs32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrdtnew_io : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u29_3Imm:$Ii), +"if ($Pt4.new) $Rdd32 = memd($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_677558, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000011110; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let BaseOpcode = "L2_loadrd_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 9; +let opExtentAlign = 3; +} +def L2_ploadrdtnew_pi : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_3Imm:$Ii), +"if ($Pt4.new) $Rdd32 = memd($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_5611087, PredNewRel { +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011011110; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadrd_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrdtnew_zomap : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4.new) $Rdd32 = memd($Rs32)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrhf_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), +"if (!$Pt4) $Rd32 = memh($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000101010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let BaseOpcode = "L2_loadrh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L2_ploadrhf_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), +"if (!$Pt4) $Rd32 = memh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_7212930, PredNewRel { +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011011010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrh_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrhf_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4) $Rd32 = memh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrhfnew_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memh($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000111010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let BaseOpcode = "L2_loadrh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L2_ploadrhfnew_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_7212930, PredNewRel { +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011011010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadrh_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrhfnew_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4.new) $Rd32 = memh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrht_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), +"if ($Pt4) $Rd32 = memh($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000001010; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let BaseOpcode = "L2_loadrh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L2_ploadrht_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), +"if ($Pt4) $Rd32 = memh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_7212930, PredNewRel { +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011011010; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrh_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrht_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4) $Rd32 = memh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrhtnew_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), +"if ($Pt4.new) $Rd32 = memh($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000011010; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let BaseOpcode = "L2_loadrh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L2_ploadrhtnew_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), +"if ($Pt4.new) $Rd32 = memh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_7212930, PredNewRel { +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011011010; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadrh_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrhtnew_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4.new) $Rd32 = memh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrif_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), +"if (!$Pt4) $Rd32 = memw($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_2835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000101100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let BaseOpcode = "L2_loadri_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L2_ploadrif_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), +"if (!$Pt4) $Rd32 = memw($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_6212930, PredNewRel { +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadri_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrif_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4) $Rd32 = memw($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrifnew_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memw($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_2835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000111100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let BaseOpcode = "L2_loadri_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L2_ploadrifnew_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memw($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_6212930, PredNewRel { +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadri_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrifnew_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4.new) $Rd32 = memw($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrit_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), +"if ($Pt4) $Rd32 = memw($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_2835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000001100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let BaseOpcode = "L2_loadri_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L2_ploadrit_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), +"if ($Pt4) $Rd32 = memw($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_6212930, PredNewRel { +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011011100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadri_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrit_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4) $Rd32 = memw($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadritnew_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u30_2Imm:$Ii), +"if ($Pt4.new) $Rd32 = memw($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_2835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000011100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let BaseOpcode = "L2_loadri_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L2_ploadritnew_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_2Imm:$Ii), +"if ($Pt4.new) $Rd32 = memw($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_6212930, PredNewRel { +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011011100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadri_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadritnew_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4.new) $Rd32 = memw($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrubf_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), +"if (!$Pt4) $Rd32 = memub($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_4835423, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000101001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let BaseOpcode = "L2_loadrub_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L2_ploadrubf_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), +"if (!$Pt4) $Rd32 = memub($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_12212978, PredNewRel { +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011011001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrub_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrubf_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4) $Rd32 = memub($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrubfnew_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memub($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_4835423, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000111001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let BaseOpcode = "L2_loadrub_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L2_ploadrubfnew_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memub($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_12212978, PredNewRel { +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011011001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadrub_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrubfnew_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4.new) $Rd32 = memub($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrubt_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), +"if ($Pt4) $Rd32 = memub($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_4835423, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000001001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let BaseOpcode = "L2_loadrub_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L2_ploadrubt_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), +"if ($Pt4) $Rd32 = memub($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_12212978, PredNewRel { +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011011001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadrub_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrubt_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4) $Rd32 = memub($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadrubtnew_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u32_0Imm:$Ii), +"if ($Pt4.new) $Rd32 = memub($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_4835423, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000011001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let BaseOpcode = "L2_loadrub_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L2_ploadrubtnew_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_0Imm:$Ii), +"if ($Pt4.new) $Rd32 = memub($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_12212978, PredNewRel { +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011011001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadrub_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadrubtnew_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4.new) $Rd32 = memub($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadruhf_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), +"if (!$Pt4) $Rd32 = memuh($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000101011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let BaseOpcode = "L2_loadruh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L2_ploadruhf_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), +"if (!$Pt4) $Rd32 = memuh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_7212930, PredNewRel { +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadruh_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadruhf_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4) $Rd32 = memuh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadruhfnew_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memuh($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000111011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let BaseOpcode = "L2_loadruh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L2_ploadruhfnew_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memuh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_7212930, PredNewRel { +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadruh_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadruhfnew_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if (!$Pt4.new) $Rd32 = memuh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadruht_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), +"if ($Pt4) $Rd32 = memuh($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000001011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let BaseOpcode = "L2_loadruh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L2_ploadruht_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), +"if ($Pt4) $Rd32 = memuh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_7212930, PredNewRel { +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011011011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let BaseOpcode = "L2_loadruh_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadruht_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4) $Rd32 = memuh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L2_ploadruhtnew_io : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32, u31_1Imm:$Ii), +"if ($Pt4.new) $Rd32 = memuh($Rs32+#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1835415, AddrModeRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b01000011011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let BaseOpcode = "L2_loadruh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L2_ploadruhtnew_pi : HInst< +(outs IntRegs:$Rd32, IntRegs:$Rx32), +(ins PredRegs:$Pt4, IntRegs:$Rx32in, s4_1Imm:$Ii), +"if ($Pt4.new) $Rd32 = memuh($Rx32++#$Ii)", +LD_tc_ld_pi_SLOT01, TypeLD>, Enc_7212930, PredNewRel { +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011011011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let BaseOpcode = "L2_loadruh_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def L2_ploadruhtnew_zomap : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, IntRegs:$Rs32), +"if ($Pt4.new) $Rd32 = memuh($Rs32)", +PSEUDO, TypeMAPPING> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_add_memopb_io : HInst< +(outs), +(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), +"memb($Rs32+#$Ii) += $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_11849200 { +let Inst{6-5} = 0b00; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110000; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_add_memopb_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memb($Rs32) += $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_add_memoph_io : HInst< +(outs), +(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"memh($Rs32+#$Ii) += $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_8849208 { +let Inst{6-5} = 0b00; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110001; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L4_add_memoph_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memh($Rs32) += $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_add_memopw_io : HInst< +(outs), +(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), +"memw($Rs32+#$Ii) += $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_9849208 { +let Inst{6-5} = 0b00; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L4_add_memopw_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memw($Rs32) += $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_and_memopb_io : HInst< +(outs), +(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), +"memb($Rs32+#$Ii) &= $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_11849200 { +let Inst{6-5} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110000; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_and_memopb_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memb($Rs32) &= $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_and_memoph_io : HInst< +(outs), +(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"memh($Rs32+#$Ii) &= $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_8849208 { +let Inst{6-5} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110001; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L4_and_memoph_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memh($Rs32) &= $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_and_memopw_io : HInst< +(outs), +(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), +"memw($Rs32+#$Ii) &= $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_9849208 { +let Inst{6-5} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L4_and_memopw_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memw($Rs32) &= $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_iadd_memopb_io : HInst< +(outs), +(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), +"memb($Rs32+#$Ii) += #$II", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_6773159 { +let Inst{6-5} = 0b00; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111000; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_iadd_memopb_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memb($Rs32) += #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_iadd_memoph_io : HInst< +(outs), +(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), +"memh($Rs32+#$Ii) += #$II", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_9773167 { +let Inst{6-5} = 0b00; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111001; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L4_iadd_memoph_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memh($Rs32) += #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_iadd_memopw_io : HInst< +(outs), +(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), +"memw($Rs32+#$Ii) += #$II", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_8773155 { +let Inst{6-5} = 0b00; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L4_iadd_memopw_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memw($Rs32) += #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_iand_memopb_io : HInst< +(outs), +(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), +"memb($Rs32+#$Ii) = clrbit(#$II)", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_6773159 { +let Inst{6-5} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111000; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_iand_memopb_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memb($Rs32) = clrbit(#$II)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_iand_memoph_io : HInst< +(outs), +(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), +"memh($Rs32+#$Ii) = clrbit(#$II)", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_9773167 { +let Inst{6-5} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111001; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L4_iand_memoph_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memh($Rs32) = clrbit(#$II)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_iand_memopw_io : HInst< +(outs), +(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), +"memw($Rs32+#$Ii) = clrbit(#$II)", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_8773155 { +let Inst{6-5} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L4_iand_memopw_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memw($Rs32) = clrbit(#$II)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_ior_memopb_io : HInst< +(outs), +(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), +"memb($Rs32+#$Ii) = setbit(#$II)", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_6773159 { +let Inst{6-5} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111000; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ior_memopb_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memb($Rs32) = setbit(#$II)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_ior_memoph_io : HInst< +(outs), +(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), +"memh($Rs32+#$Ii) = setbit(#$II)", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_9773167 { +let Inst{6-5} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111001; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L4_ior_memoph_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memh($Rs32) = setbit(#$II)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_ior_memopw_io : HInst< +(outs), +(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), +"memw($Rs32+#$Ii) = setbit(#$II)", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_8773155 { +let Inst{6-5} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L4_ior_memopw_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memw($Rs32) = setbit(#$II)", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_isub_memopb_io : HInst< +(outs), +(ins IntRegs:$Rs32, u32_0Imm:$Ii, u5_0Imm:$II), +"memb($Rs32+#$Ii) -= #$II", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_6773159 { +let Inst{6-5} = 0b01; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111000; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_isub_memopb_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memb($Rs32) -= #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_isub_memoph_io : HInst< +(outs), +(ins IntRegs:$Rs32, u31_1Imm:$Ii, u5_0Imm:$II), +"memh($Rs32+#$Ii) -= #$II", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_9773167 { +let Inst{6-5} = 0b01; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111001; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L4_isub_memoph_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memh($Rs32) -= #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_isub_memopw_io : HInst< +(outs), +(ins IntRegs:$Rs32, u30_2Imm:$Ii, u5_0Imm:$II), +"memw($Rs32+#$Ii) -= #$II", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_8773155 { +let Inst{6-5} = 0b01; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111111010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L4_isub_memopw_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, u5_0Imm:$II), +"memw($Rs32) -= #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_loadalignb_ap : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Re32), +(ins DoubleRegs:$Ryy32in, u32_0Imm:$II), +"$Ryy32 = memb_fifo($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_11047413 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011010100; +let hasNewValue = 1; +let opNewValue = 1; +let addrMode = AbsoluteSet; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let Constraints = "$Ryy32 = $Ryy32in"; +} +def L4_loadalignb_ur : HInst< +(outs DoubleRegs:$Ryy32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Ryy32 = memb_fifo($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_7303598 { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011100100; +let addrMode = BaseLongOffset; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 4; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let Constraints = "$Ryy32 = $Ryy32in"; +} +def L4_loadalignh_ap : HInst< +(outs DoubleRegs:$Ryy32, IntRegs:$Re32), +(ins DoubleRegs:$Ryy32in, u32_0Imm:$II), +"$Ryy32 = memh_fifo($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_11047413 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011010010; +let hasNewValue = 1; +let opNewValue = 1; +let addrMode = AbsoluteSet; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let Constraints = "$Ryy32 = $Ryy32in"; +} +def L4_loadalignh_ur : HInst< +(outs DoubleRegs:$Ryy32), +(ins DoubleRegs:$Ryy32in, IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Ryy32 = memh_fifo($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_7303598 { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011100010; +let addrMode = BaseLongOffset; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 4; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let Constraints = "$Ryy32 = $Ryy32in"; +} +def L4_loadbsw2_ap : HInst< +(outs IntRegs:$Rd32, IntRegs:$Re32), +(ins u32_0Imm:$II), +"$Rd32 = membh($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12616482 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011010001; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let addrMode = AbsoluteSet; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadbsw2_ur : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Rd32 = membh($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_486163 { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011100001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseLongOffset; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadbsw4_ap : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Re32), +(ins u32_0Imm:$II), +"$Rdd32 = membh($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_877823 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011010111; +let hasNewValue = 1; +let opNewValue = 1; +let addrMode = AbsoluteSet; +let accessSize = WordAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadbsw4_ur : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Rdd32 = membh($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_5582416 { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011100111; +let addrMode = BaseLongOffset; +let accessSize = WordAccess; +let isExtended = 1; +let mayLoad = 1; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadbzw2_ap : HInst< +(outs IntRegs:$Rd32, IntRegs:$Re32), +(ins u32_0Imm:$II), +"$Rd32 = memubh($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12616482 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011010011; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let addrMode = AbsoluteSet; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadbzw2_ur : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Rd32 = memubh($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_486163 { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011100011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseLongOffset; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadbzw4_ap : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Re32), +(ins u32_0Imm:$II), +"$Rdd32 = memubh($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_877823 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011010101; +let hasNewValue = 1; +let opNewValue = 1; +let addrMode = AbsoluteSet; +let accessSize = WordAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadbzw4_ur : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Rdd32 = memubh($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_5582416 { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011100101; +let addrMode = BaseLongOffset; +let accessSize = WordAccess; +let isExtended = 1; +let mayLoad = 1; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadd_locked : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = memd_locked($Rs32)", +LD_tc_ld_SLOT0, TypeLD>, Enc_4030179 { +let Inst{13-5} = 0b010000000; +let Inst{31-21} = 0b10010010000; +let accessSize = DoubleWordAccess; +let isSoloAX = 1; +let mayLoad = 1; +} +def L4_loadrb_ap : HInst< +(outs IntRegs:$Rd32, IntRegs:$Re32), +(ins u32_0Imm:$II), +"$Rd32 = memb($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12616482 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011011000; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let addrMode = AbsoluteSet; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadrb_rr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"$Rd32 = memb($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_10721363, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111010000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrb_rr"; +let isPredicable = 1; +} +def L4_loadrb_ur : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Rd32 = memb($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_486163, AddrModeRel, ImmRegShl { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011101000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseLongOffset; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadrd_ap : HInst< +(outs DoubleRegs:$Rdd32, IntRegs:$Re32), +(ins u32_0Imm:$II), +"$Rdd32 = memd($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_877823 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011011110; +let hasNewValue = 1; +let opNewValue = 1; +let addrMode = AbsoluteSet; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadrd_rr : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"$Rdd32 = memd($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_7581852, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111010110; +let addrMode = BaseRegOffset; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrd_rr"; +let isPredicable = 1; +} +def L4_loadrd_ur : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Rdd32 = memd($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_5582416, AddrModeRel, ImmRegShl { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011101110; +let addrMode = BaseLongOffset; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadrh_ap : HInst< +(outs IntRegs:$Rd32, IntRegs:$Re32), +(ins u32_0Imm:$II), +"$Rd32 = memh($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12616482 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011011010; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let addrMode = AbsoluteSet; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadrh_rr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"$Rd32 = memh($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_10721363, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111010010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrh_rr"; +let isPredicable = 1; +} +def L4_loadrh_ur : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Rd32 = memh($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_486163, AddrModeRel, ImmRegShl { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011101010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseLongOffset; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadri_ap : HInst< +(outs IntRegs:$Rd32, IntRegs:$Re32), +(ins u32_0Imm:$II), +"$Rd32 = memw($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12616482 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011011100; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let addrMode = AbsoluteSet; +let accessSize = WordAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadri_rr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"$Rd32 = memw($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_10721363, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111010100; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let InputType = "reg"; +let BaseOpcode = "L4_loadri_rr"; +let isPredicable = 1; +} +def L4_loadri_ur : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Rd32 = memw($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_486163, AddrModeRel, ImmRegShl { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011101100; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseLongOffset; +let accessSize = WordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadrub_ap : HInst< +(outs IntRegs:$Rd32, IntRegs:$Re32), +(ins u32_0Imm:$II), +"$Rd32 = memub($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12616482 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011011001; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let addrMode = AbsoluteSet; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadrub_rr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"$Rd32 = memub($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_10721363, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111010001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrub_rr"; +let isPredicable = 1; +} +def L4_loadrub_ur : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Rd32 = memub($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_486163, AddrModeRel, ImmRegShl { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011101001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseLongOffset; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadruh_ap : HInst< +(outs IntRegs:$Rd32, IntRegs:$Re32), +(ins u32_0Imm:$II), +"$Rd32 = memuh($Re32=#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_12616482 { +let Inst{7-7} = 0b0; +let Inst{13-12} = 0b01; +let Inst{31-21} = 0b10011011011; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let addrMode = AbsoluteSet; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_loadruh_rr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"$Rd32 = memuh($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_10721363, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111010011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let InputType = "reg"; +let BaseOpcode = "L4_loadruh_rr"; +let isPredicable = 1; +} +def L4_loadruh_ur : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, u2_0Imm:$Ii, u32_0Imm:$II), +"$Rd32 = memuh($Rt32<<#$Ii+#$II)", +LD_tc_ld_SLOT01, TypeLD>, Enc_486163, AddrModeRel, ImmRegShl { +let Inst{12-12} = 0b1; +let Inst{31-21} = 0b10011101011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseLongOffset; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let InputType = "imm"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_or_memopb_io : HInst< +(outs), +(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), +"memb($Rs32+#$Ii) |= $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_11849200 { +let Inst{6-5} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110000; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_or_memopb_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memb($Rs32) |= $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_or_memoph_io : HInst< +(outs), +(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"memh($Rs32+#$Ii) |= $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_8849208 { +let Inst{6-5} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110001; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L4_or_memoph_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memh($Rs32) |= $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_or_memopw_io : HInst< +(outs), +(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), +"memw($Rs32+#$Ii) |= $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_9849208 { +let Inst{6-5} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L4_or_memopw_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memw($Rs32) |= $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_ploadrbf_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4) $Rd32 = memb(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011111000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let BaseOpcode = "L4_loadrb_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrbf_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110001000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrb_rr"; +} +def L4_ploadrbfnew_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memb(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011111000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let BaseOpcode = "L4_loadrb_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrbfnew_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110011000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrb_rr"; +} +def L4_ploadrbt_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4) $Rd32 = memb(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011111000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let BaseOpcode = "L4_loadrb_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrbt_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110000000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrb_rr"; +} +def L4_ploadrbtnew_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4.new) $Rd32 = memb(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011111000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let BaseOpcode = "L4_loadrb_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrbtnew_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4.new) $Rd32 = memb($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110010000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrb_rr"; +} +def L4_ploadrdf_abs : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4) $Rdd32 = memd(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_15182416, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011111110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let BaseOpcode = "L4_loadrd_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrdf_rr : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_7254313, AddrModeRel { +let Inst{31-21} = 0b00110001110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrd_rr"; +} +def L4_ploadrdfnew_abs : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4.new) $Rdd32 = memd(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_15182416, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011111110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let BaseOpcode = "L4_loadrd_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrdfnew_rr : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_7254313, AddrModeRel { +let Inst{31-21} = 0b00110011110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrd_rr"; +} +def L4_ploadrdt_abs : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4) $Rdd32 = memd(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_15182416, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011111110; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let BaseOpcode = "L4_loadrd_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrdt_rr : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_7254313, AddrModeRel { +let Inst{31-21} = 0b00110000110; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = DoubleWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrd_rr"; +} +def L4_ploadrdtnew_abs : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4.new) $Rdd32 = memd(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_15182416, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011111110; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let BaseOpcode = "L4_loadrd_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrdtnew_rr : HInst< +(outs DoubleRegs:$Rdd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4.new) $Rdd32 = memd($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_7254313, AddrModeRel { +let Inst{31-21} = 0b00110010110; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrd_rr"; +} +def L4_ploadrhf_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4) $Rd32 = memh(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011111010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let BaseOpcode = "L4_loadrh_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrhf_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110001010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrh_rr"; +} +def L4_ploadrhfnew_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memh(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011111010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let BaseOpcode = "L4_loadrh_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrhfnew_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110011010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrh_rr"; +} +def L4_ploadrht_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4) $Rd32 = memh(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011111010; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let BaseOpcode = "L4_loadrh_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrht_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110000010; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrh_rr"; +} +def L4_ploadrhtnew_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4.new) $Rd32 = memh(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011111010; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let BaseOpcode = "L4_loadrh_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrhtnew_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4.new) $Rd32 = memh($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110010010; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrh_rr"; +} +def L4_ploadrif_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4) $Rd32 = memw(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011111100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = WordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let BaseOpcode = "L4_loadri_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrif_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110001100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let InputType = "reg"; +let BaseOpcode = "L4_loadri_rr"; +} +def L4_ploadrifnew_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memw(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011111100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = WordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let BaseOpcode = "L4_loadri_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrifnew_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let InputType = "reg"; +let BaseOpcode = "L4_loadri_rr"; +} +def L4_ploadrit_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4) $Rd32 = memw(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011111100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = WordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let BaseOpcode = "L4_loadri_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrit_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110000100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let InputType = "reg"; +let BaseOpcode = "L4_loadri_rr"; +} +def L4_ploadritnew_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4.new) $Rd32 = memw(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011111100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = WordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let BaseOpcode = "L4_loadri_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadritnew_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4.new) $Rd32 = memw($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110010100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let InputType = "reg"; +let BaseOpcode = "L4_loadri_rr"; +} +def L4_ploadrubf_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4) $Rd32 = memub(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011111001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let BaseOpcode = "L4_loadrub_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrubf_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110001001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrub_rr"; +} +def L4_ploadrubfnew_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memub(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011111001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let BaseOpcode = "L4_loadrub_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrubfnew_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110011001; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrub_rr"; +} +def L4_ploadrubt_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4) $Rd32 = memub(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011111001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let BaseOpcode = "L4_loadrub_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrubt_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110000001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrub_rr"; +} +def L4_ploadrubtnew_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4.new) $Rd32 = memub(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011111001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let BaseOpcode = "L4_loadrub_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadrubtnew_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4.new) $Rd32 = memub($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110010001; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let InputType = "reg"; +let BaseOpcode = "L4_loadrub_rr"; +} +def L4_ploadruhf_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4) $Rd32 = memuh(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10011111011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let BaseOpcode = "L4_loadruh_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadruhf_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110001011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let InputType = "reg"; +let BaseOpcode = "L4_loadruh_rr"; +} +def L4_ploadruhfnew_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if (!$Pt4.new) $Rd32 = memuh(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b111; +let Inst{31-21} = 0b10011111011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let BaseOpcode = "L4_loadruh_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadruhfnew_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if (!$Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let InputType = "reg"; +let BaseOpcode = "L4_loadruh_rr"; +} +def L4_ploadruht_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4) $Rd32 = memuh(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10011111011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let BaseOpcode = "L4_loadruh_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadruht_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110000011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let InputType = "reg"; +let BaseOpcode = "L4_loadruh_rr"; +} +def L4_ploadruhtnew_abs : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pt4, u32_0Imm:$Ii), +"if ($Pt4.new) $Rd32 = memuh(#$Ii)", +LD_tc_ld_SLOT01, TypeLD>, Enc_13344657, AddrModeRel { +let Inst{7-5} = 0b100; +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10011111011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let BaseOpcode = "L4_loadruh_abs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_ploadruhtnew_rr : HInst< +(outs IntRegs:$Rd32), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32, u2_0Imm:$Ii), +"if ($Pv4.new) $Rd32 = memuh($Rs32+$Rt32<<#$Ii)", +V4LDST_tc_ld_SLOT01, TypeLD>, Enc_1793896, AddrModeRel { +let Inst{31-21} = 0b00110010011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let InputType = "reg"; +let BaseOpcode = "L4_loadruh_rr"; +} +def L4_return : HInst< +(outs), +(ins), +"dealloc_return", +LD_tc_3or4stall_SLOT0, TypeLD>, Enc_0, PredNewRel { +let Inst{4-0} = 0b11110; +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10010110000; +let Inst{20-16} = 0b11110; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let isReturn = 1; +let mayLoad = 1; +let Uses = [R30]; +let Defs = [PC, R29, R30, R31]; +let BaseOpcode = "L4_return"; +let isBarrier = 1; +let isPredicable = 1; +let isTaken = 1; +} +def L4_return_f : HInst< +(outs), +(ins PredRegs:$Pv4), +"if (!$Pv4) dealloc_return", +LD_tc_3or4stall_SLOT0, TypeLD>, Enc_12711252, PredNewRel { +let Inst{4-0} = 0b11110; +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1100; +let Inst{31-21} = 0b10010110000; +let Inst{20-16} = 0b11110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let isReturn = 1; +let mayLoad = 1; +let Uses = [R30]; +let Defs = [PC, R29, R30, R31]; +let BaseOpcode = "L4_return"; +let isTaken = Inst{12}; +} +def L4_return_fnew_pnt : HInst< +(outs), +(ins PredRegs:$Pv4), +"if (!$Pv4.new) dealloc_return:nt", +LD_tc_3or4stall_SLOT0, TypeLD>, Enc_12711252, PredNewRel { +let Inst{4-0} = 0b11110; +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1010; +let Inst{31-21} = 0b10010110000; +let Inst{20-16} = 0b11110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let isReturn = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let Uses = [R30]; +let Defs = [PC, R29, R30, R31]; +let BaseOpcode = "L4_return"; +let isTaken = Inst{12}; +} +def L4_return_fnew_pt : HInst< +(outs), +(ins PredRegs:$Pv4), +"if (!$Pv4.new) dealloc_return:t", +LD_tc_3or4stall_SLOT0, TypeLD>, Enc_12711252, PredNewRel { +let Inst{4-0} = 0b11110; +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b1110; +let Inst{31-21} = 0b10010110000; +let Inst{20-16} = 0b11110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let isReturn = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let Uses = [R30]; +let Defs = [PC, R29, R30, R31]; +let BaseOpcode = "L4_return"; +let isTaken = Inst{12}; +} +def L4_return_t : HInst< +(outs), +(ins PredRegs:$Pv4), +"if ($Pv4) dealloc_return", +LD_tc_3or4stall_SLOT0, TypeLD>, Enc_12711252, PredNewRel { +let Inst{4-0} = 0b11110; +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b0100; +let Inst{31-21} = 0b10010110000; +let Inst{20-16} = 0b11110; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let isReturn = 1; +let mayLoad = 1; +let Uses = [R30]; +let Defs = [PC, R29, R30, R31]; +let BaseOpcode = "L4_return"; +let isTaken = Inst{12}; +} +def L4_return_tnew_pnt : HInst< +(outs), +(ins PredRegs:$Pv4), +"if ($Pv4.new) dealloc_return:nt", +LD_tc_3or4stall_SLOT0, TypeLD>, Enc_12711252, PredNewRel { +let Inst{4-0} = 0b11110; +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b0010; +let Inst{31-21} = 0b10010110000; +let Inst{20-16} = 0b11110; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let isReturn = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let Uses = [R30]; +let Defs = [PC, R29, R30, R31]; +let BaseOpcode = "L4_return"; +let isTaken = Inst{12}; +} +def L4_return_tnew_pt : HInst< +(outs), +(ins PredRegs:$Pv4), +"if ($Pv4.new) dealloc_return:t", +LD_tc_3or4stall_SLOT0, TypeLD>, Enc_12711252, PredNewRel { +let Inst{4-0} = 0b11110; +let Inst{7-5} = 0b000; +let Inst{13-10} = 0b0110; +let Inst{31-21} = 0b10010110000; +let Inst{20-16} = 0b11110; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let isReturn = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let Uses = [R30]; +let Defs = [PC, R29, R30, R31]; +let BaseOpcode = "L4_return"; +let isTaken = Inst{12}; +} +def L4_sub_memopb_io : HInst< +(outs), +(ins IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), +"memb($Rs32+#$Ii) -= $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_11849200 { +let Inst{6-5} = 0b01; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110000; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def L4_sub_memopb_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memb($Rs32) -= $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_sub_memoph_io : HInst< +(outs), +(ins IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"memh($Rs32+#$Ii) -= $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_8849208 { +let Inst{6-5} = 0b01; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110001; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def L4_sub_memoph_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memh($Rs32) -= $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def L4_sub_memopw_io : HInst< +(outs), +(ins IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), +"memw($Rs32+#$Ii) -= $Rt32", +V4LDST_tc_st_SLOT0, TypeV4LDST>, Enc_9849208 { +let Inst{6-5} = 0b01; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00111110010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let mayLoad = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def L4_sub_memopw_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memw($Rs32) -= $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def M2_acci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += add($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889, ImmRegRel { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let CextOpcode = "M2_acci"; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_accii : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rx32 += add($Rs32,#$Ii)", +M_tc_2_acc_SLOT23, TypeM>, Enc_11522288, ImmRegRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100010000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let CextOpcode = "M2_acci"; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_cmaci_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += cmpyi($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_cmacr_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += cmpyr($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_cmacs_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += cmpy($Rs32,$Rt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_cmacs_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += cmpy($Rs32,$Rt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_cmacsc_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += cmpy($Rs32,$Rt32*):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111010; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_cmacsc_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += cmpy($Rs32,$Rt32*):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_cmpyi_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = cmpyi($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101000; +let prefersSlot3 = 1; +} +def M2_cmpyr_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = cmpyr($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101000; +let prefersSlot3 = 1; +} +def M2_cmpyrs_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = cmpy($Rs32,$Rt32):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_cmpyrs_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = cmpy($Rs32,$Rt32):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_cmpyrsc_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = cmpy($Rs32,$Rt32*):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_cmpyrsc_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = cmpy($Rs32,$Rt32*):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_cmpys_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = cmpy($Rs32,$Rt32):sat", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_cmpys_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = cmpy($Rs32,$Rt32):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_cmpysc_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = cmpy($Rs32,$Rt32*):sat", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101010; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_cmpysc_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = cmpy($Rs32,$Rt32*):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_cnacs_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= cmpy($Rs32,$Rt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_cnacs_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= cmpy($Rs32,$Rt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_cnacsc_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= cmpy($Rs32,$Rt32*):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111010; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_cnacsc_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= cmpy($Rs32,$Rt32*):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_dpmpyss_acc_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpy($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_dpmpyss_nac_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpy($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_dpmpyss_rnd_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32,$Rt32):rnd", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_dpmpyss_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101000; +let prefersSlot3 = 1; +} +def M2_dpmpyuu_acc_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpyu($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_dpmpyuu_nac_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpyu($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_dpmpyuu_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpyu($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101010; +let prefersSlot3 = 1; +} +def M2_hmmpyh_rs1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32,$Rt32.h):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_hmmpyh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32,$Rt32.h):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_hmmpyl_rs1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32,$Rt32.l):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_hmmpyl_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32,$Rt32.l):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_maci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpyi($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889, ImmRegRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let CextOpcode = "M2_maci"; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_macsin : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii), +"$Rx32 -= mpyi($Rs32,#$Ii)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_11522288 { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100001100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_macsip : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u32_0Imm:$Ii), +"$Rx32 += mpyi($Rs32,#$Ii)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_11522288, ImmRegRel { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100001000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let CextOpcode = "M2_maci"; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mmachs_rs0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpywoh($Rss32,$Rtt32):rnd:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010001; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmachs_rs1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:rnd:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010101; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmachs_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpywoh($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmachs_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpywoh($Rss32,$Rtt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmacls_rs0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyweh($Rss32,$Rtt32):rnd:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010001; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmacls_rs1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:rnd:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010101; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmacls_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyweh($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmacls_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyweh($Rss32,$Rtt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmacuhs_rs0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpywouh($Rss32,$Rtt32):rnd:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010011; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmacuhs_rs1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:rnd:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010111; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmacuhs_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpywouh($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010010; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmacuhs_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpywouh($Rss32,$Rtt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmaculs_rs0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyweuh($Rss32,$Rtt32):rnd:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010011; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmaculs_rs1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010111; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmaculs_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyweuh($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010010; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmaculs_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyweuh($Rss32,$Rtt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mmpyh_rs0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpywoh($Rss32,$Rtt32):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000001; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyh_rs1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000101; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyh_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpywoh($Rss32,$Rtt32):sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyh_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpywoh($Rss32,$Rtt32):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyl_rs0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpyweh($Rss32,$Rtt32):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000001; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyl_rs1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000101; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyl_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpyweh($Rss32,$Rtt32):sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyl_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpyweh($Rss32,$Rtt32):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyuh_rs0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpywouh($Rss32,$Rtt32):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000011; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyuh_rs1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000111; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyuh_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpywouh($Rss32,$Rtt32):sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000010; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyuh_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpywouh($Rss32,$Rtt32):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyul_rs0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpyweuh($Rss32,$Rtt32):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000011; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyul_rs1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000111; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyul_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpyweuh($Rss32,$Rtt32):sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000010; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mmpyul_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpyweuh($Rss32,$Rtt32):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_acc_hh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.h,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_hh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.h,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_hl_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.h,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_hl_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.h,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_lh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.l,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_lh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.l,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_ll_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.l,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_ll_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.l,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_sat_hh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.h,$Rt32.h):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_sat_hh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.h,$Rt32.h):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_sat_hl_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.h,$Rt32.l):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_sat_hl_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.h,$Rt32.l):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_sat_lh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.l,$Rt32.h):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_sat_lh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.l,$Rt32.h):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_sat_ll_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.l,$Rt32.l):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_acc_sat_ll_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32.l,$Rt32.l):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_hh_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.h)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_hh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_hl_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.l)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_hl_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_lh_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.h)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_lh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_ll_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.l)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_ll_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_nac_hh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.h,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_hh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_hl_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.h,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_hl_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_lh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.l,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_lh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_ll_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.l,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_ll_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_sat_hh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.h,$Rt32.h):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_sat_hh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.h,$Rt32.h):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_sat_hl_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.h,$Rt32.l):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_sat_hl_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.h,$Rt32.l):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_sat_lh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.l,$Rt32.h):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_sat_lh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.l,$Rt32.h):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_sat_ll_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.l,$Rt32.l):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_nac_sat_ll_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32.l,$Rt32.l):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpy_rnd_hh_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.h):rnd", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_rnd_hh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_rnd_hl_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.l):rnd", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_rnd_hl_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_rnd_lh_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.h):rnd", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_rnd_lh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_rnd_ll_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.l):rnd", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_rnd_ll_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_sat_hh_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.h):sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_hh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_hl_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.l):sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_hl_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_lh_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.h):sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_lh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_ll_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.l):sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_ll_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_rnd_hh_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.h):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_rnd_hh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_rnd_hl_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.l):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_rnd_hl_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_rnd_lh_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.h):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_rnd_lh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_rnd_ll_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.l):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_sat_rnd_ll_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpy_up : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_up_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32,$Rt32):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpy_up_s1_sat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpy($Rs32,$Rt32):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_mpyd_acc_hh_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpy($Rs32.h,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_acc_hh_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpy($Rs32.h,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_acc_hl_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpy($Rs32.h,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_acc_hl_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpy($Rs32.h,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_acc_lh_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpy($Rs32.l,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_acc_lh_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpy($Rs32.l,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_acc_ll_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpy($Rs32.l,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_acc_ll_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpy($Rs32.l,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_hh_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.h,$Rt32.h)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100000; +let prefersSlot3 = 1; +} +def M2_mpyd_hh_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100100; +let prefersSlot3 = 1; +} +def M2_mpyd_hl_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.h,$Rt32.l)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100000; +let prefersSlot3 = 1; +} +def M2_mpyd_hl_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100100; +let prefersSlot3 = 1; +} +def M2_mpyd_lh_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.l,$Rt32.h)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100000; +let prefersSlot3 = 1; +} +def M2_mpyd_lh_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100100; +let prefersSlot3 = 1; +} +def M2_mpyd_ll_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.l,$Rt32.l)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100000; +let prefersSlot3 = 1; +} +def M2_mpyd_ll_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100100; +let prefersSlot3 = 1; +} +def M2_mpyd_nac_hh_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpy($Rs32.h,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_nac_hh_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpy($Rs32.h,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110101; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_nac_hl_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpy($Rs32.h,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_nac_hl_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpy($Rs32.h,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110101; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_nac_lh_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpy($Rs32.l,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_nac_lh_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpy($Rs32.l,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110101; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_nac_ll_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpy($Rs32.l,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_nac_ll_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpy($Rs32.l,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110101; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyd_rnd_hh_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.h,$Rt32.h):rnd", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100001; +let prefersSlot3 = 1; +} +def M2_mpyd_rnd_hh_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.h,$Rt32.h):<<1:rnd", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100101; +let prefersSlot3 = 1; +} +def M2_mpyd_rnd_hl_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.h,$Rt32.l):rnd", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100001; +let prefersSlot3 = 1; +} +def M2_mpyd_rnd_hl_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.h,$Rt32.l):<<1:rnd", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100101; +let prefersSlot3 = 1; +} +def M2_mpyd_rnd_lh_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.l,$Rt32.h):rnd", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100001; +let prefersSlot3 = 1; +} +def M2_mpyd_rnd_lh_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.l,$Rt32.h):<<1:rnd", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100101; +let prefersSlot3 = 1; +} +def M2_mpyd_rnd_ll_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.l,$Rt32.l):rnd", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100001; +let prefersSlot3 = 1; +} +def M2_mpyd_rnd_ll_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpy($Rs32.l,$Rt32.l):<<1:rnd", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100101; +let prefersSlot3 = 1; +} +def M2_mpyi : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyi($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773, ImmRegRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let CextOpcode = "M2_mpyi"; +let InputType = "reg"; +} +def M2_mpysin : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u8_0Imm:$Ii), +"$Rd32 = -mpyi($Rs32,#$Ii)", +M_tc_3x_SLOT23, TypeM>, Enc_16355964 { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100000100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpysip : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u32_0Imm:$Ii), +"$Rd32 = +mpyi($Rs32,#$Ii)", +M_tc_3x_SLOT23, TypeM>, Enc_16355964 { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100000000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def M2_mpysmi : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, m32_0Imm:$Ii), +"$Rd32 = mpyi($Rs32,#$Ii)", +M_tc_3x_SLOT23, TypeM>, ImmRegRel { +let hasNewValue = 1; +let opNewValue = 0; +let CextOpcode = "M2_mpyi"; +let InputType = "imm"; +let isPseudo = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 9; +let opExtentAlign = 0; +} +def M2_mpysu_up : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpysu($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpyu_acc_hh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpyu($Rs32.h,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_acc_hh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpyu($Rs32.h,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_acc_hl_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpyu($Rs32.h,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_acc_hl_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpyu($Rs32.h,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_acc_lh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpyu($Rs32.l,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_acc_lh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpyu($Rs32.l,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_acc_ll_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpyu($Rs32.l,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_acc_ll_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpyu($Rs32.l,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_hh_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyu($Rs32.h,$Rt32.h)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpyu_hh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyu($Rs32.h,$Rt32.h):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpyu_hl_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyu($Rs32.h,$Rt32.l)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpyu_hl_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyu($Rs32.h,$Rt32.l):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpyu_lh_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyu($Rs32.l,$Rt32.h)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpyu_lh_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyu($Rs32.l,$Rt32.h):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpyu_ll_s0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyu($Rs32.l,$Rt32.l)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpyu_ll_s1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyu($Rs32.l,$Rt32.l):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101100110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpyu_nac_hh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpyu($Rs32.h,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_nac_hh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpyu($Rs32.h,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_nac_hl_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpyu($Rs32.h,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_nac_hl_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpyu($Rs32.h,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_nac_lh_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpyu($Rs32.l,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_nac_lh_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpyu($Rs32.l,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_nac_ll_s0 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpyu($Rs32.l,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_nac_ll_s1 : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpyu($Rs32.l,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101110111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_mpyu_up : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyu($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_mpyud_acc_hh_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpyu($Rs32.h,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_acc_hh_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpyu($Rs32.h,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_acc_hl_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpyu($Rs32.h,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_acc_hl_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpyu($Rs32.h,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_acc_lh_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpyu($Rs32.l,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_acc_lh_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpyu($Rs32.l,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_acc_ll_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpyu($Rs32.l,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_acc_ll_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += mpyu($Rs32.l,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_hh_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpyu($Rs32.h,$Rt32.h)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100010; +let prefersSlot3 = 1; +} +def M2_mpyud_hh_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpyu($Rs32.h,$Rt32.h):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100110; +let prefersSlot3 = 1; +} +def M2_mpyud_hl_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpyu($Rs32.h,$Rt32.l)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100010; +let prefersSlot3 = 1; +} +def M2_mpyud_hl_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpyu($Rs32.h,$Rt32.l):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100110; +let prefersSlot3 = 1; +} +def M2_mpyud_lh_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpyu($Rs32.l,$Rt32.h)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100010; +let prefersSlot3 = 1; +} +def M2_mpyud_lh_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpyu($Rs32.l,$Rt32.h):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100110; +let prefersSlot3 = 1; +} +def M2_mpyud_ll_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpyu($Rs32.l,$Rt32.l)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100010; +let prefersSlot3 = 1; +} +def M2_mpyud_ll_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = mpyu($Rs32.l,$Rt32.l):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100100110; +let prefersSlot3 = 1; +} +def M2_mpyud_nac_hh_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpyu($Rs32.h,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_nac_hh_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpyu($Rs32.h,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110111; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_nac_hl_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpyu($Rs32.h,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_nac_hl_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpyu($Rs32.h,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110111; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_nac_lh_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpyu($Rs32.l,$Rt32.h)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_nac_lh_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpyu($Rs32.l,$Rt32.h):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110111; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_nac_ll_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpyu($Rs32.l,$Rt32.l)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyud_nac_ll_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 -= mpyu($Rs32.l,$Rt32.l):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100110111; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_mpyui : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = mpyui($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def M2_nacci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= add($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_naccii : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rx32 -= add($Rs32,#$Ii)", +M_tc_2_acc_SLOT23, TypeM>, Enc_11522288 { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100010100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_subacc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rt32, IntRegs:$Rs32), +"$Rx32 += sub($Rt32,$Rs32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_7692963 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M2_vabsdiffh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vabsdiffh($Rtt32,$Rss32)", +M_tc_2_SLOT23, TypeM>, Enc_11687333 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000011; +let prefersSlot3 = 1; +} +def M2_vabsdiffw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vabsdiffw($Rtt32,$Rss32)", +M_tc_2_SLOT23, TypeM>, Enc_11687333 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000001; +let prefersSlot3 = 1; +} +def M2_vcmac_s0_sat_i : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vcmpyi($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010010; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vcmac_s0_sat_r : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vcmpyr($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010001; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vcmpy_s0_sat_i : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vcmpyi($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000010; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vcmpy_s0_sat_r : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vcmpyr($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000001; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vcmpy_s1_sat_i : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vcmpyi($Rss32,$Rtt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vcmpy_s1_sat_r : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vcmpyr($Rss32,$Rtt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000101; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vdmacs_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vdmpy($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vdmacs_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vdmpy($Rss32,$Rtt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vdmpyrs_s0 : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = vdmpy($Rss32,$Rtt32):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_9277990 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vdmpyrs_s1 : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = vdmpy($Rss32,$Rtt32):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_9277990 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vdmpys_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vdmpy($Rss32,$Rtt32):sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vdmpys_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vdmpy($Rss32,$Rtt32):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vmac2 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += vmpyh($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vmac2es : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyeh($Rss32,$Rtt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vmac2es_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyeh($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vmac2es_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vmpyeh($Rss32,$Rtt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vmac2s_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += vmpyh($Rs32,$Rt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vmac2s_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += vmpyh($Rs32,$Rt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vmac2su_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += vmpyhsu($Rs32,$Rt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111011; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vmac2su_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += vmpyhsu($Rs32,$Rt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111111; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vmpy2es_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpyeh($Rss32,$Rtt32):sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vmpy2es_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vmpyeh($Rss32,$Rtt32):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vmpy2s_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = vmpyh($Rs32,$Rt32):sat", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vmpy2s_s0pack : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = vmpyh($Rs32,$Rt32):rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vmpy2s_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = vmpyh($Rs32,$Rt32):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vmpy2s_s1pack : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = vmpyh($Rs32,$Rt32):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM>, Enc_14071773 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101101101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vmpy2su_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = vmpyhsu($Rs32,$Rt32):sat", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101000; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vmpy2su_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = vmpyhsu($Rs32,$Rt32):<<1:sat", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101100; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vraddh : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = vraddh($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_9277990 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_vradduh : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = vradduh($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_9277990 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M2_vrcmaci_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrcmpyi($Rss32,$Rtt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vrcmaci_s0c : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrcmpyi($Rss32,$Rtt32*)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vrcmacr_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrcmpyr($Rss32,$Rtt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vrcmacr_s0c : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrcmpyr($Rss32,$Rtt32*)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vrcmpyi_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrcmpyi($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000000; +let prefersSlot3 = 1; +} +def M2_vrcmpyi_s0c : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrcmpyi($Rss32,$Rtt32*)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000010; +let prefersSlot3 = 1; +} +def M2_vrcmpyr_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrcmpyr($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000000; +let prefersSlot3 = 1; +} +def M2_vrcmpyr_s0c : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrcmpyr($Rss32,$Rtt32*)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000011; +let prefersSlot3 = 1; +} +def M2_vrcmpys_acc_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 += vrcmpys($Rss32,$Rt32):<<1:sat", +M_tc_3x_SLOT23, TypeM> { +let isPseudo = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vrcmpys_acc_s1_h : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi", +M_tc_3x_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010101; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vrcmpys_acc_s1_l : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo", +M_tc_3x_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010111; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vrcmpys_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vrcmpys($Rss32,$Rt32):<<1:sat", +M_tc_3x_SLOT23, TypeM> { +let isPseudo = 1; +} +def M2_vrcmpys_s1_h : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:hi", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000101; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vrcmpys_s1_l : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrcmpys($Rss32,$Rtt32):<<1:sat:raw:lo", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000111; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vrcmpys_s1rp : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rd32 = vrcmpys($Rss32,$Rt32):<<1:rnd:sat", +M_tc_3x_SLOT23, TypeM> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +} +def M2_vrcmpys_s1rp_h : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:hi", +M_tc_3x_SLOT23, TypeM>, Enc_9277990 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vrcmpys_s1rp_l : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = vrcmpys($Rss32,$Rtt32):<<1:rnd:sat:raw:lo", +M_tc_3x_SLOT23, TypeM>, Enc_9277990 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101001101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M2_vrmac_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrmpyh($Rss32,$Rtt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M2_vrmpy_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrmpyh($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000000; +let prefersSlot3 = 1; +} +def M2_xor_xacc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 ^= xor($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_and_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 &= and($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_and_andn : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 &= and($Rs32,~$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_and_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 &= or($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_and_xor : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 &= xor($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_cmpyi_wh : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rd32 = cmpyiwh($Rss32,$Rt32):<<1:rnd:sat", +S_3op_tc_3x_SLOT23, TypeS_3op>, Enc_14287645 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000101000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M4_cmpyi_whc : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rd32 = cmpyiwh($Rss32,$Rt32*):<<1:rnd:sat", +S_3op_tc_3x_SLOT23, TypeS_3op>, Enc_14287645, Requires<[HasV5T]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000101000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M4_cmpyr_wh : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rd32 = cmpyrwh($Rss32,$Rt32):<<1:rnd:sat", +S_3op_tc_3x_SLOT23, TypeS_3op>, Enc_14287645 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000101000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M4_cmpyr_whc : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rd32 = cmpyrwh($Rss32,$Rt32*):<<1:rnd:sat", +S_3op_tc_3x_SLOT23, TypeS_3op>, Enc_14287645, Requires<[HasV5T]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000101000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M4_mac_up_s1_sat : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += mpy($Rs32,$Rt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_mpyri_addi : HInst< +(outs IntRegs:$Rd32), +(ins u32_0Imm:$Ii, IntRegs:$Rs32, u6_0Imm:$II), +"$Rd32 = add(#$Ii,mpyi($Rs32,#$II))", +ALU64_tc_3x_SLOT23, TypeALU64>, Enc_971574, ImmRegRel { +let Inst{31-24} = 0b11011000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let CextOpcode = "M4_mpyri_addr"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def M4_mpyri_addr : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Ru32, IntRegs:$Rs32, u32_0Imm:$Ii), +"$Rd32 = add($Ru32,mpyi($Rs32,#$Ii))", +ALU64_tc_3x_SLOT23, TypeALU64>, Enc_236434, ImmRegRel { +let Inst{31-23} = 0b110111111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let CextOpcode = "M4_mpyri_addr"; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def M4_mpyri_addr_u2 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Ru32, u6_2Imm:$Ii, IntRegs:$Rs32), +"$Rd32 = add($Ru32,mpyi(#$Ii,$Rs32))", +ALU64_tc_3x_SLOT23, TypeALU64>, Enc_9959498 { +let Inst{31-23} = 0b110111110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def M4_mpyrr_addi : HInst< +(outs IntRegs:$Rd32), +(ins u32_0Imm:$Ii, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = add(#$Ii,mpyi($Rs32,$Rt32))", +ALU64_tc_3x_SLOT23, TypeALU64>, Enc_2216485, ImmRegRel { +let Inst{31-23} = 0b110101110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let CextOpcode = "M4_mpyrr_addr"; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def M4_mpyrr_addr : HInst< +(outs IntRegs:$Ry32), +(ins IntRegs:$Ru32, IntRegs:$Ry32in, IntRegs:$Rs32), +"$Ry32 = add($Ru32,mpyi($Ry32in,$Rs32))", +M_tc_3x_SLOT23, TypeM>, Enc_13770697, ImmRegRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100011000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let CextOpcode = "M4_mpyrr_addr"; +let InputType = "reg"; +let Constraints = "$Ry32 = $Ry32in"; +} +def M4_nac_up_s1_sat : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= mpy($Rs32,$Rt32):<<1:sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_or_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 |= and($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_or_andn : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 |= and($Rs32,~$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_or_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 |= or($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_or_xor : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 |= xor($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_pmpyw : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = pmpyw($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101010; +let prefersSlot3 = 1; +} +def M4_pmpyw_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 ^= pmpyw($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M4_vpmpyh : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = vpmpyh($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101110; +let prefersSlot3 = 1; +} +def M4_vpmpyh_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 ^= vpmpyh($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111101; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M4_vrmpyeh_acc_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrmpyweh($Rss32,$Rtt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M4_vrmpyeh_acc_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrmpyweh($Rss32,$Rtt32):<<1", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010101; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M4_vrmpyeh_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrmpyweh($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000010; +let prefersSlot3 = 1; +} +def M4_vrmpyeh_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrmpyweh($Rss32,$Rtt32):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000110; +let prefersSlot3 = 1; +} +def M4_vrmpyoh_acc_s0 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrmpywoh($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M4_vrmpyoh_acc_s1 : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrmpywoh($Rss32,$Rtt32):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010111; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M4_vrmpyoh_s0 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrmpywoh($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000001; +let prefersSlot3 = 1; +} +def M4_vrmpyoh_s1 : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrmpywoh($Rss32,$Rtt32):<<1", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000101; +let prefersSlot3 = 1; +} +def M4_xor_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 ^= and($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_xor_andn : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 ^= and($Rs32,~$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_xor_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 ^= or($Rs32,$Rt32)", +M_tc_2_acc_SLOT23, TypeM>, Enc_9223889 { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101111110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "reg"; +let Constraints = "$Rx32 = $Rx32in"; +} +def M4_xor_xacc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 ^= xor($Rss32,$Rtt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_12702821 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001010100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M5_vdmacbsu : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vdmpybsu($Rss32,$Rtt32):sat", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821, Requires<[HasV5T]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010001; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M5_vdmpybsu : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vdmpybsu($Rss32,$Rtt32):sat", +M_tc_3x_SLOT23, TypeM>, Enc_8333157, Requires<[HasV5T]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000101; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def M5_vmacbsu : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += vmpybsu($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M5_vmacbuu : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rxx32 += vmpybu($Rs32,$Rt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_1409050 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100111100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M5_vmpybsu : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = vmpybsu($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101010; +let prefersSlot3 = 1; +} +def M5_vmpybuu : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = vmpybu($Rs32,$Rt32)", +M_tc_3x_SLOT23, TypeM>, Enc_1997594 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11100101100; +let prefersSlot3 = 1; +} +def M5_vrmacbsu : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrmpybsu($Rss32,$Rtt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M5_vrmacbuu : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 += vrmpybu($Rss32,$Rtt32)", +M_tc_3x_acc_SLOT23, TypeM>, Enc_12702821 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101010100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def M5_vrmpybsu : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrmpybsu($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000110; +let prefersSlot3 = 1; +} +def M5_vrmpybuu : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vrmpybu($Rss32,$Rtt32)", +M_tc_3x_SLOT23, TypeM>, Enc_8333157 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000100; +let prefersSlot3 = 1; +} +def M6_vabsdiffb : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vabsdiffb($Rtt32,$Rss32)", +M_tc_2_SLOT23, TypeM>, Enc_11687333, Requires<[HasV62T]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000111; +let prefersSlot3 = 1; +} +def M6_vabsdiffub : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = vabsdiffub($Rtt32,$Rss32)", +M_tc_2_SLOT23, TypeM>, Enc_11687333, Requires<[HasV62T]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11101000101; +let prefersSlot3 = 1; +} +def PS_loadrbabs : HInst< +(outs IntRegs:$Rd32), +(ins u32_0Imm:$Ii), +"$Rd32 = memb(#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1886960, AddrModeRel { +let Inst{24-21} = 0b1000; +let Inst{31-27} = 0b01001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrb"; +let BaseOpcode = "L4_loadrb_abs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 16; +let opExtentAlign = 0; +} +def PS_loadrdabs : HInst< +(outs DoubleRegs:$Rdd32), +(ins u29_3Imm:$Ii), +"$Rdd32 = memd(#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_4975051, AddrModeRel { +let Inst{24-21} = 0b1110; +let Inst{31-27} = 0b01001; +let addrMode = Absolute; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrd"; +let BaseOpcode = "L4_loadrd_abs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 19; +let opExtentAlign = 3; +} +def PS_loadrhabs : HInst< +(outs IntRegs:$Rd32), +(ins u31_1Imm:$Ii), +"$Rd32 = memh(#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_12608570, AddrModeRel { +let Inst{24-21} = 0b1010; +let Inst{31-27} = 0b01001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrh"; +let BaseOpcode = "L4_loadrh_abs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 17; +let opExtentAlign = 1; +} +def PS_loadriabs : HInst< +(outs IntRegs:$Rd32), +(ins u30_2Imm:$Ii), +"$Rd32 = memw(#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_8814718, AddrModeRel { +let Inst{24-21} = 0b1100; +let Inst{31-27} = 0b01001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = WordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadri"; +let BaseOpcode = "L4_loadri_abs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 18; +let opExtentAlign = 2; +} +def PS_loadrubabs : HInst< +(outs IntRegs:$Rd32), +(ins u32_0Imm:$Ii), +"$Rd32 = memub(#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_1886960, AddrModeRel { +let Inst{24-21} = 0b1001; +let Inst{31-27} = 0b01001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadrub"; +let BaseOpcode = "L4_loadrub_abs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 16; +let opExtentAlign = 0; +} +def PS_loadruhabs : HInst< +(outs IntRegs:$Rd32), +(ins u31_1Imm:$Ii), +"$Rd32 = memuh(#$Ii)", +V2LDST_tc_ld_SLOT01, TypeV2LDST>, Enc_12608570, AddrModeRel { +let Inst{24-21} = 0b1011; +let Inst{31-27} = 0b01001; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayLoad = 1; +let CextOpcode = "L2_loadruh"; +let BaseOpcode = "L4_loadruh_abs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 17; +let opExtentAlign = 1; +} +def PS_storerbabs : HInst< +(outs), +(ins u32_0Imm:$Ii, IntRegs:$Rt32), +"memb(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeV2LDST>, Enc_12395768, AddrModeRel { +let Inst{24-21} = 0b0000; +let Inst{31-27} = 0b01001; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerbabs"; +let isPredicable = 1; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 16; +let opExtentAlign = 0; +} +def PS_storerbnewabs : HInst< +(outs), +(ins u32_0Imm:$Ii, IntRegs:$Nt8), +"memb(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeV2LDST>, Enc_4050532, AddrModeRel { +let Inst{12-11} = 0b00; +let Inst{24-21} = 0b0101; +let Inst{31-27} = 0b01001; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerbabs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 16; +let opExtentAlign = 0; +let opNewValue = 1; +} +def PS_storerdabs : HInst< +(outs), +(ins u29_3Imm:$Ii, DoubleRegs:$Rtt32), +"memd(#$Ii) = $Rtt32", +ST_tc_st_SLOT01, TypeV2LDST>, Enc_11682941, AddrModeRel { +let Inst{24-21} = 0b0110; +let Inst{31-27} = 0b01001; +let addrMode = Absolute; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let BaseOpcode = "S2_storerdabs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 19; +let opExtentAlign = 3; +} +def PS_storerfabs : HInst< +(outs), +(ins u31_1Imm:$Ii, IntRegs:$Rt32), +"memh(#$Ii) = $Rt32.h", +ST_tc_st_SLOT01, TypeV2LDST>, Enc_1186018, AddrModeRel { +let Inst{24-21} = 0b0011; +let Inst{31-27} = 0b01001; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let BaseOpcode = "S2_storerfabs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 17; +let opExtentAlign = 1; +} +def PS_storerhabs : HInst< +(outs), +(ins u31_1Imm:$Ii, IntRegs:$Rt32), +"memh(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeV2LDST>, Enc_1186018, AddrModeRel { +let Inst{24-21} = 0b0010; +let Inst{31-27} = 0b01001; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerhabs"; +let isPredicable = 1; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 17; +let opExtentAlign = 1; +} +def PS_storerhnewabs : HInst< +(outs), +(ins u31_1Imm:$Ii, IntRegs:$Nt8), +"memh(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeV2LDST>, Enc_13618890, AddrModeRel { +let Inst{12-11} = 0b01; +let Inst{24-21} = 0b0101; +let Inst{31-27} = 0b01001; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerhabs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 17; +let opExtentAlign = 1; +let opNewValue = 1; +} +def PS_storeriabs : HInst< +(outs), +(ins u30_2Imm:$Ii, IntRegs:$Rt32), +"memw(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeV2LDST>, Enc_15999208, AddrModeRel { +let Inst{24-21} = 0b0100; +let Inst{31-27} = 0b01001; +let addrMode = Absolute; +let accessSize = WordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeriabs"; +let isPredicable = 1; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 18; +let opExtentAlign = 2; +} +def PS_storerinewabs : HInst< +(outs), +(ins u30_2Imm:$Ii, IntRegs:$Nt8), +"memw(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeV2LDST>, Enc_12297800, AddrModeRel { +let Inst{12-11} = 0b10; +let Inst{24-21} = 0b0101; +let Inst{31-27} = 0b01001; +let addrMode = Absolute; +let accessSize = WordAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeriabs"; +let isPredicable = 1; +let DecoderNamespace = "MustExtend"; +let isExtended = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 18; +let opExtentAlign = 2; +let opNewValue = 1; +} +def S2_addasl_rrri : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32, u3_0Imm:$Ii), +"$Rd32 = addasl($Rt32,$Rs32,#$Ii)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_3494181 { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S2_allocframe : HInst< +(outs), +(ins u11_3Imm:$Ii), +"allocframe(#$Ii)", +ST_tc_ld_SLOT0, TypeST>, Enc_15830826 { +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b10100000100; +let Inst{20-16} = 0b11101; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let Uses = [R29, R30, R31]; +let Defs = [R29, R30]; +} +def S2_asl_i_p : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rdd32 = asl($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4231995 { +let Inst{7-5} = 0b010; +let Inst{31-21} = 0b10000000000; +} +def S2_asl_i_p_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 += asl($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b110; +let Inst{31-21} = 0b10000010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asl_i_p_and : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 &= asl($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b010; +let Inst{31-21} = 0b10000010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asl_i_p_nac : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 -= asl($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b010; +let Inst{31-21} = 0b10000010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asl_i_p_or : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 |= asl($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b110; +let Inst{31-21} = 0b10000010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asl_i_p_xacc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 ^= asl($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b010; +let Inst{31-21} = 0b10000010100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asl_i_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = asl($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100000; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_asl_i_r_acc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 += asl($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asl_i_r_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 &= asl($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asl_i_r_nac : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 -= asl($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asl_i_r_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 |= asl($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asl_i_r_sat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = asl($Rs32,#$Ii):sat", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100010; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def S2_asl_i_r_xacc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 ^= asl($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asl_i_vh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), +"$Rdd32 = vaslh($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2082775 { +let Inst{7-5} = 0b010; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b10000000100; +} +def S2_asl_i_vw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u5_0Imm:$Ii), +"$Rdd32 = vaslw($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13201267 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10000000010; +} +def S2_asl_r_p : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = asl($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011100; +} +def S2_asl_r_p_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 += asl($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asl_r_p_and : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 &= asl($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asl_r_p_nac : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 -= asl($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asl_r_p_or : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 |= asl($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asl_r_p_xor : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 ^= asl($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asl_r_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = asl($Rs32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110010; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_asl_r_r_acc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += asl($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asl_r_r_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 &= asl($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asl_r_r_nac : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= asl($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asl_r_r_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 |= asl($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asl_r_r_sat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = asl($Rs32,$Rt32):sat", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110000; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def S2_asl_r_vh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vaslh($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011010; +} +def S2_asl_r_vw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vaslw($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011000; +} +def S2_asr_i_p : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rdd32 = asr($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4231995 { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b10000000000; +} +def S2_asr_i_p_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 += asr($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b100; +let Inst{31-21} = 0b10000010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asr_i_p_and : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 &= asr($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b10000010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asr_i_p_nac : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 -= asr($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b10000010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asr_i_p_or : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 |= asr($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b100; +let Inst{31-21} = 0b10000010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asr_i_p_rnd : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rdd32 = asr($Rss32,#$Ii):rnd", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4231995, Requires<[HasV5T]> { +let Inst{7-5} = 0b111; +let Inst{31-21} = 0b10000000110; +let prefersSlot3 = 1; +} +def S2_asr_i_p_rnd_goodsyntax : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rdd32 = asrrnd($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Requires<[HasV5T]> { +let isPseudo = 1; +} +def S2_asr_i_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = asr($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100000; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_asr_i_r_acc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 += asr($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asr_i_r_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 &= asr($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asr_i_r_nac : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 -= asr($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asr_i_r_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 |= asr($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asr_i_r_rnd : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = asr($Rs32,#$Ii):rnd", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S2_asr_i_r_rnd_goodsyntax : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = asrrnd($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +} +def S2_asr_i_svw_trun : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, u5_0Imm:$Ii), +"$Rd32 = vasrw($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2380082 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001000110; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_asr_i_vh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), +"$Rdd32 = vasrh($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2082775 { +let Inst{7-5} = 0b000; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b10000000100; +} +def S2_asr_i_vw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u5_0Imm:$Ii), +"$Rdd32 = vasrw($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13201267 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10000000010; +} +def S2_asr_r_p : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = asr($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011100; +} +def S2_asr_r_p_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 += asr($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asr_r_p_and : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 &= asr($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asr_r_p_nac : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 -= asr($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asr_r_p_or : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 |= asr($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asr_r_p_xor : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 ^= asr($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_asr_r_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = asr($Rs32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110010; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_asr_r_r_acc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += asr($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asr_r_r_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 &= asr($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asr_r_r_nac : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= asr($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asr_r_r_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 |= asr($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_asr_r_r_sat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = asr($Rs32,$Rt32):sat", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110000; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def S2_asr_r_svw_trun : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rd32 = vasrw($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_14287645 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000101000; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_asr_r_vh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vasrh($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011010; +} +def S2_asr_r_vw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vasrw($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011000; +} +def S2_brev : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = brev($Rs32)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10001100010; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_brevp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = brev($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10000000110; +} +def S2_cabacdecbin : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = decbin($Rss32,$Rtt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001110; +let isPredicateLate = 1; +let prefersSlot3 = 1; +let Defs = [P0]; +} +def S2_cl0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = cl0($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000101; +let Inst{31-21} = 0b10001100000; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_cl0p : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = cl0($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000010; +let Inst{31-21} = 0b10001000010; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_cl1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = cl1($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10001100000; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_cl1p : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = cl1($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10001000010; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_clb : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = clb($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10001100000; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_clbnorm : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = normamt($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000111; +let Inst{31-21} = 0b10001100000; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_clbp : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = clb($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001000010; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_clrbit_i : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = clrbit($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100110; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_clrbit_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = clrbit($Rs32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110100; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_ct0 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = ct0($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10001100010; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_ct0p : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = ct0($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000010; +let Inst{31-21} = 0b10001000111; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_ct1 : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = ct1($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000101; +let Inst{31-21} = 0b10001100010; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_ct1p : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = ct1($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10001000111; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_deinterleave : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = deinterleave($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10000000110; +} +def S2_extractu : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II), +"$Rd32 = extractu($Rs32,#$Ii,#$II)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_11930928 { +let Inst{13-13} = 0b0; +let Inst{31-23} = 0b100011010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S2_extractu_rp : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), +"$Rd32 = extractu($Rs32,$Rtt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_15472748 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001001000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S2_extractup : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II), +"$Rdd32 = extractu($Rss32,#$Ii,#$II)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_9894557 { +let Inst{31-24} = 0b10000001; +let prefersSlot3 = 1; +} +def S2_extractup_rp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = extractu($Rss32,$Rtt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001000; +let prefersSlot3 = 1; +} +def S2_insert : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II), +"$Rx32 = insert($Rs32,#$Ii,#$II)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2880796 { +let Inst{13-13} = 0b0; +let Inst{31-23} = 0b100011110; +let hasNewValue = 1; +let opNewValue = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_insert_rp : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, DoubleRegs:$Rtt32), +"$Rx32 = insert($Rs32,$Rtt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_16311032 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001000000; +let hasNewValue = 1; +let opNewValue = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_insertp : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II), +"$Rxx32 = insert($Rss32,#$Ii,#$II)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_631197 { +let Inst{31-24} = 0b10000011; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_insertp_rp : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rxx32 = insert($Rss32,$Rtt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_12702821 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001010000; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_interleave : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = interleave($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000101; +let Inst{31-21} = 0b10000000110; +} +def S2_lfsp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = lfs($Rss32,$Rtt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001100; +let prefersSlot3 = 1; +} +def S2_lsl_r_p : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = lsl($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011100; +} +def S2_lsl_r_p_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 += lsl($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsl_r_p_and : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 &= lsl($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsl_r_p_nac : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 -= lsl($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsl_r_p_or : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 |= lsl($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsl_r_p_xor : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 ^= lsl($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsl_r_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = lsl($Rs32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110010; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_lsl_r_r_acc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += lsl($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsl_r_r_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 &= lsl($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsl_r_r_nac : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= lsl($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsl_r_r_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 |= lsl($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsl_r_vh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vlslh($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011010; +} +def S2_lsl_r_vw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vlslw($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011000; +} +def S2_lsr_i_p : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rdd32 = lsr($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4231995 { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b10000000000; +} +def S2_lsr_i_p_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 += lsr($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b101; +let Inst{31-21} = 0b10000010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsr_i_p_and : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 &= lsr($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b10000010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsr_i_p_nac : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 -= lsr($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b10000010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsr_i_p_or : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 |= lsr($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b101; +let Inst{31-21} = 0b10000010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsr_i_p_xacc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 ^= lsr($Rss32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8497723 { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b10000010100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsr_i_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = lsr($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100000; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_lsr_i_r_acc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 += lsr($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsr_i_r_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 &= lsr($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsr_i_r_nac : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 -= lsr($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsr_i_r_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 |= lsr($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsr_i_r_xacc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 ^= lsr($Rs32,#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_2410156 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsr_i_vh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), +"$Rdd32 = vlsrh($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2082775 { +let Inst{7-5} = 0b001; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b10000000100; +} +def S2_lsr_i_vw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u5_0Imm:$Ii), +"$Rdd32 = vlsrw($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13201267 { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10000000010; +} +def S2_lsr_r_p : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = lsr($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011100; +} +def S2_lsr_r_p_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 += lsr($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011110; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsr_r_p_and : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 &= lsr($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsr_r_p_nac : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 -= lsr($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsr_r_p_or : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 |= lsr($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsr_r_p_xor : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 ^= lsr($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001011011; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_lsr_r_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = lsr($Rs32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110010; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_lsr_r_r_acc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 += lsr($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsr_r_r_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 &= lsr($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsr_r_r_nac : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 -= lsr($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsr_r_r_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32), +"$Rx32 |= lsr($Rs32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_9223889 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001100000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_lsr_r_vh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vlsrh($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011010; +} +def S2_lsr_r_vw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vlsrw($Rss32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011000; +} +def S2_packhl : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = packhl($Rs32,$Rt32)", +ALU32_3op_tc_1_SLOT0123, TypeALU32_3op>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11110101100; +let InputType = "reg"; +} +def S2_parityp : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rd32 = parity($Rss32,$Rtt32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_9277990 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010000000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S2_pstorerbf_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memb($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_14044877, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000100000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S2_storerb_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S2_pstorerbf_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memb($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_8065534, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayStore = 1; +let BaseOpcode = "S2_storerb_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerbf_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pv4) memb($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_pstorerbfnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memb($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_8065534, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let BaseOpcode = "S2_storerb_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerbnewf_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memb($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_1737833, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b01000100101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S2_storerb_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 3; +} +def S2_pstorerbnewf_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memb($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_2813446, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b0; +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerb_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerbnewf_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if (!$Pv4) memb($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S2_pstorerbnewfnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memb($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_2813446, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerb_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerbnewt_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memb($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_1737833, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b01000000101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S2_storerb_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 3; +} +def S2_pstorerbnewt_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memb($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_2813446, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b0; +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerb_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerbnewt_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if ($Pv4) memb($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S2_pstorerbnewtnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memb($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_2813446, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b100; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerb_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerbt_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memb($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_14044877, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000000000; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S2_storerb_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S2_pstorerbt_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memb($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_8065534, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011000; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayStore = 1; +let BaseOpcode = "S2_storerb_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerbt_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pv4) memb($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_pstorerbtnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memb($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_8065534, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011000; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let BaseOpcode = "S2_storerb_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerdf_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), +"if (!$Pv4) memd($Rs32+#$Ii) = $Rtt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_11049656, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000100110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "imm"; +let BaseOpcode = "S2_storerd_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 9; +let opExtentAlign = 3; +} +def S2_pstorerdf_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), +"if (!$Pv4) memd($Rx32++#$Ii) = $Rtt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11959851, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let BaseOpcode = "S2_storerd_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerdf_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), +"if (!$Pv4) memd($Rs32) = $Rtt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_pstorerdfnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), +"if (!$Pv4.new) memd($Rx32++#$Ii) = $Rtt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11959851, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let BaseOpcode = "S2_storerd_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerdt_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), +"if ($Pv4) memd($Rs32+#$Ii) = $Rtt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_11049656, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000000110; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "imm"; +let BaseOpcode = "S2_storerd_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 9; +let opExtentAlign = 3; +} +def S2_pstorerdt_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), +"if ($Pv4) memd($Rx32++#$Ii) = $Rtt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11959851, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011110; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let BaseOpcode = "S2_storerd_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerdt_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), +"if ($Pv4) memd($Rs32) = $Rtt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_pstorerdtnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), +"if ($Pv4.new) memd($Rx32++#$Ii) = $Rtt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11959851, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011110; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let BaseOpcode = "S2_storerd_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerff_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memh($Rs32+#$Ii) = $Rt32.h", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_10979813, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000100011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "imm"; +let BaseOpcode = "S2_storerf_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def S2_pstorerff_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memh($Rx32++#$Ii) = $Rt32.h", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11065510, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let BaseOpcode = "S2_storerf_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerff_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pv4) memh($Rs32) = $Rt32.h", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_pstorerffnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32.h", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11065510, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let BaseOpcode = "S2_storerf_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerft_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memh($Rs32+#$Ii) = $Rt32.h", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_10979813, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000000011; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "imm"; +let BaseOpcode = "S2_storerf_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def S2_pstorerft_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memh($Rx32++#$Ii) = $Rt32.h", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11065510, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011011; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let BaseOpcode = "S2_storerf_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerft_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pv4) memh($Rs32) = $Rt32.h", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_pstorerftnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32.h", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11065510, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011011; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let BaseOpcode = "S2_storerf_pi"; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerhf_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memh($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_10979813, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000100010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def S2_pstorerhf_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memh($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11065510, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let BaseOpcode = "S2_storerh_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerhf_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pv4) memh($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_pstorerhfnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memh($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11065510, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let BaseOpcode = "S2_storerh_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerhnewf_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memh($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_6154421, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b01; +let Inst{31-21} = 0b01000100101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +let opNewValue = 3; +} +def S2_pstorerhnewf_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memh($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_3813442, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b0; +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerh_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerhnewf_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if (!$Pv4) memh($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S2_pstorerhnewfnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memh($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_3813442, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerh_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerhnewt_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memh($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_6154421, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b01; +let Inst{31-21} = 0b01000000101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +let opNewValue = 3; +} +def S2_pstorerhnewt_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memh($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_3813442, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b0; +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerh_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerhnewt_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if ($Pv4) memh($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S2_pstorerhnewtnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memh($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_3813442, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b101; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerh_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerht_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memh($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_10979813, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000000010; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def S2_pstorerht_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memh($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11065510, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011010; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let BaseOpcode = "S2_storerh_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerht_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pv4) memh($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_pstorerhtnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memh($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11065510, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011010; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let BaseOpcode = "S2_storerh_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerif_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memw($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_8225953, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000100100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def S2_pstorerif_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memw($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_10065510, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayStore = 1; +let BaseOpcode = "S2_storeri_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerif_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pv4) memw($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_pstorerifnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memw($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_10065510, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeri_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerinewf_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memw($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_11224149, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b10; +let Inst{31-21} = 0b01000100101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +let opNewValue = 3; +} +def S2_pstorerinewf_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memw($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_4813442, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b0; +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeri_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerinewf_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if (!$Pv4) memw($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S2_pstorerinewfnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memw($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_4813442, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = WordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeri_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerinewt_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memw($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_11224149, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b10; +let Inst{31-21} = 0b01000000101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +let opNewValue = 3; +} +def S2_pstorerinewt_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memw($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_4813442, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b0; +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeri_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerinewt_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if ($Pv4) memw($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S2_pstorerinewtnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memw($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_4813442, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b110; +let Inst{31-21} = 0b10101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = WordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeri_pi"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerit_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memw($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_8225953, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000000100; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def S2_pstorerit_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memw($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_10065510, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011100; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayStore = 1; +let BaseOpcode = "S2_storeri_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_pstorerit_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pv4) memw($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_pstoreritnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memw($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_10065510, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b10101011100; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let BaseOpcode = "S2_storeri_pi"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_setbit_i : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = setbit($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100110; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_setbit_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = setbit($Rs32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110100; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_shuffeb : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = shuffeb($Rss32,$Rtt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001000; +} +def S2_shuffeh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = shuffeh($Rss32,$Rtt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001000; +} +def S2_shuffob : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = shuffob($Rtt32,$Rss32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_11687333 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001000; +} +def S2_shuffoh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), +"$Rdd32 = shuffoh($Rtt32,$Rss32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_11687333 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001100; +} +def S2_storerb_io : HInst< +(outs), +(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Rt32), +"memb($Rs32+#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_13150110, AddrModeRel { +let Inst{24-21} = 0b1000; +let Inst{31-27} = 0b10100; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S2_storerb_io"; +let isPredicable = 1; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 0; +} +def S2_storerb_pbr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memb($Rx32++$Mu2:brev) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_7255914, AddrModeRel { +let Inst{7-0} = 0b00000000; +let Inst{31-21} = 0b10101111000; +let accessSize = ByteAccess; +let mayStore = 1; +let BaseOpcode = "S2_storerb_pbr"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerb_pci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), +"memb($Rx32++#$Ii:circ($Mu2)) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_3915770 { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{31-21} = 0b10101001000; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayStore = 1; +let Uses = [CS]; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerb_pcr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memb($Rx32++I:circ($Mu2)) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_7255914 { +let Inst{7-0} = 0b00000010; +let Inst{31-21} = 0b10101001000; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayStore = 1; +let Uses = [CS]; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerb_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Rt32), +"memb($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_12492533, AddrModeRel { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10101011000; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayStore = 1; +let BaseOpcode = "S2_storerb_pi"; +let isPredicable = 1; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerb_pr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memb($Rx32++$Mu2) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_7255914 { +let Inst{7-0} = 0b00000000; +let Inst{31-21} = 0b10101101000; +let addrMode = PostInc; +let accessSize = ByteAccess; +let mayStore = 1; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerb_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memb($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_storerbgp : HInst< +(outs), +(ins u32_0Imm:$Ii, IntRegs:$Rt32), +"memb(gp+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_12395768, AddrModeRel { +let Inst{24-21} = 0b0000; +let Inst{31-27} = 0b01001; +let accessSize = ByteAccess; +let mayStore = 1; +let Uses = [GP]; +let BaseOpcode = "S2_storerbabs"; +let isPredicable = 1; +let isNVStorable = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 16; +let opExtentAlign = 0; +} +def S2_storerbnew_io : HInst< +(outs), +(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Nt8), +"memb($Rs32+#$Ii) = $Nt8.new", +ST_tc_st_SLOT0, TypeST>, Enc_10002182, AddrModeRel { +let Inst{12-11} = 0b00; +let Inst{24-21} = 0b1101; +let Inst{31-27} = 0b10100; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S2_storerb_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 11; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S2_storerbnew_pbr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), +"memb($Rx32++$Mu2:brev) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_10067774, AddrModeRel { +let Inst{7-0} = 0b00000000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b10101111101; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "S2_storerb_pbr"; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerbnew_pci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8), +"memb($Rx32++#$Ii:circ($Mu2)) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_5326450 { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b10101001101; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let Uses = [CS]; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerbnew_pcr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), +"memb($Rx32++I:circ($Mu2)) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_10067774 { +let Inst{7-0} = 0b00000010; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b10101001101; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let Uses = [CS]; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerbnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_0Imm:$Ii, IntRegs:$Nt8), +"memb($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_5900401, AddrModeRel { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b10101011101; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "S2_storerb_pi"; +let isPredicable = 1; +let isNVStorable = 1; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerbnew_pr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), +"memb($Rx32++$Mu2) = $Nt8.new", +ST_tc_st_SLOT0, TypeST>, Enc_10067774 { +let Inst{7-0} = 0b00000000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b10101101101; +let addrMode = PostInc; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerbnew_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Nt8), +"memb($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 1; +} +def S2_storerbnewgp : HInst< +(outs), +(ins u32_0Imm:$Ii, IntRegs:$Nt8), +"memb(gp+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_4050532, AddrModeRel { +let Inst{12-11} = 0b00; +let Inst{24-21} = 0b0101; +let Inst{31-27} = 0b01001; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let Uses = [GP]; +let BaseOpcode = "S2_storerbabs"; +let isPredicable = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 16; +let opExtentAlign = 0; +let opNewValue = 1; +} +def S2_storerd_io : HInst< +(outs), +(ins IntRegs:$Rs32, s29_3Imm:$Ii, DoubleRegs:$Rtt32), +"memd($Rs32+#$Ii) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_16319737, AddrModeRel { +let Inst{24-21} = 0b1110; +let Inst{31-27} = 0b10100; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "imm"; +let BaseOpcode = "S2_storerd_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 14; +let opExtentAlign = 3; +} +def S2_storerd_pbr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32), +"memd($Rx32++$Mu2:brev) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_15816255 { +let Inst{7-0} = 0b00000000; +let Inst{31-21} = 0b10101111110; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerd_pci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_3Imm:$Ii, ModRegs:$Mu2, DoubleRegs:$Rtt32), +"memd($Rx32++#$Ii:circ($Mu2)) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_4501395 { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{31-21} = 0b10101001110; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerd_pcr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32), +"memd($Rx32++I:circ($Mu2)) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_15816255 { +let Inst{7-0} = 0b00000010; +let Inst{31-21} = 0b10101001110; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerd_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_3Imm:$Ii, DoubleRegs:$Rtt32), +"memd($Rx32++#$Ii) = $Rtt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11271630, AddrModeRel { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10101011110; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let BaseOpcode = "S2_storerd_pi"; +let isPredicable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerd_pr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, DoubleRegs:$Rtt32), +"memd($Rx32++$Mu2) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_15816255 { +let Inst{7-0} = 0b00000000; +let Inst{31-21} = 0b10101101110; +let addrMode = PostInc; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerd_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), +"memd($Rs32) = $Rtt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_storerdgp : HInst< +(outs), +(ins u29_3Imm:$Ii, DoubleRegs:$Rtt32), +"memd(gp+#$Ii) = $Rtt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_11682941, AddrModeRel { +let Inst{24-21} = 0b0110; +let Inst{31-27} = 0b01001; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let Uses = [GP]; +let BaseOpcode = "S2_storerdabs"; +let isPredicable = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 19; +let opExtentAlign = 3; +} +def S2_storerf_io : HInst< +(outs), +(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32), +"memh($Rs32+#$Ii) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_7736768, AddrModeRel { +let Inst{24-21} = 0b1011; +let Inst{31-27} = 0b10100; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "imm"; +let BaseOpcode = "S2_storerf_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +} +def S2_storerf_pbr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memh($Rx32++$Mu2:brev) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_7255914 { +let Inst{7-0} = 0b00000000; +let Inst{31-21} = 0b10101111011; +let accessSize = HalfWordAccess; +let mayStore = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerf_pci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), +"memh($Rx32++#$Ii:circ($Mu2)) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_10915758 { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{31-21} = 0b10101001011; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerf_pcr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memh($Rx32++I:circ($Mu2)) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_7255914 { +let Inst{7-0} = 0b00000010; +let Inst{31-21} = 0b10101001011; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let Uses = [CS]; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerf_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), +"memh($Rx32++#$Ii) = $Rt32.h", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11492529, AddrModeRel { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10101011011; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let BaseOpcode = "S2_storerf_pi"; +let isPredicable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerf_pr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memh($Rx32++$Mu2) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_7255914 { +let Inst{7-0} = 0b00000000; +let Inst{31-21} = 0b10101101011; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerf_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memh($Rs32) = $Rt32.h", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_storerfgp : HInst< +(outs), +(ins u31_1Imm:$Ii, IntRegs:$Rt32), +"memh(gp+#$Ii) = $Rt32.h", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_1186018, AddrModeRel { +let Inst{24-21} = 0b0011; +let Inst{31-27} = 0b01001; +let accessSize = HalfWordAccess; +let mayStore = 1; +let Uses = [GP]; +let BaseOpcode = "S2_storerfabs"; +let isPredicable = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 17; +let opExtentAlign = 1; +} +def S2_storerh_io : HInst< +(outs), +(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Rt32), +"memh($Rs32+#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_7736768, AddrModeRel { +let Inst{24-21} = 0b1010; +let Inst{31-27} = 0b10100; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_io"; +let isPredicable = 1; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +} +def S2_storerh_pbr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memh($Rx32++$Mu2:brev) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_7255914, AddrModeRel { +let Inst{7-0} = 0b00000000; +let Inst{31-21} = 0b10101111010; +let accessSize = HalfWordAccess; +let mayStore = 1; +let BaseOpcode = "S2_storerh_pbr"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerh_pci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), +"memh($Rx32++#$Ii:circ($Mu2)) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_10915758 { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{31-21} = 0b10101001010; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let Uses = [CS]; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerh_pcr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memh($Rx32++I:circ($Mu2)) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_7255914 { +let Inst{7-0} = 0b00000010; +let Inst{31-21} = 0b10101001010; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let Uses = [CS]; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerh_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Rt32), +"memh($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_11492529, AddrModeRel { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10101011010; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let BaseOpcode = "S2_storerh_pi"; +let isPredicable = 1; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerh_pr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memh($Rx32++$Mu2) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_7255914 { +let Inst{7-0} = 0b00000000; +let Inst{31-21} = 0b10101101010; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let mayStore = 1; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerh_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memh($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_storerhgp : HInst< +(outs), +(ins u31_1Imm:$Ii, IntRegs:$Rt32), +"memh(gp+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_1186018, AddrModeRel { +let Inst{24-21} = 0b0010; +let Inst{31-27} = 0b01001; +let accessSize = HalfWordAccess; +let mayStore = 1; +let Uses = [GP]; +let BaseOpcode = "S2_storerhabs"; +let isPredicable = 1; +let isNVStorable = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 17; +let opExtentAlign = 1; +} +def S2_storerhnew_io : HInst< +(outs), +(ins IntRegs:$Rs32, s31_1Imm:$Ii, IntRegs:$Nt8), +"memh($Rs32+#$Ii) = $Nt8.new", +ST_tc_st_SLOT0, TypeST>, Enc_748676, AddrModeRel { +let Inst{12-11} = 0b01; +let Inst{24-21} = 0b1101; +let Inst{31-27} = 0b10100; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 12; +let opExtentAlign = 1; +let opNewValue = 2; +} +def S2_storerhnew_pbr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), +"memh($Rx32++$Mu2:brev) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_10067774, AddrModeRel { +let Inst{7-0} = 0b00000000; +let Inst{12-11} = 0b01; +let Inst{31-21} = 0b10101111101; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "S2_storerh_pbr"; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerhnew_pci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8), +"memh($Rx32++#$Ii:circ($Mu2)) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_10326434 { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{12-11} = 0b01; +let Inst{31-21} = 0b10101001101; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let Uses = [CS]; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerhnew_pcr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), +"memh($Rx32++I:circ($Mu2)) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_10067774 { +let Inst{7-0} = 0b00000010; +let Inst{12-11} = 0b01; +let Inst{31-21} = 0b10101001101; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let Uses = [CS]; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerhnew_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_1Imm:$Ii, IntRegs:$Nt8), +"memh($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_6900405, AddrModeRel { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{13-11} = 0b001; +let Inst{31-21} = 0b10101011101; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "S2_storerh_pi"; +let isNVStorable = 1; +let isPredicable = 1; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerhnew_pr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), +"memh($Rx32++$Mu2) = $Nt8.new", +ST_tc_st_SLOT0, TypeST>, Enc_10067774 { +let Inst{7-0} = 0b00000000; +let Inst{12-11} = 0b01; +let Inst{31-21} = 0b10101101101; +let addrMode = PostInc; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerhnew_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Nt8), +"memh($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 1; +} +def S2_storerhnewgp : HInst< +(outs), +(ins u31_1Imm:$Ii, IntRegs:$Nt8), +"memh(gp+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_13618890, AddrModeRel { +let Inst{12-11} = 0b01; +let Inst{24-21} = 0b0101; +let Inst{31-27} = 0b01001; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let Uses = [GP]; +let BaseOpcode = "S2_storerhabs"; +let isPredicable = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 17; +let opExtentAlign = 1; +let opNewValue = 1; +} +def S2_storeri_io : HInst< +(outs), +(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Rt32), +"memw($Rs32+#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_6673186, AddrModeRel { +let Inst{24-21} = 0b1100; +let Inst{31-27} = 0b10100; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_io"; +let isPredicable = 1; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 13; +let opExtentAlign = 2; +} +def S2_storeri_pbr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memw($Rx32++$Mu2:brev) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_7255914, AddrModeRel { +let Inst{7-0} = 0b00000000; +let Inst{31-21} = 0b10101111100; +let accessSize = WordAccess; +let mayStore = 1; +let BaseOpcode = "S2_storeri_pbr"; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storeri_pci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Rt32), +"memw($Rx32++#$Ii:circ($Mu2)) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_9915754 { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{31-21} = 0b10101001100; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayStore = 1; +let Uses = [CS]; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storeri_pcr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memw($Rx32++I:circ($Mu2)) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_7255914 { +let Inst{7-0} = 0b00000010; +let Inst{31-21} = 0b10101001100; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayStore = 1; +let Uses = [CS]; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storeri_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Rt32), +"memw($Rx32++#$Ii) = $Rt32", +ST_tc_st_pi_SLOT01, TypeST>, Enc_10492541, AddrModeRel { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10101011100; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayStore = 1; +let BaseOpcode = "S2_storeri_pi"; +let isPredicable = 1; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storeri_pr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Rt32), +"memw($Rx32++$Mu2) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_7255914 { +let Inst{7-0} = 0b00000000; +let Inst{31-21} = 0b10101101100; +let addrMode = PostInc; +let accessSize = WordAccess; +let mayStore = 1; +let isNVStorable = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storeri_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memw($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S2_storerigp : HInst< +(outs), +(ins u30_2Imm:$Ii, IntRegs:$Rt32), +"memw(gp+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_15999208, AddrModeRel { +let Inst{24-21} = 0b0100; +let Inst{31-27} = 0b01001; +let accessSize = WordAccess; +let mayStore = 1; +let Uses = [GP]; +let BaseOpcode = "S2_storeriabs"; +let isPredicable = 1; +let isNVStorable = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 18; +let opExtentAlign = 2; +} +def S2_storerinew_io : HInst< +(outs), +(ins IntRegs:$Rs32, s30_2Imm:$Ii, IntRegs:$Nt8), +"memw($Rs32+#$Ii) = $Nt8.new", +ST_tc_st_SLOT0, TypeST>, Enc_8409782, AddrModeRel { +let Inst{12-11} = 0b10; +let Inst{24-21} = 0b1101; +let Inst{31-27} = 0b10100; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 1; +let opExtentBits = 13; +let opExtentAlign = 2; +let opNewValue = 2; +} +def S2_storerinew_pbr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), +"memw($Rx32++$Mu2:brev) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_10067774, AddrModeRel { +let Inst{7-0} = 0b00000000; +let Inst{12-11} = 0b10; +let Inst{31-21} = 0b10101111101; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "S2_storeri_pbr"; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerinew_pci : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_2Imm:$Ii, ModRegs:$Mu2, IntRegs:$Nt8), +"memw($Rx32++#$Ii:circ($Mu2)) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_11326438 { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{12-11} = 0b10; +let Inst{31-21} = 0b10101001101; +let addrMode = PostInc; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let Uses = [CS]; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerinew_pcr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), +"memw($Rx32++I:circ($Mu2)) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_10067774 { +let Inst{7-0} = 0b00000010; +let Inst{12-11} = 0b10; +let Inst{31-21} = 0b10101001101; +let addrMode = PostInc; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let Uses = [CS]; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerinew_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s4_2Imm:$Ii, IntRegs:$Nt8), +"memw($Rx32++#$Ii) = $Nt8.new", +ST_tc_st_pi_SLOT0, TypeST>, Enc_7900405, AddrModeRel { +let Inst{2-0} = 0b000; +let Inst{7-7} = 0b0; +let Inst{13-11} = 0b010; +let Inst{31-21} = 0b10101011101; +let addrMode = PostInc; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "S2_storeri_pi"; +let isPredicable = 1; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerinew_pr : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Nt8), +"memw($Rx32++$Mu2) = $Nt8.new", +ST_tc_st_SLOT0, TypeST>, Enc_10067774 { +let Inst{7-0} = 0b00000000; +let Inst{12-11} = 0b10; +let Inst{31-21} = 0b10101101101; +let addrMode = PostInc; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_storerinew_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Nt8), +"memw($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 1; +} +def S2_storerinewgp : HInst< +(outs), +(ins u30_2Imm:$Ii, IntRegs:$Nt8), +"memw(gp+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_12297800, AddrModeRel { +let Inst{12-11} = 0b10; +let Inst{24-21} = 0b0101; +let Inst{31-27} = 0b01001; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let Uses = [GP]; +let BaseOpcode = "S2_storeriabs"; +let isPredicable = 1; +let opExtendable = 0; +let isExtentSigned = 0; +let opExtentBits = 18; +let opExtentAlign = 2; +let opNewValue = 1; +} +def S2_storew_locked : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"memw_locked($Rs32,$Pd4) = $Rt32", +ST_tc_ld_SLOT0, TypeST>, Enc_10157519 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10100000101; +let accessSize = WordAccess; +let isSoloAX = 1; +let mayStore = 1; +let isPredicateLate = 1; +} +def S2_svsathb : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = vsathb($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001100100; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def S2_svsathub : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = vsathub($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000010; +let Inst{31-21} = 0b10001100100; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def S2_tableidxb : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), +"$Rx32 = tableidxb($Rs32,#$Ii,#$II):raw", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_8838398 { +let Inst{31-22} = 0b1000011100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_tableidxb_goodsyntax : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), +"$Rx32 = tableidxb($Rs32,#$Ii,#$II)", +S_2op_tc_1_SLOT23, TypeS_2op> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_tableidxd : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), +"$Rx32 = tableidxd($Rs32,#$Ii,#$II):raw", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_8838398 { +let Inst{31-22} = 0b1000011111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_tableidxd_goodsyntax : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), +"$Rx32 = tableidxd($Rs32,#$Ii,#$II)", +S_2op_tc_1_SLOT23, TypeS_2op> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_tableidxh : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), +"$Rx32 = tableidxh($Rs32,#$Ii,#$II):raw", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_8838398 { +let Inst{31-22} = 0b1000011101; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_tableidxh_goodsyntax : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), +"$Rx32 = tableidxh($Rs32,#$Ii,#$II)", +S_2op_tc_1_SLOT23, TypeS_2op> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_tableidxw : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, s6_0Imm:$II), +"$Rx32 = tableidxw($Rs32,#$Ii,#$II):raw", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_8838398 { +let Inst{31-22} = 0b1000011110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_tableidxw_goodsyntax : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II), +"$Rx32 = tableidxw($Rs32,#$Ii,#$II)", +S_2op_tc_1_SLOT23, TypeS_2op> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S2_togglebit_i : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = togglebit($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2771456 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100110; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_togglebit_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = togglebit($Rs32,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_14071773 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110100; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_tstbit_i : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Pd4 = tstbit($Rs32,#$Ii)", +S_2op_tc_2early_SLOT23, TypeS_2op>, Enc_2103742 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10000101000; +} +def S2_tstbit_r : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = tstbit($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111000; +} +def S2_valignib : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, u3_0Imm:$Ii), +"$Rdd32 = valignb($Rtt32,$Rss32,#$Ii)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_11971407 { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000000000; +} +def S2_valignrb : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32, PredRegs:$Pu4), +"$Rdd32 = valignb($Rtt32,$Rss32,$Pu4)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_11552785 { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000010000; +} +def S2_vcnegh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vcnegh($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def S2_vcrotate : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rdd32 = vcrotate($Rss32,$Rt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8940892 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000011110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def S2_vrcnegh : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32), +"$Rxx32 += vrcnegh($Rss32,$Rt32)", +S_3op_tc_3x_SLOT23, TypeS_3op>, Enc_7912540 { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b11001011001; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S2_vrndpackwh : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = vrndwh($Rss32)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10001000100; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_vrndpackwhs : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = vrndwh($Rss32):sat", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10001000100; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def S2_vsathb : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = vsathb($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10001000000; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def S2_vsathb_nopack : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = vsathb($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000111; +let Inst{31-21} = 0b10000000000; +let Defs = [USR_OVF]; +} +def S2_vsathub : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = vsathub($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001000000; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def S2_vsathub_nopack : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = vsathub($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10000000000; +let Defs = [USR_OVF]; +} +def S2_vsatwh : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = vsatwh($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000010; +let Inst{31-21} = 0b10001000000; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def S2_vsatwh_nopack : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = vsatwh($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10000000000; +let Defs = [USR_OVF]; +} +def S2_vsatwuh : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = vsatwuh($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10001000000; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def S2_vsatwuh_nopack : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32), +"$Rdd32 = vsatwuh($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_13133231 { +let Inst{13-5} = 0b000000101; +let Inst{31-21} = 0b10000000000; +let Defs = [USR_OVF]; +} +def S2_vsplatrb : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32), +"$Rd32 = vsplatb($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4075554 { +let Inst{13-5} = 0b000000111; +let Inst{31-21} = 0b10001100010; +let hasNewValue = 1; +let opNewValue = 0; +let isReMaterializable = 1; +let isAsCheapAsAMove = 1; +} +def S2_vsplatrh : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = vsplath($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4030179 { +let Inst{13-5} = 0b000000010; +let Inst{31-21} = 0b10000100010; +let isReMaterializable = 1; +let isAsCheapAsAMove = 1; +} +def S2_vspliceib : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, u3_0Imm:$Ii), +"$Rdd32 = vspliceb($Rss32,$Rtt32,#$Ii)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_16730127 { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000000100; +} +def S2_vsplicerb : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Pu4), +"$Rdd32 = vspliceb($Rss32,$Rtt32,$Pu4)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_5178985 { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000010100; +} +def S2_vsxtbh : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = vsxtbh($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4030179 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10000100000; +let isReMaterializable = 1; +let isAsCheapAsAMove = 1; +} +def S2_vsxthw : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = vsxthw($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4030179 { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10000100000; +let isReMaterializable = 1; +let isAsCheapAsAMove = 1; +} +def S2_vtrunehb : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = vtrunehb($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000010; +let Inst{31-21} = 0b10001000100; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_vtrunewh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vtrunewh($Rss32,$Rtt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001100; +} +def S2_vtrunohb : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = vtrunohb($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001000100; +let hasNewValue = 1; +let opNewValue = 0; +} +def S2_vtrunowh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vtrunowh($Rss32,$Rtt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001100; +} +def S2_vzxtbh : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = vzxtbh($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4030179 { +let Inst{13-5} = 0b000000010; +let Inst{31-21} = 0b10000100000; +let isReMaterializable = 1; +let isAsCheapAsAMove = 1; +} +def S2_vzxthw : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = vzxthw($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4030179 { +let Inst{13-5} = 0b000000110; +let Inst{31-21} = 0b10000100000; +let isReMaterializable = 1; +let isAsCheapAsAMove = 1; +} +def S4_addaddi : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Ru32, s32_0Imm:$Ii), +"$Rd32 = add($Rs32,add($Ru32,#$Ii))", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_6495334 { +let Inst{31-23} = 0b110110110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_addi_asl_ri : HInst< +(outs IntRegs:$Rx32), +(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), +"$Rx32 = add(#$Ii,asl($Rx32in,#$II))", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_117962 { +let Inst{2-0} = 0b100; +let Inst{4-4} = 0b0; +let Inst{31-24} = 0b11011110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_addi_lsr_ri : HInst< +(outs IntRegs:$Rx32), +(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), +"$Rx32 = add(#$Ii,lsr($Rx32in,#$II))", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_117962 { +let Inst{2-0} = 0b100; +let Inst{4-4} = 0b1; +let Inst{31-24} = 0b11011110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_andi_asl_ri : HInst< +(outs IntRegs:$Rx32), +(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), +"$Rx32 = and(#$Ii,asl($Rx32in,#$II))", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_117962 { +let Inst{2-0} = 0b000; +let Inst{4-4} = 0b0; +let Inst{31-24} = 0b11011110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_andi_lsr_ri : HInst< +(outs IntRegs:$Rx32), +(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), +"$Rx32 = and(#$Ii,lsr($Rx32in,#$II))", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_117962 { +let Inst{2-0} = 0b000; +let Inst{4-4} = 0b1; +let Inst{31-24} = 0b11011110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_clbaddi : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s6_0Imm:$Ii), +"$Rd32 = add(clb($Rs32),#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_5523416 { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b10001100001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S4_clbpaddi : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, s6_0Imm:$Ii), +"$Rd32 = add(clb($Rss32),#$Ii)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_10188026 { +let Inst{7-5} = 0b010; +let Inst{31-21} = 0b10001000011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S4_clbpnorm : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = normamt($Rss32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_3742184 { +let Inst{13-5} = 0b000000000; +let Inst{31-21} = 0b10001000011; +let hasNewValue = 1; +let opNewValue = 0; +} +def S4_extract : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii, u5_0Imm:$II), +"$Rd32 = extract($Rs32,#$Ii,#$II)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_11930928 { +let Inst{13-13} = 0b0; +let Inst{31-23} = 0b100011011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S4_extract_rp : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), +"$Rd32 = extract($Rs32,$Rtt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_15472748 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11001001000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S4_extractp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u6_0Imm:$Ii, u6_0Imm:$II), +"$Rdd32 = extract($Rss32,#$Ii,#$II)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_9894557 { +let Inst{31-24} = 0b10001010; +let prefersSlot3 = 1; +} +def S4_extractp_rp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = extract($Rss32,$Rtt32)", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001110; +let prefersSlot3 = 1; +} +def S4_lsli : HInst< +(outs IntRegs:$Rd32), +(ins s6_0Imm:$Ii, IntRegs:$Rt32), +"$Rd32 = lsl(#$Ii,$Rt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_518319 { +let Inst{7-6} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000110100; +let hasNewValue = 1; +let opNewValue = 0; +} +def S4_ntstbit_i : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Pd4 = !tstbit($Rs32,#$Ii)", +S_2op_tc_2early_SLOT23, TypeS_2op>, Enc_2103742 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10000101001; +} +def S4_ntstbit_r : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Pd4 = !tstbit($Rs32,$Rt32)", +S_3op_tc_2early_SLOT23, TypeS_3op>, Enc_10157519 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000111001; +} +def S4_or_andi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rx32 |= and($Rs32,#$Ii)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_6356866 { +let Inst{31-22} = 0b1101101000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_or_andix : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Ru32, IntRegs:$Rx32in, s32_0Imm:$Ii), +"$Rx32 = or($Ru32,and($Rx32in,#$Ii))", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_7504828 { +let Inst{31-22} = 0b1101101001; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_or_ori : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, s32_0Imm:$Ii), +"$Rx32 |= or($Rs32,#$Ii)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_6356866 { +let Inst{31-22} = 0b1101101010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let InputType = "imm"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 10; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_ori_asl_ri : HInst< +(outs IntRegs:$Rx32), +(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), +"$Rx32 = or(#$Ii,asl($Rx32in,#$II))", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_117962 { +let Inst{2-0} = 0b010; +let Inst{4-4} = 0b0; +let Inst{31-24} = 0b11011110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_ori_lsr_ri : HInst< +(outs IntRegs:$Rx32), +(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), +"$Rx32 = or(#$Ii,lsr($Rx32in,#$II))", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_117962 { +let Inst{2-0} = 0b010; +let Inst{4-4} = 0b1; +let Inst{31-24} = 0b11011110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_parity : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = parity($Rs32,$Rt32)", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S4_pstorerbf_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memb(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-18} = 0b10101111000000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerbabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerbf_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110101000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "reg"; +let BaseOpcode = "S4_storerb_rr"; +let isNVStorable = 1; +} +def S4_pstorerbfnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memb(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-18} = 0b10101111000000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerbabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerbfnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memb($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_14044877, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000110000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S2_storerb_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerbfnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110111000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "reg"; +let BaseOpcode = "S4_storerb_rr"; +let isNVStorable = 1; +} +def S4_pstorerbfnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pv4.new) memb($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_pstorerbnewf_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memb(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b000; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerbabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerbnewf_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b00; +let Inst{31-21} = 0b00110101101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let InputType = "reg"; +let BaseOpcode = "S4_storerb_rr"; +let opNewValue = 4; +} +def S4_pstorerbnewfnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memb(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b100; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isNVStore = 1; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerbabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerbnewfnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memb($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_1737833, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b01000110101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S2_storerb_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 3; +} +def S4_pstorerbnewfnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b00; +let Inst{31-21} = 0b00110111101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let InputType = "reg"; +let BaseOpcode = "S4_storerb_rr"; +let opNewValue = 4; +} +def S4_pstorerbnewfnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if (!$Pv4.new) memb($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S4_pstorerbnewt_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memb(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b000; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerbabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerbnewt_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b00; +let Inst{31-21} = 0b00110100101; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let InputType = "reg"; +let BaseOpcode = "S4_storerb_rr"; +let opNewValue = 4; +} +def S4_pstorerbnewtnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memb(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b100; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isNVStore = 1; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerbabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerbnewtnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memb($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_1737833, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b01000010101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S2_storerb_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 3; +} +def S4_pstorerbnewtnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b00; +let Inst{31-21} = 0b00110110101; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let InputType = "reg"; +let BaseOpcode = "S4_storerb_rr"; +let opNewValue = 4; +} +def S4_pstorerbnewtnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if ($Pv4.new) memb($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S4_pstorerbt_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memb(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-18} = 0b10101111000000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerbabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerbt_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memb($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110100000; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "reg"; +let BaseOpcode = "S4_storerb_rr"; +let isNVStorable = 1; +} +def S4_pstorerbtnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memb(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-18} = 0b10101111000000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = ByteAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S2_storerbabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerbtnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u32_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memb($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_14044877, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000010000; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S2_storerb_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerbtnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memb($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110110000; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "reg"; +let BaseOpcode = "S4_storerb_rr"; +let isNVStorable = 1; +} +def S4_pstorerbtnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pv4.new) memb($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_pstorerdf_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), +"if (!$Pv4) memd(#$Ii) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_13715847, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-18} = 0b10101111110000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let BaseOpcode = "S2_storerdabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerdf_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), +"if (!$Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_9920336, AddrModeRel { +let Inst{31-21} = 0b00110101110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "reg"; +let BaseOpcode = "S2_storerd_rr"; +} +def S4_pstorerdfnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), +"if (!$Pv4.new) memd(#$Ii) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_13715847, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-18} = 0b10101111110000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let BaseOpcode = "S2_storerdabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerdfnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), +"if (!$Pv4.new) memd($Rs32+#$Ii) = $Rtt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_11049656, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000110110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "imm"; +let BaseOpcode = "S2_storerd_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 9; +let opExtentAlign = 3; +} +def S4_pstorerdfnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), +"if (!$Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_9920336, AddrModeRel { +let Inst{31-21} = 0b00110111110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "reg"; +let BaseOpcode = "S2_storerd_rr"; +} +def S4_pstorerdfnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), +"if (!$Pv4.new) memd($Rs32) = $Rtt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_pstorerdt_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), +"if ($Pv4) memd(#$Ii) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_13715847, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-18} = 0b10101111110000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let BaseOpcode = "S2_storerdabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerdt_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), +"if ($Pv4) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_9920336, AddrModeRel { +let Inst{31-21} = 0b00110100110; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "reg"; +let BaseOpcode = "S2_storerd_rr"; +} +def S4_pstorerdtnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, DoubleRegs:$Rtt32), +"if ($Pv4.new) memd(#$Ii) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_13715847, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-18} = 0b10101111110000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let BaseOpcode = "S2_storerdabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerdtnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u29_3Imm:$Ii, DoubleRegs:$Rtt32), +"if ($Pv4.new) memd($Rs32+#$Ii) = $Rtt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_11049656, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000010110; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "imm"; +let BaseOpcode = "S2_storerd_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 9; +let opExtentAlign = 3; +} +def S4_pstorerdtnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), +"if ($Pv4.new) memd($Rs32+$Ru32<<#$Ii) = $Rtt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_9920336, AddrModeRel { +let Inst{31-21} = 0b00110110110; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = DoubleWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "reg"; +let BaseOpcode = "S2_storerd_rr"; +} +def S4_pstorerdtnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, DoubleRegs:$Rtt32), +"if ($Pv4.new) memd($Rs32) = $Rtt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_pstorerff_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memh(#$Ii) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-18} = 0b10101111011000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let BaseOpcode = "S2_storerfabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerff_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110101011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "reg"; +let BaseOpcode = "S4_storerf_rr"; +} +def S4_pstorerffnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memh(#$Ii) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-18} = 0b10101111011000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let BaseOpcode = "S2_storerfabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerffnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32.h", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_10979813, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000110011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "imm"; +let BaseOpcode = "S2_storerf_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def S4_pstorerffnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110111011; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "reg"; +let BaseOpcode = "S4_storerf_rr"; +} +def S4_pstorerffnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pv4.new) memh($Rs32) = $Rt32.h", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_pstorerft_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memh(#$Ii) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-18} = 0b10101111011000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let BaseOpcode = "S2_storerfabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerft_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110100011; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "reg"; +let BaseOpcode = "S4_storerf_rr"; +} +def S4_pstorerftnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memh(#$Ii) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-18} = 0b10101111011000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let BaseOpcode = "S2_storerfabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerftnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32.h", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_10979813, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000010011; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "imm"; +let BaseOpcode = "S2_storerf_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def S4_pstorerftnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110110011; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "reg"; +let BaseOpcode = "S4_storerf_rr"; +} +def S4_pstorerftnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pv4.new) memh($Rs32) = $Rt32.h", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_pstorerhf_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memh(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-18} = 0b10101111010000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerhabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerhf_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110101010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "reg"; +let BaseOpcode = "S2_storerh_rr"; +let isNVStorable = 1; +} +def S4_pstorerhfnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memh(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-18} = 0b10101111010000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerhabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerhfnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memh($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_10979813, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000110010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def S4_pstorerhfnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110111010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "reg"; +let BaseOpcode = "S2_storerh_rr"; +let isNVStorable = 1; +} +def S4_pstorerhfnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pv4.new) memh($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_pstorerhnewf_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memh(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b001; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerhabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerhnewf_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b01; +let Inst{31-21} = 0b00110101101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let InputType = "reg"; +let BaseOpcode = "S2_storerh_rr"; +let opNewValue = 4; +} +def S4_pstorerhnewfnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memh(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b101; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerhabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerhnewfnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memh($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_6154421, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b01; +let Inst{31-21} = 0b01000110101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +let opNewValue = 3; +} +def S4_pstorerhnewfnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b01; +let Inst{31-21} = 0b00110111101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let InputType = "reg"; +let BaseOpcode = "S2_storerh_rr"; +let opNewValue = 4; +} +def S4_pstorerhnewfnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if (!$Pv4.new) memh($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S4_pstorerhnewt_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memh(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b001; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerhabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerhnewt_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b01; +let Inst{31-21} = 0b00110100101; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let InputType = "reg"; +let BaseOpcode = "S2_storerh_rr"; +let opNewValue = 4; +} +def S4_pstorerhnewtnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memh(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b101; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerhabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerhnewtnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memh($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_6154421, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b01; +let Inst{31-21} = 0b01000010101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +let opNewValue = 3; +} +def S4_pstorerhnewtnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b01; +let Inst{31-21} = 0b00110110101; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let InputType = "reg"; +let BaseOpcode = "S2_storerh_rr"; +let opNewValue = 4; +} +def S4_pstorerhnewtnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if ($Pv4.new) memh($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S4_pstorerht_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memh(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-18} = 0b10101111010000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerhabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerht_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memh($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110100010; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "reg"; +let BaseOpcode = "S2_storerh_rr"; +let isNVStorable = 1; +} +def S4_pstorerhtnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memh(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-18} = 0b10101111010000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = HalfWordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerhabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerhtnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u31_1Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memh($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_10979813, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000010010; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 7; +let opExtentAlign = 1; +} +def S4_pstorerhtnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memh($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110110010; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "reg"; +let BaseOpcode = "S2_storerh_rr"; +let isNVStorable = 1; +} +def S4_pstorerhtnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pv4.new) memh($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_pstorerif_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memw(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-18} = 0b10101111100000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = WordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeriabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerif_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110101100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "reg"; +let BaseOpcode = "S2_storeri_rr"; +let isNVStorable = 1; +} +def S4_pstorerifnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memw(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-18} = 0b10101111100000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = WordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeriabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerifnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memw($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_8225953, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000110100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def S4_pstorerifnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110111100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "reg"; +let BaseOpcode = "S2_storeri_rr"; +let isNVStorable = 1; +} +def S4_pstorerifnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if (!$Pv4.new) memw($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_pstorerinewf_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memw(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b010; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = WordAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeriabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerinewf_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b10; +let Inst{31-21} = 0b00110101101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let InputType = "reg"; +let BaseOpcode = "S2_storeri_rr"; +let opNewValue = 4; +} +def S4_pstorerinewfnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memw(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b1; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b110; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = Absolute; +let accessSize = WordAccess; +let isNVStore = 1; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeriabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerinewfnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memw($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_11224149, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b10; +let Inst{31-21} = 0b01000110101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +let opNewValue = 3; +} +def S4_pstorerinewfnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if (!$Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b10; +let Inst{31-21} = 0b00110111101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let InputType = "reg"; +let BaseOpcode = "S2_storeri_rr"; +let opNewValue = 4; +} +def S4_pstorerinewfnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if (!$Pv4.new) memw($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S4_pstorerinewt_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memw(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b010; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = WordAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeriabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerinewt_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b10; +let Inst{31-21} = 0b00110100101; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let InputType = "reg"; +let BaseOpcode = "S2_storeri_rr"; +let opNewValue = 4; +} +def S4_pstorerinewtnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memw(#$Ii) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_1774350, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-11} = 0b110; +let Inst{31-18} = 0b10101111101000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = WordAccess; +let isNVStore = 1; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeriabs"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_pstorerinewtnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memw($Rs32+#$Ii) = $Nt8.new", +V2LDST_tc_st_SLOT0, TypeV2LDST>, Enc_11224149, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{12-11} = 0b10; +let Inst{31-21} = 0b01000010101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_io"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +let opNewValue = 3; +} +def S4_pstorerinewtnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_11000933, AddrModeRel { +let Inst{4-3} = 0b10; +let Inst{31-21} = 0b00110110101; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let InputType = "reg"; +let BaseOpcode = "S2_storeri_rr"; +let opNewValue = 4; +} +def S4_pstorerinewtnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Nt8), +"if ($Pv4.new) memw($Rs32) = $Nt8.new", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def S4_pstorerit_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memw(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b0; +let Inst{31-18} = 0b10101111100000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = WordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeriabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstorerit_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4) memw($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110100100; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "reg"; +let BaseOpcode = "S2_storeri_rr"; +let isNVStorable = 1; +} +def S4_pstoreritnew_abs : HInst< +(outs), +(ins PredRegs:$Pv4, u32_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memw(#$Ii) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_16657398, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-18} = 0b10101111100000; +let isPredicated = 1; +let addrMode = Absolute; +let accessSize = WordAccess; +let isExtended = 1; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeriabs"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_pstoreritnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u30_2Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memw($Rs32+#$Ii) = $Rt32", +V2LDST_tc_st_SLOT01, TypeV2LDST>, Enc_8225953, AddrModeRel { +let Inst{2-2} = 0b0; +let Inst{31-21} = 0b01000010100; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_io"; +let isNVStorable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 2; +} +def S4_pstoreritnew_rr : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11940513, AddrModeRel { +let Inst{31-21} = 0b00110110100; +let isPredicated = 1; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "reg"; +let BaseOpcode = "S2_storeri_rr"; +let isNVStorable = 1; +} +def S4_pstoreritnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, IntRegs:$Rt32), +"if ($Pv4.new) memw($Rs32) = $Rt32", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_stored_locked : HInst< +(outs PredRegs:$Pd4), +(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), +"memd_locked($Rs32,$Pd4) = $Rtt32", +ST_tc_ld_SLOT0, TypeST>, Enc_2921694 { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10100000111; +let accessSize = DoubleWordAccess; +let isSoloAX = 1; +let mayStore = 1; +let isPredicateLate = 1; +} +def S4_storeirb_io : HInst< +(outs), +(ins IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), +"memb($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_11282123, PredNewRel { +let Inst{31-21} = 0b00111100000; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S4_storeirb_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def S4_storeirb_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, s8_0Imm:$II), +"memb($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirbf_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), +"if (!$Pv4) memb($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_5967898, PredNewRel { +let Inst{31-21} = 0b00111000100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S4_storeirb_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirbf_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if (!$Pv4) memb($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirbfnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), +"if (!$Pv4.new) memb($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_5967898, PredNewRel { +let Inst{31-21} = 0b00111001100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S4_storeirb_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirbfnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if (!$Pv4.new) memb($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirbt_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), +"if ($Pv4) memb($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_5967898, PredNewRel { +let Inst{31-21} = 0b00111000000; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S4_storeirb_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirbt_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if ($Pv4) memb($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirbtnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_0Imm:$Ii, s32_0Imm:$II), +"if ($Pv4.new) memb($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_5967898, PredNewRel { +let Inst{31-21} = 0b00111001000; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S4_storeirb_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirbtnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if ($Pv4.new) memb($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirh_io : HInst< +(outs), +(ins IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), +"memh($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_10282127, PredNewRel { +let Inst{31-21} = 0b00111100001; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S4_storeirh_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def S4_storeirh_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, s8_0Imm:$II), +"memh($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirhf_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), +"if (!$Pv4) memh($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_4967902, PredNewRel { +let Inst{31-21} = 0b00111000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S4_storeirh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirhf_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if (!$Pv4) memh($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirhfnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), +"if (!$Pv4.new) memh($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_4967902, PredNewRel { +let Inst{31-21} = 0b00111001101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S4_storeirh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirhfnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if (!$Pv4.new) memh($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirht_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), +"if ($Pv4) memh($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_4967902, PredNewRel { +let Inst{31-21} = 0b00111000001; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S4_storeirh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirht_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if ($Pv4) memh($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirhtnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_1Imm:$Ii, s32_0Imm:$II), +"if ($Pv4.new) memh($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_4967902, PredNewRel { +let Inst{31-21} = 0b00111001001; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S4_storeirh_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirhtnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if ($Pv4.new) memh($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeiri_io : HInst< +(outs), +(ins IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), +"memw($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_9282127, PredNewRel { +let Inst{31-21} = 0b00111100010; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S4_storeiri_io"; +let isPredicable = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 8; +let opExtentAlign = 0; +} +def S4_storeiri_zomap : HInst< +(outs), +(ins IntRegs:$Rs32, s8_0Imm:$II), +"memw($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirif_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), +"if (!$Pv4) memw($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_3967902, PredNewRel { +let Inst{31-21} = 0b00111000110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S4_storeiri_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirif_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if (!$Pv4) memw($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirifnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), +"if (!$Pv4.new) memw($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_3967902, PredNewRel { +let Inst{31-21} = 0b00111001110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S4_storeiri_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirifnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if (!$Pv4.new) memw($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeirit_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), +"if ($Pv4) memw($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_3967902, PredNewRel { +let Inst{31-21} = 0b00111000010; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S4_storeiri_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeirit_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if ($Pv4) memw($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storeiritnew_io : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, u6_2Imm:$Ii, s32_0Imm:$II), +"if ($Pv4.new) memw($Rs32+#$Ii) = #$II", +V4LDST_tc_st_SLOT01, TypeST>, Enc_3967902, PredNewRel { +let Inst{31-21} = 0b00111001010; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let isPredicatedNew = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S4_storeiri_io"; +let isExtendable = 1; +let opExtendable = 3; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeiritnew_zomap : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rs32, s6_0Imm:$II), +"if ($Pv4.new) memw($Rs32) = #$II", +PSEUDO, TypeMAPPING> { +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def S4_storerb_ap : HInst< +(outs IntRegs:$Re32), +(ins u32_0Imm:$II, IntRegs:$Rt32), +"memb($Re32=#$II) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_11477246, AddrModeRel { +let Inst{7-6} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10101011000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = AbsoluteSet; +let accessSize = ByteAccess; +let isExtended = 1; +let mayStore = 1; +let BaseOpcode = "S2_storerb_ap"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storerb_rr : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"memb($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_14046916, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111011000; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "reg"; +let BaseOpcode = "S4_storerb_rr"; +let isNVStorable = 1; +let isPredicable = 1; +} +def S4_storerb_ur : HInst< +(outs), +(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), +"memb($Ru32<<#$Ii+#$II) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_14689096, AddrModeRel, ImmRegShl { +let Inst{7-7} = 0b1; +let Inst{31-21} = 0b10101101000; +let addrMode = BaseLongOffset; +let accessSize = ByteAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerb"; +let InputType = "imm"; +let BaseOpcode = "S4_storerb_ur"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storerbnew_ap : HInst< +(outs IntRegs:$Re32), +(ins u32_0Imm:$II, IntRegs:$Nt8), +"memb($Re32=#$II) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_14193700, AddrModeRel { +let Inst{7-6} = 0b10; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b10101011101; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = AbsoluteSet; +let accessSize = ByteAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "S2_storerb_ap"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_storerbnew_rr : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"memb($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_5486172, AddrModeRel { +let Inst{6-3} = 0b0000; +let Inst{31-21} = 0b00111011101; +let addrMode = BaseRegOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let InputType = "reg"; +let BaseOpcode = "S4_storerb_rr"; +let isPredicable = 1; +let opNewValue = 3; +} +def S4_storerbnew_ur : HInst< +(outs), +(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8), +"memb($Ru32<<#$Ii+#$II) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_10076500, AddrModeRel { +let Inst{7-7} = 0b1; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b10101101101; +let addrMode = BaseLongOffset; +let accessSize = ByteAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerb"; +let BaseOpcode = "S4_storerb_ur"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 3; +} +def S4_storerd_ap : HInst< +(outs IntRegs:$Re32), +(ins u32_0Imm:$II, DoubleRegs:$Rtt32), +"memd($Re32=#$II) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_8131399 { +let Inst{7-6} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10101011110; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = AbsoluteSet; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let mayStore = 1; +let BaseOpcode = "S4_storerd_ap"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storerd_rr : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, DoubleRegs:$Rtt32), +"memd($Rs32+$Ru32<<#$Ii) = $Rtt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_9772987, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111011110; +let addrMode = BaseRegOffset; +let accessSize = DoubleWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "reg"; +let BaseOpcode = "S2_storerd_rr"; +let isPredicable = 1; +} +def S4_storerd_ur : HInst< +(outs), +(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, DoubleRegs:$Rtt32), +"memd($Ru32<<#$Ii+#$II) = $Rtt32", +ST_tc_st_SLOT01, TypeST>, Enc_12848507, AddrModeRel, ImmRegShl { +let Inst{7-7} = 0b1; +let Inst{31-21} = 0b10101101110; +let addrMode = BaseLongOffset; +let accessSize = DoubleWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerd"; +let InputType = "imm"; +let BaseOpcode = "S2_storerd_ur"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storerf_ap : HInst< +(outs IntRegs:$Re32), +(ins u32_0Imm:$II, IntRegs:$Rt32), +"memh($Re32=#$II) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_11477246 { +let Inst{7-6} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10101011011; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = AbsoluteSet; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayStore = 1; +let BaseOpcode = "S4_storerf_ap"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storerf_rr : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"memh($Rs32+$Ru32<<#$Ii) = $Rt32.h", +V4LDST_tc_st_SLOT01, TypeST>, Enc_14046916, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111011011; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "reg"; +let BaseOpcode = "S4_storerf_rr"; +let isPredicable = 1; +} +def S4_storerf_ur : HInst< +(outs), +(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), +"memh($Ru32<<#$Ii+#$II) = $Rt32.h", +ST_tc_st_SLOT01, TypeST>, Enc_14689096, AddrModeRel, ImmRegShl { +let Inst{7-7} = 0b1; +let Inst{31-21} = 0b10101101011; +let addrMode = BaseLongOffset; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerf"; +let InputType = "imm"; +let BaseOpcode = "S4_storerf_rr"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storerh_ap : HInst< +(outs IntRegs:$Re32), +(ins u32_0Imm:$II, IntRegs:$Rt32), +"memh($Re32=#$II) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_11477246, AddrModeRel { +let Inst{7-6} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10101011010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = AbsoluteSet; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayStore = 1; +let BaseOpcode = "S2_storerh_ap"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storerh_rr : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"memh($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_14046916, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111011010; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "reg"; +let BaseOpcode = "S2_storerh_rr"; +let isNVStorable = 1; +let isPredicable = 1; +} +def S4_storerh_ur : HInst< +(outs), +(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), +"memh($Ru32<<#$Ii+#$II) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_14689096, AddrModeRel, ImmRegShl { +let Inst{7-7} = 0b1; +let Inst{31-21} = 0b10101101010; +let addrMode = BaseLongOffset; +let accessSize = HalfWordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storerh"; +let InputType = "imm"; +let BaseOpcode = "S2_storerh_ur"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storerhnew_ap : HInst< +(outs IntRegs:$Re32), +(ins u32_0Imm:$II, IntRegs:$Nt8), +"memh($Re32=#$II) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_14193700, AddrModeRel { +let Inst{7-6} = 0b10; +let Inst{13-11} = 0b001; +let Inst{31-21} = 0b10101011101; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = AbsoluteSet; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "S2_storerh_ap"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_storerhnew_rr : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"memh($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_5486172, AddrModeRel { +let Inst{6-3} = 0b0001; +let Inst{31-21} = 0b00111011101; +let addrMode = BaseRegOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let InputType = "reg"; +let BaseOpcode = "S2_storerh_rr"; +let isPredicable = 1; +let opNewValue = 3; +} +def S4_storerhnew_ur : HInst< +(outs), +(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8), +"memh($Ru32<<#$Ii+#$II) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_10076500, AddrModeRel { +let Inst{7-7} = 0b1; +let Inst{12-11} = 0b01; +let Inst{31-21} = 0b10101101101; +let addrMode = BaseLongOffset; +let accessSize = HalfWordAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storerh"; +let BaseOpcode = "S2_storerh_ur"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 3; +} +def S4_storeri_ap : HInst< +(outs IntRegs:$Re32), +(ins u32_0Imm:$II, IntRegs:$Rt32), +"memw($Re32=#$II) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_11477246, AddrModeRel { +let Inst{7-6} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10101011100; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = AbsoluteSet; +let accessSize = WordAccess; +let isExtended = 1; +let mayStore = 1; +let BaseOpcode = "S2_storeri_ap"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storeri_rr : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Rt32), +"memw($Rs32+$Ru32<<#$Ii) = $Rt32", +V4LDST_tc_st_SLOT01, TypeST>, Enc_14046916, AddrModeRel, ImmRegShl { +let Inst{6-5} = 0b00; +let Inst{31-21} = 0b00111011100; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "reg"; +let BaseOpcode = "S2_storeri_rr"; +let isNVStorable = 1; +let isPredicable = 1; +} +def S4_storeri_ur : HInst< +(outs), +(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Rt32), +"memw($Ru32<<#$Ii+#$II) = $Rt32", +ST_tc_st_SLOT01, TypeST>, Enc_14689096, AddrModeRel, ImmRegShl { +let Inst{7-7} = 0b1; +let Inst{31-21} = 0b10101101100; +let addrMode = BaseLongOffset; +let accessSize = WordAccess; +let isExtended = 1; +let mayStore = 1; +let CextOpcode = "S2_storeri"; +let InputType = "imm"; +let BaseOpcode = "S2_storeri_ur"; +let isNVStorable = 1; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_storerinew_ap : HInst< +(outs IntRegs:$Re32), +(ins u32_0Imm:$II, IntRegs:$Nt8), +"memw($Re32=#$II) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_14193700, AddrModeRel { +let Inst{7-6} = 0b10; +let Inst{13-11} = 0b010; +let Inst{31-21} = 0b10101011101; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = AbsoluteSet; +let accessSize = WordAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "S2_storeri_ap"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 2; +} +def S4_storerinew_rr : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Ru32, u2_0Imm:$Ii, IntRegs:$Nt8), +"memw($Rs32+$Ru32<<#$Ii) = $Nt8.new", +V4LDST_tc_st_SLOT0, TypeST>, Enc_5486172, AddrModeRel { +let Inst{6-3} = 0b0010; +let Inst{31-21} = 0b00111011101; +let addrMode = BaseRegOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let InputType = "reg"; +let BaseOpcode = "S2_storeri_rr"; +let isPredicable = 1; +let opNewValue = 3; +} +def S4_storerinew_ur : HInst< +(outs), +(ins IntRegs:$Ru32, u2_0Imm:$Ii, u32_0Imm:$II, IntRegs:$Nt8), +"memw($Ru32<<#$Ii+#$II) = $Nt8.new", +NCJ_tc_3or4stall_SLOT0, TypeST>, Enc_10076500, AddrModeRel { +let Inst{7-7} = 0b1; +let Inst{12-11} = 0b10; +let Inst{31-21} = 0b10101101101; +let addrMode = BaseLongOffset; +let accessSize = WordAccess; +let isNVStore = 1; +let isExtended = 1; +let mayStore = 1; +let isNewValue = 1; +let CextOpcode = "S2_storeri"; +let BaseOpcode = "S2_storeri_ur"; +let DecoderNamespace = "MustExtend"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +let opNewValue = 3; +} +def S4_subaddi : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, s32_0Imm:$Ii, IntRegs:$Ru32), +"$Rd32 = add($Rs32,sub(#$Ii,$Ru32))", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_6495334 { +let Inst{31-23} = 0b110110111; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def S4_subi_asl_ri : HInst< +(outs IntRegs:$Rx32), +(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), +"$Rx32 = sub(#$Ii,asl($Rx32in,#$II))", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_117962 { +let Inst{2-0} = 0b110; +let Inst{4-4} = 0b0; +let Inst{31-24} = 0b11011110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_subi_lsr_ri : HInst< +(outs IntRegs:$Rx32), +(ins u32_0Imm:$Ii, IntRegs:$Rx32in, u5_0Imm:$II), +"$Rx32 = sub(#$Ii,lsr($Rx32in,#$II))", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_117962 { +let Inst{2-0} = 0b110; +let Inst{4-4} = 0b1; +let Inst{31-24} = 0b11011110; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 8; +let opExtentAlign = 0; +let Constraints = "$Rx32 = $Rx32in"; +} +def S4_vrcrotate : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii), +"$Rdd32 = vrcrotate($Rss32,$Rt32,#$Ii)", +S_3op_tc_3x_SLOT23, TypeS_3op>, Enc_114098 { +let Inst{7-6} = 0b11; +let Inst{31-21} = 0b11000011110; +let prefersSlot3 = 1; +} +def S4_vrcrotate_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, IntRegs:$Rt32, u2_0Imm:$Ii), +"$Rxx32 += vrcrotate($Rss32,$Rt32,#$Ii)", +S_3op_tc_3x_SLOT23, TypeS_3op>, Enc_13114546 { +let Inst{7-6} = 0b00; +let Inst{31-21} = 0b11001011101; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S4_vxaddsubh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vxaddsubh($Rss32,$Rtt32):sat", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001010; +let Defs = [USR_OVF]; +} +def S4_vxaddsubhr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vxaddsubh($Rss32,$Rtt32):rnd:>>1:sat", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def S4_vxaddsubw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vxaddsubw($Rss32,$Rtt32):sat", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001010; +let Defs = [USR_OVF]; +} +def S4_vxsubaddh : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vxsubaddh($Rss32,$Rtt32):sat", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001010; +let Defs = [USR_OVF]; +} +def S4_vxsubaddhr : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vxsubaddh($Rss32,$Rtt32):rnd:>>1:sat", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001110; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def S4_vxsubaddw : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vxsubaddw($Rss32,$Rtt32):sat", +S_3op_tc_2_SLOT23, TypeS_3op>, Enc_8333157 { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001010; +let Defs = [USR_OVF]; +} +def S5_asrhub_rnd_sat : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), +"$Rd32 = vasrhub($Rss32,#$Ii):raw", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8038806, Requires<[HasV5T]> { +let Inst{7-5} = 0b100; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b10001000011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def S5_asrhub_rnd_sat_goodsyntax : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), +"$Rd32 = vasrhub($Rss32,#$Ii):rnd:sat", +S_2op_tc_2_SLOT23, TypeS_2op>, Requires<[HasV5T]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +} +def S5_asrhub_sat : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), +"$Rd32 = vasrhub($Rss32,#$Ii):sat", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_8038806, Requires<[HasV5T]> { +let Inst{7-5} = 0b101; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b10001000011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Defs = [USR_OVF]; +} +def S5_popcountp : HInst< +(outs IntRegs:$Rd32), +(ins DoubleRegs:$Rss32), +"$Rd32 = popcount($Rss32)", +S_2op_tc_2_SLOT23, TypeS_2op>, Enc_3742184, Requires<[HasV5T]> { +let Inst{13-5} = 0b000000011; +let Inst{31-21} = 0b10001000011; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +} +def S5_vasrhrnd : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), +"$Rdd32 = vasrh($Rss32,#$Ii):raw", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2082775, Requires<[HasV5T]> { +let Inst{7-5} = 0b000; +let Inst{13-12} = 0b00; +let Inst{31-21} = 0b10000000001; +let prefersSlot3 = 1; +} +def S5_vasrhrnd_goodsyntax : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u4_0Imm:$Ii), +"$Rdd32 = vasrh($Rss32,#$Ii):rnd", +S_2op_tc_1_SLOT23, TypeS_2op>, Requires<[HasV5T]> { +let isPseudo = 1; +} +def S6_rol_i_p : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rdd32 = rol($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4231995, Requires<[HasV60T]> { +let Inst{7-5} = 0b011; +let Inst{31-21} = 0b10000000000; +} +def S6_rol_i_p_acc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 += rol($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_8497723, Requires<[HasV60T]> { +let Inst{7-5} = 0b111; +let Inst{31-21} = 0b10000010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S6_rol_i_p_and : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 &= rol($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_8497723, Requires<[HasV60T]> { +let Inst{7-5} = 0b011; +let Inst{31-21} = 0b10000010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S6_rol_i_p_nac : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 -= rol($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_8497723, Requires<[HasV60T]> { +let Inst{7-5} = 0b011; +let Inst{31-21} = 0b10000010000; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S6_rol_i_p_or : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 |= rol($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_8497723, Requires<[HasV60T]> { +let Inst{7-5} = 0b111; +let Inst{31-21} = 0b10000010010; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S6_rol_i_p_xacc : HInst< +(outs DoubleRegs:$Rxx32), +(ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, u6_0Imm:$Ii), +"$Rxx32 ^= rol($Rss32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_8497723, Requires<[HasV60T]> { +let Inst{7-5} = 0b011; +let Inst{31-21} = 0b10000010100; +let prefersSlot3 = 1; +let Constraints = "$Rxx32 = $Rxx32in"; +} +def S6_rol_i_r : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rd32 = rol($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2771456, Requires<[HasV60T]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001100000; +let hasNewValue = 1; +let opNewValue = 0; +} +def S6_rol_i_r_acc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 += rol($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2410156, Requires<[HasV60T]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S6_rol_i_r_and : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 &= rol($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2410156, Requires<[HasV60T]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S6_rol_i_r_nac : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 -= rol($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2410156, Requires<[HasV60T]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110000; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S6_rol_i_r_or : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 |= rol($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2410156, Requires<[HasV60T]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110010; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S6_rol_i_r_xacc : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, IntRegs:$Rs32, u5_0Imm:$Ii), +"$Rx32 ^= rol($Rs32,#$Ii)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_2410156, Requires<[HasV60T]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10001110100; +let hasNewValue = 1; +let opNewValue = 0; +let prefersSlot3 = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def S6_vsplatrbp : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32), +"$Rdd32 = vsplatb($Rs32)", +S_2op_tc_1_SLOT23, TypeS_2op>, Enc_4030179, Requires<[HasV62T]> { +let Inst{13-5} = 0b000000100; +let Inst{31-21} = 0b10000100010; +} +def S6_vtrunehb_ppp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vtrunehb($Rss32,$Rtt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8333157, Requires<[HasV62T]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001100; +} +def S6_vtrunohb_ppp : HInst< +(outs DoubleRegs:$Rdd32), +(ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), +"$Rdd32 = vtrunohb($Rss32,$Rtt32)", +S_3op_tc_1_SLOT23, TypeS_3op>, Enc_8333157, Requires<[HasV62T]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11000001100; +} +def SA1_addi : HInst< +(outs GeneralSubRegs:$Rx16), +(ins IntRegs:$Rx16in, s32_0Imm:$Ii), +"$Rx16 = add($Rx16in,#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_3974695 { +let Inst{12-11} = 0b00; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +let isExtendable = 1; +let opExtendable = 2; +let isExtentSigned = 1; +let opExtentBits = 7; +let opExtentAlign = 0; +let Constraints = "$Rx16 = $Rx16in"; +} +def SA1_addrx : HInst< +(outs GeneralSubRegs:$Rx16), +(ins IntRegs:$Rx16in, GeneralSubRegs:$Rs16), +"$Rx16 = add($Rx16in,$Rs16)", +PSEUDO, TypeSUBINSN>, Enc_6135183 { +let Inst{12-8} = 0b11000; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +let Constraints = "$Rx16 = $Rx16in"; +} +def SA1_addsp : HInst< +(outs GeneralSubRegs:$Rd16), +(ins u6_2Imm:$Ii), +"$Rd16 = add(r29,#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_176263 { +let Inst{12-10} = 0b011; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let Uses = [R29]; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_and1 : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16), +"$Rd16 = and($Rs16,#1)", +PSEUDO, TypeSUBINSN>, Enc_14939491 { +let Inst{12-8} = 0b10010; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_clrf : HInst< +(outs GeneralSubRegs:$Rd16), +(ins), +"if (!p0) $Rd16 = #0", +PSEUDO, TypeSUBINSN>, Enc_1451363 { +let Inst{12-4} = 0b110100111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let Uses = [P0]; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_clrfnew : HInst< +(outs GeneralSubRegs:$Rd16), +(ins), +"if (!p0.new) $Rd16 = #0", +PSEUDO, TypeSUBINSN>, Enc_1451363 { +let Inst{12-4} = 0b110100101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPredicatedNew = 1; +let Uses = [P0]; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_clrt : HInst< +(outs GeneralSubRegs:$Rd16), +(ins), +"if (p0) $Rd16 = #0", +PSEUDO, TypeSUBINSN>, Enc_1451363 { +let Inst{12-4} = 0b110100110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let Uses = [P0]; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_clrtnew : HInst< +(outs GeneralSubRegs:$Rd16), +(ins), +"if (p0.new) $Rd16 = #0", +PSEUDO, TypeSUBINSN>, Enc_1451363 { +let Inst{12-4} = 0b110100100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let isPredicatedNew = 1; +let Uses = [P0]; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_cmpeqi : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u2_0Imm:$Ii), +"p0 = cmp.eq($Rs16,#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_2079016 { +let Inst{3-2} = 0b00; +let Inst{12-8} = 0b11001; +let AsmVariantName = "NonParsable"; +let Defs = [P0]; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_combine0i : HInst< +(outs GeneralDoubleLow8Regs:$Rdd8), +(ins u2_0Imm:$Ii), +"$Rdd8 = combine(#0,#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_15946706 { +let Inst{4-3} = 0b00; +let Inst{12-7} = 0b111000; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_combine1i : HInst< +(outs GeneralDoubleLow8Regs:$Rdd8), +(ins u2_0Imm:$Ii), +"$Rdd8 = combine(#1,#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_15946706 { +let Inst{4-3} = 0b01; +let Inst{12-7} = 0b111000; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_combine2i : HInst< +(outs GeneralDoubleLow8Regs:$Rdd8), +(ins u2_0Imm:$Ii), +"$Rdd8 = combine(#2,#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_15946706 { +let Inst{4-3} = 0b10; +let Inst{12-7} = 0b111000; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_combine3i : HInst< +(outs GeneralDoubleLow8Regs:$Rdd8), +(ins u2_0Imm:$Ii), +"$Rdd8 = combine(#3,#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_15946706 { +let Inst{4-3} = 0b11; +let Inst{12-7} = 0b111000; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_combinerz : HInst< +(outs GeneralDoubleLow8Regs:$Rdd8), +(ins GeneralSubRegs:$Rs16), +"$Rdd8 = combine($Rs16,#0)", +PSEUDO, TypeSUBINSN>, Enc_10501894 { +let Inst{3-3} = 0b1; +let Inst{12-8} = 0b11101; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_combinezr : HInst< +(outs GeneralDoubleLow8Regs:$Rdd8), +(ins GeneralSubRegs:$Rs16), +"$Rdd8 = combine(#0,$Rs16)", +PSEUDO, TypeSUBINSN>, Enc_10501894 { +let Inst{3-3} = 0b0; +let Inst{12-8} = 0b11101; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_dec : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16, n1Const:$n1), +"$Rd16 = add($Rs16,#$n1)", +PSEUDO, TypeSUBINSN>, Enc_10597934 { +let Inst{12-8} = 0b10011; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_inc : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16), +"$Rd16 = add($Rs16,#1)", +PSEUDO, TypeSUBINSN>, Enc_14939491 { +let Inst{12-8} = 0b10001; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_seti : HInst< +(outs GeneralSubRegs:$Rd16), +(ins u32_0Imm:$Ii), +"$Rd16 = #$Ii", +PSEUDO, TypeSUBINSN>, Enc_2176383 { +let Inst{12-10} = 0b010; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +let isExtendable = 1; +let opExtendable = 1; +let isExtentSigned = 0; +let opExtentBits = 6; +let opExtentAlign = 0; +} +def SA1_setin1 : HInst< +(outs GeneralSubRegs:$Rd16), +(ins n1Const:$n1), +"$Rd16 = #$n1", +PSEUDO, TypeSUBINSN>, Enc_13336212 { +let Inst{12-4} = 0b110100000; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_sxtb : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16), +"$Rd16 = sxtb($Rs16)", +PSEUDO, TypeSUBINSN>, Enc_14939491 { +let Inst{12-8} = 0b10101; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_sxth : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16), +"$Rd16 = sxth($Rs16)", +PSEUDO, TypeSUBINSN>, Enc_14939491 { +let Inst{12-8} = 0b10100; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_tfr : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16), +"$Rd16 = $Rs16", +PSEUDO, TypeSUBINSN>, Enc_14939491 { +let Inst{12-8} = 0b10000; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_zxtb : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16), +"$Rd16 = and($Rs16,#255)", +PSEUDO, TypeSUBINSN>, Enc_14939491 { +let Inst{12-8} = 0b10111; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SA1_zxth : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16), +"$Rd16 = zxth($Rs16)", +PSEUDO, TypeSUBINSN>, Enc_14939491 { +let Inst{12-8} = 0b10110; +let hasNewValue = 1; +let opNewValue = 0; +let AsmVariantName = "NonParsable"; +let DecoderNamespace = "SUBINSN_A"; +} +def SL1_loadri_io : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii), +"$Rd16 = memw($Rs16+#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_13606251 { +let Inst{12-12} = 0b0; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let DecoderNamespace = "SUBINSN_L1"; +} +def SL1_loadrub_io : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii), +"$Rd16 = memub($Rs16+#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_15606259 { +let Inst{12-12} = 0b1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let DecoderNamespace = "SUBINSN_L1"; +} +def SL2_deallocframe : HInst< +(outs), +(ins), +"deallocframe", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111100000000; +let accessSize = DoubleWordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let Uses = [R30]; +let Defs = [R30, R29, R31]; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_jumpr31 : HInst< +(outs), +(ins), +"jumpr r31", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111111000000; +let isTerminator = 1; +let isIndirectBranch = 1; +let cofMax1 = 1; +let AsmVariantName = "NonParsable"; +let isReturn = 1; +let Uses = [R31]; +let Defs = [PC]; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_jumpr31_f : HInst< +(outs), +(ins), +"if (!p0) jumpr r31", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111111000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let cofMax1 = 1; +let AsmVariantName = "NonParsable"; +let isReturn = 1; +let Uses = [P0, R31]; +let Defs = [PC]; +let isTaken = Inst{4}; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_jumpr31_fnew : HInst< +(outs), +(ins), +"if (!p0.new) jumpr:nt r31", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111111000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let cofMax1 = 1; +let AsmVariantName = "NonParsable"; +let isReturn = 1; +let isPredicatedNew = 1; +let Uses = [P0, R31]; +let Defs = [PC]; +let isTaken = Inst{4}; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_jumpr31_t : HInst< +(outs), +(ins), +"if (p0) jumpr r31", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111111000100; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let cofMax1 = 1; +let AsmVariantName = "NonParsable"; +let isReturn = 1; +let Uses = [P0, R31]; +let Defs = [PC]; +let isTaken = Inst{4}; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_jumpr31_tnew : HInst< +(outs), +(ins), +"if (p0.new) jumpr:nt r31", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111111000110; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let cofMax1 = 1; +let AsmVariantName = "NonParsable"; +let isReturn = 1; +let isPredicatedNew = 1; +let Uses = [P0, R31]; +let Defs = [PC]; +let isTaken = Inst{4}; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_loadrb_io : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16, u3_0Imm:$Ii), +"$Rd16 = memb($Rs16+#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_3135259 { +let Inst{12-11} = 0b10; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_loadrd_sp : HInst< +(outs GeneralDoubleLow8Regs:$Rdd8), +(ins u5_3Imm:$Ii), +"$Rdd8 = memd(r29+#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_16479122 { +let Inst{12-8} = 0b11110; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let Uses = [R29]; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_loadrh_io : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii), +"$Rd16 = memh($Rs16+#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_4135257 { +let Inst{12-11} = 0b00; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_loadri_sp : HInst< +(outs GeneralSubRegs:$Rd16), +(ins u5_2Imm:$Ii), +"$Rd16 = memw(r29+#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_64199 { +let Inst{12-9} = 0b1110; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let Uses = [R29]; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_loadruh_io : HInst< +(outs GeneralSubRegs:$Rd16), +(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii), +"$Rd16 = memuh($Rs16+#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_4135257 { +let Inst{12-11} = 0b01; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let AsmVariantName = "NonParsable"; +let mayLoad = 1; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_return : HInst< +(outs), +(ins), +"dealloc_return", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111101000000; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let AsmVariantName = "NonParsable"; +let isReturn = 1; +let mayLoad = 1; +let Uses = [R30]; +let Defs = [PC, R30, R29, R31]; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_return_f : HInst< +(outs), +(ins), +"if (!p0) dealloc_return", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111101000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let AsmVariantName = "NonParsable"; +let isReturn = 1; +let mayLoad = 1; +let Uses = [P0, R30]; +let Defs = [PC, R30, R29, R31]; +let isTaken = Inst{4}; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_return_fnew : HInst< +(outs), +(ins), +"if (!p0.new) dealloc_return:nt", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111101000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let AsmVariantName = "NonParsable"; +let isReturn = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let Uses = [P0, R30]; +let Defs = [PC, R30, R29, R31]; +let isTaken = Inst{4}; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_return_t : HInst< +(outs), +(ins), +"if (p0) dealloc_return", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111101000100; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let AsmVariantName = "NonParsable"; +let isReturn = 1; +let mayLoad = 1; +let Uses = [P0, R30]; +let Defs = [PC, R30, R29, R31]; +let isTaken = Inst{4}; +let DecoderNamespace = "SUBINSN_L2"; +} +def SL2_return_tnew : HInst< +(outs), +(ins), +"if (p0.new) dealloc_return:nt", +PSEUDO, TypeSUBINSN>, Enc_0 { +let Inst{12-0} = 0b1111101000110; +let isPredicated = 1; +let isTerminator = 1; +let isIndirectBranch = 1; +let accessSize = DoubleWordAccess; +let cofMax1 = 1; +let AsmVariantName = "NonParsable"; +let isReturn = 1; +let isPredicatedNew = 1; +let mayLoad = 1; +let Uses = [P0, R30]; +let Defs = [PC, R30, R29, R31]; +let isTaken = Inst{4}; +let DecoderNamespace = "SUBINSN_L2"; +} +def SS1_storeb_io : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii, GeneralSubRegs:$Rt16), +"memb($Rs16+#$Ii) = $Rt16", +PSEUDO, TypeSUBINSN>, Enc_13204995 { +let Inst{12-12} = 0b1; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let DecoderNamespace = "SUBINSN_S1"; +} +def SS1_storew_io : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii, GeneralSubRegs:$Rt16), +"memw($Rs16+#$Ii) = $Rt16", +PSEUDO, TypeSUBINSN>, Enc_11205051 { +let Inst{12-12} = 0b0; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let DecoderNamespace = "SUBINSN_S1"; +} +def SS2_allocframe : HInst< +(outs), +(ins u5_3Imm:$Ii), +"allocframe(#$Ii)", +PSEUDO, TypeSUBINSN>, Enc_7884306 { +let Inst{3-0} = 0b0000; +let Inst{12-9} = 0b1110; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let Uses = [R30, R29, R31]; +let Defs = [R30, R29]; +let DecoderNamespace = "SUBINSN_S2"; +} +def SS2_storebi0 : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii), +"memb($Rs16+#$Ii) = #0", +PSEUDO, TypeSUBINSN>, Enc_13536408 { +let Inst{12-8} = 0b10010; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let DecoderNamespace = "SUBINSN_S2"; +} +def SS2_storebi1 : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u4_0Imm:$Ii), +"memb($Rs16+#$Ii) = #1", +PSEUDO, TypeSUBINSN>, Enc_13536408 { +let Inst{12-8} = 0b10011; +let addrMode = BaseImmOffset; +let accessSize = ByteAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let DecoderNamespace = "SUBINSN_S2"; +} +def SS2_stored_sp : HInst< +(outs), +(ins s6_3Imm:$Ii, GeneralDoubleLow8Regs:$Rtt8), +"memd(r29+#$Ii) = $Rtt8", +PSEUDO, TypeSUBINSN>, Enc_9165078 { +let Inst{12-9} = 0b0101; +let addrMode = BaseImmOffset; +let accessSize = DoubleWordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let Uses = [R29]; +let DecoderNamespace = "SUBINSN_S2"; +} +def SS2_storeh_io : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u3_1Imm:$Ii, GeneralSubRegs:$Rt16), +"memh($Rs16+#$Ii) = $Rt16", +PSEUDO, TypeSUBINSN>, Enc_1734121 { +let Inst{12-11} = 0b00; +let addrMode = BaseImmOffset; +let accessSize = HalfWordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let DecoderNamespace = "SUBINSN_S2"; +} +def SS2_storew_sp : HInst< +(outs), +(ins u5_2Imm:$Ii, GeneralSubRegs:$Rt16), +"memw(r29+#$Ii) = $Rt16", +PSEUDO, TypeSUBINSN>, Enc_6690615 { +let Inst{12-9} = 0b0100; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let Uses = [R29]; +let DecoderNamespace = "SUBINSN_S2"; +} +def SS2_storewi0 : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii), +"memw($Rs16+#$Ii) = #0", +PSEUDO, TypeSUBINSN>, Enc_15536400 { +let Inst{12-8} = 0b10000; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let DecoderNamespace = "SUBINSN_S2"; +} +def SS2_storewi1 : HInst< +(outs), +(ins GeneralSubRegs:$Rs16, u4_2Imm:$Ii), +"memw($Rs16+#$Ii) = #1", +PSEUDO, TypeSUBINSN>, Enc_15536400 { +let Inst{12-8} = 0b10001; +let addrMode = BaseImmOffset; +let accessSize = WordAccess; +let AsmVariantName = "NonParsable"; +let mayStore = 1; +let DecoderNamespace = "SUBINSN_S2"; +} +def V6_MAP_equb : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_MAP_equb_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.eq($Vu32.ub,$Vv32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_MAP_equb_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equb_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.ub,$Vv32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equb_ior : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equb_ior_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.ub,$Vv32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equb_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equb_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.ub,$Vv32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equh : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_MAP_equh_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.eq($Vu32.uh,$Vv32.uh)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_MAP_equh_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equh_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.uh,$Vv32.uh)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equh_ior : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equh_ior_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.uh,$Vv32.uh)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equh_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equh_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.uh,$Vv32.uh)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equw : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_MAP_equw_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.eq($Vu32.uw,$Vv32.uw)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_MAP_equw_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equw_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.uw,$Vv32.uw)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equw_ior : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equw_ior_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.uw,$Vv32.uw)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equw_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_MAP_equw_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.uw,$Vv32.uw)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_extractw : HInst< +(outs IntRegs:$Rd32), +(ins VectorRegs:$Vu32, IntRegs:$Rs32), +"$Rd32 = vextract($Vu32,$Rs32)", +LD_tc_ld_SLOT0, TypeLD>, Enc_16601956, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10010010000; +let hasNewValue = 1; +let opNewValue = 0; +let isSolo = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_extractw_128B : HInst< +(outs IntRegs:$Rd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rs32), +"$Rd32 = vextract($Vu32,$Rs32)", +LD_tc_ld_SLOT0, TypeLD>, Enc_16601956, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10010010000; +let hasNewValue = 1; +let opNewValue = 0; +let isSolo = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_extractw_alt : HInst< +(outs IntRegs:$Rd32), +(ins VectorRegs:$Vu32, IntRegs:$Rs32), +"$Rd32.w = vextract($Vu32,$Rs32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_extractw_alt_128B : HInst< +(outs IntRegs:$Rd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rs32), +"$Rd32.w = vextract($Vu32,$Rs32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_hi : HInst< +(outs VectorRegs:$Vd32), +(ins VecDblRegs:$Vss32), +"$Vd32 = hi($Vss32)", +CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_hi_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecDblRegs128B:$Vss32), +"$Vd32 = hi($Vss32)", +CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_ld0 : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32 = vmem($Rt32)", +PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_ld0_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32 = vmem($Rt32)", +PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_ldnt0 : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32 = vmem($Rt32):nt", +PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_ldnt0_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32 = vmem($Rt32):nt", +PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_ldu0 : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32 = vmemu($Rt32)", +PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_ldu0_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32 = vmemu($Rt32)", +PSEUDO, TypeCVI_VM_LD>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_lo : HInst< +(outs VectorRegs:$Vd32), +(ins VecDblRegs:$Vss32), +"$Vd32 = lo($Vss32)", +CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_lo_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecDblRegs128B:$Vss32), +"$Vd32 = lo($Vss32)", +CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_lvsplatb : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32.b = vsplat($Rt32)", +CVI_VX, TypeCVI_VX>, Enc_9768377, Requires<[HasV62T,UseHVX]> { +let Inst{13-5} = 0b000000010; +let Inst{31-21} = 0b00011001110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_lvsplatb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32.b = vsplat($Rt32)", +CVI_VX, TypeCVI_VX>, Enc_9768377, Requires<[HasV62T,UseHVX]> { +let Inst{13-5} = 0b000000010; +let Inst{31-21} = 0b00011001110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_lvsplath : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32.h = vsplat($Rt32)", +CVI_VX, TypeCVI_VX>, Enc_9768377, Requires<[HasV62T,UseHVX]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b00011001110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_lvsplath_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32.h = vsplat($Rt32)", +CVI_VX, TypeCVI_VX>, Enc_9768377, Requires<[HasV62T,UseHVX]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b00011001110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_lvsplatw : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32 = vsplat($Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_9768377, Requires<[HasV60T,UseHVX]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_lvsplatw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32), +"$Vd32 = vsplat($Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_9768377, Requires<[HasV60T,UseHVX]> { +let Inst{13-5} = 0b000000001; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_pred_and : HInst< +(outs VecPredRegs:$Qd4), +(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), +"$Qd4 = and($Qs4,$Qt4)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000000; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_pred_and_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), +"$Qd4 = and($Qs4,$Qt4)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000000; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_pred_and_n : HInst< +(outs VecPredRegs:$Qd4), +(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), +"$Qd4 = and($Qs4,!$Qt4)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000101; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_pred_and_n_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), +"$Qd4 = and($Qs4,!$Qt4)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000101; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_pred_not : HInst< +(outs VecPredRegs:$Qd4), +(ins VecPredRegs:$Qs4), +"$Qd4 = not($Qs4)", +CVI_VA, TypeCVI_VA>, Enc_4897205, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000010; +let Inst{13-10} = 0b0000; +let Inst{31-16} = 0b0001111000000011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_pred_not_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VecPredRegs128B:$Qs4), +"$Qd4 = not($Qs4)", +CVI_VA, TypeCVI_VA>, Enc_4897205, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000010; +let Inst{13-10} = 0b0000; +let Inst{31-16} = 0b0001111000000011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_pred_or : HInst< +(outs VecPredRegs:$Qd4), +(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), +"$Qd4 = or($Qs4,$Qt4)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000001; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_pred_or_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), +"$Qd4 = or($Qs4,$Qt4)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000001; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_pred_or_n : HInst< +(outs VecPredRegs:$Qd4), +(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), +"$Qd4 = or($Qs4,!$Qt4)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000100; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_pred_or_n_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), +"$Qd4 = or($Qs4,!$Qt4)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000100; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_pred_scalar2 : HInst< +(outs VecPredRegs:$Qd4), +(ins IntRegs:$Rt32), +"$Qd4 = vsetq($Rt32)", +CVI_VP_LONG, TypeCVI_VP>, Enc_12781442, Requires<[HasV60T,UseHVX]> { +let Inst{13-2} = 0b000000010001; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_pred_scalar2_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins IntRegs:$Rt32), +"$Qd4 = vsetq($Rt32)", +CVI_VP_LONG, TypeCVI_VP>, Enc_12781442, Requires<[HasV60T,UseHVX]> { +let Inst{13-2} = 0b000000010001; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_pred_scalar2v2 : HInst< +(outs VecPredRegs:$Qd4), +(ins IntRegs:$Rt32), +"$Qd4 = vsetq2($Rt32)", +CVI_VP_LONG, TypeCVI_VP>, Enc_12781442, Requires<[HasV62T,UseHVX]> { +let Inst{13-2} = 0b000000010011; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_pred_scalar2v2_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins IntRegs:$Rt32), +"$Qd4 = vsetq2($Rt32)", +CVI_VP_LONG, TypeCVI_VP>, Enc_12781442, Requires<[HasV62T,UseHVX]> { +let Inst{13-2} = 0b000000010011; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_pred_xor : HInst< +(outs VecPredRegs:$Qd4), +(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), +"$Qd4 = xor($Qs4,$Qt4)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000011; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_pred_xor_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), +"$Qd4 = xor($Qs4,$Qt4)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000011; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_shuffeqh : HInst< +(outs VecPredRegs:$Qd4), +(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), +"$Qd4.b = vshuffe($Qs4.h,$Qt4.h)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV62T,UseHVX]> { +let Inst{7-2} = 0b000110; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_shuffeqh_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), +"$Qd4.b = vshuffe($Qs4.h,$Qt4.h)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV62T,UseHVX]> { +let Inst{7-2} = 0b000110; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_shuffeqw : HInst< +(outs VecPredRegs:$Qd4), +(ins VecPredRegs:$Qs4, VecPredRegs:$Qt4), +"$Qd4.h = vshuffe($Qs4.w,$Qt4.w)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV62T,UseHVX]> { +let Inst{7-2} = 0b000111; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_shuffeqw_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VecPredRegs128B:$Qs4, VecPredRegs128B:$Qt4), +"$Qd4.h = vshuffe($Qs4.w,$Qt4.w)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_6091631, Requires<[HasV62T,UseHVX]> { +let Inst{7-2} = 0b000111; +let Inst{13-10} = 0b0000; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_st0 : HInst< +(outs), +(ins IntRegs:$Rt32, VectorRegs:$Vs32), +"vmem($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_st0_128B : HInst< +(outs), +(ins IntRegs:$Rt32, VectorRegs128B:$Vs32), +"vmem($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stn0 : HInst< +(outs), +(ins IntRegs:$Rt32, VectorRegs:$Os8), +"vmem($Rt32) = $Os8.new", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 1; +} +def V6_stn0_128B : HInst< +(outs), +(ins IntRegs:$Rt32, VectorRegs128B:$Os8), +"vmem($Rt32) = $Os8.new", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 1; +} +def V6_stnnt0 : HInst< +(outs), +(ins IntRegs:$Rt32, VectorRegs:$Os8), +"vmem($Rt32):nt = $Os8.new", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 1; +} +def V6_stnnt0_128B : HInst< +(outs), +(ins IntRegs:$Rt32, VectorRegs128B:$Os8), +"vmem($Rt32):nt = $Os8.new", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 1; +} +def V6_stnp0 : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), +"if (!$Pv4) vmem($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stnp0_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +"if (!$Pv4) vmem($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stnpnt0 : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), +"if (!$Pv4) vmem($Rt32):nt = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stnpnt0_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +"if (!$Pv4) vmem($Rt32):nt = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stnq0 : HInst< +(outs), +(ins VecPredRegs:$Qv4, IntRegs:$Rt32, VectorRegs:$Vs32), +"if (!$Qv4) vmem($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stnq0_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +"if (!$Qv4) vmem($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stnqnt0 : HInst< +(outs), +(ins VecPredRegs:$Qv4, IntRegs:$Rt32, VectorRegs:$Vs32), +"if (!$Qv4) vmem($Rt32):nt = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stnqnt0_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +"if (!$Qv4) vmem($Rt32):nt = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stnt0 : HInst< +(outs), +(ins IntRegs:$Rt32, VectorRegs:$Vs32), +"vmem($Rt32):nt = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stnt0_128B : HInst< +(outs), +(ins IntRegs:$Rt32, VectorRegs128B:$Vs32), +"vmem($Rt32):nt = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stp0 : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), +"if ($Pv4) vmem($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stp0_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +"if ($Pv4) vmem($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stpnt0 : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), +"if ($Pv4) vmem($Rt32):nt = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stpnt0_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +"if ($Pv4) vmem($Rt32):nt = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stq0 : HInst< +(outs), +(ins VecPredRegs:$Qv4, IntRegs:$Rt32, VectorRegs:$Vs32), +"if ($Qv4) vmem($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stq0_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +"if ($Qv4) vmem($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stqnt0 : HInst< +(outs), +(ins VecPredRegs:$Qv4, IntRegs:$Rt32, VectorRegs:$Vs32), +"if ($Qv4) vmem($Rt32):nt = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stqnt0_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +"if ($Qv4) vmem($Rt32):nt = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stu0 : HInst< +(outs), +(ins IntRegs:$Rt32, VectorRegs:$Vs32), +"vmemu($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stu0_128B : HInst< +(outs), +(ins IntRegs:$Rt32, VectorRegs128B:$Vs32), +"vmemu($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stunp0 : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), +"if (!$Pv4) vmemu($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stunp0_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +"if (!$Pv4) vmemu($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_stup0 : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs:$Vs32), +"if ($Pv4) vmemu($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_stup0_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, VectorRegs128B:$Vs32), +"if ($Pv4) vmemu($Rt32) = $Vs32", +PSEUDO, TypeCVI_VM_ST>, Requires<[HasV60T,UseHVX]> { +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32Ub_ai : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32, s4_0Imm:$Ii), +"$Vd32 = vmemu($Rt32+#$Ii)", +CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_1244745, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32Ub_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32, s4_0Imm:$Ii), +"$Vd32 = vmemu($Rt32+#$Ii)", +CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_8437395, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32Ub_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii), +"$Vd32 = vmemu($Rx32++#$Ii)", +CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_10039393, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32Ub_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii), +"$Vd32 = vmemu($Rx32++#$Ii)", +CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_11039423, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32Ub_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32 = vmemu($Rx32++$Mu2)", +CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000111; +let Inst{31-21} = 0b00101011000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32Ub_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32 = vmemu($Rx32++$Mu2)", +CVI_VM_VP_LDU, TypeCVI_VM_VP_LDU>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000111; +let Inst{31-21} = 0b00101011000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_ai : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32, s4_0Imm:$Ii), +"$Vd32 = vmem($Rt32+#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32, s4_0Imm:$Ii), +"$Vd32 = vmem($Rt32+#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_cur_ai : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32, s4_0Imm:$Ii), +"$Vd32.cur = vmem($Rt32+#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_cur_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32, s4_0Imm:$Ii), +"$Vd32.cur = vmem($Rt32+#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_cur_npred_ai : HInst< +(outs VectorRegs:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii)", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{31-21} = 0b00101000100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_cur_npred_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii)", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{31-21} = 0b00101000100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_cur_npred_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii)", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_cur_npred_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii)", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_cur_npred_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2)", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000101; +let Inst{31-21} = 0b00101011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_cur_npred_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2)", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000101; +let Inst{31-21} = 0b00101011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_cur_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii), +"$Vd32.cur = vmem($Rx32++#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_cur_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii), +"$Vd32.cur = vmem($Rx32++#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_cur_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32.cur = vmem($Rx32++$Mu2)", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000001; +let Inst{31-21} = 0b00101011000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_cur_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32.cur = vmem($Rx32++$Mu2)", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000001; +let Inst{31-21} = 0b00101011000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_cur_pred_ai : HInst< +(outs VectorRegs:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii)", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{31-21} = 0b00101000100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_cur_pred_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii)", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{31-21} = 0b00101000100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_cur_pred_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii)", +CVI_VM_CUR_LD, TypeCOPROC_VMEM>, Enc_14560494, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_cur_pred_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii)", +CVI_VM_CUR_LD, TypeCOPROC_VMEM>, Enc_15560488, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_cur_pred_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2)", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000100; +let Inst{31-21} = 0b00101011100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_cur_pred_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2)", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000100; +let Inst{31-21} = 0b00101011100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_npred_ai : HInst< +(outs VectorRegs:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{31-21} = 0b00101000100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_npred_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{31-21} = 0b00101000100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_npred_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_npred_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_npred_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000011; +let Inst{31-21} = 0b00101011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_npred_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000011; +let Inst{31-21} = 0b00101011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_ai : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32, s4_0Imm:$Ii), +"$Vd32 = vmem($Rt32+#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_nt_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32, s4_0Imm:$Ii), +"$Vd32 = vmem($Rt32+#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_nt_cur_ai : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32, s4_0Imm:$Ii), +"$Vd32.cur = vmem($Rt32+#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_nt_cur_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32, s4_0Imm:$Ii), +"$Vd32.cur = vmem($Rt32+#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_nt_cur_npred_ai : HInst< +(outs VectorRegs:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{31-21} = 0b00101000110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_nt_cur_npred_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if (!$Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{31-21} = 0b00101000110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_nt_cur_npred_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_cur_npred_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if (!$Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_cur_npred_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000101; +let Inst{31-21} = 0b00101011110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_cur_npred_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if (!$Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000101; +let Inst{31-21} = 0b00101011110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_cur_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii), +"$Vd32.cur = vmem($Rx32++#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_cur_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii), +"$Vd32.cur = vmem($Rx32++#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_cur_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32.cur = vmem($Rx32++$Mu2):nt", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000001; +let Inst{31-21} = 0b00101011010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_cur_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32.cur = vmem($Rx32++$Mu2):nt", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000001; +let Inst{31-21} = 0b00101011010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_cur_pred_ai : HInst< +(outs VectorRegs:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{31-21} = 0b00101000110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_nt_cur_pred_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if ($Pv4) $Vd32.cur = vmem($Rt32+#$Ii):nt", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{31-21} = 0b00101000110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_nt_cur_pred_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_cur_pred_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if ($Pv4) $Vd32.cur = vmem($Rx32++#$Ii):nt", +CVI_VM_CUR_LD, TypeCVI_VM_CUR_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_cur_pred_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt", +CVI_VM_CUR_LD, TypeCOPROC_VMEM>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000100; +let Inst{31-21} = 0b00101011110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_cur_pred_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if ($Pv4) $Vd32.cur = vmem($Rx32++$Mu2):nt", +CVI_VM_CUR_LD, TypeCOPROC_VMEM>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000100; +let Inst{31-21} = 0b00101011110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_npred_ai : HInst< +(outs VectorRegs:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{31-21} = 0b00101000110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_nt_npred_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if (!$Pv4) $Vd32 = vmem($Rt32+#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{31-21} = 0b00101000110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_nt_npred_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_npred_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if (!$Pv4) $Vd32 = vmem($Rx32++#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_npred_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000011; +let Inst{31-21} = 0b00101011110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_npred_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if (!$Pv4) $Vd32 = vmem($Rx32++$Mu2):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000011; +let Inst{31-21} = 0b00101011110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii), +"$Vd32 = vmem($Rx32++#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii), +"$Vd32 = vmem($Rx32++#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32 = vmem($Rx32++$Mu2):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b00101011010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32 = vmem($Rx32++$Mu2):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b00101011010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_pred_ai : HInst< +(outs VectorRegs:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{31-21} = 0b00101000110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_nt_pred_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{31-21} = 0b00101000110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_nt_pred_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_pred_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_pred_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000010; +let Inst{31-21} = 0b00101011110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_pred_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2):nt", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000010; +let Inst{31-21} = 0b00101011110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_tmp_ai : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32, s4_0Imm:$Ii), +"$Vd32.tmp = vmem($Rt32+#$Ii):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_nt_tmp_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32, s4_0Imm:$Ii), +"$Vd32.tmp = vmem($Rt32+#$Ii):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_nt_tmp_npred_ai : HInst< +(outs VectorRegs:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{31-21} = 0b00101000110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_nt_tmp_npred_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{31-21} = 0b00101000110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_nt_tmp_npred_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_tmp_npred_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_tmp_npred_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000111; +let Inst{31-21} = 0b00101011110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_tmp_npred_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000111; +let Inst{31-21} = 0b00101011110; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_tmp_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii), +"$Vd32.tmp = vmem($Rx32++#$Ii):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_tmp_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii), +"$Vd32.tmp = vmem($Rx32++#$Ii):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_tmp_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32.tmp = vmem($Rx32++$Mu2):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000010; +let Inst{31-21} = 0b00101011010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_tmp_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32.tmp = vmem($Rx32++$Mu2):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000010; +let Inst{31-21} = 0b00101011010; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_tmp_pred_ai : HInst< +(outs VectorRegs:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{31-21} = 0b00101000110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_nt_tmp_pred_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{31-21} = 0b00101000110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_nt_tmp_pred_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_tmp_pred_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_tmp_pred_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000110; +let Inst{31-21} = 0b00101011110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_nt_tmp_pred_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2):nt", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000110; +let Inst{31-21} = 0b00101011110; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let isNonTemporal = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii), +"$Vd32 = vmem($Rx32++#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii), +"$Vd32 = vmem($Rx32++#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32 = vmem($Rx32++$Mu2)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b00101011000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32 = vmem($Rx32++$Mu2)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b00101011000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let isCVLoadable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_pred_ai : HInst< +(outs VectorRegs:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{31-21} = 0b00101000100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_pred_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if ($Pv4) $Vd32 = vmem($Rt32+#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{31-21} = 0b00101000100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_pred_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_pred_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if ($Pv4) $Vd32 = vmem($Rx32++#$Ii)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_pred_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000010; +let Inst{31-21} = 0b00101011100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_pred_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if ($Pv4) $Vd32 = vmem($Rx32++$Mu2)", +CVI_VM_LD, TypeCVI_VM_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000010; +let Inst{31-21} = 0b00101011100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_tmp_ai : HInst< +(outs VectorRegs:$Vd32), +(ins IntRegs:$Rt32, s4_0Imm:$Ii), +"$Vd32.tmp = vmem($Rt32+#$Ii)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_1244745, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_tmp_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins IntRegs:$Rt32, s4_0Imm:$Ii), +"$Vd32.tmp = vmem($Rt32+#$Ii)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_8437395, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_tmp_npred_ai : HInst< +(outs VectorRegs:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{31-21} = 0b00101000100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_tmp_npred_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if (!$Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{31-21} = 0b00101000100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_tmp_npred_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_tmp_npred_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if (!$Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_tmp_npred_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000111; +let Inst{31-21} = 0b00101011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_tmp_npred_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if (!$Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000111; +let Inst{31-21} = 0b00101011100; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_tmp_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii), +"$Vd32.tmp = vmem($Rx32++#$Ii)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_10039393, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_tmp_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii), +"$Vd32.tmp = vmem($Rx32++#$Ii)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_11039423, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_tmp_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32.tmp = vmem($Rx32++$Mu2)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000010; +let Inst{31-21} = 0b00101011000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_tmp_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2), +"$Vd32.tmp = vmem($Rx32++$Mu2)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15949334, Requires<[HasV60T,UseHVX]> { +let Inst{12-5} = 0b00000010; +let Inst{31-21} = 0b00101011000; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_tmp_pred_ai : HInst< +(outs VectorRegs:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_13338314, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{31-21} = 0b00101000100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vL32b_tmp_pred_ai_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii), +"if ($Pv4) $Vd32.tmp = vmem($Rt32+#$Ii)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_738356, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{31-21} = 0b00101000100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vL32b_tmp_pred_pi : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_14560494, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_tmp_pred_pi_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii), +"if ($Pv4) $Vd32.tmp = vmem($Rx32++#$Ii)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_15560488, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_tmp_pred_ppu : HInst< +(outs VectorRegs:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000110; +let Inst{31-21} = 0b00101011100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vL32b_tmp_pred_ppu_128B : HInst< +(outs VectorRegs128B:$Vd32, IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2), +"if ($Pv4) $Vd32.tmp = vmem($Rx32++$Mu2)", +CVI_VM_TMP_LD, TypeCVI_VM_TMP_LD>, Enc_3158657, Requires<[HasV62T,UseHVX]> { +let Inst{10-5} = 0b000110; +let Inst{31-21} = 0b00101011100; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isCVLoad = 1; +let mayLoad = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_ai : HInst< +(outs), +(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +"vmemu($Rt32+#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_6923828, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b111; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000001; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ai"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32Ub_ai_128B : HInst< +(outs), +(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), +"vmemu($Rt32+#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_5757366, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b111; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000001; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ai_128B"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32Ub_npred_ai : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +"if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b111; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ai"; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32Ub_npred_ai_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), +"if (!$Pv4) vmemu($Rt32+#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b111; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ai_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32Ub_npred_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +"if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_15459921, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_pi"; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_npred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), +"if (!$Pv4) vmemu($Rx32++#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_14459927, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_pi_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_npred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"if (!$Pv4) vmemu($Rx32++$Mu2) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-5} = 0b000111; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ppu"; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_npred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"if (!$Pv4) vmemu($Rx32++$Mu2) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-5} = 0b000111; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ppu_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +"vmemu($Rx32++#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_3296020, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b111; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001001; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_pi"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), +"vmemu($Rx32++#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_2296022, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b111; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001001; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_pi_128B"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_ppu : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"vmemu($Rx32++$Mu2) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_11281763, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{12-5} = 0b00000111; +let Inst{31-21} = 0b00101011001; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ppu"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"vmemu($Rx32++$Mu2) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_11281763, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{12-5} = 0b00000111; +let Inst{31-21} = 0b00101011001; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ppu_128B"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_pred_ai : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +"if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b110; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ai"; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32Ub_pred_ai_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), +"if ($Pv4) vmemu($Rt32+#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b110; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ai_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32Ub_pred_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +"if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_15459921, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_pi"; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_pred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), +"if ($Pv4) vmemu($Rx32++#$Ii) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_14459927, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_pi_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_pred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"if ($Pv4) vmemu($Rx32++$Mu2) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-5} = 0b000110; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ppu"; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32Ub_pred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"if ($Pv4) vmemu($Rx32++$Mu2) = $Vs32", +CVI_VM_STU, TypeCVI_VM_STU>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-5} = 0b000110; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32Ub_ppu_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_ai : HInst< +(outs), +(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +"vmem($Rt32+#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_6923828, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000001; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_ai"; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_ai_128B : HInst< +(outs), +(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), +"vmem($Rt32+#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_5757366, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000001; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32b_new_ai : HInst< +(outs), +(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8), +"vmem($Rt32+#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_6608821, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b00100; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000001; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 2; +} +def V6_vS32b_new_ai_128B : HInst< +(outs), +(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8), +"vmem($Rt32+#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2152247, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b00100; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000001; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def V6_vS32b_new_npred_ai : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8), +"if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_9372046, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01101; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 3; +} +def V6_vS32b_new_npred_ai_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8), +"if (!$Pv4) vmem($Rt32+#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_13937564, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01101; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 3; +} +def V6_vS32b_new_npred_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8), +"if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_3735566, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_npred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8), +"if (!$Pv4) vmem($Rx32++#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2735552, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_npred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +"if (!$Pv4) vmem($Rx32++$Mu2) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-3} = 0b00001101; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_npred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), +"if (!$Pv4) vmem($Rx32++$Mu2) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-3} = 0b00001101; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8), +"vmem($Rx32++#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_12244921, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b00100; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001001; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8), +"vmem($Rx32++#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_11244923, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b00100; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001001; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_ppu : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +"vmem($Rx32++$Mu2) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_1589406, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{12-3} = 0b0000000100; +let Inst{31-21} = 0b00101011001; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), +"vmem($Rx32++$Mu2) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_1589406, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{12-3} = 0b0000000100; +let Inst{31-21} = 0b00101011001; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu_128B"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_pred_ai : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8), +"if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_9372046, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01000; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 3; +} +def V6_vS32b_new_pred_ai_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8), +"if ($Pv4) vmem($Rt32+#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_13937564, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01000; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 3; +} +def V6_vS32b_new_pred_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8), +"if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_3735566, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_pred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8), +"if ($Pv4) vmem($Rx32++#$Ii) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2735552, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_pred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +"if ($Pv4) vmem($Rx32++$Mu2) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-3} = 0b00001000; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_new_pred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), +"if ($Pv4) vmem($Rx32++$Mu2) = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-3} = 0b00001000; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_npred_ai : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +"if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_ai"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_npred_ai_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), +"if (!$Pv4) vmem($Rt32+#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32b_npred_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +"if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15459921, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_pi"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_npred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), +"if (!$Pv4) vmem($Rx32++#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_14459927, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_npred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"if (!$Pv4) vmem($Rx32++$Mu2) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-5} = 0b000001; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_ppu"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_npred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"if (!$Pv4) vmem($Rx32++$Mu2) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-5} = 0b000001; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_ppu_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nqpred_ai : HInst< +(outs), +(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +"if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_16279406, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b00101000100; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_nqpred_ai_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), +"if (!$Qv4) vmem($Rt32+#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_2703240, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b00101000100; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32b_nqpred_pi : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +"if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_12397062, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001100; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nqpred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), +"if (!$Qv4) vmem($Rx32++#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13397056, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001100; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nqpred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"if (!$Qv4) vmem($Rx32++$Mu2) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { +let Inst{10-5} = 0b000001; +let Inst{31-21} = 0b00101011100; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nqpred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"if (!$Qv4) vmem($Rx32++$Mu2) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { +let Inst{10-5} = 0b000001; +let Inst{31-21} = 0b00101011100; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_ai : HInst< +(outs), +(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +"vmem($Rt32+#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_6923828, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000011; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ai"; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_nt_ai_128B : HInst< +(outs), +(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), +"vmem($Rt32+#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_5757366, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000011; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32b_nt_new_ai : HInst< +(outs), +(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8), +"vmem($Rt32+#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_6608821, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b00100; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000011; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 2; +} +def V6_vS32b_nt_new_ai_128B : HInst< +(outs), +(ins IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8), +"vmem($Rt32+#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2152247, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b00100; +let Inst{12-11} = 0b00; +let Inst{31-21} = 0b00101000011; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 2; +} +def V6_vS32b_nt_new_npred_ai : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8), +"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_9372046, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01111; +let Inst{31-21} = 0b00101000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 3; +} +def V6_vS32b_nt_new_npred_ai_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8), +"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_13937564, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01111; +let Inst{31-21} = 0b00101000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 3; +} +def V6_vS32b_nt_new_npred_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8), +"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_3735566, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_npred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8), +"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2735552, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_npred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-3} = 0b00001111; +let Inst{31-21} = 0b00101011111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_npred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), +"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-3} = 0b00001111; +let Inst{31-21} = 0b00101011111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8), +"vmem($Rx32++#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_12244921, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b00100; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001011; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8), +"vmem($Rx32++#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_11244923, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b00100; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001011; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_ppu : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +"vmem($Rx32++$Mu2):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_1589406, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{12-3} = 0b0000000100; +let Inst{31-21} = 0b00101011011; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), +"vmem($Rx32++$Mu2):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_1589406, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{12-3} = 0b0000000100; +let Inst{31-21} = 0b00101011011; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu_128B"; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 3; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_pred_ai : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Os8), +"if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_9372046, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01010; +let Inst{31-21} = 0b00101000111; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 3; +} +def V6_vS32b_nt_new_pred_ai_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Os8), +"if ($Pv4) vmem($Rt32+#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_13937564, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01010; +let Inst{31-21} = 0b00101000111; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 3; +} +def V6_vS32b_nt_new_pred_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Os8), +"if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_3735566, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001111; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_pred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Os8), +"if ($Pv4) vmem($Rx32++#$Ii):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_2735552, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-3} = 0b01010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001111; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_pred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Os8), +"if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-3} = 0b00001010; +let Inst{31-21} = 0b00101011111; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu"; +let DecoderNamespace = "EXT_mmvec"; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_new_pred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Os8), +"if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new", +CVI_VM_NEW_ST, TypeCVI_VM_NEW_ST>, Enc_8498433, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-3} = 0b00001010; +let Inst{31-21} = 0b00101011111; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let isNVStore = 1; +let mayStore = 1; +let isNonTemporal = 1; +let isNewValue = 1; +let BaseOpcode = "V6_vS32b_ppu_128B"; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let opNewValue = 4; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_npred_ai : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b00101000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ai"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_nt_npred_ai_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), +"if (!$Pv4) vmem($Rt32+#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b00101000111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32b_nt_npred_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15459921, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_pi"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_npred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), +"if (!$Pv4) vmem($Rx32++#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_14459927, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_npred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-5} = 0b000001; +let Inst{31-21} = 0b00101011111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ppu"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_npred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"if (!$Pv4) vmem($Rx32++$Mu2):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-5} = 0b000001; +let Inst{31-21} = 0b00101011111; +let isPredicated = 1; +let isPredicatedFalse = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ppu_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_nqpred_ai : HInst< +(outs), +(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +"if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_16279406, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b00101000110; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_nt_nqpred_ai_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), +"if (!$Qv4) vmem($Rt32+#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_2703240, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{31-21} = 0b00101000110; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32b_nt_nqpred_pi : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +"if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_12397062, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001110; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_nqpred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), +"if (!$Qv4) vmem($Rx32++#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13397056, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001110; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_nqpred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"if (!$Qv4) vmem($Rx32++$Mu2):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { +let Inst{10-5} = 0b000001; +let Inst{31-21} = 0b00101011110; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_nqpred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"if (!$Qv4) vmem($Rx32++$Mu2):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { +let Inst{10-5} = 0b000001; +let Inst{31-21} = 0b00101011110; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +"vmem($Rx32++#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_3296020, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001011; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_pi"; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), +"vmem($Rx32++#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_2296022, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001011; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_ppu : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"vmem($Rx32++$Mu2):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_11281763, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b00101011011; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ppu"; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"vmem($Rx32++$Mu2):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_11281763, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b00101011011; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ppu_128B"; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_pred_ai : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +"if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b00101000111; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ai"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_nt_pred_ai_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), +"if ($Pv4) vmem($Rt32+#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b00101000111; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32b_nt_pred_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +"if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15459921, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001111; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_pi"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_pred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), +"if ($Pv4) vmem($Rx32++#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_14459927, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001111; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_pred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"if ($Pv4) vmem($Rx32++$Mu2):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-5} = 0b000000; +let Inst{31-21} = 0b00101011111; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ppu"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_pred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"if ($Pv4) vmem($Rx32++$Mu2):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{10-5} = 0b000000; +let Inst{31-21} = 0b00101011111; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let BaseOpcode = "V6_vS32b_ppu_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_qpred_ai : HInst< +(outs), +(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +"if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_16279406, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b00101000110; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_nt_qpred_ai_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), +"if ($Qv4) vmem($Rt32+#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_2703240, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b00101000110; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32b_nt_qpred_pi : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +"if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_12397062, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001110; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_qpred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), +"if ($Qv4) vmem($Rx32++#$Ii):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13397056, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001110; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_qpred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"if ($Qv4) vmem($Rx32++$Mu2):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { +let Inst{10-5} = 0b000000; +let Inst{31-21} = 0b00101011110; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_nt_qpred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"if ($Qv4) vmem($Rx32++$Mu2):nt = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { +let Inst{10-5} = 0b000000; +let Inst{31-21} = 0b00101011110; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNonTemporal = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_pi : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +"vmem($Rx32++#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_3296020, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001001; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_pi"; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), +"vmem($Rx32++#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_2296022, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b00101001001; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_ppu : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"vmem($Rx32++$Mu2) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_11281763, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b00101011001; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"vmem($Rx32++$Mu2) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_11281763, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{12-5} = 0b00000000; +let Inst{31-21} = 0b00101011001; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNVStorable = 1; +let isPredicable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_pred_ai : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +"if ($Pv4) vmem($Rt32+#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_10075393, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_ai"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_pred_ai_128B : HInst< +(outs), +(ins PredRegs:$Pv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), +"if ($Pv4) vmem($Rt32+#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_9470751, Requires<[HasV60T,UseHVX]>, NewValueRel { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b00101000101; +let isPredicated = 1; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_ai_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32b_pred_pi : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +"if ($Pv4) vmem($Rx32++#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15459921, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_pi"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_pred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), +"if ($Pv4) vmem($Rx32++#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_14459927, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let BaseOpcode = "V6_vS32b_pi_128B"; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_pred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"if ($Pv4) vmem($Rx32++$Mu2) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]> { +let Inst{10-5} = 0b000000; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_pred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins PredRegs:$Pv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"if ($Pv4) vmem($Rx32++$Mu2) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_15733946, Requires<[HasV60T,UseHVX]> { +let Inst{10-5} = 0b000000; +let Inst{31-21} = 0b00101011101; +let isPredicated = 1; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let isNVStorable = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_qpred_ai : HInst< +(outs), +(ins VecPredRegs:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs:$Vs32), +"if ($Qv4) vmem($Rt32+#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_16279406, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b00101000100; +let addrMode = BaseImmOffset; +let accessSize = Vector64Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vS32b_qpred_ai_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rt32, s4_0Imm:$Ii, VectorRegs128B:$Vs32), +"if ($Qv4) vmem($Rt32+#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_2703240, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{31-21} = 0b00101000100; +let addrMode = BaseImmOffset; +let accessSize = Vector128Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vS32b_qpred_pi : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs:$Vs32), +"if ($Qv4) vmem($Rx32++#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_12397062, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001100; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_qpred_pi_128B : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, s3_0Imm:$Ii, VectorRegs128B:$Vs32), +"if ($Qv4) vmem($Rx32++#$Ii) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13397056, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00101001100; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_qpred_ppu : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs:$Vs32), +"if ($Qv4) vmem($Rx32++$Mu2) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { +let Inst{10-5} = 0b000000; +let Inst{31-21} = 0b00101011100; +let addrMode = PostInc; +let accessSize = Vector64Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vS32b_qpred_ppu_128B : HInst< +(outs IntRegs:$Rx32), +(ins VecPredRegs128B:$Qv4, IntRegs:$Rx32in, ModRegs:$Mu2, VectorRegs128B:$Vs32), +"if ($Qv4) vmem($Rx32++$Mu2) = $Vs32", +CVI_VM_ST, TypeCVI_VM_ST>, Enc_13425035, Requires<[HasV60T,UseHVX]> { +let Inst{10-5} = 0b000000; +let Inst{31-21} = 0b00101011100; +let addrMode = PostInc; +let accessSize = Vector128Access; +let mayStore = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Rx32 = $Rx32in"; +} +def V6_vabsdiffh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsdiffh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vabsdiff($Vu32.h,$Vv32.h)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsdiffh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vabsdiffh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsdiffh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vabsdiffh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsdiffub : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vabsdiff($Vu32.ub,$Vv32.ub)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsdiffub_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vabsdiff($Vu32.ub,$Vv32.ub)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsdiffub_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vabsdiffub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsdiffub_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vabsdiffub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsdiffuh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vabsdiff($Vu32.uh,$Vv32.uh)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsdiffuh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vabsdiff($Vu32.uh,$Vv32.uh)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsdiffuh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vabsdiffuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsdiffuh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vabsdiffuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsdiffw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uw = vabsdiff($Vu32.w,$Vv32.w)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsdiffw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uw = vabsdiff($Vu32.w,$Vv32.w)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsdiffw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vabsdiffw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsdiffw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vabsdiffw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.h = vabs($Vu32.h)", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.h = vabs($Vu32.h)", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vabsh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vabsh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsh_sat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.h = vabs($Vu32.h):sat", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsh_sat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.h = vabs($Vu32.h):sat", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsh_sat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vabsh($Vu32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsh_sat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vabsh($Vu32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.w = vabs($Vu32.w)", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.w = vabs($Vu32.w)", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vabsw($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vabsw($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsw_sat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.w = vabs($Vu32.w):sat", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsw_sat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.w = vabs($Vu32.w):sat", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vabsw_sat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vabsw($Vu32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vabsw_sat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vabsw($Vu32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vadd($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vadd($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vaddb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vaddb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddb_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddb_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddb_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vaddb($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddb_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vaddb($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddbnq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4) $Vx32.b += $Vu32.b", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddbnq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4) $Vx32.b += $Vu32.b", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddbnq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4.b) $Vx32.b += $Vu32.b", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddbnq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4.b) $Vx32.b += $Vu32.b", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddbq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4) $Vx32.b += $Vu32.b", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddbq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4) $Vx32.b += $Vu32.b", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddbq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4.b) $Vx32.b += $Vu32.b", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddbq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4.b) $Vx32.b += $Vu32.b", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddbsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vadd($Vu32.b,$Vv32.b):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddbsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vadd($Vu32.b,$Vv32.b):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddbsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vaddb($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddbsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vaddb($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddbsat_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011110101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddbsat_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.b = vadd($Vuu32.b,$Vvv32.b):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011110101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddbsat_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vaddb($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddbsat_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vaddb($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddcarry : HInst< +(outs VectorRegs:$Vd32, VecPredRegs:$Qx4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, VecPredRegs:$Qx4in), +"$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qx4):carry", +CVI_VA, TypeCVI_VA>, Enc_13691337, Requires<[HasV62T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vaddcarry_128B : HInst< +(outs VectorRegs128B:$Vd32, VecPredRegs128B:$Qx4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, VecPredRegs128B:$Qx4in), +"$Vd32.w = vadd($Vu32.w,$Vv32.w,$Qx4):carry", +CVI_VA, TypeCVI_VA>, Enc_13691337, Requires<[HasV62T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vaddclbh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vadd(vclb($Vu32.h),$Vv32.h)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddclbh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vadd(vclb($Vu32.h),$Vv32.h)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddclbw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vadd(vclb($Vu32.w),$Vv32.w)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddclbw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vadd(vclb($Vu32.w),$Vv32.w)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vadd($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vadd($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vaddh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vaddh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddh_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddh_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddh_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vaddh($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddh_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vaddh($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddhnq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4) $Vx32.h += $Vu32.h", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddhnq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4) $Vx32.h += $Vu32.h", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddhnq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4.h) $Vx32.h += $Vu32.h", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddhnq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4.h) $Vx32.h += $Vu32.h", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddhq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4) $Vx32.h += $Vu32.h", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddhq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4) $Vx32.h += $Vu32.h", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddhq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4.h) $Vx32.h += $Vu32.h", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddhq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4.h) $Vx32.h += $Vu32.h", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddhsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vadd($Vu32.h,$Vv32.h):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddhsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vadd($Vu32.h,$Vv32.h):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddhsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vaddh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddhsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vaddh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddhsat_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddhsat_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.h = vadd($Vuu32.h,$Vvv32.h):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddhsat_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vaddh($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddhsat_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vaddh($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddhw : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.w = vadd($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddhw_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.w = vadd($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddhw_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32.w += vadd($Vu32.h,$Vv32.h)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vaddhw_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32.w += vadd($Vu32.h,$Vv32.h)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vaddhw_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32 += vaddh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vaddhw_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32 += vaddh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vaddhw_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vaddh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddhw_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vaddh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddubh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.h = vadd($Vu32.ub,$Vv32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddubh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.h = vadd($Vu32.ub,$Vv32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddubh_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32.h += vadd($Vu32.ub,$Vv32.ub)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vaddubh_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32.h += vadd($Vu32.ub,$Vv32.ub)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vaddubh_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32 += vaddub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vaddubh_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32 += vaddub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vaddubh_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vaddub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddubh_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vaddub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddubsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vadd($Vu32.ub,$Vv32.ub):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddubsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vadd($Vu32.ub,$Vv32.ub):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddubsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vaddub($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddubsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vaddub($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddubsat_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.ub = vadd($Vuu32.ub,$Vvv32.ub):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddubsat_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.ub = vadd($Vuu32.ub,$Vvv32.ub):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddubsat_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vaddub($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddubsat_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vaddub($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddububb_sat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vadd($Vu32.ub,$Vv32.b):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011110101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddububb_sat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vadd($Vu32.ub,$Vv32.b):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011110101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vadduhsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vadd($Vu32.uh,$Vv32.uh):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vadduhsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vadd($Vu32.uh,$Vv32.uh):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vadduhsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vadduh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vadduhsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vadduh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vadduhsat_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.uh = vadd($Vuu32.uh,$Vvv32.uh):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vadduhsat_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.uh = vadd($Vuu32.uh,$Vvv32.uh):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vadduhsat_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vadduh($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vadduhsat_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vadduh($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vadduhw : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.w = vadd($Vu32.uh,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vadduhw_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.w = vadd($Vu32.uh,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vadduhw_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32.w += vadd($Vu32.uh,$Vv32.uh)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vadduhw_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32.w += vadd($Vu32.uh,$Vv32.uh)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vadduhw_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32 += vadduh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vadduhw_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32 += vadduh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vadduhw_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vadduh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vadduhw_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vadduh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vadduwsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uw = vadd($Vu32.uw,$Vv32.uw):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vadduwsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uw = vadd($Vu32.uw,$Vv32.uw):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vadduwsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vadduw($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vadduwsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vadduw($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vadduwsat_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.uw = vadd($Vuu32.uw,$Vvv32.uw):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011110101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vadduwsat_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.uw = vadd($Vuu32.uw,$Vvv32.uw):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011110101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vadduwsat_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vadduw($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vadduwsat_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vadduw($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vadd($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vadd($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vaddw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vaddw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddw_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddw_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddw_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vaddw($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddw_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vaddw($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddwnq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4) $Vx32.w += $Vu32.w", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddwnq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4) $Vx32.w += $Vu32.w", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddwnq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4.w) $Vx32.w += $Vu32.w", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddwnq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4.w) $Vx32.w += $Vu32.w", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddwq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4) $Vx32.w += $Vu32.w", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddwq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4) $Vx32.w += $Vu32.w", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddwq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4.w) $Vx32.w += $Vu32.w", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddwq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4.w) $Vx32.w += $Vu32.w", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaddwsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vadd($Vu32.w,$Vv32.w):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddwsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vadd($Vu32.w,$Vv32.w):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddwsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vaddw($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddwsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vaddw($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddwsat_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddwsat_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.w = vadd($Vuu32.w,$Vvv32.w):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaddwsat_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vaddw($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaddwsat_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vaddw($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_valignb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = valign($Vu32,$Vv32,$Rt8)", +CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_valignb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = valign($Vu32,$Vv32,$Rt8)", +CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_valignbi : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii), +"$Vd32 = valign($Vu32,$Vv32,#$Ii)", +CVI_VP_LONG, TypeCVI_VP>, Enc_7171569, Requires<[HasV60T,UseHVX]> { +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011110001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_valignbi_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii), +"$Vd32 = valign($Vu32,$Vv32,#$Ii)", +CVI_VP_LONG, TypeCVI_VP>, Enc_7171569, Requires<[HasV60T,UseHVX]> { +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011110001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vand : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vand($Vu32,$Vv32)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vand_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vand($Vu32,$Vv32)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vandnqrt : HInst< +(outs VectorRegs:$Vd32), +(ins VecPredRegs:$Qu4, IntRegs:$Rt32), +"$Vd32 = vand(!$Qu4,$Rt32)", +CVI_VX, TypeCVI_VX>, Enc_4711514, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-10} = 0b0001; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vandnqrt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecPredRegs128B:$Qu4, IntRegs:$Rt32), +"$Vd32 = vand(!$Qu4,$Rt32)", +CVI_VX, TypeCVI_VX>, Enc_4711514, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-10} = 0b0001; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vandnqrt_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VecPredRegs:$Qu4, IntRegs:$Rt32), +"$Vx32 |= vand(!$Qu4,$Rt32)", +CVI_VX, TypeCVI_VX>, Enc_4944558, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-10} = 0b1001; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vandnqrt_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VecPredRegs128B:$Qu4, IntRegs:$Rt32), +"$Vx32 |= vand(!$Qu4,$Rt32)", +CVI_VX, TypeCVI_VX>, Enc_4944558, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-10} = 0b1001; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vandnqrt_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VecPredRegs:$Qu4, IntRegs:$Rt32), +"$Vx32.ub |= vand(!$Qu4.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vandnqrt_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VecPredRegs128B:$Qu4, IntRegs:$Rt32), +"$Vx32.ub |= vand(!$Qu4.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vandnqrt_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VecPredRegs:$Qu4, IntRegs:$Rt32), +"$Vd32.ub = vand(!$Qu4.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vandnqrt_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecPredRegs128B:$Qu4, IntRegs:$Rt32), +"$Vd32.ub = vand(!$Qu4.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vandqrt : HInst< +(outs VectorRegs:$Vd32), +(ins VecPredRegs:$Qu4, IntRegs:$Rt32), +"$Vd32 = vand($Qu4,$Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_4711514, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-10} = 0b0000; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vandqrt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecPredRegs128B:$Qu4, IntRegs:$Rt32), +"$Vd32 = vand($Qu4,$Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_4711514, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-10} = 0b0000; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vandqrt_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VecPredRegs:$Qu4, IntRegs:$Rt32), +"$Vx32 |= vand($Qu4,$Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_4944558, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-10} = 0b1000; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vandqrt_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VecPredRegs128B:$Qu4, IntRegs:$Rt32), +"$Vx32 |= vand($Qu4,$Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_4944558, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-10} = 0b1000; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vandqrt_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VecPredRegs:$Qu4, IntRegs:$Rt32), +"$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vandqrt_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VecPredRegs128B:$Qu4, IntRegs:$Rt32), +"$Vx32.ub |= vand($Qu4.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vandqrt_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VecPredRegs:$Qu4, IntRegs:$Rt32), +"$Vd32.ub = vand($Qu4.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vandqrt_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecPredRegs128B:$Qu4, IntRegs:$Rt32), +"$Vd32.ub = vand($Qu4.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vandvnqv : HInst< +(outs VectorRegs:$Vd32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vu32), +"$Vd32 = vand(!$Qv4,$Vu32)", +CVI_VA, TypeCVI_VA>, Enc_1220199, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vandvnqv_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vu32), +"$Vd32 = vand(!$Qv4,$Vu32)", +CVI_VA, TypeCVI_VA>, Enc_1220199, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vandvqv : HInst< +(outs VectorRegs:$Vd32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vu32), +"$Vd32 = vand($Qv4,$Vu32)", +CVI_VA, TypeCVI_VA>, Enc_1220199, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vandvqv_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vu32), +"$Vd32 = vand($Qv4,$Vu32)", +CVI_VA, TypeCVI_VA>, Enc_1220199, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000011; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vandvrt : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Qd4 = vand($Vu32,$Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_11498120, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vandvrt_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Qd4 = vand($Vu32,$Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_11498120, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vandvrt_acc : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Qx4 |= vand($Vu32,$Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_10612292, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vandvrt_acc_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Qx4 |= vand($Vu32,$Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_10612292, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vandvrt_acc_alt : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vandvrt_acc_alt_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Qx4.ub |= vand($Vu32.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vandvrt_alt : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Qd4.ub = vand($Vu32.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vandvrt_alt_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Qd4.ub = vand($Vu32.ub,$Rt32.ub)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaslh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vasl($Vu32.h,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaslh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vasl($Vu32.h,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaslh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vaslh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaslh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vaslh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaslhv : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vasl($Vu32.h,$Vv32.h)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaslhv_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vasl($Vu32.h,$Vv32.h)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaslhv_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vaslh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaslhv_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vaslh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaslw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vasl($Vu32.w,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaslw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vasl($Vu32.w,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaslw_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vasl($Vu32.w,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaslw_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vasl($Vu32.w,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaslw_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vaslw($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaslw_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vaslw($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vaslw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vaslw($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaslw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vaslw($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaslwv : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vasl($Vu32.w,$Vv32.w)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaslwv_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vasl($Vu32.w,$Vv32.w)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vaslwv_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vaslw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vaslwv_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vaslw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vasr($Vu32.h,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vasr($Vu32.h,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vasrh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vasrh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrhbrndsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrhbrndsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrhbrndsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def V6_vasrhbsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrhbsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.b = vasr($Vu32.h,$Vv32.h,$Rt8):sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrhubrndsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrhubrndsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):rnd:sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrhubrndsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def V6_vasrhubsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrhubsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.ub = vasr($Vu32.h,$Vv32.h,$Rt8):sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrhubsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = vasrhub($Vu32,$Vv32,$Rt8):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def V6_vasrhv : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vasr($Vu32.h,$Vv32.h)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrhv_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vasr($Vu32.h,$Vv32.h)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrhv_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vasrh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrhv_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vasrh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasruwuhrndsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):rnd:sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasruwuhrndsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.uh = vasr($Vu32.uw,$Vv32.uw,$Rt8):rnd:sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vasr($Vu32.w,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vasr($Vu32.w,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrw_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vasr($Vu32.w,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vasrw_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vasr($Vu32.w,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vasrw_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vasrw($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vasrw_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vasrw($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vasrw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vasrw($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vasrw($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrwh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrwh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8)", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrwh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def V6_vasrwhrndsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrwhrndsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrwhrndsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def V6_vasrwhsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrwhsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.h = vasr($Vu32.w,$Vv32.w,$Rt8):sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrwhsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = vasrwh($Vu32,$Vv32,$Rt8):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def V6_vasrwuhrndsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrwuhrndsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):rnd:sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrwuhsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrwuhsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.uh = vasr($Vu32.w,$Vv32.w,$Rt8):sat", +CVI_VS, TypeCVI_VS>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrwuhsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = vasrwuh($Vu32,$Vv32,$Rt8):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def V6_vasrwv : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vasr($Vu32.w,$Vv32.w)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrwv_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vasr($Vu32.w,$Vv32.w)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vasrwv_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vasrw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vasrwv_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vasrw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vassign : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = $Vu32", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-16} = 0b0001111000000011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vassign_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = $Vu32", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-16} = 0b0001111000000011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vassignp : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32), +"$Vdd32 = $Vuu32", +CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vassignp_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32), +"$Vdd32 = $Vuu32", +CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavgh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vavg($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vavg($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavgh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vavgh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vavgh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavghrnd : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vavg($Vu32.h,$Vv32.h):rnd", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavghrnd_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vavg($Vu32.h,$Vv32.h):rnd", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavghrnd_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vavgh($Vu32,$Vv32):rnd", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavghrnd_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vavgh($Vu32,$Vv32):rnd", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavgub : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgub_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavgub_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vavgub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgub_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vavgub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavgubrnd : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub):rnd", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgubrnd_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vavg($Vu32.ub,$Vv32.ub):rnd", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavgubrnd_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vavgub($Vu32,$Vv32):rnd", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgubrnd_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vavgub($Vu32,$Vv32):rnd", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavguh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavguh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavguh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vavguh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavguh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vavguh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavguhrnd : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh):rnd", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavguhrnd_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vavg($Vu32.uh,$Vv32.uh):rnd", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavguhrnd_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vavguh($Vu32,$Vv32):rnd", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavguhrnd_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vavguh($Vu32,$Vv32):rnd", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavgw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vavg($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vavg($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavgw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vavgw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vavgw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavgwrnd : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vavg($Vu32.w,$Vv32.w):rnd", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgwrnd_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vavg($Vu32.w,$Vv32.w):rnd", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vavgwrnd_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vavgw($Vu32,$Vv32):rnd", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vavgwrnd_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vavgw($Vu32,$Vv32):rnd", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vccombine : HInst< +(outs VecDblRegs:$Vdd32), +(ins PredRegs:$Ps4, VectorRegs:$Vu32, VectorRegs:$Vv32), +"if ($Ps4) $Vdd32 = vcombine($Vu32,$Vv32)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_16145290, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011010011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vccombine_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins PredRegs:$Ps4, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"if ($Ps4) $Vdd32 = vcombine($Vu32,$Vv32)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_16145290, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011010011; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vcl0h : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.uh = vcl0($Vu32.uh)", +CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vcl0h_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.uh = vcl0($Vu32.uh)", +CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vcl0h_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vcl0h($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vcl0h_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vcl0h($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vcl0w : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.uw = vcl0($Vu32.uw)", +CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vcl0w_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.uw = vcl0($Vu32.uw)", +CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vcl0w_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vcl0w($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vcl0w_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vcl0w($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vcmov : HInst< +(outs VectorRegs:$Vd32), +(ins PredRegs:$Ps4, VectorRegs:$Vu32), +"if ($Ps4) $Vd32 = $Vu32", +CVI_VA, TypeCVI_VA>, Enc_12023037, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001101000000000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vcmov_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins PredRegs:$Ps4, VectorRegs128B:$Vu32), +"if ($Ps4) $Vd32 = $Vu32", +CVI_VA, TypeCVI_VA>, Enc_12023037, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001101000000000; +let isPredicated = 1; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vcombine : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vcombine($Vu32,$Vv32)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let isRegSequence = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vcombine_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vcombine($Vu32,$Vv32)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let isRegSequence = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vd0 : HInst< +(outs VectorRegs:$Vd32), +(ins), +"$Vd32 = #0", +CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vd0_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins), +"$Vd32 = #0", +CVI_VA, TypeCVI_VA>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdeal : HInst< +(outs VectorRegs:$Vy32, VectorRegs:$Vx32), +(ins VectorRegs:$Vy32in, VectorRegs:$Vx32in, IntRegs:$Rt32), +"vdeal($Vy32,$Vx32,$Rt32)", +CVI_VP_VS_LONG_EARLY, TypeCVI_VP_VS>, Enc_11422009, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001111; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; +} +def V6_vdeal_128B : HInst< +(outs VectorRegs128B:$Vy32, VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vy32in, VectorRegs128B:$Vx32in, IntRegs:$Rt32), +"vdeal($Vy32,$Vx32,$Rt32)", +CVI_VP_VS_LONG_EARLY, TypeCVI_VP_VS>, Enc_11422009, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001111; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; +} +def V6_vdealb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.b = vdeal($Vu32.b)", +CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdealb4w : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vdeale($Vu32.b,$Vv32.b)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdealb4w_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vdeale($Vu32.b,$Vv32.b)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdealb4w_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vdealb4w($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdealb4w_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vdealb4w($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdealb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.b = vdeal($Vu32.b)", +CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdealb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vdealb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdealb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vdealb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdealh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.h = vdeal($Vu32.h)", +CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdealh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.h = vdeal($Vu32.h)", +CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdealh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vdealh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdealh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vdealh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdealvdd : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vdd32 = vdeal($Vu32,$Vv32,$Rt8)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdealvdd_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vdd32 = vdeal($Vu32,$Vv32,$Rt8)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdelta : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vdelta($Vu32,$Vv32)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdelta_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vdelta($Vu32,$Vv32)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpybus : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vdmpy($Vu32.ub,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpybus_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vdmpy($Vu32.ub,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpybus_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.h += vdmpy($Vu32.ub,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpybus_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.h += vdmpy($Vu32.ub,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpybus_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vdmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpybus_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vdmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpybus_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vdmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpybus_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vdmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpybus_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32.h = vdmpy($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpybus_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32.h = vdmpy($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpybus_dv_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32.h += vdmpy($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdmpybus_dv_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32.h += vdmpy($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdmpybus_dv_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vdmpybus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdmpybus_dv_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vdmpybus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdmpybus_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vdmpybus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpybus_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vdmpybus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vu32.h,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vu32.h,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhb_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vdmpy($Vu32.h,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhb_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vdmpy($Vu32.h,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhb_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vdmpyhb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhb_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vdmpyhb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vdmpyhb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vdmpyhb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhb_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32.w = vdmpy($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhb_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32.w = vdmpy($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhb_dv_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32.w += vdmpy($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdmpyhb_dv_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32.w += vdmpy($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdmpyhb_dv_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vdmpyhb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdmpyhb_dv_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vdmpyhb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdmpyhb_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vdmpyhb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhb_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vdmpyhb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhisat : HInst< +(outs VectorRegs:$Vd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vuu32.h,$Rt32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_36641, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhisat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vuu32.h,$Rt32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_36641, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhisat_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vx32.w += vdmpy($Vuu32.h,$Rt32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5890213, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhisat_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vx32.w += vdmpy($Vuu32.h,$Rt32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5890213, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhisat_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vx32 += vdmpyh($Vuu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhisat_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vx32 += vdmpyh($Vuu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhisat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vd32 = vdmpyh($Vuu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhisat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vd32 = vdmpyh($Vuu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vu32.h,$Rt32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vu32.h,$Rt32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhsat_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vdmpy($Vu32.h,$Rt32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsat_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vdmpy($Vu32.h,$Rt32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsat_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vdmpyh($Vu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsat_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vdmpyh($Vu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vdmpyh($Vu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vdmpyh($Vu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhsuisat : HInst< +(outs VectorRegs:$Vd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vuu32.h,$Rt32.uh,#1):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_36641, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhsuisat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vuu32.h,$Rt32.uh,#1):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_36641, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhsuisat_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vx32.w += vdmpy($Vuu32.h,$Rt32.uh,#1):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5890213, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsuisat_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vx32.w += vdmpy($Vuu32.h,$Rt32.uh,#1):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5890213, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsuisat_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsuisat_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vx32 += vdmpyhsu($Vuu32,$Rt32,#1):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsuisat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhsuisat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vd32 = vdmpyhsu($Vuu32,$Rt32,#1):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhsusat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vu32.h,$Rt32.uh):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhsusat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vdmpy($Vu32.h,$Rt32.uh):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhsusat_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vdmpy($Vu32.h,$Rt32.uh):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsusat_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vdmpy($Vu32.h,$Rt32.uh):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsusat_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vdmpyhsu($Vu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsusat_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vdmpyhsu($Vu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhsusat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vdmpyhsu($Vu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhsusat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vdmpyhsu($Vu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhvsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vdmpy($Vu32.h,$Vv32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhvsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vdmpy($Vu32.h,$Vv32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdmpyhvsat_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32.w += vdmpy($Vu32.h,$Vv32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhvsat_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32.w += vdmpy($Vu32.h,$Vv32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhvsat_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32 += vdmpyh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhvsat_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32 += vdmpyh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vdmpyhvsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vdmpyh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdmpyhvsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vdmpyh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdsaduh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32.uw = vdsad($Vuu32.uh,$Rt32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdsaduh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32.uw = vdsad($Vuu32.uh,$Rt32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vdsaduh_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32.uw += vdsad($Vuu32.uh,$Rt32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdsaduh_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32.uw += vdsad($Vuu32.uh,$Rt32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdsaduh_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vdsaduh($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdsaduh_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vdsaduh($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vdsaduh_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vdsaduh($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vdsaduh_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vdsaduh($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_veqb : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.eq($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_veqb_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.eq($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_veqb_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqb_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqb_or : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqb_or_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqb_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqb_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqh : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.eq($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_veqh_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.eq($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_veqh_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqh_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqh_or : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqh_or_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqh_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqh_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqw : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.eq($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_veqw_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.eq($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_veqw_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqw_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.eq($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqw_or : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqw_or_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.eq($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqw_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_veqw_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.eq($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtb : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vgtb_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.gt($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vgtb_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtb_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtb_or : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtb_or_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtb_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtb_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgth : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.gt($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vgth_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.gt($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vgth_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgth_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgth_or : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgth_or_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgth_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgth_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtub : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.gt($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vgtub_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.gt($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vgtub_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtub_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtub_or : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b011000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtub_or_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b011000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtub_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b101000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtub_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b101000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuh : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.gt($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vgtuh_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.gt($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vgtuh_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuh_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuh_or : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b011001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuh_or_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b011001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuh_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b101001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuh_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b101001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuw : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.gt($Vu32.uw,$Vv32.uw)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vgtuw_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.gt($Vu32.uw,$Vv32.uw)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vgtuw_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.uw,$Vv32.uw)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuw_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.uw,$Vv32.uw)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b001010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuw_or : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.uw,$Vv32.uw)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b011010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuw_or_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.uw,$Vv32.uw)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b011010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuw_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.uw,$Vv32.uw)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b101010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtuw_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.uw,$Vv32.uw)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b101010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtw : HInst< +(outs VecPredRegs:$Qd4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qd4 = vcmp.gt($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vgtw_128B : HInst< +(outs VecPredRegs128B:$Qd4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qd4 = vcmp.gt($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_13983714, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vgtw_and : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtw_and_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 &= vcmp.gt($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b000110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtw_or : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtw_or_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 |= vcmp.gt($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b010110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtw_xor : HInst< +(outs VecPredRegs:$Qx4), +(ins VecPredRegs:$Qx4in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vgtw_xor_128B : HInst< +(outs VecPredRegs128B:$Qx4), +(ins VecPredRegs128B:$Qx4in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Qx4 ^= vcmp.gt($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_7470998, Requires<[HasV60T,UseHVX]> { +let Inst{7-2} = 0b100110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vhist : HInst< +(outs), +(ins), +"vhist", +CVI_HIST, TypeCVI_HIST>, Enc_0, Requires<[HasV60T,UseHVX]> { +let Inst{13-0} = 0b10000010000000; +let Inst{31-16} = 0b0001111000000000; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vhist_128B : HInst< +(outs), +(ins), +"vhist", +CVI_HIST, TypeCVI_HIST>, Enc_0, Requires<[HasV60T,UseHVX]> { +let Inst{13-0} = 0b10000010000000; +let Inst{31-16} = 0b0001111000000000; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vhistq : HInst< +(outs), +(ins VecPredRegs:$Qv4), +"vhist($Qv4)", +CVI_HIST, TypeCVI_HIST>, Enc_4109168, Requires<[HasV60T,UseHVX]> { +let Inst{13-0} = 0b10000010000000; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vhistq_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4), +"vhist($Qv4)", +CVI_HIST, TypeCVI_HIST>, Enc_4109168, Requires<[HasV60T,UseHVX]> { +let Inst{13-0} = 0b10000010000000; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vinsertwr : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, IntRegs:$Rt32), +"$Vx32.w = vinsert($Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_313333, Requires<[HasV60T,UseHVX]> { +let Inst{13-5} = 0b100000001; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vinsertwr_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, IntRegs:$Rt32), +"$Vx32.w = vinsert($Rt32)", +CVI_VX_LATE, TypeCVI_VX>, Enc_313333, Requires<[HasV60T,UseHVX]> { +let Inst{13-5} = 0b100000001; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vlalignb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = vlalign($Vu32,$Vv32,$Rt8)", +CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlalignb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32 = vlalign($Vu32,$Vv32,$Rt8)", +CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlalignbi : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii), +"$Vd32 = vlalign($Vu32,$Vv32,#$Ii)", +CVI_VP_LONG, TypeCVI_VP>, Enc_7171569, Requires<[HasV60T,UseHVX]> { +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011110011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlalignbi_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii), +"$Vd32 = vlalign($Vu32,$Vv32,#$Ii)", +CVI_VP_LONG, TypeCVI_VP>, Enc_7171569, Requires<[HasV60T,UseHVX]> { +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011110011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlsrb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.ub = vlsr($Vu32.ub,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlsrb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.ub = vlsr($Vu32.ub,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlsrh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.uh = vlsr($Vu32.uh,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlsrh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.uh = vlsr($Vu32.uh,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlsrh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vlsrh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlsrh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vlsrh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlsrhv : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vlsr($Vu32.h,$Vv32.h)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlsrhv_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vlsr($Vu32.h,$Vv32.h)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlsrhv_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vlsrh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlsrhv_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vlsrh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlsrw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.uw = vlsr($Vu32.uw,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlsrw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.uw = vlsr($Vu32.uw,$Rt32)", +CVI_VS, TypeCVI_VS>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlsrw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vlsrw($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlsrw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vlsrw($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlsrwv : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vlsr($Vu32.w,$Vv32.w)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlsrwv_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vlsr($Vu32.w,$Vv32.w)", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlsrwv_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vlsrw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlsrwv_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vlsrw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlutvvb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8)", +CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlutvvb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8)", +CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlutvvb_nm : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8):nomatch", +CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlutvvb_nm_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vd32.b = vlut32($Vu32.b,$Vv32.b,$Rt8):nomatch", +CVI_VP_LONG, TypeCVI_VP>, Enc_11083408, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlutvvb_oracc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,$Rt8)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_8877260, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vlutvvb_oracc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,$Rt8)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_8877260, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vlutvvb_oracci : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii), +"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,#$Ii)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_8280533, Requires<[HasV62T,UseHVX]> { +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vlutvvb_oracci_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii), +"$Vx32.b |= vlut32($Vu32.b,$Vv32.b,#$Ii)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_8280533, Requires<[HasV62T,UseHVX]> { +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100110; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vlutvvbi : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii), +"$Vd32.b = vlut32($Vu32.b,$Vv32.b,#$Ii)", +CVI_VP_LONG, TypeCVI_VP>, Enc_7171569, Requires<[HasV62T,UseHVX]> { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011110001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlutvvbi_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii), +"$Vd32.b = vlut32($Vu32.b,$Vv32.b,#$Ii)", +CVI_VP_LONG, TypeCVI_VP>, Enc_7171569, Requires<[HasV62T,UseHVX]> { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011110001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlutvwh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlutvwh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlutvwh_nm : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8):nomatch", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlutvwh_nm_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,$Rt8):nomatch", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-24} = 0b00011000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vlutvwh_oracc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,$Rt8)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_16213761, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vlutvwh_oracc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,$Rt8)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_16213761, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vlutvwh_oracci : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii), +"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,#$Ii)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_3457570, Requires<[HasV62T,UseHVX]> { +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vlutvwh_oracci_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii), +"$Vxx32.h |= vlut16($Vu32.b,$Vv32.h,#$Ii)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_3457570, Requires<[HasV62T,UseHVX]> { +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vlutvwhi : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, u3_0Imm:$Ii), +"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,#$Ii)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_13261538, Requires<[HasV62T,UseHVX]> { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011110011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vlutvwhi_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, u3_0Imm:$Ii), +"$Vdd32.h = vlut16($Vu32.b,$Vv32.h,#$Ii)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_13261538, Requires<[HasV62T,UseHVX]> { +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011110011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmaxb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vmax($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmaxb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vmax($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmaxb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmaxb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmaxb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmaxb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmaxh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vmax($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmaxh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vmax($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmaxh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmaxh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmaxh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmaxh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmaxub : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vmax($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmaxub_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vmax($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmaxub_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmaxub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmaxub_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmaxub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmaxuh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vmax($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmaxuh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vmax($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmaxuh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmaxuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmaxuh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmaxuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmaxw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vmax($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmaxw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vmax($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmaxw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmaxw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmaxw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmaxw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vminb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vmin($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vminb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vmin($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vminb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vminb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vminb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vminb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vminh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vmin($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vminh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vmin($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vminh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vminh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vminh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vminh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vminub : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vmin($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vminub_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vmin($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vminub_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vminub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vminub_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vminub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vminuh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vmin($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vminuh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vmin($Vu32.uh,$Vv32.uh)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vminuh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vminuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vminuh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vminuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vminw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vmin($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vminw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vmin($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vminw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vminw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vminw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vminw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpabus : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpabus_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32.h = vmpa($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpabus_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpabus_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32.h += vmpa($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpabus_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vmpabus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpabus_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vmpabus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpabus_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vmpabus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpabus_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vmpabus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpabusv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpabusv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.b)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpabusv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vmpabus($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpabusv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vmpabus($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpabuuv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.ub)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpabuuv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.h = vmpa($Vuu32.ub,$Vvv32.ub)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpabuuv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vmpabuu($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpabuuv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vmpabuu($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpahb : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32.w = vmpa($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpahb_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32.w = vmpa($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpahb_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32.w += vmpa($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpahb_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32.w += vmpa($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpahb_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vmpahb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpahb_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vmpahb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpahb_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vmpahb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpahb_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vmpahb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpauhb : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32.w = vmpa($Vuu32.uh,$Rt32.b)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpauhb_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32.w = vmpa($Vuu32.uh,$Rt32.b)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpauhb_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32.w += vmpa($Vuu32.uh,$Rt32.b)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpauhb_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32.w += vmpa($Vuu32.uh,$Rt32.b)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpauhb_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vmpauhb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpauhb_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vmpauhb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpauhb_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vmpauhb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpauhb_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vmpauhb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpybus : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vdd32.h = vmpy($Vu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpybus_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vdd32.h = vmpy($Vu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpybus_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vxx32.h += vmpy($Vu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybus_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vxx32.h += vmpy($Vu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybus_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vxx32 += vmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybus_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vxx32 += vmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybus_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vdd32 = vmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpybus_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vdd32 = vmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpybusv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.h = vmpy($Vu32.ub,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpybusv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.h = vmpy($Vu32.ub,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpybusv_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32.h += vmpy($Vu32.ub,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybusv_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32.h += vmpy($Vu32.ub,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybusv_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32 += vmpybus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybusv_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32 += vmpybus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybusv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vmpybus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpybusv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vmpybus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpybv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.h = vmpy($Vu32.b,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpybv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.h = vmpy($Vu32.b,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpybv_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32.h += vmpy($Vu32.b,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybv_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32.h += vmpy($Vu32.b,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybv_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32 += vmpyb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybv_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32 += vmpyb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpybv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vmpyb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpybv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vmpyb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyewuh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vmpye($Vu32.w,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyewuh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vmpye($Vu32.w,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyewuh_64 : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vmpye($Vu32.w,$Vv32.uh)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011110101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyewuh_64_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vmpye($Vu32.w,$Vv32.uh)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011110101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyewuh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmpyewuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyewuh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmpyewuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vdd32.w = vmpy($Vu32.h,$Rt32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vdd32.w = vmpy($Vu32.h,$Rt32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyh_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vdd32 = vmpyh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyh_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vdd32 = vmpyh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyhsat_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vxx32.w += vmpy($Vu32.h,$Rt32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhsat_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vxx32.w += vmpy($Vu32.h,$Rt32.h):sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhsat_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vxx32 += vmpyh($Vu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhsat_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vxx32 += vmpyh($Vu32,$Rt32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhsrs : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:rnd:sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyhsrs_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:rnd:sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyhsrs_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyhsrs_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyh($Vu32,$Rt32):<<1:rnd:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyhss : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyhss_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vmpy($Vu32.h,$Rt32.h):<<1:sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyhss_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyhss_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyh($Vu32,$Rt32):<<1:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyhus : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.w = vmpy($Vu32.h,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyhus_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.w = vmpy($Vu32.h,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyhus_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32.w += vmpy($Vu32.h,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhus_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32.w += vmpy($Vu32.h,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhus_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32 += vmpyhus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhus_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32 += vmpyhus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhus_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vmpyhus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyhus_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vmpyhus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyhv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.w = vmpy($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyhv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.w = vmpy($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyhv_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32.w += vmpy($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhv_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32.w += vmpy($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhv_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32 += vmpyh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhv_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32 += vmpyh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyhv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vmpyh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyhv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vmpyh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyhvsrs : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vmpy($Vu32.h,$Vv32.h):<<1:rnd:sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyhvsrs_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vmpy($Vu32.h,$Vv32.h):<<1:rnd:sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyhvsrs_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyhvsrs_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmpyh($Vu32,$Vv32):<<1:rnd:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyieoh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vmpyieo($Vu32.h,$Vv32.h)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyieoh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vmpyieo($Vu32.h,$Vv32.h)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyiewh_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32.w += vmpyie($Vu32.w,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiewh_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32.w += vmpyie($Vu32.w,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiewh_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32 += vmpyiewh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiewh_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32 += vmpyiewh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiewuh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vmpyie($Vu32.w,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyiewuh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vmpyie($Vu32.w,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyiewuh_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32.w += vmpyie($Vu32.w,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiewuh_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32.w += vmpyie($Vu32.w,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiewuh_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32 += vmpyiewuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiewuh_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32 += vmpyiewuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiewuh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmpyiewuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyiewuh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmpyiewuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyih : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vmpyi($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyih_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vmpyi($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyih_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32.h += vmpyi($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyih_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32.h += vmpyi($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyih_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32 += vmpyih($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyih_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32 += vmpyih($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyih_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmpyih($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyih_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmpyih($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyihb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vmpyi($Vu32.h,$Rt32.b)", +CVI_VX_LONG, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyihb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.h = vmpyi($Vu32.h,$Rt32.b)", +CVI_VX_LONG, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyihb_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.h += vmpyi($Vu32.h,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyihb_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.h += vmpyi($Vu32.h,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyihb_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vmpyihb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyihb_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vmpyihb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyihb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyihb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyihb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyihb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyiowh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vmpyio($Vu32.w,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyiowh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vmpyio($Vu32.w,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyiowh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmpyiowh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyiowh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmpyiowh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyiwb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vmpyi($Vu32.w,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyiwb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vmpyi($Vu32.w,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyiwb_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vmpyi($Vu32.w,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiwb_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vmpyi($Vu32.w,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiwb_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vmpyiwb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiwb_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vmpyiwb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiwb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyiwb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyiwb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyiwb($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyiwh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vmpyi($Vu32.w,$Rt32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyiwh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vmpyi($Vu32.w,$Rt32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyiwh_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vmpyi($Vu32.w,$Rt32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiwh_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vmpyi($Vu32.w,$Rt32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiwh_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vmpyiwh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiwh_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vmpyiwh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiwh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyiwh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyiwh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyiwh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyiwub : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vmpyi($Vu32.w,$Rt32.ub)", +CVI_VX_LONG, TypeCVI_VX>, Enc_16214129, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyiwub_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vmpyi($Vu32.w,$Rt32.ub)", +CVI_VX_LONG, TypeCVI_VX>, Enc_16214129, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyiwub_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vmpyi($Vu32.w,$Rt32.ub)", +CVI_VX_LONG, TypeCVI_VX>, Enc_10058269, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiwub_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vmpyi($Vu32.w,$Rt32.ub)", +CVI_VX_LONG, TypeCVI_VX>, Enc_10058269, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiwub_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vmpyiwub($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiwub_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vmpyiwub($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyiwub_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyiwub($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyiwub_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vmpyiwub($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyowh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyowh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyowh_64_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32 += vmpyo($Vu32.w,$Vv32.h)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyowh_64_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32 += vmpyo($Vu32.w,$Vv32.h)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyowh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyowh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyowh_rnd : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyowh_rnd_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyowh_rnd_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyowh_rnd_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmpyowh($Vu32,$Vv32):<<1:rnd:sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyowh_rnd_sacc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat:shift", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyowh_rnd_sacc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:rnd:sat:shift", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyowh_rnd_sacc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:rnd:sat:shift", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyowh_rnd_sacc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:rnd:sat:shift", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyowh_sacc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:sat:shift", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyowh_sacc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32.w += vmpyo($Vu32.w,$Vv32.h):<<1:sat:shift", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyowh_sacc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:sat:shift", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyowh_sacc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32 += vmpyowh($Vu32,$Vv32):<<1:sat:shift", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vmpyub : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vdd32.uh = vmpy($Vu32.ub,$Rt32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyub_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vdd32.uh = vmpy($Vu32.ub,$Rt32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyub_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vxx32.uh += vmpy($Vu32.ub,$Rt32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyub_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vxx32.uh += vmpy($Vu32.ub,$Rt32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001100; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyub_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vxx32 += vmpyub($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyub_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vxx32 += vmpyub($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyub_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vdd32 = vmpyub($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyub_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vdd32 = vmpyub($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyubv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.uh = vmpy($Vu32.ub,$Vv32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyubv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.uh = vmpy($Vu32.ub,$Vv32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyubv_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32.uh += vmpy($Vu32.ub,$Vv32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyubv_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32.uh += vmpy($Vu32.ub,$Vv32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyubv_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32 += vmpyub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyubv_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32 += vmpyub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyubv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vmpyub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyubv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vmpyub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyuh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vdd32.uw = vmpy($Vu32.uh,$Rt32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyuh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vdd32.uw = vmpy($Vu32.uh,$Rt32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_11471622, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyuh_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vxx32.uw += vmpy($Vu32.uh,$Rt32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyuh_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vxx32.uw += vmpy($Vu32.uh,$Rt32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2153798, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyuh_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vxx32 += vmpyuh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyuh_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vxx32 += vmpyuh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyuh_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vdd32 = vmpyuh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyuh_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vdd32 = vmpyuh($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyuhv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.uw = vmpy($Vu32.uh,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyuhv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.uw = vmpy($Vu32.uh,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmpyuhv_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32.uw += vmpy($Vu32.uh,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyuhv_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32.uw += vmpy($Vu32.uh,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5972412, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyuhv_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vxx32 += vmpyuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyuhv_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vxx32 += vmpyuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vmpyuhv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vmpyuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmpyuhv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vmpyuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vmux : HInst< +(outs VectorRegs:$Vd32), +(ins VecPredRegs:$Qt4, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vmux($Qt4,$Vu32,$Vv32)", +CVI_VA, TypeCVI_VA>, Enc_1572239, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011110111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vmux_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VecPredRegs128B:$Qt4, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vmux($Qt4,$Vu32,$Vv32)", +CVI_VA, TypeCVI_VA>, Enc_1572239, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011110111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnavgh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vnavg($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnavgh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vnavg($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnavgh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vnavgh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnavgh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vnavgh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnavgub : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vnavg($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnavgub_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vnavg($Vu32.ub,$Vv32.ub)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnavgub_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vnavgub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnavgub_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vnavgub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnavgw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vnavg($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnavgw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vnavg($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnavgw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vnavgw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnavgw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vnavgw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnccombine : HInst< +(outs VecDblRegs:$Vdd32), +(ins PredRegs:$Ps4, VectorRegs:$Vu32, VectorRegs:$Vv32), +"if (!$Ps4) $Vdd32 = vcombine($Vu32,$Vv32)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_16145290, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011010010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnccombine_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins PredRegs:$Ps4, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"if (!$Ps4) $Vdd32 = vcombine($Vu32,$Vv32)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_16145290, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011010010; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vncmov : HInst< +(outs VectorRegs:$Vd32), +(ins PredRegs:$Ps4, VectorRegs:$Vu32), +"if (!$Ps4) $Vd32 = $Vu32", +CVI_VA, TypeCVI_VA>, Enc_12023037, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001101000100000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vncmov_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins PredRegs:$Ps4, VectorRegs128B:$Vu32), +"if (!$Ps4) $Vd32 = $Vu32", +CVI_VA, TypeCVI_VA>, Enc_12023037, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001101000100000; +let isPredicated = 1; +let isPredicatedFalse = 1; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnormamth : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.h = vnormamt($Vu32.h)", +CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnormamth_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.h = vnormamt($Vu32.h)", +CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnormamth_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vnormamth($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnormamth_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vnormamth($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnormamtw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.w = vnormamt($Vu32.w)", +CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnormamtw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.w = vnormamt($Vu32.w)", +CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnormamtw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vnormamtw($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnormamtw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vnormamtw($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vnot : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vnot($Vu32)", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vnot_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vnot($Vu32)", +CVI_VA, TypeCVI_VA>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vor : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vor($Vu32,$Vv32)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vor_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vor($Vu32,$Vv32)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackeb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vpacke($Vu32.h,$Vv32.h)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackeb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vpacke($Vu32.h,$Vv32.h)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackeb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vpackeb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackeb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vpackeb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackeh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vpacke($Vu32.w,$Vv32.w)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackeh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vpacke($Vu32.w,$Vv32.w)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackeh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vpackeh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackeh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vpackeh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackhb_sat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vpack($Vu32.h,$Vv32.h):sat", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackhb_sat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vpack($Vu32.h,$Vv32.h):sat", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackhb_sat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vpackhb($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackhb_sat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vpackhb($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackhub_sat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vpack($Vu32.h,$Vv32.h):sat", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackhub_sat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vpack($Vu32.h,$Vv32.h):sat", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackhub_sat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vpackhub($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackhub_sat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vpackhub($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackob : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vpacko($Vu32.h,$Vv32.h)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackob_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vpacko($Vu32.h,$Vv32.h)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackob_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vpackob($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackob_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vpackob($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackoh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vpacko($Vu32.w,$Vv32.w)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackoh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vpacko($Vu32.w,$Vv32.w)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackoh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vpackoh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackoh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vpackoh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackwh_sat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vpack($Vu32.w,$Vv32.w):sat", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackwh_sat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vpack($Vu32.w,$Vv32.w):sat", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackwh_sat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vpackwh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackwh_sat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vpackwh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackwuh_sat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vpack($Vu32.w,$Vv32.w):sat", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackwuh_sat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vpack($Vu32.w,$Vv32.w):sat", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpackwuh_sat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vpackwuh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpackwuh_sat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vpackwuh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpopcounth : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.h = vpopcount($Vu32.h)", +CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpopcounth_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.h = vpopcount($Vu32.h)", +CVI_VS, TypeCVI_VS>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vpopcounth_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vpopcounth($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vpopcounth_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vpopcounth($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrdelta : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vrdelta($Vu32,$Vv32)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrdelta_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vrdelta($Vu32,$Vv32)", +CVI_VP, TypeCVI_VP>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpybus : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpybus_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.w = vrmpy($Vu32.ub,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpybus_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vrmpy($Vu32.ub,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybus_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.w += vrmpy($Vu32.ub,$Rt32.b)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybus_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vrmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybus_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vrmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybus_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vrmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpybus_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vrmpybus($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpybusi : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32.w = vrmpy($Vuu32.ub,$Rt32.b,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_14172170, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpybusi_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32.w = vrmpy($Vuu32.ub,$Rt32.b,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_14172170, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b10; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpybusi_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32.w += vrmpy($Vuu32.ub,$Rt32.b,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13189194, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b10; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrmpybusi_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32.w += vrmpy($Vuu32.ub,$Rt32.b,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13189194, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b10; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrmpybusi_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrmpybusi_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32 += vrmpybus($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrmpybusi_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpybusi_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32 = vrmpybus($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpybusv : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vrmpy($Vu32.ub,$Vv32.b)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpybusv_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vrmpy($Vu32.ub,$Vv32.b)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpybusv_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32.w += vrmpy($Vu32.ub,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybusv_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32.w += vrmpy($Vu32.ub,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybusv_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32 += vrmpybus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybusv_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32 += vrmpybus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybusv_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vrmpybus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpybusv_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vrmpybus($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpybv : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vrmpy($Vu32.b,$Vv32.b)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpybv_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vrmpy($Vu32.b,$Vv32.b)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpybv_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32.w += vrmpy($Vu32.b,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybv_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32.w += vrmpy($Vu32.b,$Vv32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybv_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32 += vrmpyb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybv_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32 += vrmpyb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpybv_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vrmpyb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpybv_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vrmpyb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpyub : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32.uw = vrmpy($Vu32.ub,$Rt32.ub)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpyub_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32.uw = vrmpy($Vu32.ub,$Rt32.ub)", +CVI_VX, TypeCVI_VX>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpyub_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32.uw += vrmpy($Vu32.ub,$Rt32.ub)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpyub_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32.uw += vrmpy($Vu32.ub,$Rt32.ub)", +CVI_VX, TypeCVI_VX>, Enc_10058269, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpyub_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vx32 += vrmpyub($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpyub_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vx32 += vrmpyub($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpyub_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vrmpyub($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpyub_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vrmpyub($Vu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpyubi : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32.uw = vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_14172170, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpyubi_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32.uw = vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_14172170, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpyubi_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32.uw += vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13189194, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b11; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrmpyubi_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32.uw += vrmpy($Vuu32.ub,$Rt32.ub,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13189194, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b11; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrmpyubi_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrmpyubi_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32 += vrmpyub($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrmpyubi_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpyubi_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32 = vrmpyub($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpyubv : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uw = vrmpy($Vu32.ub,$Vv32.ub)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpyubv_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uw = vrmpy($Vu32.ub,$Vv32.ub)", +CVI_VX, TypeCVI_VX>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrmpyubv_acc : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32.uw += vrmpy($Vu32.ub,$Vv32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpyubv_acc_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32.uw += vrmpy($Vu32.ub,$Vv32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_2328527, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpyubv_acc_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VectorRegs:$Vx32in, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vx32 += vrmpyub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpyubv_acc_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vx32 += vrmpyub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vrmpyubv_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vrmpyub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrmpyubv_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vrmpyub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vror : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, IntRegs:$Rt32), +"$Vd32 = vror($Vu32,$Rt32)", +CVI_VP, TypeCVI_VP>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vror_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, IntRegs:$Rt32), +"$Vd32 = vror($Vu32,$Rt32)", +CVI_VP, TypeCVI_VP>, Enc_16214129, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vroundhb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vround($Vu32.h,$Vv32.h):sat", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vroundhb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vround($Vu32.h,$Vv32.h):sat", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vroundhb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vroundhb($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vroundhb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vroundhb($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vroundhub : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vround($Vu32.h,$Vv32.h):sat", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vroundhub_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vround($Vu32.h,$Vv32.h):sat", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vroundhub_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vroundhub($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vroundhub_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vroundhub($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrounduhub : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vround($Vu32.uh,$Vv32.uh):sat", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrounduhub_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vround($Vu32.uh,$Vv32.uh):sat", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrounduhub_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vrounduhub($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrounduhub_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vrounduhub($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrounduwuh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vround($Vu32.uw,$Vv32.uw):sat", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrounduwuh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vround($Vu32.uw,$Vv32.uw):sat", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111111; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrounduwuh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vrounduwuh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrounduwuh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vrounduwuh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vroundwh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vround($Vu32.w,$Vv32.w):sat", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vroundwh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vround($Vu32.w,$Vv32.w):sat", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vroundwh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vroundwh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vroundwh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vroundwh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vroundwuh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vround($Vu32.w,$Vv32.w):sat", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vroundwuh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vround($Vu32.w,$Vv32.w):sat", +CVI_VS, TypeCVI_VS>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vroundwuh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vroundwuh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vroundwuh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vroundwuh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrsadubi : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32.uw = vrsad($Vuu32.ub,$Rt32.ub,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_14172170, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrsadubi_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32.uw = vrsad($Vuu32.ub,$Rt32.ub,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_14172170, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b11; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vrsadubi_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32.uw += vrsad($Vuu32.ub,$Rt32.ub,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13189194, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b11; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrsadubi_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32.uw += vrsad($Vuu32.ub,$Rt32.ub,#$Ii)", +CVI_VX_DV_LONG, TypeCVI_VX_DV>, Enc_13189194, Requires<[HasV60T,UseHVX]> { +let Inst{7-6} = 0b11; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001010; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrsadubi_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrsadubi_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vxx32 += vrsadub($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vrsadubi_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vrsadubi_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii), +"$Vdd32 = vrsadub($Vuu32,$Rt32,#$Ii)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsathub : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vsat($Vu32.h,$Vv32.h)", +CVI_VINLANESAT, TypeCVI_VINLANESAT>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsathub_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vsat($Vu32.h,$Vv32.h)", +CVI_VINLANESAT, TypeCVI_VINLANESAT>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsathub_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsathub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsathub_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsathub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsatuwuh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vsat($Vu32.uw,$Vv32.uw)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsatuwuh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vsat($Vu32.uw,$Vv32.uw)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsatuwuh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsatuwuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsatuwuh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsatuwuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsatwh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vsat($Vu32.w,$Vv32.w)", +CVI_VINLANESAT, TypeCVI_VINLANESAT>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsatwh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vsat($Vu32.w,$Vv32.w)", +CVI_VINLANESAT, TypeCVI_VINLANESAT>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsatwh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsatwh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsatwh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsatwh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsb : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32.h = vsxt($Vu32.b)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsb_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32.h = vsxt($Vu32.b)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsb_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32 = vsxtb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsb_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32 = vsxtb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32.w = vsxt($Vu32.h)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32.w = vsxt($Vu32.h)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsh_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32 = vsxth($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsh_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32 = vsxth($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshufeh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vshuffe($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshufeh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vshuffe($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshufeh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vshuffeh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshufeh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vshuffeh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshuff : HInst< +(outs VectorRegs:$Vy32, VectorRegs:$Vx32), +(ins VectorRegs:$Vy32in, VectorRegs:$Vx32in, IntRegs:$Rt32), +"vshuff($Vy32,$Vx32,$Rt32)", +CVI_VP_VS_LONG_EARLY, TypeCVI_VP_VS>, Enc_11422009, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001111; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; +} +def V6_vshuff_128B : HInst< +(outs VectorRegs128B:$Vy32, VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vy32in, VectorRegs128B:$Vx32in, IntRegs:$Rt32), +"vshuff($Vy32,$Vx32,$Rt32)", +CVI_VP_VS_LONG_EARLY, TypeCVI_VP_VS>, Enc_11422009, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001111; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; +} +def V6_vshuffb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.b = vshuff($Vu32.b)", +CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshuffb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.b = vshuff($Vu32.b)", +CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshuffb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vshuffb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshuffb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vshuffb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshuffeb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vshuffe($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshuffeb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vshuffe($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshuffeb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vshuffeb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshuffeb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vshuffeb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshuffh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32.h = vshuff($Vu32.h)", +CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshuffh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32.h = vshuff($Vu32.h)", +CVI_VP, TypeCVI_VP>, Enc_900013, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshuffh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32), +"$Vd32 = vshuffh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshuffh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32), +"$Vd32 = vshuffh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshuffob : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vshuffo($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshuffob_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vshuffo($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshuffob_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vshuffob($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshuffob_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vshuffob($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshuffvdd : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8), +"$Vdd32 = vshuff($Vu32,$Vv32,$Rt8)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshuffvdd_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, IntRegsLow8:$Rt8), +"$Vdd32 = vshuff($Vu32,$Vv32,$Rt8)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_14767681, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{31-24} = 0b00011011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshufoeb : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.b = vshuffoe($Vu32.b,$Vv32.b)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshufoeb_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.b = vshuffoe($Vu32.b,$Vv32.b)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshufoeb_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vshuffoeb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshufoeb_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vshuffoeb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshufoeh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.h = vshuffoe($Vu32.h,$Vv32.h)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshufoeh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.h = vshuffoe($Vu32.h,$Vv32.h)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshufoeh_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vshuffoeh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshufoeh_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vshuffoeh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshufoh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vshuffo($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshufoh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vshuffo($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vshufoh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vshuffoh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vshufoh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vshuffoh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubb : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vsub($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubb_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vsub($Vu32.b,$Vv32.b)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubb_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsubb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubb_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsubb($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubb_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubb_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubb_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vsubb($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubb_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vsubb($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubbnq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4) $Vx32.b -= $Vu32.b", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubbnq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4) $Vx32.b -= $Vu32.b", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubbnq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4.b) $Vx32.b -= $Vu32.b", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubbnq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4.b) $Vx32.b -= $Vu32.b", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubbq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4) $Vx32.b -= $Vu32.b", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubbq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4) $Vx32.b -= $Vu32.b", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubbq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4.b) $Vx32.b -= $Vu32.b", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubbq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4.b) $Vx32.b -= $Vu32.b", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubbsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.b = vsub($Vu32.b,$Vv32.b):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubbsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.b = vsub($Vu32.b,$Vv32.b):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubbsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsubb($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubbsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsubb($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubbsat_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011110101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubbsat_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.b = vsub($Vuu32.b,$Vvv32.b):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011110101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubbsat_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vsubb($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubbsat_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vsubb($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubcarry : HInst< +(outs VectorRegs:$Vd32, VecPredRegs:$Qx4), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32, VecPredRegs:$Qx4in), +"$Vd32.w = vsub($Vu32.w,$Vv32.w,$Qx4):carry", +CVI_VA, TypeCVI_VA>, Enc_13691337, Requires<[HasV62T,UseHVX]> { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vsubcarry_128B : HInst< +(outs VectorRegs128B:$Vd32, VecPredRegs128B:$Qx4), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32, VecPredRegs128B:$Qx4in), +"$Vd32.w = vsub($Vu32.w,$Vv32.w,$Qx4):carry", +CVI_VA, TypeCVI_VA>, Enc_13691337, Requires<[HasV62T,UseHVX]> { +let Inst{7-7} = 0b1; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Qx4 = $Qx4in"; +} +def V6_vsubh : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vsub($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubh_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vsub($Vu32.h,$Vv32.h)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubh_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsubh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubh_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsubh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubh_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubh_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubh_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vsubh($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubh_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vsubh($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubhnq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4) $Vx32.h -= $Vu32.h", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubhnq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4) $Vx32.h -= $Vu32.h", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubhnq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4.h) $Vx32.h -= $Vu32.h", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubhnq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4.h) $Vx32.h -= $Vu32.h", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubhq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4) $Vx32.h -= $Vu32.h", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubhq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4) $Vx32.h -= $Vu32.h", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000001; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubhq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4.h) $Vx32.h -= $Vu32.h", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubhq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4.h) $Vx32.h -= $Vu32.h", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubhsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.h = vsub($Vu32.h,$Vv32.h):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubhsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.h = vsub($Vu32.h,$Vv32.h):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubhsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsubh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubhsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsubh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubhsat_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubhsat_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.h = vsub($Vuu32.h,$Vvv32.h):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubhsat_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vsubh($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubhsat_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vsubh($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubhw : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.w = vsub($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubhw_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.w = vsub($Vu32.h,$Vv32.h)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubhw_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vsubh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubhw_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vsubh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsububh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsububh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.h = vsub($Vu32.ub,$Vv32.ub)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsububh_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vsubub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsububh_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vsubub($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsububsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vsub($Vu32.ub,$Vv32.ub):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsububsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vsub($Vu32.ub,$Vv32.ub):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsububsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsubub($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsububsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsubub($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsububsat_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.ub = vsub($Vuu32.ub,$Vvv32.ub):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsububsat_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.ub = vsub($Vuu32.ub,$Vvv32.ub):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsububsat_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vsubub($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsububsat_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vsubub($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubububb_sat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.ub = vsub($Vu32.ub,$Vv32.b):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011110101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubububb_sat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.ub = vsub($Vu32.ub,$Vv32.b):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011110101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubuhsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uh = vsub($Vu32.uh,$Vv32.uh):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubuhsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uh = vsub($Vu32.uh,$Vv32.uh):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubuhsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsubuh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubuhsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsubuh($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubuhsat_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.uh = vsub($Vuu32.uh,$Vvv32.uh):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubuhsat_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.uh = vsub($Vuu32.uh,$Vvv32.uh):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubuhsat_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vsubuh($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubuhsat_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vsubuh($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubuhw : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubuhw_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32.w = vsub($Vu32.uh,$Vv32.uh)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_15290236, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b110; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubuhw_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vsubuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubuhw_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vsubuh($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubuwsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.uw = vsub($Vu32.uw,$Vv32.uw):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubuwsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.uw = vsub($Vu32.uw,$Vv32.uw):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011111110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubuwsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsubuw($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubuwsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsubuw($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubuwsat_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.uw = vsub($Vuu32.uw,$Vvv32.uw):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011110101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubuwsat_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.uw = vsub($Vuu32.uw,$Vvv32.uw):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV62T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011110101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubuwsat_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vsubuw($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubuwsat_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vsubuw($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV62T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubw : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vsub($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubw_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vsub($Vu32.w,$Vv32.w)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubw_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsubw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubw_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsubw($Vu32,$Vv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubw_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubw_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b101; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100100; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubw_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vsubw($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubw_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vsubw($Vuu32,$Vvv32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubwnq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4) $Vx32.w -= $Vu32.w", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubwnq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4) $Vx32.w -= $Vu32.w", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubwnq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if (!$Qv4.w) $Vx32.w -= $Vu32.w", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubwnq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if (!$Qv4.w) $Vx32.w -= $Vu32.w", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubwq : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4) $Vx32.w -= $Vu32.w", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubwq_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4) $Vx32.w -= $Vu32.w", +CVI_VA, TypeCVI_VA>, Enc_12535811, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubwq_alt : HInst< +(outs VectorRegs:$Vx32), +(ins VecPredRegs:$Qv4, VectorRegs:$Vx32in, VectorRegs:$Vu32), +"if ($Qv4.w) $Vx32.w -= $Vu32.w", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubwq_alt_128B : HInst< +(outs VectorRegs128B:$Vx32), +(ins VecPredRegs128B:$Qv4, VectorRegs128B:$Vx32in, VectorRegs128B:$Vu32), +"if ($Qv4.w) $Vx32.w -= $Vu32.w", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vx32 = $Vx32in"; +} +def V6_vsubwsat : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32.w = vsub($Vu32.w,$Vv32.w):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubwsat_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32.w = vsub($Vu32.w,$Vv32.w):sat", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100011; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubwsat_alt : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vsubw($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubwsat_alt_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vsubw($Vu32,$Vv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubwsat_dv : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubwsat_dv_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32.w = vsub($Vuu32.w,$Vvv32.w):sat", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_13211717, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vsubwsat_dv_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, VecDblRegs:$Vvv32), +"$Vdd32 = vsubw($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vsubwsat_dv_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, VecDblRegs128B:$Vvv32), +"$Vdd32 = vsubw($Vuu32,$Vvv32):sat", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vswap : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecPredRegs:$Qt4, VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vdd32 = vswap($Qt4,$Vu32,$Vv32)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_11424254, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011110101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vswap_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecPredRegs128B:$Qt4, VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vdd32 = vswap($Qt4,$Vu32,$Vv32)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_11424254, Requires<[HasV60T,UseHVX]> { +let Inst{7-7} = 0b0; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011110101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vtmpyb : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32.h = vtmpy($Vuu32.b,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vtmpyb_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32.h = vtmpy($Vuu32.b,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vtmpyb_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32.h += vtmpy($Vuu32.b,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpyb_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32.h += vtmpy($Vuu32.b,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpyb_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vtmpyb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpyb_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vtmpyb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpyb_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vtmpyb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vtmpyb_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vtmpyb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vtmpybus : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32.h = vtmpy($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vtmpybus_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32.h = vtmpy($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vtmpybus_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32.h += vtmpy($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpybus_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32.h += vtmpy($Vuu32.ub,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpybus_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vtmpybus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpybus_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vtmpybus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpybus_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vtmpybus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vtmpybus_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vtmpybus($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vtmpyhb : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32.w = vtmpy($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vtmpyhb_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32.w = vtmpy($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_5023792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011001101; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vtmpyhb_acc : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32.w += vtmpy($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpyhb_acc_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32.w += vtmpy($Vuu32.h,$Rt32.b)", +CVI_VX_DV, TypeCVI_VX_DV>, Enc_4327792, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b1; +let Inst{31-21} = 0b00011001000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpyhb_acc_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vtmpyhb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpyhb_acc_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vxx32 += vtmpyhb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vtmpyhb_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VecDblRegs:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vtmpyhb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vtmpyhb_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VecDblRegs128B:$Vuu32, IntRegs:$Rt32), +"$Vdd32 = vtmpyhb($Vuu32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vtran2x2_map : HInst< +(outs VectorRegs:$Vy32, VectorRegs:$Vx32), +(ins VectorRegs:$Vy32in, VectorRegs:$Vx32in, IntRegs:$Rt32), +"vtrans2x2($Vy32,$Vx32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; +} +def V6_vtran2x2_map_128B : HInst< +(outs VectorRegs128B:$Vy32, VectorRegs128B:$Vx32), +(ins VectorRegs128B:$Vy32in, VectorRegs128B:$Vx32in, IntRegs:$Rt32), +"vtrans2x2($Vy32,$Vx32,$Rt32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let hasNewValue2 = 1; +let opNewValue2 = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vy32 = $Vy32in, $Vx32 = $Vx32in"; +} +def V6_vunpackb : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32.h = vunpack($Vu32.b)", +CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vunpackb_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32.h = vunpack($Vu32.b)", +CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vunpackb_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32 = vunpackb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vunpackb_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32 = vunpackb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vunpackh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32.w = vunpack($Vu32.h)", +CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vunpackh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32.w = vunpack($Vu32.h)", +CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b011; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vunpackh_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32 = vunpackh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vunpackh_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32 = vunpackh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vunpackob : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32), +"$Vxx32.h |= vunpacko($Vu32.b)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_12669374, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vunpackob_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32), +"$Vxx32.h |= vunpacko($Vu32.b)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_12669374, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b1; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vunpackob_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32), +"$Vxx32 |= vunpackob($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vunpackob_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32), +"$Vxx32 |= vunpackob($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vunpackoh : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32), +"$Vxx32.w |= vunpacko($Vu32.h)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_12669374, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vunpackoh_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32), +"$Vxx32.w |= vunpacko($Vu32.h)", +CVI_VP_VS_LONG, TypeCVI_VP_VS>, Enc_12669374, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b1; +let Inst{31-16} = 0b0001111000000000; +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vunpackoh_alt : HInst< +(outs VecDblRegs:$Vxx32), +(ins VecDblRegs:$Vxx32in, VectorRegs:$Vu32), +"$Vxx32 |= vunpackoh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vunpackoh_alt_128B : HInst< +(outs VecDblRegs128B:$Vxx32), +(ins VecDblRegs128B:$Vxx32in, VectorRegs128B:$Vu32), +"$Vxx32 |= vunpackoh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isAccumulator = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +let Constraints = "$Vxx32 = $Vxx32in"; +} +def V6_vunpackub : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32.uh = vunpack($Vu32.ub)", +CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vunpackub_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32.uh = vunpack($Vu32.ub)", +CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vunpackub_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32 = vunpackub($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vunpackub_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32 = vunpackub($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vunpackuh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32.uw = vunpack($Vu32.uh)", +CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vunpackuh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32.uw = vunpack($Vu32.uh)", +CVI_VP_VS, TypeCVI_VP_VS>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vunpackuh_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32 = vunpackuh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vunpackuh_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32 = vunpackuh($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vwhist128 : HInst< +(outs), +(ins), +"vwhist128", +CVI_HIST, TypeCVI_HIST>, Enc_0, Requires<[HasV62T,UseHVX]> { +let Inst{13-0} = 0b10010010000000; +let Inst{31-16} = 0b0001111000000000; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vwhist128_128B : HInst< +(outs), +(ins), +"vwhist128", +CVI_HIST, TypeCVI_HIST>, Enc_0, Requires<[HasV62T,UseHVX]> { +let Inst{13-0} = 0b10010010000000; +let Inst{31-16} = 0b0001111000000000; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vwhist128m : HInst< +(outs), +(ins u1_0Imm:$Ii), +"vwhist128(#$Ii)", +CVI_HIST, TypeCVI_HIST>, Enc_1291652, Requires<[HasV62T,UseHVX]> { +let Inst{7-0} = 0b10000000; +let Inst{13-9} = 0b10011; +let Inst{31-16} = 0b0001111000000000; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vwhist128m_128B : HInst< +(outs), +(ins u1_0Imm:$Ii), +"vwhist128(#$Ii)", +CVI_HIST, TypeCVI_HIST>, Enc_1291652, Requires<[HasV62T,UseHVX]> { +let Inst{7-0} = 0b10000000; +let Inst{13-9} = 0b10011; +let Inst{31-16} = 0b0001111000000000; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vwhist128q : HInst< +(outs), +(ins VecPredRegs:$Qv4), +"vwhist128($Qv4)", +CVI_HIST, TypeCVI_HIST>, Enc_4109168, Requires<[HasV62T,UseHVX]> { +let Inst{13-0} = 0b10010010000000; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vwhist128q_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4), +"vwhist128($Qv4)", +CVI_HIST, TypeCVI_HIST>, Enc_4109168, Requires<[HasV62T,UseHVX]> { +let Inst{13-0} = 0b10010010000000; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vwhist128qm : HInst< +(outs), +(ins VecPredRegs:$Qv4, u1_0Imm:$Ii), +"vwhist128($Qv4,#$Ii)", +CVI_HIST, TypeCVI_HIST>, Enc_7978128, Requires<[HasV62T,UseHVX]> { +let Inst{7-0} = 0b10000000; +let Inst{13-9} = 0b10011; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vwhist128qm_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4, u1_0Imm:$Ii), +"vwhist128($Qv4,#$Ii)", +CVI_HIST, TypeCVI_HIST>, Enc_7978128, Requires<[HasV62T,UseHVX]> { +let Inst{7-0} = 0b10000000; +let Inst{13-9} = 0b10011; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vwhist256 : HInst< +(outs), +(ins), +"vwhist256", +CVI_HIST, TypeCVI_HIST>, Enc_0, Requires<[HasV62T,UseHVX]> { +let Inst{13-0} = 0b10001010000000; +let Inst{31-16} = 0b0001111000000000; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vwhist256_128B : HInst< +(outs), +(ins), +"vwhist256", +CVI_HIST, TypeCVI_HIST>, Enc_0, Requires<[HasV62T,UseHVX]> { +let Inst{13-0} = 0b10001010000000; +let Inst{31-16} = 0b0001111000000000; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vwhist256_sat : HInst< +(outs), +(ins), +"vwhist256:sat", +CVI_HIST, TypeCVI_HIST>, Enc_0, Requires<[HasV62T,UseHVX]> { +let Inst{13-0} = 0b10001110000000; +let Inst{31-16} = 0b0001111000000000; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vwhist256_sat_128B : HInst< +(outs), +(ins), +"vwhist256:sat", +CVI_HIST, TypeCVI_HIST>, Enc_0, Requires<[HasV62T,UseHVX]> { +let Inst{13-0} = 0b10001110000000; +let Inst{31-16} = 0b0001111000000000; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vwhist256q : HInst< +(outs), +(ins VecPredRegs:$Qv4), +"vwhist256($Qv4)", +CVI_HIST, TypeCVI_HIST>, Enc_4109168, Requires<[HasV62T,UseHVX]> { +let Inst{13-0} = 0b10001010000000; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vwhist256q_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4), +"vwhist256($Qv4)", +CVI_HIST, TypeCVI_HIST>, Enc_4109168, Requires<[HasV62T,UseHVX]> { +let Inst{13-0} = 0b10001010000000; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vwhist256q_sat : HInst< +(outs), +(ins VecPredRegs:$Qv4), +"vwhist256($Qv4):sat", +CVI_HIST, TypeCVI_HIST>, Enc_4109168, Requires<[HasV62T,UseHVX]> { +let Inst{13-0} = 0b10001110000000; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vwhist256q_sat_128B : HInst< +(outs), +(ins VecPredRegs128B:$Qv4), +"vwhist256($Qv4):sat", +CVI_HIST, TypeCVI_HIST>, Enc_4109168, Requires<[HasV62T,UseHVX]> { +let Inst{13-0} = 0b10001110000000; +let Inst{21-16} = 0b000010; +let Inst{31-24} = 0b00011110; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vxor : HInst< +(outs VectorRegs:$Vd32), +(ins VectorRegs:$Vu32, VectorRegs:$Vv32), +"$Vd32 = vxor($Vu32,$Vv32)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vxor_128B : HInst< +(outs VectorRegs128B:$Vd32), +(ins VectorRegs128B:$Vu32, VectorRegs128B:$Vv32), +"$Vd32 = vxor($Vu32,$Vv32)", +CVI_VA, TypeCVI_VA>, Enc_6223403, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b111; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b00011100001; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vzb : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32.uh = vzxt($Vu32.ub)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vzb_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32.uh = vzxt($Vu32.ub)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b001; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vzb_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32 = vzxtb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vzb_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32 = vzxtb($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vzh : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32.uw = vzxt($Vu32.uh)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vzh_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32.uw = vzxt($Vu32.uh)", +CVI_VA_DV, TypeCVI_VA_DV>, Enc_14631806, Requires<[HasV60T,UseHVX]> { +let Inst{7-5} = 0b010; +let Inst{13-13} = 0b0; +let Inst{31-16} = 0b0001111000000010; +let hasNewValue = 1; +let opNewValue = 0; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def V6_vzh_alt : HInst< +(outs VecDblRegs:$Vdd32), +(ins VectorRegs:$Vu32), +"$Vdd32 = vzxth($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +} +def V6_vzh_alt_128B : HInst< +(outs VecDblRegs128B:$Vdd32), +(ins VectorRegs128B:$Vu32), +"$Vdd32 = vzxth($Vu32)", +PSEUDO, TypeMAPPING>, Requires<[HasV60T,UseHVX]> { +let hasNewValue = 1; +let opNewValue = 0; +let isPseudo = 1; +let isCodeGenOnly = 1; +let DecoderNamespace = "EXT_mmvec"; +let isCodeGenOnly = 1; +} +def Y2_barrier : HInst< +(outs), +(ins), +"barrier", +ST_tc_3stall_SLOT0, TypeST>, Enc_0 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-16} = 0b1010100000000000; +let isSoloAX = 1; +let hasSideEffects = 1; +} +def Y2_break : HInst< +(outs), +(ins), +"brkpt", +CR_tc_3x_SLOT3, TypeCR>, Enc_0 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-16} = 0b0110110000100000; +let isSolo = 1; +} +def Y2_dccleana : HInst< +(outs), +(ins IntRegs:$Rs32), +"dccleana($Rs32)", +ST_tc_ld_SLOT0, TypeST>, Enc_11704059 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-21} = 0b10100000000; +let isSoloAin1 = 1; +} +def Y2_dccleaninva : HInst< +(outs), +(ins IntRegs:$Rs32), +"dccleaninva($Rs32)", +ST_tc_ld_SLOT0, TypeST>, Enc_11704059 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-21} = 0b10100000010; +let isSoloAin1 = 1; +} +def Y2_dcfetch : HInst< +(outs), +(ins IntRegs:$Rs32), +"dcfetch($Rs32)", +PSEUDO, TypeMAPPING> { +let hasSideEffects = 1; +let isPseudo = 1; +let isCodeGenOnly = 1; +} +def Y2_dcfetchbo : HInst< +(outs), +(ins IntRegs:$Rs32, u11_3Imm:$Ii), +"dcfetch($Rs32+#$Ii)", +LD_tc_ld_SLOT0, TypeLD>, Enc_4983213 { +let Inst{13-11} = 0b000; +let Inst{31-21} = 0b10010100000; +let addrMode = BaseImmOffset; +let hasSideEffects = 1; +} +def Y2_dcinva : HInst< +(outs), +(ins IntRegs:$Rs32), +"dcinva($Rs32)", +ST_tc_ld_SLOT0, TypeST>, Enc_11704059 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-21} = 0b10100000001; +let isSoloAin1 = 1; +} +def Y2_dczeroa : HInst< +(outs), +(ins IntRegs:$Rs32), +"dczeroa($Rs32)", +ST_tc_ld_SLOT0, TypeST>, Enc_11704059 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-21} = 0b10100000110; +let mayStore = 1; +let isSoloAin1 = 1; +} +def Y2_icinva : HInst< +(outs), +(ins IntRegs:$Rs32), +"icinva($Rs32)", +J_tc_2early_SLOT2, TypeJ>, Enc_11704059 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-21} = 0b01010110110; +let isSolo = 1; +} +def Y2_isync : HInst< +(outs), +(ins), +"isync", +J_tc_2early_SLOT2, TypeJ>, Enc_0 { +let Inst{13-0} = 0b00000000000010; +let Inst{31-16} = 0b0101011111000000; +let isSolo = 1; +} +def Y2_syncht : HInst< +(outs), +(ins), +"syncht", +ST_tc_ld_SLOT0, TypeST>, Enc_0 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-16} = 0b1010100001000000; +let isSolo = 1; +} +def Y4_l2fetch : HInst< +(outs), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"l2fetch($Rs32,$Rt32)", +ST_tc_3stall_SLOT0, TypeST>, Enc_14620934 { +let Inst{7-0} = 0b00000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10100110000; +let isSoloAX = 1; +let mayStore = 1; +let hasSideEffects = 1; +} +def Y4_trace : HInst< +(outs), +(ins IntRegs:$Rs32), +"trace($Rs32)", +CR_tc_2early_SLOT3, TypeCR>, Enc_11704059 { +let Inst{13-0} = 0b00000000000000; +let Inst{31-21} = 0b01100010010; +let isSoloAX = 1; +} +def Y5_l2fetch : HInst< +(outs), +(ins IntRegs:$Rs32, DoubleRegs:$Rtt32), +"l2fetch($Rs32,$Rtt32)", +ST_tc_3stall_SLOT0, TypeST>, Enc_8943121, Requires<[HasV5T]> { +let Inst{7-0} = 0b00000000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b10100110100; +let isSoloAX = 1; +let mayStore = 1; +let hasSideEffects = 1; +} +def dep_A2_addsat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rd32 = add($Rs32,$Rt32):sat:deprecated", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_14071773 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101100; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def dep_A2_subsat : HInst< +(outs IntRegs:$Rd32), +(ins IntRegs:$Rt32, IntRegs:$Rs32), +"$Rd32 = sub($Rt32,$Rs32):sat:deprecated", +ALU64_tc_2_SLOT23, TypeALU64>, Enc_8605375 { +let Inst{7-5} = 0b100; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010101100; +let hasNewValue = 1; +let opNewValue = 0; +let Defs = [USR_OVF]; +} +def dep_S2_packhl : HInst< +(outs DoubleRegs:$Rdd32), +(ins IntRegs:$Rs32, IntRegs:$Rt32), +"$Rdd32 = packhl($Rs32,$Rt32):deprecated", +ALU64_tc_1_SLOT23, TypeALU64>, Enc_1997594 { +let Inst{7-5} = 0b000; +let Inst{13-13} = 0b0; +let Inst{31-21} = 0b11010100000; +} diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonDepMappings.td b/contrib/llvm/lib/Target/Hexagon/HexagonDepMappings.td new file mode 100644 index 000000000000..77a56a9adf10 --- /dev/null +++ b/contrib/llvm/lib/Target/Hexagon/HexagonDepMappings.td @@ -0,0 +1,654 @@ +//===--- HexagonDepMappings.td --------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +def A2_negAlias : InstAlias<"$Rd32=neg($Rs32)", (A2_subri IntRegs:$Rd32, 0, IntRegs:$Rs32)>; +def A2_notAlias : InstAlias<"$Rd32=not($Rs32)", (A2_subri IntRegs:$Rd32, -1, IntRegs:$Rs32)>; +def A2_tfrfAlias : InstAlias<"if (!$Pu4) $Rd32=$Rs32", (A2_paddif IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>; +def A2_tfrfnewAlias : InstAlias<"if (!$Pu4.new) $Rd32=$Rs32", (A2_paddifnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>; +def A2_tfrtAlias : InstAlias<"if ($Pu4) $Rd32=$Rs32", (A2_paddit IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>; +def A2_tfrtnewAlias : InstAlias<"if ($Pu4.new) $Rd32=$Rs32", (A2_padditnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$Rs32, 0)>; +def A2_vaddb_mapAlias : InstAlias<"$Rdd32=vaddb($Rss32,$Rtt32)", (A2_vaddub DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32)>; +def A2_vsubb_mapAlias : InstAlias<"$Rdd32=vsubb($Rss32,$Rtt32)", (A2_vsubub DoubleRegs:$Rdd32, DoubleRegs:$Rss32, DoubleRegs:$Rtt32)>; +def A2_zxtbAlias : InstAlias<"$Rd32=zxtb($Rs32)", (A2_andir IntRegs:$Rd32, IntRegs:$Rs32, 255)>; +def C2_cmpltAlias : InstAlias<"$Pd4=cmp.lt($Rs32,$Rt32)", (C2_cmpgt PredRegs:$Pd4, IntRegs:$Rt32, IntRegs:$Rs32)>; +def C2_cmpltuAlias : InstAlias<"$Pd4=cmp.ltu($Rs32,$Rt32)", (C2_cmpgtu PredRegs:$Pd4, IntRegs:$Rt32, IntRegs:$Rs32)>; +def C2_pxfer_mapAlias : InstAlias<"$Pd4=$Ps4", (C2_or PredRegs:$Pd4, PredRegs:$Ps4, PredRegs:$Ps4)>; +def J2_jumpf_nopred_mapAlias : InstAlias<"if (!$Pu4) jump $Ii", (J2_jumpf PredRegs:$Pu4, b30_2Imm:$Ii)>; +def J2_jumprf_nopred_mapAlias : InstAlias<"if (!$Pu4) jumpr $Rs32", (J2_jumprf PredRegs:$Pu4, IntRegs:$Rs32)>; +def J2_jumprt_nopred_mapAlias : InstAlias<"if ($Pu4) jumpr $Rs32", (J2_jumprt PredRegs:$Pu4, IntRegs:$Rs32)>; +def J2_jumpt_nopred_mapAlias : InstAlias<"if ($Pu4) jump $Ii", (J2_jumpt PredRegs:$Pu4, b30_2Imm:$Ii)>; +def L2_loadalignb_zomapAlias : InstAlias<"$Ryy32=memb_fifo($Rs32)", (L2_loadalignb_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0)>; +def L2_loadalignh_zomapAlias : InstAlias<"$Ryy32=memh_fifo($Rs32)", (L2_loadalignh_io DoubleRegs:$Ryy32, IntRegs:$Rs32, 0)>; +def L2_loadbsw2_zomapAlias : InstAlias<"$Rd32=membh($Rs32)", (L2_loadbsw2_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_loadbsw4_zomapAlias : InstAlias<"$Rdd32=membh($Rs32)", (L2_loadbsw4_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>; +def L2_loadbzw2_zomapAlias : InstAlias<"$Rd32=memubh($Rs32)", (L2_loadbzw2_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_loadbzw4_zomapAlias : InstAlias<"$Rdd32=memubh($Rs32)", (L2_loadbzw4_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>; +def L2_loadrb_zomapAlias : InstAlias<"$Rd32=memb($Rs32)", (L2_loadrb_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_loadrd_zomapAlias : InstAlias<"$Rdd32=memd($Rs32)", (L2_loadrd_io DoubleRegs:$Rdd32, IntRegs:$Rs32, 0)>; +def L2_loadrh_zomapAlias : InstAlias<"$Rd32=memh($Rs32)", (L2_loadrh_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_loadri_zomapAlias : InstAlias<"$Rd32=memw($Rs32)", (L2_loadri_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_loadrub_zomapAlias : InstAlias<"$Rd32=memub($Rs32)", (L2_loadrub_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_loadruh_zomapAlias : InstAlias<"$Rd32=memuh($Rs32)", (L2_loadruh_io IntRegs:$Rd32, IntRegs:$Rs32, 0)>; +def L2_ploadrbf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memb($Rs32)", (L2_ploadrbf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrbfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memb($Rs32)", (L2_ploadrbfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrbt_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memb($Rs32)", (L2_ploadrbt_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrbtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memb($Rs32)", (L2_ploadrbtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrdf_zomapAlias : InstAlias<"if (!$Pt4) $Rdd32=memd($Rs32)", (L2_ploadrdf_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrdfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rdd32=memd($Rs32)", (L2_ploadrdfnew_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrdt_zomapAlias : InstAlias<"if ($Pt4) $Rdd32=memd($Rs32)", (L2_ploadrdt_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrdtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rdd32=memd($Rs32)", (L2_ploadrdtnew_io DoubleRegs:$Rdd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrhf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memh($Rs32)", (L2_ploadrhf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrhfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memh($Rs32)", (L2_ploadrhfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrht_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memh($Rs32)", (L2_ploadrht_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrhtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memh($Rs32)", (L2_ploadrhtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrif_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memw($Rs32)", (L2_ploadrif_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrifnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memw($Rs32)", (L2_ploadrifnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrit_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memw($Rs32)", (L2_ploadrit_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadritnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memw($Rs32)", (L2_ploadritnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrubf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memub($Rs32)", (L2_ploadrubf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrubfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memub($Rs32)", (L2_ploadrubfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrubt_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memub($Rs32)", (L2_ploadrubt_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadrubtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memub($Rs32)", (L2_ploadrubtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadruhf_zomapAlias : InstAlias<"if (!$Pt4) $Rd32=memuh($Rs32)", (L2_ploadruhf_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadruhfnew_zomapAlias : InstAlias<"if (!$Pt4.new) $Rd32=memuh($Rs32)", (L2_ploadruhfnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadruht_zomapAlias : InstAlias<"if ($Pt4) $Rd32=memuh($Rs32)", (L2_ploadruht_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L2_ploadruhtnew_zomapAlias : InstAlias<"if ($Pt4.new) $Rd32=memuh($Rs32)", (L2_ploadruhtnew_io IntRegs:$Rd32, PredRegs:$Pt4, IntRegs:$Rs32, 0)>; +def L4_add_memopb_zomapAlias : InstAlias<"memb($Rs32)+=$Rt32", (L4_add_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_add_memoph_zomapAlias : InstAlias<"memh($Rs32)+=$Rt32", (L4_add_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_add_memopw_zomapAlias : InstAlias<"memw($Rs32)+=$Rt32", (L4_add_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_and_memopb_zomapAlias : InstAlias<"memb($Rs32)&=$Rt32", (L4_and_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_and_memoph_zomapAlias : InstAlias<"memh($Rs32)&=$Rt32", (L4_and_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_and_memopw_zomapAlias : InstAlias<"memw($Rs32)&=$Rt32", (L4_and_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_iadd_memopb_zomapAlias : InstAlias<"memb($Rs32)+=#$II", (L4_iadd_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_iadd_memoph_zomapAlias : InstAlias<"memh($Rs32)+=#$II", (L4_iadd_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_iadd_memopw_zomapAlias : InstAlias<"memw($Rs32)+=#$II", (L4_iadd_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_iand_memopb_zomapAlias : InstAlias<"memb($Rs32)=clrbit(#$II)", (L4_iand_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_iand_memoph_zomapAlias : InstAlias<"memh($Rs32)=clrbit(#$II)", (L4_iand_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_iand_memopw_zomapAlias : InstAlias<"memw($Rs32)=clrbit(#$II)", (L4_iand_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_ior_memopb_zomapAlias : InstAlias<"memb($Rs32)=setbit(#$II)", (L4_ior_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_ior_memoph_zomapAlias : InstAlias<"memh($Rs32)=setbit(#$II)", (L4_ior_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_ior_memopw_zomapAlias : InstAlias<"memw($Rs32)=setbit(#$II)", (L4_ior_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_isub_memopb_zomapAlias : InstAlias<"memb($Rs32)-=#$II", (L4_isub_memopb_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_isub_memoph_zomapAlias : InstAlias<"memh($Rs32)-=#$II", (L4_isub_memoph_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_isub_memopw_zomapAlias : InstAlias<"memw($Rs32)-=#$II", (L4_isub_memopw_io IntRegs:$Rs32, 0, u5_0Imm:$II)>; +def L4_or_memopb_zomapAlias : InstAlias<"memb($Rs32)|=$Rt32", (L4_or_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_or_memoph_zomapAlias : InstAlias<"memh($Rs32)|=$Rt32", (L4_or_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_or_memopw_zomapAlias : InstAlias<"memw($Rs32)|=$Rt32", (L4_or_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_sub_memopb_zomapAlias : InstAlias<"memb($Rs32)-=$Rt32", (L4_sub_memopb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_sub_memoph_zomapAlias : InstAlias<"memh($Rs32)-=$Rt32", (L4_sub_memoph_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def L4_sub_memopw_zomapAlias : InstAlias<"memw($Rs32)-=$Rt32", (L4_sub_memopw_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def M2_mpyuiAlias : InstAlias<"$Rd32=mpyui($Rs32,$Rt32)", (M2_mpyi IntRegs:$Rd32, IntRegs:$Rs32, IntRegs:$Rt32)>; +def S2_pstorerbf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32)=$Rt32", (S2_pstorerbf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerbnewf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32)=$Nt8.new", (S2_pstorerbnewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_pstorerbnewt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32)=$Nt8.new", (S2_pstorerbnewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_pstorerbt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32)=$Rt32", (S2_pstorerbt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerdf_zomapAlias : InstAlias<"if (!$Pv4) memd($Rs32)=$Rtt32", (S2_pstorerdf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>; +def S2_pstorerdt_zomapAlias : InstAlias<"if ($Pv4) memd($Rs32)=$Rtt32", (S2_pstorerdt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>; +def S2_pstorerff_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32)=$Rt32.h", (S2_pstorerff_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerft_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32)=$Rt32.h", (S2_pstorerft_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerhf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32)=$Rt32", (S2_pstorerhf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerhnewf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32)=$Nt8.new", (S2_pstorerhnewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_pstorerhnewt_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32)=$Nt8.new", (S2_pstorerhnewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_pstorerht_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32)=$Rt32", (S2_pstorerht_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerif_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32)=$Rt32", (S2_pstorerif_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_pstorerinewf_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32)=$Nt8.new", (S2_pstorerinewf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_pstorerinewt_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32)=$Nt8.new", (S2_pstorerinewt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_pstorerit_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32)=$Rt32", (S2_pstorerit_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_storerb_zomapAlias : InstAlias<"memb($Rs32)=$Rt32", (S2_storerb_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_storerbnew_zomapAlias : InstAlias<"memb($Rs32)=$Nt8.new", (S2_storerbnew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_storerd_zomapAlias : InstAlias<"memd($Rs32)=$Rtt32", (S2_storerd_io IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>; +def S2_storerf_zomapAlias : InstAlias<"memh($Rs32)=$Rt32.h", (S2_storerf_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_storerh_zomapAlias : InstAlias<"memh($Rs32)=$Rt32", (S2_storerh_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_storerhnew_zomapAlias : InstAlias<"memh($Rs32)=$Nt8.new", (S2_storerhnew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_storeri_zomapAlias : InstAlias<"memw($Rs32)=$Rt32", (S2_storeri_io IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S2_storerinew_zomapAlias : InstAlias<"memw($Rs32)=$Nt8.new", (S2_storerinew_io IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S2_tableidxb_goodsyntaxAlias : InstAlias<"$Rx32=tableidxb($Rs32,#$Ii,#$II)", (S2_tableidxb IntRegs:$Rx32, IntRegs:$Rs32, u4_0Imm:$Ii, u5_0Imm:$II)>; +def S4_pstorerbfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32)=$Rt32", (S4_pstorerbfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerbnewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32)=$Nt8.new", (S4_pstorerbnewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S4_pstorerbnewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32)=$Nt8.new", (S4_pstorerbnewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S4_pstorerbtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32)=$Rt32", (S4_pstorerbtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerdfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memd($Rs32)=$Rtt32", (S4_pstorerdfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>; +def S4_pstorerdtnew_zomapAlias : InstAlias<"if ($Pv4.new) memd($Rs32)=$Rtt32", (S4_pstorerdtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, DoubleRegs:$Rtt32)>; +def S4_pstorerffnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32)=$Rt32.h", (S4_pstorerffnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerftnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32)=$Rt32.h", (S4_pstorerftnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerhfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32)=$Rt32", (S4_pstorerhfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerhnewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32)=$Nt8.new", (S4_pstorerhnewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S4_pstorerhnewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32)=$Nt8.new", (S4_pstorerhnewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S4_pstorerhtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32)=$Rt32", (S4_pstorerhtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerifnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32)=$Rt32", (S4_pstorerifnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_pstorerinewfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32)=$Nt8.new", (S4_pstorerinewfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S4_pstorerinewtnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32)=$Nt8.new", (S4_pstorerinewtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Nt8)>; +def S4_pstoreritnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32)=$Rt32", (S4_pstoreritnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, IntRegs:$Rt32)>; +def S4_storeirb_zomapAlias : InstAlias<"memb($Rs32)=#$II", (S4_storeirb_io IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirbf_zomapAlias : InstAlias<"if (!$Pv4) memb($Rs32)=#$II", (S4_storeirbf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirbfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memb($Rs32)=#$II", (S4_storeirbfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirbt_zomapAlias : InstAlias<"if ($Pv4) memb($Rs32)=#$II", (S4_storeirbt_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirbtnew_zomapAlias : InstAlias<"if ($Pv4.new) memb($Rs32)=#$II", (S4_storeirbtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirh_zomapAlias : InstAlias<"memh($Rs32)=#$II", (S4_storeirh_io IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirhf_zomapAlias : InstAlias<"if (!$Pv4) memh($Rs32)=#$II", (S4_storeirhf_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirhfnew_zomapAlias : InstAlias<"if (!$Pv4.new) memh($Rs32)=#$II", (S4_storeirhfnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirht_zomapAlias : InstAlias<"if ($Pv4) memh($Rs32)=#$II", (S4_storeirht_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirhtnew_zomapAlias : InstAlias<"if ($Pv4.new) memh($Rs32)=#$II", (S4_storeirhtnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeiri_zomapAlias : InstAlias<"memw($Rs32)=#$II", (S4_storeiri_io IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirif_zomapAlias : InstAlias<"if (!$Pv4) memw($Rs32)=#$II", (S4_storeirif_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirifnew_zomapAlias : InstAlias<"if (!$Pv4.new) memw($Rs32)=#$II", (S4_storeirifnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeirit_zomapAlias : InstAlias<"if ($Pv4) memw($Rs32)=#$II", (S4_storeirit_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def S4_storeiritnew_zomapAlias : InstAlias<"if ($Pv4.new) memw($Rs32)=#$II", (S4_storeiritnew_io PredRegs:$Pv4, IntRegs:$Rs32, 0, s32_0Imm:$II)>; +def V6_MAP_equbAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_128BAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_and_128BAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_ior_128BAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equb_xor_128BAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.ub,$Vv32.ub)", (V6_veqb_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equhAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_128BAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_and_128BAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_ior_128BAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equh_xor_128BAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uh,$Vv32.uh)", (V6_veqh_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equwAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_128BAlias : InstAlias<"$Qd4=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw VecPredRegs:$Qd4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_andAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_and_128BAlias : InstAlias<"$Qx4&=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_and VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_iorAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_ior_128BAlias : InstAlias<"$Qx4|=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_or VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_xorAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_MAP_equw_xor_128BAlias : InstAlias<"$Qx4^=vcmp.eq($Vu32.uw,$Vv32.uw)", (V6_veqw_xor VecPredRegs:$Qx4, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_extractw_altAlias : InstAlias<"$Rd32.w=vextract($Vu32,$Rs32)", (V6_extractw IntRegs:$Rd32, VectorRegs:$Vu32, IntRegs:$Rs32)>, Requires<[UseHVX]>; +def V6_extractw_alt_128BAlias : InstAlias<"$Rd32.w=vextract($Vu32,$Rs32)", (V6_extractw IntRegs:$Rd32, VectorRegs:$Vu32, IntRegs:$Rs32)>, Requires<[UseHVX]>; +def V6_ld0Alias : InstAlias<"$Vd32=vmem($Rt32)", (V6_vL32b_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ld0_128BAlias : InstAlias<"$Vd32=vmem($Rt32)", (V6_vL32b_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ldnt0Alias : InstAlias<"$Vd32=vmem($Rt32):nt", (V6_vL32b_nt_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ldnt0_128BAlias : InstAlias<"$Vd32=vmem($Rt32):nt", (V6_vL32b_nt_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ldu0Alias : InstAlias<"$Vd32=vmemu($Rt32)", (V6_vL32Ub_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_ldu0_128BAlias : InstAlias<"$Vd32=vmemu($Rt32)", (V6_vL32Ub_ai VectorRegs:$Vd32, IntRegs:$Rt32, 0)>, Requires<[UseHVX]>; +def V6_st0Alias : InstAlias<"vmem($Rt32)=$Vs32", (V6_vS32b_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_st0_128BAlias : InstAlias<"vmem($Rt32)=$Vs32", (V6_vS32b_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stn0Alias : InstAlias<"vmem($Rt32)=$Os8.new", (V6_vS32b_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>; +def V6_stn0_128BAlias : InstAlias<"vmem($Rt32)=$Os8.new", (V6_vS32b_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>; +def V6_stnnt0Alias : InstAlias<"vmem($Rt32):nt=$Os8.new", (V6_vS32b_nt_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>; +def V6_stnnt0_128BAlias : InstAlias<"vmem($Rt32):nt=$Os8.new", (V6_vS32b_nt_new_ai IntRegs:$Rt32, 0, VectorRegs:$Os8)>, Requires<[UseHVX]>; +def V6_stnp0Alias : InstAlias<"if (!$Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stnp0_128BAlias : InstAlias<"if (!$Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stnpnt0Alias : InstAlias<"if (!$Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stnpnt0_128BAlias : InstAlias<"if (!$Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stnq0Alias : InstAlias<"if (!$Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stnq0_128BAlias : InstAlias<"if (!$Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stnqnt0Alias : InstAlias<"if (!$Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stnqnt0_128BAlias : InstAlias<"if (!$Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_nqpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stnt0Alias : InstAlias<"vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stnt0_128BAlias : InstAlias<"vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stp0Alias : InstAlias<"if ($Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stp0_128BAlias : InstAlias<"if ($Pv4) vmem($Rt32)=$Vs32", (V6_vS32b_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stpnt0Alias : InstAlias<"if ($Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stpnt0_128BAlias : InstAlias<"if ($Pv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stq0Alias : InstAlias<"if ($Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stq0_128BAlias : InstAlias<"if ($Qv4) vmem($Rt32)=$Vs32", (V6_vS32b_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stqnt0Alias : InstAlias<"if ($Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stqnt0_128BAlias : InstAlias<"if ($Qv4) vmem($Rt32):nt=$Vs32", (V6_vS32b_nt_qpred_ai VecPredRegs:$Qv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stu0Alias : InstAlias<"vmemu($Rt32)=$Vs32", (V6_vS32Ub_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stu0_128BAlias : InstAlias<"vmemu($Rt32)=$Vs32", (V6_vS32Ub_ai IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stunp0Alias : InstAlias<"if (!$Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stunp0_128BAlias : InstAlias<"if (!$Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_npred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stup0Alias : InstAlias<"if ($Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_stup0_128BAlias : InstAlias<"if ($Pv4) vmemu($Rt32)=$Vs32", (V6_vS32Ub_pred_ai PredRegs:$Pv4, IntRegs:$Rt32, 0, VectorRegs:$Vs32)>, Requires<[UseHVX]>; +def V6_vabsdiffh_altAlias : InstAlias<"$Vd32=vabsdiffh($Vu32,$Vv32)", (V6_vabsdiffh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffh_alt_128BAlias : InstAlias<"$Vd32=vabsdiffh($Vu32,$Vv32)", (V6_vabsdiffh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffub_altAlias : InstAlias<"$Vd32=vabsdiffub($Vu32,$Vv32)", (V6_vabsdiffub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffub_alt_128BAlias : InstAlias<"$Vd32=vabsdiffub($Vu32,$Vv32)", (V6_vabsdiffub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffuh_altAlias : InstAlias<"$Vd32=vabsdiffuh($Vu32,$Vv32)", (V6_vabsdiffuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffuh_alt_128BAlias : InstAlias<"$Vd32=vabsdiffuh($Vu32,$Vv32)", (V6_vabsdiffuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffw_altAlias : InstAlias<"$Vd32=vabsdiffw($Vu32,$Vv32)", (V6_vabsdiffw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsdiffw_alt_128BAlias : InstAlias<"$Vd32=vabsdiffw($Vu32,$Vv32)", (V6_vabsdiffw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vabsh_altAlias : InstAlias<"$Vd32=vabsh($Vu32)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsh_alt_128BAlias : InstAlias<"$Vd32=vabsh($Vu32)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsh_sat_altAlias : InstAlias<"$Vd32=vabsh($Vu32):sat", (V6_vabsh_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsh_sat_alt_128BAlias : InstAlias<"$Vd32=vabsh($Vu32):sat", (V6_vabsh_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsuh_altAlias : InstAlias<"$Vd32.uh=vabs($Vu32.h)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsuh_alt_128BAlias : InstAlias<"$Vd32.uh=vabs($Vu32.h)", (V6_vabsh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsuw_altAlias : InstAlias<"$Vd32.uw=vabs($Vu32.w)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsuw_alt_128BAlias : InstAlias<"$Vd32.uw=vabs($Vu32.w)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsw_altAlias : InstAlias<"$Vd32=vabsw($Vu32)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsw_alt_128BAlias : InstAlias<"$Vd32=vabsw($Vu32)", (V6_vabsw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsw_sat_altAlias : InstAlias<"$Vd32=vabsw($Vu32):sat", (V6_vabsw_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vabsw_sat_alt_128BAlias : InstAlias<"$Vd32=vabsw($Vu32):sat", (V6_vabsw_sat VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddb_altAlias : InstAlias<"$Vd32=vaddb($Vu32,$Vv32)", (V6_vaddb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddb_alt_128BAlias : InstAlias<"$Vd32=vaddb($Vu32,$Vv32)", (V6_vaddb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddb_dv_altAlias : InstAlias<"$Vdd32=vaddb($Vuu32,$Vvv32)", (V6_vaddb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddb_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddb($Vuu32,$Vvv32)", (V6_vaddb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddbnq_alt_128BAlias : InstAlias<"if (!$Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddbq_alt_128BAlias : InstAlias<"if ($Qv4.b) $Vx32.b+=$Vu32.b", (V6_vaddbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddh_altAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32)", (V6_vaddh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddh_alt_128BAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32)", (V6_vaddh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddh_dv_altAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32)", (V6_vaddh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddh_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32)", (V6_vaddh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddhnq_alt_128BAlias : InstAlias<"if (!$Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddhq_alt_128BAlias : InstAlias<"if ($Qv4.h) $Vx32.h+=$Vu32.h", (V6_vaddhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddhsat_altAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32):sat", (V6_vaddhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddhsat_alt_128BAlias : InstAlias<"$Vd32=vaddh($Vu32,$Vv32):sat", (V6_vaddhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddhsat_dv_altAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32):sat", (V6_vaddhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddh($Vuu32,$Vvv32):sat", (V6_vaddhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddhw_altAlias : InstAlias<"$Vdd32=vaddh($Vu32,$Vv32)", (V6_vaddhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddhw_alt_128BAlias : InstAlias<"$Vdd32=vaddh($Vu32,$Vv32)", (V6_vaddhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddubh_altAlias : InstAlias<"$Vdd32=vaddub($Vu32,$Vv32)", (V6_vaddubh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddubh_alt_128BAlias : InstAlias<"$Vdd32=vaddub($Vu32,$Vv32)", (V6_vaddubh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddubsat_altAlias : InstAlias<"$Vd32=vaddub($Vu32,$Vv32):sat", (V6_vaddubsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddubsat_alt_128BAlias : InstAlias<"$Vd32=vaddub($Vu32,$Vv32):sat", (V6_vaddubsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddubsat_dv_altAlias : InstAlias<"$Vdd32=vaddub($Vuu32,$Vvv32):sat", (V6_vaddubsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddubsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddub($Vuu32,$Vvv32):sat", (V6_vaddubsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vadduhsat_altAlias : InstAlias<"$Vd32=vadduh($Vu32,$Vv32):sat", (V6_vadduhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vadduhsat_alt_128BAlias : InstAlias<"$Vd32=vadduh($Vu32,$Vv32):sat", (V6_vadduhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vadduhsat_dv_altAlias : InstAlias<"$Vdd32=vadduh($Vuu32,$Vvv32):sat", (V6_vadduhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vadduhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vadduh($Vuu32,$Vvv32):sat", (V6_vadduhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vadduhw_altAlias : InstAlias<"$Vdd32=vadduh($Vu32,$Vv32)", (V6_vadduhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vadduhw_alt_128BAlias : InstAlias<"$Vdd32=vadduh($Vu32,$Vv32)", (V6_vadduhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddw_altAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32)", (V6_vaddw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddw_alt_128BAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32)", (V6_vaddw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddw_dv_altAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32)", (V6_vaddw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddw_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32)", (V6_vaddw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddwnq_alt_128BAlias : InstAlias<"if (!$Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddwq_alt_128BAlias : InstAlias<"if ($Qv4.w) $Vx32.w+=$Vu32.w", (V6_vaddwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vaddwsat_altAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32):sat", (V6_vaddwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddwsat_alt_128BAlias : InstAlias<"$Vd32=vaddw($Vu32,$Vv32):sat", (V6_vaddwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaddwsat_dv_altAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32):sat", (V6_vaddwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vaddwsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vaddw($Vuu32,$Vvv32):sat", (V6_vaddwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vandqrt_acc_altAlias : InstAlias<"$Vx32.ub|=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt_acc VectorRegs:$Vx32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandqrt_acc_alt_128BAlias : InstAlias<"$Vx32.ub|=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt_acc VectorRegs:$Vx32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandqrt_altAlias : InstAlias<"$Vd32.ub=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt VectorRegs:$Vd32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandqrt_alt_128BAlias : InstAlias<"$Vd32.ub=vand($Qu4.ub,$Rt32.ub)", (V6_vandqrt VectorRegs:$Vd32, VecPredRegs:$Qu4, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandvrt_acc_altAlias : InstAlias<"$Qx4.ub|=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt_acc VecPredRegs:$Qx4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandvrt_acc_alt_128BAlias : InstAlias<"$Qx4.ub|=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt_acc VecPredRegs:$Qx4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandvrt_altAlias : InstAlias<"$Qd4.ub=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt VecPredRegs:$Qd4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vandvrt_alt_128BAlias : InstAlias<"$Qd4.ub=vand($Vu32.ub,$Rt32.ub)", (V6_vandvrt VecPredRegs:$Qd4, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslh_altAlias : InstAlias<"$Vd32=vaslh($Vu32,$Rt32)", (V6_vaslh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslh_alt_128BAlias : InstAlias<"$Vd32=vaslh($Vu32,$Rt32)", (V6_vaslh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslhv_altAlias : InstAlias<"$Vd32=vaslh($Vu32,$Vv32)", (V6_vaslhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaslhv_alt_128BAlias : InstAlias<"$Vd32=vaslh($Vu32,$Vv32)", (V6_vaslhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaslw_acc_altAlias : InstAlias<"$Vx32+=vaslw($Vu32,$Rt32)", (V6_vaslw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslw_acc_alt_128BAlias : InstAlias<"$Vx32+=vaslw($Vu32,$Rt32)", (V6_vaslw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslw_altAlias : InstAlias<"$Vd32=vaslw($Vu32,$Rt32)", (V6_vaslw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslw_alt_128BAlias : InstAlias<"$Vd32=vaslw($Vu32,$Rt32)", (V6_vaslw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vaslwv_altAlias : InstAlias<"$Vd32=vaslw($Vu32,$Vv32)", (V6_vaslwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vaslwv_alt_128BAlias : InstAlias<"$Vd32=vaslw($Vu32,$Vv32)", (V6_vaslwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vasrh_altAlias : InstAlias<"$Vd32=vasrh($Vu32,$Rt32)", (V6_vasrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrh_alt_128BAlias : InstAlias<"$Vd32=vasrh($Vu32,$Rt32)", (V6_vasrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrhbrndsat_altAlias : InstAlias<"$Vd32=vasrhb($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhbrndsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrhubrndsat_altAlias : InstAlias<"$Vd32=vasrhub($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrhubrndsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrhubsat_altAlias : InstAlias<"$Vd32=vasrhub($Vu32,$Vv32,$Rt8):sat", (V6_vasrhubsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrhv_altAlias : InstAlias<"$Vd32=vasrh($Vu32,$Vv32)", (V6_vasrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vasrhv_alt_128BAlias : InstAlias<"$Vd32=vasrh($Vu32,$Vv32)", (V6_vasrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vasrw_acc_altAlias : InstAlias<"$Vx32+=vasrw($Vu32,$Rt32)", (V6_vasrw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrw_acc_alt_128BAlias : InstAlias<"$Vx32+=vasrw($Vu32,$Rt32)", (V6_vasrw_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrw_altAlias : InstAlias<"$Vd32=vasrw($Vu32,$Rt32)", (V6_vasrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrw_alt_128BAlias : InstAlias<"$Vd32=vasrw($Vu32,$Rt32)", (V6_vasrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vasrwh_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8)", (V6_vasrwhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrwhrndsat_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8):rnd:sat", (V6_vasrwhrndsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrwhsat_altAlias : InstAlias<"$Vd32=vasrwh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrwuhsat_altAlias : InstAlias<"$Vd32=vasrwuh($Vu32,$Vv32,$Rt8):sat", (V6_vasrwuhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32, IntRegsLow8:$Rt8)>; +def V6_vasrwv_altAlias : InstAlias<"$Vd32=vasrw($Vu32,$Vv32)", (V6_vasrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vasrwv_alt_128BAlias : InstAlias<"$Vd32=vasrw($Vu32,$Vv32)", (V6_vasrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgh_altAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32)", (V6_vavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgh_alt_128BAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32)", (V6_vavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavghrnd_altAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32):rnd", (V6_vavghrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavghrnd_alt_128BAlias : InstAlias<"$Vd32=vavgh($Vu32,$Vv32):rnd", (V6_vavghrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgub_altAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32)", (V6_vavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgub_alt_128BAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32)", (V6_vavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgubrnd_altAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32):rnd", (V6_vavgubrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgubrnd_alt_128BAlias : InstAlias<"$Vd32=vavgub($Vu32,$Vv32):rnd", (V6_vavgubrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavguh_altAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32)", (V6_vavguh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavguh_alt_128BAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32)", (V6_vavguh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavguhrnd_altAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32):rnd", (V6_vavguhrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavguhrnd_alt_128BAlias : InstAlias<"$Vd32=vavguh($Vu32,$Vv32):rnd", (V6_vavguhrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgw_altAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32)", (V6_vavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgw_alt_128BAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32)", (V6_vavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgwrnd_altAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32):rnd", (V6_vavgwrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vavgwrnd_alt_128BAlias : InstAlias<"$Vd32=vavgw($Vu32,$Vv32):rnd", (V6_vavgwrnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vcl0h_altAlias : InstAlias<"$Vd32=vcl0h($Vu32)", (V6_vcl0h VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vcl0h_alt_128BAlias : InstAlias<"$Vd32=vcl0h($Vu32)", (V6_vcl0h VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vcl0w_altAlias : InstAlias<"$Vd32=vcl0w($Vu32)", (V6_vcl0w VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vcl0w_alt_128BAlias : InstAlias<"$Vd32=vcl0w($Vu32)", (V6_vcl0w VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vd0Alias : InstAlias<"$Vd32=#0", (V6_vxor VectorRegs:$Vd32, VectorRegs:$Vd32, VectorRegs:$Vd32)>, Requires<[UseHVX]>; +def V6_vd0_128BAlias : InstAlias<"$Vd32=#0", (V6_vxor VectorRegs:$Vd32, VectorRegs:$Vd32, VectorRegs:$Vd32)>, Requires<[UseHVX]>; +def V6_vdd0Alias : InstAlias<"$Vdd32=#0", (V6_vsubw_dv VecDblRegs:$Vdd32, W15, W15)>, Requires<[UseHVX]>; +def V6_vdd0_128BAlias : InstAlias<"$Vdd32=#0", (V6_vsubw_dv VecDblRegs:$Vdd32, W15, W15)>, Requires<[UseHVX]>; +def V6_vdealb4w_altAlias : InstAlias<"$Vd32=vdealb4w($Vu32,$Vv32)", (V6_vdealb4w VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vdealb4w_alt_128BAlias : InstAlias<"$Vd32=vdealb4w($Vu32,$Vv32)", (V6_vdealb4w VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vdealb_altAlias : InstAlias<"$Vd32=vdealb($Vu32)", (V6_vdealb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vdealb_alt_128BAlias : InstAlias<"$Vd32=vdealb($Vu32)", (V6_vdealb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vdealh_altAlias : InstAlias<"$Vd32=vdealh($Vu32)", (V6_vdealh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vdealh_alt_128BAlias : InstAlias<"$Vd32=vdealh($Vu32)", (V6_vdealh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vdmpybus_acc_altAlias : InstAlias<"$Vx32+=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_altAlias : InstAlias<"$Vd32=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_alt_128BAlias : InstAlias<"$Vd32=vdmpybus($Vu32,$Rt32)", (V6_vdmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_dv_acc_altAlias : InstAlias<"$Vxx32+=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_dv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_dv_altAlias : InstAlias<"$Vdd32=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpybus_dv_alt_128BAlias : InstAlias<"$Vdd32=vdmpybus($Vuu32,$Rt32)", (V6_vdmpybus_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_acc_altAlias : InstAlias<"$Vx32+=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_altAlias : InstAlias<"$Vd32=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_alt_128BAlias : InstAlias<"$Vd32=vdmpyhb($Vu32,$Rt32)", (V6_vdmpyhb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_dv_acc_altAlias : InstAlias<"$Vxx32+=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_dv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_dv_altAlias : InstAlias<"$Vdd32=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhb_dv_alt_128BAlias : InstAlias<"$Vdd32=vdmpyhb($Vuu32,$Rt32)", (V6_vdmpyhb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhisat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhisat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhisat_altAlias : InstAlias<"$Vd32=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhisat_alt_128BAlias : InstAlias<"$Vd32=vdmpyh($Vuu32,$Rt32):sat", (V6_vdmpyhisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsat_altAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsat_alt_128BAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Rt32):sat", (V6_vdmpyhsat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsuisat_acc_altAlias : InstAlias<"$Vx32+=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsuisat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat_acc VectorRegs:$Vx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsuisat_altAlias : InstAlias<"$Vd32=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsuisat_alt_128BAlias : InstAlias<"$Vd32=vdmpyhsu($Vuu32,$Rt32,#1):sat", (V6_vdmpyhsuisat VectorRegs:$Vd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsusat_acc_altAlias : InstAlias<"$Vx32+=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsusat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsusat_altAlias : InstAlias<"$Vd32=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhsusat_alt_128BAlias : InstAlias<"$Vd32=vdmpyhsu($Vu32,$Rt32):sat", (V6_vdmpyhsusat VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdmpyhvsat_acc_altAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vdmpyhvsat_acc_alt_128BAlias : InstAlias<"$Vx32+=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vdmpyhvsat_altAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vdmpyhvsat_alt_128BAlias : InstAlias<"$Vd32=vdmpyh($Vu32,$Vv32):sat", (V6_vdmpyhvsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vdsaduh_acc_altAlias : InstAlias<"$Vxx32+=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdsaduh_acc_alt_128BAlias : InstAlias<"$Vxx32+=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdsaduh_altAlias : InstAlias<"$Vdd32=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vdsaduh_alt_128BAlias : InstAlias<"$Vdd32=vdsaduh($Vuu32,$Rt32)", (V6_vdsaduh VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vlsrh_altAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Rt32)", (V6_vlsrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vlsrh_alt_128BAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Rt32)", (V6_vlsrh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vlsrhv_altAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Vv32)", (V6_vlsrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vlsrhv_alt_128BAlias : InstAlias<"$Vd32=vlsrh($Vu32,$Vv32)", (V6_vlsrhv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vlsrw_altAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Rt32)", (V6_vlsrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vlsrw_alt_128BAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Rt32)", (V6_vlsrw VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vlsrwv_altAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Vv32)", (V6_vlsrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vlsrwv_alt_128BAlias : InstAlias<"$Vd32=vlsrw($Vu32,$Vv32)", (V6_vlsrwv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxh_altAlias : InstAlias<"$Vd32=vmaxh($Vu32,$Vv32)", (V6_vmaxh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxh_alt_128BAlias : InstAlias<"$Vd32=vmaxh($Vu32,$Vv32)", (V6_vmaxh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxub_altAlias : InstAlias<"$Vd32=vmaxub($Vu32,$Vv32)", (V6_vmaxub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxub_alt_128BAlias : InstAlias<"$Vd32=vmaxub($Vu32,$Vv32)", (V6_vmaxub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxuh_altAlias : InstAlias<"$Vd32=vmaxuh($Vu32,$Vv32)", (V6_vmaxuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxuh_alt_128BAlias : InstAlias<"$Vd32=vmaxuh($Vu32,$Vv32)", (V6_vmaxuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxw_altAlias : InstAlias<"$Vd32=vmaxw($Vu32,$Vv32)", (V6_vmaxw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmaxw_alt_128BAlias : InstAlias<"$Vd32=vmaxw($Vu32,$Vv32)", (V6_vmaxw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vminh_altAlias : InstAlias<"$Vd32=vminh($Vu32,$Vv32)", (V6_vminh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vminh_alt_128BAlias : InstAlias<"$Vd32=vminh($Vu32,$Vv32)", (V6_vminh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vminub_altAlias : InstAlias<"$Vd32=vminub($Vu32,$Vv32)", (V6_vminub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vminub_alt_128BAlias : InstAlias<"$Vd32=vminub($Vu32,$Vv32)", (V6_vminub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vminuh_altAlias : InstAlias<"$Vd32=vminuh($Vu32,$Vv32)", (V6_vminuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vminuh_alt_128BAlias : InstAlias<"$Vd32=vminuh($Vu32,$Vv32)", (V6_vminuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vminw_altAlias : InstAlias<"$Vd32=vminw($Vu32,$Vv32)", (V6_vminw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vminw_alt_128BAlias : InstAlias<"$Vd32=vminw($Vu32,$Vv32)", (V6_vminw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpabus_acc_altAlias : InstAlias<"$Vxx32+=vmpabus($Vuu32,$Rt32)", (V6_vmpabus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpabus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpabus($Vuu32,$Rt32)", (V6_vmpabus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpabus_altAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Rt32)", (V6_vmpabus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpabus_alt_128BAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Rt32)", (V6_vmpabus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpabusv_altAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Vvv32)", (V6_vmpabusv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vmpabusv_alt_128BAlias : InstAlias<"$Vdd32=vmpabus($Vuu32,$Vvv32)", (V6_vmpabusv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vmpabuuv_altAlias : InstAlias<"$Vdd32=vmpabuu($Vuu32,$Vvv32)", (V6_vmpabuuv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vmpabuuv_alt_128BAlias : InstAlias<"$Vdd32=vmpabuu($Vuu32,$Vvv32)", (V6_vmpabuuv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vmpahb_acc_altAlias : InstAlias<"$Vxx32+=vmpahb($Vuu32,$Rt32)", (V6_vmpahb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpahb_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpahb($Vuu32,$Rt32)", (V6_vmpahb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpahb_altAlias : InstAlias<"$Vdd32=vmpahb($Vuu32,$Rt32)", (V6_vmpahb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpahb_alt_128BAlias : InstAlias<"$Vdd32=vmpahb($Vuu32,$Rt32)", (V6_vmpahb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpybus_acc_altAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Rt32)", (V6_vmpybus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpybus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Rt32)", (V6_vmpybus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpybus_altAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Rt32)", (V6_vmpybus VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpybus_alt_128BAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Rt32)", (V6_vmpybus VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpybusv_acc_altAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Vv32)", (V6_vmpybusv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybusv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpybus($Vu32,$Vv32)", (V6_vmpybusv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybusv_altAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Vv32)", (V6_vmpybusv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybusv_alt_128BAlias : InstAlias<"$Vdd32=vmpybus($Vu32,$Vv32)", (V6_vmpybusv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybv_acc_altAlias : InstAlias<"$Vxx32+=vmpyb($Vu32,$Vv32)", (V6_vmpybv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyb($Vu32,$Vv32)", (V6_vmpybv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybv_altAlias : InstAlias<"$Vdd32=vmpyb($Vu32,$Vv32)", (V6_vmpybv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpybv_alt_128BAlias : InstAlias<"$Vdd32=vmpyb($Vu32,$Vv32)", (V6_vmpybv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyewuh_altAlias : InstAlias<"$Vd32=vmpyewuh($Vu32,$Vv32)", (V6_vmpyewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyewuh_alt_128BAlias : InstAlias<"$Vd32=vmpyewuh($Vu32,$Vv32)", (V6_vmpyewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyh_altAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Rt32)", (V6_vmpyh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyh_alt_128BAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Rt32)", (V6_vmpyh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhsat_acc_altAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Rt32):sat", (V6_vmpyhsat_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhsat_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Rt32):sat", (V6_vmpyhsat_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhsrs_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:rnd:sat", (V6_vmpyhsrs VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhsrs_alt_128BAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:rnd:sat", (V6_vmpyhsrs VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhss_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:sat", (V6_vmpyhss VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhss_alt_128BAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Rt32):<<1:sat", (V6_vmpyhss VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyhus_acc_altAlias : InstAlias<"$Vxx32+=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhus_altAlias : InstAlias<"$Vdd32=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhus_alt_128BAlias : InstAlias<"$Vdd32=vmpyhus($Vu32,$Vv32)", (V6_vmpyhus VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhv_acc_altAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Vv32)", (V6_vmpyhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyh($Vu32,$Vv32)", (V6_vmpyhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhv_altAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Vv32)", (V6_vmpyhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhv_alt_128BAlias : InstAlias<"$Vdd32=vmpyh($Vu32,$Vv32)", (V6_vmpyhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhvsrs_altAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyhvsrs VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyhvsrs_alt_128BAlias : InstAlias<"$Vd32=vmpyh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyhvsrs VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewh_acc_altAlias : InstAlias<"$Vx32+=vmpyiewh($Vu32,$Vv32)", (V6_vmpyiewh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewh_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiewh($Vu32,$Vv32)", (V6_vmpyiewh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewuh_acc_altAlias : InstAlias<"$Vx32+=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewuh_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewuh_altAlias : InstAlias<"$Vd32=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiewuh_alt_128BAlias : InstAlias<"$Vd32=vmpyiewuh($Vu32,$Vv32)", (V6_vmpyiewuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyih_acc_altAlias : InstAlias<"$Vx32+=vmpyih($Vu32,$Vv32)", (V6_vmpyih_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyih_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyih($Vu32,$Vv32)", (V6_vmpyih_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyih_altAlias : InstAlias<"$Vd32=vmpyih($Vu32,$Vv32)", (V6_vmpyih VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyih_alt_128BAlias : InstAlias<"$Vd32=vmpyih($Vu32,$Vv32)", (V6_vmpyih VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyihb_acc_altAlias : InstAlias<"$Vx32+=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyihb_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyihb_altAlias : InstAlias<"$Vd32=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyihb_alt_128BAlias : InstAlias<"$Vd32=vmpyihb($Vu32,$Rt32)", (V6_vmpyihb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiowh_altAlias : InstAlias<"$Vd32=vmpyiowh($Vu32,$Vv32)", (V6_vmpyiowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiowh_alt_128BAlias : InstAlias<"$Vd32=vmpyiowh($Vu32,$Vv32)", (V6_vmpyiowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyiwb_acc_altAlias : InstAlias<"$Vx32+=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwb_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwb_altAlias : InstAlias<"$Vd32=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwb_alt_128BAlias : InstAlias<"$Vd32=vmpyiwb($Vu32,$Rt32)", (V6_vmpyiwb VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwh_acc_altAlias : InstAlias<"$Vx32+=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwh_acc_alt_128BAlias : InstAlias<"$Vx32+=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwh_altAlias : InstAlias<"$Vd32=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyiwh_alt_128BAlias : InstAlias<"$Vd32=vmpyiwh($Vu32,$Rt32)", (V6_vmpyiwh VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyowh_altAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:sat", (V6_vmpyowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyowh_alt_128BAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:sat", (V6_vmpyowh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyowh_rnd_altAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyowh_rnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyowh_rnd_alt_128BAlias : InstAlias<"$Vd32=vmpyowh($Vu32,$Vv32):<<1:rnd:sat", (V6_vmpyowh_rnd VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyub_acc_altAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Rt32)", (V6_vmpyub_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyub_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Rt32)", (V6_vmpyub_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyub_altAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Rt32)", (V6_vmpyub VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyub_alt_128BAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Rt32)", (V6_vmpyub VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyubv_acc_altAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Vv32)", (V6_vmpyubv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyubv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyub($Vu32,$Vv32)", (V6_vmpyubv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyubv_altAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Vv32)", (V6_vmpyubv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyubv_alt_128BAlias : InstAlias<"$Vdd32=vmpyub($Vu32,$Vv32)", (V6_vmpyubv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyuh_acc_altAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyuh_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyuh_altAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyuh_alt_128BAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Rt32)", (V6_vmpyuh VecDblRegs:$Vdd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vmpyuhv_acc_altAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyuhv_acc_alt_128BAlias : InstAlias<"$Vxx32+=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv_acc VecDblRegs:$Vxx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyuhv_altAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vmpyuhv_alt_128BAlias : InstAlias<"$Vdd32=vmpyuh($Vu32,$Vv32)", (V6_vmpyuhv VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgh_altAlias : InstAlias<"$Vd32=vnavgh($Vu32,$Vv32)", (V6_vnavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgh_alt_128BAlias : InstAlias<"$Vd32=vnavgh($Vu32,$Vv32)", (V6_vnavgh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgub_altAlias : InstAlias<"$Vd32=vnavgub($Vu32,$Vv32)", (V6_vnavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgub_alt_128BAlias : InstAlias<"$Vd32=vnavgub($Vu32,$Vv32)", (V6_vnavgub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgw_altAlias : InstAlias<"$Vd32=vnavgw($Vu32,$Vv32)", (V6_vnavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vnavgw_alt_128BAlias : InstAlias<"$Vd32=vnavgw($Vu32,$Vv32)", (V6_vnavgw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vnormamth_altAlias : InstAlias<"$Vd32=vnormamth($Vu32)", (V6_vnormamth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vnormamth_alt_128BAlias : InstAlias<"$Vd32=vnormamth($Vu32)", (V6_vnormamth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vnormamtw_altAlias : InstAlias<"$Vd32=vnormamtw($Vu32)", (V6_vnormamtw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vnormamtw_alt_128BAlias : InstAlias<"$Vd32=vnormamtw($Vu32)", (V6_vnormamtw VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vpackeb_altAlias : InstAlias<"$Vd32=vpackeb($Vu32,$Vv32)", (V6_vpackeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackeb_alt_128BAlias : InstAlias<"$Vd32=vpackeb($Vu32,$Vv32)", (V6_vpackeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackeh_altAlias : InstAlias<"$Vd32=vpackeh($Vu32,$Vv32)", (V6_vpackeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackeh_alt_128BAlias : InstAlias<"$Vd32=vpackeh($Vu32,$Vv32)", (V6_vpackeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackhb_sat_altAlias : InstAlias<"$Vd32=vpackhb($Vu32,$Vv32):sat", (V6_vpackhb_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackhb_sat_alt_128BAlias : InstAlias<"$Vd32=vpackhb($Vu32,$Vv32):sat", (V6_vpackhb_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackhub_sat_altAlias : InstAlias<"$Vd32=vpackhub($Vu32,$Vv32):sat", (V6_vpackhub_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackhub_sat_alt_128BAlias : InstAlias<"$Vd32=vpackhub($Vu32,$Vv32):sat", (V6_vpackhub_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackob_altAlias : InstAlias<"$Vd32=vpackob($Vu32,$Vv32)", (V6_vpackob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackob_alt_128BAlias : InstAlias<"$Vd32=vpackob($Vu32,$Vv32)", (V6_vpackob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackoh_altAlias : InstAlias<"$Vd32=vpackoh($Vu32,$Vv32)", (V6_vpackoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackoh_alt_128BAlias : InstAlias<"$Vd32=vpackoh($Vu32,$Vv32)", (V6_vpackoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackwh_sat_altAlias : InstAlias<"$Vd32=vpackwh($Vu32,$Vv32):sat", (V6_vpackwh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackwh_sat_alt_128BAlias : InstAlias<"$Vd32=vpackwh($Vu32,$Vv32):sat", (V6_vpackwh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackwuh_sat_altAlias : InstAlias<"$Vd32=vpackwuh($Vu32,$Vv32):sat", (V6_vpackwuh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpackwuh_sat_alt_128BAlias : InstAlias<"$Vd32=vpackwuh($Vu32,$Vv32):sat", (V6_vpackwuh_sat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vpopcounth_altAlias : InstAlias<"$Vd32=vpopcounth($Vu32)", (V6_vpopcounth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vpopcounth_alt_128BAlias : InstAlias<"$Vd32=vpopcounth($Vu32)", (V6_vpopcounth VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vrmpybus_acc_altAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpybus_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpybus_altAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpybus_alt_128BAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Rt32)", (V6_vrmpybus VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpybusi_acc_altAlias : InstAlias<"$Vxx32+=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpybusi_acc_alt_128BAlias : InstAlias<"$Vxx32+=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpybusi_altAlias : InstAlias<"$Vdd32=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpybusi_alt_128BAlias : InstAlias<"$Vdd32=vrmpybus($Vuu32,$Rt32,#$Ii)", (V6_vrmpybusi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpybusv_acc_altAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybusv_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybusv_altAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybusv_alt_128BAlias : InstAlias<"$Vd32=vrmpybus($Vu32,$Vv32)", (V6_vrmpybusv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybv_acc_altAlias : InstAlias<"$Vx32+=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybv_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybv_altAlias : InstAlias<"$Vd32=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpybv_alt_128BAlias : InstAlias<"$Vd32=vrmpyb($Vu32,$Vv32)", (V6_vrmpybv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpyub_acc_altAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpyub_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub_acc VectorRegs:$Vx32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpyub_altAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpyub_alt_128BAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Rt32)", (V6_vrmpyub VectorRegs:$Vd32, VectorRegs:$Vu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vrmpyubi_acc_altAlias : InstAlias<"$Vxx32+=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpyubi_acc_alt_128BAlias : InstAlias<"$Vxx32+=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpyubi_altAlias : InstAlias<"$Vdd32=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpyubi_alt_128BAlias : InstAlias<"$Vdd32=vrmpyub($Vuu32,$Rt32,#$Ii)", (V6_vrmpyubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrmpyubv_acc_altAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpyubv_acc_alt_128BAlias : InstAlias<"$Vx32+=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv_acc VectorRegs:$Vx32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpyubv_altAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrmpyubv_alt_128BAlias : InstAlias<"$Vd32=vrmpyub($Vu32,$Vv32)", (V6_vrmpyubv VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundhb_altAlias : InstAlias<"$Vd32=vroundhb($Vu32,$Vv32):sat", (V6_vroundhb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundhb_alt_128BAlias : InstAlias<"$Vd32=vroundhb($Vu32,$Vv32):sat", (V6_vroundhb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundhub_altAlias : InstAlias<"$Vd32=vroundhub($Vu32,$Vv32):sat", (V6_vroundhub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundhub_alt_128BAlias : InstAlias<"$Vd32=vroundhub($Vu32,$Vv32):sat", (V6_vroundhub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundwh_altAlias : InstAlias<"$Vd32=vroundwh($Vu32,$Vv32):sat", (V6_vroundwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundwh_alt_128BAlias : InstAlias<"$Vd32=vroundwh($Vu32,$Vv32):sat", (V6_vroundwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundwuh_altAlias : InstAlias<"$Vd32=vroundwuh($Vu32,$Vv32):sat", (V6_vroundwuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vroundwuh_alt_128BAlias : InstAlias<"$Vd32=vroundwuh($Vu32,$Vv32):sat", (V6_vroundwuh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vrsadubi_acc_altAlias : InstAlias<"$Vxx32+=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrsadubi_acc_alt_128BAlias : InstAlias<"$Vxx32+=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrsadubi_altAlias : InstAlias<"$Vdd32=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vrsadubi_alt_128BAlias : InstAlias<"$Vdd32=vrsadub($Vuu32,$Rt32,#$Ii)", (V6_vrsadubi VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32, u1_0Imm:$Ii)>, Requires<[UseHVX]>; +def V6_vsathub_altAlias : InstAlias<"$Vd32=vsathub($Vu32,$Vv32)", (V6_vsathub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsathub_alt_128BAlias : InstAlias<"$Vd32=vsathub($Vu32,$Vv32)", (V6_vsathub VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsatwh_altAlias : InstAlias<"$Vd32=vsatwh($Vu32,$Vv32)", (V6_vsatwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsatwh_alt_128BAlias : InstAlias<"$Vd32=vsatwh($Vu32,$Vv32)", (V6_vsatwh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsb_altAlias : InstAlias<"$Vdd32=vsxtb($Vu32)", (V6_vsb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsb_alt_128BAlias : InstAlias<"$Vdd32=vsxtb($Vu32)", (V6_vsb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsh_altAlias : InstAlias<"$Vdd32=vsxth($Vu32)", (V6_vsh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsh_alt_128BAlias : InstAlias<"$Vdd32=vsxth($Vu32)", (V6_vsh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vshufeh_altAlias : InstAlias<"$Vd32=vshuffeh($Vu32,$Vv32)", (V6_vshufeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufeh_alt_128BAlias : InstAlias<"$Vd32=vshuffeh($Vu32,$Vv32)", (V6_vshufeh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshuffb_altAlias : InstAlias<"$Vd32=vshuffb($Vu32)", (V6_vshuffb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vshuffb_alt_128BAlias : InstAlias<"$Vd32=vshuffb($Vu32)", (V6_vshuffb VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vshuffeb_altAlias : InstAlias<"$Vd32=vshuffeb($Vu32,$Vv32)", (V6_vshuffeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshuffeb_alt_128BAlias : InstAlias<"$Vd32=vshuffeb($Vu32,$Vv32)", (V6_vshuffeb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshuffh_altAlias : InstAlias<"$Vd32=vshuffh($Vu32)", (V6_vshuffh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vshuffh_alt_128BAlias : InstAlias<"$Vd32=vshuffh($Vu32)", (V6_vshuffh VectorRegs:$Vd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vshuffob_altAlias : InstAlias<"$Vd32=vshuffob($Vu32,$Vv32)", (V6_vshuffob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshuffob_alt_128BAlias : InstAlias<"$Vd32=vshuffob($Vu32,$Vv32)", (V6_vshuffob VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoeb_altAlias : InstAlias<"$Vdd32=vshuffoeb($Vu32,$Vv32)", (V6_vshufoeb VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoeb_alt_128BAlias : InstAlias<"$Vdd32=vshuffoeb($Vu32,$Vv32)", (V6_vshufoeb VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoeh_altAlias : InstAlias<"$Vdd32=vshuffoeh($Vu32,$Vv32)", (V6_vshufoeh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoeh_alt_128BAlias : InstAlias<"$Vdd32=vshuffoeh($Vu32,$Vv32)", (V6_vshufoeh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoh_altAlias : InstAlias<"$Vd32=vshuffoh($Vu32,$Vv32)", (V6_vshufoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vshufoh_alt_128BAlias : InstAlias<"$Vd32=vshuffoh($Vu32,$Vv32)", (V6_vshufoh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubb_altAlias : InstAlias<"$Vd32=vsubb($Vu32,$Vv32)", (V6_vsubb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubb_alt_128BAlias : InstAlias<"$Vd32=vsubb($Vu32,$Vv32)", (V6_vsubb VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubb_dv_altAlias : InstAlias<"$Vdd32=vsubb($Vuu32,$Vvv32)", (V6_vsubb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubb_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubb($Vuu32,$Vvv32)", (V6_vsubb_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubbnq_altAlias : InstAlias<"if (!$Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubbnq_alt_128BAlias : InstAlias<"if (!$Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubbq_altAlias : InstAlias<"if ($Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubbq_alt_128BAlias : InstAlias<"if ($Qv4.b) $Vx32.b-=$Vu32.b", (V6_vsubbq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubh_altAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32)", (V6_vsubh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubh_alt_128BAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32)", (V6_vsubh VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubh_dv_altAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32)", (V6_vsubh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubh_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32)", (V6_vsubh_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubhnq_altAlias : InstAlias<"if (!$Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubhnq_alt_128BAlias : InstAlias<"if (!$Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubhq_altAlias : InstAlias<"if ($Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubhq_alt_128BAlias : InstAlias<"if ($Qv4.h) $Vx32.h-=$Vu32.h", (V6_vsubhq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubhsat_altAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32):sat", (V6_vsubhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubhsat_alt_128BAlias : InstAlias<"$Vd32=vsubh($Vu32,$Vv32):sat", (V6_vsubhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubhsat_dv_altAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32):sat", (V6_vsubhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubh($Vuu32,$Vvv32):sat", (V6_vsubhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubhw_altAlias : InstAlias<"$Vdd32=vsubh($Vu32,$Vv32)", (V6_vsubhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubhw_alt_128BAlias : InstAlias<"$Vdd32=vsubh($Vu32,$Vv32)", (V6_vsubhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsububh_altAlias : InstAlias<"$Vdd32=vsubub($Vu32,$Vv32)", (V6_vsububh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsububh_alt_128BAlias : InstAlias<"$Vdd32=vsubub($Vu32,$Vv32)", (V6_vsububh VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsububsat_altAlias : InstAlias<"$Vd32=vsubub($Vu32,$Vv32):sat", (V6_vsububsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsububsat_alt_128BAlias : InstAlias<"$Vd32=vsubub($Vu32,$Vv32):sat", (V6_vsububsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsububsat_dv_altAlias : InstAlias<"$Vdd32=vsubub($Vuu32,$Vvv32):sat", (V6_vsububsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsububsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubub($Vuu32,$Vvv32):sat", (V6_vsububsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubuhsat_altAlias : InstAlias<"$Vd32=vsubuh($Vu32,$Vv32):sat", (V6_vsubuhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubuhsat_alt_128BAlias : InstAlias<"$Vd32=vsubuh($Vu32,$Vv32):sat", (V6_vsubuhsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubuhsat_dv_altAlias : InstAlias<"$Vdd32=vsubuh($Vuu32,$Vvv32):sat", (V6_vsubuhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubuhsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubuh($Vuu32,$Vvv32):sat", (V6_vsubuhsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubuhw_altAlias : InstAlias<"$Vdd32=vsubuh($Vu32,$Vv32)", (V6_vsubuhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubuhw_alt_128BAlias : InstAlias<"$Vdd32=vsubuh($Vu32,$Vv32)", (V6_vsubuhw VecDblRegs:$Vdd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubw_altAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32)", (V6_vsubw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubw_alt_128BAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32)", (V6_vsubw VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubw_dv_altAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32)", (V6_vsubw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubw_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32)", (V6_vsubw_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubwnq_altAlias : InstAlias<"if (!$Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubwnq_alt_128BAlias : InstAlias<"if (!$Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwnq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubwq_altAlias : InstAlias<"if ($Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubwq_alt_128BAlias : InstAlias<"if ($Qv4.w) $Vx32.w-=$Vu32.w", (V6_vsubwq VectorRegs:$Vx32, VecPredRegs:$Qv4, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vsubwsat_altAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32):sat", (V6_vsubwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubwsat_alt_128BAlias : InstAlias<"$Vd32=vsubw($Vu32,$Vv32):sat", (V6_vsubwsat VectorRegs:$Vd32, VectorRegs:$Vu32, VectorRegs:$Vv32)>, Requires<[UseHVX]>; +def V6_vsubwsat_dv_altAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32):sat", (V6_vsubwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vsubwsat_dv_alt_128BAlias : InstAlias<"$Vdd32=vsubw($Vuu32,$Vvv32):sat", (V6_vsubwsat_dv VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, VecDblRegs:$Vvv32)>, Requires<[UseHVX]>; +def V6_vtmpyb_acc_altAlias : InstAlias<"$Vxx32+=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyb_acc_alt_128BAlias : InstAlias<"$Vxx32+=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyb_altAlias : InstAlias<"$Vdd32=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyb_alt_128BAlias : InstAlias<"$Vdd32=vtmpyb($Vuu32,$Rt32)", (V6_vtmpyb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpybus_acc_altAlias : InstAlias<"$Vxx32+=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpybus_acc_alt_128BAlias : InstAlias<"$Vxx32+=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpybus_altAlias : InstAlias<"$Vdd32=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpybus_alt_128BAlias : InstAlias<"$Vdd32=vtmpybus($Vuu32,$Rt32)", (V6_vtmpybus VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyhb_acc_altAlias : InstAlias<"$Vxx32+=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyhb_acc_alt_128BAlias : InstAlias<"$Vxx32+=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb_acc VecDblRegs:$Vxx32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyhb_altAlias : InstAlias<"$Vdd32=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtmpyhb_alt_128BAlias : InstAlias<"$Vdd32=vtmpyhb($Vuu32,$Rt32)", (V6_vtmpyhb VecDblRegs:$Vdd32, VecDblRegs:$Vuu32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtran2x2_mapAlias : InstAlias<"vtrans2x2($Vy32,$Vx32,$Rt32)", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vtran2x2_map_128BAlias : InstAlias<"vtrans2x2($Vy32,$Vx32,$Rt32)", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, IntRegs:$Rt32)>, Requires<[UseHVX]>; +def V6_vunpackb_altAlias : InstAlias<"$Vdd32=vunpackb($Vu32)", (V6_vunpackb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackb_alt_128BAlias : InstAlias<"$Vdd32=vunpackb($Vu32)", (V6_vunpackb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackh_altAlias : InstAlias<"$Vdd32=vunpackh($Vu32)", (V6_vunpackh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackh_alt_128BAlias : InstAlias<"$Vdd32=vunpackh($Vu32)", (V6_vunpackh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackoh_altAlias : InstAlias<"$Vxx32|=vunpackoh($Vu32)", (V6_vunpackoh VecDblRegs:$Vxx32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackoh_alt_128BAlias : InstAlias<"$Vxx32|=vunpackoh($Vu32)", (V6_vunpackoh VecDblRegs:$Vxx32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackub_altAlias : InstAlias<"$Vdd32=vunpackub($Vu32)", (V6_vunpackub VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackub_alt_128BAlias : InstAlias<"$Vdd32=vunpackub($Vu32)", (V6_vunpackub VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackuh_altAlias : InstAlias<"$Vdd32=vunpackuh($Vu32)", (V6_vunpackuh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vunpackuh_alt_128BAlias : InstAlias<"$Vdd32=vunpackuh($Vu32)", (V6_vunpackuh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vzb_altAlias : InstAlias<"$Vdd32=vzxtb($Vu32)", (V6_vzb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vzb_alt_128BAlias : InstAlias<"$Vdd32=vzxtb($Vu32)", (V6_vzb VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vzh_altAlias : InstAlias<"$Vdd32=vzxth($Vu32)", (V6_vzh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def V6_vzh_alt_128BAlias : InstAlias<"$Vdd32=vzxth($Vu32)", (V6_vzh VecDblRegs:$Vdd32, VectorRegs:$Vu32)>, Requires<[UseHVX]>; +def Y2_dcfetchAlias : InstAlias<"dcfetch($Rs32)", (Y2_dcfetchbo IntRegs:$Rs32, 0)>; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonDepOperands.td b/contrib/llvm/lib/Target/Hexagon/HexagonDepOperands.td new file mode 100644 index 000000000000..0e83b2678732 --- /dev/null +++ b/contrib/llvm/lib/Target/Hexagon/HexagonDepOperands.td @@ -0,0 +1,132 @@ +//===--- HexagonDepOperands.td --------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +def s3_0ImmOperand : AsmOperandClass { let Name = "s3_0Imm"; let RenderMethod = "addSignedImmOperands"; } +def s3_0Imm : Operand<i32> { let ParserMatchClass = s3_0ImmOperand; let DecoderMethod = "s3_0ImmDecoder"; } +def s3_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<3, 0>(N->getSExtValue());}]>; +def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; let RenderMethod = "addSignedImmOperands"; } +def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand; let DecoderMethod = "s4_0ImmDecoder"; } +def s4_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 0>(N->getSExtValue());}]>; +def s29_3ImmOperand : AsmOperandClass { let Name = "s29_3Imm"; let RenderMethod = "addSignedImmOperands"; } +def s29_3Imm : Operand<i32> { let ParserMatchClass = s29_3ImmOperand; let DecoderMethod = "s29_3ImmDecoder"; } +def s29_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 3>(N->getSExtValue());}]>; +def s10_6ImmOperand : AsmOperandClass { let Name = "s10_6Imm"; let RenderMethod = "addSignedImmOperands"; } +def s10_6Imm : Operand<i32> { let ParserMatchClass = s10_6ImmOperand; let DecoderMethod = "s10_6ImmDecoder"; } +def s10_6ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<10, 6>(N->getSExtValue());}]>; +def u6_0ImmOperand : AsmOperandClass { let Name = "u6_0Imm"; let RenderMethod = "addImmOperands"; } +def u6_0Imm : Operand<i32> { let ParserMatchClass = u6_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u6_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<6, 0>(N->getSExtValue());}]>; +def a30_2ImmOperand : AsmOperandClass { let Name = "a30_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def a30_2Imm : Operand<i32> { let ParserMatchClass = a30_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } +def a30_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 2>(N->getSExtValue());}]>; +def u29_3ImmOperand : AsmOperandClass { let Name = "u29_3Imm"; let RenderMethod = "addImmOperands"; } +def u29_3Imm : Operand<i32> { let ParserMatchClass = u29_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u29_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<32, 3>(N->getSExtValue());}]>; +def s8_0ImmOperand : AsmOperandClass { let Name = "s8_0Imm"; let RenderMethod = "addSignedImmOperands"; } +def s8_0Imm : Operand<i32> { let ParserMatchClass = s8_0ImmOperand; let DecoderMethod = "s8_0ImmDecoder"; } +def s8_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<8, 0>(N->getSExtValue());}]>; +def u32_0ImmOperand : AsmOperandClass { let Name = "u32_0Imm"; let RenderMethod = "addImmOperands"; } +def u32_0Imm : Operand<i32> { let ParserMatchClass = u32_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u32_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<32, 0>(N->getSExtValue());}]>; +def u4_2ImmOperand : AsmOperandClass { let Name = "u4_2Imm"; let RenderMethod = "addImmOperands"; } +def u4_2Imm : Operand<i32> { let ParserMatchClass = u4_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u4_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<4, 2>(N->getSExtValue());}]>; +def u3_0ImmOperand : AsmOperandClass { let Name = "u3_0Imm"; let RenderMethod = "addImmOperands"; } +def u3_0Imm : Operand<i32> { let ParserMatchClass = u3_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u3_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<3, 0>(N->getSExtValue());}]>; +def b15_2ImmOperand : AsmOperandClass { let Name = "b15_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def b15_2Imm : Operand<OtherVT> { let ParserMatchClass = b15_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } +def b15_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<15, 2>(N->getSExtValue());}]>; +def u11_3ImmOperand : AsmOperandClass { let Name = "u11_3Imm"; let RenderMethod = "addImmOperands"; } +def u11_3Imm : Operand<i32> { let ParserMatchClass = u11_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u11_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<11, 3>(N->getSExtValue());}]>; +def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; let RenderMethod = "addSignedImmOperands"; } +def s4_3Imm : Operand<i32> { let ParserMatchClass = s4_3ImmOperand; let DecoderMethod = "s4_3ImmDecoder"; } +def s4_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 3>(N->getSExtValue());}]>; +def m32_0ImmOperand : AsmOperandClass { let Name = "m32_0Imm"; let RenderMethod = "addImmOperands"; } +def m32_0Imm : Operand<i32> { let ParserMatchClass = m32_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def m32_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 0>(N->getSExtValue());}]>; +def u3_1ImmOperand : AsmOperandClass { let Name = "u3_1Imm"; let RenderMethod = "addImmOperands"; } +def u3_1Imm : Operand<i32> { let ParserMatchClass = u3_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u3_1ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<3, 1>(N->getSExtValue());}]>; +def u1_0ImmOperand : AsmOperandClass { let Name = "u1_0Imm"; let RenderMethod = "addImmOperands"; } +def u1_0Imm : Operand<i32> { let ParserMatchClass = u1_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u1_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<1, 0>(N->getSExtValue());}]>; +def s31_1ImmOperand : AsmOperandClass { let Name = "s31_1Imm"; let RenderMethod = "addSignedImmOperands"; } +def s31_1Imm : Operand<i32> { let ParserMatchClass = s31_1ImmOperand; let DecoderMethod = "s31_1ImmDecoder"; } +def s31_1ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 1>(N->getSExtValue());}]>; +def s30_2ImmOperand : AsmOperandClass { let Name = "s30_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def s30_2Imm : Operand<i32> { let ParserMatchClass = s30_2ImmOperand; let DecoderMethod = "s30_2ImmDecoder"; } +def s30_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 2>(N->getSExtValue());}]>; +def u4_0ImmOperand : AsmOperandClass { let Name = "u4_0Imm"; let RenderMethod = "addImmOperands"; } +def u4_0Imm : Operand<i32> { let ParserMatchClass = u4_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u4_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<4, 0>(N->getSExtValue());}]>; +def s6_0ImmOperand : AsmOperandClass { let Name = "s6_0Imm"; let RenderMethod = "addSignedImmOperands"; } +def s6_0Imm : Operand<i32> { let ParserMatchClass = s6_0ImmOperand; let DecoderMethod = "s6_0ImmDecoder"; } +def s6_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<6, 0>(N->getSExtValue());}]>; +def u5_3ImmOperand : AsmOperandClass { let Name = "u5_3Imm"; let RenderMethod = "addImmOperands"; } +def u5_3Imm : Operand<i32> { let ParserMatchClass = u5_3ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u5_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<5, 3>(N->getSExtValue());}]>; +def s32_0ImmOperand : AsmOperandClass { let Name = "s32_0Imm"; let RenderMethod = "addSignedImmOperands"; } +def s32_0Imm : Operand<i32> { let ParserMatchClass = s32_0ImmOperand; let DecoderMethod = "s32_0ImmDecoder"; } +def s32_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 0>(N->getSExtValue());}]>; +def s6_3ImmOperand : AsmOperandClass { let Name = "s6_3Imm"; let RenderMethod = "addSignedImmOperands"; } +def s6_3Imm : Operand<i32> { let ParserMatchClass = s6_3ImmOperand; let DecoderMethod = "s6_3ImmDecoder"; } +def s6_3ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<6, 3>(N->getSExtValue());}]>; +def u10_0ImmOperand : AsmOperandClass { let Name = "u10_0Imm"; let RenderMethod = "addImmOperands"; } +def u10_0Imm : Operand<i32> { let ParserMatchClass = u10_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u10_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<10, 0>(N->getSExtValue());}]>; +def u31_1ImmOperand : AsmOperandClass { let Name = "u31_1Imm"; let RenderMethod = "addImmOperands"; } +def u31_1Imm : Operand<i32> { let ParserMatchClass = u31_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u31_1ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<32, 1>(N->getSExtValue());}]>; +def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; let RenderMethod = "addSignedImmOperands"; } +def s4_1Imm : Operand<i32> { let ParserMatchClass = s4_1ImmOperand; let DecoderMethod = "s4_1ImmDecoder"; } +def s4_1ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 1>(N->getSExtValue());}]>; +def u16_0ImmOperand : AsmOperandClass { let Name = "u16_0Imm"; let RenderMethod = "addImmOperands"; } +def u16_0Imm : Operand<i32> { let ParserMatchClass = u16_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u16_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<16, 0>(N->getSExtValue());}]>; +def u6_1ImmOperand : AsmOperandClass { let Name = "u6_1Imm"; let RenderMethod = "addImmOperands"; } +def u6_1Imm : Operand<i32> { let ParserMatchClass = u6_1ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u6_1ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<6, 1>(N->getSExtValue());}]>; +def u5_2ImmOperand : AsmOperandClass { let Name = "u5_2Imm"; let RenderMethod = "addImmOperands"; } +def u5_2Imm : Operand<i32> { let ParserMatchClass = u5_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u5_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<5, 2>(N->getSExtValue());}]>; +def u26_6ImmOperand : AsmOperandClass { let Name = "u26_6Imm"; let RenderMethod = "addImmOperands"; } +def u26_6Imm : Operand<i32> { let ParserMatchClass = u26_6ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u26_6ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<26, 6>(N->getSExtValue());}]>; +def u6_2ImmOperand : AsmOperandClass { let Name = "u6_2Imm"; let RenderMethod = "addImmOperands"; } +def u6_2Imm : Operand<i32> { let ParserMatchClass = u6_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u6_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<6, 2>(N->getSExtValue());}]>; +def u7_0ImmOperand : AsmOperandClass { let Name = "u7_0Imm"; let RenderMethod = "addImmOperands"; } +def u7_0Imm : Operand<i32> { let ParserMatchClass = u7_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u7_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<7, 0>(N->getSExtValue());}]>; +def b13_2ImmOperand : AsmOperandClass { let Name = "b13_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def b13_2Imm : Operand<OtherVT> { let ParserMatchClass = b13_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } +def b13_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<13, 2>(N->getSExtValue());}]>; +def u5_0ImmOperand : AsmOperandClass { let Name = "u5_0Imm"; let RenderMethod = "addImmOperands"; } +def u5_0Imm : Operand<i32> { let ParserMatchClass = u5_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u5_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<5, 0>(N->getSExtValue());}]>; +def u2_0ImmOperand : AsmOperandClass { let Name = "u2_0Imm"; let RenderMethod = "addImmOperands"; } +def u2_0Imm : Operand<i32> { let ParserMatchClass = u2_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u2_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<2, 0>(N->getSExtValue());}]>; +def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def s4_2Imm : Operand<i32> { let ParserMatchClass = s4_2ImmOperand; let DecoderMethod = "s4_2ImmDecoder"; } +def s4_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<4, 2>(N->getSExtValue());}]>; +def b30_2ImmOperand : AsmOperandClass { let Name = "b30_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def b30_2Imm : Operand<OtherVT> { let ParserMatchClass = b30_2ImmOperand; let DecoderMethod = "brtargetDecoder"; let PrintMethod = "printBrtarget"; } +def b30_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<32, 2>(N->getSExtValue());}]>; +def u8_0ImmOperand : AsmOperandClass { let Name = "u8_0Imm"; let RenderMethod = "addImmOperands"; } +def u8_0Imm : Operand<i32> { let ParserMatchClass = u8_0ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u8_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<8, 0>(N->getSExtValue());}]>; +def u30_2ImmOperand : AsmOperandClass { let Name = "u30_2Imm"; let RenderMethod = "addImmOperands"; } +def u30_2Imm : Operand<i32> { let ParserMatchClass = u30_2ImmOperand; let DecoderMethod = "unsignedImmDecoder"; } +def u30_2ImmPred : PatLeaf<(i32 imm), [{ return isShiftedUInt<32, 2>(N->getSExtValue());}]>; +def s10_0ImmOperand : AsmOperandClass { let Name = "s10_0Imm"; let RenderMethod = "addSignedImmOperands"; } +def s10_0Imm : Operand<i32> { let ParserMatchClass = s10_0ImmOperand; let DecoderMethod = "s10_0ImmDecoder"; } +def s10_0ImmPred : PatLeaf<(i32 imm), [{ return isShiftedInt<10, 0>(N->getSExtValue());}]>; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index a5351cd08da5..67af947e089d 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -105,6 +105,8 @@ namespace { cl::init(false), cl::desc("Enable branch probability info")); cl::opt<unsigned> SizeLimit("eif-limit", cl::init(6), cl::Hidden, cl::desc("Size limit in Hexagon early if-conversion")); + cl::opt<bool> SkipExitBranches("eif-no-loop-exit", cl::init(false), + cl::Hidden, cl::desc("Do not convert branches that may exit the loop")); struct PrintMB { PrintMB(const MachineBasicBlock *B) : MB(B) {} @@ -142,8 +144,8 @@ namespace { raw_ostream &operator<<(raw_ostream &OS, const PrintFP &P) { OS << "{ SplitB:" << PrintMB(P.FP.SplitB) << ", PredR:" << PrintReg(P.FP.PredR, &P.TRI) - << ", TrueB:" << PrintMB(P.FP.TrueB) << ", FalseB:" - << PrintMB(P.FP.FalseB) + << ", TrueB:" << PrintMB(P.FP.TrueB) + << ", FalseB:" << PrintMB(P.FP.FalseB) << ", JoinB:" << PrintMB(P.FP.JoinB) << " }"; return OS; } @@ -187,7 +189,8 @@ namespace { bool usesUndefVReg(const MachineInstr *MI) const; bool isValid(const FlowPattern &FP) const; unsigned countPredicateDefs(const MachineBasicBlock *B) const; - unsigned computePhiCost(MachineBasicBlock *B) const; + unsigned computePhiCost(const MachineBasicBlock *B, + const FlowPattern &FP) const; bool isProfitable(const FlowPattern &FP) const; bool isPredicableStore(const MachineInstr *MI) const; bool isSafeToSpeculate(const MachineInstr *MI) const; @@ -199,6 +202,9 @@ namespace { MachineBasicBlock::iterator At, MachineBasicBlock *FromB, unsigned PredR, bool IfTrue); + unsigned buildMux(MachineBasicBlock *B, MachineBasicBlock::iterator At, + const TargetRegisterClass *DRC, unsigned PredR, unsigned TR, + unsigned TSR, unsigned FR, unsigned FSR); void updatePhiNodes(MachineBasicBlock *WhereB, const FlowPattern &FP); void convert(const FlowPattern &FP); @@ -230,7 +236,7 @@ bool HexagonEarlyIfConversion::isPreheader(const MachineBasicBlock *B) const { return false; MachineBasicBlock *SB = *B->succ_begin(); MachineLoop *L = MLI->getLoopFor(SB); - return L && SB == L->getHeader(); + return L && SB == L->getHeader() && MDT->dominates(B, SB); } bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B, @@ -264,9 +270,6 @@ bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B, // mark as diamond with both sides equal? return false; } - // Loop could be null for both. - if (MLI->getLoopFor(T1B) != L || MLI->getLoopFor(T2B) != L) - return false; // Record the true/false blocks in such a way that "true" means "if (PredR)", // and "false" means "if (!PredR)". @@ -289,8 +292,14 @@ bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B, // it has a single successor. In fact, the block has to end either with // an unconditional branch (which can be predicated), or with a fall- // through. - bool TOk = (TNP == 1) && (TNS == 1); - bool FOk = (FNP == 1) && (FNS == 1); + // Also, skip blocks that do not belong to the same loop. + bool TOk = (TNP == 1 && TNS == 1 && MLI->getLoopFor(TB) == L); + bool FOk = (FNP == 1 && FNS == 1 && MLI->getLoopFor(FB) == L); + + // If requested (via an option), do not consider branches where the + // true and false targets do not belong to the same loop. + if (SkipExitBranches && MLI->getLoopFor(TB) != MLI->getLoopFor(FB)) + return false; // If neither is predicable, there is nothing interesting. if (!TOk && !FOk) @@ -307,17 +316,15 @@ bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B, // Diamond: "if (P) then TB; else FB;". } else { // TOk && !FOk - if (TSB == FB) { + if (TSB == FB) JB = FB; - FB = nullptr; - } + FB = nullptr; } } else { // !TOk && FOk (at least one must be true by now). - if (FSB == TB) { + if (FSB == TB) JB = TB; - TB = nullptr; - } + TB = nullptr; } // Don't try to predicate loop preheaders. if ((TB && isPreheader(TB)) || (FB && isPreheader(FB))) { @@ -383,8 +390,14 @@ bool HexagonEarlyIfConversion::isValidCandidate(const MachineBasicBlock *B) unsigned R = MO.getReg(); if (!TargetRegisterInfo::isVirtualRegister(R)) continue; - if (MRI->getRegClass(R) != &Hexagon::PredRegsRegClass) - continue; + switch (MRI->getRegClass(R)->getID()) { + case Hexagon::PredRegsRegClassID: + case Hexagon::VecPredRegsRegClassID: + case Hexagon::VecPredRegs128BRegClassID: + break; + default: + continue; + } for (auto U = MRI->use_begin(R); U != MRI->use_end(); ++U) if (U->getParent()->isPHI()) return false; @@ -442,24 +455,39 @@ bool HexagonEarlyIfConversion::isValid(const FlowPattern &FP) const { return true; } -unsigned HexagonEarlyIfConversion::computePhiCost(MachineBasicBlock *B) const { - assert(B->pred_size() <= 2); +unsigned HexagonEarlyIfConversion::computePhiCost(const MachineBasicBlock *B, + const FlowPattern &FP) const { if (B->pred_size() < 2) return 0; unsigned Cost = 0; - MachineBasicBlock::const_iterator I, E = B->getFirstNonPHI(); - for (I = B->begin(); I != E; ++I) { - const MachineOperand &RO1 = I->getOperand(1); - const MachineOperand &RO3 = I->getOperand(3); - assert(RO1.isReg() && RO3.isReg()); + for (const MachineInstr &MI : *B) { + if (!MI.isPHI()) + break; + // If both incoming blocks are one of the TrueB/FalseB/SplitB, then + // a MUX may be needed. Otherwise the PHI will need to be updated at + // no extra cost. + // Find the interesting PHI operands for further checks. + SmallVector<unsigned,2> Inc; + for (unsigned i = 1, e = MI.getNumOperands(); i != e; i += 2) { + const MachineBasicBlock *BB = MI.getOperand(i+1).getMBB(); + if (BB == FP.SplitB || BB == FP.TrueB || BB == FP.FalseB) + Inc.push_back(i); + } + assert(Inc.size() <= 2); + if (Inc.size() < 2) + continue; + + const MachineOperand &RA = MI.getOperand(1); + const MachineOperand &RB = MI.getOperand(3); + assert(RA.isReg() && RB.isReg()); // Must have a MUX if the phi uses a subregister. - if (RO1.getSubReg() != 0 || RO3.getSubReg() != 0) { + if (RA.getSubReg() != 0 || RB.getSubReg() != 0) { Cost++; continue; } - MachineInstr *Def1 = MRI->getVRegDef(RO1.getReg()); - MachineInstr *Def3 = MRI->getVRegDef(RO3.getReg()); + const MachineInstr *Def1 = MRI->getVRegDef(RA.getReg()); + const MachineInstr *Def3 = MRI->getVRegDef(RB.getReg()); if (!HII->isPredicable(*Def1) || !HII->isPredicable(*Def3)) Cost++; } @@ -485,7 +513,6 @@ unsigned HexagonEarlyIfConversion::countPredicateDefs( bool HexagonEarlyIfConversion::isProfitable(const FlowPattern &FP) const { if (FP.TrueB && FP.FalseB) { - // Do not IfCovert if the branch is one sided. if (MBPI) { BranchProbability Prob(9, 10); @@ -510,18 +537,16 @@ bool HexagonEarlyIfConversion::isProfitable(const FlowPattern &FP) const { // the code size. If the predicated blocks are smaller than a packet size, // approximate the spare room in the packet that could be filled with the // predicated/speculated instructions. - unsigned TS = 0, FS = 0, Spare = 0; - if (FP.TrueB) { - TS = std::distance(FP.TrueB->begin(), FP.TrueB->getFirstTerminator()); - if (TS < HEXAGON_PACKET_SIZE) - Spare += HEXAGON_PACKET_SIZE-TS; - } - if (FP.FalseB) { - FS = std::distance(FP.FalseB->begin(), FP.FalseB->getFirstTerminator()); - if (FS < HEXAGON_PACKET_SIZE) - Spare += HEXAGON_PACKET_SIZE-TS; - } - unsigned TotalIn = TS+FS; + auto TotalCount = [] (const MachineBasicBlock *B, unsigned &Spare) { + if (!B) + return 0u; + unsigned T = std::distance(B->begin(), B->getFirstTerminator()); + if (T < HEXAGON_PACKET_SIZE) + Spare += HEXAGON_PACKET_SIZE-T; + return T; + }; + unsigned Spare = 0; + unsigned TotalIn = TotalCount(FP.TrueB, Spare) + TotalCount(FP.FalseB, Spare); DEBUG(dbgs() << "Total number of instructions to be predicated/speculated: " << TotalIn << ", spare room: " << Spare << "\n"); if (TotalIn >= SizeLimit+Spare) @@ -536,17 +561,17 @@ bool HexagonEarlyIfConversion::isProfitable(const FlowPattern &FP) const { unsigned TotalPh = 0; unsigned PredDefs = countPredicateDefs(FP.SplitB); if (FP.JoinB) { - TotalPh = computePhiCost(FP.JoinB); + TotalPh = computePhiCost(FP.JoinB, FP); PredDefs += countPredicateDefs(FP.JoinB); } else { if (FP.TrueB && FP.TrueB->succ_size() > 0) { MachineBasicBlock *SB = *FP.TrueB->succ_begin(); - TotalPh += computePhiCost(SB); + TotalPh += computePhiCost(SB, FP); PredDefs += countPredicateDefs(SB); } if (FP.FalseB && FP.FalseB->succ_size() > 0) { MachineBasicBlock *SB = *FP.FalseB->succ_begin(); - TotalPh += computePhiCost(SB); + TotalPh += computePhiCost(SB, FP); PredDefs += countPredicateDefs(SB); } } @@ -680,12 +705,12 @@ void HexagonEarlyIfConversion::predicateInstr(MachineBasicBlock *ToB, MachineInstrBuilder MIB = BuildMI(*ToB, At, DL, HII->get(COpc)); MachineInstr::mop_iterator MOI = MI->operands_begin(); if (HII->isPostIncrement(*MI)) { - MIB.addOperand(*MOI); + MIB.add(*MOI); ++MOI; } MIB.addReg(PredR); for (const MachineOperand &MO : make_range(MOI, MI->operands_end())) - MIB.addOperand(MO); + MIB.add(MO); // Set memory references. MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); @@ -733,6 +758,43 @@ void HexagonEarlyIfConversion::predicateBlockNB(MachineBasicBlock *ToB, } } +unsigned HexagonEarlyIfConversion::buildMux(MachineBasicBlock *B, + MachineBasicBlock::iterator At, const TargetRegisterClass *DRC, + unsigned PredR, unsigned TR, unsigned TSR, unsigned FR, unsigned FSR) { + unsigned Opc = 0; + switch (DRC->getID()) { + case Hexagon::IntRegsRegClassID: + Opc = Hexagon::C2_mux; + break; + case Hexagon::DoubleRegsRegClassID: + Opc = Hexagon::PS_pselect; + break; + case Hexagon::VectorRegsRegClassID: + Opc = Hexagon::PS_vselect; + break; + case Hexagon::VecDblRegsRegClassID: + Opc = Hexagon::PS_wselect; + break; + case Hexagon::VectorRegs128BRegClassID: + Opc = Hexagon::PS_vselect_128B; + break; + case Hexagon::VecDblRegs128BRegClassID: + Opc = Hexagon::PS_wselect_128B; + break; + default: + llvm_unreachable("unexpected register type"); + } + const MCInstrDesc &D = HII->get(Opc); + + DebugLoc DL = B->findBranchDebugLoc(); + unsigned MuxR = MRI->createVirtualRegister(DRC); + BuildMI(*B, At, DL, D, MuxR) + .addReg(PredR) + .addReg(TR, 0, TSR) + .addReg(FR, 0, FSR); + return MuxR; +} + void HexagonEarlyIfConversion::updatePhiNodes(MachineBasicBlock *WhereB, const FlowPattern &FP) { // Visit all PHI nodes in the WhereB block and generate MUX instructions @@ -759,40 +821,25 @@ void HexagonEarlyIfConversion::updatePhiNodes(MachineBasicBlock *WhereB, TR = SR, TSR = SSR; else if (FR == 0) FR = SR, FSR = SSR; - assert(TR && FR); - - using namespace Hexagon; - - unsigned DR = PN->getOperand(0).getReg(); - const TargetRegisterClass *RC = MRI->getRegClass(DR); - unsigned Opc = 0; - if (RC == &IntRegsRegClass) - Opc = C2_mux; - else if (RC == &DoubleRegsRegClass) - Opc = PS_pselect; - else if (RC == &VectorRegsRegClass) - Opc = PS_vselect; - else if (RC == &VecDblRegsRegClass) - Opc = PS_wselect; - else if (RC == &VectorRegs128BRegClass) - Opc = PS_vselect_128B; - else if (RC == &VecDblRegs128BRegClass) - Opc = PS_wselect_128B; - else - llvm_unreachable("unexpected register type"); - const MCInstrDesc &D = HII->get(Opc); - - MachineBasicBlock::iterator MuxAt = FP.SplitB->getFirstTerminator(); - DebugLoc DL; - if (MuxAt != FP.SplitB->end()) - DL = MuxAt->getDebugLoc(); - unsigned MuxR = MRI->createVirtualRegister(RC); - BuildMI(*FP.SplitB, MuxAt, DL, D, MuxR) - .addReg(FP.PredR) - .addReg(TR, 0, TSR) - .addReg(FR, 0, FSR); - - PN->addOperand(MachineOperand::CreateReg(MuxR, false)); + + assert(TR || FR); + unsigned MuxR = 0, MuxSR = 0; + + if (TR && FR) { + unsigned DR = PN->getOperand(0).getReg(); + const TargetRegisterClass *RC = MRI->getRegClass(DR); + MuxR = buildMux(FP.SplitB, FP.SplitB->getFirstTerminator(), RC, + FP.PredR, TR, TSR, FR, FSR); + } else if (TR) { + MuxR = TR; + MuxSR = TSR; + } else { + MuxR = FR; + MuxSR = FSR; + } + + PN->addOperand(MachineOperand::CreateReg(MuxR, false, false, false, false, + false, false, MuxSR)); PN->addOperand(MachineOperand::CreateMBB(FP.SplitB)); } } diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp index 8f070d842b8c..d8ba5dcd35ad 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -362,14 +362,16 @@ void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM, if (Range.empty()) return; - auto IsRegDef = [this,Reg,LM] (MachineOperand &Op) -> bool { + // Return two booleans: { def-modifes-reg, def-covers-reg }. + auto IsRegDef = [this,Reg,LM] (MachineOperand &Op) -> std::pair<bool,bool> { if (!Op.isReg() || !Op.isDef()) - return false; + return { false, false }; unsigned DR = Op.getReg(), DSR = Op.getSubReg(); if (!TargetRegisterInfo::isVirtualRegister(DR) || DR != Reg) - return false; + return { false, false }; LaneBitmask SLM = getLaneMask(DR, DSR); - return (SLM & LM).any(); + LaneBitmask A = SLM & LM; + return { A.any(), A == SLM }; }; // The splitting step will create pairs of predicated definitions without @@ -453,20 +455,27 @@ void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM, // Remove <dead> flags from all defs that are not dead after live range // extension, and collect all def operands. They will be used to generate // the necessary implicit uses. + // At the same time, add <dead> flag to all defs that are actually dead. + // This can happen, for example, when a mux with identical inputs is + // replaced with a COPY: the use of the predicate register disappears and + // the dead can become dead. std::set<RegisterRef> DefRegs; for (auto &Seg : Range) { if (!Seg.start.isRegister()) continue; MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start); for (auto &Op : DefI->operands()) { - if (Seg.start.isDead() || !IsRegDef(Op)) - continue; - DefRegs.insert(Op); - Op.setIsDead(false); + auto P = IsRegDef(Op); + if (P.second && Seg.end.isDead()) { + Op.setIsDead(true); + } else if (P.first) { + DefRegs.insert(Op); + Op.setIsDead(false); + } } } - // Finally, add implicit uses to each predicated def that is reached + // Now, add implicit uses to each predicated def that is reached // by other defs. for (auto &Seg : Range) { if (!Seg.start.isRegister() || !Range.liveAt(Seg.start.getPrevSlot())) @@ -486,6 +495,7 @@ void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM, for (RegisterRef R : ImpUses) MachineInstrBuilder(MF, DefI).addReg(R.Reg, RegState::Implicit, R.Sub); } + } void HexagonExpandCondsets::updateDeadFlags(unsigned Reg) { @@ -595,9 +605,9 @@ MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg()); } else { MIB = BuildMI(B, At, DL, HII->get(Opc)) - .addReg(DstR, DstState, DstSR) - .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) - .addOperand(SrcOp); + .addReg(DstR, DstState, DstSR) + .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) + .add(SrcOp); } DEBUG(dbgs() << "created an initial copy: " << *MIB); @@ -622,6 +632,12 @@ bool HexagonExpandCondsets::split(MachineInstr &MI, bool ReadUndef = MD.isUndef(); MachineBasicBlock::iterator At = MI; + auto updateRegs = [&UpdRegs] (const MachineInstr &MI) -> void { + for (auto &Op : MI.operands()) + if (Op.isReg()) + UpdRegs.insert(Op.getReg()); + }; + // If this is a mux of the same register, just replace it with COPY. // Ideally, this would happen earlier, so that register coalescing would // see it. @@ -630,6 +646,8 @@ bool HexagonExpandCondsets::split(MachineInstr &MI, if (ST.isReg() && SF.isReg()) { RegisterRef RT(ST); if (RT == RegisterRef(SF)) { + // Copy regs to update first. + updateRegs(MI); MI.setDesc(HII->get(TargetOpcode::COPY)); unsigned S = getRegState(ST); while (MI.getNumOperands() > 1) @@ -651,9 +669,7 @@ bool HexagonExpandCondsets::split(MachineInstr &MI, LIS->InsertMachineInstrInMaps(*TfrF); // Will need to recalculate live intervals for all registers in MI. - for (auto &Op : MI.operands()) - if (Op.isReg()) - UpdRegs.insert(Op.getReg()); + updateRegs(MI); removeInstr(MI); return true; @@ -828,7 +844,7 @@ void HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp, while (Ox < NP) { MachineOperand &MO = MI.getOperand(Ox); if (!MO.isReg() || !MO.isImplicit()) - MB.addOperand(MO); + MB.add(MO); Ox++; } diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp index dfd1f1d4f886..015d3b840e6f 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp @@ -190,5 +190,5 @@ void HexagonFixupHwLoops::useExtLoopInstr(MachineFunction &MF, MIB = BuildMI(*MBB, MII, DL, TII->get(newOp)); for (unsigned i = 0; i < MII->getNumOperands(); ++i) - MIB.addOperand(MII->getOperand(i)); + MIB.add(MII->getOperand(i)); } diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp index a3f6273f9f67..0e2380f4316a 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -301,16 +301,30 @@ static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR, // the frame creation/destruction instructions. if (MO.isFI()) return true; - if (!MO.isReg()) - continue; - unsigned R = MO.getReg(); - // Virtual registers will need scavenging, which then may require - // a stack slot. - if (TargetRegisterInfo::isVirtualRegister(R)) - return true; - for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S) - if (CSR[*S]) + if (MO.isReg()) { + unsigned R = MO.getReg(); + // Virtual registers will need scavenging, which then may require + // a stack slot. + if (TargetRegisterInfo::isVirtualRegister(R)) return true; + for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S) + if (CSR[*S]) + return true; + continue; + } + if (MO.isRegMask()) { + // A regmask would normally have all callee-saved registers marked + // as preserved, so this check would not be needed, but in case of + // ever having other regmasks (for other calling conventions), + // make sure they would be processed correctly. + const uint32_t *BM = MO.getRegMask(); + for (int x = CSR.find_first(); x >= 0; x = CSR.find_next(x)) { + unsigned R = x; + // If this regmask does not preserve a CSR, a frame will be needed. + if (!(BM[R/32] & (1u << (R%32)))) + return true; + } + } } } return false; @@ -1473,8 +1487,7 @@ bool HexagonFrameLowering::expandCopy(MachineBasicBlock &B, return false; unsigned TmpR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); - BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), TmpR) - .addOperand(MI->getOperand(1)); + BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), TmpR).add(MI->getOperand(1)); BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), DstR) .addReg(TmpR, RegState::Kill); @@ -1646,8 +1659,15 @@ bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B, LivePhysRegs LPR(&HRI); LPR.addLiveIns(B); SmallVector<std::pair<unsigned, const MachineOperand*>,2> Clobbers; - for (auto R = B.begin(); R != It; ++R) + for (auto R = B.begin(); R != It; ++R) { + Clobbers.clear(); LPR.stepForward(*R, Clobbers); + // Dead defs are recorded in Clobbers, but are not automatically removed + // from the live set. + for (auto &C : Clobbers) + if (C.second->isReg() && C.second->isDead()) + LPR.removeReg(C.first); + } DebugLoc DL = MI->getDebugLoc(); unsigned SrcR = MI->getOperand(2).getReg(); @@ -1985,9 +2005,9 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, // class HaveRC and a new class NewRC. Return nullptr if a common class // cannot be found, otherwise return the resulting class. If HaveRC is // nullptr, assume that it is still unset. - auto getCommonRC = [&HRI] (const TargetRegisterClass *HaveRC, - const TargetRegisterClass *NewRC) - -> const TargetRegisterClass* { + auto getCommonRC = + [](const TargetRegisterClass *HaveRC, + const TargetRegisterClass *NewRC) -> const TargetRegisterClass * { if (HaveRC == nullptr || HaveRC == NewRC) return NewRC; // Different classes, both non-null. Pick the more general one. @@ -2221,7 +2241,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF, if (SrcRR.Reg != FoundR || SrcRR.Sub != 0) { const DebugLoc &DL = SI.getDebugLoc(); CopyIn = BuildMI(B, StartIt, DL, HII.get(TargetOpcode::COPY), FoundR) - .addOperand(SrcOp); + .add(SrcOp); } ++StartIt; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonGenExtract.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonGenExtract.cpp index bb5e379ce014..c99ad5130aef 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonGenExtract.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonGenExtract.cpp @@ -197,13 +197,13 @@ bool HexagonGenExtract::convert(Instruction *In) { // It is still ok to generate extract, but only if the mask eliminates // those bits (i.e. M does not have any bits set beyond U). APInt C = APInt::getHighBitsSet(BW, BW-U); - if (M.intersects(C) || !APIntOps::isMask(W, M)) + if (M.intersects(C) || !M.isMask(W)) return false; } else { // Check if M starts with a contiguous sequence of W times 1 bits. Get // the low U bits of M (which eliminates the 0 bits shifted in on the // left), and check if the result is APInt's "mask": - if (!APIntOps::isMask(W, M.getLoBits(U))) + if (!M.getLoBits(U).isMask(W)) return false; } @@ -221,11 +221,8 @@ bool HexagonGenExtract::convert(Instruction *In) { bool HexagonGenExtract::visitBlock(BasicBlock *B) { // Depth-first, bottom-up traversal. - DomTreeNode *DTN = DT->getNode(B); - typedef GraphTraits<DomTreeNode*> GTN; - typedef GTN::ChildIteratorType Iter; - for (Iter I = GTN::child_begin(DTN), E = GTN::child_end(DTN); I != E; ++I) - visitBlock((*I)->getBlock()); + for (auto *DTN : children<DomTreeNode*>(DT->getNode(B))) + visitBlock(DTN->getBlock()); // Allow limiting the number of generated extracts for debugging purposes. bool HasCutoff = ExtractCutoff.getPosition(); diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp index 5a8e392d1275..54d99d399f88 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp @@ -947,11 +947,8 @@ void HexagonGenInsert::collectInBlock(MachineBasicBlock *B, BlockDefs.insert(InsDefs); } - MachineDomTreeNode *N = MDT->getNode(B); - typedef GraphTraits<MachineDomTreeNode*> GTN; - typedef GTN::ChildIteratorType ChildIter; - for (ChildIter I = GTN::child_begin(N), E = GTN::child_end(N); I != E; ++I) { - MachineBasicBlock *SB = (*I)->getBlock(); + for (auto *DTN : children<MachineDomTreeNode*>(MDT->getNode(B))) { + MachineBasicBlock *SB = DTN->getBlock(); collectInBlock(SB, AVs); } @@ -1422,9 +1419,9 @@ bool HexagonGenInsert::generateInserts() { bool HexagonGenInsert::removeDeadCode(MachineDomTreeNode *N) { bool Changed = false; - typedef GraphTraits<MachineDomTreeNode*> GTN; - for (auto I = GTN::child_begin(N), E = GTN::child_end(N); I != E; ++I) - Changed |= removeDeadCode(*I); + + for (auto *DTN : children<MachineDomTreeNode*>(N)) + Changed |= removeDeadCode(DTN); MachineBasicBlock *B = N->getBlock(); std::vector<MachineInstr*> Instrs; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonGenMux.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonGenMux.cpp index a718df9c70ab..85222944c77c 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonGenMux.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonGenMux.cpp @@ -324,9 +324,9 @@ bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) { if (!MxOpc) continue; BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR) - .addReg(MX.PredR) - .addOperand(*MX.SrcT) - .addOperand(*MX.SrcF); + .addReg(MX.PredR) + .add(*MX.SrcT) + .add(*MX.SrcF); B.erase(MX.Def1); B.erase(MX.Def2); Changed = true; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp index e477dcc0f64a..86a8089401c2 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -100,6 +100,7 @@ namespace { MachineRegisterInfo *MRI; MachineDominatorTree *MDT; const HexagonInstrInfo *TII; + const HexagonRegisterInfo *TRI; #ifndef NDEBUG static int Counter; #endif @@ -381,7 +382,9 @@ bool HexagonHardwareLoops::runOnMachineFunction(MachineFunction &MF) { MLI = &getAnalysis<MachineLoopInfo>(); MRI = &MF.getRegInfo(); MDT = &getAnalysis<MachineDominatorTree>(); - TII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo(); + const HexagonSubtarget &HST = MF.getSubtarget<HexagonSubtarget>(); + TII = HST.getInstrInfo(); + TRI = HST.getRegisterInfo(); for (auto &L : *MLI) if (!L->getParentLoop()) { @@ -960,24 +963,21 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop, /// \brief Return true if the operation is invalid within hardware loop. bool HexagonHardwareLoops::isInvalidLoopOperation(const MachineInstr *MI, bool IsInnerHWLoop) const { - // Call is not allowed because the callee may use a hardware loop except for // the case when the call never returns. if (MI->getDesc().isCall()) return !TII->doesNotReturn(*MI); // Check if the instruction defines a hardware loop register. - for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - const MachineOperand &MO = MI->getOperand(i); - if (!MO.isReg() || !MO.isDef()) - continue; - unsigned R = MO.getReg(); - if (IsInnerHWLoop && (R == Hexagon::LC0 || R == Hexagon::SA0 || - R == Hexagon::LC1 || R == Hexagon::SA1)) - return true; - if (!IsInnerHWLoop && (R == Hexagon::LC1 || R == Hexagon::SA1)) + using namespace Hexagon; + static const unsigned Regs01[] = { LC0, SA0, LC1, SA1 }; + static const unsigned Regs1[] = { LC1, SA1 }; + auto CheckRegs = IsInnerHWLoop ? makeArrayRef(Regs01, array_lengthof(Regs01)) + : makeArrayRef(Regs1, array_lengthof(Regs1)); + for (unsigned R : CheckRegs) + if (MI->modifiesRegister(R, TRI)) return true; - } + return false; } @@ -1511,7 +1511,7 @@ bool HexagonHardwareLoops::checkForImmediate(const MachineOperand &MO, int64_t V1, V2; if (!checkForImmediate(S1, V1) || !checkForImmediate(S2, V2)) return false; - TV = V2 | (V1 << 32); + TV = V2 | (static_cast<uint64_t>(V1) << 32); break; } case TargetOpcode::REG_SEQUENCE: { diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonIICHVX.td b/contrib/llvm/lib/Target/Hexagon/HexagonIICHVX.td new file mode 100644 index 000000000000..4081a225832b --- /dev/null +++ b/contrib/llvm/lib/Target/Hexagon/HexagonIICHVX.td @@ -0,0 +1,102 @@ +//===--- HexagonIICHVX.td -------------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +// +// Though all these itinerary classes exist for V60 onwards, they are being +// listed here as 'HVXV62Itin' because itinerary class description prior to V62 +// doesn't include operand cycle info. In future, I plan to merge them +// together and call it 'HVXItin'. +// +class HVXV62Itin { + list<InstrItinData> HVXV62Itin_list = [ + InstrItinData<COPROC_VMEM_vtc_long_SLOT01, + [InstrStage<1, [SLOT0, SLOT1]>], + [3, 1, 1, 1]>, + InstrItinData<COPROC_VX_vtc_long_SLOT23, + [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1, 1]>, + InstrItinData<COPROC_VX_vtc_SLOT23, + [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1, 1]>, + InstrItinData<CVI_VA, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, + InstrStage<1, [CVI_XLANE,CVI_SHIFT, + CVI_MPY0, CVI_MPY1]>], + [1, 1, 1, 1]>, + InstrItinData<CVI_VA_DV, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, + InstrStage<1, [CVI_XLSHF, CVI_MPY01]>], + [1, 1, 1, 1]>, + InstrItinData<CVI_VX_LONG, [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], + [1, 1, 1, 1]>, + InstrItinData<CVI_VX_LATE, [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], + [1, 1, 1, 1]>, + InstrItinData<CVI_VX, [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY0, CVI_MPY1]>], + [1, 1, 1, 1]>, + InstrItinData<CVI_VX_DV_LONG, [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01]>], [1, 1, 1, 1]>, + InstrItinData<CVI_VX_DV, [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [CVI_MPY01]>], [1, 1, 1, 1]>, + InstrItinData<CVI_VX_DV_SLOT2, [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_MPY01]>], [1, 1, 1, 1]>, + InstrItinData<CVI_VX_DV_SLOT2_LONG_EARLY, + [InstrStage<1, [SLOT2], 0>, + InstrStage<1, [CVI_MPY01]>], [1, 1, 1, 1]>, + InstrItinData<CVI_VP, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, + InstrStage<1, [CVI_XLANE]>], [1, 1, 1, 1]>, + InstrItinData<CVI_VP_LONG, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, + InstrStage<1, [CVI_XLANE]>], [1, 1, 1, 1]>, + InstrItinData<CVI_VP_VS_EARLY, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, + InstrStage<1, [CVI_XLSHF]>], [1, 1, 1, 1]>, + InstrItinData<CVI_VP_VS_LONG, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, + InstrStage<1, [CVI_XLSHF]>], [1, 1, 1, 1]>, + InstrItinData<CVI_VP_VS, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, + InstrStage<1, [CVI_XLSHF]>], [1, 1, 1, 1]>, + InstrItinData<CVI_VP_VS_LONG_EARLY, + [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, + InstrStage<1, [CVI_XLSHF]>], [1, 1, 1, 1]>, + InstrItinData<CVI_VP_DV, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, + InstrStage<1, [CVI_XLSHF]>], [1, 1, 1, 1]>, + InstrItinData<CVI_VS, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, + InstrStage<1, [CVI_SHIFT]>], [1, 1, 1, 1]>, + InstrItinData<CVI_VINLANESAT, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, + InstrStage<1, [CVI_XLANE, CVI_SHIFT, + CVI_MPY0, CVI_MPY1]>], + [1, 1, 1, 1]>, + InstrItinData<CVI_VM_LD, [InstrStage<1, [SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_XLANE, CVI_SHIFT, + CVI_MPY0, CVI_MPY1]>], + [1, 1, 1, 1]>, + InstrItinData<CVI_VM_TMP_LD, [InstrStage<1,[SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_LD]>],[1, 1, 1, 1, 10]>, + InstrItinData<CVI_VM_CUR_LD, [InstrStage<1,[SLOT0, SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_XLANE, CVI_SHIFT, + CVI_MPY0, CVI_MPY1]>], + [1, 1, 1, 1]>, + InstrItinData<CVI_VM_VP_LDU, [InstrStage<1,[SLOT0], 0>, + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_LD], 0>, + InstrStage<1, [CVI_XLANE]>], [1, 1, 1, 1]>, + InstrItinData<CVI_VM_ST, [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_XLANE, CVI_SHIFT, + CVI_MPY0, CVI_MPY1]>], + [1, 1, 1, 1]>, + InstrItinData<CVI_VM_NEW_ST, [InstrStage<1,[SLOT0], 0>, + InstrStage<1, [CVI_ST]>], [1, 1, 1, 1]>, + InstrItinData<CVI_VM_STU, [InstrStage<1, [SLOT0], 0>, + InstrStage<1, [SLOT1], 0>, + InstrStage<1, [CVI_ST], 0>, + InstrStage<1, [CVI_XLANE]>], [1, 1, 1, 1]>, + InstrItinData<CVI_HIST, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>, + InstrStage<1, [CVI_ALL]>], [1, 1, 1, 1]>]; +} diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonIICScalar.td b/contrib/llvm/lib/Target/Hexagon/HexagonIICScalar.td new file mode 100644 index 000000000000..e69cfbdad688 --- /dev/null +++ b/contrib/llvm/lib/Target/Hexagon/HexagonIICScalar.td @@ -0,0 +1,164 @@ +//===--- HexagonIICScalar.td ----------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +// These itinerary class descriptions are based on the instruction timing +// classes as per V62. Curretnly, they are just extracted from +// HexagonScheduleV62.td but will soon be auto-generated by HexagonGen.py. + +class ScalarItin { + list<InstrItinData> ScalarItin_list = [ + InstrItinData<ALU32_2op_tc_1_SLOT0123 , + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>, + InstrItinData<ALU32_2op_tc_2early_SLOT0123, + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>, + InstrItinData<ALU32_3op_tc_1_SLOT0123 , + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>, + InstrItinData<ALU32_3op_tc_2_SLOT0123 , + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>, + InstrItinData<ALU32_3op_tc_2early_SLOT0123, + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>, + InstrItinData<ALU32_ADDI_tc_1_SLOT0123 , + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>, + + // ALU64 + InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [1, 1, 1]>, + InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1]>, + InstrItinData<ALU64_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1]>, + InstrItinData<ALU64_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1]>, + + // CR -> System + InstrItinData<CR_tc_2_SLOT3 , [InstrStage<1, [SLOT3]>], [2, 1, 1]>, + InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<1, [SLOT3]>], [2, 1, 1]>, + InstrItinData<CR_tc_3x_SLOT3 , [InstrStage<1, [SLOT3]>], [3, 1, 1]>, + + // Jump (conditional/unconditional/return etc) + InstrItinData<CR_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1, 1]>, + InstrItinData<CR_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1, 1]>, + InstrItinData<CJ_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [1, 1, 1, 1]>, + InstrItinData<CJ_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1, 1]>, + InstrItinData<J_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1, 1]>, + InstrItinData<J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1, 1]>, + + // JR + InstrItinData<J_tc_2early_SLOT2 , [InstrStage<1, [SLOT2]>], [2, 1, 1]>, + InstrItinData<J_tc_3stall_SLOT2 , [InstrStage<1, [SLOT2]>], [3, 1, 1]>, + + // Extender + InstrItinData<EXTENDER_tc_1_SLOT0123, [InstrStage<1, + [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1, 1]>, + + // Load + InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], + [3, 1]>, + InstrItinData<LD_tc_ld_pi_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], + [3, 1]>, + InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<1, [SLOT0]>], [4, 1]>, + InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>], [3, 1]>, + + // M + InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [1, 1, 1]>, + InstrItinData<M_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1]>, + InstrItinData<M_tc_2_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1]>, + InstrItinData<M_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1]>, + InstrItinData<M_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1]>, + InstrItinData<M_tc_3x_acc_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1, 1]>, + InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [4, 1, 1]>, + InstrItinData<M_tc_3or4x_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [4, 1, 1]>, + InstrItinData<M_tc_3stall_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1]>, + + // Store + InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], + [1, 1, 1]>, + InstrItinData<ST_tc_st_pi_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>], + [1, 1, 1]>, + InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<1, [SLOT0]>], [3, 1, 1]>, + InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>], [3, 1, 1]>, + InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>], [1, 1, 1]>, + InstrItinData<ST_tc_st_pi_SLOT0 , [InstrStage<1, [SLOT0]>], [1, 1, 1]>, + + // S + InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [1, 1, 1]>, + InstrItinData<S_2op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1]>, + InstrItinData<S_2op_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1]>, + // The S_2op_tc_3x_SLOT23 slots are 4 cycles on v60. + InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [4, 1, 1]>, + InstrItinData<S_3op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [1, 1, 1]>, + InstrItinData<S_3op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1]>, + InstrItinData<S_3op_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1]>, + InstrItinData<S_3op_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1]>, + InstrItinData<S_3op_tc_3stall_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1]>, + InstrItinData<S_3op_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1]>, + + // New Value Compare Jump + InstrItinData<NCJ_tc_3or4stall_SLOT0, [InstrStage<1, [SLOT0]>], + [3, 1, 1, 1]>, + + // Mem ops + InstrItinData<V2LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>], + [1, 1, 1, 1]>, + InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], + [2, 1, 1, 1]>, + InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], + [1, 1, 1, 1]>, + InstrItinData<V4LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>], + [1, 1, 1, 1]>, + InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], + [3, 1, 1, 1]>, + InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], + [1, 1, 1, 1]>, + + // Endloop + InstrItinData<J_tc_2early_SLOT0123, [InstrStage<1, [SLOT_ENDLOOP]>], + [2]>, + InstrItinData<MAPPING_tc_1_SLOT0123 , + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], + [1, 1, 1, 1]>, + + // Duplex and Compound + InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>], [1, 1, 1]>, + InstrItinData<COMPOUND_CJ_ARCHDEPSLOT, + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>, + InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>, + // Misc + InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], + [1, 1, 1]>, + InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], + [1, 1, 1]>, + InstrItinData<PSEUDOM , [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>]; +} diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index f6012d29d422..8e10c521a77d 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -123,6 +123,12 @@ private: bool isAlignedMemNode(const MemSDNode *N) const; bool isPositiveHalfWord(const SDNode *N) const; + // DAG preprocessing functions. + void ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes); + void ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes); + void ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes); + void ppHoistZextI1(std::vector<SDNode*> &&Nodes); + SmallDenseMap<SDNode *,int> RootWeights; SmallDenseMap<SDNode *,int> RootHeights; SmallDenseMap<const Value *,int> GAUsesInFunction; @@ -932,55 +938,21 @@ void HexagonDAGToDAGISel::SelectBitcast(SDNode *N) { void HexagonDAGToDAGISel::Select(SDNode *N) { - if (N->isMachineOpcode()) { - N->setNodeId(-1); - return; // Already selected. - } + if (N->isMachineOpcode()) + return N->setNodeId(-1); // Already selected. switch (N->getOpcode()) { - case ISD::Constant: - SelectConstant(N); - return; - - case ISD::ConstantFP: - SelectConstantFP(N); - return; - - case ISD::FrameIndex: - SelectFrameIndex(N); - return; - - case ISD::BITCAST: - SelectBitcast(N); - return; - - case ISD::SHL: - SelectSHL(N); - return; - - case ISD::LOAD: - SelectLoad(N); - return; - - case ISD::STORE: - SelectStore(N); - return; - - case ISD::MUL: - SelectMul(N); - return; - - case ISD::ZERO_EXTEND: - SelectZeroExtend(N); - return; - - case ISD::INTRINSIC_W_CHAIN: - SelectIntrinsicWChain(N); - return; - - case ISD::INTRINSIC_WO_CHAIN: - SelectIntrinsicWOChain(N); - return; + case ISD::Constant: return SelectConstant(N); + case ISD::ConstantFP: return SelectConstantFP(N); + case ISD::FrameIndex: return SelectFrameIndex(N); + case ISD::BITCAST: return SelectBitcast(N); + case ISD::SHL: return SelectSHL(N); + case ISD::LOAD: return SelectLoad(N); + case ISD::STORE: return SelectStore(N); + case ISD::MUL: return SelectMul(N); + case ISD::ZERO_EXTEND: return SelectZeroExtend(N); + case ISD::INTRINSIC_W_CHAIN: return SelectIntrinsicWChain(N); + case ISD::INTRINSIC_WO_CHAIN: return SelectIntrinsicWOChain(N); } SelectCode(N); @@ -1010,15 +982,52 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, } -void HexagonDAGToDAGISel::PreprocessISelDAG() { +static bool isMemOPCandidate(SDNode *I, SDNode *U) { + // I is an operand of U. Check if U is an arithmetic (binary) operation + // usable in a memop, where the other operand is a loaded value, and the + // result of U is stored in the same location. + + if (!U->hasOneUse()) + return false; + unsigned Opc = U->getOpcode(); + switch (Opc) { + case ISD::ADD: + case ISD::SUB: + case ISD::AND: + case ISD::OR: + break; + default: + return false; + } + + SDValue S0 = U->getOperand(0); + SDValue S1 = U->getOperand(1); + SDValue SY = (S0.getNode() == I) ? S1 : S0; + + SDNode *UUse = *U->use_begin(); + if (UUse->getNumValues() != 1) + return false; + + // Check if one of the inputs to U is a load instruction and the output + // is used by a store instruction. If so and they also have the same + // base pointer, then don't preoprocess this node sequence as it + // can be matched to a memop. + SDNode *SYNode = SY.getNode(); + if (UUse->getOpcode() == ISD::STORE && SYNode->getOpcode() == ISD::LOAD) { + SDValue LDBasePtr = cast<MemSDNode>(SYNode)->getBasePtr(); + SDValue STBasePtr = cast<MemSDNode>(UUse)->getBasePtr(); + if (LDBasePtr == STBasePtr) + return true; + } + return false; +} + + +// Transform: (or (select c x 0) z) -> (select c (or x z) z) +// (or (select c 0 y) z) -> (select c z (or y z)) +void HexagonDAGToDAGISel::ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes) { SelectionDAG &DAG = *CurDAG; - std::vector<SDNode*> Nodes; - for (SDNode &Node : DAG.allnodes()) - Nodes.push_back(&Node); - // Simplify: (or (select c x 0) z) -> (select c (or x z) z) - // (or (select c 0 y) z) -> (select c z (or y z)) - // This may not be the right thing for all targets, so do it here. for (auto I : Nodes) { if (I->getOpcode() != ISD::OR) continue; @@ -1056,18 +1065,22 @@ void HexagonDAGToDAGISel::PreprocessISelDAG() { } } } +} + +// Transform: (store ch val (add x (add (shl y c) e))) +// to: (store ch val (add x (shl (add y d) c))), +// where e = (shl d c) for some integer d. +// The purpose of this is to enable generation of loads/stores with +// shifted addressing mode, i.e. mem(x+y<<#c). For that, the shift +// value c must be 0, 1 or 2. +void HexagonDAGToDAGISel::ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes) { + SelectionDAG &DAG = *CurDAG; - // Transform: (store ch addr (add x (add (shl y c) e))) - // to: (store ch addr (add x (shl (add y d) c))), - // where e = (shl d c) for some integer d. - // The purpose of this is to enable generation of loads/stores with - // shifted addressing mode, i.e. mem(x+y<<#c). For that, the shift - // value c must be 0, 1 or 2. for (auto I : Nodes) { if (I->getOpcode() != ISD::STORE) continue; - // I matched: (store ch addr Off) + // I matched: (store ch val Off) SDValue Off = I->getOperand(2); // Off needs to match: (add x (add (shl y c) (shl d c)))) if (Off.getOpcode() != ISD::ADD) @@ -1109,15 +1122,192 @@ void HexagonDAGToDAGISel::PreprocessISelDAG() { SDValue NewShl = DAG.getNode(ISD::SHL, DL, VT, NewAdd, C); ReplaceNode(T0.getNode(), NewShl.getNode()); } +} + +// Transform: (load ch (add x (and (srl y c) Mask))) +// to: (load ch (add x (shl (srl y d) d-c))) +// where +// Mask = 00..0 111..1 0.0 +// | | +-- d-c 0s, and d-c is 0, 1 or 2. +// | +-------- 1s +// +-------------- at most c 0s +// Motivating example: +// DAG combiner optimizes (add x (shl (srl y 5) 2)) +// to (add x (and (srl y 3) 1FFFFFFC)) +// which results in a constant-extended and(##...,lsr). This transformation +// undoes this simplification for cases where the shl can be folded into +// an addressing mode. +void HexagonDAGToDAGISel::ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes) { + SelectionDAG &DAG = *CurDAG; + + for (SDNode *N : Nodes) { + unsigned Opc = N->getOpcode(); + if (Opc != ISD::LOAD && Opc != ISD::STORE) + continue; + SDValue Addr = Opc == ISD::LOAD ? N->getOperand(1) : N->getOperand(2); + // Addr must match: (add x T0) + if (Addr.getOpcode() != ISD::ADD) + continue; + SDValue T0 = Addr.getOperand(1); + // T0 must match: (and T1 Mask) + if (T0.getOpcode() != ISD::AND) + continue; + + // We have an AND. + // + // Check the first operand. It must be: (srl y c). + SDValue S = T0.getOperand(0); + if (S.getOpcode() != ISD::SRL) + continue; + ConstantSDNode *SN = dyn_cast<ConstantSDNode>(S.getOperand(1).getNode()); + if (SN == nullptr) + continue; + if (SN->getAPIntValue().getBitWidth() != 32) + continue; + uint32_t CV = SN->getZExtValue(); + + // Check the second operand: the supposed mask. + ConstantSDNode *MN = dyn_cast<ConstantSDNode>(T0.getOperand(1).getNode()); + if (MN == nullptr) + continue; + if (MN->getAPIntValue().getBitWidth() != 32) + continue; + uint32_t Mask = MN->getZExtValue(); + // Examine the mask. + uint32_t TZ = countTrailingZeros(Mask); + uint32_t M1 = countTrailingOnes(Mask >> TZ); + uint32_t LZ = countLeadingZeros(Mask); + // Trailing zeros + middle ones + leading zeros must equal the width. + if (TZ + M1 + LZ != 32) + continue; + // The number of trailing zeros will be encoded in the addressing mode. + if (TZ > 2) + continue; + // The number of leading zeros must be at most c. + if (LZ > CV) + continue; + + // All looks good. + SDValue Y = S.getOperand(0); + EVT VT = Addr.getValueType(); + SDLoc dl(S); + // TZ = D-C, so D = TZ+C. + SDValue D = DAG.getConstant(TZ+CV, dl, VT); + SDValue DC = DAG.getConstant(TZ, dl, VT); + SDValue NewSrl = DAG.getNode(ISD::SRL, dl, VT, Y, D); + SDValue NewShl = DAG.getNode(ISD::SHL, dl, VT, NewSrl, DC); + ReplaceNode(T0.getNode(), NewShl.getNode()); + } +} + +// Transform: (op ... (zext i1 c) ...) -> (select c (op ... 0 ...) +// (op ... 1 ...)) +void HexagonDAGToDAGISel::ppHoistZextI1(std::vector<SDNode*> &&Nodes) { + SelectionDAG &DAG = *CurDAG; + + for (SDNode *N : Nodes) { + unsigned Opc = N->getOpcode(); + if (Opc != ISD::ZERO_EXTEND) + continue; + SDValue OpI1 = N->getOperand(0); + EVT OpVT = OpI1.getValueType(); + if (!OpVT.isSimple() || OpVT.getSimpleVT() != MVT::i1) + continue; + for (auto I = N->use_begin(), E = N->use_end(); I != E; ++I) { + SDNode *U = *I; + if (U->getNumValues() != 1) + continue; + EVT UVT = U->getValueType(0); + if (!UVT.isSimple() || !UVT.isInteger() || UVT.getSimpleVT() == MVT::i1) + continue; + if (isMemOPCandidate(N, U)) + continue; + + // Potentially simplifiable operation. + unsigned I1N = I.getOperandNo(); + SmallVector<SDValue,2> Ops(U->getNumOperands()); + for (unsigned i = 0, n = U->getNumOperands(); i != n; ++i) + Ops[i] = U->getOperand(i); + EVT BVT = Ops[I1N].getValueType(); + + SDLoc dl(U); + SDValue C0 = DAG.getConstant(0, dl, BVT); + SDValue C1 = DAG.getConstant(1, dl, BVT); + SDValue If0, If1; + + if (isa<MachineSDNode>(U)) { + unsigned UseOpc = U->getMachineOpcode(); + Ops[I1N] = C0; + If0 = SDValue(DAG.getMachineNode(UseOpc, dl, UVT, Ops), 0); + Ops[I1N] = C1; + If1 = SDValue(DAG.getMachineNode(UseOpc, dl, UVT, Ops), 0); + } else { + unsigned UseOpc = U->getOpcode(); + Ops[I1N] = C0; + If0 = DAG.getNode(UseOpc, dl, UVT, Ops); + Ops[I1N] = C1; + If1 = DAG.getNode(UseOpc, dl, UVT, Ops); + } + SDValue Sel = DAG.getNode(ISD::SELECT, dl, UVT, OpI1, If1, If0); + DAG.ReplaceAllUsesWith(U, Sel.getNode()); + } + } +} + +void HexagonDAGToDAGISel::PreprocessISelDAG() { + // Repack all nodes before calling each preprocessing function, + // because each of them can modify the set of nodes. + auto getNodes = [this] () -> std::vector<SDNode*> { + std::vector<SDNode*> T; + T.reserve(CurDAG->allnodes_size()); + for (SDNode &N : CurDAG->allnodes()) + T.push_back(&N); + return T; + }; + + // Transform: (or (select c x 0) z) -> (select c (or x z) z) + // (or (select c 0 y) z) -> (select c z (or y z)) + ppSimplifyOrSelect0(getNodes()); + + // Transform: (store ch val (add x (add (shl y c) e))) + // to: (store ch val (add x (shl (add y d) c))), + // where e = (shl d c) for some integer d. + // The purpose of this is to enable generation of loads/stores with + // shifted addressing mode, i.e. mem(x+y<<#c). For that, the shift + // value c must be 0, 1 or 2. + ppAddrReorderAddShl(getNodes()); + + // Transform: (load ch (add x (and (srl y c) Mask))) + // to: (load ch (add x (shl (srl y d) d-c))) + // where + // Mask = 00..0 111..1 0.0 + // | | +-- d-c 0s, and d-c is 0, 1 or 2. + // | +-------- 1s + // +-------------- at most c 0s + // Motivating example: + // DAG combiner optimizes (add x (shl (srl y 5) 2)) + // to (add x (and (srl y 3) 1FFFFFFC)) + // which results in a constant-extended and(##...,lsr). This transformation + // undoes this simplification for cases where the shl can be folded into + // an addressing mode. + ppAddrRewriteAndSrl(getNodes()); + + // Transform: (op ... (zext i1 c) ...) -> (select c (op ... 0 ...) + // (op ... 1 ...)) + ppHoistZextI1(getNodes()); + + DEBUG_WITH_TYPE("isel", { + dbgs() << "Preprocessed (Hexagon) selection DAG:"; + CurDAG->dump(); + }); if (EnableAddressRebalancing) { rebalanceAddressTrees(); - DEBUG( - dbgs() << "************* SelectionDAG after preprocessing: ***********\n"; + DEBUG_WITH_TYPE("isel", { + dbgs() << "Address tree balanced selection DAG:"; CurDAG->dump(); - dbgs() << "************* End SelectionDAG after preprocessing ********\n"; - ); + }); } } diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp index e87e1e6a7e0f..418dd71aeb4b 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -256,7 +256,9 @@ static bool CC_Hexagon (unsigned ValNo, MVT ValVT, MVT LocVT, return false; } - if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) { + if (LocVT == MVT::i1) { + LocVT = MVT::i32; + } else if (LocVT == MVT::i8 || LocVT == MVT::i16) { LocVT = MVT::i32; ValVT = MVT::i32; if (ArgFlags.isSExt()) @@ -483,9 +485,7 @@ static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT, } } - unsigned Offset = State.AllocateStack(4, 4); - State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); - return false; + return true; } static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT, @@ -498,9 +498,7 @@ static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT, } } - unsigned Offset = State.AllocateStack(8, 8); - State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); - return false; + return true; } static bool RetCC_HexagonVector(unsigned ValNo, MVT ValVT, @@ -511,7 +509,6 @@ static bool RetCC_HexagonVector(unsigned ValNo, MVT ValVT, bool UseHVX = HST.useHVXOps(); bool UseHVXDbl = HST.useHVXDblOps(); - unsigned OffSiz = 64; if (LocVT == MVT::v16i32) { if (unsigned Reg = State.AllocateReg(Hexagon::V0)) { State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); @@ -523,18 +520,14 @@ static bool RetCC_HexagonVector(unsigned ValNo, MVT ValVT, State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); return false; } - OffSiz = 128; } else if (LocVT == MVT::v64i32) { if (unsigned Reg = State.AllocateReg(Hexagon::W0)) { State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); return false; } - OffSiz = 256; } - unsigned Offset = State.AllocateStack(OffSiz, OffSiz); - State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); - return false; + return true; } void HexagonTargetLowering::promoteLdStType(MVT VT, MVT PromotedLdStVT) { @@ -590,6 +583,16 @@ static bool isHvxVectorType(MVT Ty) { } } +bool +HexagonTargetLowering::CanLowerReturn( + CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, + const SmallVectorImpl<ISD::OutputArg> &Outs, + LLVMContext &Context) const { + SmallVector<CCValAssign, 16> RVLocs; + CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); + return CCInfo.CheckReturn(Outs, RetCC_Hexagon); +} + // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is // passed by value, the function prototype is modified to return void and // the value is stored in memory pointed by a pointer passed by caller. @@ -644,11 +647,11 @@ bool HexagonTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { /// LowerCallResult - Lower the result values of an ISD::CALL into the /// appropriate copies out of appropriate physical registers. This assumes that -/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call +/// Chain/Glue are the input chain/glue to use, and that TheCall is the call /// being lowered. Returns a SDNode with the same number of values as the /// ISD::CALL. SDValue HexagonTargetLowering::LowerCallResult( - SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, + SDValue Chain, SDValue Glue, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const { @@ -671,21 +674,24 @@ SDValue HexagonTargetLowering::LowerCallResult( // predicate register as the call result. auto &MRI = DAG.getMachineFunction().getRegInfo(); SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), - MVT::i32, InFlag); + MVT::i32, Glue); // FR0 = (Value, Chain, Glue) unsigned PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass); SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR, FR0.getValue(0), FR0.getValue(2)); // TPR = (Chain, Glue) - RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1, - TPR.getValue(1)); + // Don't glue this CopyFromReg, because it copies from a virtual + // register. If it is glued to the call, InstrEmitter will add it + // as an implicit def to the call (EmitMachineNode). + RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1); + Glue = TPR.getValue(1); } else { RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), - RVLocs[i].getValVT(), InFlag); + RVLocs[i].getValVT(), Glue); + Glue = RetVal.getValue(2); } InVals.push_back(RetVal.getValue(0)); Chain = RetVal.getValue(1); - InFlag = RetVal.getValue(2); } return Chain; @@ -840,16 +846,17 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, if (!MemOpChains.empty()) Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); + SDValue Glue; if (!IsTailCall) { SDValue C = DAG.getConstant(NumBytes, dl, PtrVT, true); Chain = DAG.getCALLSEQ_START(Chain, C, dl); + Glue = Chain.getValue(1); } // Build a sequence of copy-to-reg nodes chained together with token // chain and flag operands which copy the outgoing args into registers. // The Glue is necessary since all emitted instructions must be // stuck together. - SDValue Glue; if (!IsTailCall) { for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, @@ -902,6 +909,10 @@ HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, RegsToPass[i].second.getValueType())); } + const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallConv); + assert(Mask && "Missing call preserved mask for calling convention"); + Ops.push_back(DAG.getRegisterMask(Mask)); + if (Glue.getNode()) Ops.push_back(Glue); @@ -1054,6 +1065,18 @@ SDValue HexagonTargetLowering::LowerPREFETCH(SDValue Op, return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero); } +// Custom-handle ISD::READCYCLECOUNTER because the target-independent SDNode +// is marked as having side-effects, while the register read on Hexagon does +// not have any. TableGen refuses to accept the direct pattern from that node +// to the A4_tfrcpp. +SDValue HexagonTargetLowering::LowerREADCYCLECOUNTER(SDValue Op, + SelectionDAG &DAG) const { + SDValue Chain = Op.getOperand(0); + SDLoc dl(Op); + SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other); + return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain); +} + SDValue HexagonTargetLowering::LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const { SDValue Chain = Op.getOperand(0); @@ -1140,10 +1163,25 @@ SDValue HexagonTargetLowering::LowerFormalArguments( EVT RegVT = VA.getLocVT(); if (RegVT == MVT::i8 || RegVT == MVT::i16 || RegVT == MVT::i32 || RegVT == MVT::f32) { - unsigned VReg = + unsigned VReg = RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); - InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); + SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); + // Treat values of type MVT::i1 specially: they are passed in + // registers of type i32, but they need to remain as values of + // type i1 for consistency of the argument lowering. + if (VA.getValVT() == MVT::i1) { + // Generate a copy into a predicate register and use the value + // of the register as the "InVal". + unsigned PReg = + RegInfo.createVirtualRegister(&Hexagon::PredRegsRegClass); + SDNode *T = DAG.getMachineNode(Hexagon::C2_tfrrp, dl, MVT::i1, + Copy.getValue(0)); + Copy = DAG.getCopyToReg(Copy.getValue(1), dl, PReg, SDValue(T, 0)); + Copy = DAG.getCopyFromReg(Copy, dl, PReg, MVT::i1); + } + InVals.push_back(Copy); + Chain = Copy.getValue(1); } else if (RegVT == MVT::i64 || RegVT == MVT::f64) { unsigned VReg = RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass); @@ -1217,7 +1255,7 @@ SDValue HexagonTargetLowering::LowerFormalArguments( InVals.push_back(FIN); } else { InVals.push_back( - DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, MachinePointerInfo())); + DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo())); } } } @@ -1272,17 +1310,6 @@ static bool isSExtFree(SDValue N) { return false; } -SDValue HexagonTargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const { - SDLoc dl(Op); - SDValue InpVal = Op.getOperand(0); - if (isa<ConstantSDNode>(InpVal)) { - uint64_t V = cast<ConstantSDNode>(InpVal)->getZExtValue(); - return DAG.getTargetConstant(countPopulation(V), dl, MVT::i64); - } - SDValue PopOut = DAG.getNode(HexagonISD::POPCOUNT, dl, MVT::i32, InpVal); - return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, PopOut); -} - SDValue HexagonTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { SDLoc dl(Op); @@ -1571,9 +1598,10 @@ HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) SDValue HexagonTargetLowering::GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, - GlobalAddressSDNode *GA, SDValue *InFlag, EVT PtrVT, unsigned ReturnReg, + GlobalAddressSDNode *GA, SDValue Glue, EVT PtrVT, unsigned ReturnReg, unsigned char OperandFlags) const { - MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); SDLoc dl(GA); SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, @@ -1585,23 +1613,21 @@ HexagonTargetLowering::GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, // 2. Callee which in this case is the Global address value. // 3. Registers live into the call.In this case its R0, as we // have just one argument to be passed. - // 4. InFlag if there is any. + // 4. Glue. // Note: The order is important. - if (InFlag) { - SDValue Ops[] = { Chain, TGA, - DAG.getRegister(Hexagon::R0, PtrVT), *InFlag }; - Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops); - } else { - SDValue Ops[] = { Chain, TGA, DAG.getRegister(Hexagon::R0, PtrVT)}; - Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops); - } + const auto &HRI = *Subtarget.getRegisterInfo(); + const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallingConv::C); + assert(Mask && "Missing call preserved mask for calling convention"); + SDValue Ops[] = { Chain, TGA, DAG.getRegister(Hexagon::R0, PtrVT), + DAG.getRegisterMask(Mask), Glue }; + Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops); // Inform MFI that function has calls. MFI.setAdjustsStack(true); - SDValue Flag = Chain.getValue(1); - return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); + Glue = Chain.getValue(1); + return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Glue); } // @@ -1694,7 +1720,7 @@ HexagonTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InFlag); InFlag = Chain.getValue(1); - return GetDynamicTLSAddr(DAG, Chain, GA, &InFlag, PtrVT, + return GetDynamicTLSAddr(DAG, Chain, GA, InFlag, PtrVT, Hexagon::R0, HexagonII::MO_GDPLT); } @@ -1821,6 +1847,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); setOperationAction(ISD::INLINEASM, MVT::Other, Custom); setOperationAction(ISD::PREFETCH, MVT::Other, Custom); + setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom); setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); @@ -1891,7 +1918,12 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, setOperationAction(ISD::CTPOP, MVT::i8, Promote); setOperationAction(ISD::CTPOP, MVT::i16, Promote); setOperationAction(ISD::CTPOP, MVT::i32, Promote); - setOperationAction(ISD::CTPOP, MVT::i64, Custom); + setOperationAction(ISD::CTPOP, MVT::i64, Legal); + + setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); + setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); + setOperationAction(ISD::BSWAP, MVT::i32, Legal); + setOperationAction(ISD::BSWAP, MVT::i64, Legal); // We custom lower i64 to i64 mul, so that it is not considered as a legal // operation. There is a pattern that will match i64 mul and transform it @@ -1901,7 +1933,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM, for (unsigned IntExpOp : { ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR, - ISD::BSWAP, ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS, + ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS, ISD::SMUL_LOHI, ISD::UMUL_LOHI }) { setOperationAction(IntExpOp, MVT::i32, Expand); setOperationAction(IntExpOp, MVT::i64, Expand); @@ -2268,7 +2300,6 @@ const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const { case HexagonISD::INSERTRP: return "HexagonISD::INSERTRP"; case HexagonISD::JT: return "HexagonISD::JT"; case HexagonISD::PACKHL: return "HexagonISD::PACKHL"; - case HexagonISD::POPCOUNT: return "HexagonISD::POPCOUNT"; case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG"; case HexagonISD::SHUFFEB: return "HexagonISD::SHUFFEB"; case HexagonISD::SHUFFEH: return "HexagonISD::SHUFFEH"; @@ -2296,6 +2327,7 @@ const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const { case HexagonISD::VSRLW: return "HexagonISD::VSRLW"; case HexagonISD::VSXTBH: return "HexagonISD::VSXTBH"; case HexagonISD::VSXTBW: return "HexagonISD::VSXTBW"; + case HexagonISD::READCYCLE: return "HexagonISD::READCYCLE"; case HexagonISD::OP_END: break; } return nullptr; @@ -2968,11 +3000,11 @@ HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); case ISD::SETCC: return LowerSETCC(Op, DAG); case ISD::VSELECT: return LowerVSELECT(Op, DAG); - case ISD::CTPOP: return LowerCTPOP(Op, DAG); case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG); case ISD::INLINEASM: return LowerINLINEASM(Op, DAG); case ISD::PREFETCH: return LowerPREFETCH(Op, DAG); + case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); } } @@ -3026,37 +3058,25 @@ HexagonTargetLowering::getRegForInlineAsmConstraint( return std::make_pair(0U, &Hexagon::DoubleRegsRegClass); } case 'q': // q0-q3 - switch (VT.SimpleTy) { + switch (VT.getSizeInBits()) { default: - llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type"); - case MVT::v1024i1: - case MVT::v512i1: - case MVT::v32i16: - case MVT::v16i32: - case MVT::v64i8: - case MVT::v8i64: + llvm_unreachable("getRegForInlineAsmConstraint Unhandled vector size"); + case 512: return std::make_pair(0U, &Hexagon::VecPredRegsRegClass); + case 1024: + return std::make_pair(0U, &Hexagon::VecPredRegs128BRegClass); } case 'v': // V0-V31 - switch (VT.SimpleTy) { + switch (VT.getSizeInBits()) { default: - llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type"); - case MVT::v16i32: - case MVT::v32i16: - case MVT::v64i8: - case MVT::v8i64: + llvm_unreachable("getRegForInlineAsmConstraint Unhandled vector size"); + case 512: return std::make_pair(0U, &Hexagon::VectorRegsRegClass); - case MVT::v32i32: - case MVT::v64i16: - case MVT::v16i64: - case MVT::v128i8: + case 1024: if (Subtarget.hasV60TOps() && UseHVX && UseHVXDbl) return std::make_pair(0U, &Hexagon::VectorRegs128BRegClass); return std::make_pair(0U, &Hexagon::VecDblRegsRegClass); - case MVT::v256i8: - case MVT::v128i16: - case MVT::v64i32: - case MVT::v32i64: + case 2048: return std::make_pair(0U, &Hexagon::VecDblRegs128BRegClass); } diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/contrib/llvm/lib/Target/Hexagon/HexagonISelLowering.h index a8ed29e585d4..fb8f0ba6b057 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/contrib/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -50,7 +50,6 @@ namespace HexagonISD { JT, // Jump table. CP, // Constant pool. - POPCOUNT, COMBINE, PACKHL, VSPLATB, @@ -86,6 +85,7 @@ namespace HexagonISD { TC_RETURN, EH_RETURN, DCFETCH, + READCYCLE, OP_END }; @@ -146,6 +146,7 @@ namespace HexagonISD { SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const; SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const; SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const; SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; SDValue @@ -163,7 +164,7 @@ namespace HexagonISD { SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const; SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, - GlobalAddressSDNode *GA, SDValue *InFlag, EVT PtrVT, + GlobalAddressSDNode *GA, SDValue InFlag, EVT PtrVT, unsigned ReturnReg, unsigned char OperandFlags) const; SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; @@ -179,12 +180,16 @@ namespace HexagonISD { SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; + bool CanLowerReturn(CallingConv::ID CallConv, + MachineFunction &MF, bool isVarArg, + const SmallVectorImpl<ISD::OutputArg> &Outs, + LLVMContext &Context) const override; + SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonInstrAlias.td b/contrib/llvm/lib/Target/Hexagon/HexagonInstrAlias.td deleted file mode 100644 index 7283d94ee759..000000000000 --- a/contrib/llvm/lib/Target/Hexagon/HexagonInstrAlias.td +++ /dev/null @@ -1,652 +0,0 @@ -//==- HexagonInstrAlias.td - Hexagon Instruction Aliases ---*- tablegen -*--==// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// Hexagon Instruction Mappings -//===----------------------------------------------------------------------===// - - -def : InstAlias<"memb({GP}+#$addr) = $Nt.new", - (S2_storerbnewgp u16_0Imm:$addr, IntRegs:$Nt)>; -def : InstAlias<"memh({GP}+#$addr) = $Nt.new", - (S2_storerhnewgp u16_1Imm:$addr, IntRegs:$Nt)>; -def : InstAlias<"memw({GP}+#$addr) = $Nt.new", - (S2_storerinewgp u16_2Imm:$addr, IntRegs:$Nt)>; -def : InstAlias<"memb({GP}+#$addr) = $Nt", - (S2_storerbgp u16_0Imm:$addr, IntRegs:$Nt)>; -def : InstAlias<"memh({GP}+#$addr) = $Nt", - (S2_storerhgp u16_1Imm:$addr, IntRegs:$Nt)>; -def : InstAlias<"memh({GP}+#$addr) = $Nt.h", - (S2_storerfgp u16_1Imm:$addr, IntRegs:$Nt)>; -def : InstAlias<"memw({GP}+#$addr) = $Nt", - (S2_storerigp u16_2Imm:$addr, IntRegs:$Nt)>; -def : InstAlias<"memd({GP}+#$addr) = $Nt", - (S2_storerdgp u16_3Imm:$addr, DoubleRegs:$Nt)>; - -def : InstAlias<"$Nt = memb({GP}+#$addr)", - (L2_loadrbgp IntRegs:$Nt, u16_0Imm:$addr)>; -def : InstAlias<"$Nt = memub({GP}+#$addr)", - (L2_loadrubgp IntRegs:$Nt, u16_0Imm:$addr)>; -def : InstAlias<"$Nt = memh({GP}+#$addr)", - (L2_loadrhgp IntRegs:$Nt, u16_1Imm:$addr)>; -def : InstAlias<"$Nt = memuh({GP}+#$addr)", - (L2_loadruhgp IntRegs:$Nt, u16_1Imm:$addr)>; -def : InstAlias<"$Nt = memw({GP}+#$addr)", - (L2_loadrigp IntRegs:$Nt, u16_2Imm:$addr)>; -def : InstAlias<"$Nt = memd({GP}+#$addr)", - (L2_loadrdgp DoubleRegs:$Nt, u16_3Imm:$addr)>; - -// Alias of: memXX($Rs+#XX) = $Rt to memXX($Rs) = $Rt -def : InstAlias<"memb($Rs) = $Rt", - (S2_storerb_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"memh($Rs) = $Rt", - (S2_storerh_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"memh($Rs) = $Rt.h", - (S2_storerf_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"memw($Rs) = $Rt", - (S2_storeri_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"memb($Rs) = $Rt.new", - (S2_storerbnew_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"memh($Rs) = $Rt.new", - (S2_storerhnew_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"memw($Rs) = $Rt.new", - (S2_storerinew_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"memb($Rs) = #$S8", - (S4_storeirb_io IntRegs:$Rs, 0, s8_0Ext:$S8), 0>; - -def : InstAlias<"memh($Rs) = #$S8", - (S4_storeirh_io IntRegs:$Rs, 0, s8_0Ext:$S8), 0>; - -def : InstAlias<"memw($Rs) = #$S8", - (S4_storeiri_io IntRegs:$Rs, 0, s8_0Ext:$S8), 0>; - -def : InstAlias<"memd($Rs) = $Rtt", - (S2_storerd_io IntRegs:$Rs, 0, DoubleRegs:$Rtt), 0>; - -def : InstAlias<"memb($Rs) = setbit(#$U5)", - (L4_ior_memopb_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>; - -def : InstAlias<"memh($Rs) = setbit(#$U5)", - (L4_ior_memoph_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>; - -def : InstAlias<"memw($Rs) = setbit(#$U5)", - (L4_ior_memopw_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>; - -def : InstAlias<"memb($Rs) = clrbit(#$U5)", - (L4_iand_memopb_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>; - -def : InstAlias<"memh($Rs) = clrbit(#$U5)", - (L4_iand_memoph_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>; - -def : InstAlias<"memw($Rs) = clrbit(#$U5)", - (L4_iand_memopw_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>; - -// Alias of: $Rd = memXX($Rs+#XX) to $Rd = memXX($Rs) -def : InstAlias<"$Rd = memb($Rs)", - (L2_loadrb_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rd = memub($Rs)", - (L2_loadrub_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rd = memh($Rs)", - (L2_loadrh_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rd = memuh($Rs)", - (L2_loadruh_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rd = memw($Rs)", - (L2_loadri_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rdd = memd($Rs)", - (L2_loadrd_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rd = memubh($Rs)", - (L2_loadbzw2_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rdd = memubh($Rs)", - (L2_loadbzw4_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rd = membh($Rs)", - (L2_loadbsw2_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rdd = membh($Rs)", - (L2_loadbsw4_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rdd = memb_fifo($Rs)", - (L2_loadalignb_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"$Rdd = memh_fifo($Rs)", - (L2_loadalignh_io DoubleRegs:$Rdd, IntRegs:$Rs, 0), 0>; - -// Alias of: if ($Pt) $Rd = memXX($Rs + #$u6_X) -// to: if ($Pt) $Rd = memXX($Rs) -def : InstAlias<"if ($Pt) $Rd = memb($Rs)", - (L2_ploadrbt_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if ($Pt) $Rd = memub($Rs)", - (L2_ploadrubt_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if ($Pt) $Rd = memh($Rs)", - (L2_ploadrht_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if ($Pt) $Rd = memuh($Rs)", - (L2_ploadruht_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if ($Pt) $Rd = memw($Rs)", - (L2_ploadrit_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if ($Pt) $Rdd = memd($Rs)", - (L2_ploadrdt_io DoubleRegs:$Rdd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -// Alias of: if ($Pt) memXX($Rs + #$u6_X) = $Rt -// to: if ($Pt) memXX($Rs) = $Rt -def : InstAlias<"if ($Pt) memb($Rs) = $Rt", - (S2_pstorerbt_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pt) memh($Rs) = $Rt", - (S2_pstorerht_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pt) memh($Rs) = $Rt.h", - (S2_pstorerft_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pt) memw($Rs) = $Rt", - (S2_pstorerit_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pt) memd($Rs) = $Rtt", - (S2_pstorerdt_io PredRegs:$Pt, IntRegs:$Rs, 0, DoubleRegs:$Rtt), 0>; - -def : InstAlias<"if ($Pt) memb($Rs) = $Rt.new", - (S2_pstorerbnewt_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pt) memh($Rs) = $Rt.new", - (S2_pstorerhnewt_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pt) memw($Rs) = $Rt.new", - (S2_pstorerinewt_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pt.new) memb($Rs) = $Rt.new", - (S4_pstorerbnewtnew_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pt.new) memh($Rs) = $Rt.new", - (S4_pstorerhnewtnew_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pt.new) memw($Rs) = $Rt.new", - (S4_pstorerinewtnew_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - - -// Alias of: if (!$Pt) $Rd = memXX($Rs + #$u6_X) -// to: if (!$Pt) $Rd = memXX($Rs) -def : InstAlias<"if (!$Pt) $Rd = memb($Rs)", - (L2_ploadrbf_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt) $Rd = memub($Rs)", - (L2_ploadrubf_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt) $Rd = memh($Rs)", - (L2_ploadrhf_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt) $Rd = memuh($Rs)", - (L2_ploadruhf_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt) $Rd = memw($Rs)", - (L2_ploadrif_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt) $Rdd = memd($Rs)", - (L2_ploadrdf_io DoubleRegs:$Rdd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -// Alias of: if (!$Pt) memXX($Rs + #$u6_X) = $Rt -// to: if (!$Pt) memXX($Rs) = $Rt -def : InstAlias<"if (!$Pt) memb($Rs) = $Rt", - (S2_pstorerbf_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pt) memh($Rs) = $Rt", - (S2_pstorerhf_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pt) memh($Rs) = $Rt.h", - (S2_pstorerff_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pt) memw($Rs) = $Rt", - (S2_pstorerif_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pt) memd($Rs) = $Rtt", - (S2_pstorerdf_io PredRegs:$Pt, IntRegs:$Rs, 0, DoubleRegs:$Rtt), 0>; - -def : InstAlias<"if (!$Pt) memb($Rs) = $Rt.new", - (S2_pstorerbnewf_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pt) memh($Rs) = $Rt.new", - (S2_pstorerhnewf_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pt) memw($Rs) = $Rt.new", - (S2_pstorerinewf_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pt.new) memb($Rs) = $Rt.new", - (S4_pstorerbnewfnew_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pt.new) memh($Rs) = $Rt.new", - (S4_pstorerhnewfnew_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pt.new) memw($Rs) = $Rt.new", - (S4_pstorerinewfnew_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pt) memb($Rs) = #$S6", - (S4_storeirbt_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if ($Pt) memh($Rs) = #$S6", - (S4_storeirht_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if ($Pt) memw($Rs) = #$S6", - (S4_storeirit_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if ($Pt.new) memb($Rs) = #$S6", - (S4_storeirbtnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if ($Pt.new) memh($Rs) = #$S6", - (S4_storeirhtnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if ($Pt.new) memw($Rs) = #$S6", - (S4_storeiritnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if (!$Pt) memb($Rs) = #$S6", - (S4_storeirbf_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if (!$Pt) memh($Rs) = #$S6", - (S4_storeirhf_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if (!$Pt) memw($Rs) = #$S6", - (S4_storeirif_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if (!$Pt.new) memb($Rs) = #$S6", - (S4_storeirbfnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if (!$Pt.new) memh($Rs) = #$S6", - (S4_storeirhfnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -def : InstAlias<"if (!$Pt.new) memw($Rs) = #$S6", - (S4_storeirifnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>; - -// Alias of: memXX($Rs + $u6_X) |= $Rt, also &=, +=, -= -// to: memXX($Rs) |= $Rt -def : InstAlias<"memb($Rs) &= $Rt", - (L4_and_memopb_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memb($Rs) |= $Rt", - (L4_or_memopb_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memb($Rs) += $Rt", - (L4_add_memopb_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memb($Rs) -= $Rt", - (L4_sub_memopb_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memb($Rs) += #$U5", - (L4_iadd_memopb_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memb($Rs) -= #$U5", - (L4_isub_memopb_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memh($Rs) &= $Rt", - (L4_and_memoph_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memh($Rs) |= $Rt", - (L4_or_memoph_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memh($Rs) += $Rt", - (L4_add_memoph_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memh($Rs) -= $Rt", - (L4_sub_memoph_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memh($Rs) += #$U5", - (L4_iadd_memoph_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memh($Rs) -= #$U5", - (L4_isub_memoph_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memw($Rs) &= $Rt", - (L4_and_memopw_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memw($Rs) |= $Rt", - (L4_or_memopw_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memw($Rs) += $Rt", - (L4_add_memopw_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memw($Rs) -= $Rt", - (L4_sub_memopw_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memw($Rs) += #$U5", - (L4_iadd_memopw_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>, - Requires<[UseMEMOP]>; - -def : InstAlias<"memw($Rs) -= #$U5", - (L4_isub_memopw_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>, - Requires<[UseMEMOP]>; - -// -// Alias of: if ($Pv.new) memX($Rs) = $Rt -// to: if (p3.new) memX(r17 + #0) = $Rt -def : InstAlias<"if ($Pv.new) memb($Rs) = $Rt", - (S4_pstorerbtnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pv.new) memh($Rs) = $Rt", - (S4_pstorerhtnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pv.new) memh($Rs) = $Rt.h", - (S4_pstorerftnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pv.new) memw($Rs) = $Rt", - (S4_pstoreritnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if ($Pv.new) memd($Rs) = $Rtt", - (S4_pstorerdtnew_io - PredRegs:$Pv, IntRegs:$Rs, 0, DoubleRegs:$Rtt), 0>; - -def : InstAlias<"if (!$Pv.new) memb($Rs) = $Rt", - (S4_pstorerbfnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pv.new) memh($Rs) = $Rt", - (S4_pstorerhfnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pv.new) memh($Rs) = $Rt.h", - (S4_pstorerffnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pv.new) memw($Rs) = $Rt", - (S4_pstorerifnew_io PredRegs:$Pv, IntRegs:$Rs, 0, IntRegs:$Rt), 0>; - -def : InstAlias<"if (!$Pv.new) memd($Rs) = $Rtt", - (S4_pstorerdfnew_io - PredRegs:$Pv, IntRegs:$Rs, 0, DoubleRegs:$Rtt), 0>; - -// -// Alias of: if ($Pt.new) $Rd = memub($Rs) -- And if (!$Pt.new) ... -// to: if ($Pt.new) $Rd = memub($Rs + #$u6_0) -def : InstAlias<"if ($Pt.new) $Rd = memub($Rs)", - (L2_ploadrubtnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if ($Pt.new) $Rd = memb($Rs)", - (L2_ploadrbtnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if ($Pt.new) $Rd = memh($Rs)", - (L2_ploadrhtnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if ($Pt.new) $Rd = memuh($Rs)", - (L2_ploadruhtnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if ($Pt.new) $Rd = memw($Rs)", - (L2_ploadritnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if ($Pt.new) $Rdd = memd($Rs)", - (L2_ploadrdtnew_io DoubleRegs:$Rdd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt.new) $Rd = memub($Rs)", - (L2_ploadrubfnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt.new) $Rd = memb($Rs)", - (L2_ploadrbfnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt.new) $Rd = memh($Rs)", - (L2_ploadrhfnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt.new) $Rd = memuh($Rs)", - (L2_ploadruhfnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt.new) $Rd = memw($Rs)", - (L2_ploadrifnew_io IntRegs:$Rd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"if (!$Pt.new) $Rdd = memd($Rs)", - (L2_ploadrdfnew_io DoubleRegs:$Rdd, PredRegs:$Pt, IntRegs:$Rs, 0), 0>; - -def : InstAlias<"dcfetch($Rs)", - (Y2_dcfetchbo IntRegs:$Rs, 0), 0>; - -// Alias of some insn mappings, others must be handled by the parser -def : InstAlias<"$Pd=cmp.lt($Rs, $Rt)", - (C2_cmpgt PredRegs:$Pd, IntRegs:$Rt, IntRegs:$Rs), 0>; -def : InstAlias<"$Pd=cmp.ltu($Rs, $Rt)", - (C2_cmpgtu PredRegs:$Pd, IntRegs:$Rt, IntRegs:$Rs), 0>; - -// Rd=neg(Rs) is aliased to Rd=sub(#0,Rs) -def : InstAlias<"$Rd = neg($Rs)", - (A2_subri IntRegs:$Rd, 0, IntRegs:$Rs), 0>; - -def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>; -def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>; -def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>; -def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>; - -def : InstAlias<"$Pd = $Ps", - (C2_or PredRegs:$Pd, PredRegs:$Ps, PredRegs:$Ps), 0>; - -def : InstAlias<"$Rdd = vaddb($Rss, $Rtt)", - (A2_vaddub DoubleRegs:$Rdd, DoubleRegs:$Rss, DoubleRegs:$Rtt), 1>; - -def : InstAlias<"$Rdd = vsubb($Rss,$Rtt)", - (A2_vsubub DoubleRegs:$Rdd, DoubleRegs:$Rss, DoubleRegs:$Rtt), 0>; - -def : InstAlias<"$Rd = mpyui($Rs,$Rt)", - (M2_mpyi IntRegs:$Rd, IntRegs:$Rs, IntRegs:$Rt), 0>; - -// Assembler mapped insns: cmp.lt(a,b) -> cmp.gt(b,a) -def : InstAlias<"$Pd=cmp.lt($Rs, $Rt)", - (C2_cmpgt PredRegs:$Pd, IntRegs:$Rt, IntRegs:$Rs), 0>; -def : InstAlias<"$Pd=cmp.ltu($Rs, $Rt)", - (C2_cmpgtu PredRegs:$Pd, IntRegs:$Rt, IntRegs:$Rs), 0>; - -// maps if (!Pu) jumpr Rs -> if (!Pu) jumpr:nt Rs -def : InstAlias<"if (!$Pu) jumpr $Rs", - (J2_jumprf PredRegs:$Pu, IntRegs:$Rs)>, - Requires<[HasV60T]>; - -// maps if (Pu) jumpr Rs -> if (Pu) jumpr:nt Rs -def : InstAlias<"if ($Pu) jumpr $Rs", - (J2_jumprt PredRegs:$Pu, IntRegs:$Rs)>, - Requires<[HasV60T]>; - -// maps if (!Pu) jump $r15_2 -> if (!Pu) jump:nt $r15_2 -def : InstAlias<"if (!$Pu) jump $r15_2", - (J2_jumpf PredRegs:$Pu, brtarget:$r15_2)>, - Requires<[HasV60T]>; - -// maps if (Pu) jump $r15_2 -> if (Pu) jump:nt $r15_2 -def : InstAlias<"if ($Pu) jump $r15_2", - (J2_jumpt PredRegs:$Pu, brtarget:$r15_2)>, - Requires<[HasV60T]>; - -def : InstAlias<"if ($src) jump $r15_2", - (J2_jumpt PredRegs:$src, brtarget:$r15_2), 0>; - -def : InstAlias<"if (!$src) jump $r15_2", - (J2_jumpf PredRegs:$src, brtarget:$r15_2), 0>; - -def : InstAlias<"if ($src1) jumpr $src2", - (J2_jumprt PredRegs:$src1, IntRegs:$src2), 0>; - -def : InstAlias<"if (!$src1) jumpr $src2", - (J2_jumprf PredRegs:$src1, IntRegs:$src2), 0>; - -// maps Vdd = Vss to Vdd = V6_vassignp(Vss) -def : InstAlias<"$Vdd = $Vss", - (V6_vassignp VecDblRegs:$Vdd, VecDblRegs:$Vss)>, - Requires<[HasV60T]>; - -// maps Vd = #0 to Vd = vxor(Vd, Vd) -def : InstAlias<"$Vd = #0", - (V6_vxor VectorRegs:$Vd, VectorRegs:$Vd, VectorRegs:$Vd)>, - Requires<[HasV60T]>; - -// maps Vdd = #0 to Vdd = vsub(Vdd, Vdd) -def : InstAlias<"$Vdd = #0", - (V6_vsubw_dv VecDblRegs:$Vdd, VecDblRegs:$Vdd, VecDblRegs:$Vdd)>, - Requires<[HasV60T]>; - -// maps "$Qd = vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd = vcmp.eq($Vu.h, $Vv.h)" -def : InstAlias<"$Qd = vcmp.eq($Vu.uh, $Vv.uh)", - (V6_veqh VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd &= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd &= vcmp.eq($Vu.h, $Vv.h)" -def : InstAlias<"$Qd &= vcmp.eq($Vu.uh, $Vv.uh)", - (V6_veqh_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd |= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd |= vcmp.eq($Vu.h, $Vv.h)" -def : InstAlias<"$Qd |= vcmp.eq($Vu.uh, $Vv.uh)", - (V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd ^= vcmp.eq($Vu.h, $Vv.h)" -def : InstAlias<"$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)", - (V6_veqh_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd = vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd = vcmp.eq($Vu.w, $Vv.w)" -def : InstAlias<"$Qd = vcmp.eq($Vu.uw, $Vv.uw)", - (V6_veqw VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd &= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd &= vcmp.eq($Vu.w, $Vv.w)" -def : InstAlias<"$Qd &= vcmp.eq($Vu.uw, $Vv.uw)", - (V6_veqw_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd |= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd |= vcmp.eq($Vu.w, $Vv.w)" -def : InstAlias<"$Qd |= vcmp.eq($Vu.uw, $Vv.uw)", - (V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd ^= vcmp.eq($Vu.w, $Vv.w)" -def : InstAlias<"$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)", - (V6_veqw_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd = vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd = vcmp.eq($Vu.b, $Vv.b)" -def : InstAlias<"$Qd = vcmp.eq($Vu.ub, $Vv.ub)", - (V6_veqb VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd &= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd &= vcmp.eq($Vu.b, $Vv.b)" -def : InstAlias<"$Qd &= vcmp.eq($Vu.ub, $Vv.ub)", - (V6_veqb_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd |= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd |= vcmp.eq($Vu.b, $Vv.b)" -def : InstAlias<"$Qd |= vcmp.eq($Vu.ub, $Vv.ub)", - (V6_veqb_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd ^= vcmp.eq($Vu.b, $Vv.b)" -def : InstAlias<"$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)", - (V6_veqb_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>, - Requires<[HasV60T]>; - -// maps "$Rd.w = vextract($Vu, $Rs)" -> "$Rd = vextract($Vu, $Rs)" -def : InstAlias<"$Rd.w = vextract($Vu, $Rs)", - (V6_extractw IntRegs:$Rd, VectorRegs:$Vu, IntRegs:$Rs)>, - Requires<[HasV60T]>; - -// Mapping from vtrans2x2(Vy32,Vx32,Rt32) to vshuff(Vy32,Vx32,Rt32) -def : InstAlias<"vtrans2x2($Vy, $Vx, $Rt)", - (V6_vshuff VectorRegs:$Vy, VectorRegs:$Vx, IntRegs:$Rt)>, - Requires<[HasV60T]>; - -def : InstAlias<"$Vt=vmem($Rs)", - (V6_vL32b_ai VectorRegs:$Vt, IntRegs:$Rs, 0)>, - Requires<[HasV60T]>; - -def : InstAlias<"$Vt=vmem($Rs):nt", - (V6_vL32b_nt_ai VectorRegs:$Vt, IntRegs:$Rs, 0)>, - Requires<[HasV60T]>; - -def : InstAlias<"vmem($Rs)=$Vt", - (V6_vS32b_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"vmem($Rs):nt=$Vt", - (V6_vS32b_nt_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"vmem($Rs)=$Vt.new", - (V6_vS32b_new_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"vmem($Rs):nt=$Vt.new", - (V6_vS32b_nt_new_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"if ($Qv) vmem($Rs)=$Vt", - (V6_vS32b_qpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"if (!$Qv) vmem($Rs)=$Vt", - (V6_vS32b_nqpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"if ($Qv) vmem($Rs):nt=$Vt", - (V6_vS32b_nt_qpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"if (!$Qv) vmem($Rs):nt=$Vt", - (V6_vS32b_nt_nqpred_ai VecPredRegs:$Qv, IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"if ($Pv) vmem($Rs)=$Vt", - (V6_vS32b_pred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"if (!$Pv) vmem($Rs)=$Vt", - (V6_vS32b_npred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"if ($Pv) vmem($Rs):nt=$Vt", - (V6_vS32b_nt_pred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"if (!$Pv) vmem($Rs):nt=$Vt", - (V6_vS32b_nt_npred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"$Vt=vmemu($Rs)", - (V6_vL32Ub_ai VectorRegs:$Vt, IntRegs:$Rs, 0)>, - Requires<[HasV60T]>; - -def : InstAlias<"vmemu($Rs)=$Vt", - (V6_vS32Ub_ai IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"if ($Pv) vmemu($Rs)=$Vt", - (V6_vS32Ub_pred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - -def : InstAlias<"if (!$Pv) vmemu($Rs)=$Vt", - (V6_vS32Ub_npred_ai PredRegs:$Pv, IntRegs:$Rs, 0, VectorRegs:$Vt)>, - Requires<[HasV60T]>; - - diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonInstrEnc.td b/contrib/llvm/lib/Target/Hexagon/HexagonInstrEnc.td deleted file mode 100644 index 280832fd167f..000000000000 --- a/contrib/llvm/lib/Target/Hexagon/HexagonInstrEnc.td +++ /dev/null @@ -1,1019 +0,0 @@ -class Enc_COPROC_VX_3op_v<bits<15> opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<5> src2; - - let Inst{31-16} = { opc{14-4}, src2}; - let Inst{13-0} = { opc{3}, src1, opc{2-0}, dst}; -} - -class V6_vtmpyb_enc : Enc_COPROC_VX_3op_v<0b000110010000000>; -class V6_vtmpybus_enc : Enc_COPROC_VX_3op_v<0b000110010000001>; -class V6_vdmpyhb_enc : Enc_COPROC_VX_3op_v<0b000110010000010>; -class V6_vrmpyub_enc : Enc_COPROC_VX_3op_v<0b000110010000011>; -class V6_vrmpybus_enc : Enc_COPROC_VX_3op_v<0b000110010000100>; -class V6_vdsaduh_enc : Enc_COPROC_VX_3op_v<0b000110010000101>; -class V6_vdmpybus_enc : Enc_COPROC_VX_3op_v<0b000110010000110>; -class V6_vdmpybus_dv_enc : Enc_COPROC_VX_3op_v<0b000110010000111>; -class V6_vtmpyb_acc_enc : Enc_COPROC_VX_3op_v<0b000110010001000>; -class V6_vtmpybus_acc_enc : Enc_COPROC_VX_3op_v<0b000110010001001>; -class V6_vtmpyhb_acc_enc : Enc_COPROC_VX_3op_v<0b000110010001010>; -class V6_vdmpyhb_acc_enc : Enc_COPROC_VX_3op_v<0b000110010001011>; -class V6_vrmpyub_acc_enc : Enc_COPROC_VX_3op_v<0b000110010001100>; -class V6_vrmpybus_acc_enc : Enc_COPROC_VX_3op_v<0b000110010001101>; -class V6_vdmpybus_acc_enc : Enc_COPROC_VX_3op_v<0b000110010001110>; -class V6_vdmpybus_dv_acc_enc : Enc_COPROC_VX_3op_v<0b000110010001111>; -class V6_vdmpyhsusat_enc : Enc_COPROC_VX_3op_v<0b000110010010000>; -class V6_vdmpyhsuisat_enc : Enc_COPROC_VX_3op_v<0b000110010010001>; -class V6_vdmpyhsat_enc : Enc_COPROC_VX_3op_v<0b000110010010010>; -class V6_vdmpyhisat_enc : Enc_COPROC_VX_3op_v<0b000110010010011>; -class V6_vdmpyhb_dv_enc : Enc_COPROC_VX_3op_v<0b000110010010100>; -class V6_vmpybus_enc : Enc_COPROC_VX_3op_v<0b000110010010101>; -class V6_vmpabus_enc : Enc_COPROC_VX_3op_v<0b000110010010110>; -class V6_vmpahb_enc : Enc_COPROC_VX_3op_v<0b000110010010111>; -class V6_vdmpyhsusat_acc_enc : Enc_COPROC_VX_3op_v<0b000110010011000>; -class V6_vdmpyhsuisat_acc_enc : Enc_COPROC_VX_3op_v<0b000110010011001>; -class V6_vdmpyhisat_acc_enc : Enc_COPROC_VX_3op_v<0b000110010011010>; -class V6_vdmpyhsat_acc_enc : Enc_COPROC_VX_3op_v<0b000110010011011>; -class V6_vdmpyhb_dv_acc_enc : Enc_COPROC_VX_3op_v<0b000110010011100>; -class V6_vmpybus_acc_enc : Enc_COPROC_VX_3op_v<0b000110010011101>; -class V6_vmpabus_acc_enc : Enc_COPROC_VX_3op_v<0b000110010011110>; -class V6_vmpahb_acc_enc : Enc_COPROC_VX_3op_v<0b000110010011111>; -class V6_vmpyh_enc : Enc_COPROC_VX_3op_v<0b000110010100000>; -class V6_vmpyhss_enc : Enc_COPROC_VX_3op_v<0b000110010100001>; -class V6_vmpyhsrs_enc : Enc_COPROC_VX_3op_v<0b000110010100010>; -class V6_vmpyuh_enc : Enc_COPROC_VX_3op_v<0b000110010100011>; -class V6_vmpyhsat_acc_enc : Enc_COPROC_VX_3op_v<0b000110010101000>; -class V6_vmpyuh_acc_enc : Enc_COPROC_VX_3op_v<0b000110010101001>; -class V6_vmpyiwb_acc_enc : Enc_COPROC_VX_3op_v<0b000110010101010>; -class V6_vmpyiwh_acc_enc : Enc_COPROC_VX_3op_v<0b000110010101011>; -class V6_vmpyihb_enc : Enc_COPROC_VX_3op_v<0b000110010110000>; -class V6_vror_enc : Enc_COPROC_VX_3op_v<0b000110010110001>; -class V6_vasrw_enc : Enc_COPROC_VX_3op_v<0b000110010110101>; -class V6_vasrh_enc : Enc_COPROC_VX_3op_v<0b000110010110110>; -class V6_vaslw_enc : Enc_COPROC_VX_3op_v<0b000110010110111>; -class V6_vdsaduh_acc_enc : Enc_COPROC_VX_3op_v<0b000110010111000>; -class V6_vmpyihb_acc_enc : Enc_COPROC_VX_3op_v<0b000110010111001>; -class V6_vaslw_acc_enc : Enc_COPROC_VX_3op_v<0b000110010111010>; -class V6_vasrw_acc_enc : Enc_COPROC_VX_3op_v<0b000110010111101>; -class V6_vaslh_enc : Enc_COPROC_VX_3op_v<0b000110011000000>; -class V6_vlsrw_enc : Enc_COPROC_VX_3op_v<0b000110011000001>; -class V6_vlsrh_enc : Enc_COPROC_VX_3op_v<0b000110011000010>; -class V6_vmpyiwh_enc : Enc_COPROC_VX_3op_v<0b000110011000111>; -class V6_vmpyub_acc_enc : Enc_COPROC_VX_3op_v<0b000110011001000>; -class V6_vmpyiwb_enc : Enc_COPROC_VX_3op_v<0b000110011010000>; -class V6_vtmpyhb_enc : Enc_COPROC_VX_3op_v<0b000110011010100>; -class V6_vmpyub_enc : Enc_COPROC_VX_3op_v<0b000110011100000>; -class V6_vrmpyubv_enc : Enc_COPROC_VX_3op_v<0b000111000000000>; -class V6_vrmpybv_enc : Enc_COPROC_VX_3op_v<0b000111000000001>; -class V6_vrmpybusv_enc : Enc_COPROC_VX_3op_v<0b000111000000010>; -class V6_vdmpyhvsat_enc : Enc_COPROC_VX_3op_v<0b000111000000011>; -class V6_vmpybv_enc : Enc_COPROC_VX_3op_v<0b000111000000100>; -class V6_vmpyubv_enc : Enc_COPROC_VX_3op_v<0b000111000000101>; -class V6_vmpybusv_enc : Enc_COPROC_VX_3op_v<0b000111000000110>; -class V6_vmpyhv_enc : Enc_COPROC_VX_3op_v<0b000111000000111>; -class V6_vrmpyubv_acc_enc : Enc_COPROC_VX_3op_v<0b000111000001000>; -class V6_vrmpybv_acc_enc : Enc_COPROC_VX_3op_v<0b000111000001001>; -class V6_vrmpybusv_acc_enc : Enc_COPROC_VX_3op_v<0b000111000001010>; -class V6_vdmpyhvsat_acc_enc : Enc_COPROC_VX_3op_v<0b000111000001011>; -class V6_vmpybv_acc_enc : Enc_COPROC_VX_3op_v<0b000111000001100>; -class V6_vmpyubv_acc_enc : Enc_COPROC_VX_3op_v<0b000111000001101>; -class V6_vmpybusv_acc_enc : Enc_COPROC_VX_3op_v<0b000111000001110>; -class V6_vmpyhv_acc_enc : Enc_COPROC_VX_3op_v<0b000111000001111>; -class V6_vmpyuhv_enc : Enc_COPROC_VX_3op_v<0b000111000010000>; -class V6_vmpyhvsrs_enc : Enc_COPROC_VX_3op_v<0b000111000010001>; -class V6_vmpyhus_enc : Enc_COPROC_VX_3op_v<0b000111000010010>; -class V6_vmpabusv_enc : Enc_COPROC_VX_3op_v<0b000111000010011>; -class V6_vmpyih_enc : Enc_COPROC_VX_3op_v<0b000111000010100>; -class V6_vand_enc : Enc_COPROC_VX_3op_v<0b000111000010101>; -class V6_vor_enc : Enc_COPROC_VX_3op_v<0b000111000010110>; -class V6_vxor_enc : Enc_COPROC_VX_3op_v<0b000111000010111>; -class V6_vmpyuhv_acc_enc : Enc_COPROC_VX_3op_v<0b000111000011000>; -class V6_vmpyhus_acc_enc : Enc_COPROC_VX_3op_v<0b000111000011001>; -class V6_vmpyih_acc_enc : Enc_COPROC_VX_3op_v<0b000111000011100>; -class V6_vmpyiewuh_acc_enc : Enc_COPROC_VX_3op_v<0b000111000011101>; -class V6_vmpyowh_sacc_enc : Enc_COPROC_VX_3op_v<0b000111000011110>; -class V6_vmpyowh_rnd_sacc_enc : Enc_COPROC_VX_3op_v<0b000111000011111>; -class V6_vaddw_enc : Enc_COPROC_VX_3op_v<0b000111000100000>; -class V6_vaddubsat_enc : Enc_COPROC_VX_3op_v<0b000111000100001>; -class V6_vadduhsat_enc : Enc_COPROC_VX_3op_v<0b000111000100010>; -class V6_vaddhsat_enc : Enc_COPROC_VX_3op_v<0b000111000100011>; -class V6_vaddwsat_enc : Enc_COPROC_VX_3op_v<0b000111000100100>; -class V6_vsubb_enc : Enc_COPROC_VX_3op_v<0b000111000100101>; -class V6_vsubh_enc : Enc_COPROC_VX_3op_v<0b000111000100110>; -class V6_vsubw_enc : Enc_COPROC_VX_3op_v<0b000111000100111>; -class V6_vmpyiewh_acc_enc : Enc_COPROC_VX_3op_v<0b000111000101000>; -class V6_vsububsat_enc : Enc_COPROC_VX_3op_v<0b000111000110000>; -class V6_vsubuhsat_enc : Enc_COPROC_VX_3op_v<0b000111000110001>; -class V6_vsubhsat_enc : Enc_COPROC_VX_3op_v<0b000111000110010>; -class V6_vsubwsat_enc : Enc_COPROC_VX_3op_v<0b000111000110011>; -class V6_vaddb_dv_enc : Enc_COPROC_VX_3op_v<0b000111000110100>; -class V6_vaddh_dv_enc : Enc_COPROC_VX_3op_v<0b000111000110101>; -class V6_vaddw_dv_enc : Enc_COPROC_VX_3op_v<0b000111000110110>; -class V6_vaddubsat_dv_enc : Enc_COPROC_VX_3op_v<0b000111000110111>; -class V6_vadduhsat_dv_enc : Enc_COPROC_VX_3op_v<0b000111001000000>; -class V6_vaddhsat_dv_enc : Enc_COPROC_VX_3op_v<0b000111001000001>; -class V6_vaddwsat_dv_enc : Enc_COPROC_VX_3op_v<0b000111001000010>; -class V6_vsubb_dv_enc : Enc_COPROC_VX_3op_v<0b000111001000011>; -class V6_vsubh_dv_enc : Enc_COPROC_VX_3op_v<0b000111001000100>; -class V6_vsubw_dv_enc : Enc_COPROC_VX_3op_v<0b000111001000101>; -class V6_vsububsat_dv_enc : Enc_COPROC_VX_3op_v<0b000111001000110>; -class V6_vsubuhsat_dv_enc : Enc_COPROC_VX_3op_v<0b000111001000111>; -class V6_vsubhsat_dv_enc : Enc_COPROC_VX_3op_v<0b000111001010000>; -class V6_vsubwsat_dv_enc : Enc_COPROC_VX_3op_v<0b000111001010001>; -class V6_vaddubh_enc : Enc_COPROC_VX_3op_v<0b000111001010010>; -class V6_vadduhw_enc : Enc_COPROC_VX_3op_v<0b000111001010011>; -class V6_vaddhw_enc : Enc_COPROC_VX_3op_v<0b000111001010100>; -class V6_vsububh_enc : Enc_COPROC_VX_3op_v<0b000111001010101>; -class V6_vsubuhw_enc : Enc_COPROC_VX_3op_v<0b000111001010110>; -class V6_vsubhw_enc : Enc_COPROC_VX_3op_v<0b000111001010111>; -class V6_vabsdiffub_enc : Enc_COPROC_VX_3op_v<0b000111001100000>; -class V6_vabsdiffh_enc : Enc_COPROC_VX_3op_v<0b000111001100001>; -class V6_vabsdiffuh_enc : Enc_COPROC_VX_3op_v<0b000111001100010>; -class V6_vabsdiffw_enc : Enc_COPROC_VX_3op_v<0b000111001100011>; -class V6_vavgub_enc : Enc_COPROC_VX_3op_v<0b000111001100100>; -class V6_vavguh_enc : Enc_COPROC_VX_3op_v<0b000111001100101>; -class V6_vavgh_enc : Enc_COPROC_VX_3op_v<0b000111001100110>; -class V6_vavgw_enc : Enc_COPROC_VX_3op_v<0b000111001100111>; -class V6_vnavgub_enc : Enc_COPROC_VX_3op_v<0b000111001110000>; -class V6_vnavgh_enc : Enc_COPROC_VX_3op_v<0b000111001110001>; -class V6_vnavgw_enc : Enc_COPROC_VX_3op_v<0b000111001110010>; -class V6_vavgubrnd_enc : Enc_COPROC_VX_3op_v<0b000111001110011>; -class V6_vavguhrnd_enc : Enc_COPROC_VX_3op_v<0b000111001110100>; -class V6_vavghrnd_enc : Enc_COPROC_VX_3op_v<0b000111001110101>; -class V6_vavgwrnd_enc : Enc_COPROC_VX_3op_v<0b000111001110110>; -class V6_vmpabuuv_enc : Enc_COPROC_VX_3op_v<0b000111001110111>; -class V6_vminub_enc : Enc_COPROC_VX_3op_v<0b000111110000001>; -class V6_vminuh_enc : Enc_COPROC_VX_3op_v<0b000111110000010>; -class V6_vminh_enc : Enc_COPROC_VX_3op_v<0b000111110000011>; -class V6_vminw_enc : Enc_COPROC_VX_3op_v<0b000111110000100>; -class V6_vmaxub_enc : Enc_COPROC_VX_3op_v<0b000111110000101>; -class V6_vmaxuh_enc : Enc_COPROC_VX_3op_v<0b000111110000110>; -class V6_vmaxh_enc : Enc_COPROC_VX_3op_v<0b000111110000111>; -class V6_vmaxw_enc : Enc_COPROC_VX_3op_v<0b000111110010000>; -class V6_vdelta_enc : Enc_COPROC_VX_3op_v<0b000111110010001>; -class V6_vrdelta_enc : Enc_COPROC_VX_3op_v<0b000111110010011>; -class V6_vdealb4w_enc : Enc_COPROC_VX_3op_v<0b000111110010111>; -class V6_vmpyowh_rnd_enc : Enc_COPROC_VX_3op_v<0b000111110100000>; -class V6_vshuffeb_enc : Enc_COPROC_VX_3op_v<0b000111110100001>; -class V6_vshuffob_enc : Enc_COPROC_VX_3op_v<0b000111110100010>; -class V6_vshufeh_enc : Enc_COPROC_VX_3op_v<0b000111110100011>; -class V6_vshufoh_enc : Enc_COPROC_VX_3op_v<0b000111110100100>; -class V6_vshufoeh_enc : Enc_COPROC_VX_3op_v<0b000111110100101>; -class V6_vshufoeb_enc : Enc_COPROC_VX_3op_v<0b000111110100110>; -class V6_vcombine_enc : Enc_COPROC_VX_3op_v<0b000111110100111>; -class V6_vmpyieoh_enc : Enc_COPROC_VX_3op_v<0b000111110110000>; -class V6_vsathub_enc : Enc_COPROC_VX_3op_v<0b000111110110010>; -class V6_vsatwh_enc : Enc_COPROC_VX_3op_v<0b000111110110011>; -class V6_vroundwh_enc : Enc_COPROC_VX_3op_v<0b000111110110100>; -class V6_vroundwuh_enc : Enc_COPROC_VX_3op_v<0b000111110110101>; -class V6_vroundhb_enc : Enc_COPROC_VX_3op_v<0b000111110110110>; -class V6_vroundhub_enc : Enc_COPROC_VX_3op_v<0b000111110110111>; -class V6_vasrwv_enc : Enc_COPROC_VX_3op_v<0b000111111010000>; -class V6_vlsrwv_enc : Enc_COPROC_VX_3op_v<0b000111111010001>; -class V6_vlsrhv_enc : Enc_COPROC_VX_3op_v<0b000111111010010>; -class V6_vasrhv_enc : Enc_COPROC_VX_3op_v<0b000111111010011>; -class V6_vaslwv_enc : Enc_COPROC_VX_3op_v<0b000111111010100>; -class V6_vaslhv_enc : Enc_COPROC_VX_3op_v<0b000111111010101>; -class V6_vaddb_enc : Enc_COPROC_VX_3op_v<0b000111111010110>; -class V6_vaddh_enc : Enc_COPROC_VX_3op_v<0b000111111010111>; -class V6_vmpyiewuh_enc : Enc_COPROC_VX_3op_v<0b000111111100000>; -class V6_vmpyiowh_enc : Enc_COPROC_VX_3op_v<0b000111111100001>; -class V6_vpackeb_enc : Enc_COPROC_VX_3op_v<0b000111111100010>; -class V6_vpackeh_enc : Enc_COPROC_VX_3op_v<0b000111111100011>; -class V6_vpackhub_sat_enc : Enc_COPROC_VX_3op_v<0b000111111100101>; -class V6_vpackhb_sat_enc : Enc_COPROC_VX_3op_v<0b000111111100110>; -class V6_vpackwuh_sat_enc : Enc_COPROC_VX_3op_v<0b000111111100111>; -class V6_vpackwh_sat_enc : Enc_COPROC_VX_3op_v<0b000111111110000>; -class V6_vpackob_enc : Enc_COPROC_VX_3op_v<0b000111111110001>; -class V6_vpackoh_enc : Enc_COPROC_VX_3op_v<0b000111111110010>; -class V6_vmpyewuh_enc : Enc_COPROC_VX_3op_v<0b000111111110101>; -class V6_vmpyowh_enc : Enc_COPROC_VX_3op_v<0b000111111110111>; -class V6_extractw_enc : Enc_COPROC_VX_3op_v<0b100100100000001>; -class M6_vabsdiffub_enc : Enc_COPROC_VX_3op_v<0b111010001010000>; -class M6_vabsdiffb_enc : Enc_COPROC_VX_3op_v<0b111010001110000>; - -class Enc_COPROC_VX_cmp<bits<13> opc> : OpcodeHexagon { - bits<2> dst; - bits<5> src1; - bits<5> src2; - - let Inst{31-16} = { 0b00011, opc{12-7}, src2{4-0} }; - let Inst{13-0} = { opc{6}, src1{4-0}, opc{5-0}, dst{1-0} }; -} - -class V6_vandvrt_acc_enc : Enc_COPROC_VX_cmp<0b0010111100000>; -class V6_vandvrt_enc : Enc_COPROC_VX_cmp<0b0011010010010>; -class V6_veqb_and_enc : Enc_COPROC_VX_cmp<0b1001001000000>; -class V6_veqh_and_enc : Enc_COPROC_VX_cmp<0b1001001000001>; -class V6_veqw_and_enc : Enc_COPROC_VX_cmp<0b1001001000010>; -class V6_vgtb_and_enc : Enc_COPROC_VX_cmp<0b1001001000100>; -class V6_vgth_and_enc : Enc_COPROC_VX_cmp<0b1001001000101>; -class V6_vgtw_and_enc : Enc_COPROC_VX_cmp<0b1001001000110>; -class V6_vgtub_and_enc : Enc_COPROC_VX_cmp<0b1001001001000>; -class V6_vgtuh_and_enc : Enc_COPROC_VX_cmp<0b1001001001001>; -class V6_vgtuw_and_enc : Enc_COPROC_VX_cmp<0b1001001001010>; -class V6_veqb_or_enc : Enc_COPROC_VX_cmp<0b1001001010000>; -class V6_veqh_or_enc : Enc_COPROC_VX_cmp<0b1001001010001>; -class V6_veqw_or_enc : Enc_COPROC_VX_cmp<0b1001001010010>; -class V6_vgtb_or_enc : Enc_COPROC_VX_cmp<0b1001001010100>; -class V6_vgth_or_enc : Enc_COPROC_VX_cmp<0b1001001010101>; -class V6_vgtw_or_enc : Enc_COPROC_VX_cmp<0b1001001010110>; -class V6_vgtub_or_enc : Enc_COPROC_VX_cmp<0b1001001011000>; -class V6_vgtuh_or_enc : Enc_COPROC_VX_cmp<0b1001001011001>; -class V6_vgtuw_or_enc : Enc_COPROC_VX_cmp<0b1001001011010>; -class V6_veqb_xor_enc : Enc_COPROC_VX_cmp<0b1001001100000>; -class V6_veqh_xor_enc : Enc_COPROC_VX_cmp<0b1001001100001>; -class V6_veqw_xor_enc : Enc_COPROC_VX_cmp<0b1001001100010>; -class V6_vgtb_xor_enc : Enc_COPROC_VX_cmp<0b1001001100100>; -class V6_vgth_xor_enc : Enc_COPROC_VX_cmp<0b1001001100101>; -class V6_vgtw_xor_enc : Enc_COPROC_VX_cmp<0b1001001100110>; -class V6_vgtub_xor_enc : Enc_COPROC_VX_cmp<0b1001001101000>; -class V6_vgtuh_xor_enc : Enc_COPROC_VX_cmp<0b1001001101001>; -class V6_vgtuw_xor_enc : Enc_COPROC_VX_cmp<0b1001001101010>; -class V6_veqb_enc : Enc_COPROC_VX_cmp<0b1111000000000>; -class V6_veqh_enc : Enc_COPROC_VX_cmp<0b1111000000001>; -class V6_veqw_enc : Enc_COPROC_VX_cmp<0b1111000000010>; -class V6_vgtb_enc : Enc_COPROC_VX_cmp<0b1111000000100>; -class V6_vgth_enc : Enc_COPROC_VX_cmp<0b1111000000101>; -class V6_vgtw_enc : Enc_COPROC_VX_cmp<0b1111000000110>; -class V6_vgtub_enc : Enc_COPROC_VX_cmp<0b1111000001000>; -class V6_vgtuh_enc : Enc_COPROC_VX_cmp<0b1111000001001>; -class V6_vgtuw_enc : Enc_COPROC_VX_cmp<0b1111000001010>; - -class Enc_COPROC_VX_p2op<bits<5> opc> : OpcodeHexagon { - bits<2> src1; - bits<5> dst; - bits<5> src2; - - let Inst{31-16} = { 0b00011110, src1{1-0}, 0b0000, opc{4-3} }; - let Inst{13-0} = { 1, src2{4-0}, opc{2-0}, dst{4-0} }; -} - -class V6_vaddbq_enc : Enc_COPROC_VX_p2op<0b01000>; -class V6_vaddhq_enc : Enc_COPROC_VX_p2op<0b01001>; -class V6_vaddwq_enc : Enc_COPROC_VX_p2op<0b01010>; -class V6_vaddbnq_enc : Enc_COPROC_VX_p2op<0b01011>; -class V6_vaddhnq_enc : Enc_COPROC_VX_p2op<0b01100>; -class V6_vaddwnq_enc : Enc_COPROC_VX_p2op<0b01101>; -class V6_vsubbq_enc : Enc_COPROC_VX_p2op<0b01110>; -class V6_vsubhq_enc : Enc_COPROC_VX_p2op<0b01111>; -class V6_vsubwq_enc : Enc_COPROC_VX_p2op<0b10000>; -class V6_vsubbnq_enc : Enc_COPROC_VX_p2op<0b10001>; -class V6_vsubhnq_enc : Enc_COPROC_VX_p2op<0b10010>; -class V6_vsubwnq_enc : Enc_COPROC_VX_p2op<0b10011>; - -class Enc_COPROC_VX_2op<bits<6> opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - - let Inst{31-16} = { 0b00011110000000, opc{5-4} }; - let Inst{13-0} = { opc{3}, src1{4-0}, opc{2-0}, dst{4-0} }; -} - -class V6_vabsh_enc : Enc_COPROC_VX_2op<0b000000>; -class V6_vabsh_sat_enc : Enc_COPROC_VX_2op<0b000001>; -class V6_vabsw_enc : Enc_COPROC_VX_2op<0b000010>; -class V6_vabsw_sat_enc : Enc_COPROC_VX_2op<0b000011>; -class V6_vnot_enc : Enc_COPROC_VX_2op<0b000100>; -class V6_vdealh_enc : Enc_COPROC_VX_2op<0b000110>; -class V6_vdealb_enc : Enc_COPROC_VX_2op<0b000111>; -class V6_vunpackob_enc : Enc_COPROC_VX_2op<0b001000>; -class V6_vunpackoh_enc : Enc_COPROC_VX_2op<0b001001>; -class V6_vunpackub_enc : Enc_COPROC_VX_2op<0b010000>; -class V6_vunpackuh_enc : Enc_COPROC_VX_2op<0b010001>; -class V6_vunpackb_enc : Enc_COPROC_VX_2op<0b010010>; -class V6_vunpackh_enc : Enc_COPROC_VX_2op<0b010011>; -class V6_vshuffh_enc : Enc_COPROC_VX_2op<0b010111>; -class V6_vshuffb_enc : Enc_COPROC_VX_2op<0b100000>; -class V6_vzb_enc : Enc_COPROC_VX_2op<0b100001>; -class V6_vzh_enc : Enc_COPROC_VX_2op<0b100010>; -class V6_vsb_enc : Enc_COPROC_VX_2op<0b100011>; -class V6_vsh_enc : Enc_COPROC_VX_2op<0b100100>; -class V6_vcl0w_enc : Enc_COPROC_VX_2op<0b100101>; -class V6_vpopcounth_enc : Enc_COPROC_VX_2op<0b100110>; -class V6_vcl0h_enc : Enc_COPROC_VX_2op<0b100111>; -class V6_vnormamtw_enc : Enc_COPROC_VX_2op<0b110100>; -class V6_vnormamth_enc : Enc_COPROC_VX_2op<0b110101>; -class V6_vassign_enc : Enc_COPROC_VX_2op<0b111111>; - -class Enc_COPROC_VMEM_vL32_b_ai<bits<4> opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<10> src2; - bits<4> src2_vector; - - let src2_vector = src2{9-6}; - let Inst{31-16} = { 0b001010000, opc{3}, 0, src1{4-0} }; - let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, opc{2-0}, dst{4-0} }; -} - -class V6_vL32b_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b0000>; -class V6_vL32b_cur_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b0001>; -class V6_vL32b_tmp_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b0010>; -class V6_vL32Ub_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b0111>; -class V6_vL32b_nt_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b1000>; -class V6_vL32b_nt_cur_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b1001>; -class V6_vL32b_nt_tmp_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b1010>; - -class Enc_COPROC_VMEM_vL32_b_ai_128B<bits<4> opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<11> src2; - bits<4> src2_vector; - - let src2_vector = src2{10-7}; - let Inst{31-16} = { 0b001010000, opc{3}, 0, src1{4-0} }; - let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, opc{2-0}, dst{4-0} }; -} - -class V6_vL32b_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b0000>; -class V6_vL32b_cur_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b0001>; -class V6_vL32b_tmp_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b0010>; -class V6_vL32Ub_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b0111>; -class V6_vL32b_nt_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b1000>; -class V6_vL32b_nt_cur_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b1001>; -class V6_vL32b_nt_tmp_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b1010>; - -class Enc_COPROC_VMEM_vS32_b_ai_64B<bits<4> opc> : OpcodeHexagon { - bits<5> src1; - bits<10> src2; - bits<4> src2_vector; - bits<5> src3; - - let src2_vector = src2{9-6}; - let Inst{31-16} = { 0b001010000, opc{3}, 1, src1{4-0} }; - let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, opc{2-0}, src3{4-0} }; -} - -class Enc_COPROC_VMEM_vS32_b_ai_128B<bits<4> opc> : OpcodeHexagon { - bits<5> src1; - bits<11> src2; - bits<4> src2_vector; - bits<5> src3; - - let src2_vector = src2{10-7}; - let Inst{31-16} = { 0b001010000, opc{3}, 1, src1{4-0} }; - let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, opc{2-0}, src3{4-0} }; -} - -class V6_vS32b_ai_enc : Enc_COPROC_VMEM_vS32_b_ai_64B<0b0000>; -class V6_vS32Ub_ai_enc : Enc_COPROC_VMEM_vS32_b_ai_64B<0b0111>; -class V6_vS32b_nt_ai_enc : Enc_COPROC_VMEM_vS32_b_ai_64B<0b1000>; - -class V6_vS32b_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_ai_128B<0b0000>; -class V6_vS32Ub_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_ai_128B<0b0111>; -class V6_vS32b_nt_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_ai_128B<0b1000>; - -class Enc_COPROC_VMEM_vS32b_n_ew_ai_64B<bits<1> opc> : OpcodeHexagon { - bits<5> src1; - bits<10> src2; - bits<4> src2_vector; - bits<3> src3; - - let src2_vector = src2{9-6}; - let Inst{31-16} = { 0b001010000, opc{0}, 1, src1{4-0} }; - let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, 0b00100, src3{2-0} }; -} - -class V6_vS32b_new_ai_enc : Enc_COPROC_VMEM_vS32b_n_ew_ai_64B<0>; -class V6_vS32b_nt_new_ai_enc : Enc_COPROC_VMEM_vS32b_n_ew_ai_64B<1>; - -class Enc_COPROC_VMEM_vS32b_n_ew_ai_128B<bits<1> opc> : OpcodeHexagon { - bits<5> src1; - bits<11> src2; - bits<4> src2_vector; - bits<3> src3; - - let src2_vector = src2{10-7}; - let Inst{31-16} = { 0b001010000, opc{0}, 1, src1{4-0} }; - let Inst{13-0} = { src2_vector{3}, 0b00, src2_vector{2-0}, 0b00100, src3{2-0} }; -} - -class V6_vS32b_new_ai_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_ai_128B<0>; -class V6_vS32b_nt_new_ai_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_ai_128B<1>; - -class Enc_COPROC_VMEM_vS32_b_pred_ai<bits<5> opc> : OpcodeHexagon { - bits<2> src1; - bits<5> src2; - bits<10> src3; - bits<4> src3_vector; - bits<5> src4; - - let src3_vector = src3{9-6}; - let Inst{31-16} = { 0b001010001, opc{4-3}, src2{4-0} }; - let Inst{13-0} = { src3_vector{3}, src1{1-0}, src3_vector{2-0}, opc{2-0}, src4{4-0} }; -} - -class Enc_COPROC_VMEM_vS32_b_pred_ai_128B<bits<5> opc> : OpcodeHexagon { - bits<2> src1; - bits<5> src2; - bits<11> src3; - bits<4> src3_vector; - bits<5> src4; - - let src3_vector = src3{10-7}; - let Inst{31-16} = { 0b001010001, opc{4-3}, src2{4-0} }; - let Inst{13-0} = { src3_vector{3}, src1{1-0}, src3_vector{2-0}, opc{2-0}, src4{4-0} }; -} - -class V6_vS32b_qpred_ai_enc : Enc_COPROC_VMEM_vS32_b_pred_ai<0b00000>; -class V6_vS32b_nqpred_ai_enc : Enc_COPROC_VMEM_vS32_b_pred_ai<0b00001>; -class V6_vS32b_pred_ai_enc : Enc_COPROC_VMEM_vS32_b_pred_ai<0b01000>; -class V6_vS32b_npred_ai_enc : Enc_COPROC_VMEM_vS32_b_pred_ai<0b01001>; -class V6_vS32Ub_pred_ai_enc : Enc_COPROC_VMEM_vS32_b_pred_ai<0b01110>; -class V6_vS32Ub_npred_ai_enc : Enc_COPROC_VMEM_vS32_b_pred_ai<0b01111>; -class V6_vS32b_nt_qpred_ai_enc : Enc_COPROC_VMEM_vS32_b_pred_ai<0b10000>; -class V6_vS32b_nt_nqpred_ai_enc : Enc_COPROC_VMEM_vS32_b_pred_ai<0b10001>; -class V6_vS32b_nt_pred_ai_enc : Enc_COPROC_VMEM_vS32_b_pred_ai<0b11000>; -class V6_vS32b_nt_npred_ai_enc : Enc_COPROC_VMEM_vS32_b_pred_ai<0b11001>; - -class V6_vS32b_qpred_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_ai_128B<0b00000>; -class V6_vS32b_nqpred_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_ai_128B<0b00001>; -class V6_vS32b_pred_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_ai_128B<0b01000>; -class V6_vS32b_npred_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_ai_128B<0b01001>; -class V6_vS32Ub_pred_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_ai_128B<0b01110>; -class V6_vS32Ub_npred_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_ai_128B<0b01111>; -class V6_vS32b_nt_qpred_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_ai_128B<0b10000>; -class V6_vS32b_nt_nqpred_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_ai_128B<0b10001>; -class V6_vS32b_nt_pred_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_ai_128B<0b11000>; -class V6_vS32b_nt_npred_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_ai_128B<0b11001>; - -class Enc_COPROC_VMEM_vS32b_n_ew_pred_ai<bits<4> opc> : OpcodeHexagon { - bits<2> src1; - bits<5> src2; - bits<10> src3; - bits<4> src3_vector; - bits<3> src4; - - let src3_vector = src3{9-6}; - let Inst{31-16} = { 0b001010001, opc{3}, 1, src2{4-0} }; - let Inst{13-0} = { src3_vector{3}, src1{1-0}, src3_vector{2-0}, 0b01, opc{2-0}, src4{2-0} }; -} - -class V6_vS32b_new_pred_ai_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai<0b0000>; -class V6_vS32b_new_npred_ai_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai<0b0101>; -class V6_vS32b_nt_new_pred_ai_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai<0b1010>; -class V6_vS32b_nt_new_npred_ai_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai<0b1111>; - -class Enc_COPROC_VMEM_vS32b_n_ew_pred_ai_128B<bits<4> opc> : OpcodeHexagon { - bits<2> src1; - bits<5> src2; - bits<11> src3; - bits<4> src3_vector; - bits<3> src4; - - let src3_vector = src3{10-7}; - let Inst{31-16} = { 0b001010001, opc{3}, 1, src2{4-0} }; - let Inst{13-0} = { src3_vector{3}, src1{1-0}, src3_vector{2-0}, 0b01, opc{2-0}, src4{2-0} }; -} - -class V6_vS32b_new_pred_ai_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai_128B<0b0000>; -class V6_vS32b_new_npred_ai_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai_128B<0b0101>; -class V6_vS32b_nt_new_pred_ai_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai_128B<0b1010>; -class V6_vS32b_nt_new_npred_ai_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai_128B<0b1111>; - -// TODO: Change script to generate dst, src1, src2 instead of -// dst, dst2, src1. -class Enc_COPROC_VMEM_vL32_b_pi<bits<4> opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<9> src2; - bits<3> src2_vector; - - let src2_vector = src2{8-6}; - let Inst{31-16} = { 0b001010010, opc{3}, 0, src1{4-0} }; - let Inst{13-0} = { 0b000, src2_vector{2-0}, opc{2-0}, dst{4-0} }; -} - -class V6_vL32b_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b0000>; -class V6_vL32b_cur_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b0001>; -class V6_vL32b_tmp_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b0010>; -class V6_vL32Ub_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b0111>; -class V6_vL32b_nt_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b1000>; -class V6_vL32b_nt_cur_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b1001>; -class V6_vL32b_nt_tmp_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b1010>; - -class Enc_COPROC_VMEM_vL32_b_pi_128B<bits<4> opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<10> src2; - bits<3> src2_vector; - - let src2_vector = src2{9-7}; - let Inst{31-16} = { 0b001010010, opc{3}, 0, src1{4-0} }; - let Inst{13-0} = { 0b000, src2_vector{2-0}, opc{2-0}, dst{4-0} }; -} - -class V6_vL32b_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b0000>; -class V6_vL32b_cur_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b0001>; -class V6_vL32b_tmp_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b0010>; -class V6_vL32Ub_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b0111>; -class V6_vL32b_nt_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b1000>; -class V6_vL32b_nt_cur_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b1001>; -class V6_vL32b_nt_tmp_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b1010>; - - -// TODO: Change script to generate src1, src2 and src3 instead of -// dst, src1, src2. -class Enc_COPROC_VMEM_vS32_b_pi<bits<4> opc> : OpcodeHexagon { - bits<5> src1; - bits<9> src2; - bits<3> src2_vector; - bits<5> src3; - - let src2_vector = src2{8-6}; - let Inst{31-16} = { 0b001010010, opc{3}, 1, src1{4-0} }; - let Inst{10-0} = {src2_vector{2-0}, opc{2-0}, src3{4-0} }; -} - -class V6_vS32b_pi_enc : Enc_COPROC_VMEM_vS32_b_pi<0b0000>; -class V6_vS32Ub_pi_enc : Enc_COPROC_VMEM_vS32_b_pi<0b0111>; -class V6_vS32b_nt_pi_enc : Enc_COPROC_VMEM_vS32_b_pi<0b1000>; - -class Enc_COPROC_VMEM_vS32_b_pi_128B<bits<4> opc> : OpcodeHexagon { - bits<5> src1; - bits<10> src2; - bits<3> src2_vector; - bits<5> src3; - - let src2_vector = src2{9-7}; - let Inst{31-16} = { 0b001010010, opc{3}, 1, src1{4-0} }; - let Inst{10-0} = {src2_vector{2-0}, opc{2-0}, src3{4-0} }; -} - -class V6_vS32b_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pi_128B<0b0000>; -class V6_vS32Ub_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pi_128B<0b0111>; -class V6_vS32b_nt_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pi_128B<0b1000>; - -// TODO: Change script to generate src1, src2 and src3 instead of -// dst, src1, src2. -class Enc_COPROC_VMEM_vS32b_n_ew_pi<bits<1> opc> : OpcodeHexagon { - bits<5> src1; - bits<9> src2; - bits<3> src2_vector; - bits<3> src3; - - let src2_vector = src2{8-6}; - let Inst{31-16} = { 0b001010010, opc{0}, 1, src1{4-0} }; - let Inst{13-0} = { 0b000, src2_vector{2-0}, 0b00100, src3{2-0} }; -} - -class V6_vS32b_new_pi_enc : Enc_COPROC_VMEM_vS32b_n_ew_pi<0>; -class V6_vS32b_nt_new_pi_enc : Enc_COPROC_VMEM_vS32b_n_ew_pi<1>; - -class Enc_COPROC_VMEM_vS32b_n_ew_pi_128B<bits<1> opc> : OpcodeHexagon { - bits<5> src1; - bits<10> src2; - bits<3> src2_vector; - bits<3> src3; - - let src2_vector = src2{9-7}; - let Inst{31-16} = { 0b001010010, opc{0}, 1, src1{4-0} }; - let Inst{13-0} = { 0b000, src2_vector{2-0}, 0b00100, src3{2-0} }; -} - -class V6_vS32b_new_pi_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pi_128B<0>; -class V6_vS32b_nt_new_pi_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pi_128B<1>; - -// TODO: Change script to generate src1, src2,src3 and src4 instead of -// dst, src1, src2, src3. -class Enc_COPROC_VMEM_vS32_b_pred_pi<bits<5> opc> : OpcodeHexagon { - bits<2> src1; - bits<5> src2; - bits<9> src3; - bits<3> src3_vector; - bits<5> src4; - - let src3_vector = src3{8-6}; - let Inst{31-16} = { 0b001010011, opc{4-3}, src2{4-0} }; - let Inst{13-0} = { 0, src1{1-0}, src3_vector{2-0}, opc{2-0}, src4{4-0} }; -} - -class V6_vS32b_qpred_pi_enc : Enc_COPROC_VMEM_vS32_b_pred_pi<0b00000>; -class V6_vS32b_nqpred_pi_enc : Enc_COPROC_VMEM_vS32_b_pred_pi<0b00001>; -class V6_vS32b_pred_pi_enc : Enc_COPROC_VMEM_vS32_b_pred_pi<0b01000>; -class V6_vS32b_npred_pi_enc : Enc_COPROC_VMEM_vS32_b_pred_pi<0b01001>; -class V6_vS32Ub_pred_pi_enc : Enc_COPROC_VMEM_vS32_b_pred_pi<0b01110>; -class V6_vS32Ub_npred_pi_enc : Enc_COPROC_VMEM_vS32_b_pred_pi<0b01111>; -class V6_vS32b_nt_qpred_pi_enc : Enc_COPROC_VMEM_vS32_b_pred_pi<0b10000>; -class V6_vS32b_nt_nqpred_pi_enc : Enc_COPROC_VMEM_vS32_b_pred_pi<0b10001>; -class V6_vS32b_nt_pred_pi_enc : Enc_COPROC_VMEM_vS32_b_pred_pi<0b11000>; -class V6_vS32b_nt_npred_pi_enc : Enc_COPROC_VMEM_vS32_b_pred_pi<0b11001>; - -// TODO: Change script to generate src1, src2,src3 and src4 instead of -// dst, src1, src2, src3. -class Enc_COPROC_VMEM_vS32_b_pred_pi_128B<bits<5> opc> : OpcodeHexagon { - bits<2> src1; - bits<5> src2; - bits<10> src3; - bits<3> src3_vector; - bits<5> src4; - - let src3_vector = src3{9-7}; - let Inst{31-16} = { 0b001010011, opc{4-3}, src2{4-0} }; - let Inst{13-0} = { 0, src1{1-0}, src3_vector{2-0}, opc{2-0}, src4{4-0} }; -} - -class V6_vS32b_qpred_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_pi_128B<0b00000>; -class V6_vS32b_nqpred_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_pi_128B<0b00001>; -class V6_vS32b_pred_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_pi_128B<0b01000>; -class V6_vS32b_npred_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_pi_128B<0b01001>; -class V6_vS32Ub_pred_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_pi_128B<0b01110>; -class V6_vS32Ub_npred_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_pi_128B<0b01111>; -class V6_vS32b_nt_qpred_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_pi_128B<0b10000>; -class V6_vS32b_nt_nqpred_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_pi_128B<0b10001>; -class V6_vS32b_nt_pred_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_pi_128B<0b11000>; -class V6_vS32b_nt_npred_pi_128B_enc : Enc_COPROC_VMEM_vS32_b_pred_pi_128B<0b11001>; - -class Enc_COPROC_VMEM_vS32b_n_ew_pred_pi<bits<4> opc> : OpcodeHexagon { - bits<2> src1; - bits<5> src2; - bits<9> src3; - bits<3> src3_vector; - bits<3> src4; - - let src3_vector = src3{8-6}; - let Inst{31-16} = { 0b001010011, opc{3}, 1, src2{4-0} }; - let Inst{13-0} = { 0, src1{1-0}, src3_vector{2-0}, 0b01, opc{2-0}, src4{2-0} }; -} - -class V6_vS32b_new_pred_pi_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi<0b0000>; -class V6_vS32b_new_npred_pi_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi<0b0101>; -class V6_vS32b_nt_new_pred_pi_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi<0b1010>; -class V6_vS32b_nt_new_npred_pi_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi<0b1111>; - -class Enc_COPROC_VMEM_vS32b_n_ew_pred_pi_128B<bits<4> opc> : OpcodeHexagon { - bits<2> src1; - bits<5> src2; - bits<10> src3; - bits<3> src3_vector; - bits<3> src4; - - let src3_vector = src3{9-7}; - let Inst{31-16} = { 0b001010011, opc{3}, 1, src2{4-0} }; - let Inst{13-0} = { 0, src1{1-0}, src3_vector{2-0}, 0b01, opc{2-0}, src4{2-0} }; -} - -class V6_vS32b_new_pred_pi_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi_128B<0b0000>; -class V6_vS32b_new_npred_pi_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi_128B<0b0101>; -class V6_vS32b_nt_new_pred_pi_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi_128B<0b1010>; -class V6_vS32b_nt_new_npred_pi_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi_128B<0b1111>; - -class Enc_LD_load_m<bits<13> opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<1> src2; - - let Inst{31-16} = { opc{12}, 0, opc{11-10}, 1, opc{9-4}, src1{4-0} }; - let Inst{13-0} = { src2{0}, 0b000, opc{3}, 0, opc{2-0}, dst{4-0} }; -} - -class V6_vL32b_ppu_enc : Enc_LD_load_m<0b0100110000000>; -class V6_vL32b_cur_ppu_enc : Enc_LD_load_m<0b0100110000001>; -class V6_vL32b_tmp_ppu_enc : Enc_LD_load_m<0b0100110000010>; -class V6_vL32Ub_ppu_enc : Enc_LD_load_m<0b0100110000111>; -class V6_vL32b_nt_ppu_enc : Enc_LD_load_m<0b0100110100000>; -class V6_vL32b_nt_cur_ppu_enc : Enc_LD_load_m<0b0100110100001>; -class V6_vL32b_nt_tmp_ppu_enc : Enc_LD_load_m<0b0100110100010>; - -class Enc_COPROC_VMEM_vS32_b_ppu<bits<4> opc> : OpcodeHexagon { - bits<5> src1; - bits<1> src2; - bits<5> src3; - - let Inst{31-16} = { 0b001010110, opc{3}, 1, src1{4-0} }; - let Inst{13-0} = { src2{0}, 0b00000, opc{2-0}, src3{4-0} }; -} - -class V6_vS32b_ppu_enc : Enc_COPROC_VMEM_vS32_b_ppu<0b0000>; -class V6_vS32Ub_ppu_enc : Enc_COPROC_VMEM_vS32_b_ppu<0b0111>; -class V6_vS32b_nt_ppu_enc : Enc_COPROC_VMEM_vS32_b_ppu<0b1000>; - -class Enc_COPROC_VMEM_vS32b_new_ppu<bits<1> opc> : OpcodeHexagon { - bits<5> src1; - bits<1> src2; - bits<3> src3; - - let Inst{31-16} = { 0b001010110, opc{0}, 1, src1{4-0} }; - let Inst{13-0} = { src2{0}, 0b0000000100, src3{2-0} }; -} - -class V6_vS32b_new_ppu_enc : Enc_COPROC_VMEM_vS32b_new_ppu<0>; -class V6_vS32b_nt_new_ppu_enc : Enc_COPROC_VMEM_vS32b_new_ppu<1>; - -class Enc_COPROC_VMEM_vS32_b_pred_ppu<bits<5> opc> : OpcodeHexagon { - bits<2> src1; - bits<5> src2; - bits<1> src3; - bits<5> src4; - - let Inst{31-16} = { 0b001010111, opc{4-3}, src2{4-0} }; - let Inst{13-0} = { src3{0}, src1{1-0}, 0b000, opc{2-0}, src4{4-0} }; -} - -class V6_vS32b_qpred_ppu_enc : Enc_COPROC_VMEM_vS32_b_pred_ppu<0b00000>; -class V6_vS32b_nqpred_ppu_enc : Enc_COPROC_VMEM_vS32_b_pred_ppu<0b00001>; -class V6_vS32b_pred_ppu_enc : Enc_COPROC_VMEM_vS32_b_pred_ppu<0b01000>; -class V6_vS32b_npred_ppu_enc : Enc_COPROC_VMEM_vS32_b_pred_ppu<0b01001>; -class V6_vS32Ub_pred_ppu_enc : Enc_COPROC_VMEM_vS32_b_pred_ppu<0b01110>; -class V6_vS32Ub_npred_ppu_enc : Enc_COPROC_VMEM_vS32_b_pred_ppu<0b01111>; -class V6_vS32b_nt_qpred_ppu_enc : Enc_COPROC_VMEM_vS32_b_pred_ppu<0b10000>; -class V6_vS32b_nt_nqpred_ppu_enc : Enc_COPROC_VMEM_vS32_b_pred_ppu<0b10001>; -class V6_vS32b_nt_pred_ppu_enc : Enc_COPROC_VMEM_vS32_b_pred_ppu<0b11000>; -class V6_vS32b_nt_npred_ppu_enc : Enc_COPROC_VMEM_vS32_b_pred_ppu<0b11001>; - -class Enc_COPROC_VMEM_vS32b_n_ew_pred_ppu<bits<4> opc> : OpcodeHexagon { - bits<2> src1; - bits<5> src2; - bits<1> src3; - bits<3> src4; - - let Inst{31-16} = { 0b001010111, opc{3}, 1, src2{4-0} }; - let Inst{13-0} = { src3{0}, src1{1-0}, 0b00001, opc{2-0}, src4{2-0} }; -} - -class V6_vS32b_new_pred_ppu_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ppu<0b0000>; -class V6_vS32b_new_npred_ppu_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ppu<0b0101>; -class V6_vS32b_nt_new_pred_ppu_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ppu<0b1010>; -class V6_vS32b_nt_new_npred_ppu_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ppu<0b1111>; - - -class Enc_COPROC_VX_4op_i<bits<5> opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<5> src2; - bits<1> src3; - - let Inst{31-16} = { 0b00011001, opc{4-2}, src2{4-0} }; - let Inst{13-0} = { opc{1}, src1{4-0}, 1, opc{0}, src3{0}, dst{4-0} }; -} - -class V6_vrmpybusi_enc : Enc_COPROC_VX_4op_i<0b01000>; -class V6_vrsadubi_enc : Enc_COPROC_VX_4op_i<0b01001>; -class V6_vrmpybusi_acc_enc : Enc_COPROC_VX_4op_i<0b01010>; -class V6_vrsadubi_acc_enc : Enc_COPROC_VX_4op_i<0b01011>; -class V6_vrmpyubi_acc_enc : Enc_COPROC_VX_4op_i<0b01111>; -class V6_vrmpyubi_enc : Enc_COPROC_VX_4op_i<0b10101>; - -class Enc_COPROC_VX_vandqrt<bits<5> opc> : OpcodeHexagon { - bits<5> dst; - bits<2> src1; - bits<5> src2; - - let Inst{31-16} = { 0b00011001, opc{4-3}, 1, src2{4-0} }; - let Inst{13-0} = { opc{2}, 0b000, src1{1-0}, opc{1-0}, 1, dst{4-0} }; -} - -class V6_vandqrt_acc_enc : Enc_COPROC_VX_vandqrt<0b01101>; -class V6_vandqrt_enc : Enc_COPROC_VX_vandqrt<0b10010>; - -class Enc_COPROC_VX_cards<bits<2> opc> : OpcodeHexagon { - bits<5> src1; - bits<5> src2; - bits<5> src3; - - let Inst{31-16} = { 0b00011001111, src3{4-0} }; - let Inst{13-0} = { 1, src1{4-0}, 0, opc{1-0}, src2{4-0} }; -} - -class V6_vshuff_enc : Enc_COPROC_VX_cards<0b01>; -class V6_vdeal_enc : Enc_COPROC_VX_cards<0b10>; - - -class Enc_COPROC_VX_v_cmov<bits<1> opc> : OpcodeHexagon { - bits<2> src1; - bits<5> dst; - bits<5> src2; - - let Inst{31-16} = { 0b0001101000, opc{0}, 0b00000 }; - let Inst{13-0} = { 0, src2{4-0}, 0, src1{1-0}, dst{4-0} }; -} - -class V6_vcmov_enc : Enc_COPROC_VX_v_cmov<0>; -class V6_vncmov_enc : Enc_COPROC_VX_v_cmov<1>; - -class Enc_X_p3op<bits<8> opc> : OpcodeHexagon { - bits<2> src1; - bits<5> dst; - bits<5> src2; - bits<5> src3; - - let Inst{31-16} = { opc{7-5}, 0b1101, opc{4}, 0, opc{3-2}, src3{4-0} }; - let Inst{13-0} = { opc{1}, src2{4-0}, opc{0}, src1{1-0}, dst{4-0} }; -} - -class V6_vnccombine_enc : Enc_X_p3op<0b00001000>; -class V6_vccombine_enc : Enc_X_p3op<0b00001100>; - -class Enc_COPROC_VX_4op_r<bits<4> opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<5> src2; - bits<3> src3; - - let Inst{31-16} = { 0b00011011, src2{4-0}, src3{2-0} }; - let Inst{13-0} = { opc{3}, src1{4-0}, opc{2-0}, dst{4-0} }; -} - -class V6_valignb_enc : Enc_COPROC_VX_4op_r<0b0000>; -class V6_vlalignb_enc : Enc_COPROC_VX_4op_r<0b0001>; -class V6_vasrwh_enc : Enc_COPROC_VX_4op_r<0b0010>; -class V6_vasrwhsat_enc : Enc_COPROC_VX_4op_r<0b0011>; -class V6_vasrwhrndsat_enc : Enc_COPROC_VX_4op_r<0b0100>; -class V6_vasrwuhsat_enc : Enc_COPROC_VX_4op_r<0b0101>; -class V6_vasrhubsat_enc : Enc_COPROC_VX_4op_r<0b0110>; -class V6_vasrhubrndsat_enc : Enc_COPROC_VX_4op_r<0b0111>; -class V6_vasrhbrndsat_enc : Enc_COPROC_VX_4op_r<0b1000>; -class V6_vlutvvb_enc : Enc_COPROC_VX_4op_r<0b1001>; -class V6_vshuffvdd_enc : Enc_COPROC_VX_4op_r<0b1011>; -class V6_vdealvdd_enc : Enc_COPROC_VX_4op_r<0b1100>; -class V6_vlutvvb_oracc_enc : Enc_COPROC_VX_4op_r<0b1101>; -class V6_vlutvwh_enc : Enc_COPROC_VX_4op_r<0b1110>; -class V6_vlutvwh_oracc_enc : Enc_COPROC_VX_4op_r<0b1111>; - -class Enc_S_3op_valign_i<bits<9> opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<5> src2; - bits<3> src3; - - let Inst{31-16} = { opc{8-7}, 0, opc{6-3}, 0b00, opc{2-1}, src2{4-0} }; - let Inst{13-0} = { opc{0}, src1{4-0}, src3{2-0}, dst{4-0} }; -} - -class V6_vlutb_enc : Enc_S_3op_valign_i<0b001100000>; -class V6_vlutb_dv_enc : Enc_S_3op_valign_i<0b001100010>; -class V6_vlutb_acc_enc : Enc_S_3op_valign_i<0b001100100>; -class V6_vlutb_dv_acc_enc : Enc_S_3op_valign_i<0b001100110>; -class V6_valignbi_enc : Enc_S_3op_valign_i<0b001111011>; -class V6_vlalignbi_enc : Enc_S_3op_valign_i<0b001111111>; -class S2_valignib_enc : Enc_S_3op_valign_i<0b110000000>; -class S2_addasl_rrri_enc : Enc_S_3op_valign_i<0b110010000>; - -class Enc_COPROC_VX_3op_q<bits<3> opc> : OpcodeHexagon { - bits<2> dst; - bits<2> src1; - bits<2> src2; - - let Inst{31-16} = { 0b00011110, src2{1-0}, 0b000011 }; - let Inst{13-0} = { 0b0000, src1{1-0}, 0b000, opc{2-0}, dst{1-0} }; -} - -class V6_pred_and_enc : Enc_COPROC_VX_3op_q<0b000>; -class V6_pred_or_enc : Enc_COPROC_VX_3op_q<0b001>; -class V6_pred_xor_enc : Enc_COPROC_VX_3op_q<0b011>; -class V6_pred_or_n_enc : Enc_COPROC_VX_3op_q<0b100>; -class V6_pred_and_n_enc : Enc_COPROC_VX_3op_q<0b101>; - -class V6_pred_not_enc : OpcodeHexagon { - bits<2> dst; - bits<2> src1; - - let Inst{31-16} = { 0b0001111000000011 }; - let Inst{13-0} = { 0b0000, src1{1-0}, 0b000010, dst{1-0} }; -} - -class Enc_COPROC_VX_4op_q<bits<1> opc> : OpcodeHexagon { - bits<5> dst; - bits<2> src1; - bits<5> src2; - bits<5> src3; - - let Inst{31-16} = { 0b000111101, opc{0}, 1, src3{4-0} }; - let Inst{13-0} = { 1, src2{4-0}, 0, src1{1-0}, dst{4-0} }; -} - -class V6_vswap_enc : Enc_COPROC_VX_4op_q<0>; -class V6_vmux_enc : Enc_COPROC_VX_4op_q<1>; - -class Enc_X_2op<bits<16> opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - - let Inst{31-16} = { opc{15-5}, src1{4-0} }; - let Inst{13-0} = { opc{4-3}, 0b0000, opc{2-0}, dst{4-0} }; -} - -class V6_lvsplatw_enc : Enc_X_2op<0b0001100110100001>; -class V6_vinsertwr_enc : Enc_X_2op<0b0001100110110001>; -class S6_vsplatrbp_enc : Enc_X_2op<0b1000010001000100>; - - -class Enc_CR_2op_r<bits<12> opc> : OpcodeHexagon { - bits<2> dst; - bits<5> src1; - - let Inst{31-16} = { opc{11}, 0, opc{10-7}, 0, opc{6-3}, src1{4-0} }; - let Inst{13-0} = { opc{2}, 0b000000, opc{1}, 0b000, opc{0}, dst{1-0} }; -} - -class V6_pred_scalar2_enc : Enc_CR_2op_r<0b001101101011>; -class Y5_l2locka_enc : Enc_CR_2op_r<0b110000111100>; - -class Enc_S_3op_i6<bits<9> opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<6> src2; - - let Inst{31-16} = { 0b1000, opc{8-6}, 0, opc{5-3}, src1{4-0} }; - let Inst{13-0} = { src2{5-0}, opc{2-0}, dst{4-0} }; -} - -class S6_rol_i_p_enc : Enc_S_3op_i6<0b000000011>; -class S6_rol_i_p_nac_enc : Enc_S_3op_i6<0b001000011>; -class S6_rol_i_p_acc_enc : Enc_S_3op_i6<0b001000111>; -class S6_rol_i_p_and_enc : Enc_S_3op_i6<0b001010011>; -class S6_rol_i_p_or_enc : Enc_S_3op_i6<0b001010111>; -class S6_rol_i_p_xacc_enc : Enc_S_3op_i6<0b001100011>; - -class Enc_X_3op_r<bits<15> opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<5> src2; - - let Inst{31-16} = { opc{14-4}, src1{4-0} }; - let Inst{13-0} = { opc{3}, src2{4-0}, opc{2-0}, dst{4-0} }; -} - -class S6_rol_i_r_enc : Enc_X_3op_r<0b100011000000011>; -class S6_rol_i_r_nac_enc : Enc_X_3op_r<0b100011100000011>; -class S6_rol_i_r_acc_enc : Enc_X_3op_r<0b100011100000111>; -class S6_rol_i_r_and_enc : Enc_X_3op_r<0b100011100100011>; -class S6_rol_i_r_or_enc : Enc_X_3op_r<0b100011100100111>; -class S6_rol_i_r_xacc_enc : Enc_X_3op_r<0b100011101000011>; -class S6_vtrunehb_ppp_enc : Enc_X_3op_r<0b110000011000011>; -class S6_vtrunohb_ppp_enc : Enc_X_3op_r<0b110000011000101>; - -class Enc_no_operands<bits<25> opc> : OpcodeHexagon { - - let Inst{31-16} = { opc{24-10}, 0 }; - let Inst{13-0} = { opc{9-7}, 0b000, opc{6-0}, 0 }; -} - -class Y5_l2gunlock_enc : Enc_no_operands<0b1010100000100000010000000>; -class Y5_l2gclean_enc : Enc_no_operands<0b1010100000100000100000000>; -class Y5_l2gcleaninv_enc : Enc_no_operands<0b1010100000100000110000000>; -class V6_vhist_enc : Enc_no_operands<0b0001111000000001001000000>; - -class Enc_J_jumpr<bits<13> opc> : OpcodeHexagon { - bits<5> src1; - - let Inst{31-16} = { opc{12-6}, 0, opc{5-3}, src1{4-0} }; - let Inst{13-0} = { 0b00, opc{2}, 0b0000, opc{1-0}, 0b00000 }; -} - -class Y5_l2unlocka_enc : Enc_J_jumpr<0b1010011011000>; -class Y2_l2cleaninvidx_enc : Enc_J_jumpr<0b1010100011000>; - -class Enc_ST_l2gclean_pa<bits<2> opc> : OpcodeHexagon { - bits<5> src1; - - let Inst{31-16} = { 0b101001101, opc{1-0}, 0b00000 }; - let Inst{13-0} = { 0, src1{4-0}, 0b00000000 }; -} - -class Y6_l2gcleanpa_enc : Enc_ST_l2gclean_pa<0b01>; -class Y6_l2gcleaninvpa_enc : Enc_ST_l2gclean_pa<0b10>; - -class A5_ACS_enc : OpcodeHexagon { - bits<5> dst1; - bits<2> dst2; - bits<5> src1; - bits<5> src2; - - let Inst{31-16} = { 0b11101010101, src1{4-0} }; - let Inst{13-0} = { 0, src2{4-0}, 0, dst2{1-0}, dst1{4-0} }; -} - -class Enc_X_4op_r<bits<8> opc> : OpcodeHexagon { - bits<5> dst; - bits<5> src1; - bits<5> src2; - bits<2> src3; - - let Inst{31-16} = { 0b11, opc{7}, 0, opc{6-5}, 1, opc{4-1}, src1{4-0} }; - let Inst{13-0} = { 0, src2{4-0}, opc{0}, src3{1-0}, dst{4-0} }; -} - -class S2_vsplicerb_enc : Enc_X_4op_r<0b00001000>; -class S2_cabacencbin_enc : Enc_X_4op_r<0b00001010>; -class F2_sffma_sc_enc : Enc_X_4op_r<0b11110111>; - -class V6_vhistq_enc : OpcodeHexagon { - bits<2> src1; - - let Inst{31-16} = { 0b00011110, src1{1-0}, 0b000010 }; - let Inst{13-0} = { 0b10000010000000 }; -} - -// TODO: Change script to generate dst1 instead of dst. -class A6_vminub_RdP_enc : OpcodeHexagon { - bits<5> dst1; - bits<2> dst2; - bits<5> src1; - bits<5> src2; - - let Inst{31-16} = { 0b11101010111, src2{4-0} }; - let Inst{13-0} = { 0, src1{4-0}, 0, dst2{1-0}, dst1{4-0} }; -} diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonInstrFormats.td b/contrib/llvm/lib/Target/Hexagon/HexagonInstrFormats.td index fa3cccbd0879..39c2a6e4f5a5 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/contrib/llvm/lib/Target/Hexagon/HexagonInstrFormats.td @@ -7,26 +7,6 @@ // //===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// Hexagon Instruction Flags + -// -// *** Must match HexagonBaseInfo.h *** -//===----------------------------------------------------------------------===// - -class IType<bits<5> t> { - bits<5> Value = t; -} -def TypePSEUDO : IType<0>; -def TypeALU32 : IType<1>; -def TypeCR : IType<2>; -def TypeJR : IType<3>; -def TypeJ : IType<4>; -def TypeLD : IType<5>; -def TypeST : IType<6>; -def TypeSYSTEM : IType<7>; -def TypeXTYPE : IType<8>; -def TypeENDLOOP: IType<31>; - // Maintain list of valid subtargets for each instruction. class SubTarget<bits<6> value> { bits<6> Value = value; @@ -54,6 +34,7 @@ class MemAccessSize<bits<4> value> { bits<4> Value = value; } +// MemAccessSize is represented as 1+log2(N) where N is size in bits. def NoMemAccess : MemAccessSize<0>;// Not a memory access instruction. def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb). def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh). @@ -70,10 +51,9 @@ def Vector128Access : MemAccessSize<8>;// Vector access instruction (memv) class OpcodeHexagon { field bits<32> Inst = ?; // Default to an invalid insn. bits<4> IClass = 0; // ICLASS + bits<1> zero = 0; let Inst{31-28} = IClass; - - bits<1> zero = 0; } class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, @@ -99,85 +79,88 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, // Instruction type according to the ISA. IType Type = type; - let TSFlags{4-0} = Type.Value; + let TSFlags{5-0} = Type.Value; // Solo instructions, i.e., those that cannot be in a packet with others. bits<1> isSolo = 0; - let TSFlags{5} = isSolo; + let TSFlags{6} = isSolo; // Packed only with A or X-type instructions. bits<1> isSoloAX = 0; - let TSFlags{6} = isSoloAX; + let TSFlags{7} = isSoloAX; // Only A-type instruction in first slot or nothing. bits<1> isSoloAin1 = 0; - let TSFlags{7} = isSoloAin1; + let TSFlags{8} = isSoloAin1; // Predicated instructions. bits<1> isPredicated = 0; - let TSFlags{8} = isPredicated; + let TSFlags{9} = isPredicated; bits<1> isPredicatedFalse = 0; - let TSFlags{9} = isPredicatedFalse; + let TSFlags{10} = isPredicatedFalse; bits<1> isPredicatedNew = 0; - let TSFlags{10} = isPredicatedNew; + let TSFlags{11} = isPredicatedNew; bits<1> isPredicateLate = 0; - let TSFlags{11} = isPredicateLate; // Late predicate producer insn. + let TSFlags{12} = isPredicateLate; // Late predicate producer insn. // New-value insn helper fields. bits<1> isNewValue = 0; - let TSFlags{12} = isNewValue; // New-value consumer insn. + let TSFlags{13} = isNewValue; // New-value consumer insn. bits<1> hasNewValue = 0; - let TSFlags{13} = hasNewValue; // New-value producer insn. + let TSFlags{14} = hasNewValue; // New-value producer insn. bits<3> opNewValue = 0; - let TSFlags{16-14} = opNewValue; // New-value produced operand. + let TSFlags{17-15} = opNewValue; // New-value produced operand. bits<1> isNVStorable = 0; - let TSFlags{17} = isNVStorable; // Store that can become new-value store. + let TSFlags{18} = isNVStorable; // Store that can become new-value store. bits<1> isNVStore = 0; - let TSFlags{18} = isNVStore; // New-value store insn. + let TSFlags{19} = isNVStore; // New-value store insn. bits<1> isCVLoadable = 0; - let TSFlags{19} = isCVLoadable; // Load that can become cur-value load. + let TSFlags{20} = isCVLoadable; // Load that can become cur-value load. bits<1> isCVLoad = 0; - let TSFlags{20} = isCVLoad; // Cur-value load insn. + let TSFlags{21} = isCVLoad; // Cur-value load insn. // Immediate extender helper fields. bits<1> isExtendable = 0; - let TSFlags{21} = isExtendable; // Insn may be extended. + let TSFlags{22} = isExtendable; // Insn may be extended. bits<1> isExtended = 0; - let TSFlags{22} = isExtended; // Insn must be extended. + let TSFlags{23} = isExtended; // Insn must be extended. bits<3> opExtendable = 0; - let TSFlags{25-23} = opExtendable; // Which operand may be extended. + let TSFlags{26-24} = opExtendable; // Which operand may be extended. bits<1> isExtentSigned = 0; - let TSFlags{26} = isExtentSigned; // Signed or unsigned range. + let TSFlags{27} = isExtentSigned; // Signed or unsigned range. bits<5> opExtentBits = 0; - let TSFlags{31-27} = opExtentBits; //Number of bits of range before extending. + let TSFlags{32-28} = opExtentBits; //Number of bits of range before extending. bits<2> opExtentAlign = 0; - let TSFlags{33-32} = opExtentAlign; // Alignment exponent before extending. + let TSFlags{34-33} = opExtentAlign; // Alignment exponent before extending. // If an instruction is valid on a subtarget, set the corresponding // bit from validSubTargets. // By default, instruction is valid on all subtargets. SubTarget validSubTargets = HasAnySubT; - let TSFlags{39-34} = validSubTargets.Value; + let TSFlags{40-35} = validSubTargets.Value; // Addressing mode for load/store instructions. AddrModeType addrMode = NoAddrMode; - let TSFlags{42-40} = addrMode.Value; + let TSFlags{43-41} = addrMode.Value; // Memory access size for mem access instructions (load/store) MemAccessSize accessSize = NoMemAccess; - let TSFlags{46-43} = accessSize.Value; + let TSFlags{47-44} = accessSize.Value; bits<1> isTaken = 0; - let TSFlags {47} = isTaken; // Branch prediction. + let TSFlags {48} = isTaken; // Branch prediction. bits<1> isFP = 0; - let TSFlags {48} = isFP; // Floating-point. + let TSFlags {49} = isFP; // Floating-point. bits<1> hasNewValue2 = 0; - let TSFlags{50} = hasNewValue2; // Second New-value producer insn. + let TSFlags{51} = hasNewValue2; // Second New-value producer insn. bits<3> opNewValue2 = 0; - let TSFlags{53-51} = opNewValue2; // Second New-value produced operand. + let TSFlags{54-52} = opNewValue2; // Second New-value produced operand. bits<1> isAccumulator = 0; - let TSFlags{54} = isAccumulator; + let TSFlags{55} = isAccumulator; + + bits<1> prefersSlot3 = 0; + let TSFlags{56} = prefersSlot3; // Complex XU bit cofMax1 = 0; let TSFlags{60} = cofMax1; @@ -200,9 +183,13 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, let NValueST = !if(isNVStore, "true", "false"); let isNT = !if(isNonTemporal, "true", "false"); + let hasSideEffects = 0; // *** Must match MCTargetDesc/HexagonBaseInfo.h *** } +class HInst<dag outs, dag ins, string asmstr, InstrItinClass itin, IType type> : + InstHexagon<outs, ins, asmstr, [], "", itin, type>; + //===----------------------------------------------------------------------===// // Instruction Classes Definitions + //===----------------------------------------------------------------------===// @@ -214,14 +201,13 @@ class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01> : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon; -let mayLoad = 1 in -class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = ""> - : LDInst<outs, ins, asmstr, pattern, cstr>; +class PseudoLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon; class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = ""> - : LDInst<outs, ins, asmstr, pattern, cstr>; + : PseudoLDInst<outs, ins, asmstr, pattern, cstr>; // LD Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. @@ -247,6 +233,11 @@ class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01> : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon; +let mayStore = 1 in +class STInst_NoOpcode<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>; + class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = ""> : STInst<outs, ins, asmstr, pattern, cstr>; @@ -269,28 +260,24 @@ class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01> : STInst<outs, ins, asmstr, pattern, cstr, itin>; -// SYSTEM Instruction Class in V4 can take SLOT0 only -// In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1. -class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = ST_tc_3stall_SLOT0> - : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeSYSTEM>, - OpcodeHexagon; - -// ALU32 Instruction Class in V2/V3/V4. -// Definition of the instruction class NOT CHANGED. -class ALU32Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> - : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU32>, OpcodeHexagon; - // ALU64 Instruction Class in V2/V3. // XTYPE Instruction Class in V4. // Definition of the instruction class NOT CHANGED. // Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4. class ALU64Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23> - : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>, + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU64>, OpcodeHexagon; +// ALU64 Instruction Class in V2/V3. +// XTYPE Instruction Class in V4. +// Definition of the instruction class NOT CHANGED. +// Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4. +class ALU64Inst_NoOpcode<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU64>; + + class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23> : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>; @@ -302,13 +289,13 @@ class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [], // Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4. class MInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23> - : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>, + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeM>, OpcodeHexagon; // Same as above but doesn't derive from OpcodeHexagon class MInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23> - : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>; + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeM>; // M Instruction Class in V2/V3. // XTYPE Instruction Class in V4. @@ -324,12 +311,16 @@ class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [], // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4. class SInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23> - : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>, + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeS_2op>, OpcodeHexagon; +class SInst_NoOpcode<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeS_2op>; + class SInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23> - : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>; + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeS_2op>; // S Instruction Class in V2/V3. // XTYPE Instruction Class in V4. @@ -337,7 +328,9 @@ class SInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [], // Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4. class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = S_3op_tc_1_SLOT23> - : SInst<outs, ins, asmstr, pattern, cstr, itin>; + : SInst<outs, ins, asmstr, pattern, cstr, itin> { + let Type = TypeS_3op; +} // J Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. @@ -349,12 +342,6 @@ class JInst_CJUMP_UCJUMP<dag outs, dag ins, string asmstr, list<dag> pattern = [ string cstr = "", InstrItinClass itin = J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT> : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>, OpcodeHexagon; -// JR Instruction Class in V2/V3/V4. -// Definition of the instruction class NOT CHANGED. -class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = J_tc_2early_SLOT2> - : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJR>, OpcodeHexagon; - // CR Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], @@ -383,26 +370,6 @@ class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [], // Instruction Classes Definitions - //===----------------------------------------------------------------------===// - -// -// ALU32 patterns -//. -class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> - : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; - -class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> - : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; - -class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> - : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; - -class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> - : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; - // // ALU64 patterns. // diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonInstrFormatsV4.td b/contrib/llvm/lib/Target/Hexagon/HexagonInstrFormatsV4.td index 493d04703da9..1fdf930c62fd 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonInstrFormatsV4.td +++ b/contrib/llvm/lib/Target/Hexagon/HexagonInstrFormatsV4.td @@ -11,18 +11,6 @@ // //===----------------------------------------------------------------------===// -//----------------------------------------------------------------------------// -// Hexagon Instruction Flags -// -// *** Must match BaseInfo.h *** -//----------------------------------------------------------------------------// - -def TypeV4LDST : IType<9>; -def TypeNV : IType<10>; -def TypeDUPLEX : IType<11>; -def TypeCOMPOUND : IType<12>; -def TypePREFIX : IType<30>; - // Duplex Instruction Class Declaration //===----------------------------------------------------------------------===// @@ -61,7 +49,7 @@ class InstDuplex<bits<4> iClass, list<dag> pattern = [], // *** Must match MCTargetDesc/HexagonBaseInfo.h *** - let TSFlags{4-0} = Type.Value; + let TSFlags{5-0} = Type.Value; // Predicated instructions. bits<1> isPredicated = 0; @@ -107,7 +95,7 @@ class InstDuplex<bits<4> iClass, list<dag> pattern = [], // class NVInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = NCJ_tc_3or4stall_SLOT0> - : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeNV>, OpcodeHexagon; + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeNCJ>, OpcodeHexagon; class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = NCJ_tc_3or4stall_SLOT0> @@ -141,7 +129,7 @@ class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [], class EXTENDERInst<dag outs, dag ins, string asmstr, list<dag> pattern = []> : InstHexagon<outs, ins, asmstr, pattern, "", EXTENDER_tc_1_SLOT0123, - TypePREFIX>, OpcodeHexagon; + TypeEXTENDER>, OpcodeHexagon; class SUBInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = ""> @@ -150,11 +138,11 @@ class SUBInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], class CJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, + : InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>, OpcodeHexagon; class CJInst_JMPSET<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = ""> - : InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND, TypeCOMPOUND>, + : InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND, TypeCJ>, OpcodeHexagon; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonInstrFormatsV60.td b/contrib/llvm/lib/Target/Hexagon/HexagonInstrFormatsV60.td index b9f4373a0b79..c8a7faea5ed5 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonInstrFormatsV60.td +++ b/contrib/llvm/lib/Target/Hexagon/HexagonInstrFormatsV60.td @@ -12,28 +12,6 @@ //===----------------------------------------------------------------------===// //----------------------------------------------------------------------------// -// Hexagon Instruction Flags + -// -// *** Must match BaseInfo.h *** -//----------------------------------------------------------------------------// - -def TypeCVI_VA : IType<13>; -def TypeCVI_VA_DV : IType<14>; -def TypeCVI_VX : IType<15>; -def TypeCVI_VX_DV : IType<16>; -def TypeCVI_VP : IType<17>; -def TypeCVI_VP_VS : IType<18>; -def TypeCVI_VS : IType<19>; -def TypeCVI_VINLANESAT : IType<20>; -def TypeCVI_VM_LD : IType<21>; -def TypeCVI_VM_TMP_LD : IType<22>; -def TypeCVI_VM_CUR_LD : IType<23>; -def TypeCVI_VM_VP_LDU : IType<24>; -def TypeCVI_VM_ST : IType<25>; -def TypeCVI_VM_NEW_ST : IType<26>; -def TypeCVI_VM_STU : IType<27>; -def TypeCVI_HIST : IType<28>; -//----------------------------------------------------------------------------// // Instruction Classes Definitions + //----------------------------------------------------------------------------// diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 0a7dc6b49d00..b265a883da5c 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -152,10 +152,11 @@ static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB, /// On Hexagon, we have two instructions used to set-up the hardware loop /// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions /// to indicate the end of a loop. -static MachineInstr *findLoopInstr(MachineBasicBlock *BB, int EndLoopOp, +static MachineInstr *findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp, + MachineBasicBlock *TargetBB, SmallPtrSet<MachineBasicBlock *, 8> &Visited) { - int LOOPi; - int LOOPr; + unsigned LOOPi; + unsigned LOOPr; if (EndLoopOp == Hexagon::ENDLOOP0) { LOOPi = Hexagon::J2_loop0i; LOOPr = Hexagon::J2_loop0r; @@ -165,26 +166,24 @@ static MachineInstr *findLoopInstr(MachineBasicBlock *BB, int EndLoopOp, } // The loop set-up instruction will be in a predecessor block - for (MachineBasicBlock::pred_iterator PB = BB->pred_begin(), - PE = BB->pred_end(); PB != PE; ++PB) { + for (MachineBasicBlock *PB : BB->predecessors()) { // If this has been visited, already skip it. - if (!Visited.insert(*PB).second) + if (!Visited.insert(PB).second) continue; - if (*PB == BB) + if (PB == BB) continue; - for (MachineBasicBlock::reverse_instr_iterator I = (*PB)->instr_rbegin(), - E = (*PB)->instr_rend(); I != E; ++I) { - int Opc = I->getOpcode(); + for (auto I = PB->instr_rbegin(), E = PB->instr_rend(); I != E; ++I) { + unsigned Opc = I->getOpcode(); if (Opc == LOOPi || Opc == LOOPr) return &*I; - // We've reached a different loop, which means the loop0 has been removed. - if (Opc == EndLoopOp) + // We've reached a different loop, which means the loop01 has been + // removed. + if (Opc == EndLoopOp && I->getOperand(0).getMBB() != TargetBB) return nullptr; } // Check the predecessors for the LOOP instruction. - MachineInstr *loop = findLoopInstr(*PB, EndLoopOp, Visited); - if (loop) - return loop; + if (MachineInstr *Loop = findLoopInstr(PB, EndLoopOp, TargetBB, Visited)) + return Loop; } return nullptr; } @@ -597,7 +596,8 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB, // Since we're adding an ENDLOOP, there better be a LOOP instruction. // Check for it, and change the BB target if needed. SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs; - MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, VisitedBBs); + MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(), + VisitedBBs); assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP"); Loop->getOperand(0).setMBB(TBB); // Add the ENDLOOP after the finding the LOOP0. @@ -637,7 +637,8 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB, // Since we're adding an ENDLOOP, there better be a LOOP instruction. // Check for it, and change the BB target if needed. SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs; - MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, VisitedBBs); + MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, Cond[1].getMBB(), + VisitedBBs); assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP"); Loop->getOperand(0).setMBB(TBB); // Add the ENDLOOP after the finding the LOOP0. @@ -687,7 +688,8 @@ unsigned HexagonInstrInfo::reduceLoopCount(MachineBasicBlock &MBB, MachineFunction *MF = MBB.getParent(); DebugLoc DL = Cmp.getDebugLoc(); SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs; - MachineInstr *Loop = findLoopInstr(&MBB, Cmp.getOpcode(), VisitedBBs); + MachineInstr *Loop = findLoopInstr(&MBB, Cmp.getOpcode(), + Cmp.getOperand(0).getMBB(), VisitedBBs); if (!Loop) return 0; // If the loop trip count is a compile-time value, then just change the @@ -1074,13 +1076,13 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6; MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc)) - .addOperand(MI.getOperand(0)) + .add(MI.getOperand(0)) .addImm(MI.getOperand(1).getImm()) .addReg(SrcSubLo) .setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); MI1New->getOperand(0).setIsKill(false); BuildMI(MBB, MI, DL, get(NewOpc)) - .addOperand(MI.getOperand(0)) + .add(MI.getOperand(0)) // The Vectors are indexed in multiples of vector size. .addImm(MI.getOperand(1).getImm() + Offset) .addReg(SrcSubHi) @@ -1106,15 +1108,13 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { unsigned DstReg = MI.getOperand(0).getReg(); unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6; - MachineInstr *MI1New = - BuildMI(MBB, MI, DL, get(NewOpc), - HRI.getSubReg(DstReg, Hexagon::vsub_lo)) - .addOperand(MI.getOperand(1)) - .addImm(MI.getOperand(2).getImm()); + MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc), + HRI.getSubReg(DstReg, Hexagon::vsub_lo)) + .add(MI.getOperand(1)) + .addImm(MI.getOperand(2).getImm()); MI1New->getOperand(1).setIsKill(false); - BuildMI(MBB, MI, DL, get(NewOpc), - HRI.getSubReg(DstReg, Hexagon::vsub_hi)) - .addOperand(MI.getOperand(1)) + BuildMI(MBB, MI, DL, get(NewOpc), HRI.getSubReg(DstReg, Hexagon::vsub_hi)) + .add(MI.getOperand(1)) // The Vectors are indexed in multiples of vector size. .addImm(MI.getOperand(2).getImm() + Offset) .setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); @@ -1227,18 +1227,18 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg()); if (Op0.getReg() != Op2.getReg()) { auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov)) - .addOperand(Op0) - .addOperand(Op1) - .addOperand(Op2); + .add(Op0) + .add(Op1) + .add(Op2); if (IsDestLive) T.addReg(Op0.getReg(), RegState::Implicit); IsDestLive = true; } if (Op0.getReg() != Op3.getReg()) { auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov)) - .addOperand(Op0) - .addOperand(Op1) - .addOperand(Op3); + .add(Op0) + .add(Op1) + .add(Op3); if (IsDestLive) T.addReg(Op0.getReg(), RegState::Implicit); } @@ -1259,10 +1259,10 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { unsigned SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo); unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi); auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine)) - .addOperand(Op0) - .addOperand(Op1) - .addReg(SrcHi) - .addReg(SrcLo); + .add(Op0) + .add(Op1) + .addReg(SrcHi) + .addReg(SrcLo); if (IsDestLive) T.addReg(Op0.getReg(), RegState::Implicit); IsDestLive = true; @@ -1271,10 +1271,10 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { unsigned SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo); unsigned SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi); auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine)) - .addOperand(Op0) - .addOperand(Op1) - .addReg(SrcHi) - .addReg(SrcLo); + .add(Op0) + .add(Op1) + .addReg(SrcHi) + .addReg(SrcLo); if (IsDestLive) T.addReg(Op0.getReg(), RegState::Implicit); } @@ -1376,7 +1376,7 @@ bool HexagonInstrInfo::PredicateInstruction( MachineOperand &Op = MI.getOperand(NOp); if (!Op.isReg() || !Op.isDef() || Op.isImplicit()) break; - T.addOperand(Op); + T.add(Op); NOp++; } @@ -1386,7 +1386,7 @@ bool HexagonInstrInfo::PredicateInstruction( assert(GotPredReg); T.addReg(PredReg, PredRegFlags); while (NOp < NumOps) - T.addOperand(MI.getOperand(NOp++)); + T.add(MI.getOperand(NOp++)); MI.setDesc(get(PredOpc)); while (unsigned n = MI.getNumOperands()) @@ -1413,18 +1413,28 @@ bool HexagonInstrInfo::DefinesPredicate( auto &HRI = getRegisterInfo(); for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) { MachineOperand MO = MI.getOperand(oper); - if (MO.isReg() && MO.isDef()) { + if (MO.isReg()) { + if (!MO.isDef()) + continue; const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg()); if (RC == &Hexagon::PredRegsRegClass) { Pred.push_back(MO); return true; } + continue; + } else if (MO.isRegMask()) { + for (unsigned PR : Hexagon::PredRegsRegClass) { + if (!MI.modifiesRegister(PR, &HRI)) + continue; + Pred.push_back(MO); + return true; + } } } return false; } -bool HexagonInstrInfo::isPredicable(MachineInstr &MI) const { +bool HexagonInstrInfo::isPredicable(const MachineInstr &MI) const { return MI.getDesc().isPredicable(); } @@ -1715,7 +1725,7 @@ bool HexagonInstrInfo::isComplex(const MachineInstr &MI) const { // Return true if the instruction is a compund branch instruction. bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr &MI) const { - return (getType(MI) == HexagonII::TypeCOMPOUND && MI.isBranch()); + return getType(MI) == HexagonII::TypeCJ && MI.isBranch(); } bool HexagonInstrInfo::isCondInst(const MachineInstr &MI) const { @@ -3009,10 +3019,12 @@ bool HexagonInstrInfo::producesStall(const MachineInstr &MI, bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const { - for (unsigned opNum = 0; opNum < MI.getNumOperands(); opNum++) { - const MachineOperand &MO = MI.getOperand(opNum); + for (const MachineOperand &MO : MI.operands()) { + // Predicate register must be explicitly defined. + if (MO.isRegMask() && MO.clobbersPhysReg(PredReg)) + return false; if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg)) - return false; // Predicate register must be explicitly defined. + return false; } // Hexagon Programmer's Reference says that decbin, memw_locked, and @@ -3415,7 +3427,9 @@ int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const { return NVOpcode; switch (MI.getOpcode()) { - default: llvm_unreachable("Unknown .new type"); + default: + llvm::report_fatal_error(std::string("Unknown .new type: ") + + std::to_string(MI.getOpcode()).c_str()); case Hexagon::S4_storerb_ur: return Hexagon::S4_storerbnew_ur; @@ -3456,20 +3470,75 @@ int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const { int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const { // We assume that block can have at most two successors. - bool taken = false; const MachineBasicBlock *Src = MI.getParent(); const MachineOperand &BrTarget = MI.getOperand(1); - const MachineBasicBlock *Dst = BrTarget.getMBB(); + bool Taken = false; + const BranchProbability OneHalf(1, 2); - const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst); - if (Prediction >= BranchProbability(1,2)) - taken = true; + if (BrTarget.isMBB()) { + const MachineBasicBlock *Dst = BrTarget.getMBB(); + Taken = MBPI->getEdgeProbability(Src, Dst) >= OneHalf; + } else { + // The branch target is not a basic block (most likely a function). + // Since BPI only gives probabilities for targets that are basic blocks, + // try to identify another target of this branch (potentially a fall- + // -through) and check the probability of that target. + // + // The only handled branch combinations are: + // - one conditional branch, + // - one conditional branch followed by one unconditional branch. + // Otherwise, assume not-taken. + assert(MI.isConditionalBranch()); + const MachineBasicBlock &B = *MI.getParent(); + bool SawCond = false, Bad = false; + for (const MachineInstr &I : B) { + if (!I.isBranch()) + continue; + if (I.isConditionalBranch()) { + SawCond = true; + if (&I != &MI) { + Bad = true; + break; + } + } + if (I.isUnconditionalBranch() && !SawCond) { + Bad = true; + break; + } + } + if (!Bad) { + MachineBasicBlock::const_instr_iterator It(MI); + MachineBasicBlock::const_instr_iterator NextIt = std::next(It); + if (NextIt == B.instr_end()) { + // If this branch is the last, look for the fall-through block. + for (const MachineBasicBlock *SB : B.successors()) { + if (!B.isLayoutSuccessor(SB)) + continue; + Taken = MBPI->getEdgeProbability(Src, SB) < OneHalf; + break; + } + } else { + assert(NextIt->isUnconditionalBranch()); + // Find the first MBB operand and assume it's the target. + const MachineBasicBlock *BT = nullptr; + for (const MachineOperand &Op : NextIt->operands()) { + if (!Op.isMBB()) + continue; + BT = Op.getMBB(); + break; + } + Taken = BT && MBPI->getEdgeProbability(Src, BT) < OneHalf; + } + } // if (!Bad) + } + + // The Taken flag should be set to something reasonable by this point. switch (MI.getOpcode()) { case Hexagon::J2_jumpt: - return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew; + return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew; case Hexagon::J2_jumpf: - return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew; + return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew; default: llvm_unreachable("Unexpected jump instruction."); @@ -3479,26 +3548,46 @@ int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr &MI, // Return .new predicate version for an instruction. int HexagonInstrInfo::getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const { - int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode()); - if (NewOpcode >= 0) // Valid predicate new instruction - return NewOpcode; - switch (MI.getOpcode()) { // Condtional Jumps case Hexagon::J2_jumpt: case Hexagon::J2_jumpf: return getDotNewPredJumpOp(MI, MBPI); - - default: - assert(0 && "Unknown .new type"); } - return 0; + + int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode()); + if (NewOpcode >= 0) + return NewOpcode; + + dbgs() << "Cannot convert to .new: " << getName(MI.getOpcode()) << '\n'; + llvm_unreachable(nullptr); } -int HexagonInstrInfo::getDotOldOp(const int opc) const { - int NewOp = opc; +int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const { + int NewOp = MI.getOpcode(); if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form NewOp = Hexagon::getPredOldOpcode(NewOp); + const MachineFunction &MF = *MI.getParent()->getParent(); + const HexagonSubtarget &HST = MF.getSubtarget<HexagonSubtarget>(); + // All Hexagon architectures have prediction bits on dot-new branches, + // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure + // to pick the right opcode when converting back to dot-old. + if (!HST.getFeatureBits()[Hexagon::ArchV60]) { + switch (NewOp) { + case Hexagon::J2_jumptpt: + NewOp = Hexagon::J2_jumpt; + break; + case Hexagon::J2_jumpfpt: + NewOp = Hexagon::J2_jumpf; + break; + case Hexagon::J2_jumprtpt: + NewOp = Hexagon::J2_jumprt; + break; + case Hexagon::J2_jumprfpt: + NewOp = Hexagon::J2_jumprf; + break; + } + } assert(NewOp >= 0 && "Couldn't change predicate new instruction to its old form."); } diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.h index 2358d4b7e4c0..b268c7a28171 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.h @@ -235,7 +235,7 @@ public: /// Return true if the specified instruction can be predicated. /// By default, this returns true for every instruction with a /// PredicateOperand. - bool isPredicable(MachineInstr &MI) const override; + bool isPredicable(const MachineInstr &MI) const override; /// Test if the given instruction should be considered a scheduling boundary. /// This primarily includes labels and terminators. @@ -404,7 +404,7 @@ public: const MachineBranchProbabilityInfo *MBPI) const; int getDotNewPredOp(const MachineInstr &MI, const MachineBranchProbabilityInfo *MBPI) const; - int getDotOldOp(const int opc) const; + int getDotOldOp(const MachineInstr &MI) const; HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI) const; short getEquivalentHWInstr(const MachineInstr &MI) const; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.td deleted file mode 100644 index c5719ad5b6d8..000000000000 --- a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ /dev/null @@ -1,4799 +0,0 @@ -//==- HexagonInstrInfo.td - Target Description for Hexagon -*- tablegen -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon instructions in TableGen format. -// -//===----------------------------------------------------------------------===// - -include "HexagonInstrFormats.td" -include "HexagonOperands.td" -include "HexagonInstrEnc.td" - -//===----------------------------------------------------------------------===// -// Compare -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, isCompare = 1, InputType = "imm", isExtendable = 1, - opExtendable = 2 in -class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp> - : ALU32Inst <(outs PredRegs:$dst), - (ins IntRegs:$src1, ImmOp:$src2), - "$dst = "#!if(isNot, "!","")#mnemonic#"($src1, #$src2)", - [], "",ALU32_2op_tc_2early_SLOT0123 >, ImmRegRel { - bits<2> dst; - bits<5> src1; - bits<10> src2; - let CextOpcode = mnemonic; - let opExtentBits = !if(!eq(mnemonic, "cmp.gtu"), 9, 10); - let isExtentSigned = !if(!eq(mnemonic, "cmp.gtu"), 0, 1); - - let IClass = 0b0111; - - let Inst{27-24} = 0b0101; - let Inst{23-22} = MajOp; - let Inst{21} = !if(!eq(mnemonic, "cmp.gtu"), 0, src2{9}); - let Inst{20-16} = src1; - let Inst{13-5} = src2{8-0}; - let Inst{4} = isNot; - let Inst{3-2} = 0b00; - let Inst{1-0} = dst; - } - -def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10_0Ext>; -def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10_0Ext>; -def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9_0Ext>; - -//===----------------------------------------------------------------------===// -// ALU32/ALU + -//===----------------------------------------------------------------------===// -// Add. - -let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in -class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev, - bit IsComm> - : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = "#mnemonic#"($Rs, $Rt)", - [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel { - let isCommutable = IsComm; - let BaseOpcode = mnemonic#_rr; - let CextOpcode = mnemonic; - - bits<5> Rs; - bits<5> Rt; - bits<5> Rd; - - let IClass = 0b1111; - let Inst{27} = 0b0; - let Inst{26-24} = MajOp; - let Inst{23-21} = MinOp; - let Inst{20-16} = !if(OpsRev,Rt,Rs); - let Inst{12-8} = !if(OpsRev,Rs,Rt); - let Inst{4-0} = Rd; -} - -let hasSideEffects = 0, hasNewValue = 1 in -class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp, - bit OpsRev, bit PredNot, bit PredNew> - : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt), - "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "# - "$Rd = "#mnemonic#"($Rs, $Rt)", - [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel { - let isPredicated = 1; - let isPredicatedFalse = PredNot; - let isPredicatedNew = PredNew; - let BaseOpcode = mnemonic#_rr; - let CextOpcode = mnemonic; - - bits<2> Pu; - bits<5> Rs; - bits<5> Rt; - bits<5> Rd; - - let IClass = 0b1111; - let Inst{27} = 0b1; - let Inst{26-24} = MajOp; - let Inst{23-21} = MinOp; - let Inst{20-16} = !if(OpsRev,Rt,Rs); - let Inst{13} = PredNew; - let Inst{12-8} = !if(OpsRev,Rs,Rt); - let Inst{7} = PredNot; - let Inst{6-5} = Pu; - let Inst{4-0} = Rd; -} - -class T_ALU32_combineh<string Op1, string Op2, bits<3> MajOp, bits<3> MinOp, - bit OpsRev> - : T_ALU32_3op<"", MajOp, MinOp, OpsRev, 0> { - let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")"; -} - -def A2_combine_hh : T_ALU32_combineh<".h", ".h", 0b011, 0b100, 1>; -def A2_combine_hl : T_ALU32_combineh<".h", ".l", 0b011, 0b101, 1>; -def A2_combine_lh : T_ALU32_combineh<".l", ".h", 0b011, 0b110, 1>; -def A2_combine_ll : T_ALU32_combineh<".l", ".l", 0b011, 0b111, 1>; - -class T_ALU32_3op_sfx<string mnemonic, string suffix, bits<3> MajOp, - bits<3> MinOp, bit OpsRev, bit IsComm> - : T_ALU32_3op<"", MajOp, MinOp, OpsRev, IsComm> { - let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix; -} - -def A2_svaddh : T_ALU32_3op<"vaddh", 0b110, 0b000, 0, 1>; -def A2_svsubh : T_ALU32_3op<"vsubh", 0b110, 0b100, 1, 0>; - -let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123 in { - def A2_svaddhs : T_ALU32_3op_sfx<"vaddh", ":sat", 0b110, 0b001, 0, 1>; - def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>; - def A2_svadduhs : T_ALU32_3op_sfx<"vadduh", ":sat", 0b110, 0b011, 0, 1>; - def A2_svsubhs : T_ALU32_3op_sfx<"vsubh", ":sat", 0b110, 0b101, 1, 0>; - def A2_subsat : T_ALU32_3op_sfx<"sub", ":sat", 0b110, 0b110, 1, 0>; - def A2_svsubuhs : T_ALU32_3op_sfx<"vsubuh", ":sat", 0b110, 0b111, 1, 0>; -} - -let Itinerary = ALU32_3op_tc_2_SLOT0123 in -def A2_svavghs : T_ALU32_3op_sfx<"vavgh", ":rnd", 0b111, 0b001, 0, 1>; - -def A2_svavgh : T_ALU32_3op<"vavgh", 0b111, 0b000, 0, 1>; -def A2_svnavgh : T_ALU32_3op<"vnavgh", 0b111, 0b011, 1, 0>; - -multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp, - bit OpsRev> { - def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>; - def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>; - def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>; - def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>; -} - -multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp, - bit OpsRev, bit IsComm> { - let isPredicable = 1 in - def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>; - defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>; -} - -defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>; -defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>; -defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>; -defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>; -defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>; - -// A few special cases producing register pairs: -let OutOperandList = (outs DoubleRegs:$Rd), hasNewValue = 0 in { - def S2_packhl : T_ALU32_3op <"packhl", 0b101, 0b100, 0, 0>; - - let isPredicable = 1 in - def A2_combinew : T_ALU32_3op <"combine", 0b101, 0b000, 0, 0>; - - // Conditional combinew uses "newt/f" instead of "t/fnew". - def C2_ccombinewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 0>; - def C2_ccombinewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 0>; - def C2_ccombinewnewt : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 0, 1>; - def C2_ccombinewnewf : T_ALU32_3op_pred<"combine", 0b101, 0b000, 0, 1, 1>; -} - -let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in -class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm> - : ALU32_rr<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Pd = "#mnemonic#"($Rs, $Rt)", - [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel { - let CextOpcode = mnemonic; - let isCommutable = IsComm; - bits<5> Rs; - bits<5> Rt; - bits<2> Pd; - - let IClass = 0b1111; - let Inst{27-24} = 0b0010; - let Inst{22-21} = MinOp; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{4} = IsNeg; - let Inst{3-2} = 0b00; - let Inst{1-0} = Pd; -} - -let Itinerary = ALU32_3op_tc_2early_SLOT0123 in { - def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>; - def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>; - def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>; -} - -let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1 in -def C2_mux: ALU32_rr<(outs IntRegs:$Rd), - (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt), - "$Rd = mux($Pu, $Rs, $Rt)", [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel { - bits<5> Rd; - bits<2> Pu; - bits<5> Rs; - bits<5> Rt; - - let CextOpcode = "mux"; - let InputType = "reg"; - let hasSideEffects = 0; - let IClass = 0b1111; - - let Inst{27-24} = 0b0100; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{6-5} = Pu; - let Inst{4-0} = Rd; -} - -// Combines the two immediates into a double register. -// Increase complexity to make it greater than any complexity of a combine -// that involves a register. - -let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1, - isExtentSigned = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 1, - AddedComplexity = 75 in -def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8_0Ext:$s8, s8_0Imm:$S8), - "$Rdd = combine(#$s8, #$S8)", - []> { - bits<5> Rdd; - bits<8> s8; - bits<8> S8; - - let IClass = 0b0111; - let Inst{27-23} = 0b11000; - let Inst{22-16} = S8{7-1}; - let Inst{13} = S8{0}; - let Inst{12-5} = s8; - let Inst{4-0} = Rdd; - } - -//===----------------------------------------------------------------------===// -// Template class for predicated ADD of a reg and an Immediate value. -//===----------------------------------------------------------------------===// -let hasNewValue = 1, hasSideEffects = 0 in -class T_Addri_Pred <bit PredNot, bit PredNew> - : ALU32_ri <(outs IntRegs:$Rd), - (ins PredRegs:$Pu, IntRegs:$Rs, s8_0Ext:$s8), - !if(PredNot, "if (!$Pu", "if ($Pu")#!if(PredNew,".new) $Rd = ", - ") $Rd = ")#"add($Rs, #$s8)"> { - bits<5> Rd; - bits<2> Pu; - bits<5> Rs; - bits<8> s8; - - let isPredicatedNew = PredNew; - let IClass = 0b0111; - - let Inst{27-24} = 0b0100; - let Inst{23} = PredNot; - let Inst{22-21} = Pu; - let Inst{20-16} = Rs; - let Inst{13} = PredNew; - let Inst{12-5} = s8; - let Inst{4-0} = Rd; - } - -//===----------------------------------------------------------------------===// -// A2_addi: Add a signed immediate to a register. -//===----------------------------------------------------------------------===// -let hasNewValue = 1, hasSideEffects = 0 in -class T_Addri <Operand immOp> - : ALU32_ri <(outs IntRegs:$Rd), - (ins IntRegs:$Rs, immOp:$s16), - "$Rd = add($Rs, #$s16)", [], "", ALU32_ADDI_tc_1_SLOT0123> { - bits<5> Rd; - bits<5> Rs; - bits<16> s16; - - let IClass = 0b1011; - - let Inst{27-21} = s16{15-9}; - let Inst{20-16} = Rs; - let Inst{13-5} = s16{8-0}; - let Inst{4-0} = Rd; - } - -//===----------------------------------------------------------------------===// -// Multiclass for ADD of a register and an immediate value. -//===----------------------------------------------------------------------===// -multiclass Addri_Pred<string mnemonic, bit PredNot> { - let isPredicatedFalse = PredNot in { - def NAME : T_Addri_Pred<PredNot, 0>; - // Predicate new - def NAME#new : T_Addri_Pred<PredNot, 1>; - } -} - -let isExtendable = 1, isExtentSigned = 1, InputType = "imm" in -multiclass Addri_base<string mnemonic, SDNode OpNode> { - let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in { - let opExtendable = 2, opExtentBits = 16, isPredicable = 1, isAdd = 1 in - def A2_#NAME : T_Addri<s16_0Ext>; - - let opExtendable = 3, opExtentBits = 8, isPredicated = 1 in { - defm A2_p#NAME#t : Addri_Pred<mnemonic, 0>; - defm A2_p#NAME#f : Addri_Pred<mnemonic, 1>; - } - } -} - -defm addi : Addri_base<"add", add>, ImmRegRel, PredNewRel; - -let hasNewValue = 1, hasSideEffects = 0, isPseudo = 1 in -def A2_iconst - : ALU32_ri <(outs IntRegs:$Rd), - (ins s23_2Imm:$s23_2), - "$Rd = iconst(#$s23_2)"> {} - -//===----------------------------------------------------------------------===// -// Template class used for the following ALU32 instructions. -// Rd=and(Rs,#s10) -// Rd=or(Rs,#s10) -//===----------------------------------------------------------------------===// -let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10, -InputType = "imm", hasNewValue = 1 in -class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp> - : ALU32_ri <(outs IntRegs:$Rd), - (ins IntRegs:$Rs, s10_0Ext:$s10), - "$Rd = "#mnemonic#"($Rs, #$s10)" , - []> { - bits<5> Rd; - bits<5> Rs; - bits<10> s10; - let CextOpcode = mnemonic; - - let IClass = 0b0111; - - let Inst{27-24} = 0b0110; - let Inst{23-22} = MinOp; - let Inst{21} = s10{9}; - let Inst{20-16} = Rs; - let Inst{13-5} = s10{8-0}; - let Inst{4-0} = Rd; - } - -def A2_orir : T_ALU32ri_logical<"or", or, 0b10>, ImmRegRel; -def A2_andir : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel; - -// Subtract register from immediate -// Rd32=sub(#s10,Rs32) -let isExtendable = 1, CextOpcode = "sub", opExtendable = 1, isExtentSigned = 1, - opExtentBits = 10, InputType = "imm", hasNewValue = 1, hasSideEffects = 0 in -def A2_subri: ALU32_ri <(outs IntRegs:$Rd), (ins s10_0Ext:$s10, IntRegs:$Rs), - "$Rd = sub(#$s10, $Rs)", []>, ImmRegRel { - bits<5> Rd; - bits<10> s10; - bits<5> Rs; - - let IClass = 0b0111; - - let Inst{27-22} = 0b011001; - let Inst{21} = s10{9}; - let Inst{20-16} = Rs; - let Inst{13-5} = s10{8-0}; - let Inst{4-0} = Rd; - } - -// Nop. -let hasSideEffects = 0 in -def A2_nop: ALU32Inst <(outs), (ins), "nop" > { - let IClass = 0b0111; - let Inst{27-24} = 0b1111; -} - -let hasSideEffects = 0, hasNewValue = 1 in -class T_tfr16<bit isHi> - : ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16_0Imm:$u16), - "$Rx"#!if(isHi, ".h", ".l")#" = #$u16", - [], "$src1 = $Rx" > { - bits<5> Rx; - bits<16> u16; - - let IClass = 0b0111; - let Inst{27-26} = 0b00; - let Inst{25-24} = !if(isHi, 0b10, 0b01); - let Inst{23-22} = u16{15-14}; - let Inst{21} = 0b1; - let Inst{20-16} = Rx; - let Inst{13-0} = u16{13-0}; - } - -def A2_tfril: T_tfr16<0>; -def A2_tfrih: T_tfr16<1>; - -// Conditional transfer is an alias to conditional "Rd = add(Rs, #0)". -let isPredicated = 1, hasNewValue = 1, opNewValue = 0 in -class T_tfr_pred<bit isPredNot, bit isPredNew> - : ALU32Inst<(outs IntRegs:$dst), - (ins PredRegs:$src1, IntRegs:$src2), - "if ("#!if(isPredNot, "!", "")# - "$src1"#!if(isPredNew, ".new", "")# - ") $dst = $src2"> { - bits<5> dst; - bits<2> src1; - bits<5> src2; - - let isPredicatedFalse = isPredNot; - let isPredicatedNew = isPredNew; - let IClass = 0b0111; - - let Inst{27-24} = 0b0100; - let Inst{23} = isPredNot; - let Inst{13} = isPredNew; - let Inst{12-5} = 0; - let Inst{4-0} = dst; - let Inst{22-21} = src1; - let Inst{20-16} = src2; - } - -let isPredicable = 1 in -class T_tfr : ALU32Inst<(outs IntRegs:$dst), (ins IntRegs:$src), - "$dst = $src"> { - bits<5> dst; - bits<5> src; - - let IClass = 0b0111; - - let Inst{27-21} = 0b0000011; - let Inst{20-16} = src; - let Inst{13} = 0b0; - let Inst{4-0} = dst; - } - -let InputType = "reg", hasNewValue = 1, hasSideEffects = 0 in -multiclass tfr_base<string CextOp> { - let CextOpcode = CextOp, BaseOpcode = CextOp in { - def NAME : T_tfr; - - // Predicate - def t : T_tfr_pred<0, 0>; - def f : T_tfr_pred<1, 0>; - // Predicate new - def tnew : T_tfr_pred<0, 1>; - def fnew : T_tfr_pred<1, 1>; - } -} - -// Assembler mapped to C2_ccombinew[t|f|newt|newf]. -// Please don't add bits to this instruction as it'll be converted into -// 'combine' before object code emission. -let isPredicated = 1 in -class T_tfrp_pred<bit PredNot, bit PredNew> - : ALU32_rr <(outs DoubleRegs:$dst), - (ins PredRegs:$src1, DoubleRegs:$src2), - "if ("#!if(PredNot, "!", "")#"$src1" - #!if(PredNew, ".new", "")#") $dst = $src2" > { - let isPredicatedFalse = PredNot; - let isPredicatedNew = PredNew; - } - -// Assembler mapped to A2_combinew. -// Please don't add bits to this instruction as it'll be converted into -// 'combine' before object code emission. -class T_tfrp : ALU32Inst <(outs DoubleRegs:$dst), - (ins DoubleRegs:$src), - "$dst = $src">; - -let hasSideEffects = 0 in -multiclass TFR64_base<string BaseName> { - let BaseOpcode = BaseName in { - let isPredicable = 1 in - def NAME : T_tfrp; - // Predicate - def t : T_tfrp_pred <0, 0>; - def f : T_tfrp_pred <1, 0>; - // Predicate new - def tnew : T_tfrp_pred <0, 1>; - def fnew : T_tfrp_pred <1, 1>; - } -} - -let InputType = "imm", isExtendable = 1, isExtentSigned = 1, opExtentBits = 12, - isMoveImm = 1, opExtendable = 2, BaseOpcode = "TFRI", CextOpcode = "TFR", - hasSideEffects = 0, isPredicated = 1, hasNewValue = 1 in -class T_TFRI_Pred<bit PredNot, bit PredNew> - : ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12_0Ext:$s12), - "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") $Rd = #$s12", - [], "", ALU32_2op_tc_1_SLOT0123>, ImmRegRel, PredNewRel { - let isPredicatedFalse = PredNot; - let isPredicatedNew = PredNew; - - bits<5> Rd; - bits<2> Pu; - bits<12> s12; - - let IClass = 0b0111; - let Inst{27-24} = 0b1110; - let Inst{23} = PredNot; - let Inst{22-21} = Pu; - let Inst{20} = 0b0; - let Inst{19-16,12-5} = s12; - let Inst{13} = PredNew; - let Inst{4-0} = Rd; -} - -def C2_cmoveit : T_TFRI_Pred<0, 0>; -def C2_cmoveif : T_TFRI_Pred<1, 0>; -def C2_cmovenewit : T_TFRI_Pred<0, 1>; -def C2_cmovenewif : T_TFRI_Pred<1, 1>; - -let InputType = "imm", isExtendable = 1, isExtentSigned = 1, - CextOpcode = "TFR", BaseOpcode = "TFRI", hasNewValue = 1, opNewValue = 0, - isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16, isMoveImm = 1, - isPredicated = 0, isPredicable = 1, isReMaterializable = 1 in -def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16_0Ext:$s16), "$Rd = #$s16", - [], "", ALU32_2op_tc_1_SLOT0123>, - ImmRegRel, PredRel { - bits<5> Rd; - bits<16> s16; - - let IClass = 0b0111; - let Inst{27-24} = 0b1000; - let Inst{23-22,20-16,13-5} = s16; - let Inst{4-0} = Rd; -} - -defm A2_tfr : tfr_base<"TFR">, ImmRegRel, PredNewRel; -let isAsmParserOnly = 1 in -defm A2_tfrp : TFR64_base<"TFR64">, PredNewRel; - -// Assembler mapped -let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1, - isAsmParserOnly = 1 in -def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8_0Imm64:$src1), - "$dst = #$src1", - []>; - -// TODO: see if this instruction can be deleted.. -let isExtendable = 1, opExtendable = 1, opExtentBits = 6, - isAsmParserOnly = 1 in { -def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u64_0Imm:$src1), - "$dst = #$src1">; -def TFRI64_V2_ext : ALU64_rr<(outs DoubleRegs:$dst), - (ins s8_0Ext:$src1, s8_0Imm:$src2), - "$dst = combine(##$src1, #$src2)">; -} - -//===----------------------------------------------------------------------===// -// ALU32/ALU - -//===----------------------------------------------------------------------===// - - -//===----------------------------------------------------------------------===// -// ALU32/PERM + -//===----------------------------------------------------------------------===// -// Scalar mux register immediate. -let hasSideEffects = 0, isExtentSigned = 1, CextOpcode = "MUX", - InputType = "imm", hasNewValue = 1, isExtendable = 1, opExtentBits = 8 in -class T_MUX1 <bit MajOp, dag ins, string AsmStr> - : ALU32Inst <(outs IntRegs:$Rd), ins, AsmStr>, ImmRegRel { - bits<5> Rd; - bits<2> Pu; - bits<8> s8; - bits<5> Rs; - - let IClass = 0b0111; - let Inst{27-24} = 0b0011; - let Inst{23} = MajOp; - let Inst{22-21} = Pu; - let Inst{20-16} = Rs; - let Inst{13} = 0b0; - let Inst{12-5} = s8; - let Inst{4-0} = Rd; -} - -let opExtendable = 2 in -def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8_0Ext:$s8, IntRegs:$Rs), - "$Rd = mux($Pu, #$s8, $Rs)">; - -let opExtendable = 3 in -def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8_0Ext:$s8), - "$Rd = mux($Pu, $Rs, #$s8)">; - -// C2_muxii: Scalar mux immediates. -let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, - opExtentBits = 8, opExtendable = 2 in -def C2_muxii: ALU32Inst <(outs IntRegs:$Rd), - (ins PredRegs:$Pu, s8_0Ext:$s8, s8_0Imm:$S8), - "$Rd = mux($Pu, #$s8, #$S8)" , - []> { - bits<5> Rd; - bits<2> Pu; - bits<8> s8; - bits<8> S8; - - let IClass = 0b0111; - - let Inst{27-25} = 0b101; - let Inst{24-23} = Pu; - let Inst{22-16} = S8{7-1}; - let Inst{13} = S8{0}; - let Inst{12-5} = s8; - let Inst{4-0} = Rd; - } - -let isCodeGenOnly = 1, isPseudo = 1 in -def PS_pselect : ALU64_rr<(outs DoubleRegs:$Rd), - (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt), - ".error \"should not emit\" ", []>; - - -//===----------------------------------------------------------------------===// -// template class for non-predicated alu32_2op instructions -// - aslh, asrh, sxtb, sxth, zxth -//===----------------------------------------------------------------------===// -let hasNewValue = 1, opNewValue = 0 in -class T_ALU32_2op <string mnemonic, bits<3> minOp> : - ALU32Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rs), - "$Rd = "#mnemonic#"($Rs)", [] > { - bits<5> Rd; - bits<5> Rs; - - let IClass = 0b0111; - - let Inst{27-24} = 0b0000; - let Inst{23-21} = minOp; - let Inst{13} = 0b0; - let Inst{4-0} = Rd; - let Inst{20-16} = Rs; -} - -//===----------------------------------------------------------------------===// -// template class for predicated alu32_2op instructions -// - aslh, asrh, sxtb, sxth, zxtb, zxth -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -class T_ALU32_2op_Pred <string mnemonic, bits<3> minOp, bit isPredNot, - bit isPredNew > : - ALU32Inst <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs), - !if(isPredNot, "if (!$Pu", "if ($Pu") - #!if(isPredNew, ".new) ",") ")#"$Rd = "#mnemonic#"($Rs)"> { - bits<5> Rd; - bits<2> Pu; - bits<5> Rs; - - let IClass = 0b0111; - - let Inst{27-24} = 0b0000; - let Inst{23-21} = minOp; - let Inst{13} = 0b1; - let Inst{11} = isPredNot; - let Inst{10} = isPredNew; - let Inst{4-0} = Rd; - let Inst{9-8} = Pu; - let Inst{20-16} = Rs; -} - -multiclass ALU32_2op_Pred<string mnemonic, bits<3> minOp, bit PredNot> { - let isPredicatedFalse = PredNot in { - def NAME : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 0>; - - // Predicate new - let isPredicatedNew = 1 in - def NAME#new : T_ALU32_2op_Pred<mnemonic, minOp, PredNot, 1>; - } -} - -multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> { - let BaseOpcode = mnemonic in { - let isPredicable = 1, hasSideEffects = 0 in - def A2_#NAME : T_ALU32_2op<mnemonic, minOp>; - - let isPredicated = 1, hasSideEffects = 0 in { - defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>; - defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>; - } - } -} - -defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel; -defm asrh : ALU32_2op_base<"asrh", 0b001>, PredNewRel; -defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel; -defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel; -defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel; - -// Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255). -// Compiler would want to generate 'zxtb' instead of 'and' because 'zxtb' has -// predicated forms while 'and' doesn't. Since integrated assembler can't -// handle 'mapped' instructions, we need to encode 'zxtb' same as 'and' where -// immediate operand is set to '255'. - -let hasNewValue = 1, opNewValue = 0 in -class T_ZXTB: ALU32Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rs), - "$Rd = zxtb($Rs)", [] > { // Rd = and(Rs,255) - bits<5> Rd; - bits<5> Rs; - bits<10> s10 = 255; - - let IClass = 0b0111; - - let Inst{27-22} = 0b011000; - let Inst{4-0} = Rd; - let Inst{20-16} = Rs; - let Inst{21} = s10{9}; - let Inst{13-5} = s10{8-0}; -} - -//Rd=zxtb(Rs): assembler mapped to "Rd=and(Rs,#255) -multiclass ZXTB_base <string mnemonic, bits<3> minOp> { - let BaseOpcode = mnemonic in { - let isPredicable = 1, hasSideEffects = 0 in - def A2_#NAME : T_ZXTB; - - let isPredicated = 1, hasSideEffects = 0 in { - defm A4_p#NAME#t : ALU32_2op_Pred<mnemonic, minOp, 0>; - defm A4_p#NAME#f : ALU32_2op_Pred<mnemonic, minOp, 1>; - } - } -} - -defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel; - -//===----------------------------------------------------------------------===// -// Template class for vector add and avg -//===----------------------------------------------------------------------===// - -class T_VectALU_64 <string opc, bits<3> majOp, bits<3> minOp, - bit isSat, bit isRnd, bit isCrnd, bit SwapOps > - : ALU64_rr < (outs DoubleRegs:$Rdd), - (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Rdd = "#opc#"($Rss, $Rtt)"#!if(isRnd, ":rnd", "") - #!if(isCrnd,":crnd","") - #!if(isSat, ":sat", ""), - [], "", ALU64_tc_2_SLOT23 > { - bits<5> Rdd; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1101; - - let Inst{27-24} = 0b0011; - let Inst{23-21} = majOp; - let Inst{20-16} = !if (SwapOps, Rtt, Rss); - let Inst{12-8} = !if (SwapOps, Rss, Rtt); - let Inst{7-5} = minOp; - let Inst{4-0} = Rdd; - } - -// ALU64 - Vector add -// Rdd=vadd[u][bhw](Rss,Rtt) -let Itinerary = ALU64_tc_1_SLOT23 in { - def A2_vaddub : T_VectALU_64 < "vaddub", 0b000, 0b000, 0, 0, 0, 0>; - def A2_vaddh : T_VectALU_64 < "vaddh", 0b000, 0b010, 0, 0, 0, 0>; - def A2_vaddw : T_VectALU_64 < "vaddw", 0b000, 0b101, 0, 0, 0, 0>; -} - -// Rdd=vadd[u][bhw](Rss,Rtt):sat -let Defs = [USR_OVF] in { - def A2_vaddubs : T_VectALU_64 < "vaddub", 0b000, 0b001, 1, 0, 0, 0>; - def A2_vaddhs : T_VectALU_64 < "vaddh", 0b000, 0b011, 1, 0, 0, 0>; - def A2_vadduhs : T_VectALU_64 < "vadduh", 0b000, 0b100, 1, 0, 0, 0>; - def A2_vaddws : T_VectALU_64 < "vaddw", 0b000, 0b110, 1, 0, 0, 0>; -} - -// ALU64 - Vector average -// Rdd=vavg[u][bhw](Rss,Rtt) -let Itinerary = ALU64_tc_1_SLOT23 in { - def A2_vavgub : T_VectALU_64 < "vavgub", 0b010, 0b000, 0, 0, 0, 0>; - def A2_vavgh : T_VectALU_64 < "vavgh", 0b010, 0b010, 0, 0, 0, 0>; - def A2_vavguh : T_VectALU_64 < "vavguh", 0b010, 0b101, 0, 0, 0, 0>; - def A2_vavgw : T_VectALU_64 < "vavgw", 0b011, 0b000, 0, 0, 0, 0>; - def A2_vavguw : T_VectALU_64 < "vavguw", 0b011, 0b011, 0, 0, 0, 0>; -} - -// Rdd=vavg[u][bhw](Rss,Rtt)[:rnd|:crnd] -def A2_vavgubr : T_VectALU_64 < "vavgub", 0b010, 0b001, 0, 1, 0, 0>; -def A2_vavghr : T_VectALU_64 < "vavgh", 0b010, 0b011, 0, 1, 0, 0>; -def A2_vavghcr : T_VectALU_64 < "vavgh", 0b010, 0b100, 0, 0, 1, 0>; -def A2_vavguhr : T_VectALU_64 < "vavguh", 0b010, 0b110, 0, 1, 0, 0>; - -def A2_vavgwr : T_VectALU_64 < "vavgw", 0b011, 0b001, 0, 1, 0, 0>; -def A2_vavgwcr : T_VectALU_64 < "vavgw", 0b011, 0b010, 0, 0, 1, 0>; -def A2_vavguwr : T_VectALU_64 < "vavguw", 0b011, 0b100, 0, 1, 0, 0>; - -// Rdd=vnavg[bh](Rss,Rtt) -let Itinerary = ALU64_tc_1_SLOT23 in { - def A2_vnavgh : T_VectALU_64 < "vnavgh", 0b100, 0b000, 0, 0, 0, 1>; - def A2_vnavgw : T_VectALU_64 < "vnavgw", 0b100, 0b011, 0, 0, 0, 1>; -} - -// Rdd=vnavg[bh](Rss,Rtt)[:rnd|:crnd]:sat -let Defs = [USR_OVF] in { - def A2_vnavghr : T_VectALU_64 < "vnavgh", 0b100, 0b001, 1, 1, 0, 1>; - def A2_vnavghcr : T_VectALU_64 < "vnavgh", 0b100, 0b010, 1, 0, 1, 1>; - def A2_vnavgwr : T_VectALU_64 < "vnavgw", 0b100, 0b100, 1, 1, 0, 1>; - def A2_vnavgwcr : T_VectALU_64 < "vnavgw", 0b100, 0b110, 1, 0, 1, 1>; -} - -// Rdd=vsub[u][bh](Rss,Rtt) -let Itinerary = ALU64_tc_1_SLOT23 in { - def A2_vsubub : T_VectALU_64 < "vsubub", 0b001, 0b000, 0, 0, 0, 1>; - def A2_vsubh : T_VectALU_64 < "vsubh", 0b001, 0b010, 0, 0, 0, 1>; - def A2_vsubw : T_VectALU_64 < "vsubw", 0b001, 0b101, 0, 0, 0, 1>; -} - -// Rdd=vsub[u][bh](Rss,Rtt):sat -let Defs = [USR_OVF] in { - def A2_vsububs : T_VectALU_64 < "vsubub", 0b001, 0b001, 1, 0, 0, 1>; - def A2_vsubhs : T_VectALU_64 < "vsubh", 0b001, 0b011, 1, 0, 0, 1>; - def A2_vsubuhs : T_VectALU_64 < "vsubuh", 0b001, 0b100, 1, 0, 0, 1>; - def A2_vsubws : T_VectALU_64 < "vsubw", 0b001, 0b110, 1, 0, 0, 1>; -} - -// Rdd=vmax[u][bhw](Rss,Rtt) -def A2_vmaxb : T_VectALU_64 < "vmaxb", 0b110, 0b110, 0, 0, 0, 1>; -def A2_vmaxub : T_VectALU_64 < "vmaxub", 0b110, 0b000, 0, 0, 0, 1>; -def A2_vmaxh : T_VectALU_64 < "vmaxh", 0b110, 0b001, 0, 0, 0, 1>; -def A2_vmaxuh : T_VectALU_64 < "vmaxuh", 0b110, 0b010, 0, 0, 0, 1>; -def A2_vmaxw : T_VectALU_64 < "vmaxw", 0b110, 0b011, 0, 0, 0, 1>; -def A2_vmaxuw : T_VectALU_64 < "vmaxuw", 0b101, 0b101, 0, 0, 0, 1>; - -// Rdd=vmin[u][bhw](Rss,Rtt) -def A2_vminb : T_VectALU_64 < "vminb", 0b110, 0b111, 0, 0, 0, 1>; -def A2_vminub : T_VectALU_64 < "vminub", 0b101, 0b000, 0, 0, 0, 1>; -def A2_vminh : T_VectALU_64 < "vminh", 0b101, 0b001, 0, 0, 0, 1>; -def A2_vminuh : T_VectALU_64 < "vminuh", 0b101, 0b010, 0, 0, 0, 1>; -def A2_vminw : T_VectALU_64 < "vminw", 0b101, 0b011, 0, 0, 0, 1>; -def A2_vminuw : T_VectALU_64 < "vminuw", 0b101, 0b100, 0, 0, 0, 1>; - -//===----------------------------------------------------------------------===// -// Template class for vector compare -//===----------------------------------------------------------------------===// -let hasSideEffects = 0 in -class T_vcmp <string Str, bits<4> minOp> - : ALU64_rr <(outs PredRegs:$Pd), - (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Pd = "#Str#"($Rss, $Rtt)", [], - "", ALU64_tc_2early_SLOT23> { - bits<2> Pd; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1101; - - let Inst{27-23} = 0b00100; - let Inst{13} = minOp{3}; - let Inst{7-5} = minOp{2-0}; - let Inst{1-0} = Pd; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - } - -// Vector compare bytes -def A2_vcmpbeq : T_vcmp <"vcmpb.eq", 0b0110>; -def A2_vcmpbgtu : T_vcmp <"vcmpb.gtu", 0b0111>; - -// Vector compare halfwords -def A2_vcmpheq : T_vcmp <"vcmph.eq", 0b0011>; -def A2_vcmphgt : T_vcmp <"vcmph.gt", 0b0100>; -def A2_vcmphgtu : T_vcmp <"vcmph.gtu", 0b0101>; - -// Vector compare words -def A2_vcmpweq : T_vcmp <"vcmpw.eq", 0b0000>; -def A2_vcmpwgt : T_vcmp <"vcmpw.gt", 0b0001>; -def A2_vcmpwgtu : T_vcmp <"vcmpw.gtu", 0b0010>; - -//===----------------------------------------------------------------------===// -// ALU32/PERM - -//===----------------------------------------------------------------------===// - - -//===----------------------------------------------------------------------===// -// ALU32/PRED + -//===----------------------------------------------------------------------===// -// No bits needed. If cmp.ge is found the assembler parser will -// transform it to cmp.gt subtracting 1 from the immediate. -let isPseudo = 1 in { -def C2_cmpgei: ALU32Inst < - (outs PredRegs:$Pd), (ins IntRegs:$Rs, s8_0Ext:$s8), - "$Pd = cmp.ge($Rs, #$s8)">; -def C2_cmpgeui: ALU32Inst < - (outs PredRegs:$Pd), (ins IntRegs:$Rs, u8_0Ext:$s8), - "$Pd = cmp.geu($Rs, #$s8)">; -} - - -//===----------------------------------------------------------------------===// -// ALU32/PRED - -//===----------------------------------------------------------------------===// - - -//===----------------------------------------------------------------------===// -// ALU64/ALU + -//===----------------------------------------------------------------------===// -// Add. -//===----------------------------------------------------------------------===// -// Template Class -// Add/Subtract halfword -// Rd=add(Rt.L,Rs.[HL])[:sat] -// Rd=sub(Rt.L,Rs.[HL])[:sat] -// Rd=add(Rt.[LH],Rs.[HL])[:sat][:<16] -// Rd=sub(Rt.[LH],Rs.[HL])[:sat][:<16] -//===----------------------------------------------------------------------===// - -let hasNewValue = 1, opNewValue = 0 in -class T_XTYPE_ADD_SUB <bits<2> LHbits, bit isSat, bit hasShift, bit isSub> - : ALU64Inst <(outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs), - "$Rd = "#!if(isSub,"sub","add")#"($Rt." - #!if(hasShift, !if(LHbits{1},"h","l"),"l") #", $Rs." - #!if(hasShift, !if(LHbits{0},"h)","l)"), !if(LHbits{1},"h)","l)")) - #!if(isSat,":sat","") - #!if(hasShift,":<<16",""), [], "", ALU64_tc_1_SLOT23> { - bits<5> Rd; - bits<5> Rt; - bits<5> Rs; - let IClass = 0b1101; - - let Inst{27-23} = 0b01010; - let Inst{22} = hasShift; - let Inst{21} = isSub; - let Inst{7} = isSat; - let Inst{6-5} = LHbits; - let Inst{4-0} = Rd; - let Inst{12-8} = Rt; - let Inst{20-16} = Rs; - } - -//Rd=sub(Rt.L,Rs.[LH]) -def A2_subh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 1>; -def A2_subh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 1>; - -//Rd=add(Rt.L,Rs.[LH]) -def A2_addh_l16_ll : T_XTYPE_ADD_SUB <0b00, 0, 0, 0>; -def A2_addh_l16_hl : T_XTYPE_ADD_SUB <0b10, 0, 0, 0>; - -let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF] in { - //Rd=sub(Rt.L,Rs.[LH]):sat - def A2_subh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 1>; - def A2_subh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 1>; - - //Rd=add(Rt.L,Rs.[LH]):sat - def A2_addh_l16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 0, 0>; - def A2_addh_l16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 0, 0>; -} - -//Rd=sub(Rt.[LH],Rs.[LH]):<<16 -def A2_subh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 1>; -def A2_subh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 1>; -def A2_subh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 1>; -def A2_subh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 1>; - -//Rd=add(Rt.[LH],Rs.[LH]):<<16 -def A2_addh_h16_ll : T_XTYPE_ADD_SUB <0b00, 0, 1, 0>; -def A2_addh_h16_lh : T_XTYPE_ADD_SUB <0b01, 0, 1, 0>; -def A2_addh_h16_hl : T_XTYPE_ADD_SUB <0b10, 0, 1, 0>; -def A2_addh_h16_hh : T_XTYPE_ADD_SUB <0b11, 0, 1, 0>; - -let Itinerary = ALU64_tc_2_SLOT23, Defs = [USR_OVF] in { - //Rd=sub(Rt.[LH],Rs.[LH]):sat:<<16 - def A2_subh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 1>; - def A2_subh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 1>; - def A2_subh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 1>; - def A2_subh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 1>; - - //Rd=add(Rt.[LH],Rs.[LH]):sat:<<16 - def A2_addh_h16_sat_ll : T_XTYPE_ADD_SUB <0b00, 1, 1, 0>; - def A2_addh_h16_sat_lh : T_XTYPE_ADD_SUB <0b01, 1, 1, 0>; - def A2_addh_h16_sat_hl : T_XTYPE_ADD_SUB <0b10, 1, 1, 0>; - def A2_addh_h16_sat_hh : T_XTYPE_ADD_SUB <0b11, 1, 1, 0>; -} - -let hasSideEffects = 0, hasNewValue = 1 in -def S2_parityp: ALU64Inst<(outs IntRegs:$Rd), - (ins DoubleRegs:$Rs, DoubleRegs:$Rt), - "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - let Inst{27-24} = 0b0000; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{4-0} = Rd; -} - -let hasNewValue = 1, opNewValue = 0, hasSideEffects = 0 in -class T_XTYPE_MIN_MAX < bit isMax, bit isUnsigned > - : ALU64Inst < (outs IntRegs:$Rd), (ins IntRegs:$Rt, IntRegs:$Rs), - "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","") - #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> { - bits<5> Rd; - bits<5> Rt; - bits<5> Rs; - - let IClass = 0b1101; - - let Inst{27-23} = 0b01011; - let Inst{22-21} = !if(isMax, 0b10, 0b01); - let Inst{7} = isUnsigned; - let Inst{4-0} = Rd; - let Inst{12-8} = !if(isMax, Rs, Rt); - let Inst{20-16} = !if(isMax, Rt, Rs); - } - -def A2_min : T_XTYPE_MIN_MAX < 0, 0 >; -def A2_minu : T_XTYPE_MIN_MAX < 0, 1 >; -def A2_max : T_XTYPE_MIN_MAX < 1, 0 >; -def A2_maxu : T_XTYPE_MIN_MAX < 1, 1 >; - -class T_cmp64_rr<string mnemonic, bits<3> MinOp, bit IsComm> - : ALU64_rr<(outs PredRegs:$Pd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt), - "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", ALU64_tc_2early_SLOT23> { - let isCompare = 1; - let isCommutable = IsComm; - let hasSideEffects = 0; - - bits<2> Pd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - let Inst{27-21} = 0b0010100; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{7-5} = MinOp; - let Inst{1-0} = Pd; -} - -def C2_cmpeqp : T_cmp64_rr<"cmp.eq", 0b000, 1>; -def C2_cmpgtp : T_cmp64_rr<"cmp.gt", 0b010, 0>; -def C2_cmpgtup : T_cmp64_rr<"cmp.gtu", 0b100, 0>; - -def C2_vmux : ALU64_rr<(outs DoubleRegs:$Rd), - (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt), - "$Rd = vmux($Pu, $Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> { - let hasSideEffects = 0; - - bits<5> Rd; - bits<2> Pu; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - let Inst{27-24} = 0b0001; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{6-5} = Pu; - let Inst{4-0} = Rd; -} - -class T_ALU64_rr<string mnemonic, string suffix, bits<4> RegType, - bits<3> MajOp, bits<3> MinOp, bit OpsRev, bit IsComm, - string Op2Pfx> - : ALU64_rr<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rs, DoubleRegs:$Rt), - "$Rd = " #mnemonic# "($Rs, " #Op2Pfx# "$Rt)" #suffix, [], - "", ALU64_tc_1_SLOT23> { - let hasSideEffects = 0; - let isCommutable = IsComm; - - bits<5> Rs; - bits<5> Rt; - bits<5> Rd; - - let IClass = 0b1101; - let Inst{27-24} = RegType; - let Inst{23-21} = MajOp; - let Inst{20-16} = !if (OpsRev,Rt,Rs); - let Inst{12-8} = !if (OpsRev,Rs,Rt); - let Inst{7-5} = MinOp; - let Inst{4-0} = Rd; -} - -class T_ALU64_arith<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit IsSat, - bit OpsRev, bit IsComm> - : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev, - IsComm, "">; - -let isAdd = 1 in -def A2_addp : T_ALU64_arith<"add", 0b000, 0b111, 0, 0, 1>; -def A2_subp : T_ALU64_arith<"sub", 0b001, 0b111, 0, 1, 0>; - -class T_ALU64_logical<string mnemonic, bits<3> MinOp, bit OpsRev, bit IsComm, - bit IsNeg> - : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm, - !if(IsNeg,"~","")>; - -def A2_andp : T_ALU64_logical<"and", 0b000, 0, 1, 0>; -def A2_orp : T_ALU64_logical<"or", 0b010, 0, 1, 0>; -def A2_xorp : T_ALU64_logical<"xor", 0b100, 0, 1, 0>; - -//===----------------------------------------------------------------------===// -// ALU64/ALU - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// ALU64/BIT + -//===----------------------------------------------------------------------===// -// -//===----------------------------------------------------------------------===// -// ALU64/BIT - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// ALU64/PERM + -//===----------------------------------------------------------------------===// -// -//===----------------------------------------------------------------------===// -// ALU64/PERM - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// CR + -//===----------------------------------------------------------------------===// -// Logical reductions on predicates. - -// Looping instructions. - -// Pipelined looping instructions. - -// Logical operations on predicates. -let hasSideEffects = 0 in -class T_LOGICAL_1OP<string MnOp, bits<2> OpBits> - : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps), - "$Pd = " # MnOp # "($Ps)", [], "", CR_tc_2early_SLOT23> { - bits<2> Pd; - bits<2> Ps; - - let IClass = 0b0110; - let Inst{27-23} = 0b10111; - let Inst{22-21} = OpBits; - let Inst{20} = 0b0; - let Inst{17-16} = Ps; - let Inst{13} = 0b0; - let Inst{1-0} = Pd; -} - -def C2_any8 : T_LOGICAL_1OP<"any8", 0b00>; -def C2_all8 : T_LOGICAL_1OP<"all8", 0b01>; -def C2_not : T_LOGICAL_1OP<"not", 0b10>; - -let hasSideEffects = 0 in -class T_LOGICAL_2OP<string MnOp, bits<3> OpBits, bit IsNeg, bit Rev> - : CRInst<(outs PredRegs:$Pd), (ins PredRegs:$Ps, PredRegs:$Pt), - "$Pd = " # MnOp # "($Ps, " # !if (IsNeg,"!","") # "$Pt)", - [], "", CR_tc_2early_SLOT23> { - bits<2> Pd; - bits<2> Ps; - bits<2> Pt; - - let IClass = 0b0110; - let Inst{27-24} = 0b1011; - let Inst{23-21} = OpBits; - let Inst{20} = 0b0; - let Inst{17-16} = !if(Rev,Pt,Ps); // Rs and Rt are reversed for some - let Inst{13} = 0b0; // instructions. - let Inst{9-8} = !if(Rev,Ps,Pt); - let Inst{1-0} = Pd; -} - -def C2_and : T_LOGICAL_2OP<"and", 0b000, 0, 1>; -def C2_or : T_LOGICAL_2OP<"or", 0b001, 0, 1>; -def C2_xor : T_LOGICAL_2OP<"xor", 0b010, 0, 0>; -def C2_andn : T_LOGICAL_2OP<"and", 0b011, 1, 1>; -def C2_orn : T_LOGICAL_2OP<"or", 0b111, 1, 1>; - -let hasSideEffects = 0, hasNewValue = 1 in -def C2_vitpack : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps, PredRegs:$Pt), - "$Rd = vitpack($Ps, $Pt)", [], "", S_2op_tc_1_SLOT23> { - bits<5> Rd; - bits<2> Ps; - bits<2> Pt; - - let IClass = 0b1000; - let Inst{27-24} = 0b1001; - let Inst{22-21} = 0b00; - let Inst{17-16} = Ps; - let Inst{9-8} = Pt; - let Inst{4-0} = Rd; -} - -let hasSideEffects = 0 in -def C2_mask : SInst<(outs DoubleRegs:$Rd), (ins PredRegs:$Pt), - "$Rd = mask($Pt)", [], "", S_2op_tc_1_SLOT23> { - bits<5> Rd; - bits<2> Pt; - - let IClass = 0b1000; - let Inst{27-24} = 0b0110; - let Inst{9-8} = Pt; - let Inst{4-0} = Rd; -} - -// User control register transfer. -//===----------------------------------------------------------------------===// -// CR - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// JR + -//===----------------------------------------------------------------------===// - -class CondStr<string CReg, bit True, bit New> { - string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") "; -} -class JumpOpcStr<string Mnemonic, bit New, bit Taken> { - string S = Mnemonic # !if(Taken, ":t", ":nt"); -} - -let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0, - isPredicable = 1, - isExtendable = 1, opExtendable = 0, isExtentSigned = 1, - opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in -class T_JMP<string ExtStr> - : JInst_CJUMP_UCJUMP<(outs), (ins brtarget:$dst), - "jump " # ExtStr # "$dst", - [], "", J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT> { - bits<24> dst; - let IClass = 0b0101; - - let Inst{27-25} = 0b100; - let Inst{24-16} = dst{23-15}; - let Inst{13-1} = dst{14-2}; -} - -let isBranch = 1, Defs = [PC], hasSideEffects = 0, isPredicated = 1, - isExtendable = 1, opExtendable = 1, isExtentSigned = 1, - opExtentBits = 17, opExtentAlign = 2, InputType = "imm" in -class T_JMP_c<bit PredNot, bit isPredNew, bit isTak, string ExtStr> - : JInst_CJUMP_UCJUMP<(outs), (ins PredRegs:$src, brtarget:$dst), - CondStr<"$src", !if(PredNot,0,1), isPredNew>.S # - JumpOpcStr<"jump", isPredNew, isTak>.S # " " # - ExtStr # "$dst", - [], "", J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT>, ImmRegRel { - let isTaken = isTak; - let isPredicatedFalse = PredNot; - let isPredicatedNew = isPredNew; - bits<2> src; - bits<17> dst; - - let IClass = 0b0101; - - let Inst{27-24} = 0b1100; - let Inst{21} = PredNot; - let Inst{12} = isTak; - let Inst{11} = isPredNew; - let Inst{9-8} = src; - let Inst{23-22} = dst{16-15}; - let Inst{20-16} = dst{14-10}; - let Inst{13} = dst{9}; - let Inst{7-1} = dst{8-2}; - } - -multiclass JMP_Pred<bit PredNot, string ExtStr> { - def NAME : T_JMP_c<PredNot, 0, 0, ExtStr>; // not taken - // Predicate new - def NAME#newpt : T_JMP_c<PredNot, 1, 1, ExtStr>; // taken - def NAME#new : T_JMP_c<PredNot, 1, 0, ExtStr>; // not taken -} - -multiclass JMP_base<string BaseOp, string ExtStr> { - let BaseOpcode = BaseOp in { - def NAME : T_JMP<ExtStr>; - defm t : JMP_Pred<0, ExtStr>; - defm f : JMP_Pred<1, ExtStr>; - } -} - -// Jumps to address stored in a register, JUMPR_MISC -// if ([[!]P[.new]]) jumpr[:t/nt] Rs -let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC], - isPredicable = 1, hasSideEffects = 0, InputType = "reg" in -class T_JMPr - : JRInst<(outs), (ins IntRegs:$dst), - "jumpr $dst", [], "", J_tc_2early_SLOT2> { - bits<5> dst; - - let IClass = 0b0101; - let Inst{27-21} = 0b0010100; - let Inst{20-16} = dst; -} - -let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1, - hasSideEffects = 0, InputType = "reg" in -class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak> - : JRInst <(outs), (ins PredRegs:$src, IntRegs:$dst), - CondStr<"$src", !if(PredNot,0,1), isPredNew>.S # - JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst", [], - "", J_tc_2early_SLOT2> { - - let isTaken = isTak; - let isPredicatedFalse = PredNot; - let isPredicatedNew = isPredNew; - bits<2> src; - bits<5> dst; - - let IClass = 0b0101; - - let Inst{27-22} = 0b001101; - let Inst{21} = PredNot; - let Inst{20-16} = dst; - let Inst{12} = isTak; - let Inst{11} = isPredNew; - let Inst{9-8} = src; -} - -multiclass JMPR_Pred<bit PredNot> { - def NAME : T_JMPr_c<PredNot, 0, 0>; // not taken - // Predicate new - def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken - def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken -} - -multiclass JMPR_base<string BaseOp> { - let BaseOpcode = BaseOp in { - def NAME : T_JMPr; - defm t : JMPR_Pred<0>; - defm f : JMPR_Pred<1>; - } -} - -let isCall = 1, hasSideEffects = 1 in -class JUMPR_MISC_CALLR<bit isPred, bit isPredNot, - dag InputDag = (ins IntRegs:$Rs)> - : JRInst<(outs), InputDag, - !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs", - "if ($Pu) callr $Rs"), - "callr $Rs"), - [], "", J_tc_2early_SLOT2> { - bits<5> Rs; - bits<2> Pu; - let isPredicated = isPred; - let isPredicatedFalse = isPredNot; - - let IClass = 0b0101; - let Inst{27-25} = 0b000; - let Inst{24-23} = !if (isPred, 0b10, 0b01); - let Inst{22} = 0; - let Inst{21} = isPredNot; - let Inst{9-8} = !if (isPred, Pu, 0b00); - let Inst{20-16} = Rs; - - } - -let Defs = VolatileV3.Regs in { - def J2_callrt : JUMPR_MISC_CALLR<1, 0, (ins PredRegs:$Pu, IntRegs:$Rs)>; - def J2_callrf : JUMPR_MISC_CALLR<1, 1, (ins PredRegs:$Pu, IntRegs:$Rs)>; -} - -let isTerminator = 1, hasSideEffects = 0 in { - defm J2_jump : JMP_base<"JMP", "">, PredNewRel; - - defm J2_jumpr : JMPR_base<"JMPr">, PredNewRel; - - let isReturn = 1, isPseudo = 1, isCodeGenOnly = 1 in - defm PS_jmpret : JMPR_base<"JMPret">, PredNewRel; -} - -let validSubTargets = HasV60SubT in -multiclass JMPpt_base<string BaseOp> { - let BaseOpcode = BaseOp in { - def tpt : T_JMP_c <0, 0, 1, "">; // Predicate true - taken - def fpt : T_JMP_c <1, 0, 1, "">; // Predicate false - taken - } -} - -let validSubTargets = HasV60SubT in -multiclass JMPRpt_base<string BaseOp> { - let BaseOpcode = BaseOp in { - def tpt : T_JMPr_c<0, 0, 1>; // predicate true - taken - def fpt : T_JMPr_c<1, 0, 1>; // predicate false - taken - } -} - -defm J2_jumpr : JMPRpt_base<"JMPr">; -defm J2_jump : JMPpt_base<"JMP">; - -// A return through builtin_eh_return. -let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0, - isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in -def EH_RETURN_JMPR : T_JMPr; - -//===----------------------------------------------------------------------===// -// JR - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// LD + -//===----------------------------------------------------------------------===// - -// Load - Base with Immediate offset addressing mode -let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, AddedComplexity = 20 in -class T_load_io <string mnemonic, RegisterClass RC, bits<4> MajOp, - Operand ImmOp> - : LDInst<(outs RC:$dst), (ins IntRegs:$src1, ImmOp:$offset), - "$dst = "#mnemonic#"($src1 + #$offset)", []>, AddrModeRel { - bits<4> name; - bits<5> dst; - bits<5> src1; - bits<14> offset; - bits<11> offsetBits; - - string ImmOpStr = !cast<string>(ImmOp); - let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), offset{13-3}, - !if (!eq(ImmOpStr, "s11_2Ext"), offset{12-2}, - !if (!eq(ImmOpStr, "s11_1Ext"), offset{11-1}, - /* s11_0Ext */ offset{10-0}))); - let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14, - !if (!eq(ImmOpStr, "s11_2Ext"), 13, - !if (!eq(ImmOpStr, "s11_1Ext"), 12, - /* s11_0Ext */ 11))); - let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1); - - let IClass = 0b1001; - - let Inst{27} = 0b0; - let Inst{26-25} = offsetBits{10-9}; - let Inst{24-21} = MajOp; - let Inst{20-16} = src1; - let Inst{13-5} = offsetBits{8-0}; - let Inst{4-0} = dst; - } - -let opExtendable = 3, isExtentSigned = 0, isPredicated = 1 in -class T_pload_io <string mnemonic, RegisterClass RC, bits<4>MajOp, - Operand ImmOp, bit isNot, bit isPredNew> - : LDInst<(outs RC:$dst), - (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset), - "if ("#!if(isNot, "!$src1", "$src1") - #!if(isPredNew, ".new", "") - #") $dst = "#mnemonic#"($src2 + #$offset)", - [],"", V2LDST_tc_ld_SLOT01> , AddrModeRel { - bits<5> dst; - bits<2> src1; - bits<5> src2; - bits<9> offset; - bits<6> offsetBits; - string ImmOpStr = !cast<string>(ImmOp); - - let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), offset{8-3}, - !if (!eq(ImmOpStr, "u6_2Ext"), offset{7-2}, - !if (!eq(ImmOpStr, "u6_1Ext"), offset{6-1}, - /* u6_0Ext */ offset{5-0}))); - let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9, - !if (!eq(ImmOpStr, "u6_2Ext"), 8, - !if (!eq(ImmOpStr, "u6_1Ext"), 7, - /* u6_0Ext */ 6))); - let hasNewValue = !if (!eq(ImmOpStr, "u6_3Ext"), 0, 1); - let isPredicatedNew = isPredNew; - let isPredicatedFalse = isNot; - - let IClass = 0b0100; - - let Inst{27} = 0b0; - let Inst{27} = 0b0; - let Inst{26} = isNot; - let Inst{25} = isPredNew; - let Inst{24-21} = MajOp; - let Inst{20-16} = src2; - let Inst{13} = 0b0; - let Inst{12-11} = src1; - let Inst{10-5} = offsetBits; - let Inst{4-0} = dst; - } - -let isExtendable = 1, hasSideEffects = 0, addrMode = BaseImmOffset in -multiclass LD_Idxd<string mnemonic, string CextOp, RegisterClass RC, - Operand ImmOp, Operand predImmOp, bits<4>MajOp> { - let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in { - let isPredicable = 1 in - def L2_#NAME#_io : T_load_io <mnemonic, RC, MajOp, ImmOp>; - - // Predicated - def L2_p#NAME#t_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 0>; - def L2_p#NAME#f_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 0>; - - // Predicated new - def L2_p#NAME#tnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 0, 1>; - def L2_p#NAME#fnew_io : T_pload_io <mnemonic, RC, MajOp, predImmOp, 1, 1>; - } -} - -let accessSize = ByteAccess in { - defm loadrb: LD_Idxd <"memb", "LDrib", IntRegs, s11_0Ext, u6_0Ext, 0b1000>; - defm loadrub: LD_Idxd <"memub", "LDriub", IntRegs, s11_0Ext, u6_0Ext, 0b1001>; -} - -let accessSize = HalfWordAccess, opExtentAlign = 1 in { - defm loadrh: LD_Idxd <"memh", "LDrih", IntRegs, s11_1Ext, u6_1Ext, 0b1010>; - defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>; -} - -let accessSize = WordAccess, opExtentAlign = 2 in -defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>; - -let accessSize = DoubleWordAccess, opExtentAlign = 3 in -defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>; - -let accessSize = HalfWordAccess, opExtentAlign = 1 in { - def L2_loadbsw2_io: T_load_io<"membh", IntRegs, 0b0001, s11_1Ext>; - def L2_loadbzw2_io: T_load_io<"memubh", IntRegs, 0b0011, s11_1Ext>; -} - -let accessSize = WordAccess, opExtentAlign = 2 in { - def L2_loadbzw4_io: T_load_io<"memubh", DoubleRegs, 0b0101, s11_2Ext>; - def L2_loadbsw4_io: T_load_io<"membh", DoubleRegs, 0b0111, s11_2Ext>; -} - -let addrMode = BaseImmOffset, isExtendable = 1, hasSideEffects = 0, - opExtendable = 3, isExtentSigned = 1 in -class T_loadalign_io <string str, bits<4> MajOp, Operand ImmOp> - : LDInst<(outs DoubleRegs:$dst), - (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset), - "$dst = "#str#"($src2 + #$offset)", [], - "$src1 = $dst">, AddrModeRel { - bits<4> name; - bits<5> dst; - bits<5> src2; - bits<12> offset; - bits<11> offsetBits; - - let offsetBits = !if (!eq(!cast<string>(ImmOp), "s11_1Ext"), offset{11-1}, - /* s11_0Ext */ offset{10-0}); - let IClass = 0b1001; - - let Inst{27} = 0b0; - let Inst{26-25} = offsetBits{10-9}; - let Inst{24-21} = MajOp; - let Inst{20-16} = src2; - let Inst{13-5} = offsetBits{8-0}; - let Inst{4-0} = dst; - } - -let accessSize = HalfWordAccess, opExtentBits = 12, opExtentAlign = 1 in -def L2_loadalignh_io: T_loadalign_io <"memh_fifo", 0b0010, s11_1Ext>; - -let accessSize = ByteAccess, opExtentBits = 11 in -def L2_loadalignb_io: T_loadalign_io <"memb_fifo", 0b0100, s11_0Ext>; - -//===----------------------------------------------------------------------===// -// Post increment load -//===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// Template class for non-predicated post increment loads with immediate offset. -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, addrMode = PostInc in -class T_load_pi <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<4> MajOp > - : LDInstPI <(outs RC:$dst, IntRegs:$dst2), - (ins IntRegs:$src1, ImmOp:$offset), - "$dst = "#mnemonic#"($src1++#$offset)" , - [], - "$src1 = $dst2" > , - PredNewRel { - bits<5> dst; - bits<5> src1; - bits<7> offset; - bits<4> offsetBits; - - string ImmOpStr = !cast<string>(ImmOp); - let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, - !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, - !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, - /* s4_0Imm */ offset{3-0}))); - let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1); - - let IClass = 0b1001; - - let Inst{27-25} = 0b101; - let Inst{24-21} = MajOp; - let Inst{20-16} = src1; - let Inst{13-12} = 0b00; - let Inst{8-5} = offsetBits; - let Inst{4-0} = dst; - } - -//===----------------------------------------------------------------------===// -// Template class for predicated post increment loads with immediate offset. -//===----------------------------------------------------------------------===// -let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in -class T_pload_pi <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<4> MajOp, bit isPredNot, bit isPredNew > - : LDInst <(outs RC:$dst, IntRegs:$dst2), - (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset), - !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#"$dst = "#mnemonic#"($src2++#$offset)", - [] , - "$src2 = $dst2" > , - PredNewRel { - bits<5> dst; - bits<2> src1; - bits<5> src2; - bits<7> offset; - bits<4> offsetBits; - - let isPredicatedNew = isPredNew; - let isPredicatedFalse = isPredNot; - - string ImmOpStr = !cast<string>(ImmOp); - let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, - !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, - !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, - /* s4_0Imm */ offset{3-0}))); - let hasNewValue = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1); - - let IClass = 0b1001; - - let Inst{27-25} = 0b101; - let Inst{24-21} = MajOp; - let Inst{20-16} = src2; - let Inst{13} = 0b1; - let Inst{12} = isPredNew; - let Inst{11} = isPredNot; - let Inst{10-9} = src1; - let Inst{8-5} = offsetBits; - let Inst{4-0} = dst; - } - -//===----------------------------------------------------------------------===// -// Multiclass for post increment loads with immediate offset. -//===----------------------------------------------------------------------===// - -multiclass LD_PostInc <string mnemonic, string BaseOp, RegisterClass RC, - Operand ImmOp, bits<4> MajOp> { - let BaseOpcode = "POST_"#BaseOp in { - let isPredicable = 1 in - def L2_#NAME#_pi : T_load_pi < mnemonic, RC, ImmOp, MajOp>; - - // Predicated - def L2_p#NAME#t_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 0>; - def L2_p#NAME#f_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 0>; - - // Predicated new - def L2_p#NAME#tnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 0, 1>; - def L2_p#NAME#fnew_pi : T_pload_pi < mnemonic, RC, ImmOp, MajOp, 1, 1>; - } -} - -// post increment byte loads with immediate offset -let accessSize = ByteAccess in { - defm loadrb : LD_PostInc <"memb", "LDrib", IntRegs, s4_0Imm, 0b1000>; - defm loadrub : LD_PostInc <"memub", "LDriub", IntRegs, s4_0Imm, 0b1001>; -} - -// post increment halfword loads with immediate offset -let accessSize = HalfWordAccess, opExtentAlign = 1 in { - defm loadrh : LD_PostInc <"memh", "LDrih", IntRegs, s4_1Imm, 0b1010>; - defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>; -} - -// post increment word loads with immediate offset -let accessSize = WordAccess, opExtentAlign = 2 in -defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>; - -// post increment doubleword loads with immediate offset -let accessSize = DoubleWordAccess, opExtentAlign = 3 in -defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>; - -// Rd=memb[u]h(Rx++#s4:1) -// Rdd=memb[u]h(Rx++#s4:2) -let accessSize = HalfWordAccess, opExtentAlign = 1 in { - def L2_loadbsw2_pi : T_load_pi <"membh", IntRegs, s4_1Imm, 0b0001>; - def L2_loadbzw2_pi : T_load_pi <"memubh", IntRegs, s4_1Imm, 0b0011>; -} -let accessSize = WordAccess, opExtentAlign = 2, hasNewValue = 0 in { - def L2_loadbsw4_pi : T_load_pi <"membh", DoubleRegs, s4_2Imm, 0b0111>; - def L2_loadbzw4_pi : T_load_pi <"memubh", DoubleRegs, s4_2Imm, 0b0101>; -} - -//===----------------------------------------------------------------------===// -// Template class for post increment fifo loads with immediate offset. -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, addrMode = PostInc in -class T_loadalign_pi <string mnemonic, Operand ImmOp, bits<4> MajOp > - : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$dst2), - (ins DoubleRegs:$src1, IntRegs:$src2, ImmOp:$offset), - "$dst = "#mnemonic#"($src2++#$offset)" , - [], "$src2 = $dst2, $src1 = $dst" > , - PredNewRel { - bits<5> dst; - bits<5> src2; - bits<5> offset; - bits<4> offsetBits; - - let offsetBits = !if (!eq(!cast<string>(ImmOp), "s4_1Imm"), offset{4-1}, - /* s4_0Imm */ offset{3-0}); - let IClass = 0b1001; - - let Inst{27-25} = 0b101; - let Inst{24-21} = MajOp; - let Inst{20-16} = src2; - let Inst{13-12} = 0b00; - let Inst{8-5} = offsetBits; - let Inst{4-0} = dst; - } - -// Ryy=memh_fifo(Rx++#s4:1) -// Ryy=memb_fifo(Rx++#s4:0) -let accessSize = ByteAccess in -def L2_loadalignb_pi : T_loadalign_pi <"memb_fifo", s4_0Imm, 0b0100>; - -let accessSize = HalfWordAccess, opExtentAlign = 1 in -def L2_loadalignh_pi : T_loadalign_pi <"memh_fifo", s4_1Imm, 0b0010>; - -//===----------------------------------------------------------------------===// -// Template class for post increment loads with register offset. -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, addrMode = PostInc in -class T_load_pr <string mnemonic, RegisterClass RC, bits<4> MajOp, - MemAccessSize AccessSz> - : LDInstPI <(outs RC:$dst, IntRegs:$_dst_), - (ins IntRegs:$src1, ModRegs:$src2), - "$dst = "#mnemonic#"($src1++$src2)" , - [], "$src1 = $_dst_" > { - bits<5> dst; - bits<5> src1; - bits<1> src2; - - let accessSize = AccessSz; - let IClass = 0b1001; - - let Inst{27-25} = 0b110; - let Inst{24-21} = MajOp; - let Inst{20-16} = src1; - let Inst{13} = src2; - let Inst{12} = 0b0; - let Inst{7} = 0b0; - let Inst{4-0} = dst; - } - -let hasNewValue = 1 in { - def L2_loadrb_pr : T_load_pr <"memb", IntRegs, 0b1000, ByteAccess>; - def L2_loadrub_pr : T_load_pr <"memub", IntRegs, 0b1001, ByteAccess>; - def L2_loadrh_pr : T_load_pr <"memh", IntRegs, 0b1010, HalfWordAccess>; - def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>; - def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>; - - def L2_loadbzw2_pr : T_load_pr <"memubh", IntRegs, 0b0011, HalfWordAccess>; -} - -def L2_loadrd_pr : T_load_pr <"memd", DoubleRegs, 0b1110, DoubleWordAccess>; -def L2_loadbzw4_pr : T_load_pr <"memubh", DoubleRegs, 0b0101, WordAccess>; - -// Load predicate. -let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13, - isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in -def LDriw_pred : LDInst<(outs PredRegs:$dst), - (ins IntRegs:$addr, s11_2Ext:$off), - ".error \"should not emit\"", []>; -// Load modifier. -let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13, - isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in -def LDriw_mod : LDInst<(outs ModRegs:$dst), - (ins IntRegs:$addr, s11_2Ext:$off), - ".error \"should not emit\"", []>; - -let Defs = [R29, R30, R31], Uses = [R30], hasSideEffects = 0 in - def L2_deallocframe : LDInst<(outs), (ins), - "deallocframe", - []> { - let IClass = 0b1001; - - let Inst{27-16} = 0b000000011110; - let Inst{13} = 0b0; - let Inst{4-0} = 0b11110; -} - -// Load / Post increment circular addressing mode. -let Uses = [CS], hasSideEffects = 0, addrMode = PostInc in -class T_load_pcr<string mnemonic, RegisterClass RC, bits<4> MajOp> - : LDInst <(outs RC:$dst, IntRegs:$_dst_), - (ins IntRegs:$Rz, ModRegs:$Mu), - "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [], - "$Rz = $_dst_" > { - bits<5> dst; - bits<5> Rz; - bit Mu; - - let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1); - let IClass = 0b1001; - - let Inst{27-25} = 0b100; - let Inst{24-21} = MajOp; - let Inst{20-16} = Rz; - let Inst{13} = Mu; - let Inst{12} = 0b0; - let Inst{9} = 0b1; - let Inst{7} = 0b0; - let Inst{4-0} = dst; - } - -let accessSize = ByteAccess in { - def L2_loadrb_pcr : T_load_pcr <"memb", IntRegs, 0b1000>; - def L2_loadrub_pcr : T_load_pcr <"memub", IntRegs, 0b1001>; -} - -let accessSize = HalfWordAccess in { - def L2_loadrh_pcr : T_load_pcr <"memh", IntRegs, 0b1010>; - def L2_loadruh_pcr : T_load_pcr <"memuh", IntRegs, 0b1011>; - def L2_loadbsw2_pcr : T_load_pcr <"membh", IntRegs, 0b0001>; - def L2_loadbzw2_pcr : T_load_pcr <"memubh", IntRegs, 0b0011>; -} - -let accessSize = WordAccess in { - def L2_loadri_pcr : T_load_pcr <"memw", IntRegs, 0b1100>; - let hasNewValue = 0 in { - def L2_loadbzw4_pcr : T_load_pcr <"memubh", DoubleRegs, 0b0101>; - def L2_loadbsw4_pcr : T_load_pcr <"membh", DoubleRegs, 0b0111>; - } -} - -let accessSize = DoubleWordAccess in -def L2_loadrd_pcr : T_load_pcr <"memd", DoubleRegs, 0b1110>; - -// Load / Post increment circular addressing mode. -let Uses = [CS], hasSideEffects = 0, addrMode = PostInc in -class T_loadalign_pcr<string mnemonic, bits<4> MajOp, MemAccessSize AccessSz > - : LDInst <(outs DoubleRegs:$dst, IntRegs:$_dst_), - (ins DoubleRegs:$_src_, IntRegs:$Rz, ModRegs:$Mu), - "$dst = "#mnemonic#"($Rz ++ I:circ($Mu))", [], - "$Rz = $_dst_, $dst = $_src_" > { - bits<5> dst; - bits<5> Rz; - bit Mu; - - let accessSize = AccessSz; - let IClass = 0b1001; - - let Inst{27-25} = 0b100; - let Inst{24-21} = MajOp; - let Inst{20-16} = Rz; - let Inst{13} = Mu; - let Inst{12} = 0b0; - let Inst{9} = 0b1; - let Inst{7} = 0b0; - let Inst{4-0} = dst; - } - -def L2_loadalignb_pcr : T_loadalign_pcr <"memb_fifo", 0b0100, ByteAccess>; -def L2_loadalignh_pcr : T_loadalign_pcr <"memh_fifo", 0b0010, HalfWordAccess>; - -//===----------------------------------------------------------------------===// -// Circular loads with immediate offset. -//===----------------------------------------------------------------------===// -let Uses = [CS], mayLoad = 1, hasSideEffects = 0, addrMode = PostInc in -class T_load_pci <string mnemonic, RegisterClass RC, - Operand ImmOp, bits<4> MajOp> - : LDInstPI<(outs RC:$dst, IntRegs:$_dst_), - (ins IntRegs:$Rz, ImmOp:$offset, ModRegs:$Mu), - "$dst = "#mnemonic#"($Rz ++ #$offset:circ($Mu))", [], - "$Rz = $_dst_"> { - bits<5> dst; - bits<5> Rz; - bits<1> Mu; - bits<7> offset; - bits<4> offsetBits; - - string ImmOpStr = !cast<string>(ImmOp); - let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1); - let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, - !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, - !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, - /* s4_0Imm */ offset{3-0}))); - let IClass = 0b1001; - let Inst{27-25} = 0b100; - let Inst{24-21} = MajOp; - let Inst{20-16} = Rz; - let Inst{13} = Mu; - let Inst{12} = 0b0; - let Inst{9} = 0b0; - let Inst{8-5} = offsetBits; - let Inst{4-0} = dst; - } - -// Byte variants of circ load -let accessSize = ByteAccess in { - def L2_loadrb_pci : T_load_pci <"memb", IntRegs, s4_0Imm, 0b1000>; - def L2_loadrub_pci : T_load_pci <"memub", IntRegs, s4_0Imm, 0b1001>; -} - -// Half word variants of circ load -let accessSize = HalfWordAccess in { - def L2_loadrh_pci : T_load_pci <"memh", IntRegs, s4_1Imm, 0b1010>; - def L2_loadruh_pci : T_load_pci <"memuh", IntRegs, s4_1Imm, 0b1011>; - def L2_loadbzw2_pci : T_load_pci <"memubh", IntRegs, s4_1Imm, 0b0011>; - def L2_loadbsw2_pci : T_load_pci <"membh", IntRegs, s4_1Imm, 0b0001>; -} - -// Word variants of circ load -let accessSize = WordAccess in -def L2_loadri_pci : T_load_pci <"memw", IntRegs, s4_2Imm, 0b1100>; - -let accessSize = WordAccess, hasNewValue = 0 in { - def L2_loadbzw4_pci : T_load_pci <"memubh", DoubleRegs, s4_2Imm, 0b0101>; - def L2_loadbsw4_pci : T_load_pci <"membh", DoubleRegs, s4_2Imm, 0b0111>; -} - -let accessSize = DoubleWordAccess, hasNewValue = 0 in -def L2_loadrd_pci : T_load_pci <"memd", DoubleRegs, s4_3Imm, 0b1110>; - - -// TODO: memb_fifo and memh_fifo must take destination register as input. -// One-off circ loads - not enough in common to break into a class. -let accessSize = ByteAccess in -def L2_loadalignb_pci : T_load_pci <"memb_fifo", DoubleRegs, s4_0Imm, 0b0100>; - -let accessSize = HalfWordAccess, opExtentAlign = 1 in -def L2_loadalignh_pci : T_load_pci <"memh_fifo", DoubleRegs, s4_1Imm, 0b0010>; - -// L[24]_load[wd]_locked: Load word/double with lock. -let isSoloAX = 1 in -class T_load_locked <string mnemonic, RegisterClass RC> - : LD0Inst <(outs RC:$dst), - (ins IntRegs:$src), - "$dst = "#mnemonic#"($src)"> { - bits<5> dst; - bits<5> src; - let IClass = 0b1001; - let Inst{27-21} = 0b0010000; - let Inst{20-16} = src; - let Inst{13-12} = !if (!eq(mnemonic, "memd_locked"), 0b01, 0b00); - let Inst{5} = 0; - let Inst{4-0} = dst; -} -let hasNewValue = 1, accessSize = WordAccess, opNewValue = 0 in - def L2_loadw_locked : T_load_locked <"memw_locked", IntRegs>; -let accessSize = DoubleWordAccess in - def L4_loadd_locked : T_load_locked <"memd_locked", DoubleRegs>; - -// S[24]_store[wd]_locked: Store word/double conditionally. -let isSoloAX = 1, isPredicateLate = 1 in -class T_store_locked <string mnemonic, RegisterClass RC> - : ST0Inst <(outs PredRegs:$Pd), (ins IntRegs:$Rs, RC:$Rt), - mnemonic#"($Rs, $Pd) = $Rt"> { - bits<2> Pd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1010; - let Inst{27-23} = 0b00001; - let Inst{22} = !if (!eq(mnemonic, "memw_locked"), 0b0, 0b1); - let Inst{21} = 0b1; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{1-0} = Pd; -} - -let accessSize = WordAccess in -def S2_storew_locked : T_store_locked <"memw_locked", IntRegs>; - -let accessSize = DoubleWordAccess in -def S4_stored_locked : T_store_locked <"memd_locked", DoubleRegs>; - -//===----------------------------------------------------------------------===// -// Bit-reversed loads with auto-increment register -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, addrMode = PostInc in -class T_load_pbr<string mnemonic, RegisterClass RC, - MemAccessSize addrSize, bits<4> majOp> - : LDInst - <(outs RC:$dst, IntRegs:$_dst_), - (ins IntRegs:$Rz, ModRegs:$Mu), - "$dst = "#mnemonic#"($Rz ++ $Mu:brev)" , - [] , "$Rz = $_dst_" > { - - let accessSize = addrSize; - - bits<5> dst; - bits<5> Rz; - bits<1> Mu; - - let IClass = 0b1001; - - let Inst{27-25} = 0b111; - let Inst{24-21} = majOp; - let Inst{20-16} = Rz; - let Inst{13} = Mu; - let Inst{12} = 0b0; - let Inst{7} = 0b0; - let Inst{4-0} = dst; - } - -let hasNewValue =1, opNewValue = 0 in { - def L2_loadrb_pbr : T_load_pbr <"memb", IntRegs, ByteAccess, 0b1000>; - def L2_loadrub_pbr : T_load_pbr <"memub", IntRegs, ByteAccess, 0b1001>; - def L2_loadrh_pbr : T_load_pbr <"memh", IntRegs, HalfWordAccess, 0b1010>; - def L2_loadruh_pbr : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>; - def L2_loadbsw2_pbr : T_load_pbr <"membh", IntRegs, HalfWordAccess, 0b0001>; - def L2_loadbzw2_pbr : T_load_pbr <"memubh", IntRegs, HalfWordAccess, 0b0011>; - def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>; -} - -def L2_loadbzw4_pbr : T_load_pbr <"memubh", DoubleRegs, WordAccess, 0b0101>; -def L2_loadbsw4_pbr : T_load_pbr <"membh", DoubleRegs, WordAccess, 0b0111>; -def L2_loadrd_pbr : T_load_pbr <"memd", DoubleRegs, DoubleWordAccess, 0b1110>; - -def L2_loadalignb_pbr :T_load_pbr <"memb_fifo", DoubleRegs, ByteAccess, 0b0100>; -def L2_loadalignh_pbr :T_load_pbr <"memh_fifo", DoubleRegs, - HalfWordAccess, 0b0010>; - -//===----------------------------------------------------------------------===// -// LD - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// MTYPE/ALU + -//===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// MTYPE/ALU - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// MTYPE/COMPLEX + -//===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// MTYPE/COMPLEX - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// MTYPE/MPYH + -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// Template Class -// MPYS / Multipy signed/unsigned halfwords -//Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat] -//===----------------------------------------------------------------------===// - -let hasNewValue = 1, opNewValue = 0 in -class T_M2_mpy < bits<2> LHbits, bit isSat, bit isRnd, - bit hasShift, bit isUnsigned> - : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l") - #", $Rt."#!if(LHbits{0},"h)","l)") - #!if(hasShift,":<<1","") - #!if(isRnd,":rnd","") - #!if(isSat,":sat",""), - [], "", M_tc_3x_SLOT23 > { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1100; - let Inst{23} = hasShift; - let Inst{22} = isUnsigned; - let Inst{21} = isRnd; - let Inst{7} = isSat; - let Inst{6-5} = LHbits; - let Inst{4-0} = Rd; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - } - -//Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1] -def M2_mpy_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 0>; -def M2_mpy_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 0>; -def M2_mpy_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 0>; -def M2_mpy_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 0>; -def M2_mpy_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 0>; -def M2_mpy_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 0>; -def M2_mpy_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 0>; -def M2_mpy_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 0>; - -//Rd=mpyu(Rs.[H|L],Rt.[H|L])[:<<1] -def M2_mpyu_ll_s1: T_M2_mpy<0b00, 0, 0, 1, 1>; -def M2_mpyu_ll_s0: T_M2_mpy<0b00, 0, 0, 0, 1>; -def M2_mpyu_lh_s1: T_M2_mpy<0b01, 0, 0, 1, 1>; -def M2_mpyu_lh_s0: T_M2_mpy<0b01, 0, 0, 0, 1>; -def M2_mpyu_hl_s1: T_M2_mpy<0b10, 0, 0, 1, 1>; -def M2_mpyu_hl_s0: T_M2_mpy<0b10, 0, 0, 0, 1>; -def M2_mpyu_hh_s1: T_M2_mpy<0b11, 0, 0, 1, 1>; -def M2_mpyu_hh_s0: T_M2_mpy<0b11, 0, 0, 0, 1>; - -//Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1]:rnd -def M2_mpy_rnd_ll_s1: T_M2_mpy <0b00, 0, 1, 1, 0>; -def M2_mpy_rnd_ll_s0: T_M2_mpy <0b00, 0, 1, 0, 0>; -def M2_mpy_rnd_lh_s1: T_M2_mpy <0b01, 0, 1, 1, 0>; -def M2_mpy_rnd_lh_s0: T_M2_mpy <0b01, 0, 1, 0, 0>; -def M2_mpy_rnd_hl_s1: T_M2_mpy <0b10, 0, 1, 1, 0>; -def M2_mpy_rnd_hl_s0: T_M2_mpy <0b10, 0, 1, 0, 0>; -def M2_mpy_rnd_hh_s1: T_M2_mpy <0b11, 0, 1, 1, 0>; -def M2_mpy_rnd_hh_s0: T_M2_mpy <0b11, 0, 1, 0, 0>; - -//Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:sat] -//Rd=mpy(Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat] -let Defs = [USR_OVF] in { - def M2_mpy_sat_ll_s1: T_M2_mpy <0b00, 1, 0, 1, 0>; - def M2_mpy_sat_ll_s0: T_M2_mpy <0b00, 1, 0, 0, 0>; - def M2_mpy_sat_lh_s1: T_M2_mpy <0b01, 1, 0, 1, 0>; - def M2_mpy_sat_lh_s0: T_M2_mpy <0b01, 1, 0, 0, 0>; - def M2_mpy_sat_hl_s1: T_M2_mpy <0b10, 1, 0, 1, 0>; - def M2_mpy_sat_hl_s0: T_M2_mpy <0b10, 1, 0, 0, 0>; - def M2_mpy_sat_hh_s1: T_M2_mpy <0b11, 1, 0, 1, 0>; - def M2_mpy_sat_hh_s0: T_M2_mpy <0b11, 1, 0, 0, 0>; - - def M2_mpy_sat_rnd_ll_s1: T_M2_mpy <0b00, 1, 1, 1, 0>; - def M2_mpy_sat_rnd_ll_s0: T_M2_mpy <0b00, 1, 1, 0, 0>; - def M2_mpy_sat_rnd_lh_s1: T_M2_mpy <0b01, 1, 1, 1, 0>; - def M2_mpy_sat_rnd_lh_s0: T_M2_mpy <0b01, 1, 1, 0, 0>; - def M2_mpy_sat_rnd_hl_s1: T_M2_mpy <0b10, 1, 1, 1, 0>; - def M2_mpy_sat_rnd_hl_s0: T_M2_mpy <0b10, 1, 1, 0, 0>; - def M2_mpy_sat_rnd_hh_s1: T_M2_mpy <0b11, 1, 1, 1, 0>; - def M2_mpy_sat_rnd_hh_s0: T_M2_mpy <0b11, 1, 1, 0, 0>; -} - -//===----------------------------------------------------------------------===// -// Template Class -// MPYS / Multipy signed/unsigned halfwords and add/subtract the -// result from the accumulator. -//Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat] -//===----------------------------------------------------------------------===// - -let hasNewValue = 1, opNewValue = 0 in -class T_M2_mpy_acc < bits<2> LHbits, bit isSat, bit isNac, - bit hasShift, bit isUnsigned > - : MInst_acc<(outs IntRegs:$Rx), (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt), - "$Rx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy") - #"($Rs."#!if(LHbits{1},"h","l") - #", $Rt."#!if(LHbits{0},"h)","l)") - #!if(hasShift,":<<1","") - #!if(isSat,":sat",""), - [], "$dst2 = $Rx", M_tc_3x_SLOT23 > { - bits<5> Rx; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1110; - let Inst{27-24} = 0b1110; - let Inst{23} = hasShift; - let Inst{22} = isUnsigned; - let Inst{21} = isNac; - let Inst{7} = isSat; - let Inst{6-5} = LHbits; - let Inst{4-0} = Rx; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - } - -//Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1] -def M2_mpy_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 0>; -def M2_mpy_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 0>; -def M2_mpy_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 0>; -def M2_mpy_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 0>; -def M2_mpy_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 0>; -def M2_mpy_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 0>; -def M2_mpy_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 0>; -def M2_mpy_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 0>; - -//Rx += mpyu(Rs.[H|L],Rt.[H|L])[:<<1] -def M2_mpyu_acc_ll_s1: T_M2_mpy_acc <0b00, 0, 0, 1, 1>; -def M2_mpyu_acc_ll_s0: T_M2_mpy_acc <0b00, 0, 0, 0, 1>; -def M2_mpyu_acc_lh_s1: T_M2_mpy_acc <0b01, 0, 0, 1, 1>; -def M2_mpyu_acc_lh_s0: T_M2_mpy_acc <0b01, 0, 0, 0, 1>; -def M2_mpyu_acc_hl_s1: T_M2_mpy_acc <0b10, 0, 0, 1, 1>; -def M2_mpyu_acc_hl_s0: T_M2_mpy_acc <0b10, 0, 0, 0, 1>; -def M2_mpyu_acc_hh_s1: T_M2_mpy_acc <0b11, 0, 0, 1, 1>; -def M2_mpyu_acc_hh_s0: T_M2_mpy_acc <0b11, 0, 0, 0, 1>; - -//Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1] -def M2_mpy_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 0>; -def M2_mpy_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 0>; -def M2_mpy_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 0>; -def M2_mpy_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 0>; -def M2_mpy_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 0>; -def M2_mpy_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 0>; -def M2_mpy_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 0>; -def M2_mpy_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 0>; - -//Rx -= mpyu(Rs.[H|L],Rt.[H|L])[:<<1] -def M2_mpyu_nac_ll_s1: T_M2_mpy_acc <0b00, 0, 1, 1, 1>; -def M2_mpyu_nac_ll_s0: T_M2_mpy_acc <0b00, 0, 1, 0, 1>; -def M2_mpyu_nac_lh_s1: T_M2_mpy_acc <0b01, 0, 1, 1, 1>; -def M2_mpyu_nac_lh_s0: T_M2_mpy_acc <0b01, 0, 1, 0, 1>; -def M2_mpyu_nac_hl_s1: T_M2_mpy_acc <0b10, 0, 1, 1, 1>; -def M2_mpyu_nac_hl_s0: T_M2_mpy_acc <0b10, 0, 1, 0, 1>; -def M2_mpyu_nac_hh_s1: T_M2_mpy_acc <0b11, 0, 1, 1, 1>; -def M2_mpyu_nac_hh_s0: T_M2_mpy_acc <0b11, 0, 1, 0, 1>; - -//Rx += mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat -def M2_mpy_acc_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 0, 1, 0>; -def M2_mpy_acc_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 0, 0, 0>; -def M2_mpy_acc_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 0, 1, 0>; -def M2_mpy_acc_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 0, 0, 0>; -def M2_mpy_acc_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 0, 1, 0>; -def M2_mpy_acc_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 0, 0, 0>; -def M2_mpy_acc_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 0, 1, 0>; -def M2_mpy_acc_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 0, 0, 0>; - -//Rx -= mpy(Rs.[H|L],Rt.[H|L])[:<<1]:sat -def M2_mpy_nac_sat_ll_s1: T_M2_mpy_acc <0b00, 1, 1, 1, 0>; -def M2_mpy_nac_sat_ll_s0: T_M2_mpy_acc <0b00, 1, 1, 0, 0>; -def M2_mpy_nac_sat_lh_s1: T_M2_mpy_acc <0b01, 1, 1, 1, 0>; -def M2_mpy_nac_sat_lh_s0: T_M2_mpy_acc <0b01, 1, 1, 0, 0>; -def M2_mpy_nac_sat_hl_s1: T_M2_mpy_acc <0b10, 1, 1, 1, 0>; -def M2_mpy_nac_sat_hl_s0: T_M2_mpy_acc <0b10, 1, 1, 0, 0>; -def M2_mpy_nac_sat_hh_s1: T_M2_mpy_acc <0b11, 1, 1, 1, 0>; -def M2_mpy_nac_sat_hh_s0: T_M2_mpy_acc <0b11, 1, 1, 0, 0>; - -//===----------------------------------------------------------------------===// -// Template Class -// MPYS / Multipy signed/unsigned halfwords and add/subtract the -// result from the 64-bit destination register. -//Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat] -//===----------------------------------------------------------------------===// - -class T_M2_mpyd_acc < bits<2> LHbits, bit isNac, bit hasShift, bit isUnsigned> - : MInst_acc<(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt), - "$Rxx "#!if(isNac,"-= ","+= ")#!if(isUnsigned,"mpyu","mpy") - #"($Rs."#!if(LHbits{1},"h","l") - #", $Rt."#!if(LHbits{0},"h)","l)") - #!if(hasShift,":<<1",""), - [], "$dst2 = $Rxx", M_tc_3x_SLOT23 > { - bits<5> Rxx; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b0110; - let Inst{23} = hasShift; - let Inst{22} = isUnsigned; - let Inst{21} = isNac; - let Inst{7} = 0; - let Inst{6-5} = LHbits; - let Inst{4-0} = Rxx; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - } - -def M2_mpyd_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 0>; -def M2_mpyd_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 0>; -def M2_mpyd_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 0>; -def M2_mpyd_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 0>; - -def M2_mpyd_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 0>; -def M2_mpyd_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 0>; -def M2_mpyd_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 0>; -def M2_mpyd_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 0>; - -def M2_mpyd_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 0>; -def M2_mpyd_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 0>; -def M2_mpyd_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 0>; -def M2_mpyd_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 0>; - -def M2_mpyd_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 0>; -def M2_mpyd_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 0>; -def M2_mpyd_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 0>; -def M2_mpyd_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 0>; - -def M2_mpyud_acc_hh_s0: T_M2_mpyd_acc <0b11, 0, 0, 1>; -def M2_mpyud_acc_hl_s0: T_M2_mpyd_acc <0b10, 0, 0, 1>; -def M2_mpyud_acc_lh_s0: T_M2_mpyd_acc <0b01, 0, 0, 1>; -def M2_mpyud_acc_ll_s0: T_M2_mpyd_acc <0b00, 0, 0, 1>; - -def M2_mpyud_acc_hh_s1: T_M2_mpyd_acc <0b11, 0, 1, 1>; -def M2_mpyud_acc_hl_s1: T_M2_mpyd_acc <0b10, 0, 1, 1>; -def M2_mpyud_acc_lh_s1: T_M2_mpyd_acc <0b01, 0, 1, 1>; -def M2_mpyud_acc_ll_s1: T_M2_mpyd_acc <0b00, 0, 1, 1>; - -def M2_mpyud_nac_hh_s0: T_M2_mpyd_acc <0b11, 1, 0, 1>; -def M2_mpyud_nac_hl_s0: T_M2_mpyd_acc <0b10, 1, 0, 1>; -def M2_mpyud_nac_lh_s0: T_M2_mpyd_acc <0b01, 1, 0, 1>; -def M2_mpyud_nac_ll_s0: T_M2_mpyd_acc <0b00, 1, 0, 1>; - -def M2_mpyud_nac_hh_s1: T_M2_mpyd_acc <0b11, 1, 1, 1>; -def M2_mpyud_nac_hl_s1: T_M2_mpyd_acc <0b10, 1, 1, 1>; -def M2_mpyud_nac_lh_s1: T_M2_mpyd_acc <0b01, 1, 1, 1>; -def M2_mpyud_nac_ll_s1: T_M2_mpyd_acc <0b00, 1, 1, 1>; - -//===----------------------------------------------------------------------===// -// Template Class -- Vector Multipy -// Used for complex multiply real or imaginary, dual multiply and even halfwords -//===----------------------------------------------------------------------===// -class T_M2_vmpy < string opc, bits<3> MajOp, bits<3> MinOp, bit hasShift, - bit isRnd, bit isSat > - : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Rdd = "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","") - #!if(isRnd,":rnd","") - #!if(isSat,":sat",""), - [] > { - bits<5> Rdd; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1000; - let Inst{23-21} = MajOp; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rdd; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - } - -// Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat -let Defs = [USR_OVF] in { -def M2_vcmpy_s1_sat_i: T_M2_vmpy <"vcmpyi", 0b110, 0b110, 1, 0, 1>; -def M2_vcmpy_s0_sat_i: T_M2_vmpy <"vcmpyi", 0b010, 0b110, 0, 0, 1>; - -// Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat -def M2_vcmpy_s1_sat_r: T_M2_vmpy <"vcmpyr", 0b101, 0b110, 1, 0, 1>; -def M2_vcmpy_s0_sat_r: T_M2_vmpy <"vcmpyr", 0b001, 0b110, 0, 0, 1>; - -// Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat -def M2_vdmpys_s1: T_M2_vmpy <"vdmpy", 0b100, 0b100, 1, 0, 1>; -def M2_vdmpys_s0: T_M2_vmpy <"vdmpy", 0b000, 0b100, 0, 0, 1>; - -// Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat -def M2_vmpy2es_s1: T_M2_vmpy <"vmpyeh", 0b100, 0b110, 1, 0, 1>; -def M2_vmpy2es_s0: T_M2_vmpy <"vmpyeh", 0b000, 0b110, 0, 0, 1>; - -//Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat -def M2_mmpyh_s0: T_M2_vmpy <"vmpywoh", 0b000, 0b111, 0, 0, 1>; -def M2_mmpyh_s1: T_M2_vmpy <"vmpywoh", 0b100, 0b111, 1, 0, 1>; -def M2_mmpyh_rs0: T_M2_vmpy <"vmpywoh", 0b001, 0b111, 0, 1, 1>; -def M2_mmpyh_rs1: T_M2_vmpy <"vmpywoh", 0b101, 0b111, 1, 1, 1>; - -//Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat -def M2_mmpyl_s0: T_M2_vmpy <"vmpyweh", 0b000, 0b101, 0, 0, 1>; -def M2_mmpyl_s1: T_M2_vmpy <"vmpyweh", 0b100, 0b101, 1, 0, 1>; -def M2_mmpyl_rs0: T_M2_vmpy <"vmpyweh", 0b001, 0b101, 0, 1, 1>; -def M2_mmpyl_rs1: T_M2_vmpy <"vmpyweh", 0b101, 0b101, 1, 1, 1>; - -//Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat -def M2_mmpyuh_s0: T_M2_vmpy <"vmpywouh", 0b010, 0b111, 0, 0, 1>; -def M2_mmpyuh_s1: T_M2_vmpy <"vmpywouh", 0b110, 0b111, 1, 0, 1>; -def M2_mmpyuh_rs0: T_M2_vmpy <"vmpywouh", 0b011, 0b111, 0, 1, 1>; -def M2_mmpyuh_rs1: T_M2_vmpy <"vmpywouh", 0b111, 0b111, 1, 1, 1>; - -//Rdd=vmpyweuh(Rss,Rtt)[:<<1][:rnd]:sat -def M2_mmpyul_s0: T_M2_vmpy <"vmpyweuh", 0b010, 0b101, 0, 0, 1>; -def M2_mmpyul_s1: T_M2_vmpy <"vmpyweuh", 0b110, 0b101, 1, 0, 1>; -def M2_mmpyul_rs0: T_M2_vmpy <"vmpyweuh", 0b011, 0b101, 0, 1, 1>; -def M2_mmpyul_rs1: T_M2_vmpy <"vmpyweuh", 0b111, 0b101, 1, 1, 1>; -} - -let hasNewValue = 1, opNewValue = 0 in -class T_MType_mpy <string mnemonic, bits<4> RegTyBits, RegisterClass RC, - bits<3> MajOp, bits<3> MinOp, bit isSat = 0, bit isRnd = 0, - string op2Suffix = "", bit isRaw = 0, bit isHi = 0 > - : MInst <(outs IntRegs:$dst), (ins RC:$src1, RC:$src2), - "$dst = "#mnemonic - #"($src1, $src2"#op2Suffix#")" - #!if(MajOp{2}, ":<<1", "") - #!if(isRnd, ":rnd", "") - #!if(isSat, ":sat", "") - #!if(isRaw, !if(isHi, ":raw:hi", ":raw:lo"), ""), [] > { - bits<5> dst; - bits<5> src1; - bits<5> src2; - - let IClass = 0b1110; - - let Inst{27-24} = RegTyBits; - let Inst{23-21} = MajOp; - let Inst{20-16} = src1; - let Inst{13} = 0b0; - let Inst{12-8} = src2; - let Inst{7-5} = MinOp; - let Inst{4-0} = dst; - } - -class T_MType_vrcmpy <string mnemonic, bits<3> MajOp, bits<3> MinOp, bit isHi> - : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, 1, 1, "", 1, isHi>; - -class T_MType_dd <string mnemonic, bits<3> MajOp, bits<3> MinOp, - bit isSat = 0, bit isRnd = 0 > - : T_MType_mpy <mnemonic, 0b1001, DoubleRegs, MajOp, MinOp, isSat, isRnd>; - -class T_MType_rr1 <string mnemonic, bits<3> MajOp, bits<3> MinOp, - bit isSat = 0, bit isRnd = 0 > - : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd>; - -class T_MType_rr2 <string mnemonic, bits<3> MajOp, bits<3> MinOp, - bit isSat = 0, bit isRnd = 0, string op2str = "" > - : T_MType_mpy<mnemonic, 0b1101, IntRegs, MajOp, MinOp, isSat, isRnd, op2str>; - -def M2_vradduh : T_MType_dd <"vradduh", 0b000, 0b001, 0, 0>; -def M2_vdmpyrs_s0 : T_MType_dd <"vdmpy", 0b000, 0b000, 1, 1>; -def M2_vdmpyrs_s1 : T_MType_dd <"vdmpy", 0b100, 0b000, 1, 1>; - -let CextOpcode = "mpyi", InputType = "reg" in -def M2_mpyi : T_MType_rr1 <"mpyi", 0b000, 0b000>, ImmRegRel; - -def M2_mpy_up : T_MType_rr1 <"mpy", 0b000, 0b001>; -def M2_mpyu_up : T_MType_rr1 <"mpyu", 0b010, 0b001>; - -def M2_dpmpyss_rnd_s0 : T_MType_rr1 <"mpy", 0b001, 0b001, 0, 1>; - -def M2_vmpy2s_s0pack : T_MType_rr1 <"vmpyh", 0b001, 0b111, 1, 1>; -def M2_vmpy2s_s1pack : T_MType_rr1 <"vmpyh", 0b101, 0b111, 1, 1>; - -def M2_hmmpyh_rs1 : T_MType_rr2 <"mpy", 0b101, 0b100, 1, 1, ".h">; -def M2_hmmpyl_rs1 : T_MType_rr2 <"mpy", 0b111, 0b100, 1, 1, ".l">; - -def M2_cmpyrs_s0 : T_MType_rr2 <"cmpy", 0b001, 0b110, 1, 1>; -def M2_cmpyrs_s1 : T_MType_rr2 <"cmpy", 0b101, 0b110, 1, 1>; -def M2_cmpyrsc_s0 : T_MType_rr2 <"cmpy", 0b011, 0b110, 1, 1, "*">; -def M2_cmpyrsc_s1 : T_MType_rr2 <"cmpy", 0b111, 0b110, 1, 1, "*">; - -// V4 Instructions -def M2_vraddh : T_MType_dd <"vraddh", 0b001, 0b111, 0>; -def M2_mpysu_up : T_MType_rr1 <"mpysu", 0b011, 0b001, 0>; -def M2_mpy_up_s1 : T_MType_rr1 <"mpy", 0b101, 0b010, 0>; -def M2_mpy_up_s1_sat : T_MType_rr1 <"mpy", 0b111, 0b000, 1>; - -def M2_hmmpyh_s1 : T_MType_rr2 <"mpy", 0b101, 0b000, 1, 0, ".h">; -def M2_hmmpyl_s1 : T_MType_rr2 <"mpy", 0b101, 0b001, 1, 0, ".l">; - -let hasNewValue = 1, opNewValue = 0 in -class T_MType_mpy_ri <bit isNeg, Operand ImmOp, list<dag> pattern> - : MInst < (outs IntRegs:$Rd), (ins IntRegs:$Rs, ImmOp:$u8), - "$Rd ="#!if(isNeg, "- ", "+ ")#"mpyi($Rs, #$u8)" , - pattern, "", M_tc_3x_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<8> u8; - - let IClass = 0b1110; - - let Inst{27-24} = 0b0000; - let Inst{23} = isNeg; - let Inst{13} = 0b0; - let Inst{4-0} = Rd; - let Inst{20-16} = Rs; - let Inst{12-5} = u8; - } - -let isExtendable = 1, opExtentBits = 8, opExtendable = 2 in -def M2_mpysip : T_MType_mpy_ri <0, u8_0Ext, []>; - -def M2_mpysin : T_MType_mpy_ri <1, u8_0Imm, []>; - -// Assember mapped to M2_mpyi -let isAsmParserOnly = 1 in -def M2_mpyui : MInst<(outs IntRegs:$dst), - (ins IntRegs:$src1, IntRegs:$src2), - "$dst = mpyui($src1, $src2)">; - -// Rd=mpyi(Rs,#m9) -// s9 is NOT the same as m9 - but it works.. so far. -// Assembler maps to either Rd=+mpyi(Rs,#u8) or Rd=-mpyi(Rs,#u8) -// depending on the value of m9. See Arch Spec. -let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9, - CextOpcode = "mpyi", InputType = "imm", hasNewValue = 1, - isAsmParserOnly = 1 in -def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9_0Ext:$src2), - "$dst = mpyi($src1, #$src2)", []>, ImmRegRel; - -let hasNewValue = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 3, - InputType = "imm" in -class T_MType_acc_ri <string mnemonic, bits<3> MajOp, Operand ImmOp, - list<dag> pattern = []> - : MInst < (outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, ImmOp:$src3), - "$dst "#mnemonic#"($src2, #$src3)", - pattern, "$src1 = $dst", M_tc_2_SLOT23> { - bits<5> dst; - bits<5> src2; - bits<8> src3; - - let IClass = 0b1110; - - let Inst{27-26} = 0b00; - let Inst{25-23} = MajOp; - let Inst{20-16} = src2; - let Inst{13} = 0b0; - let Inst{12-5} = src3; - let Inst{4-0} = dst; - } - -let InputType = "reg", hasNewValue = 1 in -class T_MType_acc_rr <string mnemonic, bits<3> MajOp, bits<3> MinOp, - bit isSwap = 0, list<dag> pattern = [], bit hasNot = 0, - bit isSat = 0, bit isShift = 0> - : MInst < (outs IntRegs:$dst), - (ins IntRegs:$src1, IntRegs:$src2, IntRegs:$src3), - "$dst "#mnemonic#"($src2, "#!if(hasNot, "~$src3)","$src3)") - #!if(isShift, ":<<1", "") - #!if(isSat, ":sat", ""), - pattern, "$src1 = $dst", M_tc_2_SLOT23 > { - bits<5> dst; - bits<5> src2; - bits<5> src3; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1111; - let Inst{23-21} = MajOp; - let Inst{20-16} = !if(isSwap, src3, src2); - let Inst{13} = 0b0; - let Inst{12-8} = !if(isSwap, src2, src3); - let Inst{7-5} = MinOp; - let Inst{4-0} = dst; - } - -let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23 in { - def M2_macsip : T_MType_acc_ri <"+= mpyi", 0b010, u8_0Ext, []>, ImmRegRel; - - def M2_maci : T_MType_acc_rr <"+= mpyi", 0b000, 0b000, 0, []>, ImmRegRel; -} - -let CextOpcode = "ADD_acc" in { - let isExtentSigned = 1 in - def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8_0Ext, []>, ImmRegRel; - - def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0, []>, ImmRegRel; -} - -let CextOpcode = "SUB_acc" in { - let isExtentSigned = 1 in - def M2_naccii : T_MType_acc_ri <"-= add", 0b101, s8_0Ext>, ImmRegRel; - - def M2_nacci : T_MType_acc_rr <"-= add", 0b100, 0b001, 0>, ImmRegRel; -} - -let Itinerary = M_tc_3x_SLOT23 in -def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8_0Ext>; - -def M2_xor_xacc : T_MType_acc_rr < "^= xor", 0b100, 0b011, 0>; -def M2_subacc : T_MType_acc_rr <"+= sub", 0b000, 0b011, 1>; - -//===----------------------------------------------------------------------===// -// Template Class -- XType Vector Instructions -//===----------------------------------------------------------------------===// -class T_XTYPE_Vect < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj > - : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Rdd = "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"), - [] > { - bits<5> Rdd; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1000; - let Inst{23-21} = MajOp; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rdd; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - } - -class T_XTYPE_Vect_acc < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj > - : MInst <(outs DoubleRegs:$Rdd), - (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Rdd += "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"), - [], "$dst2 = $Rdd",M_tc_3x_SLOT23 > { - bits<5> Rdd; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1010; - let Inst{23-21} = MajOp; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rdd; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - } - -class T_XTYPE_Vect_diff < bits<3> MajOp, string opc > - : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rtt, DoubleRegs:$Rss), - "$Rdd = "#opc#"($Rtt, $Rss)", - [], "",M_tc_2_SLOT23 > { - bits<5> Rdd; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1000; - let Inst{23-21} = MajOp; - let Inst{7-5} = 0b000; - let Inst{4-0} = Rdd; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - } - -// Vector reduce add unsigned bytes: Rdd32=vrmpybu(Rss32,Rtt32) -def A2_vraddub: T_XTYPE_Vect <"vraddub", 0b010, 0b001, 0>; -def A2_vraddub_acc: T_XTYPE_Vect_acc <"vraddub", 0b010, 0b001, 0>; - -// Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt) -def A2_vrsadub: T_XTYPE_Vect <"vrsadub", 0b010, 0b010, 0>; -def A2_vrsadub_acc: T_XTYPE_Vect_acc <"vrsadub", 0b010, 0b010, 0>; - -// Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss) -def M2_vabsdiffh: T_XTYPE_Vect_diff<0b011, "vabsdiffh">; - -// Vector absolute difference words: Rdd=vabsdiffw(Rtt,Rss) -def M2_vabsdiffw: T_XTYPE_Vect_diff<0b001, "vabsdiffw">; - -// Vector reduce complex multiply real or imaginary: -// Rdd[+]=vrcmpy[ir](Rss,Rtt[*]) -def M2_vrcmpyi_s0: T_XTYPE_Vect <"vrcmpyi", 0b000, 0b000, 0>; -def M2_vrcmpyi_s0c: T_XTYPE_Vect <"vrcmpyi", 0b010, 0b000, 1>; -def M2_vrcmaci_s0: T_XTYPE_Vect_acc <"vrcmpyi", 0b000, 0b000, 0>; -def M2_vrcmaci_s0c: T_XTYPE_Vect_acc <"vrcmpyi", 0b010, 0b000, 1>; - -def M2_vrcmpyr_s0: T_XTYPE_Vect <"vrcmpyr", 0b000, 0b001, 0>; -def M2_vrcmpyr_s0c: T_XTYPE_Vect <"vrcmpyr", 0b011, 0b001, 1>; -def M2_vrcmacr_s0: T_XTYPE_Vect_acc <"vrcmpyr", 0b000, 0b001, 0>; -def M2_vrcmacr_s0c: T_XTYPE_Vect_acc <"vrcmpyr", 0b011, 0b001, 1>; - -// Vector reduce halfwords: -// Rdd[+]=vrmpyh(Rss,Rtt) -def M2_vrmpy_s0: T_XTYPE_Vect <"vrmpyh", 0b000, 0b010, 0>; -def M2_vrmac_s0: T_XTYPE_Vect_acc <"vrmpyh", 0b000, 0b010, 0>; - -//===----------------------------------------------------------------------===// -// Template Class -- Vector Multipy with accumulation. -// Used for complex multiply real or imaginary, dual multiply and even halfwords -//===----------------------------------------------------------------------===// -let Defs = [USR_OVF] in -class T_M2_vmpy_acc_sat < string opc, bits<3> MajOp, bits<3> MinOp, - bit hasShift, bit isRnd > - : MInst <(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","") - #!if(isRnd,":rnd","")#":sat", - [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > { - bits<5> Rxx; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1010; - let Inst{23-21} = MajOp; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rxx; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - } - -class T_M2_vmpy_acc < string opc, bits<3> MajOp, bits<3> MinOp, - bit hasShift, bit isRnd > - : MInst <(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","") - #!if(isRnd,":rnd",""), - [], "$dst2 = $Rxx",M_tc_3x_SLOT23 > { - bits<5> Rxx; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1010; - let Inst{23-21} = MajOp; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rxx; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - } - -// Vector multiply word by signed half with accumulation -// Rxx+=vmpyw[eo]h(Rss,Rtt)[:<<1][:rnd]:sat -def M2_mmacls_s1: T_M2_vmpy_acc_sat <"vmpyweh", 0b100, 0b101, 1, 0>; -def M2_mmacls_s0: T_M2_vmpy_acc_sat <"vmpyweh", 0b000, 0b101, 0, 0>; -def M2_mmacls_rs1: T_M2_vmpy_acc_sat <"vmpyweh", 0b101, 0b101, 1, 1>; -def M2_mmacls_rs0: T_M2_vmpy_acc_sat <"vmpyweh", 0b001, 0b101, 0, 1>; - -def M2_mmachs_s1: T_M2_vmpy_acc_sat <"vmpywoh", 0b100, 0b111, 1, 0>; -def M2_mmachs_s0: T_M2_vmpy_acc_sat <"vmpywoh", 0b000, 0b111, 0, 0>; -def M2_mmachs_rs1: T_M2_vmpy_acc_sat <"vmpywoh", 0b101, 0b111, 1, 1>; -def M2_mmachs_rs0: T_M2_vmpy_acc_sat <"vmpywoh", 0b001, 0b111, 0, 1>; - -// Vector multiply word by unsigned half with accumulation -// Rxx+=vmpyw[eo]uh(Rss,Rtt)[:<<1][:rnd]:sat -def M2_mmaculs_s1: T_M2_vmpy_acc_sat <"vmpyweuh", 0b110, 0b101, 1, 0>; -def M2_mmaculs_s0: T_M2_vmpy_acc_sat <"vmpyweuh", 0b010, 0b101, 0, 0>; -def M2_mmaculs_rs1: T_M2_vmpy_acc_sat <"vmpyweuh", 0b111, 0b101, 1, 1>; -def M2_mmaculs_rs0: T_M2_vmpy_acc_sat <"vmpyweuh", 0b011, 0b101, 0, 1>; - -def M2_mmacuhs_s1: T_M2_vmpy_acc_sat <"vmpywouh", 0b110, 0b111, 1, 0>; -def M2_mmacuhs_s0: T_M2_vmpy_acc_sat <"vmpywouh", 0b010, 0b111, 0, 0>; -def M2_mmacuhs_rs1: T_M2_vmpy_acc_sat <"vmpywouh", 0b111, 0b111, 1, 1>; -def M2_mmacuhs_rs0: T_M2_vmpy_acc_sat <"vmpywouh", 0b011, 0b111, 0, 1>; - -// Vector multiply even halfwords with accumulation -// Rxx+=vmpyeh(Rss,Rtt)[:<<1][:sat] -def M2_vmac2es: T_M2_vmpy_acc <"vmpyeh", 0b001, 0b010, 0, 0>; -def M2_vmac2es_s1: T_M2_vmpy_acc_sat <"vmpyeh", 0b100, 0b110, 1, 0>; -def M2_vmac2es_s0: T_M2_vmpy_acc_sat <"vmpyeh", 0b000, 0b110, 0, 0>; - -// Vector dual multiply with accumulation -// Rxx+=vdmpy(Rss,Rtt)[:sat] -def M2_vdmacs_s1: T_M2_vmpy_acc_sat <"vdmpy", 0b100, 0b100, 1, 0>; -def M2_vdmacs_s0: T_M2_vmpy_acc_sat <"vdmpy", 0b000, 0b100, 0, 0>; - -// Vector complex multiply real or imaginary with accumulation -// Rxx+=vcmpy[ir](Rss,Rtt):sat -def M2_vcmac_s0_sat_r: T_M2_vmpy_acc_sat <"vcmpyr", 0b001, 0b100, 0, 0>; -def M2_vcmac_s0_sat_i: T_M2_vmpy_acc_sat <"vcmpyi", 0b010, 0b100, 0, 0>; - -//===----------------------------------------------------------------------===// -// Template Class -- Multiply signed/unsigned halfwords with and without -// saturation and rounding -//===----------------------------------------------------------------------===// -class T_M2_mpyd < bits<2> LHbits, bit isRnd, bit hasShift, bit isUnsigned > - : MInst < (outs DoubleRegs:$Rdd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rdd = "#!if(isUnsigned,"mpyu","mpy")#"($Rs."#!if(LHbits{1},"h","l") - #", $Rt."#!if(LHbits{0},"h)","l)") - #!if(hasShift,":<<1","") - #!if(isRnd,":rnd",""), - [] > { - bits<5> Rdd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b0100; - let Inst{23} = hasShift; - let Inst{22} = isUnsigned; - let Inst{21} = isRnd; - let Inst{6-5} = LHbits; - let Inst{4-0} = Rdd; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; -} - -def M2_mpyd_hh_s0: T_M2_mpyd<0b11, 0, 0, 0>; -def M2_mpyd_hl_s0: T_M2_mpyd<0b10, 0, 0, 0>; -def M2_mpyd_lh_s0: T_M2_mpyd<0b01, 0, 0, 0>; -def M2_mpyd_ll_s0: T_M2_mpyd<0b00, 0, 0, 0>; - -def M2_mpyd_hh_s1: T_M2_mpyd<0b11, 0, 1, 0>; -def M2_mpyd_hl_s1: T_M2_mpyd<0b10, 0, 1, 0>; -def M2_mpyd_lh_s1: T_M2_mpyd<0b01, 0, 1, 0>; -def M2_mpyd_ll_s1: T_M2_mpyd<0b00, 0, 1, 0>; - -def M2_mpyd_rnd_hh_s0: T_M2_mpyd<0b11, 1, 0, 0>; -def M2_mpyd_rnd_hl_s0: T_M2_mpyd<0b10, 1, 0, 0>; -def M2_mpyd_rnd_lh_s0: T_M2_mpyd<0b01, 1, 0, 0>; -def M2_mpyd_rnd_ll_s0: T_M2_mpyd<0b00, 1, 0, 0>; - -def M2_mpyd_rnd_hh_s1: T_M2_mpyd<0b11, 1, 1, 0>; -def M2_mpyd_rnd_hl_s1: T_M2_mpyd<0b10, 1, 1, 0>; -def M2_mpyd_rnd_lh_s1: T_M2_mpyd<0b01, 1, 1, 0>; -def M2_mpyd_rnd_ll_s1: T_M2_mpyd<0b00, 1, 1, 0>; - -//Rdd=mpyu(Rs.[HL],Rt.[HL])[:<<1] -def M2_mpyud_hh_s0: T_M2_mpyd<0b11, 0, 0, 1>; -def M2_mpyud_hl_s0: T_M2_mpyd<0b10, 0, 0, 1>; -def M2_mpyud_lh_s0: T_M2_mpyd<0b01, 0, 0, 1>; -def M2_mpyud_ll_s0: T_M2_mpyd<0b00, 0, 0, 1>; - -def M2_mpyud_hh_s1: T_M2_mpyd<0b11, 0, 1, 1>; -def M2_mpyud_hl_s1: T_M2_mpyd<0b10, 0, 1, 1>; -def M2_mpyud_lh_s1: T_M2_mpyd<0b01, 0, 1, 1>; -def M2_mpyud_ll_s1: T_M2_mpyd<0b00, 0, 1, 1>; - -//===----------------------------------------------------------------------===// -// Template Class for xtype mpy: -// Vector multiply -// Complex multiply -// multiply 32X32 and use full result -//===----------------------------------------------------------------------===// -let hasSideEffects = 0 in -class T_XTYPE_mpy64 <string mnemonic, bits<3> MajOp, bits<3> MinOp, - bit isSat, bit hasShift, bit isConj> - : MInst <(outs DoubleRegs:$Rdd), - (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rdd = "#mnemonic#"($Rs, $Rt"#!if(isConj,"*)",")") - #!if(hasShift,":<<1","") - #!if(isSat,":sat",""), - [] > { - bits<5> Rdd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b0101; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rdd; - } - -//===----------------------------------------------------------------------===// -// Template Class for xtype mpy with accumulation into 64-bit: -// Vector multiply -// Complex multiply -// multiply 32X32 and use full result -//===----------------------------------------------------------------------===// -class T_XTYPE_mpy64_acc <string op1, string op2, bits<3> MajOp, bits<3> MinOp, - bit isSat, bit hasShift, bit isConj> - : MInst <(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt), - "$Rxx "#op2#"= "#op1#"($Rs, $Rt"#!if(isConj,"*)",")") - #!if(hasShift,":<<1","") - #!if(isSat,":sat",""), - - [] , "$dst2 = $Rxx" > { - bits<5> Rxx; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b0111; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rxx; - } - -// MPY - Multiply and use full result -// Rdd = mpy[u](Rs,Rt) -def M2_dpmpyss_s0 : T_XTYPE_mpy64 < "mpy", 0b000, 0b000, 0, 0, 0>; -def M2_dpmpyuu_s0 : T_XTYPE_mpy64 < "mpyu", 0b010, 0b000, 0, 0, 0>; - -// Rxx[+-]= mpy[u](Rs,Rt) -def M2_dpmpyss_acc_s0 : T_XTYPE_mpy64_acc < "mpy", "+", 0b000, 0b000, 0, 0, 0>; -def M2_dpmpyss_nac_s0 : T_XTYPE_mpy64_acc < "mpy", "-", 0b001, 0b000, 0, 0, 0>; -def M2_dpmpyuu_acc_s0 : T_XTYPE_mpy64_acc < "mpyu", "+", 0b010, 0b000, 0, 0, 0>; -def M2_dpmpyuu_nac_s0 : T_XTYPE_mpy64_acc < "mpyu", "-", 0b011, 0b000, 0, 0, 0>; - -// Complex multiply real or imaginary -// Rxx=cmpy[ir](Rs,Rt) -def M2_cmpyi_s0 : T_XTYPE_mpy64 < "cmpyi", 0b000, 0b001, 0, 0, 0>; -def M2_cmpyr_s0 : T_XTYPE_mpy64 < "cmpyr", 0b000, 0b010, 0, 0, 0>; - -// Rxx+=cmpy[ir](Rs,Rt) -def M2_cmaci_s0 : T_XTYPE_mpy64_acc < "cmpyi", "+", 0b000, 0b001, 0, 0, 0>; -def M2_cmacr_s0 : T_XTYPE_mpy64_acc < "cmpyr", "+", 0b000, 0b010, 0, 0, 0>; - -// Complex multiply -// Rdd=cmpy(Rs,Rt)[:<<]:sat -def M2_cmpys_s0 : T_XTYPE_mpy64 < "cmpy", 0b000, 0b110, 1, 0, 0>; -def M2_cmpys_s1 : T_XTYPE_mpy64 < "cmpy", 0b100, 0b110, 1, 1, 0>; - -// Rdd=cmpy(Rs,Rt*)[:<<]:sat -def M2_cmpysc_s0 : T_XTYPE_mpy64 < "cmpy", 0b010, 0b110, 1, 0, 1>; -def M2_cmpysc_s1 : T_XTYPE_mpy64 < "cmpy", 0b110, 0b110, 1, 1, 1>; - -// Rxx[-+]=cmpy(Rs,Rt)[:<<1]:sat -def M2_cmacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b000, 0b110, 1, 0, 0>; -def M2_cnacs_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b000, 0b111, 1, 0, 0>; -def M2_cmacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b100, 0b110, 1, 1, 0>; -def M2_cnacs_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b100, 0b111, 1, 1, 0>; - -// Rxx[-+]=cmpy(Rs,Rt*)[:<<1]:sat -def M2_cmacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b010, 0b110, 1, 0, 1>; -def M2_cnacsc_s0 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b010, 0b111, 1, 0, 1>; -def M2_cmacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "+", 0b110, 0b110, 1, 1, 1>; -def M2_cnacsc_s1 : T_XTYPE_mpy64_acc < "cmpy", "-", 0b110, 0b111, 1, 1, 1>; - -// Vector multiply halfwords -// Rdd=vmpyh(Rs,Rt)[:<<]:sat -//let Defs = [USR_OVF] in { - def M2_vmpy2s_s1 : T_XTYPE_mpy64 < "vmpyh", 0b100, 0b101, 1, 1, 0>; - def M2_vmpy2s_s0 : T_XTYPE_mpy64 < "vmpyh", 0b000, 0b101, 1, 0, 0>; -//} - -// Rxx+=vmpyh(Rs,Rt)[:<<1][:sat] -def M2_vmac2 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b001, 0b001, 0, 0, 0>; -def M2_vmac2s_s1 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b100, 0b101, 1, 1, 0>; -def M2_vmac2s_s0 : T_XTYPE_mpy64_acc < "vmpyh", "+", 0b000, 0b101, 1, 0, 0>; - -//===----------------------------------------------------------------------===// -// MTYPE/MPYH - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// MTYPE/MPYS + -//===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// MTYPE/MPYS - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// MTYPE/VB + -//===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// MTYPE/VB - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// MTYPE/VH + -//===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// MTYPE/VH - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// ST + -//===----------------------------------------------------------------------===// -/// -// Store doubleword. -//===----------------------------------------------------------------------===// -// Template class for non-predicated post increment stores with immediate offset -//===----------------------------------------------------------------------===// -let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc in -class T_store_pi <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<4> MajOp, bit isHalf > - : STInst <(outs IntRegs:$_dst_), - (ins IntRegs:$src1, ImmOp:$offset, RC:$src2), - mnemonic#"($src1++#$offset) = $src2"#!if(isHalf, ".h", ""), - [], "$src1 = $_dst_" >, - AddrModeRel { - bits<5> src1; - bits<5> src2; - bits<7> offset; - bits<4> offsetBits; - - string ImmOpStr = !cast<string>(ImmOp); - let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, - !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, - !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, - /* s4_0Imm */ offset{3-0}))); - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, !if(isHalf,0,1)); - - let IClass = 0b1010; - - let Inst{27-25} = 0b101; - let Inst{24-21} = MajOp; - let Inst{20-16} = src1; - let Inst{13} = 0b0; - let Inst{12-8} = src2; - let Inst{7} = 0b0; - let Inst{6-3} = offsetBits; - let Inst{1} = 0b0; - } - -//===----------------------------------------------------------------------===// -// Template class for predicated post increment stores with immediate offset -//===----------------------------------------------------------------------===// -let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in -class T_pstore_pi <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<4> MajOp, bit isHalf, bit isPredNot, bit isPredNew> - : STInst <(outs IntRegs:$_dst_), - (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3), - !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($src2++#$offset) = $src3"#!if(isHalf, ".h", ""), - [], "$src2 = $_dst_" >, - AddrModeRel { - bits<2> src1; - bits<5> src2; - bits<7> offset; - bits<5> src3; - bits<4> offsetBits; - - string ImmOpStr = !cast<string>(ImmOp); - let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3}, - !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, - !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, - /* s4_0Imm */ offset{3-0}))); - - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, !if(isHalf,0,1)); - let isPredicatedNew = isPredNew; - let isPredicatedFalse = isPredNot; - - let IClass = 0b1010; - - let Inst{27-25} = 0b101; - let Inst{24-21} = MajOp; - let Inst{20-16} = src2; - let Inst{13} = 0b1; - let Inst{12-8} = src3; - let Inst{7} = isPredNew; - let Inst{6-3} = offsetBits; - let Inst{2} = isPredNot; - let Inst{1-0} = src1; - } - -multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC, - Operand ImmOp, bits<4> MajOp, bit isHalf = 0 > { - - let BaseOpcode = "POST_"#BaseOp in { - def S2_#NAME#_pi : T_store_pi <mnemonic, RC, ImmOp, MajOp, isHalf>; - - // Predicated - def S2_p#NAME#t_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 0, 0>; - def S2_p#NAME#f_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 1, 0>; - - // Predicated new - def S2_p#NAME#tnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, - isHalf, 0, 1>; - def S2_p#NAME#fnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, - isHalf, 1, 1>; - } -} - -let accessSize = ByteAccess in -defm storerb: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm, 0b1000>; - -let accessSize = HalfWordAccess in -defm storerh: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm, 0b1010>; - -let accessSize = WordAccess in -defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>; - -let accessSize = DoubleWordAccess in -defm storerd: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm, 0b1110>; - -let accessSize = HalfWordAccess, isNVStorable = 0 in -defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>; - -//===----------------------------------------------------------------------===// -// Template class for post increment stores with register offset. -//===----------------------------------------------------------------------===// -class T_store_pr <string mnemonic, RegisterClass RC, bits<3> MajOp, - MemAccessSize AccessSz, bit isHalf = 0> - : STInst <(outs IntRegs:$_dst_), - (ins IntRegs:$src1, ModRegs:$src2, RC:$src3), - mnemonic#"($src1++$src2) = $src3"#!if(isHalf, ".h", ""), - [], "$src1 = $_dst_" > { - bits<5> src1; - bits<1> src2; - bits<5> src3; - let accessSize = AccessSz; - - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if(!eq(mnemonic,"memd"), 0, !if(isHalf,0,1)); - - let IClass = 0b1010; - - let Inst{27-24} = 0b1101; - let Inst{23-21} = MajOp; - let Inst{20-16} = src1; - let Inst{13} = src2; - let Inst{12-8} = src3; - let Inst{7} = 0b0; - } - -def S2_storerb_pr : T_store_pr<"memb", IntRegs, 0b000, ByteAccess>; -def S2_storerh_pr : T_store_pr<"memh", IntRegs, 0b010, HalfWordAccess>; -def S2_storeri_pr : T_store_pr<"memw", IntRegs, 0b100, WordAccess>; -def S2_storerd_pr : T_store_pr<"memd", DoubleRegs, 0b110, DoubleWordAccess>; -def S2_storerf_pr : T_store_pr<"memh", IntRegs, 0b011, HalfWordAccess, 1>; - -let opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in -class T_store_io <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<3> MajOp, bit isH = 0> - : STInst <(outs), - (ins IntRegs:$src1, ImmOp:$src2, RC:$src3), - mnemonic#"($src1+#$src2) = $src3"#!if(isH,".h","")>, - AddrModeRel, ImmRegRel { - bits<5> src1; - bits<14> src2; // Actual address offset - bits<5> src3; - bits<11> offsetBits; // Represents offset encoding - - string ImmOpStr = !cast<string>(ImmOp); - - let opExtentBits = !if (!eq(ImmOpStr, "s11_3Ext"), 14, - !if (!eq(ImmOpStr, "s11_2Ext"), 13, - !if (!eq(ImmOpStr, "s11_1Ext"), 12, - /* s11_0Ext */ 11))); - let offsetBits = !if (!eq(ImmOpStr, "s11_3Ext"), src2{13-3}, - !if (!eq(ImmOpStr, "s11_2Ext"), src2{12-2}, - !if (!eq(ImmOpStr, "s11_1Ext"), src2{11-1}, - /* s11_0Ext */ src2{10-0}))); - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1)); - let IClass = 0b1010; - - let Inst{27} = 0b0; - let Inst{26-25} = offsetBits{10-9}; - let Inst{24} = 0b1; - let Inst{23-21} = MajOp; - let Inst{20-16} = src1; - let Inst{13} = offsetBits{8}; - let Inst{12-8} = src3; - let Inst{7-0} = offsetBits{7-0}; - } - -let opExtendable = 2, isPredicated = 1 in -class T_pstore_io <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<3>MajOp, bit PredNot, bit isPredNew, bit isH = 0> - : STInst <(outs), - (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4), - !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($src2+#$src3) = $src4"#!if(isH,".h",""), - [],"",V2LDST_tc_st_SLOT01 >, - AddrModeRel, ImmRegRel { - bits<2> src1; - bits<5> src2; - bits<9> src3; // Actual address offset - bits<5> src4; - bits<6> offsetBits; // Represents offset encoding - - let isPredicatedNew = isPredNew; - let isPredicatedFalse = PredNot; - - string ImmOpStr = !cast<string>(ImmOp); - let opExtentBits = !if (!eq(ImmOpStr, "u6_3Ext"), 9, - !if (!eq(ImmOpStr, "u6_2Ext"), 8, - !if (!eq(ImmOpStr, "u6_1Ext"), 7, - /* u6_0Ext */ 6))); - let offsetBits = !if (!eq(ImmOpStr, "u6_3Ext"), src3{8-3}, - !if (!eq(ImmOpStr, "u6_2Ext"), src3{7-2}, - !if (!eq(ImmOpStr, "u6_1Ext"), src3{6-1}, - /* u6_0Ext */ src3{5-0}))); - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1)); - - let IClass = 0b0100; - - let Inst{27} = 0b0; - let Inst{26} = PredNot; - let Inst{25} = isPredNew; - let Inst{24} = 0b0; - let Inst{23-21} = MajOp; - let Inst{20-16} = src2; - let Inst{13} = offsetBits{5}; - let Inst{12-8} = src4; - let Inst{7-3} = offsetBits{4-0}; - let Inst{1-0} = src1; - } - -let isExtendable = 1, hasSideEffects = 0 in -multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC, - Operand ImmOp, Operand predImmOp, bits<3> MajOp, bit isH = 0> { - let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in { - def S2_#NAME#_io : T_store_io <mnemonic, RC, ImmOp, MajOp, isH>; - - // Predicated - def S2_p#NAME#t_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 0, 0, isH>; - def S2_p#NAME#f_io : T_pstore_io<mnemonic, RC, predImmOp, MajOp, 1, 0, isH>; - - // Predicated new - def S4_p#NAME#tnew_io : T_pstore_io <mnemonic, RC, predImmOp, - MajOp, 0, 1, isH>; - def S4_p#NAME#fnew_io : T_pstore_io <mnemonic, RC, predImmOp, - MajOp, 1, 1, isH>; - } -} - -let addrMode = BaseImmOffset, InputType = "imm" in { - let accessSize = ByteAccess in - defm storerb: ST_Idxd < "memb", "STrib", IntRegs, s11_0Ext, u6_0Ext, 0b000>; - - let accessSize = HalfWordAccess, opExtentAlign = 1 in - defm storerh: ST_Idxd < "memh", "STrih", IntRegs, s11_1Ext, u6_1Ext, 0b010>; - - let accessSize = WordAccess, opExtentAlign = 2 in - defm storeri: ST_Idxd < "memw", "STriw", IntRegs, s11_2Ext, u6_2Ext, 0b100>; - - let accessSize = DoubleWordAccess, isNVStorable = 0, opExtentAlign = 3 in - defm storerd: ST_Idxd < "memd", "STrid", DoubleRegs, s11_3Ext, - u6_3Ext, 0b110>; - - let accessSize = HalfWordAccess, opExtentAlign = 1 in - defm storerf: ST_Idxd < "memh", "STrif", IntRegs, s11_1Ext, - u6_1Ext, 0b011, 1>; -} - -// Store predicate. -let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13, - isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in -def STriw_pred : STInst<(outs), - (ins IntRegs:$addr, s11_2Ext:$off, PredRegs:$src1), - ".error \"should not emit\"", []>; -// Store modifier. -let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13, - isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in -def STriw_mod : STInst<(outs), - (ins IntRegs:$addr, s11_2Ext:$off, ModRegs:$src1), - ".error \"should not emit\"", []>; - -// S2_allocframe: Allocate stack frame. -let Defs = [R29, R30], Uses = [R29, R31, R30], - hasSideEffects = 0, accessSize = DoubleWordAccess in -def S2_allocframe: ST0Inst < - (outs), (ins u11_3Imm:$u11_3), - "allocframe(#$u11_3)" > { - bits<14> u11_3; - - let IClass = 0b1010; - let Inst{27-16} = 0b000010011101; - let Inst{13-11} = 0b000; - let Inst{10-0} = u11_3{13-3}; - } - -// S2_storer[bhwdf]_pci: Store byte/half/word/double. -// S2_storer[bhwdf]_pci -> S2_storerbnew_pci -let Uses = [CS], addrMode = PostInc in -class T_store_pci <string mnemonic, RegisterClass RC, - Operand Imm, bits<4>MajOp, - MemAccessSize AlignSize, string RegSrc = "Rt"> - : STInst <(outs IntRegs:$_dst_), - (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, RC:$Rt), - #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $"#RegSrc#"", - [] , - "$Rz = $_dst_" > { - bits<5> Rz; - bits<7> offset; - bits<1> Mu; - bits<5> Rt; - let accessSize = AlignSize; - let isNVStorable = !if(!eq(mnemonic,"memd"), 0, - !if(!eq(RegSrc,"Rt.h"), 0, 1)); - - let IClass = 0b1010; - let Inst{27-25} = 0b100; - let Inst{24-21} = MajOp; - let Inst{20-16} = Rz; - let Inst{13} = Mu; - let Inst{12-8} = Rt; - let Inst{7} = 0b0; - let Inst{6-3} = - !if (!eq(!cast<string>(AlignSize), "DoubleWordAccess"), offset{6-3}, - !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2}, - !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1}, - /* ByteAccess */ offset{3-0}))); - let Inst{1} = 0b0; - } - -def S2_storerb_pci : T_store_pci<"memb", IntRegs, s4_0Imm, 0b1000, - ByteAccess>; -def S2_storerh_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1010, - HalfWordAccess>; -def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011, - HalfWordAccess, "Rt.h">; -def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100, - WordAccess>; -def S2_storerd_pci : T_store_pci<"memd", DoubleRegs, s4_3Imm, 0b1110, - DoubleWordAccess>; - -let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 4, - addrMode = PostInc in -class T_storenew_pci <string mnemonic, Operand Imm, - bits<2>MajOp, MemAccessSize AlignSize> - : NVInst < (outs IntRegs:$_dst_), - (ins IntRegs:$Rz, Imm:$offset, ModRegs:$Mu, IntRegs:$Nt), - #mnemonic#"($Rz ++ #$offset:circ($Mu)) = $Nt.new", - [], - "$Rz = $_dst_"> { - bits<5> Rz; - bits<6> offset; - bits<1> Mu; - bits<3> Nt; - - let accessSize = AlignSize; - - let IClass = 0b1010; - let Inst{27-21} = 0b1001101; - let Inst{20-16} = Rz; - let Inst{13} = Mu; - let Inst{12-11} = MajOp; - let Inst{10-8} = Nt; - let Inst{7} = 0b0; - let Inst{6-3} = - !if (!eq(!cast<string>(AlignSize), "WordAccess"), offset{5-2}, - !if (!eq(!cast<string>(AlignSize), "HalfWordAccess"), offset{4-1}, - /* ByteAccess */ offset{3-0})); - let Inst{1} = 0b0; - } - -def S2_storerbnew_pci : T_storenew_pci <"memb", s4_0Imm, 0b00, ByteAccess>; -def S2_storerhnew_pci : T_storenew_pci <"memh", s4_1Imm, 0b01, HalfWordAccess>; -def S2_storerinew_pci : T_storenew_pci <"memw", s4_2Imm, 0b10, WordAccess>; - -//===----------------------------------------------------------------------===// -// Circular stores with auto-increment register -//===----------------------------------------------------------------------===// -let Uses = [CS], addrMode = PostInc in -class T_store_pcr <string mnemonic, RegisterClass RC, bits<4>MajOp, - MemAccessSize AlignSize, string RegSrc = "Rt"> - : STInst <(outs IntRegs:$_dst_), - (ins IntRegs:$Rz, ModRegs:$Mu, RC:$Rt), - #mnemonic#"($Rz ++ I:circ($Mu)) = $"#RegSrc#"", - [], - "$Rz = $_dst_" > { - bits<5> Rz; - bits<1> Mu; - bits<5> Rt; - - let accessSize = AlignSize; - let isNVStorable = !if(!eq(mnemonic,"memd"), 0, - !if(!eq(RegSrc,"Rt.h"), 0, 1)); - - let IClass = 0b1010; - let Inst{27-25} = 0b100; - let Inst{24-21} = MajOp; - let Inst{20-16} = Rz; - let Inst{13} = Mu; - let Inst{12-8} = Rt; - let Inst{7} = 0b0; - let Inst{1} = 0b1; - } - -def S2_storerb_pcr : T_store_pcr<"memb", IntRegs, 0b1000, ByteAccess>; -def S2_storerh_pcr : T_store_pcr<"memh", IntRegs, 0b1010, HalfWordAccess>; -def S2_storeri_pcr : T_store_pcr<"memw", IntRegs, 0b1100, WordAccess>; -def S2_storerd_pcr : T_store_pcr<"memd", DoubleRegs, 0b1110, DoubleWordAccess>; -def S2_storerf_pcr : T_store_pcr<"memh", IntRegs, 0b1011, - HalfWordAccess, "Rt.h">; - -//===----------------------------------------------------------------------===// -// Circular .new stores with auto-increment register -//===----------------------------------------------------------------------===// -let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3, - addrMode = PostInc in -class T_storenew_pcr <string mnemonic, bits<2>MajOp, - MemAccessSize AlignSize> - : NVInst <(outs IntRegs:$_dst_), - (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt), - #mnemonic#"($Rz ++ I:circ($Mu)) = $Nt.new" , - [] , - "$Rz = $_dst_"> { - bits<5> Rz; - bits<1> Mu; - bits<3> Nt; - - let accessSize = AlignSize; - - let IClass = 0b1010; - let Inst{27-21} = 0b1001101; - let Inst{20-16} = Rz; - let Inst{13} = Mu; - let Inst{12-11} = MajOp; - let Inst{10-8} = Nt; - let Inst{7} = 0b0; - let Inst{1} = 0b1; - } - -def S2_storerbnew_pcr : T_storenew_pcr <"memb", 0b00, ByteAccess>; -def S2_storerhnew_pcr : T_storenew_pcr <"memh", 0b01, HalfWordAccess>; -def S2_storerinew_pcr : T_storenew_pcr <"memw", 0b10, WordAccess>; - -//===----------------------------------------------------------------------===// -// Bit-reversed stores with auto-increment register -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, addrMode = PostInc in -class T_store_pbr<string mnemonic, RegisterClass RC, - MemAccessSize addrSize, bits<3> majOp, - bit isHalf = 0> - : STInst - <(outs IntRegs:$_dst_), - (ins IntRegs:$Rz, ModRegs:$Mu, RC:$src), - #mnemonic#"($Rz ++ $Mu:brev) = $src"#!if (!eq(isHalf, 1), ".h", ""), - [], "$Rz = $_dst_" > { - - let accessSize = addrSize; - - bits<5> Rz; - bits<1> Mu; - bits<5> src; - - let IClass = 0b1010; - - let Inst{27-24} = 0b1111; - let Inst{23-21} = majOp; - let Inst{7} = 0b0; - let Inst{20-16} = Rz; - let Inst{13} = Mu; - let Inst{12-8} = src; - } - -let isNVStorable = 1 in { - let BaseOpcode = "S2_storerb_pbr" in - def S2_storerb_pbr : T_store_pbr<"memb", IntRegs, ByteAccess, - 0b000>, NewValueRel; - let BaseOpcode = "S2_storerh_pbr" in - def S2_storerh_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, - 0b010>, NewValueRel; - let BaseOpcode = "S2_storeri_pbr" in - def S2_storeri_pbr : T_store_pbr<"memw", IntRegs, WordAccess, - 0b100>, NewValueRel; -} - -def S2_storerf_pbr : T_store_pbr<"memh", IntRegs, HalfWordAccess, 0b011, 1>; -def S2_storerd_pbr : T_store_pbr<"memd", DoubleRegs, DoubleWordAccess, 0b110>; - -//===----------------------------------------------------------------------===// -// Bit-reversed .new stores with auto-increment register -//===----------------------------------------------------------------------===// -let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3, - hasSideEffects = 0, addrMode = PostInc in -class T_storenew_pbr<string mnemonic, MemAccessSize addrSize, bits<2> majOp> - : NVInst <(outs IntRegs:$_dst_), - (ins IntRegs:$Rz, ModRegs:$Mu, IntRegs:$Nt), - #mnemonic#"($Rz ++ $Mu:brev) = $Nt.new", [], - "$Rz = $_dst_">, NewValueRel { - let accessSize = addrSize; - bits<5> Rz; - bits<1> Mu; - bits<3> Nt; - - let IClass = 0b1010; - - let Inst{27-21} = 0b1111101; - let Inst{12-11} = majOp; - let Inst{7} = 0b0; - let Inst{20-16} = Rz; - let Inst{13} = Mu; - let Inst{10-8} = Nt; - } - -let BaseOpcode = "S2_storerb_pbr" in -def S2_storerbnew_pbr : T_storenew_pbr<"memb", ByteAccess, 0b00>; - -let BaseOpcode = "S2_storerh_pbr" in -def S2_storerhnew_pbr : T_storenew_pbr<"memh", HalfWordAccess, 0b01>; - -let BaseOpcode = "S2_storeri_pbr" in -def S2_storerinew_pbr : T_storenew_pbr<"memw", WordAccess, 0b10>; - -//===----------------------------------------------------------------------===// -// ST - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// Template class for S_2op instructions. -//===----------------------------------------------------------------------===// -let hasSideEffects = 0 in -class T_S2op_1 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut, - RegisterClass RCIn, bits<2> MajOp, bits<3> MinOp, bit isSat> - : SInst <(outs RCOut:$dst), (ins RCIn:$src), - "$dst = "#mnemonic#"($src)"#!if(isSat, ":sat", ""), - [], "", S_2op_tc_1_SLOT23 > { - bits<5> dst; - bits<5> src; - - let IClass = 0b1000; - - let Inst{27-24} = RegTyBits; - let Inst{23-22} = MajOp; - let Inst{21} = 0b0; - let Inst{20-16} = src; - let Inst{7-5} = MinOp; - let Inst{4-0} = dst; - } - -class T_S2op_1_di <string mnemonic, bits<2> MajOp, bits<3> MinOp> - : T_S2op_1 <mnemonic, 0b0100, DoubleRegs, IntRegs, MajOp, MinOp, 0>; - -let hasNewValue = 1 in -class T_S2op_1_id <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0> - : T_S2op_1 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, isSat>; - -let hasNewValue = 1 in -class T_S2op_1_ii <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit isSat = 0> - : T_S2op_1 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, isSat>; - -// Vector sign/zero extend -let isReMaterializable = 1, isAsCheapAsAMove = 1 in { - def S2_vsxtbh : T_S2op_1_di <"vsxtbh", 0b00, 0b000>; - def S2_vsxthw : T_S2op_1_di <"vsxthw", 0b00, 0b100>; - def S2_vzxtbh : T_S2op_1_di <"vzxtbh", 0b00, 0b010>; - def S2_vzxthw : T_S2op_1_di <"vzxthw", 0b00, 0b110>; -} - -// Vector splat bytes/halfwords -let isReMaterializable = 1, isAsCheapAsAMove = 1 in { - def S2_vsplatrb : T_S2op_1_ii <"vsplatb", 0b01, 0b111>; - def S2_vsplatrh : T_S2op_1_di <"vsplath", 0b01, 0b010>; -} - -// Sign extend word to doubleword -def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>; - -// Vector saturate and pack -let Defs = [USR_OVF] in { - def S2_svsathb : T_S2op_1_ii <"vsathb", 0b10, 0b000>; - def S2_svsathub : T_S2op_1_ii <"vsathub", 0b10, 0b010>; - def S2_vsathb : T_S2op_1_id <"vsathb", 0b00, 0b110>; - def S2_vsathub : T_S2op_1_id <"vsathub", 0b00, 0b000>; - def S2_vsatwh : T_S2op_1_id <"vsatwh", 0b00, 0b010>; - def S2_vsatwuh : T_S2op_1_id <"vsatwuh", 0b00, 0b100>; -} - -// Vector truncate -def S2_vtrunohb : T_S2op_1_id <"vtrunohb", 0b10, 0b000>; -def S2_vtrunehb : T_S2op_1_id <"vtrunehb", 0b10, 0b010>; - -// Swizzle the bytes of a word -def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>; - -// Saturate -let Defs = [USR_OVF] in { - def A2_sat : T_S2op_1_id <"sat", 0b11, 0b000>; - def A2_satb : T_S2op_1_ii <"satb", 0b11, 0b111>; - def A2_satub : T_S2op_1_ii <"satub", 0b11, 0b110>; - def A2_sath : T_S2op_1_ii <"sath", 0b11, 0b100>; - def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>; - def A2_roundsat : T_S2op_1_id <"round", 0b11, 0b001, 0b1>; -} - -let Itinerary = S_2op_tc_2_SLOT23 in { - // Vector round and pack - def S2_vrndpackwh : T_S2op_1_id <"vrndwh", 0b10, 0b100>; - - let Defs = [USR_OVF] in - def S2_vrndpackwhs : T_S2op_1_id <"vrndwh", 0b10, 0b110, 1>; - - // Bit reverse - def S2_brev : T_S2op_1_ii <"brev", 0b01, 0b110>; - - // Absolute value word - def A2_abs : T_S2op_1_ii <"abs", 0b10, 0b100>; - - let Defs = [USR_OVF] in - def A2_abssat : T_S2op_1_ii <"abs", 0b10, 0b101, 1>; - - // Negate with saturation - let Defs = [USR_OVF] in - def A2_negsat : T_S2op_1_ii <"neg", 0b10, 0b110, 1>; -} - -class T_S2op_2 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut, - RegisterClass RCIn, bits<3> MajOp, bits<3> MinOp, - bit isSat, bit isRnd, list<dag> pattern = []> - : SInst <(outs RCOut:$dst), - (ins RCIn:$src, u5_0Imm:$u5), - "$dst = "#mnemonic#"($src, #$u5)"#!if(isSat, ":sat", "") - #!if(isRnd, ":rnd", ""), - pattern, "", S_2op_tc_2_SLOT23> { - bits<5> dst; - bits<5> src; - bits<5> u5; - - let IClass = 0b1000; - - let Inst{27-24} = RegTyBits; - let Inst{23-21} = MajOp; - let Inst{20-16} = src; - let Inst{13} = 0b0; - let Inst{12-8} = u5; - let Inst{7-5} = MinOp; - let Inst{4-0} = dst; - } - -class T_S2op_2_di <string mnemonic, bits<3> MajOp, bits<3> MinOp> - : T_S2op_2 <mnemonic, 0b1000, DoubleRegs, IntRegs, MajOp, MinOp, 0, 0>; - -let hasNewValue = 1 in -class T_S2op_2_id <string mnemonic, bits<3> MajOp, bits<3> MinOp> - : T_S2op_2 <mnemonic, 0b1000, IntRegs, DoubleRegs, MajOp, MinOp, 0, 0>; - -let hasNewValue = 1 in -class T_S2op_2_ii <string mnemonic, bits<3> MajOp, bits<3> MinOp, - bit isSat = 0, bit isRnd = 0, list<dag> pattern = []> - : T_S2op_2 <mnemonic, 0b1100, IntRegs, IntRegs, MajOp, MinOp, - isSat, isRnd, pattern>; - -class T_S2op_shift <string mnemonic, bits<3> MajOp, bits<3> MinOp, SDNode OpNd> - : T_S2op_2_ii <mnemonic, MajOp, MinOp, 0, 0, []>; - -// Vector arithmetic shift right by immediate with truncate and pack -def S2_asr_i_svw_trun : T_S2op_2_id <"vasrw", 0b110, 0b010>; - -// Arithmetic/logical shift right/left by immediate -let Itinerary = S_2op_tc_1_SLOT23 in { - def S2_asr_i_r : T_S2op_shift <"asr", 0b000, 0b000, sra>; - def S2_lsr_i_r : T_S2op_shift <"lsr", 0b000, 0b001, srl>; - def S2_asl_i_r : T_S2op_shift <"asl", 0b000, 0b010, shl>; -} - -// Shift left by immediate with saturation -let Defs = [USR_OVF] in -def S2_asl_i_r_sat : T_S2op_2_ii <"asl", 0b010, 0b010, 1>; - -// Shift right with round -def S2_asr_i_r_rnd : T_S2op_2_ii <"asr", 0b010, 0b000, 0, 1>; - -let isAsmParserOnly = 1 in -def S2_asr_i_r_rnd_goodsyntax - : SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5_0Imm:$u5), - "$dst = asrrnd($src, #$u5)", - [], "", S_2op_tc_1_SLOT23>; - -let isAsmParserOnly = 1 in -def A2_not: ALU32_rr<(outs IntRegs:$dst),(ins IntRegs:$src), - "$dst = not($src)">; - -class T_S2op_3<string opc, bits<2>MajOp, bits<3>minOp, bits<1> sat = 0> - : SInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss), - "$Rdd = "#opc#"($Rss)"#!if(!eq(sat, 1),":sat","")> { - bits<5> Rss; - bits<5> Rdd; - let IClass = 0b1000; - let Inst{27-24} = 0; - let Inst{23-22} = MajOp; - let Inst{20-16} = Rss; - let Inst{7-5} = minOp; - let Inst{4-0} = Rdd; -} - -def A2_absp : T_S2op_3 <"abs", 0b10, 0b110>; -def A2_negp : T_S2op_3 <"neg", 0b10, 0b101>; -def A2_notp : T_S2op_3 <"not", 0b10, 0b100>; - -// Innterleave/deinterleave -def S2_interleave : T_S2op_3 <"interleave", 0b11, 0b101>; -def S2_deinterleave : T_S2op_3 <"deinterleave", 0b11, 0b100>; - -// Vector Complex conjugate -def A2_vconj : T_S2op_3 <"vconj", 0b10, 0b111, 1>; - -// Vector saturate without pack -def S2_vsathb_nopack : T_S2op_3 <"vsathb", 0b00, 0b111>; -def S2_vsathub_nopack : T_S2op_3 <"vsathub", 0b00, 0b100>; -def S2_vsatwh_nopack : T_S2op_3 <"vsatwh", 0b00, 0b110>; -def S2_vsatwuh_nopack : T_S2op_3 <"vsatwuh", 0b00, 0b101>; - -// Vector absolute value halfwords with and without saturation -// Rdd64=vabsh(Rss64)[:sat] -def A2_vabsh : T_S2op_3 <"vabsh", 0b01, 0b100>; -def A2_vabshsat : T_S2op_3 <"vabsh", 0b01, 0b101, 1>; - -// Vector absolute value words with and without saturation -def A2_vabsw : T_S2op_3 <"vabsw", 0b01, 0b110>; -def A2_vabswsat : T_S2op_3 <"vabsw", 0b01, 0b111, 1>; - -//===----------------------------------------------------------------------===// -// STYPE/BIT + -//===----------------------------------------------------------------------===// -// Bit count - -let hasSideEffects = 0, hasNewValue = 1 in -class T_COUNT_LEADING<string MnOp, bits<3> MajOp, bits<3> MinOp, bit Is32, - dag Out, dag Inp> - : SInst<Out, Inp, "$Rd = "#MnOp#"($Rs)", [], "", S_2op_tc_1_SLOT23> { - bits<5> Rs; - bits<5> Rd; - let IClass = 0b1000; - let Inst{27} = 0b1; - let Inst{26} = Is32; - let Inst{25-24} = 0b00; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rd; -} - -class T_COUNT_LEADING_32<string MnOp, bits<3> MajOp, bits<3> MinOp> - : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b1, - (outs IntRegs:$Rd), (ins IntRegs:$Rs)>; - -class T_COUNT_LEADING_64<string MnOp, bits<3> MajOp, bits<3> MinOp> - : T_COUNT_LEADING<MnOp, MajOp, MinOp, 0b0, - (outs IntRegs:$Rd), (ins DoubleRegs:$Rs)>; - -def S2_cl0 : T_COUNT_LEADING_32<"cl0", 0b000, 0b101>; -def S2_cl1 : T_COUNT_LEADING_32<"cl1", 0b000, 0b110>; -def S2_ct0 : T_COUNT_LEADING_32<"ct0", 0b010, 0b100>; -def S2_ct1 : T_COUNT_LEADING_32<"ct1", 0b010, 0b101>; -def S2_cl0p : T_COUNT_LEADING_64<"cl0", 0b010, 0b010>; -def S2_cl1p : T_COUNT_LEADING_64<"cl1", 0b010, 0b100>; -def S2_clb : T_COUNT_LEADING_32<"clb", 0b000, 0b100>; -def S2_clbp : T_COUNT_LEADING_64<"clb", 0b010, 0b000>; -def S2_clbnorm : T_COUNT_LEADING_32<"normamt", 0b000, 0b111>; - -// The 64-bit counts leading/trailing are defined in HexagonInstrInfoV4.td. - -// Bit set/clear/toggle - -let hasSideEffects = 0, hasNewValue = 1 in -class T_SCT_BIT_IMM<string MnOp, bits<3> MinOp> - : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5_0Imm:$u5), - "$Rd = "#MnOp#"($Rs, #$u5)", [], "", S_2op_tc_1_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> u5; - let IClass = 0b1000; - let Inst{27-21} = 0b1100110; - let Inst{20-16} = Rs; - let Inst{13} = 0b0; - let Inst{12-8} = u5; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rd; -} - -let hasSideEffects = 0, hasNewValue = 1 in -class T_SCT_BIT_REG<string MnOp, bits<2> MinOp> - : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = "#MnOp#"($Rs, $Rt)", [], "", S_3op_tc_1_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - let IClass = 0b1100; - let Inst{27-22} = 0b011010; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{7-6} = MinOp; - let Inst{4-0} = Rd; -} - -def S2_clrbit_i : T_SCT_BIT_IMM<"clrbit", 0b001>; -def S2_setbit_i : T_SCT_BIT_IMM<"setbit", 0b000>; -def S2_togglebit_i : T_SCT_BIT_IMM<"togglebit", 0b010>; -def S2_clrbit_r : T_SCT_BIT_REG<"clrbit", 0b01>; -def S2_setbit_r : T_SCT_BIT_REG<"setbit", 0b00>; -def S2_togglebit_r : T_SCT_BIT_REG<"togglebit", 0b10>; - -// Bit test - -let hasSideEffects = 0 in -class T_TEST_BIT_IMM<string MnOp, bits<3> MajOp> - : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5_0Imm:$u5), - "$Pd = "#MnOp#"($Rs, #$u5)", - [], "", S_2op_tc_2early_SLOT23> { - bits<2> Pd; - bits<5> Rs; - bits<5> u5; - let IClass = 0b1000; - let Inst{27-24} = 0b0101; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{13} = 0; - let Inst{12-8} = u5; - let Inst{1-0} = Pd; -} - -let hasSideEffects = 0 in -class T_TEST_BIT_REG<string MnOp, bit IsNeg> - : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Pd = "#MnOp#"($Rs, $Rt)", - [], "", S_3op_tc_2early_SLOT23> { - bits<2> Pd; - bits<5> Rs; - bits<5> Rt; - let IClass = 0b1100; - let Inst{27-22} = 0b011100; - let Inst{21} = IsNeg; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{1-0} = Pd; -} - -def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>; -def S2_tstbit_r : T_TEST_BIT_REG<"tstbit", 0>; - -let hasSideEffects = 0 in -class T_TEST_BITS_IMM<string MnOp, bits<2> MajOp, bit IsNeg> - : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u6_0Imm:$u6), - "$Pd = "#MnOp#"($Rs, #$u6)", - [], "", S_2op_tc_2early_SLOT23> { - bits<2> Pd; - bits<5> Rs; - bits<6> u6; - let IClass = 0b1000; - let Inst{27-24} = 0b0101; - let Inst{23-22} = MajOp; - let Inst{21} = IsNeg; - let Inst{20-16} = Rs; - let Inst{13-8} = u6; - let Inst{1-0} = Pd; -} - -let hasSideEffects = 0 in -class T_TEST_BITS_REG<string MnOp, bits<2> MajOp, bit IsNeg> - : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Pd = "#MnOp#"($Rs, $Rt)", - [], "", S_3op_tc_2early_SLOT23> { - bits<2> Pd; - bits<5> Rs; - bits<5> Rt; - let IClass = 0b1100; - let Inst{27-24} = 0b0111; - let Inst{23-22} = MajOp; - let Inst{21} = IsNeg; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{1-0} = Pd; -} - -def C2_bitsclri : T_TEST_BITS_IMM<"bitsclr", 0b10, 0>; -def C2_bitsclr : T_TEST_BITS_REG<"bitsclr", 0b10, 0>; -def C2_bitsset : T_TEST_BITS_REG<"bitsset", 0b01, 0>; - -//===----------------------------------------------------------------------===// -// STYPE/BIT - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// STYPE/COMPLEX + -//===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// STYPE/COMPLEX - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// XTYPE/PERM + -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// XTYPE/PERM - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// STYPE/PRED + -//===----------------------------------------------------------------------===// - -// Predicate transfer. -let hasSideEffects = 0, hasNewValue = 1 in -def C2_tfrpr : SInst<(outs IntRegs:$Rd), (ins PredRegs:$Ps), - "$Rd = $Ps", [], "", S_2op_tc_1_SLOT23> { - bits<5> Rd; - bits<2> Ps; - - let IClass = 0b1000; - let Inst{27-24} = 0b1001; - let Inst{22} = 0b1; - let Inst{17-16} = Ps; - let Inst{4-0} = Rd; -} - -// Transfer general register to predicate. -let hasSideEffects = 0 in -def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs), - "$Pd = $Rs", [], "", S_2op_tc_2early_SLOT23> { - bits<2> Pd; - bits<5> Rs; - - let IClass = 0b1000; - let Inst{27-21} = 0b0101010; - let Inst{20-16} = Rs; - let Inst{1-0} = Pd; -} - -let hasSideEffects = 0, isCodeGenOnly = 1 in -def C2_pxfer_map: SInst<(outs PredRegs:$dst), (ins PredRegs:$src), - "$dst = $src">; - -//===----------------------------------------------------------------------===// -// STYPE/PRED - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// STYPE/SHIFT + -//===----------------------------------------------------------------------===// -class S_2OpInstImm<string Mnemonic, bits<3>MajOp, bits<3>MinOp, - Operand Imm, list<dag> pattern = [], bit isRnd = 0> - : SInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, Imm:$src2), - "$dst = "#Mnemonic#"($src1, #$src2)"#!if(isRnd, ":rnd", ""), - pattern> { - bits<5> src1; - bits<5> dst; - let IClass = 0b1000; - let Inst{27-24} = 0; - let Inst{23-21} = MajOp; - let Inst{20-16} = src1; - let Inst{7-5} = MinOp; - let Inst{4-0} = dst; -} - -class S_2OpInstImmI6<string Mnemonic, SDNode OpNode, bits<3>MinOp> - : S_2OpInstImm<Mnemonic, 0b000, MinOp, u6_0Imm, []> { - bits<6> src2; - let Inst{13-8} = src2; -} - -// Shift by immediate. -def S2_asr_i_p : S_2OpInstImmI6<"asr", sra, 0b000>; -def S2_asl_i_p : S_2OpInstImmI6<"asl", shl, 0b010>; -def S2_lsr_i_p : S_2OpInstImmI6<"lsr", srl, 0b001>; - -// Shift left by small amount and add. -let AddedComplexity = 100, hasNewValue = 1, hasSideEffects = 0 in -def S2_addasl_rrri: SInst <(outs IntRegs:$Rd), - (ins IntRegs:$Rt, IntRegs:$Rs, u3_0Imm:$u3), - "$Rd = addasl($Rt, $Rs, #$u3)" , [], - "", S_3op_tc_2_SLOT23> { - bits<5> Rd; - bits<5> Rt; - bits<5> Rs; - bits<3> u3; - - let IClass = 0b1100; - - let Inst{27-21} = 0b0100000; - let Inst{20-16} = Rs; - let Inst{13} = 0b0; - let Inst{12-8} = Rt; - let Inst{7-5} = u3; - let Inst{4-0} = Rd; - } - -//===----------------------------------------------------------------------===// -// STYPE/SHIFT - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// STYPE/VH + -//===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// STYPE/VH - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// STYPE/VW + -//===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// STYPE/VW - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// SYSTEM/SUPER + -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// SYSTEM/USER + -//===----------------------------------------------------------------------===// -let hasSideEffects = 1, isSoloAX = 1 in -def Y2_barrier : SYSInst<(outs), (ins), "barrier", [],"",ST_tc_st_SLOT0> { - let Inst{31-28} = 0b1010; - let Inst{27-21} = 0b1000000; -} - -//===----------------------------------------------------------------------===// -// SYSTEM/SUPER - -//===----------------------------------------------------------------------===// - -// Generate frameindex addresses. The main reason for the offset operand is -// that every instruction that is allowed to have frame index as an operand -// will then have that operand followed by an immediate operand (the offset). -// This simplifies the frame-index elimination code. -// -let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1, - isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in { - def PS_fi : ALU32_ri<(outs IntRegs:$Rd), - (ins IntRegs:$fi, s32_0Imm:$off), "">; - def PS_fia : ALU32_ri<(outs IntRegs:$Rd), - (ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">; -} - -//===----------------------------------------------------------------------===// -// CRUSER - Type. -//===----------------------------------------------------------------------===// -// HW loop -let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2, - opExtendable = 0, hasSideEffects = 0 in -class LOOP_iBase<string mnemonic, Operand brOp, bit mustExtend = 0> - : CRInst<(outs), (ins brOp:$offset, u10_0Imm:$src2), - #mnemonic#"($offset, #$src2)", - [], "" , CR_tc_3x_SLOT3> { - bits<9> offset; - bits<10> src2; - - let IClass = 0b0110; - - let Inst{27-22} = 0b100100; - let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1); - let Inst{20-16} = src2{9-5}; - let Inst{12-8} = offset{8-4}; - let Inst{7-5} = src2{4-2}; - let Inst{4-3} = offset{3-2}; - let Inst{1-0} = src2{1-0}; -} - -let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2, - opExtendable = 0, hasSideEffects = 0 in -class LOOP_rBase<string mnemonic, Operand brOp, bit mustExtend = 0> - : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2), - #mnemonic#"($offset, $src2)", - [], "" ,CR_tc_3x_SLOT3> { - bits<9> offset; - bits<5> src2; - - let IClass = 0b0110; - - let Inst{27-22} = 0b000000; - let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1); - let Inst{20-16} = src2; - let Inst{12-8} = offset{8-4}; - let Inst{4-3} = offset{3-2}; - } - -multiclass LOOP_ri<string mnemonic> { - def i : LOOP_iBase<mnemonic, brtarget>; - def r : LOOP_rBase<mnemonic, brtarget>; - - let isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in { - def iext: LOOP_iBase<mnemonic, brtargetExt, 1>; - def rext: LOOP_rBase<mnemonic, brtargetExt, 1>; - } -} - - -let Defs = [SA0, LC0, USR] in -defm J2_loop0 : LOOP_ri<"loop0">; - -// Interestingly only loop0's appear to set usr.lpcfg -let Defs = [SA1, LC1] in -defm J2_loop1 : LOOP_ri<"loop1">; - -let isBranch = 1, isTerminator = 1, hasSideEffects = 0, - Defs = [PC, LC0], Uses = [SA0, LC0] in { -def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset), - ":endloop0", - []>; -} - -let isBranch = 1, isTerminator = 1, hasSideEffects = 0, - Defs = [PC, LC1], Uses = [SA1, LC1] in { -def ENDLOOP1 : Endloop<(outs), (ins brtarget:$offset), - ":endloop1", - []>; -} - -// Pipelined loop instructions, sp[123]loop0 -let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0, - isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2, - opExtendable = 0, isPredicateLate = 1 in -class SPLOOP_iBase<string SP, bits<2> op> - : CRInst <(outs), (ins brtarget:$r7_2, u10_0Imm:$U10), - "p3 = sp"#SP#"loop0($r7_2, #$U10)" > { - bits<9> r7_2; - bits<10> U10; - - let IClass = 0b0110; - - let Inst{22-21} = op; - let Inst{27-23} = 0b10011; - let Inst{20-16} = U10{9-5}; - let Inst{12-8} = r7_2{8-4}; - let Inst{7-5} = U10{4-2}; - let Inst{4-3} = r7_2{3-2}; - let Inst{1-0} = U10{1-0}; - } - -let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0, - isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2, - opExtendable = 0, isPredicateLate = 1 in -class SPLOOP_rBase<string SP, bits<2> op> - : CRInst <(outs), (ins brtarget:$r7_2, IntRegs:$Rs), - "p3 = sp"#SP#"loop0($r7_2, $Rs)" > { - bits<9> r7_2; - bits<5> Rs; - - let IClass = 0b0110; - - let Inst{22-21} = op; - let Inst{27-23} = 0b00001; - let Inst{20-16} = Rs; - let Inst{12-8} = r7_2{8-4}; - let Inst{4-3} = r7_2{3-2}; - } - -multiclass SPLOOP_ri<string mnemonic, bits<2> op> { - def i : SPLOOP_iBase<mnemonic, op>; - def r : SPLOOP_rBase<mnemonic, op>; -} - -defm J2_ploop1s : SPLOOP_ri<"1", 0b01>; -defm J2_ploop2s : SPLOOP_ri<"2", 0b10>; -defm J2_ploop3s : SPLOOP_ri<"3", 0b11>; - -// if (Rs[!>=<]=#0) jump:[t/nt] -let Defs = [PC], isPredicated = 1, isBranch = 1, hasSideEffects = 0, - hasSideEffects = 0 in -class J2_jump_0_Base<string compare, bit isTak, bits<2> op> - : CRInst <(outs), (ins IntRegs:$Rs, brtarget:$r13_2), - "if ($Rs"#compare#"#0) jump"#!if(isTak, ":t", ":nt")#" $r13_2" > { - bits<5> Rs; - bits<15> r13_2; - - let IClass = 0b0110; - - let Inst{27-24} = 0b0001; - let Inst{23-22} = op; - let Inst{12} = isTak; - let Inst{21} = r13_2{14}; - let Inst{20-16} = Rs; - let Inst{11-1} = r13_2{12-2}; - let Inst{13} = r13_2{13}; - } - -multiclass J2_jump_compare_0<string compare, bits<2> op> { - def NAME : J2_jump_0_Base<compare, 0, op>; - def NAME#pt : J2_jump_0_Base<compare, 1, op>; -} - -defm J2_jumprz : J2_jump_compare_0<"!=", 0b00>; -defm J2_jumprgtez : J2_jump_compare_0<">=", 0b01>; -defm J2_jumprnz : J2_jump_compare_0<"==", 0b10>; -defm J2_jumprltez : J2_jump_compare_0<"<=", 0b11>; - -// Transfer to/from Control/GPR Guest/GPR -let hasSideEffects = 0 in -class TFR_CR_RS_base<RegisterClass CTRC, RegisterClass RC, bit isDouble> - : CRInst <(outs CTRC:$dst), (ins RC:$src), - "$dst = $src", [], "", CR_tc_3x_SLOT3> { - bits<5> dst; - bits<5> src; - - let IClass = 0b0110; - - let Inst{27-25} = 0b001; - let Inst{24} = isDouble; - let Inst{23-21} = 0b001; - let Inst{20-16} = src; - let Inst{4-0} = dst; - } - -def A2_tfrrcr : TFR_CR_RS_base<CtrRegs, IntRegs, 0b0>; -def A4_tfrpcp : TFR_CR_RS_base<CtrRegs64, DoubleRegs, 0b1>; -def : InstAlias<"m0 = $Rs", (A2_tfrrcr C6, IntRegs:$Rs)>; -def : InstAlias<"m1 = $Rs", (A2_tfrrcr C7, IntRegs:$Rs)>; - -let hasSideEffects = 0 in -class TFR_RD_CR_base<RegisterClass RC, RegisterClass CTRC, bit isSingle> - : CRInst <(outs RC:$dst), (ins CTRC:$src), - "$dst = $src", [], "", CR_tc_3x_SLOT3> { - bits<5> dst; - bits<5> src; - - let IClass = 0b0110; - - let Inst{27-26} = 0b10; - let Inst{25} = isSingle; - let Inst{24-21} = 0b0000; - let Inst{20-16} = src; - let Inst{4-0} = dst; - } - -let hasNewValue = 1, opNewValue = 0 in -def A2_tfrcrr : TFR_RD_CR_base<IntRegs, CtrRegs, 1>; -def A4_tfrcpp : TFR_RD_CR_base<DoubleRegs, CtrRegs64, 0>; -def : InstAlias<"$Rd = m0", (A2_tfrcrr IntRegs:$Rd, C6)>; -def : InstAlias<"$Rd = m1", (A2_tfrcrr IntRegs:$Rd, C7)>; - -// Y4_trace: Send value to etm trace. -let isSoloAX = 1, hasSideEffects = 0 in -def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs), - "trace($Rs)"> { - bits<5> Rs; - - let IClass = 0b0110; - let Inst{27-21} = 0b0010010; - let Inst{20-16} = Rs; - } - -// HI/LO Instructions -let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0, - hasNewValue = 1, opNewValue = 0 in -class REG_IMMED<string RegHalf, bit Rs, bits<3> MajOp, bit MinOp> - : ALU32_ri<(outs IntRegs:$dst), - (ins u16_0Imm:$imm_value), - "$dst"#RegHalf#" = $imm_value", []> { - bits<5> dst; - bits<32> imm_value; - let IClass = 0b0111; - - let Inst{27} = Rs; - let Inst{26-24} = MajOp; - let Inst{21} = MinOp; - let Inst{20-16} = dst; - let Inst{23-22} = imm_value{15-14}; - let Inst{13-0} = imm_value{13-0}; -} - -let isAsmParserOnly = 1 in { - def LO : REG_IMMED<".l", 0b0, 0b001, 0b1>; - def HI : REG_IMMED<".h", 0b0, 0b010, 0b1>; -} - -let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in { - def CONST32 : CONSTLDInst<(outs IntRegs:$Rd), (ins i32imm:$v), - "$Rd = CONST32(#$v)", []>; - def CONST64 : CONSTLDInst<(outs DoubleRegs:$Rd), (ins i64imm:$v), - "$Rd = CONST64(#$v)", []>; -} - -let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1, - isCodeGenOnly = 1 in -def PS_true : SInst<(outs PredRegs:$dst), (ins), "", []>; - -let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1, - isCodeGenOnly = 1 in -def PS_false : SInst<(outs PredRegs:$dst), (ins), "", []>; - -let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in -def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), - ".error \"should not emit\" ", []>; - -let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in -def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), - ".error \"should not emit\" ", []>; - -// Call subroutine indirectly. -let Defs = VolatileV3.Regs in -def J2_callr : JUMPR_MISC_CALLR<0, 1>; - -// Indirect tail-call. -let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, - isTerminator = 1, isCodeGenOnly = 1 in -def PS_tailcall_r : T_JMPr; - -// Direct tail-calls. -let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, - isTerminator = 1, isCodeGenOnly = 1 in -def PS_tailcall_i : JInst<(outs), (ins calltarget:$dst), "", []>; - -// The reason for the custom inserter is to record all ALLOCA instructions -// in MachineFunctionInfo. -let Defs = [R29], isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 1 in -def PS_alloca: ALU32Inst<(outs IntRegs:$Rd), - (ins IntRegs:$Rs, u32_0Imm:$A), "", []>; - -let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in -def PS_aligna : ALU32Inst<(outs IntRegs:$Rd), (ins u32_0Imm:$A), "", []>; - -// XTYPE/SHIFT -// -//===----------------------------------------------------------------------===// -// Template Class -// Shift by immediate/register and accumulate/logical -//===----------------------------------------------------------------------===// - -// Rx[+-&|]=asr(Rs,#u5) -// Rx[+-&|^]=lsr(Rs,#u5) -// Rx[+-&|^]=asl(Rs,#u5) - -let hasNewValue = 1, opNewValue = 0 in -class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1, - SDNode OpNode2, bits<3> majOp, bits<2> minOp> - : SInst_acc<(outs IntRegs:$Rx), - (ins IntRegs:$src1, IntRegs:$Rs, u5_0Imm:$u5), - "$Rx "#opc2#opc1#"($Rs, #$u5)", [], - "$src1 = $Rx", S_2op_tc_2_SLOT23> { - bits<5> Rx; - bits<5> Rs; - bits<5> u5; - - let IClass = 0b1000; - - let Inst{27-24} = 0b1110; - let Inst{23-22} = majOp{2-1}; - let Inst{13} = 0b0; - let Inst{7} = majOp{0}; - let Inst{6-5} = minOp; - let Inst{4-0} = Rx; - let Inst{20-16} = Rs; - let Inst{12-8} = u5; - } - -// Rx[+-&|]=asr(Rs,Rt) -// Rx[+-&|^]=lsr(Rs,Rt) -// Rx[+-&|^]=asl(Rs,Rt) - -let hasNewValue = 1, opNewValue = 0 in -class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1, - SDNode OpNode2, bits<2> majOp, bits<2> minOp> - : SInst_acc<(outs IntRegs:$Rx), - (ins IntRegs:$src1, IntRegs:$Rs, IntRegs:$Rt), - "$Rx "#opc2#opc1#"($Rs, $Rt)", [], - "$src1 = $Rx", S_3op_tc_2_SLOT23 > { - bits<5> Rx; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1100; - - let Inst{27-24} = 0b1100; - let Inst{23-22} = majOp; - let Inst{7-6} = minOp; - let Inst{4-0} = Rx; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - } - -// Rxx[+-&|]=asr(Rss,#u6) -// Rxx[+-&|^]=lsr(Rss,#u6) -// Rxx[+-&|^]=asl(Rss,#u6) - -class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1, - SDNode OpNode2, bits<3> majOp, bits<2> minOp> - : SInst_acc<(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$src1, DoubleRegs:$Rss, u6_0Imm:$u6), - "$Rxx "#opc2#opc1#"($Rss, #$u6)", [], - "$src1 = $Rxx", S_2op_tc_2_SLOT23> { - bits<5> Rxx; - bits<5> Rss; - bits<6> u6; - - let IClass = 0b1000; - - let Inst{27-24} = 0b0010; - let Inst{23-22} = majOp{2-1}; - let Inst{7} = majOp{0}; - let Inst{6-5} = minOp; - let Inst{4-0} = Rxx; - let Inst{20-16} = Rss; - let Inst{13-8} = u6; - } - - -// Rxx[+-&|]=asr(Rss,Rt) -// Rxx[+-&|^]=lsr(Rss,Rt) -// Rxx[+-&|^]=asl(Rss,Rt) -// Rxx[+-&|^]=lsl(Rss,Rt) - -class T_shift_reg_acc_p <string opc1, string opc2, SDNode OpNode1, - SDNode OpNode2, bits<3> majOp, bits<2> minOp> - : SInst_acc<(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$src1, DoubleRegs:$Rss, IntRegs:$Rt), - "$Rxx "#opc2#opc1#"($Rss, $Rt)", [], - "$src1 = $Rxx", S_3op_tc_2_SLOT23> { - bits<5> Rxx; - bits<5> Rss; - bits<5> Rt; - - let IClass = 0b1100; - - let Inst{27-24} = 0b1011; - let Inst{23-21} = majOp; - let Inst{20-16} = Rss; - let Inst{12-8} = Rt; - let Inst{7-6} = minOp; - let Inst{4-0} = Rxx; - } - -//===----------------------------------------------------------------------===// -// Multi-class for the shift instructions with logical/arithmetic operators. -//===----------------------------------------------------------------------===// - -multiclass xtype_imm_base<string OpcStr1, string OpcStr2, SDNode OpNode1, - SDNode OpNode2, bits<3> majOp, bits<2> minOp > { - def _i_r#NAME : T_shift_imm_acc_r< OpcStr1, OpcStr2, OpNode1, - OpNode2, majOp, minOp >; - def _i_p#NAME : T_shift_imm_acc_p< OpcStr1, OpcStr2, OpNode1, - OpNode2, majOp, minOp >; -} - -multiclass xtype_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> { - let AddedComplexity = 100 in - defm _acc : xtype_imm_base< opc1, "+= ", OpNode, add, 0b001, minOp>; - - defm _nac : xtype_imm_base< opc1, "-= ", OpNode, sub, 0b000, minOp>; - defm _and : xtype_imm_base< opc1, "&= ", OpNode, and, 0b010, minOp>; - defm _or : xtype_imm_base< opc1, "|= ", OpNode, or, 0b011, minOp>; -} - -multiclass xtype_xor_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> { -let AddedComplexity = 100 in - defm _xacc : xtype_imm_base< opc1, "^= ", OpNode, xor, 0b100, minOp>; -} - -defm S2_asr : xtype_imm_acc<"asr", sra, 0b00>; - -defm S2_lsr : xtype_imm_acc<"lsr", srl, 0b01>, - xtype_xor_imm_acc<"lsr", srl, 0b01>; - -defm S2_asl : xtype_imm_acc<"asl", shl, 0b10>, - xtype_xor_imm_acc<"asl", shl, 0b10>; - -multiclass xtype_reg_acc_r<string opc1, SDNode OpNode, bits<2>minOp> { - let AddedComplexity = 100 in - def _acc : T_shift_reg_acc_r <opc1, "+= ", OpNode, add, 0b11, minOp>; - - def _nac : T_shift_reg_acc_r <opc1, "-= ", OpNode, sub, 0b10, minOp>; - def _and : T_shift_reg_acc_r <opc1, "&= ", OpNode, and, 0b01, minOp>; - def _or : T_shift_reg_acc_r <opc1, "|= ", OpNode, or, 0b00, minOp>; -} - -multiclass xtype_reg_acc_p<string opc1, SDNode OpNode, bits<2>minOp> { - let AddedComplexity = 100 in - def _acc : T_shift_reg_acc_p <opc1, "+= ", OpNode, add, 0b110, minOp>; - - def _nac : T_shift_reg_acc_p <opc1, "-= ", OpNode, sub, 0b100, minOp>; - def _and : T_shift_reg_acc_p <opc1, "&= ", OpNode, and, 0b010, minOp>; - def _or : T_shift_reg_acc_p <opc1, "|= ", OpNode, or, 0b000, minOp>; - def _xor : T_shift_reg_acc_p <opc1, "^= ", OpNode, xor, 0b011, minOp>; -} - -multiclass xtype_reg_acc<string OpcStr, SDNode OpNode, bits<2> minOp > { - defm _r_r : xtype_reg_acc_r <OpcStr, OpNode, minOp>; - defm _r_p : xtype_reg_acc_p <OpcStr, OpNode, minOp>; -} - -defm S2_asl : xtype_reg_acc<"asl", shl, 0b10>; -defm S2_asr : xtype_reg_acc<"asr", sra, 0b00>; -defm S2_lsr : xtype_reg_acc<"lsr", srl, 0b01>; -defm S2_lsl : xtype_reg_acc<"lsl", shl, 0b11>; - -//===----------------------------------------------------------------------===// -let hasSideEffects = 0 in -class T_S3op_1 <string mnemonic, RegisterClass RC, bits<2> MajOp, bits<3> MinOp, - bit SwapOps, bit isSat = 0, bit isRnd = 0, bit hasShift = 0> - : SInst <(outs RC:$dst), - (ins DoubleRegs:$src1, DoubleRegs:$src2), - "$dst = "#mnemonic#"($src1, $src2)"#!if(isRnd, ":rnd", "") - #!if(hasShift,":>>1","") - #!if(isSat, ":sat", ""), - [], "", S_3op_tc_2_SLOT23 > { - bits<5> dst; - bits<5> src1; - bits<5> src2; - - let IClass = 0b1100; - - let Inst{27-24} = 0b0001; - let Inst{23-22} = MajOp; - let Inst{20-16} = !if (SwapOps, src2, src1); - let Inst{12-8} = !if (SwapOps, src1, src2); - let Inst{7-5} = MinOp; - let Inst{4-0} = dst; - } - -class T_S3op_64 <string mnemonic, bits<2> MajOp, bits<3> MinOp, bit SwapOps, - bit isSat = 0, bit isRnd = 0, bit hasShift = 0 > - : T_S3op_1 <mnemonic, DoubleRegs, MajOp, MinOp, SwapOps, - isSat, isRnd, hasShift>; - -let Itinerary = S_3op_tc_1_SLOT23 in { - def S2_shuffeb : T_S3op_64 < "shuffeb", 0b00, 0b010, 0>; - def S2_shuffeh : T_S3op_64 < "shuffeh", 0b00, 0b110, 0>; - def S2_shuffob : T_S3op_64 < "shuffob", 0b00, 0b100, 1>; - def S2_shuffoh : T_S3op_64 < "shuffoh", 0b10, 0b000, 1>; - - def S2_vtrunewh : T_S3op_64 < "vtrunewh", 0b10, 0b010, 0>; - def S2_vtrunowh : T_S3op_64 < "vtrunowh", 0b10, 0b100, 0>; -} - -def S2_lfsp : T_S3op_64 < "lfs", 0b10, 0b110, 0>; - -let hasSideEffects = 0 in -class T_S3op_2 <string mnemonic, bits<3> MajOp, bit SwapOps> - : SInst < (outs DoubleRegs:$Rdd), - (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu), - "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu)", - [], "", S_3op_tc_1_SLOT23 > { - bits<5> Rdd; - bits<5> Rss; - bits<5> Rtt; - bits<2> Pu; - - let IClass = 0b1100; - - let Inst{27-24} = 0b0010; - let Inst{23-21} = MajOp; - let Inst{20-16} = !if (SwapOps, Rtt, Rss); - let Inst{12-8} = !if (SwapOps, Rss, Rtt); - let Inst{6-5} = Pu; - let Inst{4-0} = Rdd; - } - -def S2_valignrb : T_S3op_2 < "valignb", 0b000, 1>; -def S2_vsplicerb : T_S3op_2 < "vspliceb", 0b100, 0>; - -//===----------------------------------------------------------------------===// -// Template class used by vector shift, vector rotate, vector neg, -// 32-bit shift, 64-bit shifts, etc. -//===----------------------------------------------------------------------===// - -let hasSideEffects = 0 in -class T_S3op_3 <string mnemonic, RegisterClass RC, bits<2> MajOp, - bits<2> MinOp, bit isSat = 0, list<dag> pattern = [] > - : SInst <(outs RC:$dst), - (ins RC:$src1, IntRegs:$src2), - "$dst = "#mnemonic#"($src1, $src2)"#!if(isSat, ":sat", ""), - pattern, "", S_3op_tc_1_SLOT23> { - bits<5> dst; - bits<5> src1; - bits<5> src2; - - let IClass = 0b1100; - - let Inst{27-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b0110, 0b0011); - let Inst{23-22} = MajOp; - let Inst{20-16} = src1; - let Inst{12-8} = src2; - let Inst{7-6} = MinOp; - let Inst{4-0} = dst; - } - -let hasNewValue = 1 in -class T_S3op_shift32 <string mnemonic, SDNode OpNode, bits<2> MinOp> - : T_S3op_3 <mnemonic, IntRegs, 0b01, MinOp, 0, []>; - -let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in -class T_S3op_shift32_Sat <string mnemonic, bits<2> MinOp> - : T_S3op_3 <mnemonic, IntRegs, 0b00, MinOp, 1, []>; - - -class T_S3op_shift64 <string mnemonic, SDNode OpNode, bits<2> MinOp> - : T_S3op_3 <mnemonic, DoubleRegs, 0b10, MinOp, 0, []>; - - -class T_S3op_shiftVect <string mnemonic, bits<2> MajOp, bits<2> MinOp> - : T_S3op_3 <mnemonic, DoubleRegs, MajOp, MinOp, 0, []>; - - -// Shift by register -// Rdd=[asr|lsr|asl|lsl](Rss,Rt) - -def S2_asr_r_p : T_S3op_shift64 < "asr", sra, 0b00>; -def S2_lsr_r_p : T_S3op_shift64 < "lsr", srl, 0b01>; -def S2_asl_r_p : T_S3op_shift64 < "asl", shl, 0b10>; -def S2_lsl_r_p : T_S3op_shift64 < "lsl", shl, 0b11>; - -// Rd=[asr|lsr|asl|lsl](Rs,Rt) - -def S2_asr_r_r : T_S3op_shift32<"asr", sra, 0b00>; -def S2_lsr_r_r : T_S3op_shift32<"lsr", srl, 0b01>; -def S2_asl_r_r : T_S3op_shift32<"asl", shl, 0b10>; -def S2_lsl_r_r : T_S3op_shift32<"lsl", shl, 0b11>; - -// Shift by register with saturation -// Rd=asr(Rs,Rt):sat -// Rd=asl(Rs,Rt):sat - -let Defs = [USR_OVF] in { - def S2_asr_r_r_sat : T_S3op_shift32_Sat<"asr", 0b00>; - def S2_asl_r_r_sat : T_S3op_shift32_Sat<"asl", 0b10>; -} - -let hasNewValue = 1, hasSideEffects = 0 in -class T_S3op_8 <string opc, bits<3> MinOp, bit isSat, bit isRnd, bit hasShift, bit hasSplat = 0> - : SInst < (outs IntRegs:$Rd), - (ins DoubleRegs:$Rss, IntRegs:$Rt), - "$Rd = "#opc#"($Rss, $Rt"#!if(hasSplat, "*", "")#")" - #!if(hasShift, ":<<1", "") - #!if(isRnd, ":rnd", "") - #!if(isSat, ":sat", ""), - [], "", S_3op_tc_1_SLOT23 > { - bits<5> Rd; - bits<5> Rss; - bits<5> Rt; - - let IClass = 0b1100; - - let Inst{27-24} = 0b0101; - let Inst{20-16} = Rss; - let Inst{12-8} = Rt; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rd; - } - -def S2_asr_r_svw_trun : T_S3op_8<"vasrw", 0b010, 0, 0, 0>; - -let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in -def S2_vcrotate : T_S3op_shiftVect < "vcrotate", 0b11, 0b00>; - -let hasSideEffects = 0 in -class T_S3op_7 <string mnemonic, bit MajOp > - : SInst <(outs DoubleRegs:$Rdd), - (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, u3_0Imm:$u3), - "$Rdd = "#mnemonic#"($Rss, $Rtt, #$u3)" , - [], "", S_3op_tc_1_SLOT23 > { - bits<5> Rdd; - bits<5> Rss; - bits<5> Rtt; - bits<3> u3; - - let IClass = 0b1100; - - let Inst{27-24} = 0b0000; - let Inst{23} = MajOp; - let Inst{20-16} = !if(MajOp, Rss, Rtt); - let Inst{12-8} = !if(MajOp, Rtt, Rss); - let Inst{7-5} = u3; - let Inst{4-0} = Rdd; - } - -def S2_valignib : T_S3op_7 < "valignb", 0>; -def S2_vspliceib : T_S3op_7 < "vspliceb", 1>; - -//===----------------------------------------------------------------------===// -// Template class for 'insert bitfield' instructions -//===----------------------------------------------------------------------===// -let hasSideEffects = 0 in -class T_S3op_insert <string mnemonic, RegisterClass RC> - : SInst <(outs RC:$dst), - (ins RC:$src1, RC:$src2, DoubleRegs:$src3), - "$dst = "#mnemonic#"($src2, $src3)" , - [], "$src1 = $dst", S_3op_tc_1_SLOT23 > { - bits<5> dst; - bits<5> src2; - bits<5> src3; - - let IClass = 0b1100; - - let Inst{27-26} = 0b10; - let Inst{25-24} = !if(!eq(!cast<string>(RC), "IntRegs"), 0b00, 0b10); - let Inst{23} = 0b0; - let Inst{20-16} = src2; - let Inst{12-8} = src3; - let Inst{4-0} = dst; - } - -let hasSideEffects = 0 in -class T_S2op_insert <bits<4> RegTyBits, RegisterClass RC, Operand ImmOp> - : SInst <(outs RC:$dst), (ins RC:$dst2, RC:$src1, ImmOp:$src2, ImmOp:$src3), - "$dst = insert($src1, #$src2, #$src3)", - [], "$dst2 = $dst", S_2op_tc_2_SLOT23> { - bits<5> dst; - bits<5> src1; - bits<6> src2; - bits<6> src3; - bit bit23; - bit bit13; - string ImmOpStr = !cast<string>(ImmOp); - - let bit23 = !if (!eq(ImmOpStr, "u6_0Imm"), src3{5}, 0); - let bit13 = !if (!eq(ImmOpStr, "u6_0Imm"), src2{5}, 0); - - let IClass = 0b1000; - - let Inst{27-24} = RegTyBits; - let Inst{23} = bit23; - let Inst{22-21} = src3{4-3}; - let Inst{20-16} = src1; - let Inst{13} = bit13; - let Inst{12-8} = src2{4-0}; - let Inst{7-5} = src3{2-0}; - let Inst{4-0} = dst; - } - -// Rx=insert(Rs,Rtt) -// Rx=insert(Rs,#u5,#U5) -let hasNewValue = 1 in { - def S2_insert_rp : T_S3op_insert <"insert", IntRegs>; - def S2_insert : T_S2op_insert <0b1111, IntRegs, u5_0Imm>; -} - -// Rxx=insert(Rss,Rtt) -// Rxx=insert(Rss,#u6,#U6) -def S2_insertp_rp : T_S3op_insert<"insert", DoubleRegs>; -def S2_insertp : T_S2op_insert <0b0011, DoubleRegs, u6_0Imm>; - - -//===----------------------------------------------------------------------===// -// Template class for 'extract bitfield' instructions -//===----------------------------------------------------------------------===// -let hasNewValue = 1, hasSideEffects = 0 in -class T_S3op_extract <string mnemonic, bits<2> MinOp> - : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs, DoubleRegs:$Rtt), - "$Rd = "#mnemonic#"($Rs, $Rtt)", - [], "", S_3op_tc_2_SLOT23 > { - bits<5> Rd; - bits<5> Rs; - bits<5> Rtt; - - let IClass = 0b1100; - - let Inst{27-22} = 0b100100; - let Inst{20-16} = Rs; - let Inst{12-8} = Rtt; - let Inst{7-6} = MinOp; - let Inst{4-0} = Rd; - } - -let hasSideEffects = 0 in -class T_S2op_extract <string mnemonic, bits<4> RegTyBits, - RegisterClass RC, Operand ImmOp> - : SInst <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2, ImmOp:$src3), - "$dst = "#mnemonic#"($src1, #$src2, #$src3)", - [], "", S_2op_tc_2_SLOT23> { - bits<5> dst; - bits<5> src1; - bits<6> src2; - bits<6> src3; - bit bit23; - bit bit13; - string ImmOpStr = !cast<string>(ImmOp); - - let bit23 = !if (!eq(ImmOpStr, "u6_0Imm"), src3{5}, - !if (!eq(mnemonic, "extractu"), 0, 1)); - - let bit13 = !if (!eq(ImmOpStr, "u6_0Imm"), src2{5}, 0); - - let IClass = 0b1000; - - let Inst{27-24} = RegTyBits; - let Inst{23} = bit23; - let Inst{22-21} = src3{4-3}; - let Inst{20-16} = src1; - let Inst{13} = bit13; - let Inst{12-8} = src2{4-0}; - let Inst{7-5} = src3{2-0}; - let Inst{4-0} = dst; - } - -// Extract bitfield - -// Rdd=extractu(Rss,Rtt) -// Rdd=extractu(Rss,#u6,#U6) -def S2_extractup_rp : T_S3op_64 < "extractu", 0b00, 0b000, 0>; -def S2_extractup : T_S2op_extract <"extractu", 0b0001, DoubleRegs, u6_0Imm>; - -// Rd=extractu(Rs,Rtt) -// Rd=extractu(Rs,#u5,#U5) -let hasNewValue = 1 in { - def S2_extractu_rp : T_S3op_extract<"extractu", 0b00>; - def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5_0Imm>; -} - -//===----------------------------------------------------------------------===// -// :raw for of tableindx[bdhw] insns -//===----------------------------------------------------------------------===// - -let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -class tableidxRaw<string OpStr, bits<2>MinOp> - : SInst <(outs IntRegs:$Rx), - (ins IntRegs:$_dst_, IntRegs:$Rs, u4_0Imm:$u4, s6_0Imm:$S6), - "$Rx = "#OpStr#"($Rs, #$u4, #$S6):raw", - [], "$Rx = $_dst_" > { - bits<5> Rx; - bits<5> Rs; - bits<4> u4; - bits<6> S6; - - let IClass = 0b1000; - - let Inst{27-24} = 0b0111; - let Inst{23-22} = MinOp; - let Inst{21} = u4{3}; - let Inst{20-16} = Rs; - let Inst{13-8} = S6; - let Inst{7-5} = u4{2-0}; - let Inst{4-0} = Rx; - } - -def S2_tableidxb : tableidxRaw<"tableidxb", 0b00>; -def S2_tableidxh : tableidxRaw<"tableidxh", 0b01>; -def S2_tableidxw : tableidxRaw<"tableidxw", 0b10>; -def S2_tableidxd : tableidxRaw<"tableidxd", 0b11>; - -//===----------------------------------------------------------------------===// -// Template class for 'table index' instructions which are assembler mapped -// to their :raw format. -//===----------------------------------------------------------------------===// -let isPseudo = 1 in -class tableidx_goodsyntax <string mnemonic> - : SInst <(outs IntRegs:$Rx), - (ins IntRegs:$_dst_, IntRegs:$Rs, u4_0Imm:$u4, u5_0Imm:$u5), - "$Rx = "#mnemonic#"($Rs, #$u4, #$u5)", - [], "$Rx = $_dst_" >; - -def S2_tableidxb_goodsyntax : tableidx_goodsyntax<"tableidxb">; -def S2_tableidxh_goodsyntax : tableidx_goodsyntax<"tableidxh">; -def S2_tableidxw_goodsyntax : tableidx_goodsyntax<"tableidxw">; -def S2_tableidxd_goodsyntax : tableidx_goodsyntax<"tableidxd">; - -//===----------------------------------------------------------------------===// -// V3 Instructions + -//===----------------------------------------------------------------------===// - -include "HexagonInstrInfoV3.td" - -//===----------------------------------------------------------------------===// -// V3 Instructions - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// V4 Instructions + -//===----------------------------------------------------------------------===// - -include "HexagonInstrInfoV4.td" - -//===----------------------------------------------------------------------===// -// V4 Instructions - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// V5 Instructions + -//===----------------------------------------------------------------------===// - -include "HexagonInstrInfoV5.td" - -//===----------------------------------------------------------------------===// -// V5 Instructions - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// V60 Instructions + -//===----------------------------------------------------------------------===// - -include "HexagonInstrInfoV60.td" - -//===----------------------------------------------------------------------===// -// V60 Instructions - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// ALU32/64/Vector + -//===----------------------------------------------------------------------===/// - -include "HexagonInstrInfoVector.td" - -include "HexagonInstrAlias.td" -include "HexagonSystemInst.td" - diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfoV3.td b/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfoV3.td deleted file mode 100644 index 225f94405076..000000000000 --- a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfoV3.td +++ /dev/null @@ -1,215 +0,0 @@ -//=- HexagonInstrInfoV3.td - Target Desc. for Hexagon Target -*- tablegen -*-=// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon V3 instructions in TableGen format. -// -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// J + -//===----------------------------------------------------------------------===// -// Call subroutine. -let isCall = 1, hasSideEffects = 1, isPredicable = 1, - isExtended = 0, isExtendable = 1, opExtendable = 0, - isExtentSigned = 1, opExtentBits = 24, opExtentAlign = 2 in -class T_Call<bit CSR, string ExtStr> - : JInst<(outs), (ins calltarget:$dst), - "call " # ExtStr # "$dst", [], "", J_tc_2early_SLOT23> { - let BaseOpcode = "call"; - bits<24> dst; - - let Defs = !if (CSR, VolatileV3.Regs, []); - let IClass = 0b0101; - let Inst{27-25} = 0b101; - let Inst{24-16,13-1} = dst{23-2}; - let Inst{0} = 0b0; -} - -let isCall = 1, hasSideEffects = 1, isPredicated = 1, - isExtended = 0, isExtendable = 1, opExtendable = 1, - isExtentSigned = 1, opExtentBits = 17, opExtentAlign = 2 in -class T_CallPred<bit CSR, bit IfTrue, string ExtStr> - : JInst<(outs), (ins PredRegs:$Pu, calltarget:$dst), - CondStr<"$Pu", IfTrue, 0>.S # "call " # ExtStr # "$dst", - [], "", J_tc_2early_SLOT23> { - let BaseOpcode = "call"; - let isPredicatedFalse = !if(IfTrue,0,1); - bits<2> Pu; - bits<17> dst; - - let Defs = !if (CSR, VolatileV3.Regs, []); - let IClass = 0b0101; - let Inst{27-24} = 0b1101; - let Inst{23-22,20-16,13,7-1} = dst{16-2}; - let Inst{21} = !if(IfTrue,0,1); - let Inst{11} = 0b0; - let Inst{9-8} = Pu; -} - -multiclass T_Calls<bit CSR, string ExtStr> { - def NAME : T_Call<CSR, ExtStr>; - def t : T_CallPred<CSR, 1, ExtStr>; - def f : T_CallPred<CSR, 0, ExtStr>; -} - -defm J2_call: T_Calls<1, "">, PredRel; - -let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, - Defs = VolatileV3.Regs in -def PS_call_nr : T_Call<1, "">, PredRel; - -let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, - Defs = [PC, R31, R6, R7, P0] in -def PS_call_stk : T_Call<0, "">, PredRel; - -//===----------------------------------------------------------------------===// -// J - -//===----------------------------------------------------------------------===// - - -//===----------------------------------------------------------------------===// -// JR + -//===----------------------------------------------------------------------===// -// Call subroutine from register. - -let isCodeGenOnly = 1, Defs = VolatileV3.Regs in { - def PS_callr_nr : JUMPR_MISC_CALLR<0, 1>; // Call, no return. -} - -//===----------------------------------------------------------------------===// -// JR - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// ALU64/ALU + -//===----------------------------------------------------------------------===// - -let Defs = [USR_OVF], Itinerary = ALU64_tc_2_SLOT23 in -def A2_addpsat : T_ALU64_arith<"add", 0b011, 0b101, 1, 0, 1>; - -class T_ALU64_addsp_hl<string suffix, bits<3> MinOp> - : T_ALU64_rr<"add", suffix, 0b0011, 0b011, MinOp, 0, 0, "">; - -def A2_addspl : T_ALU64_addsp_hl<":raw:lo", 0b110>; -def A2_addsph : T_ALU64_addsp_hl<":raw:hi", 0b111>; - -let hasSideEffects = 0, isAsmParserOnly = 1 in -def A2_addsp : ALU64_rr<(outs DoubleRegs:$Rd), - (ins IntRegs:$Rs, DoubleRegs:$Rt), "$Rd = add($Rs, $Rt)", [], - "", ALU64_tc_1_SLOT23>; - - -let hasSideEffects = 0 in -class T_XTYPE_MIN_MAX_P<bit isMax, bit isUnsigned> - : ALU64Inst<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rt, DoubleRegs:$Rs), - "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","") - #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - - let Inst{27-23} = 0b00111; - let Inst{22-21} = !if(isMax, 0b10, 0b01); - let Inst{20-16} = !if(isMax, Rt, Rs); - let Inst{12-8} = !if(isMax, Rs, Rt); - let Inst{7} = 0b1; - let Inst{6} = !if(isMax, 0b0, 0b1); - let Inst{5} = isUnsigned; - let Inst{4-0} = Rd; -} - -def A2_minp : T_XTYPE_MIN_MAX_P<0, 0>; -def A2_minup : T_XTYPE_MIN_MAX_P<0, 1>; -def A2_maxp : T_XTYPE_MIN_MAX_P<1, 0>; -def A2_maxup : T_XTYPE_MIN_MAX_P<1, 1>; - -//===----------------------------------------------------------------------===// -// ALU64/ALU - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// :raw form of vrcmpys:hi/lo insns -//===----------------------------------------------------------------------===// -// Vector reduce complex multiply by scalar. -let Defs = [USR_OVF], hasSideEffects = 0 in -class T_vrcmpRaw<string HiLo, bits<3>MajOp>: - MInst<(outs DoubleRegs:$Rdd), - (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Rdd = vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, []> { - bits<5> Rdd; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1000; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - let Inst{7-5} = 0b100; - let Inst{4-0} = Rdd; -} - -def M2_vrcmpys_s1_h: T_vrcmpRaw<"hi", 0b101>; -def M2_vrcmpys_s1_l: T_vrcmpRaw<"lo", 0b111>; - -// Assembler mapped to M2_vrcmpys_s1_h or M2_vrcmpys_s1_l -let hasSideEffects = 0, isAsmParserOnly = 1 in -def M2_vrcmpys_s1 - : MInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, IntRegs:$Rt), - "$Rdd=vrcmpys($Rss,$Rt):<<1:sat">; - -// Vector reduce complex multiply by scalar with accumulation. -let Defs = [USR_OVF], hasSideEffects = 0 in -class T_vrcmpys_acc<string HiLo, bits<3>MajOp>: - MInst <(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$_src_, DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Rxx += vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, [], - "$Rxx = $_src_"> { - bits<5> Rxx; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1010; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - let Inst{7-5} = 0b100; - let Inst{4-0} = Rxx; - } - -def M2_vrcmpys_acc_s1_h: T_vrcmpys_acc<"hi", 0b101>; -def M2_vrcmpys_acc_s1_l: T_vrcmpys_acc<"lo", 0b111>; - -// Assembler mapped to M2_vrcmpys_acc_s1_h or M2_vrcmpys_acc_s1_l - -let isAsmParserOnly = 1 in -def M2_vrcmpys_acc_s1 - : MInst <(outs DoubleRegs:$dst), - (ins DoubleRegs:$dst2, DoubleRegs:$src1, IntRegs:$src2), - "$dst += vrcmpys($src1, $src2):<<1:sat", [], - "$dst2 = $dst">; - -def M2_vrcmpys_s1rp_h : T_MType_vrcmpy <"vrcmpys", 0b101, 0b110, 1>; -def M2_vrcmpys_s1rp_l : T_MType_vrcmpy <"vrcmpys", 0b101, 0b111, 0>; - -// Assembler mapped to M2_vrcmpys_s1rp_h or M2_vrcmpys_s1rp_l -let isAsmParserOnly = 1 in -def M2_vrcmpys_s1rp - : MInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, IntRegs:$Rt), - "$Rd=vrcmpys($Rss,$Rt):<<1:rnd:sat">; - - -// S2_cabacdecbin: Cabac decode bin. -let Defs = [P0], isPredicateLate = 1, Itinerary = S_3op_tc_1_SLOT23 in -def S2_cabacdecbin : T_S3op_64 < "decbin", 0b11, 0b110, 0>; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td b/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td deleted file mode 100644 index 18943a082d28..000000000000 --- a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ /dev/null @@ -1,3301 +0,0 @@ -//=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon V4 instructions in TableGen format. -// -//===----------------------------------------------------------------------===// - -def DuplexIClass0: InstDuplex < 0 >; -def DuplexIClass1: InstDuplex < 1 >; -def DuplexIClass2: InstDuplex < 2 >; -let isExtendable = 1 in { - def DuplexIClass3: InstDuplex < 3 >; - def DuplexIClass4: InstDuplex < 4 >; - def DuplexIClass5: InstDuplex < 5 >; - def DuplexIClass6: InstDuplex < 6 >; - def DuplexIClass7: InstDuplex < 7 >; -} -def DuplexIClass8: InstDuplex < 8 >; -def DuplexIClass9: InstDuplex < 9 >; -def DuplexIClassA: InstDuplex < 0xA >; -def DuplexIClassB: InstDuplex < 0xB >; -def DuplexIClassC: InstDuplex < 0xC >; -def DuplexIClassD: InstDuplex < 0xD >; -def DuplexIClassE: InstDuplex < 0xE >; -def DuplexIClassF: InstDuplex < 0xF >; - -let hasSideEffects = 0 in -class T_Immext<Operand ImmType> - : EXTENDERInst<(outs), (ins ImmType:$imm), - "immext(#$imm)", []> { - bits<32> imm; - let IClass = 0b0000; - - let Inst{27-16} = imm{31-20}; - let Inst{13-0} = imm{19-6}; - } - -def A4_ext : T_Immext<u26_6Imm>; -let isCodeGenOnly = 1 in { - let isBranch = 1 in - def A4_ext_b : T_Immext<brtarget>; - let isCall = 1 in - def A4_ext_c : T_Immext<calltarget>; - def A4_ext_g : T_Immext<globaladdress>; -} - -// Hexagon V4 Architecture spec defines 8 instruction classes: -// LD ST ALU32 XTYPE J JR MEMOP NV CR SYSTEM(system is not implemented in the -// compiler) - -// LD Instructions: -// ======================================== -// Loads (8/16/32/64 bit) -// Deallocframe - -// ST Instructions: -// ======================================== -// Stores (8/16/32/64 bit) -// Allocframe - -// ALU32 Instructions: -// ======================================== -// Arithmetic / Logical (32 bit) -// Vector Halfword - -// XTYPE Instructions (32/64 bit): -// ======================================== -// Arithmetic, Logical, Bit Manipulation -// Multiply (Integer, Fractional, Complex) -// Permute / Vector Permute Operations -// Predicate Operations -// Shift / Shift with Add/Sub/Logical -// Vector Byte ALU -// Vector Halfword (ALU, Shift, Multiply) -// Vector Word (ALU, Shift) - -// J Instructions: -// ======================================== -// Jump/Call PC-relative - -// JR Instructions: -// ======================================== -// Jump/Call Register - -// MEMOP Instructions: -// ======================================== -// Operation on memory (8/16/32 bit) - -// NV Instructions: -// ======================================== -// New-value Jumps -// New-value Stores - -// CR Instructions: -// ======================================== -// Control-Register Transfers -// Hardware Loop Setup -// Predicate Logicals & Reductions - -// SYSTEM Instructions (not implemented in the compiler): -// ======================================== -// Prefetch -// Cache Maintenance -// Bus Operations - - -//===----------------------------------------------------------------------===// -// ALU32 + -//===----------------------------------------------------------------------===// - -class T_ALU32_3op_not<string mnemonic, bits<3> MajOp, bits<3> MinOp, - bit OpsRev> - : T_ALU32_3op<mnemonic, MajOp, MinOp, OpsRev, 0> { - let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)"; -} - -let BaseOpcode = "andn_rr", CextOpcode = "andn" in -def A4_andn : T_ALU32_3op_not<"and", 0b001, 0b100, 1>; -let BaseOpcode = "orn_rr", CextOpcode = "orn" in -def A4_orn : T_ALU32_3op_not<"or", 0b001, 0b101, 1>; - -let CextOpcode = "rcmp.eq" in -def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>; -let CextOpcode = "!rcmp.eq" in -def A4_rcmpneq : T_ALU32_3op<"!cmp.eq", 0b011, 0b011, 0, 1>; - -def C4_cmpneq : T_ALU32_3op_cmp<"!cmp.eq", 0b00, 1, 1>; -def C4_cmplte : T_ALU32_3op_cmp<"!cmp.gt", 0b10, 1, 0>; -def C4_cmplteu : T_ALU32_3op_cmp<"!cmp.gtu", 0b11, 1, 0>; - -class T_CMP_rrbh<string mnemonic, bits<3> MinOp, bit IsComm> - : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>, - ImmRegRel { - let InputType = "reg"; - let CextOpcode = mnemonic; - let isCompare = 1; - let isCommutable = IsComm; - let hasSideEffects = 0; - - bits<2> Pd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1100; - let Inst{27-21} = 0b0111110; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{7-5} = MinOp; - let Inst{1-0} = Pd; -} - -def A4_cmpbeq : T_CMP_rrbh<"cmpb.eq", 0b110, 1>; -def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>; -def A4_cmpbgtu : T_CMP_rrbh<"cmpb.gtu", 0b111, 0>; -def A4_cmpheq : T_CMP_rrbh<"cmph.eq", 0b011, 1>; -def A4_cmphgt : T_CMP_rrbh<"cmph.gt", 0b100, 0>; -def A4_cmphgtu : T_CMP_rrbh<"cmph.gtu", 0b101, 0>; - -class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm, - Operand ImmType, bit IsImmExt, bit IsImmSigned, int ImmBits> - : ALU64Inst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, ImmType:$Imm), - "$Pd = "#mnemonic#"($Rs, #$Imm)", [], "", ALU64_tc_2early_SLOT23>, - ImmRegRel { - let InputType = "imm"; - let CextOpcode = mnemonic; - let isCompare = 1; - let isCommutable = IsComm; - let hasSideEffects = 0; - let isExtendable = IsImmExt; - let opExtendable = !if (IsImmExt, 2, 0); - let isExtentSigned = IsImmSigned; - let opExtentBits = ImmBits; - - bits<2> Pd; - bits<5> Rs; - bits<8> Imm; - - let IClass = 0b1101; - let Inst{27-24} = 0b1101; - let Inst{22-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{12-5} = Imm; - let Inst{4} = 0b0; - let Inst{3} = IsHalf; - let Inst{1-0} = Pd; -} - -def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8_0Imm, 0, 0, 8>; -def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8_0Imm, 0, 1, 8>; -def A4_cmpbgtui : T_CMP_ribh<"cmpb.gtu", 0b10, 0, 0, u7_0Ext, 1, 0, 7>; -def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8_0Ext, 1, 1, 8>; -def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8_0Ext, 1, 1, 8>; -def A4_cmphgtui : T_CMP_ribh<"cmph.gtu", 0b10, 1, 0, u7_0Ext, 1, 0, 7>; - -class T_RCMP_EQ_ri<string mnemonic, bit IsNeg> - : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8_0Ext:$s8), - "$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>, - ImmRegRel { - let InputType = "imm"; - let CextOpcode = !if (IsNeg, "!rcmp.eq", "rcmp.eq"); - let isExtendable = 1; - let opExtendable = 2; - let isExtentSigned = 1; - let opExtentBits = 8; - let hasNewValue = 1; - - bits<5> Rd; - bits<5> Rs; - bits<8> s8; - - let IClass = 0b0111; - let Inst{27-24} = 0b0011; - let Inst{22} = 0b1; - let Inst{21} = IsNeg; - let Inst{20-16} = Rs; - let Inst{13} = 0b1; - let Inst{12-5} = s8; - let Inst{4-0} = Rd; -} - -def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>; -def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>; - -//===----------------------------------------------------------------------===// -// ALU32 - -//===----------------------------------------------------------------------===// - - -//===----------------------------------------------------------------------===// -// ALU32/PERM + -//===----------------------------------------------------------------------===// - -// Combine a word and an immediate into a register pair. -let hasSideEffects = 0, isExtentSigned = 1, isExtendable = 1, - opExtentBits = 8 in -class T_Combine1 <bits<2> MajOp, dag ins, string AsmStr> - : ALU32Inst <(outs DoubleRegs:$Rdd), ins, AsmStr> { - bits<5> Rdd; - bits<5> Rs; - bits<8> s8; - - let IClass = 0b0111; - let Inst{27-24} = 0b0011; - let Inst{22-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{13} = 0b1; - let Inst{12-5} = s8; - let Inst{4-0} = Rdd; - } - -let opExtendable = 2 in -def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8_0Ext:$s8), - "$Rdd = combine($Rs, #$s8)">; - -let opExtendable = 1 in -def A4_combineir : T_Combine1<0b01, (ins s8_0Ext:$s8, IntRegs:$Rs), - "$Rdd = combine(#$s8, $Rs)">; - -// A4_combineii: Set two small immediates. -let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in -def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8_0Imm:$s8, u6_0Ext:$U6), - "$Rdd = combine(#$s8, #$U6)"> { - bits<5> Rdd; - bits<8> s8; - bits<6> U6; - - let IClass = 0b0111; - let Inst{27-23} = 0b11001; - let Inst{20-16} = U6{5-1}; - let Inst{13} = U6{0}; - let Inst{12-5} = s8; - let Inst{4-0} = Rdd; - } - -//===----------------------------------------------------------------------===// -// ALU32/PERM - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// LD + -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// Template class for load instructions with Absolute set addressing mode. -//===----------------------------------------------------------------------===// -let isExtended = 1, opExtendable = 2, opExtentBits = 6, addrMode = AbsoluteSet, - hasSideEffects = 0 in -class T_LD_abs_set<string mnemonic, RegisterClass RC, bits<4>MajOp>: - LDInst<(outs RC:$dst1, IntRegs:$dst2), - (ins u6_0Ext:$addr), - "$dst1 = "#mnemonic#"($dst2 = #$addr)", - []> { - bits<7> name; - bits<5> dst1; - bits<5> dst2; - bits<6> addr; - - let IClass = 0b1001; - let Inst{27-25} = 0b101; - let Inst{24-21} = MajOp; - let Inst{13-12} = 0b01; - let Inst{4-0} = dst1; - let Inst{20-16} = dst2; - let Inst{11-8} = addr{5-2}; - let Inst{6-5} = addr{1-0}; -} - -let accessSize = ByteAccess, hasNewValue = 1 in { - def L4_loadrb_ap : T_LD_abs_set <"memb", IntRegs, 0b1000>; - def L4_loadrub_ap : T_LD_abs_set <"memub", IntRegs, 0b1001>; -} - -let accessSize = HalfWordAccess, hasNewValue = 1 in { - def L4_loadrh_ap : T_LD_abs_set <"memh", IntRegs, 0b1010>; - def L4_loadruh_ap : T_LD_abs_set <"memuh", IntRegs, 0b1011>; - def L4_loadbsw2_ap : T_LD_abs_set <"membh", IntRegs, 0b0001>; - def L4_loadbzw2_ap : T_LD_abs_set <"memubh", IntRegs, 0b0011>; -} - -let accessSize = WordAccess, hasNewValue = 1 in - def L4_loadri_ap : T_LD_abs_set <"memw", IntRegs, 0b1100>; - -let accessSize = WordAccess in { - def L4_loadbzw4_ap : T_LD_abs_set <"memubh", DoubleRegs, 0b0101>; - def L4_loadbsw4_ap : T_LD_abs_set <"membh", DoubleRegs, 0b0111>; -} - -let accessSize = DoubleWordAccess in -def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>; - -let accessSize = ByteAccess in - def L4_loadalignb_ap : T_LD_abs_set <"memb_fifo", DoubleRegs, 0b0100>; - -let accessSize = HalfWordAccess in -def L4_loadalignh_ap : T_LD_abs_set <"memh_fifo", DoubleRegs, 0b0010>; - -// Load - Indirect with long offset -let InputType = "imm", addrMode = BaseLongOffset, isExtended = 1, -opExtentBits = 6, opExtendable = 3 in -class T_LoadAbsReg <string mnemonic, string CextOp, RegisterClass RC, - bits<4> MajOp> - : LDInst <(outs RC:$dst), (ins IntRegs:$src1, u2_0Imm:$src2, u6_0Ext:$src3), - "$dst = "#mnemonic#"($src1<<#$src2 + #$src3)", - [] >, ImmRegShl { - bits<5> dst; - bits<5> src1; - bits<2> src2; - bits<6> src3; - let CextOpcode = CextOp; - let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1); - - let IClass = 0b1001; - let Inst{27-25} = 0b110; - let Inst{24-21} = MajOp; - let Inst{20-16} = src1; - let Inst{13} = src2{1}; - let Inst{12} = 0b1; - let Inst{11-8} = src3{5-2}; - let Inst{7} = src2{0}; - let Inst{6-5} = src3{1-0}; - let Inst{4-0} = dst; - } - -let accessSize = ByteAccess in { - def L4_loadrb_ur : T_LoadAbsReg<"memb", "LDrib", IntRegs, 0b1000>; - def L4_loadrub_ur : T_LoadAbsReg<"memub", "LDriub", IntRegs, 0b1001>; - def L4_loadalignb_ur : T_LoadAbsReg<"memb_fifo", "LDrib_fifo", - DoubleRegs, 0b0100>; -} - -let accessSize = HalfWordAccess in { - def L4_loadrh_ur : T_LoadAbsReg<"memh", "LDrih", IntRegs, 0b1010>; - def L4_loadruh_ur : T_LoadAbsReg<"memuh", "LDriuh", IntRegs, 0b1011>; - def L4_loadbsw2_ur : T_LoadAbsReg<"membh", "LDribh2", IntRegs, 0b0001>; - def L4_loadbzw2_ur : T_LoadAbsReg<"memubh", "LDriubh2", IntRegs, 0b0011>; - def L4_loadalignh_ur : T_LoadAbsReg<"memh_fifo", "LDrih_fifo", - DoubleRegs, 0b0010>; -} - -let accessSize = WordAccess in { - def L4_loadri_ur : T_LoadAbsReg<"memw", "LDriw", IntRegs, 0b1100>; - def L4_loadbsw4_ur : T_LoadAbsReg<"membh", "LDribh4", DoubleRegs, 0b0111>; - def L4_loadbzw4_ur : T_LoadAbsReg<"memubh", "LDriubh4", DoubleRegs, 0b0101>; -} - -let accessSize = DoubleWordAccess in -def L4_loadrd_ur : T_LoadAbsReg<"memd", "LDrid", DoubleRegs, 0b1110>; - - -//===----------------------------------------------------------------------===// -// Template classes for the non-predicated load instructions with -// base + register offset addressing mode -//===----------------------------------------------------------------------===// -class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>: - LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2_0Imm:$u2), - "$dst = "#mnemonic#"($src1 + $src2<<#$u2)", - [], "", V4LDST_tc_ld_SLOT01>, ImmRegShl, AddrModeRel { - bits<5> dst; - bits<5> src1; - bits<5> src2; - bits<2> u2; - - let IClass = 0b0011; - - let Inst{27-24} = 0b1010; - let Inst{23-21} = MajOp; - let Inst{20-16} = src1; - let Inst{12-8} = src2; - let Inst{13} = u2{1}; - let Inst{7} = u2{0}; - let Inst{4-0} = dst; - } - -//===----------------------------------------------------------------------===// -// Template classes for the predicated load instructions with -// base + register offset addressing mode -//===----------------------------------------------------------------------===// -let isPredicated = 1 in -class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, - bit isNot, bit isPredNew>: - LDInst <(outs RC:$dst), - (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2_0Imm:$u2), - !if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)", - [], "", V4LDST_tc_ld_SLOT01>, AddrModeRel { - bits<5> dst; - bits<2> src1; - bits<5> src2; - bits<5> src3; - bits<2> u2; - - let isPredicatedFalse = isNot; - let isPredicatedNew = isPredNew; - - let IClass = 0b0011; - - let Inst{27-26} = 0b00; - let Inst{25} = isPredNew; - let Inst{24} = isNot; - let Inst{23-21} = MajOp; - let Inst{20-16} = src2; - let Inst{12-8} = src3; - let Inst{13} = u2{1}; - let Inst{7} = u2{0}; - let Inst{6-5} = src1; - let Inst{4-0} = dst; - } - -//===----------------------------------------------------------------------===// -// multiclass for load instructions with base + register offset -// addressing mode -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, addrMode = BaseRegOffset in -multiclass ld_idxd_shl <string mnemonic, string CextOp, RegisterClass RC, - bits<3> MajOp > { - let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl, - InputType = "reg" in { - let isPredicable = 1 in - def L4_#NAME#_rr : T_load_rr <mnemonic, RC, MajOp>; - - // Predicated - def L4_p#NAME#t_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 0>; - def L4_p#NAME#f_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 0>; - - // Predicated new - def L4_p#NAME#tnew_rr : T_pload_rr <mnemonic, RC, MajOp, 0, 1>; - def L4_p#NAME#fnew_rr : T_pload_rr <mnemonic, RC, MajOp, 1, 1>; - } -} - -let hasNewValue = 1, accessSize = ByteAccess in { - defm loadrb : ld_idxd_shl<"memb", "LDrib", IntRegs, 0b000>; - defm loadrub : ld_idxd_shl<"memub", "LDriub", IntRegs, 0b001>; -} - -let hasNewValue = 1, accessSize = HalfWordAccess in { - defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>; - defm loadruh : ld_idxd_shl<"memuh", "LDriuh", IntRegs, 0b011>; -} - -let hasNewValue = 1, accessSize = WordAccess in -defm loadri : ld_idxd_shl<"memw", "LDriw", IntRegs, 0b100>; - -let accessSize = DoubleWordAccess in -defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>; - -//===----------------------------------------------------------------------===// -// LD - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// ST + -//===----------------------------------------------------------------------===// -/// -//===----------------------------------------------------------------------===// -// Template class for store instructions with Absolute set addressing mode. -//===----------------------------------------------------------------------===// -let isExtended = 1, opExtendable = 1, opExtentBits = 6, - addrMode = AbsoluteSet in -class T_ST_absset <string mnemonic, string BaseOp, RegisterClass RC, - bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0> - : STInst<(outs IntRegs:$dst), - (ins u6_0Ext:$addr, RC:$src), - mnemonic#"($dst = #$addr) = $src"#!if(isHalf, ".h","")>, NewValueRel { - bits<5> dst; - bits<6> addr; - bits<5> src; - let accessSize = AccessSz; - let BaseOpcode = BaseOp#"_AbsSet"; - - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1)); - - let IClass = 0b1010; - - let Inst{27-24} = 0b1011; - let Inst{23-21} = MajOp; - let Inst{20-16} = dst; - let Inst{13} = 0b0; - let Inst{12-8} = src; - let Inst{7} = 0b1; - let Inst{5-0} = addr; - } - -def S4_storerb_ap : T_ST_absset <"memb", "STrib", IntRegs, 0b000, ByteAccess>; -def S4_storerh_ap : T_ST_absset <"memh", "STrih", IntRegs, 0b010, - HalfWordAccess>; -def S4_storeri_ap : T_ST_absset <"memw", "STriw", IntRegs, 0b100, WordAccess>; - -let isNVStorable = 0 in { - def S4_storerf_ap : T_ST_absset <"memh", "STrif", IntRegs, - 0b011, HalfWordAccess, 1>; - def S4_storerd_ap : T_ST_absset <"memd", "STrid", DoubleRegs, - 0b110, DoubleWordAccess>; -} - -let opExtendable = 1, isNewValue = 1, isNVStore = 1, opNewValue = 2, -isExtended = 1, opExtentBits= 6 in -class T_ST_absset_nv <string mnemonic, string BaseOp, bits<2> MajOp, - MemAccessSize AccessSz > - : NVInst <(outs IntRegs:$dst), - (ins u6_0Ext:$addr, IntRegs:$src), - mnemonic#"($dst = #$addr) = $src.new">, NewValueRel { - bits<5> dst; - bits<6> addr; - bits<3> src; - let accessSize = AccessSz; - let BaseOpcode = BaseOp#"_AbsSet"; - - let IClass = 0b1010; - - let Inst{27-21} = 0b1011101; - let Inst{20-16} = dst; - let Inst{13-11} = 0b000; - let Inst{12-11} = MajOp; - let Inst{10-8} = src; - let Inst{7} = 0b1; - let Inst{5-0} = addr; - } - -let mayStore = 1, addrMode = AbsoluteSet in { - def S4_storerbnew_ap : T_ST_absset_nv <"memb", "STrib", 0b00, ByteAccess>; - def S4_storerhnew_ap : T_ST_absset_nv <"memh", "STrih", 0b01, HalfWordAccess>; - def S4_storerinew_ap : T_ST_absset_nv <"memw", "STriw", 0b10, WordAccess>; -} - -let isExtended = 1, opExtendable = 2, opExtentBits = 6, InputType = "imm", - addrMode = BaseLongOffset, AddedComplexity = 40 in -class T_StoreAbsReg <string mnemonic, string CextOp, RegisterClass RC, - bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0> - : STInst<(outs), - (ins IntRegs:$src1, u2_0Imm:$src2, u6_0Ext:$src3, RC:$src4), - mnemonic#"($src1<<#$src2 + #$src3) = $src4"#!if(isHalf, ".h",""), - []>, ImmRegShl, NewValueRel { - - bits<5> src1; - bits<2> src2; - bits<6> src3; - bits<5> src4; - - let accessSize = AccessSz; - let CextOpcode = CextOp; - let BaseOpcode = CextOp#"_shl"; - - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1)); - - let IClass = 0b1010; - - let Inst{27-24} =0b1101; - let Inst{23-21} = MajOp; - let Inst{20-16} = src1; - let Inst{13} = src2{1}; - let Inst{12-8} = src4; - let Inst{7} = 0b1; - let Inst{6} = src2{0}; - let Inst{5-0} = src3; -} - -def S4_storerb_ur : T_StoreAbsReg <"memb", "STrib", IntRegs, 0b000, ByteAccess>; -def S4_storerh_ur : T_StoreAbsReg <"memh", "STrih", IntRegs, 0b010, - HalfWordAccess>; -def S4_storerf_ur : T_StoreAbsReg <"memh", "STrif", IntRegs, 0b011, - HalfWordAccess, 1>; -def S4_storeri_ur : T_StoreAbsReg <"memw", "STriw", IntRegs, 0b100, WordAccess>; -def S4_storerd_ur : T_StoreAbsReg <"memd", "STrid", DoubleRegs, 0b110, - DoubleWordAccess>; - -let mayStore = 1, isNVStore = 1, isExtended = 1, addrMode = BaseLongOffset, - opExtentBits = 6, isNewValue = 1, opNewValue = 3, opExtendable = 2 in -class T_StoreAbsRegNV <string mnemonic, string CextOp, bits<2> MajOp, - MemAccessSize AccessSz> - : NVInst <(outs ), - (ins IntRegs:$src1, u2_0Imm:$src2, u6_0Ext:$src3, IntRegs:$src4), - mnemonic#"($src1<<#$src2 + #$src3) = $src4.new">, NewValueRel { - bits<5> src1; - bits<2> src2; - bits<6> src3; - bits<3> src4; - - let CextOpcode = CextOp; - let BaseOpcode = CextOp#"_shl"; - let IClass = 0b1010; - - let Inst{27-21} = 0b1101101; - let Inst{12-11} = 0b00; - let Inst{7} = 0b1; - let Inst{20-16} = src1; - let Inst{13} = src2{1}; - let Inst{12-11} = MajOp; - let Inst{10-8} = src4; - let Inst{6} = src2{0}; - let Inst{5-0} = src3; - } - -def S4_storerbnew_ur : T_StoreAbsRegNV <"memb", "STrib", 0b00, ByteAccess>; -def S4_storerhnew_ur : T_StoreAbsRegNV <"memh", "STrih", 0b01, HalfWordAccess>; -def S4_storerinew_ur : T_StoreAbsRegNV <"memw", "STriw", 0b10, WordAccess>; - -//===----------------------------------------------------------------------===// -// Template classes for the non-predicated store instructions with -// base + register offset addressing mode -//===----------------------------------------------------------------------===// -let isPredicable = 1 in -class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH> - : STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2_0Imm:$u2, RC:$Rt), - mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""), - [],"",V4LDST_tc_st_SLOT01>, ImmRegShl, AddrModeRel { - - bits<5> Rs; - bits<5> Ru; - bits<2> u2; - bits<5> Rt; - - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1)); - - let IClass = 0b0011; - - let Inst{27-24} = 0b1011; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{12-8} = Ru; - let Inst{13} = u2{1}; - let Inst{7} = u2{0}; - let Inst{4-0} = Rt; - } - -//===----------------------------------------------------------------------===// -// Template classes for the predicated store instructions with -// base + register offset addressing mode -//===----------------------------------------------------------------------===// -let isPredicated = 1 in -class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, - bit isNot, bit isPredNew, bit isH> - : STInst <(outs), - (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2_0Imm:$u2, RC:$Rt), - - !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""), - [], "", V4LDST_tc_st_SLOT01> , AddrModeRel{ - bits<2> Pv; - bits<5> Rs; - bits<5> Ru; - bits<2> u2; - bits<5> Rt; - - let isPredicatedFalse = isNot; - let isPredicatedNew = isPredNew; - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1)); - - let IClass = 0b0011; - - let Inst{27-26} = 0b01; - let Inst{25} = isPredNew; - let Inst{24} = isNot; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{12-8} = Ru; - let Inst{13} = u2{1}; - let Inst{7} = u2{0}; - let Inst{6-5} = Pv; - let Inst{4-0} = Rt; - } - -//===----------------------------------------------------------------------===// -// Template classes for the new-value store instructions with -// base + register offset addressing mode -//===----------------------------------------------------------------------===// -let isPredicable = 1, isNewValue = 1, opNewValue = 3 in -class T_store_new_rr <string mnemonic, bits<2> MajOp> : - NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2_0Imm:$u2, IntRegs:$Nt), - mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new", - [],"",V4LDST_tc_st_SLOT0>, ImmRegShl, AddrModeRel { - - bits<5> Rs; - bits<5> Ru; - bits<2> u2; - bits<3> Nt; - - let IClass = 0b0011; - - let Inst{27-21} = 0b1011101; - let Inst{20-16} = Rs; - let Inst{12-8} = Ru; - let Inst{13} = u2{1}; - let Inst{7} = u2{0}; - let Inst{4-3} = MajOp; - let Inst{2-0} = Nt; - } - -//===----------------------------------------------------------------------===// -// Template classes for the predicated new-value store instructions with -// base + register offset addressing mode -//===----------------------------------------------------------------------===// -let isPredicated = 1, isNewValue = 1, opNewValue = 4 in -class T_pstore_new_rr <string mnemonic, bits<2> MajOp, bit isNot, bit isPredNew> - : NVInst<(outs), - (ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2_0Imm:$u2, IntRegs:$Nt), - !if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new", - [], "", V4LDST_tc_st_SLOT0>, AddrModeRel { - bits<2> Pv; - bits<5> Rs; - bits<5> Ru; - bits<2> u2; - bits<3> Nt; - - let isPredicatedFalse = isNot; - let isPredicatedNew = isPredNew; - - let IClass = 0b0011; - let Inst{27-26} = 0b01; - let Inst{25} = isPredNew; - let Inst{24} = isNot; - let Inst{23-21} = 0b101; - let Inst{20-16} = Rs; - let Inst{12-8} = Ru; - let Inst{13} = u2{1}; - let Inst{7} = u2{0}; - let Inst{6-5} = Pv; - let Inst{4-3} = MajOp; - let Inst{2-0} = Nt; - } - -//===----------------------------------------------------------------------===// -// multiclass for store instructions with base + register offset addressing -// mode -//===----------------------------------------------------------------------===// -let isNVStorable = 1 in -multiclass ST_Idxd_shl<string mnemonic, string CextOp, RegisterClass RC, - bits<3> MajOp, bit isH = 0> { - let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in { - def S4_#NAME#_rr : T_store_rr <mnemonic, RC, MajOp, isH>; - - // Predicated - def S4_p#NAME#t_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 0, isH>; - def S4_p#NAME#f_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 0, isH>; - - // Predicated new - def S4_p#NAME#tnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 0, 1, isH>; - def S4_p#NAME#fnew_rr : T_pstore_rr <mnemonic, RC, MajOp, 1, 1, isH>; - } -} - -//===----------------------------------------------------------------------===// -// multiclass for new-value store instructions with base + register offset -// addressing mode. -//===----------------------------------------------------------------------===// -let mayStore = 1, isNVStore = 1 in -multiclass ST_Idxd_shl_nv <string mnemonic, string CextOp, RegisterClass RC, - bits<2> MajOp> { - let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in { - def S4_#NAME#new_rr : T_store_new_rr<mnemonic, MajOp>; - - // Predicated - def S4_p#NAME#newt_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 0>; - def S4_p#NAME#newf_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 0>; - - // Predicated new - def S4_p#NAME#newtnew_rr : T_pstore_new_rr <mnemonic, MajOp, 0, 1>; - def S4_p#NAME#newfnew_rr : T_pstore_new_rr <mnemonic, MajOp, 1, 1>; - } -} - -let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0 in { - let accessSize = ByteAccess in - defm storerb: ST_Idxd_shl<"memb", "STrib", IntRegs, 0b000>, - ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>; - - let accessSize = HalfWordAccess in - defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>, - ST_Idxd_shl_nv<"memh", "STrih", IntRegs, 0b01>; - - let accessSize = WordAccess in - defm storeri: ST_Idxd_shl<"memw", "STriw", IntRegs, 0b100>, - ST_Idxd_shl_nv<"memw", "STriw", IntRegs, 0b10>; - - let isNVStorable = 0, accessSize = DoubleWordAccess in - defm storerd: ST_Idxd_shl<"memd", "STrid", DoubleRegs, 0b110>; - - let isNVStorable = 0, accessSize = HalfWordAccess in - defm storerf: ST_Idxd_shl<"memh", "STrif", IntRegs, 0b011, 1>; -} - -//===----------------------------------------------------------------------===// -// Template class -//===----------------------------------------------------------------------===// -let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8, - opExtendable = 2 in -class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp > - : STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8_0Ext:$S8), - mnemonic#"($Rs+#$offset)=#$S8", - [], "", V4LDST_tc_st_SLOT01>, - ImmRegRel, PredNewRel { - bits<5> Rs; - bits<8> S8; - bits<8> offset; - bits<6> offsetBits; - - string OffsetOpStr = !cast<string>(OffsetOp); - let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2}, - !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1}, - /* u6_0Imm */ offset{5-0})); - - let IClass = 0b0011; - - let Inst{27-25} = 0b110; - let Inst{22-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{12-7} = offsetBits; - let Inst{13} = S8{7}; - let Inst{6-0} = S8{6-0}; - } - -let isPredicated = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 6, - opExtendable = 3 in -class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp, - bit isPredNot, bit isPredNew > - : STInst <(outs ), - (ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6_0Ext:$S6), - !if(isPredNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($Rs+#$offset)=#$S6", - [], "", V4LDST_tc_st_SLOT01>, - ImmRegRel, PredNewRel { - bits<2> Pv; - bits<5> Rs; - bits<6> S6; - bits<8> offset; - bits<6> offsetBits; - - string OffsetOpStr = !cast<string>(OffsetOp); - let offsetBits = !if (!eq(OffsetOpStr, "u6_2Imm"), offset{7-2}, - !if (!eq(OffsetOpStr, "u6_1Imm"), offset{6-1}, - /* u6_0Imm */ offset{5-0})); - let isPredicatedNew = isPredNew; - let isPredicatedFalse = isPredNot; - - let IClass = 0b0011; - - let Inst{27-25} = 0b100; - let Inst{24} = isPredNew; - let Inst{23} = isPredNot; - let Inst{22-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{13} = S6{5}; - let Inst{12-7} = offsetBits; - let Inst{6-5} = Pv; - let Inst{4-0} = S6{4-0}; - } - - -//===----------------------------------------------------------------------===// -// multiclass for store instructions with base + immediate offset -// addressing mode and immediate stored value. -// mem[bhw](Rx++#s4:3)=#s8 -// if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6 -//===----------------------------------------------------------------------===// - -multiclass ST_Imm_Pred <string mnemonic, Operand OffsetOp, bits<2> MajOp, - bit PredNot> { - def _io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 0>; - // Predicate new - def new_io : T_StoreImm_pred <mnemonic, OffsetOp, MajOp, PredNot, 1>; -} - -multiclass ST_Imm <string mnemonic, string CextOp, Operand OffsetOp, - bits<2> MajOp> { - let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in { - def _io : T_StoreImm <mnemonic, OffsetOp, MajOp>; - - defm t : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 0>; - defm f : ST_Imm_Pred <mnemonic, OffsetOp, MajOp, 1>; - } -} - -let hasSideEffects = 0, addrMode = BaseImmOffset, - InputType = "imm" in { - let accessSize = ByteAccess in - defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>; - - let accessSize = HalfWordAccess in - defm S4_storeirh : ST_Imm<"memh", "STrih", u6_1Imm, 0b01>; - - let accessSize = WordAccess in - defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>; -} - -//===----------------------------------------------------------------------=== -// ST - -//===----------------------------------------------------------------------=== - - -//===----------------------------------------------------------------------===// -// NV/ST + -//===----------------------------------------------------------------------===// - -let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in -class T_store_io_nv <string mnemonic, RegisterClass RC, - Operand ImmOp, bits<2>MajOp> - : NVInst_V4 <(outs), - (ins IntRegs:$src1, ImmOp:$src2, RC:$src3), - mnemonic#"($src1+#$src2) = $src3.new", - [],"",ST_tc_st_SLOT0> { - bits<5> src1; - bits<13> src2; // Actual address offset - bits<3> src3; - bits<11> offsetBits; // Represents offset encoding - - let opExtentBits = !if (!eq(mnemonic, "memb"), 11, - !if (!eq(mnemonic, "memh"), 12, - !if (!eq(mnemonic, "memw"), 13, 0))); - - let opExtentAlign = !if (!eq(mnemonic, "memb"), 0, - !if (!eq(mnemonic, "memh"), 1, - !if (!eq(mnemonic, "memw"), 2, 0))); - - let offsetBits = !if (!eq(mnemonic, "memb"), src2{10-0}, - !if (!eq(mnemonic, "memh"), src2{11-1}, - !if (!eq(mnemonic, "memw"), src2{12-2}, 0))); - - let IClass = 0b1010; - - let Inst{27} = 0b0; - let Inst{26-25} = offsetBits{10-9}; - let Inst{24-21} = 0b1101; - let Inst{20-16} = src1; - let Inst{13} = offsetBits{8}; - let Inst{12-11} = MajOp; - let Inst{10-8} = src3; - let Inst{7-0} = offsetBits{7-0}; - } - -let opExtendable = 2, opNewValue = 3, isPredicated = 1 in -class T_pstore_io_nv <string mnemonic, RegisterClass RC, Operand predImmOp, - bits<2>MajOp, bit PredNot, bit isPredNew> - : NVInst_V4 <(outs), - (ins PredRegs:$src1, IntRegs:$src2, predImmOp:$src3, RC:$src4), - !if(PredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($src2+#$src3) = $src4.new", - [],"",V2LDST_tc_st_SLOT0> { - bits<2> src1; - bits<5> src2; - bits<9> src3; - bits<3> src4; - bits<6> offsetBits; // Represents offset encoding - - let isPredicatedNew = isPredNew; - let isPredicatedFalse = PredNot; - let opExtentBits = !if (!eq(mnemonic, "memb"), 6, - !if (!eq(mnemonic, "memh"), 7, - !if (!eq(mnemonic, "memw"), 8, 0))); - - let opExtentAlign = !if (!eq(mnemonic, "memb"), 0, - !if (!eq(mnemonic, "memh"), 1, - !if (!eq(mnemonic, "memw"), 2, 0))); - - let offsetBits = !if (!eq(mnemonic, "memb"), src3{5-0}, - !if (!eq(mnemonic, "memh"), src3{6-1}, - !if (!eq(mnemonic, "memw"), src3{7-2}, 0))); - - let IClass = 0b0100; - - let Inst{27} = 0b0; - let Inst{26} = PredNot; - let Inst{25} = isPredNew; - let Inst{24-21} = 0b0101; - let Inst{20-16} = src2; - let Inst{13} = offsetBits{5}; - let Inst{12-11} = MajOp; - let Inst{10-8} = src4; - let Inst{7-3} = offsetBits{4-0}; - let Inst{2} = 0b0; - let Inst{1-0} = src1; - } - -// multiclass for new-value store instructions with base + immediate offset. -// -let mayStore = 1, isNVStore = 1, isNewValue = 1, hasSideEffects = 0, - isExtendable = 1 in -multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC, - Operand ImmOp, Operand predImmOp, bits<2> MajOp> { - - let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in { - def S2_#NAME#new_io : T_store_io_nv <mnemonic, RC, ImmOp, MajOp>; - // Predicated - def S2_p#NAME#newt_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 0, 0>; - def S2_p#NAME#newf_io :T_pstore_io_nv <mnemonic, RC, predImmOp, MajOp, 1, 0>; - // Predicated new - def S4_p#NAME#newtnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp, - MajOp, 0, 1>; - def S4_p#NAME#newfnew_io :T_pstore_io_nv <mnemonic, RC, predImmOp, - MajOp, 1, 1>; - } -} - -let addrMode = BaseImmOffset, InputType = "imm" in { - let accessSize = ByteAccess in - defm storerb: ST_Idxd_nv<"memb", "STrib", IntRegs, s11_0Ext, - u6_0Ext, 0b00>, AddrModeRel; - - let accessSize = HalfWordAccess, opExtentAlign = 1 in - defm storerh: ST_Idxd_nv<"memh", "STrih", IntRegs, s11_1Ext, - u6_1Ext, 0b01>, AddrModeRel; - - let accessSize = WordAccess, opExtentAlign = 2 in - defm storeri: ST_Idxd_nv<"memw", "STriw", IntRegs, s11_2Ext, - u6_2Ext, 0b10>, AddrModeRel; -} - -//===----------------------------------------------------------------------===// -// Post increment loads with register offset. -//===----------------------------------------------------------------------===// - -let hasNewValue = 1 in -def L2_loadbsw2_pr : T_load_pr <"membh", IntRegs, 0b0001, HalfWordAccess>; - -def L2_loadbsw4_pr : T_load_pr <"membh", DoubleRegs, 0b0111, WordAccess>; - -let hasSideEffects = 0, addrMode = PostInc in -class T_loadalign_pr <string mnemonic, bits<4> MajOp, MemAccessSize AccessSz> - : LDInstPI <(outs DoubleRegs:$dst, IntRegs:$_dst_), - (ins DoubleRegs:$src1, IntRegs:$src2, ModRegs:$src3), - "$dst = "#mnemonic#"($src2++$src3)", [], - "$src1 = $dst, $src2 = $_dst_"> { - bits<5> dst; - bits<5> src2; - bits<1> src3; - - let accessSize = AccessSz; - let IClass = 0b1001; - - let Inst{27-25} = 0b110; - let Inst{24-21} = MajOp; - let Inst{20-16} = src2; - let Inst{13} = src3; - let Inst{12} = 0b0; - let Inst{7} = 0b0; - let Inst{4-0} = dst; - } - -def L2_loadalignb_pr : T_loadalign_pr <"memb_fifo", 0b0100, ByteAccess>; -def L2_loadalignh_pr : T_loadalign_pr <"memh_fifo", 0b0010, HalfWordAccess>; - -//===----------------------------------------------------------------------===// -// Template class for non-predicated post increment .new stores -// mem[bhwd](Rx++#s4:[0123])=Nt.new -//===----------------------------------------------------------------------===// -let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc, isNVStore = 1, - isNewValue = 1, opNewValue = 3 in -class T_StorePI_nv <string mnemonic, Operand ImmOp, bits<2> MajOp > - : NVInstPI_V4 <(outs IntRegs:$_dst_), - (ins IntRegs:$src1, ImmOp:$offset, IntRegs:$src2), - mnemonic#"($src1++#$offset) = $src2.new", - [], "$src1 = $_dst_">, - AddrModeRel { - bits<5> src1; - bits<3> src2; - bits<7> offset; - bits<4> offsetBits; - - string ImmOpStr = !cast<string>(ImmOp); - let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, - !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, - /* s4_0Imm */ offset{3-0})); - let IClass = 0b1010; - - let Inst{27-21} = 0b1011101; - let Inst{20-16} = src1; - let Inst{13} = 0b0; - let Inst{12-11} = MajOp; - let Inst{10-8} = src2; - let Inst{7} = 0b0; - let Inst{6-3} = offsetBits; - let Inst{1} = 0b0; - } - -//===----------------------------------------------------------------------===// -// Template class for predicated post increment .new stores -// if([!]Pv[.new]) mem[bhwd](Rx++#s4:[0123])=Nt.new -//===----------------------------------------------------------------------===// -let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc, isNVStore = 1, - isNewValue = 1, opNewValue = 4 in -class T_StorePI_nv_pred <string mnemonic, Operand ImmOp, - bits<2> MajOp, bit isPredNot, bit isPredNew > - : NVInstPI_V4 <(outs IntRegs:$_dst_), - (ins PredRegs:$src1, IntRegs:$src2, - ImmOp:$offset, IntRegs:$src3), - !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#mnemonic#"($src2++#$offset) = $src3.new", - [], "$src2 = $_dst_">, - AddrModeRel { - bits<2> src1; - bits<5> src2; - bits<3> src3; - bits<7> offset; - bits<4> offsetBits; - - string ImmOpStr = !cast<string>(ImmOp); - let offsetBits = !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, - !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, - /* s4_0Imm */ offset{3-0})); - let isPredicatedNew = isPredNew; - let isPredicatedFalse = isPredNot; - - let IClass = 0b1010; - - let Inst{27-21} = 0b1011101; - let Inst{20-16} = src2; - let Inst{13} = 0b1; - let Inst{12-11} = MajOp; - let Inst{10-8} = src3; - let Inst{7} = isPredNew; - let Inst{6-3} = offsetBits; - let Inst{2} = isPredNot; - let Inst{1-0} = src1; - } - -multiclass ST_PostInc_Pred_nv<string mnemonic, Operand ImmOp, - bits<2> MajOp, bit PredNot> { - def _pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 0>; - - // Predicate new - def new_pi : T_StorePI_nv_pred <mnemonic, ImmOp, MajOp, PredNot, 1>; -} - -multiclass ST_PostInc_nv<string mnemonic, string BaseOp, Operand ImmOp, - bits<2> MajOp> { - let BaseOpcode = "POST_"#BaseOp in { - def S2_#NAME#_pi : T_StorePI_nv <mnemonic, ImmOp, MajOp>; - - // Predicated - defm S2_p#NAME#t : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 0>; - defm S2_p#NAME#f : ST_PostInc_Pred_nv <mnemonic, ImmOp, MajOp, 1>; - } -} - -let accessSize = ByteAccess in -defm storerbnew: ST_PostInc_nv <"memb", "STrib", s4_0Imm, 0b00>; - -let accessSize = HalfWordAccess in -defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>; - -let accessSize = WordAccess in -defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>; - -//===----------------------------------------------------------------------===// -// Template class for post increment .new stores with register offset -//===----------------------------------------------------------------------===// -let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in -class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz> - : NVInstPI_V4 <(outs IntRegs:$_dst_), - (ins IntRegs:$src1, ModRegs:$src2, IntRegs:$src3), - #mnemonic#"($src1++$src2) = $src3.new", - [], "$src1 = $_dst_"> { - bits<5> src1; - bits<1> src2; - bits<3> src3; - let accessSize = AccessSz; - - let IClass = 0b1010; - - let Inst{27-21} = 0b1101101; - let Inst{20-16} = src1; - let Inst{13} = src2; - let Inst{12-11} = MajOp; - let Inst{10-8} = src3; - let Inst{7} = 0b0; - } - -def S2_storerbnew_pr : T_StorePI_RegNV<"memb", 0b00, ByteAccess>; -def S2_storerhnew_pr : T_StorePI_RegNV<"memh", 0b01, HalfWordAccess>; -def S2_storerinew_pr : T_StorePI_RegNV<"memw", 0b10, WordAccess>; - -// memb(Rx++#s4:0:circ(Mu))=Nt.new -// memb(Rx++I:circ(Mu))=Nt.new -// memb(Rx++Mu:brev)=Nt.new -// memh(Rx++#s4:1:circ(Mu))=Nt.new -// memh(Rx++I:circ(Mu))=Nt.new -// memh(Rx++Mu)=Nt.new -// memh(Rx++Mu:brev)=Nt.new - -// memw(Rx++#s4:2:circ(Mu))=Nt.new -// memw(Rx++I:circ(Mu))=Nt.new -// memw(Rx++Mu)=Nt.new -// memw(Rx++Mu:brev)=Nt.new - -//===----------------------------------------------------------------------===// -// NV/ST - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// NV/J + -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// multiclass/template class for the new-value compare jumps with the register -// operands. -//===----------------------------------------------------------------------===// - -let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11, - opExtentAlign = 2 in -class NVJrr_template<string mnemonic, bits<3> majOp, bit NvOpNum, - bit isNegCond, bit isTak> - : NVInst_V4<(outs), - (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset), - "if ("#!if(isNegCond, "!","")#mnemonic# - "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")# - "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:" - #!if(isTak, "t","nt")#" $offset", []> { - - bits<5> src1; - bits<5> src2; - bits<3> Ns; // New-Value Operand - bits<5> RegOp; // Non-New-Value Operand - bits<11> offset; - - let isTaken = isTak; - let isPredicatedFalse = isNegCond; - let opNewValue{0} = NvOpNum; - - let Ns = !if(!eq(NvOpNum, 0), src1{2-0}, src2{2-0}); - let RegOp = !if(!eq(NvOpNum, 0), src2, src1); - - let IClass = 0b0010; - let Inst{27-26} = 0b00; - let Inst{25-23} = majOp; - let Inst{22} = isNegCond; - let Inst{18-16} = Ns; - let Inst{13} = isTak; - let Inst{12-8} = RegOp; - let Inst{21-20} = offset{10-9}; - let Inst{7-1} = offset{8-2}; -} - - -multiclass NVJrr_cond<string mnemonic, bits<3> majOp, bit NvOpNum, - bit isNegCond> { - // Branch not taken: - def _nt: NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 0>; - // Branch taken: - def _t : NVJrr_template<mnemonic, majOp, NvOpNum, isNegCond, 1>; -} - -// NvOpNum = 0 -> First Operand is a new-value Register -// NvOpNum = 1 -> Second Operand is a new-value Register - -multiclass NVJrr_base<string mnemonic, string BaseOp, bits<3> majOp, - bit NvOpNum> { - let BaseOpcode = BaseOp#_NVJ in { - defm _t_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 0>; // True cond - defm _f_jumpnv : NVJrr_cond<mnemonic, majOp, NvOpNum, 1>; // False cond - } -} - -// if ([!]cmp.eq(Ns.new,Rt)) jump:[n]t #r9:2 -// if ([!]cmp.gt(Ns.new,Rt)) jump:[n]t #r9:2 -// if ([!]cmp.gtu(Ns.new,Rt)) jump:[n]t #r9:2 -// if ([!]cmp.gt(Rt,Ns.new)) jump:[n]t #r9:2 -// if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2 - -let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1, - Defs = [PC], hasSideEffects = 0 in { - defm J4_cmpeq : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel; - defm J4_cmpgt : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel; - defm J4_cmpgtu : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel; - defm J4_cmplt : NVJrr_base<"cmp.gt", "CMPLT", 0b011, 1>, PredRel; - defm J4_cmpltu : NVJrr_base<"cmp.gtu", "CMPLTU", 0b100, 1>, PredRel; -} - -//===----------------------------------------------------------------------===// -// multiclass/template class for the new-value compare jumps instruction -// with a register and an unsigned immediate (U5) operand. -//===----------------------------------------------------------------------===// - -let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11, - opExtentAlign = 2 in -class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond, - bit isTak> - : NVInst_V4<(outs), - (ins IntRegs:$src1, u5_0Imm:$src2, brtarget:$offset), - "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:" - #!if(isTak, "t","nt")#" $offset", []> { - - let isTaken = isTak; - let isPredicatedFalse = isNegCond; - let isTaken = isTak; - - bits<3> src1; - bits<5> src2; - bits<11> offset; - - let IClass = 0b0010; - let Inst{26} = 0b1; - let Inst{25-23} = majOp; - let Inst{22} = isNegCond; - let Inst{18-16} = src1; - let Inst{13} = isTak; - let Inst{12-8} = src2; - let Inst{21-20} = offset{10-9}; - let Inst{7-1} = offset{8-2}; -} - -multiclass NVJri_cond<string mnemonic, bits<3> majOp, bit isNegCond> { - // Branch not taken: - def _nt: NVJri_template<mnemonic, majOp, isNegCond, 0>; - // Branch taken: - def _t : NVJri_template<mnemonic, majOp, isNegCond, 1>; -} - -multiclass NVJri_base<string mnemonic, string BaseOp, bits<3> majOp> { - let BaseOpcode = BaseOp#_NVJri in { - defm _t_jumpnv : NVJri_cond<mnemonic, majOp, 0>; // True Cond - defm _f_jumpnv : NVJri_cond<mnemonic, majOp, 1>; // False cond - } -} - -// if ([!]cmp.eq(Ns.new,#U5)) jump:[n]t #r9:2 -// if ([!]cmp.gt(Ns.new,#U5)) jump:[n]t #r9:2 -// if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2 - -let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1, - Defs = [PC], hasSideEffects = 0 in { - defm J4_cmpeqi : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel; - defm J4_cmpgti : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel; - defm J4_cmpgtui : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel; -} - -//===----------------------------------------------------------------------===// -// multiclass/template class for the new-value compare jumps instruction -// with a register and an hardcoded 0/-1 immediate value. -//===----------------------------------------------------------------------===// - -let isExtendable = 1, isExtentSigned = 1, opExtentBits = 11, - opExtentAlign = 2 in -class NVJ_ConstImm_template<string mnemonic, bits<3> majOp, string ImmVal, - bit isNegCond, bit isTak> - : NVInst_V4<(outs), - !if(!eq(ImmVal, "{-1}"), - (ins IntRegs:$src1, n1Const:$n1, brtarget:$offset), - (ins IntRegs:$src1, brtarget:$offset)), - "if ("#!if(isNegCond, "!","")#mnemonic - #"($src1.new, #" # !if(!eq(ImmVal, "{-1}"), "$n1", ImmVal) # ")) jump:" - #!if(isTak, "t","nt")#" $offset", []> { - - let isTaken = isTak; - let isPredicatedFalse = isNegCond; - let isTaken = isTak; - let opExtendable = !if(!eq(ImmVal, "{-1}"), 2, 1); - - bits<3> src1; - bits<11> offset; - let IClass = 0b0010; - let Inst{26} = 0b1; - let Inst{25-23} = majOp; - let Inst{22} = isNegCond; - let Inst{18-16} = src1; - let Inst{13} = isTak; - let Inst{21-20} = offset{10-9}; - let Inst{7-1} = offset{8-2}; -} - -multiclass NVJ_ConstImm_cond<string mnemonic, bits<3> majOp, string ImmVal, - bit isNegCond> { - // Branch not taken: - def _nt: NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 0>; - // Branch taken: - def _t : NVJ_ConstImm_template<mnemonic, majOp, ImmVal, isNegCond, 1>; -} - -multiclass NVJ_ConstImm_base<string mnemonic, string BaseOp, bits<3> majOp, - string ImmVal> { - let BaseOpcode = BaseOp#_NVJ_ConstImm in { - defm _t_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 0>; // True - defm _f_jumpnv : NVJ_ConstImm_cond<mnemonic, majOp, ImmVal, 1>; // False - } -} - -// if ([!]tstbit(Ns.new,#0)) jump:[n]t #r9:2 -// if ([!]cmp.eq(Ns.new,#-1)) jump:[n]t #r9:2 -// if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2 - -let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1, - Defs = [PC], hasSideEffects = 0 in { - defm J4_tstbit0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel; - defm J4_cmpeqn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "{-1}">, PredRel; - defm J4_cmpgtn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "{-1}">, PredRel; -} - -// J4_hintjumpr: Hint indirect conditional jump. -let isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in -def J4_hintjumpr: JRInst < - (outs), - (ins IntRegs:$Rs), - "hintjr($Rs)"> { - bits<5> Rs; - let IClass = 0b0101; - let Inst{27-21} = 0b0010101; - let Inst{20-16} = Rs; - } - -//===----------------------------------------------------------------------===// -// NV/J - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// CR + -//===----------------------------------------------------------------------===// - -// PC-relative add -let hasNewValue = 1, isExtendable = 1, opExtendable = 1, - isExtentSigned = 0, opExtentBits = 6, hasSideEffects = 0, Uses = [PC] in -def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6_0Ext:$u6), - "$Rd = add(pc, #$u6)", [], "", CR_tc_2_SLOT3 > { - bits<5> Rd; - bits<6> u6; - - let IClass = 0b0110; - let Inst{27-16} = 0b101001001001; - let Inst{12-7} = u6; - let Inst{4-0} = Rd; - } - - - -let hasSideEffects = 0 in -class T_LOGICAL_3OP<string MnOp1, string MnOp2, bits<2> OpBits, bit IsNeg> - : CRInst<(outs PredRegs:$Pd), - (ins PredRegs:$Ps, PredRegs:$Pt, PredRegs:$Pu), - "$Pd = " # MnOp1 # "($Ps, " # MnOp2 # "($Pt, " # - !if (IsNeg,"!","") # "$Pu))", - [], "", CR_tc_2early_SLOT23> { - bits<2> Pd; - bits<2> Ps; - bits<2> Pt; - bits<2> Pu; - - let IClass = 0b0110; - let Inst{27-24} = 0b1011; - let Inst{23} = IsNeg; - let Inst{22-21} = OpBits; - let Inst{20} = 0b1; - let Inst{17-16} = Ps; - let Inst{13} = 0b0; - let Inst{9-8} = Pt; - let Inst{7-6} = Pu; - let Inst{1-0} = Pd; -} - -def C4_and_and : T_LOGICAL_3OP<"and", "and", 0b00, 0>; -def C4_and_or : T_LOGICAL_3OP<"and", "or", 0b01, 0>; -def C4_or_and : T_LOGICAL_3OP<"or", "and", 0b10, 0>; -def C4_or_or : T_LOGICAL_3OP<"or", "or", 0b11, 0>; -def C4_and_andn : T_LOGICAL_3OP<"and", "and", 0b00, 1>; -def C4_and_orn : T_LOGICAL_3OP<"and", "or", 0b01, 1>; -def C4_or_andn : T_LOGICAL_3OP<"or", "and", 0b10, 1>; -def C4_or_orn : T_LOGICAL_3OP<"or", "or", 0b11, 1>; - -//===----------------------------------------------------------------------===// -// CR - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// XTYPE/ALU + -//===----------------------------------------------------------------------===// - -// Logical with-not instructions. -def A4_andnp : T_ALU64_logical<"and", 0b001, 1, 0, 1>; -def A4_ornp : T_ALU64_logical<"or", 0b011, 1, 0, 1>; - -let hasNewValue = 1, hasSideEffects = 0 in -def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = parity($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - let Inst{27-21} = 0b0101111; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{4-0} = Rd; -} - -// Add and accumulate. -// Rd=add(Rs,add(Ru,#s6)) -let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 6, - opExtendable = 3 in -def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd), - (ins IntRegs:$Rs, IntRegs:$Ru, s6_0Ext:$s6), - "$Rd = add($Rs, add($Ru, #$s6))" , [], - "", ALU64_tc_2_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> Ru; - bits<6> s6; - - let IClass = 0b1101; - - let Inst{27-23} = 0b10110; - let Inst{22-21} = s6{5-4}; - let Inst{20-16} = Rs; - let Inst{13} = s6{3}; - let Inst{12-8} = Rd; - let Inst{7-5} = s6{2-0}; - let Inst{4-0} = Ru; - } - -let isExtentSigned = 1, hasSideEffects = 0, hasNewValue = 1, isExtendable = 1, - opExtentBits = 6, opExtendable = 2 in -def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd), - (ins IntRegs:$Rs, s6_0Ext:$s6, IntRegs:$Ru), - "$Rd = add($Rs, sub(#$s6, $Ru))", - [], "", ALU64_tc_2_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<6> s6; - bits<5> Ru; - - let IClass = 0b1101; - - let Inst{27-23} = 0b10111; - let Inst{22-21} = s6{5-4}; - let Inst{20-16} = Rs; - let Inst{13} = s6{3}; - let Inst{12-8} = Rd; - let Inst{7-5} = s6{2-0}; - let Inst{4-0} = Ru; - } - -def S4_extractp_rp : T_S3op_64 < "extract", 0b11, 0b100, 0>; -def S4_extractp : T_S2op_extract <"extract", 0b1010, DoubleRegs, u6_0Imm>; - -let hasNewValue = 1 in { - def S4_extract_rp : T_S3op_extract<"extract", 0b01>; - def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5_0Imm>; -} - -// Complex add/sub halfwords/words -let Defs = [USR_OVF] in { - def S4_vxaddsubh : T_S3op_64 < "vxaddsubh", 0b01, 0b100, 0, 1>; - def S4_vxaddsubw : T_S3op_64 < "vxaddsubw", 0b01, 0b000, 0, 1>; - def S4_vxsubaddh : T_S3op_64 < "vxsubaddh", 0b01, 0b110, 0, 1>; - def S4_vxsubaddw : T_S3op_64 < "vxsubaddw", 0b01, 0b010, 0, 1>; -} - -let Defs = [USR_OVF] in { - def S4_vxaddsubhr : T_S3op_64 < "vxaddsubh", 0b11, 0b000, 0, 1, 1, 1>; - def S4_vxsubaddhr : T_S3op_64 < "vxsubaddh", 0b11, 0b010, 0, 1, 1, 1>; -} - -let Itinerary = M_tc_3x_SLOT23, Defs = [USR_OVF] in { - def M4_mac_up_s1_sat: T_MType_acc_rr<"+= mpy", 0b011, 0b000, 0, [], 0, 1, 1>; - def M4_nac_up_s1_sat: T_MType_acc_rr<"-= mpy", 0b011, 0b001, 0, [], 0, 1, 1>; -} - -// Logical xor with xor accumulation. -// Rxx^=xor(Rss,Rtt) -let hasSideEffects = 0 in -def M4_xor_xacc - : SInst <(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Rxx ^= xor($Rss, $Rtt)", [], - "$dst2 = $Rxx", S_3op_tc_1_SLOT23> { - bits<5> Rxx; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1100; - - let Inst{27-22} = 0b101010; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - let Inst{7-5} = 0b000; - let Inst{4-0} = Rxx; - } - -// Rotate and reduce bytes -// Rdd=vrcrotate(Rss,Rt,#u2) -let hasSideEffects = 0 in -def S4_vrcrotate - : SInst <(outs DoubleRegs:$Rdd), - (ins DoubleRegs:$Rss, IntRegs:$Rt, u2_0Imm:$u2), - "$Rdd = vrcrotate($Rss, $Rt, #$u2)", - [], "", S_3op_tc_3x_SLOT23> { - bits<5> Rdd; - bits<5> Rss; - bits<5> Rt; - bits<2> u2; - - let IClass = 0b1100; - - let Inst{27-22} = 0b001111; - let Inst{20-16} = Rss; - let Inst{13} = u2{1}; - let Inst{12-8} = Rt; - let Inst{7-6} = 0b11; - let Inst{5} = u2{0}; - let Inst{4-0} = Rdd; - } - -// Rotate and reduce bytes with accumulation -// Rxx+=vrcrotate(Rss,Rt,#u2) -let hasSideEffects = 0 in -def S4_vrcrotate_acc - : SInst <(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt, u2_0Imm:$u2), - "$Rxx += vrcrotate($Rss, $Rt, #$u2)", [], - "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> { - bits<5> Rxx; - bits<5> Rss; - bits<5> Rt; - bits<2> u2; - - let IClass = 0b1100; - - let Inst{27-21} = 0b1011101; - let Inst{20-16} = Rss; - let Inst{13} = u2{1}; - let Inst{12-8} = Rt; - let Inst{5} = u2{0}; - let Inst{4-0} = Rxx; - } - -// Vector reduce conditional negate halfwords -let hasSideEffects = 0 in -def S2_vrcnegh - : SInst <(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt), - "$Rxx += vrcnegh($Rss, $Rt)", [], - "$dst2 = $Rxx", S_3op_tc_3x_SLOT23> { - bits<5> Rxx; - bits<5> Rss; - bits<5> Rt; - - let IClass = 0b1100; - - let Inst{27-21} = 0b1011001; - let Inst{20-16} = Rss; - let Inst{13} = 0b1; - let Inst{12-8} = Rt; - let Inst{7-5} = 0b111; - let Inst{4-0} = Rxx; - } - -// Split bitfield -def A4_bitspliti : T_S2op_2_di <"bitsplit", 0b110, 0b100>; - -// Arithmetic/Convergent round -def A4_cround_ri : T_S2op_2_ii <"cround", 0b111, 0b000>; - -def A4_round_ri : T_S2op_2_ii <"round", 0b111, 0b100>; - -let Defs = [USR_OVF] in -def A4_round_ri_sat : T_S2op_2_ii <"round", 0b111, 0b110, 1>; - -// Logical-logical words. -// Compound or-and -- Rx=or(Ru,and(Rx,#s10)) -let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 10, - opExtendable = 3 in -def S4_or_andix: - ALU64Inst<(outs IntRegs:$Rx), - (ins IntRegs:$Ru, IntRegs:$_src_, s10_0Ext:$s10), - "$Rx = or($Ru, and($_src_, #$s10))" , [] , - "$_src_ = $Rx", ALU64_tc_2_SLOT23> { - bits<5> Rx; - bits<5> Ru; - bits<10> s10; - - let IClass = 0b1101; - - let Inst{27-22} = 0b101001; - let Inst{20-16} = Rx; - let Inst{21} = s10{9}; - let Inst{13-5} = s10{8-0}; - let Inst{4-0} = Ru; - } - -// Miscellaneous ALU64 instructions. -// -let hasNewValue = 1, hasSideEffects = 0 in -def A4_modwrapu: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = modwrap($Rs, $Rt)", [], "", ALU64_tc_2_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - let Inst{27-21} = 0b0011111; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{7-5} = 0b111; - let Inst{4-0} = Rd; -} - -let hasSideEffects = 0 in -def A4_bitsplit: ALU64Inst<(outs DoubleRegs:$Rd), - (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = bitsplit($Rs, $Rt)", [], "", ALU64_tc_1_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - let Inst{27-24} = 0b0100; - let Inst{21} = 0b1; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{4-0} = Rd; -} - -let hasSideEffects = 0 in -def dep_S2_packhl: ALU64Inst<(outs DoubleRegs:$Rd), - (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = packhl($Rs, $Rt):deprecated", [], "", ALU64_tc_1_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - let Inst{27-24} = 0b0100; - let Inst{21} = 0b0; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{4-0} = Rd; -} - -let hasNewValue = 1, hasSideEffects = 0 in -def dep_A2_addsat: ALU64Inst<(outs IntRegs:$Rd), - (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = add($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - let Inst{27-21} = 0b0101100; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{7} = 0b0; - let Inst{4-0} = Rd; -} - -let hasNewValue = 1, hasSideEffects = 0 in -def dep_A2_subsat: ALU64Inst<(outs IntRegs:$Rd), - (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = sub($Rs, $Rt):sat:deprecated", [], "", ALU64_tc_2_SLOT23> { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - let Inst{27-21} = 0b0101100; - let Inst{20-16} = Rt; - let Inst{12-8} = Rs; - let Inst{7} = 0b1; - let Inst{4-0} = Rd; -} - -// Rx[&|]=xor(Rs,Rt) -def M4_or_xor : T_MType_acc_rr < "|= xor", 0b110, 0b001, 0>; -def M4_and_xor : T_MType_acc_rr < "&= xor", 0b010, 0b010, 0>; - -// Rx[&|^]=or(Rs,Rt) -def M4_xor_or : T_MType_acc_rr < "^= or", 0b110, 0b011, 0>; - -let CextOpcode = "ORr_ORr" in -def M4_or_or : T_MType_acc_rr < "|= or", 0b110, 0b000, 0>; -def M4_and_or : T_MType_acc_rr < "&= or", 0b010, 0b001, 0>; - -// Rx[&|^]=and(Rs,Rt) -def M4_xor_and : T_MType_acc_rr < "^= and", 0b110, 0b010, 0>; - -let CextOpcode = "ORr_ANDr" in -def M4_or_and : T_MType_acc_rr < "|= and", 0b010, 0b011, 0>; -def M4_and_and : T_MType_acc_rr < "&= and", 0b010, 0b000, 0>; - -// Rx[&|^]=and(Rs,~Rt) -def M4_xor_andn : T_MType_acc_rr < "^= and", 0b001, 0b010, 0, [], 1>; -def M4_or_andn : T_MType_acc_rr < "|= and", 0b001, 0b000, 0, [], 1>; -def M4_and_andn : T_MType_acc_rr < "&= and", 0b001, 0b001, 0, [], 1>; - -// Compound or-or and or-and -let isExtentSigned = 1, InputType = "imm", hasNewValue = 1, isExtendable = 1, - opExtentBits = 10, opExtendable = 3 in -class T_CompOR <string mnemonic, bits<2> MajOp, SDNode OpNode> - : MInst_acc <(outs IntRegs:$Rx), - (ins IntRegs:$src1, IntRegs:$Rs, s10_0Ext:$s10), - "$Rx |= "#mnemonic#"($Rs, #$s10)", [], - "$src1 = $Rx", ALU64_tc_2_SLOT23>, ImmRegRel { - bits<5> Rx; - bits<5> Rs; - bits<10> s10; - - let IClass = 0b1101; - - let Inst{27-24} = 0b1010; - let Inst{23-22} = MajOp; - let Inst{20-16} = Rs; - let Inst{21} = s10{9}; - let Inst{13-5} = s10{8-0}; - let Inst{4-0} = Rx; - } - -let CextOpcode = "ORr_ANDr" in -def S4_or_andi : T_CompOR <"and", 0b00, and>; - -let CextOpcode = "ORr_ORr" in -def S4_or_ori : T_CompOR <"or", 0b10, or>; - -// Modulo wrap -// Rd=modwrap(Rs,Rt) -// Round -// Rd=cround(Rs,#u5) -// Rd=cround(Rs,Rt) -// Rd=round(Rs,#u5)[:sat] -// Rd=round(Rs,Rt)[:sat] -// Vector reduce add unsigned halfwords -// Rd=vraddh(Rss,Rtt) -// Vector add bytes -// Rdd=vaddb(Rss,Rtt) -// Vector conditional negate -// Rdd=vcnegh(Rss,Rt) -// Rxx+=vrcnegh(Rss,Rt) -// Vector maximum bytes -// Rdd=vmaxb(Rtt,Rss) -// Vector reduce maximum halfwords -// Rxx=vrmaxh(Rss,Ru) -// Rxx=vrmaxuh(Rss,Ru) -// Vector reduce maximum words -// Rxx=vrmaxuw(Rss,Ru) -// Rxx=vrmaxw(Rss,Ru) -// Vector minimum bytes -// Rdd=vminb(Rtt,Rss) -// Vector reduce minimum halfwords -// Rxx=vrminh(Rss,Ru) -// Rxx=vrminuh(Rss,Ru) -// Vector reduce minimum words -// Rxx=vrminuw(Rss,Ru) -// Rxx=vrminw(Rss,Ru) -// Vector subtract bytes -// Rdd=vsubb(Rss,Rtt) - -//===----------------------------------------------------------------------===// -// XTYPE/ALU - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// XTYPE/BIT + -//===----------------------------------------------------------------------===// - -// Bit reverse -def S2_brevp : T_S2op_3 <"brev", 0b11, 0b110>; - -// Bit count -def S2_ct0p : T_COUNT_LEADING_64<"ct0", 0b111, 0b010>; -def S2_ct1p : T_COUNT_LEADING_64<"ct1", 0b111, 0b100>; -def S4_clbpnorm : T_COUNT_LEADING_64<"normamt", 0b011, 0b000>; - -let hasSideEffects = 0, hasNewValue = 1 in -def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6_0Imm:$s6), - "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> { - bits<5> Rs; - bits<5> Rd; - bits<6> s6; - let IClass = 0b1000; - let Inst{27-24} = 0b1100; - let Inst{23-21} = 0b001; - let Inst{20-16} = Rs; - let Inst{13-8} = s6; - let Inst{7-5} = 0b000; - let Inst{4-0} = Rd; -} - -let hasSideEffects = 0, hasNewValue = 1 in -def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6_0Imm:$s6), - "$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> { - bits<5> Rs; - bits<5> Rd; - bits<6> s6; - let IClass = 0b1000; - let Inst{27-24} = 0b1000; - let Inst{23-21} = 0b011; - let Inst{20-16} = Rs; - let Inst{13-8} = s6; - let Inst{7-5} = 0b010; - let Inst{4-0} = Rd; -} - - -// Bit test/set/clear -def S4_ntstbit_i : T_TEST_BIT_IMM<"!tstbit", 0b001>; -def S4_ntstbit_r : T_TEST_BIT_REG<"!tstbit", 1>; - -def C4_nbitsset : T_TEST_BITS_REG<"!bitsset", 0b01, 1>; -def C4_nbitsclr : T_TEST_BITS_REG<"!bitsclr", 0b10, 1>; -def C4_nbitsclri : T_TEST_BITS_IMM<"!bitsclr", 0b10, 1>; - -//===----------------------------------------------------------------------===// -// XTYPE/BIT - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// XTYPE/MPY + -//===----------------------------------------------------------------------===// - -// Rd=add(#u6,mpyi(Rs,#U6)) -- Multiply by immed and add immed. - -let hasNewValue = 1, isExtendable = 1, opExtentBits = 6, opExtendable = 1 in -def M4_mpyri_addi : MInst<(outs IntRegs:$Rd), - (ins u6_0Ext:$u6, IntRegs:$Rs, u6_0Imm:$U6), - "$Rd = add(#$u6, mpyi($Rs, #$U6))" , [],"",ALU64_tc_3x_SLOT23> { - bits<5> Rd; - bits<6> u6; - bits<5> Rs; - bits<6> U6; - - let IClass = 0b1101; - - let Inst{27-24} = 0b1000; - let Inst{23} = U6{5}; - let Inst{22-21} = u6{5-4}; - let Inst{20-16} = Rs; - let Inst{13} = u6{3}; - let Inst{12-8} = Rd; - let Inst{7-5} = u6{2-0}; - let Inst{4-0} = U6{4-0}; - } - -// Rd=add(#u6,mpyi(Rs,Rt)) -let CextOpcode = "ADD_MPY", InputType = "imm", hasNewValue = 1, - isExtendable = 1, opExtentBits = 6, opExtendable = 1 in -def M4_mpyrr_addi : MInst <(outs IntRegs:$Rd), - (ins u6_0Ext:$u6, IntRegs:$Rs, IntRegs:$Rt), - "$Rd = add(#$u6, mpyi($Rs, $Rt))" , [], "", ALU64_tc_3x_SLOT23>, ImmRegRel { - bits<5> Rd; - bits<6> u6; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - - let Inst{27-23} = 0b01110; - let Inst{22-21} = u6{5-4}; - let Inst{20-16} = Rs; - let Inst{13} = u6{3}; - let Inst{12-8} = Rt; - let Inst{7-5} = u6{2-0}; - let Inst{4-0} = Rd; - } - -let hasNewValue = 1 in -class T_AddMpy <bit MajOp, PatLeaf ImmPred, dag ins> - : ALU64Inst <(outs IntRegs:$dst), ins, - "$dst = add($src1, mpyi("#!if(MajOp,"$src3, #$src2))", - "#$src2, $src3))"), [], - "", ALU64_tc_3x_SLOT23> { - bits<5> dst; - bits<5> src1; - bits<8> src2; - bits<5> src3; - - let IClass = 0b1101; - - bits<6> ImmValue = !if(MajOp, src2{5-0}, src2{7-2}); - - let Inst{27-24} = 0b1111; - let Inst{23} = MajOp; - let Inst{22-21} = ImmValue{5-4}; - let Inst{20-16} = src3; - let Inst{13} = ImmValue{3}; - let Inst{12-8} = dst; - let Inst{7-5} = ImmValue{2-0}; - let Inst{4-0} = src1; - } - -def M4_mpyri_addr_u2 : T_AddMpy<0b0, u6_2ImmPred, - (ins IntRegs:$src1, u6_2Imm:$src2, IntRegs:$src3)>; - -let isExtendable = 1, opExtentBits = 6, opExtendable = 3, - CextOpcode = "ADD_MPY", InputType = "imm" in -def M4_mpyri_addr : T_AddMpy<0b1, u32_0ImmPred, - (ins IntRegs:$src1, IntRegs:$src3, u6_0Ext:$src2)>, ImmRegRel; - -// Rx=add(Ru,mpyi(Rx,Rs)) -let CextOpcode = "ADD_MPY", InputType = "reg", hasNewValue = 1 in -def M4_mpyrr_addr: MInst_acc <(outs IntRegs:$Rx), - (ins IntRegs:$Ru, IntRegs:$_src_, IntRegs:$Rs), - "$Rx = add($Ru, mpyi($_src_, $Rs))", [], - "$_src_ = $Rx", M_tc_3x_SLOT23>, ImmRegRel { - bits<5> Rx; - bits<5> Ru; - bits<5> Rs; - - let IClass = 0b1110; - - let Inst{27-21} = 0b0011000; - let Inst{12-8} = Rx; - let Inst{4-0} = Ru; - let Inst{20-16} = Rs; - } - - -// Vector reduce multiply word by signed half (32x16) -//Rdd=vrmpyweh(Rss,Rtt)[:<<1] -def M4_vrmpyeh_s0 : T_M2_vmpy<"vrmpyweh", 0b010, 0b100, 0, 0, 0>; -def M4_vrmpyeh_s1 : T_M2_vmpy<"vrmpyweh", 0b110, 0b100, 1, 0, 0>; - -//Rdd=vrmpywoh(Rss,Rtt)[:<<1] -def M4_vrmpyoh_s0 : T_M2_vmpy<"vrmpywoh", 0b001, 0b010, 0, 0, 0>; -def M4_vrmpyoh_s1 : T_M2_vmpy<"vrmpywoh", 0b101, 0b010, 1, 0, 0>; - -//Rdd+=vrmpyweh(Rss,Rtt)[:<<1] -def M4_vrmpyeh_acc_s0: T_M2_vmpy_acc<"vrmpyweh", 0b001, 0b110, 0, 0>; -def M4_vrmpyeh_acc_s1: T_M2_vmpy_acc<"vrmpyweh", 0b101, 0b110, 1, 0>; - -//Rdd=vrmpywoh(Rss,Rtt)[:<<1] -def M4_vrmpyoh_acc_s0: T_M2_vmpy_acc<"vrmpywoh", 0b011, 0b110, 0, 0>; -def M4_vrmpyoh_acc_s1: T_M2_vmpy_acc<"vrmpywoh", 0b111, 0b110, 1, 0>; - -// Vector multiply halfwords, signed by unsigned -// Rdd=vmpyhsu(Rs,Rt)[:<<]:sat -def M2_vmpy2su_s0 : T_XTYPE_mpy64 < "vmpyhsu", 0b000, 0b111, 1, 0, 0>; -def M2_vmpy2su_s1 : T_XTYPE_mpy64 < "vmpyhsu", 0b100, 0b111, 1, 1, 0>; - -// Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat -def M2_vmac2su_s0 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b011, 0b101, 1, 0, 0>; -def M2_vmac2su_s1 : T_XTYPE_mpy64_acc < "vmpyhsu", "+", 0b111, 0b101, 1, 1, 0>; - -// Vector polynomial multiply halfwords -// Rdd=vpmpyh(Rs,Rt) -def M4_vpmpyh : T_XTYPE_mpy64 < "vpmpyh", 0b110, 0b111, 0, 0, 0>; - -// Rxx^=vpmpyh(Rs,Rt) -def M4_vpmpyh_acc : T_XTYPE_mpy64_acc < "vpmpyh", "^", 0b101, 0b111, 0, 0, 0>; - -// Polynomial multiply words -// Rdd=pmpyw(Rs,Rt) -def M4_pmpyw : T_XTYPE_mpy64 < "pmpyw", 0b010, 0b111, 0, 0, 0>; - -// Rxx^=pmpyw(Rs,Rt) -def M4_pmpyw_acc : T_XTYPE_mpy64_acc < "pmpyw", "^", 0b001, 0b111, 0, 0, 0>; - -//===----------------------------------------------------------------------===// -// XTYPE/MPY - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// ALU64/Vector compare -//===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// Template class for vector compare -//===----------------------------------------------------------------------===// - -let hasSideEffects = 0 in -class T_vcmpImm <string Str, bits<2> cmpOp, bits<2> minOp, Operand ImmOprnd> - : ALU64_rr <(outs PredRegs:$Pd), - (ins DoubleRegs:$Rss, ImmOprnd:$Imm), - "$Pd = "#Str#"($Rss, #$Imm)", - [], "", ALU64_tc_2early_SLOT23> { - bits<2> Pd; - bits<5> Rss; - bits<32> Imm; - bits<8> ImmBits; - let ImmBits{6-0} = Imm{6-0}; - let ImmBits{7} = !if (!eq(cmpOp,0b10), 0b0, Imm{7}); // 0 for vcmp[bhw].gtu - - let IClass = 0b1101; - - let Inst{27-24} = 0b1100; - let Inst{22-21} = cmpOp; - let Inst{20-16} = Rss; - let Inst{12-5} = ImmBits; - let Inst{4-3} = minOp; - let Inst{1-0} = Pd; - } - -// Vector compare bytes -def A4_vcmpbgt : T_vcmp <"vcmpb.gt", 0b1010>; - -let AsmString = "$Pd = any8(vcmpb.eq($Rss, $Rtt))" in -def A4_vcmpbeq_any : T_vcmp <"any8(vcmpb.gt", 0b1000>; - -def A4_vcmpbeqi : T_vcmpImm <"vcmpb.eq", 0b00, 0b00, u8_0Imm>; -def A4_vcmpbgti : T_vcmpImm <"vcmpb.gt", 0b01, 0b00, s8_0Imm>; -def A4_vcmpbgtui : T_vcmpImm <"vcmpb.gtu", 0b10, 0b00, u7_0Imm>; - -// Vector compare halfwords -def A4_vcmpheqi : T_vcmpImm <"vcmph.eq", 0b00, 0b01, s8_0Imm>; -def A4_vcmphgti : T_vcmpImm <"vcmph.gt", 0b01, 0b01, s8_0Imm>; -def A4_vcmphgtui : T_vcmpImm <"vcmph.gtu", 0b10, 0b01, u7_0Imm>; - -// Vector compare words -def A4_vcmpweqi : T_vcmpImm <"vcmpw.eq", 0b00, 0b10, s8_0Imm>; -def A4_vcmpwgti : T_vcmpImm <"vcmpw.gt", 0b01, 0b10, s8_0Imm>; -def A4_vcmpwgtui : T_vcmpImm <"vcmpw.gtu", 0b10, 0b10, u7_0Imm>; - -//===----------------------------------------------------------------------===// -// XTYPE/SHIFT + -//===----------------------------------------------------------------------===// -// Shift by immediate and accumulate/logical. -// Rx=add(#u8,asl(Rx,#U5)) Rx=add(#u8,lsr(Rx,#U5)) -// Rx=sub(#u8,asl(Rx,#U5)) Rx=sub(#u8,lsr(Rx,#U5)) -// Rx=and(#u8,asl(Rx,#U5)) Rx=and(#u8,lsr(Rx,#U5)) -// Rx=or(#u8,asl(Rx,#U5)) Rx=or(#u8,lsr(Rx,#U5)) -let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8, - hasNewValue = 1, opNewValue = 0 in -class T_S4_ShiftOperate<string MnOp, string MnSh, bit asl_lsr, - bits<2> MajOp, InstrItinClass Itin> - : MInst_acc<(outs IntRegs:$Rd), (ins u8_0Ext:$u8, IntRegs:$Rx, u5_0Imm:$U5), - "$Rd = "#MnOp#"(#$u8, "#MnSh#"($Rx, #$U5))", - [], "$Rd = $Rx", Itin> { - - bits<5> Rd; - bits<8> u8; - bits<5> Rx; - bits<5> U5; - - let IClass = 0b1101; - let Inst{27-24} = 0b1110; - let Inst{23-21} = u8{7-5}; - let Inst{20-16} = Rd; - let Inst{13} = u8{4}; - let Inst{12-8} = U5; - let Inst{7-5} = u8{3-1}; - let Inst{4} = asl_lsr; - let Inst{3} = u8{0}; - let Inst{2-1} = MajOp; -} - -multiclass T_ShiftOperate<string mnemonic, bits<2> MajOp, InstrItinClass Itin> { - def _asl_ri : T_S4_ShiftOperate<mnemonic, "asl", 0, MajOp, Itin>; - def _lsr_ri : T_S4_ShiftOperate<mnemonic, "lsr", 1, MajOp, Itin>; -} - -defm S4_addi : T_ShiftOperate<"add", 0b10, ALU64_tc_2_SLOT23>; -defm S4_andi : T_ShiftOperate<"and", 0b00, ALU64_tc_2_SLOT23>; -defm S4_ori : T_ShiftOperate<"or", 0b01, ALU64_tc_1_SLOT23>; -defm S4_subi : T_ShiftOperate<"sub", 0b11, ALU64_tc_1_SLOT23>; - -// Vector conditional negate -// Rdd=vcnegh(Rss,Rt) -let Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in -def S2_vcnegh : T_S3op_shiftVect < "vcnegh", 0b11, 0b01>; - -// Rd=[cround|round](Rs,Rt) -let hasNewValue = 1, Itinerary = S_3op_tc_2_SLOT23 in { - def A4_cround_rr : T_S3op_3 < "cround", IntRegs, 0b11, 0b00>; - def A4_round_rr : T_S3op_3 < "round", IntRegs, 0b11, 0b10>; -} - -// Rd=round(Rs,Rt):sat -let hasNewValue = 1, Defs = [USR_OVF], Itinerary = S_3op_tc_2_SLOT23 in -def A4_round_rr_sat : T_S3op_3 < "round", IntRegs, 0b11, 0b11, 1>; - -// Rd=[cmpyiwh|cmpyrwh](Rss,Rt):<<1:rnd:sat -let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23 in { - def M4_cmpyi_wh : T_S3op_8<"cmpyiwh", 0b100, 1, 1, 1>; - def M4_cmpyr_wh : T_S3op_8<"cmpyrwh", 0b110, 1, 1, 1>; -} - -// Rdd=[add|sub](Rss,Rtt,Px):carry -let isPredicateLate = 1, hasSideEffects = 0 in -class T_S3op_carry <string mnemonic, bits<3> MajOp> - : SInst < (outs DoubleRegs:$Rdd, PredRegs:$Px), - (ins DoubleRegs:$Rss, DoubleRegs:$Rtt, PredRegs:$Pu), - "$Rdd = "#mnemonic#"($Rss, $Rtt, $Pu):carry", - [], "$Px = $Pu", S_3op_tc_1_SLOT23 > { - bits<5> Rdd; - bits<5> Rss; - bits<5> Rtt; - bits<2> Pu; - - let IClass = 0b1100; - - let Inst{27-24} = 0b0010; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - let Inst{6-5} = Pu; - let Inst{4-0} = Rdd; - } - -def A4_addp_c : T_S3op_carry < "add", 0b110 >; -def A4_subp_c : T_S3op_carry < "sub", 0b111 >; - -let Itinerary = S_3op_tc_3_SLOT23, hasSideEffects = 0 in -class T_S3op_6 <string mnemonic, bits<3> MinOp, bit isUnsigned> - : SInst <(outs DoubleRegs:$Rxx), - (ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Ru), - "$Rxx = "#mnemonic#"($Rss, $Ru)" , - [] , "$dst2 = $Rxx"> { - bits<5> Rxx; - bits<5> Rss; - bits<5> Ru; - - let IClass = 0b1100; - - let Inst{27-21} = 0b1011001; - let Inst{20-16} = Rss; - let Inst{13} = isUnsigned; - let Inst{12-8} = Rxx; - let Inst{7-5} = MinOp; - let Inst{4-0} = Ru; - } - -// Vector reduce maximum halfwords -// Rxx=vrmax[u]h(Rss,Ru) -def A4_vrmaxh : T_S3op_6 < "vrmaxh", 0b001, 0>; -def A4_vrmaxuh : T_S3op_6 < "vrmaxuh", 0b001, 1>; - -// Vector reduce maximum words -// Rxx=vrmax[u]w(Rss,Ru) -def A4_vrmaxw : T_S3op_6 < "vrmaxw", 0b010, 0>; -def A4_vrmaxuw : T_S3op_6 < "vrmaxuw", 0b010, 1>; - -// Vector reduce minimum halfwords -// Rxx=vrmin[u]h(Rss,Ru) -def A4_vrminh : T_S3op_6 < "vrminh", 0b101, 0>; -def A4_vrminuh : T_S3op_6 < "vrminuh", 0b101, 1>; - -// Vector reduce minimum words -// Rxx=vrmin[u]w(Rss,Ru) -def A4_vrminw : T_S3op_6 < "vrminw", 0b110, 0>; -def A4_vrminuw : T_S3op_6 < "vrminuw", 0b110, 1>; - -// Shift an immediate left by register amount. -let hasNewValue = 1, hasSideEffects = 0 in -def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6_0Imm:$s6, IntRegs:$Rt), - "$Rd = lsl(#$s6, $Rt)" , [], "", S_3op_tc_1_SLOT23> { - bits<5> Rd; - bits<6> s6; - bits<5> Rt; - - let IClass = 0b1100; - - let Inst{27-22} = 0b011010; - let Inst{20-16} = s6{5-1}; - let Inst{12-8} = Rt; - let Inst{7-6} = 0b11; - let Inst{4-0} = Rd; - let Inst{5} = s6{0}; - } - -//===----------------------------------------------------------------------===// -// XTYPE/SHIFT - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// MEMOP -//===----------------------------------------------------------------------===// - - -//===----------------------------------------------------------------------===// -// Template class for MemOp instructions with the register value. -//===----------------------------------------------------------------------===// -class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp, - string memOp, bits<2> memOpBits> : - MEMInst_V4<(outs), - (ins IntRegs:$base, ImmOp:$offset, IntRegs:$delta), - opc#"($base+#$offset)"#memOp#"$delta", - []>, - Requires<[UseMEMOP]> { - - bits<5> base; - bits<5> delta; - bits<32> offset; - bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2 - - let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0}, - !if (!eq(opcBits, 0b01), offset{6-1}, - !if (!eq(opcBits, 0b10), offset{7-2},0))); - - let opExtentAlign = opcBits; - let IClass = 0b0011; - let Inst{27-24} = 0b1110; - let Inst{22-21} = opcBits; - let Inst{20-16} = base; - let Inst{13} = 0b0; - let Inst{12-7} = offsetBits; - let Inst{6-5} = memOpBits; - let Inst{4-0} = delta; -} - -//===----------------------------------------------------------------------===// -// Template class for MemOp instructions with the immediate value. -//===----------------------------------------------------------------------===// -class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp, - string memOp, bits<2> memOpBits> : - MEMInst_V4 <(outs), - (ins IntRegs:$base, ImmOp:$offset, u5_0Imm:$delta), - opc#"($base+#$offset)"#memOp#"#$delta" - #!if(memOpBits{1},")", ""), // clrbit, setbit - include ')' - []>, - Requires<[UseMEMOP]> { - - bits<5> base; - bits<5> delta; - bits<32> offset; - bits<6> offsetBits; // memb - u6:0 , memh - u6:1, memw - u6:2 - - let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0}, - !if (!eq(opcBits, 0b01), offset{6-1}, - !if (!eq(opcBits, 0b10), offset{7-2},0))); - - let opExtentAlign = opcBits; - let IClass = 0b0011; - let Inst{27-24} = 0b1111; - let Inst{22-21} = opcBits; - let Inst{20-16} = base; - let Inst{13} = 0b0; - let Inst{12-7} = offsetBits; - let Inst{6-5} = memOpBits; - let Inst{4-0} = delta; -} - -// multiclass to define MemOp instructions with register operand. -multiclass MemOp_rr<string opc, bits<2> opcBits, Operand ImmOp> { - def L4_add#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add - def L4_sub#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " -= ", 0b01>; // sub - def L4_and#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " &= ", 0b10>; // and - def L4_or#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " |= ", 0b11>; // or -} - -// multiclass to define MemOp instructions with immediate Operand. -multiclass MemOp_ri<string opc, bits<2> opcBits, Operand ImmOp> { - def L4_iadd#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >; - def L4_isub#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " -= ", 0b01 >; - def L4_iand#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = clrbit(", 0b10>; - def L4_ior#NAME : MemOp_ri_base<opc, opcBits, ImmOp, " = setbit(", 0b11>; -} - -multiclass MemOp_base <string opc, bits<2> opcBits, Operand ImmOp> { - defm _#NAME : MemOp_rr <opc, opcBits, ImmOp>; - defm _#NAME : MemOp_ri <opc, opcBits, ImmOp>; -} - -// Define MemOp instructions. -let isExtendable = 1, opExtendable = 1, isExtentSigned = 0 in { - let opExtentBits = 6, accessSize = ByteAccess in - defm memopb_io : MemOp_base <"memb", 0b00, u6_0Ext>; - - let opExtentBits = 7, accessSize = HalfWordAccess in - defm memoph_io : MemOp_base <"memh", 0b01, u6_1Ext>; - - let opExtentBits = 8, accessSize = WordAccess in - defm memopw_io : MemOp_base <"memw", 0b10, u6_2Ext>; -} - - -//===----------------------------------------------------------------------===// -// XTYPE/PRED + -//===----------------------------------------------------------------------===// - -// Hexagon V4 only supports these flavors of byte/half compare instructions: -// EQ/GT/GTU. Other flavors like GE/GEU/LT/LTU/LE/LEU are not supported by -// hardware. However, compiler can still implement these patterns through -// appropriate patterns combinations based on current implemented patterns. -// The implemented patterns are: EQ/GT/GTU. -// Missing patterns are: GE/GEU/LT/LTU/LE/LEU. - -// Following instruction is not being extended as it results into the -// incorrect code for negative numbers. -// Pd=cmpb.eq(Rs,#u8) - -// p=!cmp.eq(r1,#s10) -def C4_cmpneqi : T_CMP <"cmp.eq", 0b00, 1, s10_0Ext>; -def C4_cmpltei : T_CMP <"cmp.gt", 0b01, 1, s10_0Ext>; -def C4_cmplteui : T_CMP <"cmp.gtu", 0b10, 1, u9_0Ext>; - -//===----------------------------------------------------------------------===// -// XTYPE/PRED - -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// Multiclass for DeallocReturn -//===----------------------------------------------------------------------===// -class L4_RETURN<string mnemonic, bit isNot, bit isPredNew, bit isTak> - : LD0Inst<(outs), (ins PredRegs:$src), - !if(isNot, "if (!$src", "if ($src")# - !if(isPredNew, ".new) ", ") ")#mnemonic# - !if(isPredNew, #!if(isTak,":t", ":nt"),""), - [], "", LD_tc_3or4stall_SLOT0> { - - bits<2> src; - let BaseOpcode = "L4_RETURN"; - let isPredicatedFalse = isNot; - let isPredicatedNew = isPredNew; - let isTaken = isTak; - let IClass = 0b1001; - - let Inst{27-16} = 0b011000011110; - - let Inst{13} = isNot; - let Inst{12} = isTak; - let Inst{11} = isPredNew; - let Inst{10} = 0b0; - let Inst{9-8} = src; - let Inst{4-0} = 0b11110; - } - -// Produce all predicated forms, p, !p, p.new, !p.new, :t, :nt -multiclass L4_RETURN_PRED<string mnemonic, bit PredNot> { - let isPredicated = 1 in { - def _#NAME# : L4_RETURN <mnemonic, PredNot, 0, 1>; - def _#NAME#new_pnt : L4_RETURN <mnemonic, PredNot, 1, 0>; - def _#NAME#new_pt : L4_RETURN <mnemonic, PredNot, 1, 1>; - } -} - -multiclass LD_MISC_L4_RETURN<string mnemonic> { - let isBarrier = 1, isPredicable = 1 in - def NAME : LD0Inst <(outs), (ins), mnemonic, [], "", - LD_tc_3or4stall_SLOT0> { - let BaseOpcode = "L4_RETURN"; - let IClass = 0b1001; - let Inst{27-16} = 0b011000011110; - let Inst{13-10} = 0b0000; - let Inst{4-0} = 0b11110; - } - defm t : L4_RETURN_PRED<mnemonic, 0 >; - defm f : L4_RETURN_PRED<mnemonic, 1 >; -} - -let isReturn = 1, isTerminator = 1, - Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0 in -defm L4_return: LD_MISC_L4_RETURN <"dealloc_return">, PredNewRel; - -// Restore registers and dealloc return function call. -let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1, - Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in { - def RESTORE_DEALLOC_RET_JMP_V4 : T_JMP<"">; - - let isExtended = 1, opExtendable = 0 in - def RESTORE_DEALLOC_RET_JMP_V4_EXT : T_JMP<"">; - - let Defs = [R14, R15, R28, R29, R30, R31, PC] in { - def RESTORE_DEALLOC_RET_JMP_V4_PIC : T_JMP<"">; - - let isExtended = 1, opExtendable = 0 in - def RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC : T_JMP<"">; - } -} - -// Restore registers and dealloc frame before a tail call. -let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in { - def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : T_Call<0, "">, PredRel; - - let isExtended = 1, opExtendable = 0 in - def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT : T_Call<0, "">, PredRel; - - let Defs = [R14, R15, R28, R29, R30, R31, PC] in { - def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC : T_Call<0, "">, PredRel; - - let isExtended = 1, opExtendable = 0 in - def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC : T_Call<0, "">, PredRel; - } -} - -// Save registers function call. -let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in { - def SAVE_REGISTERS_CALL_V4 : T_Call<0, "">, PredRel; - - let isExtended = 1, opExtendable = 0 in - def SAVE_REGISTERS_CALL_V4_EXT : T_Call<0, "">, PredRel; - - let Defs = [P0] in - def SAVE_REGISTERS_CALL_V4STK : T_Call<0, "">, PredRel; - - let Defs = [P0], isExtended = 1, opExtendable = 0 in - def SAVE_REGISTERS_CALL_V4STK_EXT : T_Call<0, "">, PredRel; - - let Defs = [R14, R15, R28] in - def SAVE_REGISTERS_CALL_V4_PIC : T_Call<0, "">, PredRel; - - let Defs = [R14, R15, R28], isExtended = 1, opExtendable = 0 in - def SAVE_REGISTERS_CALL_V4_EXT_PIC : T_Call<0, "">, PredRel; - - let Defs = [R14, R15, R28, P0] in - def SAVE_REGISTERS_CALL_V4STK_PIC : T_Call<0, "">, PredRel; - - let Defs = [R14, R15, R28, P0], isExtended = 1, opExtendable = 0 in - def SAVE_REGISTERS_CALL_V4STK_EXT_PIC : T_Call<0, "">, PredRel; -} - -//===----------------------------------------------------------------------===// -// Template class for non predicated store instructions with -// GP-Relative or absolute addressing. -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, isPredicable = 1 in -class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<2>MajOp, bit isAbs, bit isHalf> - : STInst<(outs), (ins ImmOp:$addr, RC:$src), - mnemonic # "(#$addr) = $src"#!if(isHalf, ".h",""), - [], "", V2LDST_tc_st_SLOT01> { - bits<19> addr; - bits<5> src; - bits<16> offsetBits; - - string ImmOpStr = !cast<string>(ImmOp); - let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3}, - !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2}, - !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1}, - /* u16_0Imm */ addr{15-0}))); - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1)); - let Uses = !if (isAbs, [], [GP]); - - let IClass = 0b0100; - let Inst{27} = 1; - let Inst{26-25} = offsetBits{15-14}; - let Inst{24} = 0b0; - let Inst{23-22} = MajOp; - let Inst{21} = isHalf; - let Inst{20-16} = offsetBits{13-9}; - let Inst{13} = offsetBits{8}; - let Inst{12-8} = src; - let Inst{7-0} = offsetBits{7-0}; - } - -//===----------------------------------------------------------------------===// -// Template class for predicated store instructions with -// GP-Relative or absolute addressing. -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, isPredicated = 1, opExtentBits = 6, opExtendable = 1 in -class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp, - bit isHalf, bit isNot, bit isNew> - : STInst<(outs), (ins PredRegs:$src1, u32_0MustExt:$absaddr, RC: $src2), - !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ", - ") ")#mnemonic#"(#$absaddr) = $src2"#!if(isHalf, ".h",""), - [], "", ST_tc_st_SLOT01>, AddrModeRel { - bits<2> src1; - bits<6> absaddr; - bits<5> src2; - - let isPredicatedNew = isNew; - let isPredicatedFalse = isNot; - // Store upper-half and store doubleword cannot be NV. - let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isHalf,0,1)); - - let IClass = 0b1010; - - let Inst{27-24} = 0b1111; - let Inst{23-22} = MajOp; - let Inst{21} = isHalf; - let Inst{17-16} = absaddr{5-4}; - let Inst{13} = isNew; - let Inst{12-8} = src2; - let Inst{7} = 0b1; - let Inst{6-3} = absaddr{3-0}; - let Inst{2} = isNot; - let Inst{1-0} = src1; - } - -//===----------------------------------------------------------------------===// -// Template class for predicated store instructions with absolute addressing. -//===----------------------------------------------------------------------===// -class T_StoreAbs <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<2> MajOp, bit isHalf> - : T_StoreAbsGP <mnemonic, RC, u32_0MustExt, MajOp, 1, isHalf>, - AddrModeRel { - string ImmOpStr = !cast<string>(ImmOp); - let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19, - !if (!eq(ImmOpStr, "u16_2Imm"), 18, - !if (!eq(ImmOpStr, "u16_1Imm"), 17, - /* u16_0Imm */ 16))); - - let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3, - !if (!eq(ImmOpStr, "u16_2Imm"), 2, - !if (!eq(ImmOpStr, "u16_1Imm"), 1, - /* u16_0Imm */ 0))); -} - -//===----------------------------------------------------------------------===// -// Multiclass for store instructions with absolute addressing. -//===----------------------------------------------------------------------===// -let addrMode = Absolute, isExtended = 1 in -multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC, - Operand ImmOp, bits<2> MajOp, bit isHalf = 0> { - let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in { - let opExtendable = 0, isPredicable = 1 in - def PS_#NAME#abs : T_StoreAbs <mnemonic, RC, ImmOp, MajOp, isHalf>; - - // Predicated - def S4_p#NAME#t_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 0>; - def S4_p#NAME#f_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 0>; - - // .new Predicated - def S4_p#NAME#tnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 0, 1>; - def S4_p#NAME#fnew_abs : T_StoreAbs_Pred<mnemonic, RC, MajOp, isHalf, 1, 1>; - } -} - -//===----------------------------------------------------------------------===// -// Template class for non predicated new-value store instructions with -// GP-Relative or absolute addressing. -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, isPredicable = 1, mayStore = 1, isNVStore = 1, - isNewValue = 1, opNewValue = 1 in -class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp> - : NVInst_V4<(outs), (ins ImmOp:$addr, IntRegs:$src), - mnemonic #"(#$addr) = $src.new", - [], "", V2LDST_tc_st_SLOT0> { - bits<19> addr; - bits<3> src; - bits<16> offsetBits; - - string ImmOpStr = !cast<string>(ImmOp); - let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3}, - !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2}, - !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1}, - /* u16_0Imm */ addr{15-0}))); - let IClass = 0b0100; - - let Inst{27} = 1; - let Inst{26-25} = offsetBits{15-14}; - let Inst{24-21} = 0b0101; - let Inst{20-16} = offsetBits{13-9}; - let Inst{13} = offsetBits{8}; - let Inst{12-11} = MajOp; - let Inst{10-8} = src; - let Inst{7-0} = offsetBits{7-0}; - } - -//===----------------------------------------------------------------------===// -// Template class for predicated new-value store instructions with -// absolute addressing. -//===----------------------------------------------------------------------===// -let hasSideEffects = 0, isPredicated = 1, mayStore = 1, isNVStore = 1, - isNewValue = 1, opNewValue = 2, opExtentBits = 6, opExtendable = 1 in -class T_StoreAbs_NV_Pred <string mnemonic, bits<2> MajOp, bit isNot, bit isNew> - : NVInst_V4<(outs), (ins PredRegs:$src1, u32_0MustExt:$absaddr, IntRegs:$src2), - !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ", - ") ")#mnemonic#"(#$absaddr) = $src2.new", - [], "", ST_tc_st_SLOT0>, AddrModeRel { - bits<2> src1; - bits<6> absaddr; - bits<3> src2; - - let isPredicatedNew = isNew; - let isPredicatedFalse = isNot; - - let IClass = 0b1010; - - let Inst{27-24} = 0b1111; - let Inst{23-21} = 0b101; - let Inst{17-16} = absaddr{5-4}; - let Inst{13} = isNew; - let Inst{12-11} = MajOp; - let Inst{10-8} = src2; - let Inst{7} = 0b1; - let Inst{6-3} = absaddr{3-0}; - let Inst{2} = isNot; - let Inst{1-0} = src1; -} - -//===----------------------------------------------------------------------===// -// Template class for non-predicated new-value store instructions with -// absolute addressing. -//===----------------------------------------------------------------------===// -class T_StoreAbs_NV <string mnemonic, Operand ImmOp, bits<2> MajOp> - : T_StoreAbsGP_NV <mnemonic, u32_0MustExt, MajOp>, AddrModeRel { - - string ImmOpStr = !cast<string>(ImmOp); - let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19, - !if (!eq(ImmOpStr, "u16_2Imm"), 18, - !if (!eq(ImmOpStr, "u16_1Imm"), 17, - /* u16_0Imm */ 16))); - - let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3, - !if (!eq(ImmOpStr, "u16_2Imm"), 2, - !if (!eq(ImmOpStr, "u16_1Imm"), 1, - /* u16_0Imm */ 0))); -} - -//===----------------------------------------------------------------------===// -// Multiclass for new-value store instructions with absolute addressing. -//===----------------------------------------------------------------------===// -let addrMode = Absolute, isExtended = 1 in -multiclass ST_Abs_NV <string mnemonic, string CextOp, Operand ImmOp, - bits<2> MajOp> { - let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in { - let opExtendable = 0, isPredicable = 1 in - def PS_#NAME#newabs : T_StoreAbs_NV <mnemonic, ImmOp, MajOp>; - - // Predicated - def S4_p#NAME#newt_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 0>; - def S4_p#NAME#newf_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 0>; - - // .new Predicated - def S4_p#NAME#newtnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 0, 1>; - def S4_p#NAME#newfnew_abs : T_StoreAbs_NV_Pred <mnemonic, MajOp, 1, 1>; - } -} - -//===----------------------------------------------------------------------===// -// Stores with absolute addressing -//===----------------------------------------------------------------------===// -let accessSize = ByteAccess in -defm storerb : ST_Abs <"memb", "STrib", IntRegs, u16_0Imm, 0b00>, - ST_Abs_NV <"memb", "STrib", u16_0Imm, 0b00>; - -let accessSize = HalfWordAccess in -defm storerh : ST_Abs <"memh", "STrih", IntRegs, u16_1Imm, 0b01>, - ST_Abs_NV <"memh", "STrih", u16_1Imm, 0b01>; - -let accessSize = WordAccess in -defm storeri : ST_Abs <"memw", "STriw", IntRegs, u16_2Imm, 0b10>, - ST_Abs_NV <"memw", "STriw", u16_2Imm, 0b10>; - -let isNVStorable = 0, accessSize = DoubleWordAccess in -defm storerd : ST_Abs <"memd", "STrid", DoubleRegs, u16_3Imm, 0b11>; - -let isNVStorable = 0, accessSize = HalfWordAccess in -defm storerf : ST_Abs <"memh", "STrif", IntRegs, u16_1Imm, 0b01, 1>; - -//===----------------------------------------------------------------------===// -// GP-relative stores. -// mem[bhwd](#global)=Rt -// Once predicated, these instructions map to absolute addressing mode. -// if ([!]Pv[.new]) mem[bhwd](##global)=Rt -//===----------------------------------------------------------------------===// - -let Uses = [GP], isAsmParserOnly = 1 in -class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC, - Operand ImmOp, bits<2> MajOp, bit isHalf = 0> - : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, 0, isHalf> { - // Set BaseOpcode same as absolute addressing instructions so that - // non-predicated GP-Rel instructions can have relate with predicated - // Absolute instruction. - let BaseOpcode = BaseOp#_abs; - } - -let Uses = [GP], isAsmParserOnly = 1 in -multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp, - bits<2> MajOp, bit isHalf = 0> { - // Set BaseOpcode same as absolute addressing instructions so that - // non-predicated GP-Rel instructions can have relate with predicated - // Absolute instruction. - let BaseOpcode = BaseOp#_abs in { - def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp, - 0, isHalf>; - // New-value store - def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp> ; - } -} - -let accessSize = ByteAccess in -defm S2_storerb : ST_GP<"memb", "STrib", u16_0Imm, 0b00>, NewValueRel; - -let accessSize = HalfWordAccess in -defm S2_storerh : ST_GP<"memh", "STrih", u16_1Imm, 0b01>, NewValueRel; - -let accessSize = WordAccess in -defm S2_storeri : ST_GP<"memw", "STriw", u16_2Imm, 0b10>, NewValueRel; - -let isNVStorable = 0, accessSize = DoubleWordAccess in -def S2_storerdgp : T_StoreGP <"memd", "STrid", DoubleRegs, - u16_3Imm, 0b11>, PredNewRel; - -let isNVStorable = 0, accessSize = HalfWordAccess in -def S2_storerfgp : T_StoreGP <"memh", "STrif", IntRegs, - u16_1Imm, 0b01, 1>, PredNewRel; - -//===----------------------------------------------------------------------===// -// Template class for non predicated load instructions with -// absolute addressing mode. -//===----------------------------------------------------------------------===// -let isPredicable = 1, hasSideEffects = 0 in -class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<3> MajOp> - : LDInst <(outs RC:$dst), (ins ImmOp:$addr), - "$dst = "#mnemonic# "(#$addr)", - [], "", V2LDST_tc_ld_SLOT01> { - bits<5> dst; - bits<19> addr; - bits<16> offsetBits; - - string ImmOpStr = !cast<string>(ImmOp); - let offsetBits = !if (!eq(ImmOpStr, "u16_3Imm"), addr{18-3}, - !if (!eq(ImmOpStr, "u16_2Imm"), addr{17-2}, - !if (!eq(ImmOpStr, "u16_1Imm"), addr{16-1}, - /* u16_0Imm */ addr{15-0}))); - - let IClass = 0b0100; - - let Inst{27} = 0b1; - let Inst{26-25} = offsetBits{15-14}; - let Inst{24} = 0b1; - let Inst{23-21} = MajOp; - let Inst{20-16} = offsetBits{13-9}; - let Inst{13-5} = offsetBits{8-0}; - let Inst{4-0} = dst; - } - -class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<3> MajOp> - : T_LoadAbsGP <mnemonic, RC, u32_0MustExt, MajOp>, AddrModeRel { - - string ImmOpStr = !cast<string>(ImmOp); - let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19, - !if (!eq(ImmOpStr, "u16_2Imm"), 18, - !if (!eq(ImmOpStr, "u16_1Imm"), 17, - /* u16_0Imm */ 16))); - - let opExtentAlign = !if (!eq(ImmOpStr, "u16_3Imm"), 3, - !if (!eq(ImmOpStr, "u16_2Imm"), 2, - !if (!eq(ImmOpStr, "u16_1Imm"), 1, - /* u16_0Imm */ 0))); - } - -//===----------------------------------------------------------------------===// -// Template class for predicated load instructions with -// absolute addressing mode. -//===----------------------------------------------------------------------===// -let isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opExtentBits = 6, - opExtendable = 2 in -class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp, - bit isPredNot, bit isPredNew> - : LDInst <(outs RC:$dst), (ins PredRegs:$src1, u32_0MustExt:$absaddr), - !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", - ") ")#"$dst = "#mnemonic#"(#$absaddr)">, AddrModeRel { - bits<5> dst; - bits<2> src1; - bits<6> absaddr; - - let isPredicatedNew = isPredNew; - let isPredicatedFalse = isPredNot; - let hasNewValue = !if (!eq(!cast<string>(RC), "DoubleRegs"), 0, 1); - - let IClass = 0b1001; - - let Inst{27-24} = 0b1111; - let Inst{23-21} = MajOp; - let Inst{20-16} = absaddr{5-1}; - let Inst{13} = 0b1; - let Inst{12} = isPredNew; - let Inst{11} = isPredNot; - let Inst{10-9} = src1; - let Inst{8} = absaddr{0}; - let Inst{7} = 0b1; - let Inst{4-0} = dst; - } - -//===----------------------------------------------------------------------===// -// Multiclass for the load instructions with absolute addressing mode. -//===----------------------------------------------------------------------===// -multiclass LD_Abs_Pred<string mnemonic, RegisterClass RC, bits<3> MajOp, - bit PredNot> { - def _abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 0>; - // Predicate new - def new_abs : T_LoadAbs_Pred <mnemonic, RC, MajOp, PredNot, 1>; -} - -let addrMode = Absolute, isExtended = 1 in -multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC, - Operand ImmOp, bits<3> MajOp> { - let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in { - let opExtendable = 1, isPredicable = 1 in - def PS_#NAME#abs: T_LoadAbs <mnemonic, RC, ImmOp, MajOp>; - - // Predicated - defm L4_p#NAME#t : LD_Abs_Pred<mnemonic, RC, MajOp, 0>; - defm L4_p#NAME#f : LD_Abs_Pred<mnemonic, RC, MajOp, 1>; - } -} - -let accessSize = ByteAccess, hasNewValue = 1 in { - defm loadrb : LD_Abs<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>; - defm loadrub : LD_Abs<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>; -} - -let accessSize = HalfWordAccess, hasNewValue = 1 in { - defm loadrh : LD_Abs<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>; - defm loadruh : LD_Abs<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>; -} - -let accessSize = WordAccess, hasNewValue = 1 in -defm loadri : LD_Abs<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>; - -let accessSize = DoubleWordAccess in -defm loadrd : LD_Abs<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>; - -//===----------------------------------------------------------------------===// -// multiclass for load instructions with GP-relative addressing mode. -// Rx=mem[bhwd](##global) -// Once predicated, these instructions map to absolute addressing mode. -// if ([!]Pv[.new]) Rx=mem[bhwd](##global) -//===----------------------------------------------------------------------===// - -let isAsmParserOnly = 1, Uses = [GP] in -class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp, - bits<3> MajOp> - : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp>, PredNewRel { - let BaseOpcode = BaseOp#_abs; - } - -let accessSize = ByteAccess, hasNewValue = 1 in { - def L2_loadrbgp : T_LoadGP<"memb", "LDrib", IntRegs, u16_0Imm, 0b000>; - def L2_loadrubgp : T_LoadGP<"memub", "LDriub", IntRegs, u16_0Imm, 0b001>; -} - -let accessSize = HalfWordAccess, hasNewValue = 1 in { - def L2_loadrhgp : T_LoadGP<"memh", "LDrih", IntRegs, u16_1Imm, 0b010>; - def L2_loadruhgp : T_LoadGP<"memuh", "LDriuh", IntRegs, u16_1Imm, 0b011>; -} - -let accessSize = WordAccess, hasNewValue = 1 in -def L2_loadrigp : T_LoadGP<"memw", "LDriw", IntRegs, u16_2Imm, 0b100>; - -let accessSize = DoubleWordAccess in -def L2_loadrdgp : T_LoadGP<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>; - -//===----------------------------------------------------------------------===// -// :raw for of boundscheck:hi:lo insns -//===----------------------------------------------------------------------===// - -// A4_boundscheck_lo: Detect if a register is within bounds. -let hasSideEffects = 0 in -def A4_boundscheck_lo: ALU64Inst < - (outs PredRegs:$Pd), - (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Pd = boundscheck($Rss, $Rtt):raw:lo"> { - bits<2> Pd; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1101; - - let Inst{27-23} = 0b00100; - let Inst{13} = 0b1; - let Inst{7-5} = 0b100; - let Inst{1-0} = Pd; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - } - -// A4_boundscheck_hi: Detect if a register is within bounds. -let hasSideEffects = 0 in -def A4_boundscheck_hi: ALU64Inst < - (outs PredRegs:$Pd), - (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), - "$Pd = boundscheck($Rss, $Rtt):raw:hi"> { - bits<2> Pd; - bits<5> Rss; - bits<5> Rtt; - - let IClass = 0b1101; - - let Inst{27-23} = 0b00100; - let Inst{13} = 0b1; - let Inst{7-5} = 0b101; - let Inst{1-0} = Pd; - let Inst{20-16} = Rss; - let Inst{12-8} = Rtt; - } - -let hasSideEffects = 0, isAsmParserOnly = 1 in -def A4_boundscheck : MInst < - (outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt), - "$Pd=boundscheck($Rs,$Rtt)">; - -// A4_tlbmatch: Detect if a VA/ASID matches a TLB entry. -let isPredicateLate = 1, hasSideEffects = 0 in -def A4_tlbmatch : ALU64Inst<(outs PredRegs:$Pd), - (ins DoubleRegs:$Rs, IntRegs:$Rt), - "$Pd = tlbmatch($Rs, $Rt)", - [], "", ALU64_tc_2early_SLOT23> { - bits<2> Pd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1101; - let Inst{27-23} = 0b00100; - let Inst{20-16} = Rs; - let Inst{13} = 0b1; - let Inst{12-8} = Rt; - let Inst{7-5} = 0b011; - let Inst{1-0} = Pd; - } - -// Use LD0Inst for dcfetch, but set "mayLoad" to 0 because this doesn't -// really do a load. -let hasSideEffects = 1, mayLoad = 0 in -def Y2_dcfetchbo : LD0Inst<(outs), (ins IntRegs:$Rs, u11_3Imm:$u11_3), - "dcfetch($Rs + #$u11_3)", - [], "", LD_tc_ld_SLOT0> { - bits<5> Rs; - bits<14> u11_3; - - let IClass = 0b1001; - let Inst{27-21} = 0b0100000; - let Inst{20-16} = Rs; - let Inst{13} = 0b0; - let Inst{10-0} = u11_3{13-3}; -} - - -//===----------------------------------------------------------------------===// -// Compound instructions -//===----------------------------------------------------------------------===// - -let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1, - isPredicated = 1, isPredicatedNew = 1, isExtendable = 1, - opExtentBits = 11, opExtentAlign = 2, opExtendable = 1, - isTerminator = 1 in -class CJInst_tstbit_R0<string px, bit np, string tnt> - : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2), - ""#px#" = tstbit($Rs, #0); if (" - #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2", - [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon { - bits<4> Rs; - bits<11> r9_2; - - // np: !p[01] - let isPredicatedFalse = np; - // tnt: Taken/Not Taken - let isBrTaken = !if (!eq(tnt, "t"), "true", "false"); - let isTaken = !if (!eq(tnt, "t"), 1, 0); - - let IClass = 0b0001; - let Inst{27-26} = 0b00; - let Inst{25} = !if (!eq(px, "!p1"), 1, - !if (!eq(px, "p1"), 1, 0)); - let Inst{24-23} = 0b11; - let Inst{22} = np; - let Inst{21-20} = r9_2{10-9}; - let Inst{19-16} = Rs; - let Inst{13} = !if (!eq(tnt, "t"), 1, 0); - let Inst{9-8} = 0b11; - let Inst{7-1} = r9_2{8-2}; -} - -let Defs = [PC, P0], Uses = [P0] in { - def J4_tstbit0_tp0_jump_nt : CJInst_tstbit_R0<"p0", 0, "nt">; - def J4_tstbit0_tp0_jump_t : CJInst_tstbit_R0<"p0", 0, "t">; - def J4_tstbit0_fp0_jump_nt : CJInst_tstbit_R0<"p0", 1, "nt">; - def J4_tstbit0_fp0_jump_t : CJInst_tstbit_R0<"p0", 1, "t">; -} - -let Defs = [PC, P1], Uses = [P1] in { - def J4_tstbit0_tp1_jump_nt : CJInst_tstbit_R0<"p1", 0, "nt">; - def J4_tstbit0_tp1_jump_t : CJInst_tstbit_R0<"p1", 0, "t">; - def J4_tstbit0_fp1_jump_nt : CJInst_tstbit_R0<"p1", 1, "nt">; - def J4_tstbit0_fp1_jump_t : CJInst_tstbit_R0<"p1", 1, "t">; -} - - -let isBranch = 1, hasSideEffects = 0, - isExtentSigned = 1, isPredicated = 1, isPredicatedNew = 1, - isExtendable = 1, opExtentBits = 11, opExtentAlign = 2, - opExtendable = 2, isTerminator = 1 in -class CJInst_RR<string px, string op, bit np, string tnt> - : InstHexagon<(outs), (ins IntRegs:$Rs, IntRegs:$Rt, brtarget:$r9_2), - ""#px#" = cmp."#op#"($Rs, $Rt); if (" - #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2", - [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon { - bits<4> Rs; - bits<4> Rt; - bits<11> r9_2; - - // np: !p[01] - let isPredicatedFalse = np; - // tnt: Taken/Not Taken - let isBrTaken = !if (!eq(tnt, "t"), "true", "false"); - let isTaken = !if (!eq(tnt, "t"), 1, 0); - - let IClass = 0b0001; - let Inst{27-23} = !if (!eq(op, "eq"), 0b01000, - !if (!eq(op, "gt"), 0b01001, - !if (!eq(op, "gtu"), 0b01010, 0))); - let Inst{22} = np; - let Inst{21-20} = r9_2{10-9}; - let Inst{19-16} = Rs; - let Inst{13} = !if (!eq(tnt, "t"), 1, 0); - // px: Predicate reg 0/1 - let Inst{12} = !if (!eq(px, "!p1"), 1, - !if (!eq(px, "p1"), 1, 0)); - let Inst{11-8} = Rt; - let Inst{7-1} = r9_2{8-2}; -} - -// P[10] taken/not taken. -multiclass T_tnt_CJInst_RR<string op, bit np> { - let Defs = [PC, P0], Uses = [P0] in { - def NAME#p0_jump_nt : CJInst_RR<"p0", op, np, "nt">; - def NAME#p0_jump_t : CJInst_RR<"p0", op, np, "t">; - } - let Defs = [PC, P1], Uses = [P1] in { - def NAME#p1_jump_nt : CJInst_RR<"p1", op, np, "nt">; - def NAME#p1_jump_t : CJInst_RR<"p1", op, np, "t">; - } -} -// Predicate / !Predicate -multiclass T_pnp_CJInst_RR<string op>{ - defm J4_cmp#NAME#_t : T_tnt_CJInst_RR<op, 0>; - defm J4_cmp#NAME#_f : T_tnt_CJInst_RR<op, 1>; -} -// TypeCJ Instructions compare RR and jump -defm eq : T_pnp_CJInst_RR<"eq">; -defm gt : T_pnp_CJInst_RR<"gt">; -defm gtu : T_pnp_CJInst_RR<"gtu">; - -let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1, - isPredicated = 1, isPredicatedNew = 1, isExtendable = 1, opExtentBits = 11, - opExtentAlign = 2, opExtendable = 2, isTerminator = 1 in -class CJInst_RU5<string px, string op, bit np, string tnt> - : InstHexagon<(outs), (ins IntRegs:$Rs, u5_0Imm:$U5, brtarget:$r9_2), - ""#px#" = cmp."#op#"($Rs, #$U5); if (" - #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2", - [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon { - bits<4> Rs; - bits<5> U5; - bits<11> r9_2; - - // np: !p[01] - let isPredicatedFalse = np; - // tnt: Taken/Not Taken - let isBrTaken = !if (!eq(tnt, "t"), "true", "false"); - let isTaken = !if (!eq(tnt, "t"), 1, 0); - - let IClass = 0b0001; - let Inst{27-26} = 0b00; - // px: Predicate reg 0/1 - let Inst{25} = !if (!eq(px, "!p1"), 1, - !if (!eq(px, "p1"), 1, 0)); - let Inst{24-23} = !if (!eq(op, "eq"), 0b00, - !if (!eq(op, "gt"), 0b01, - !if (!eq(op, "gtu"), 0b10, 0))); - let Inst{22} = np; - let Inst{21-20} = r9_2{10-9}; - let Inst{19-16} = Rs; - let Inst{13} = !if (!eq(tnt, "t"), 1, 0); - let Inst{12-8} = U5; - let Inst{7-1} = r9_2{8-2}; -} -// P[10] taken/not taken. -multiclass T_tnt_CJInst_RU5<string op, bit np> { - let Defs = [PC, P0], Uses = [P0] in { - def NAME#p0_jump_nt : CJInst_RU5<"p0", op, np, "nt">; - def NAME#p0_jump_t : CJInst_RU5<"p0", op, np, "t">; - } - let Defs = [PC, P1], Uses = [P1] in { - def NAME#p1_jump_nt : CJInst_RU5<"p1", op, np, "nt">; - def NAME#p1_jump_t : CJInst_RU5<"p1", op, np, "t">; - } -} -// Predicate / !Predicate -multiclass T_pnp_CJInst_RU5<string op>{ - defm J4_cmp#NAME#i_t : T_tnt_CJInst_RU5<op, 0>; - defm J4_cmp#NAME#i_f : T_tnt_CJInst_RU5<op, 1>; -} -// TypeCJ Instructions compare RI and jump -defm eq : T_pnp_CJInst_RU5<"eq">; -defm gt : T_pnp_CJInst_RU5<"gt">; -defm gtu : T_pnp_CJInst_RU5<"gtu">; - -let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1, - isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, - isExtendable = 1, opExtentBits = 11, opExtentAlign = 2, opExtendable = 2, - isTerminator = 1 in -class CJInst_Rn1<string px, string op, bit np, string tnt> - : InstHexagon<(outs), (ins IntRegs:$Rs, n1Const:$n1, brtarget:$r9_2), - ""#px#" = cmp."#op#"($Rs,#$n1); if (" - #!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2", - [], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon { - bits<4> Rs; - bits<11> r9_2; - - // np: !p[01] - let isPredicatedFalse = np; - // tnt: Taken/Not Taken - let isBrTaken = !if (!eq(tnt, "t"), "true", "false"); - let isTaken = !if (!eq(tnt, "t"), 1, 0); - - let IClass = 0b0001; - let Inst{27-26} = 0b00; - let Inst{25} = !if (!eq(px, "!p1"), 1, - !if (!eq(px, "p1"), 1, 0)); - - let Inst{24-23} = 0b11; - let Inst{22} = np; - let Inst{21-20} = r9_2{10-9}; - let Inst{19-16} = Rs; - let Inst{13} = !if (!eq(tnt, "t"), 1, 0); - let Inst{9-8} = !if (!eq(op, "eq"), 0b00, - !if (!eq(op, "gt"), 0b01, 0)); - let Inst{7-1} = r9_2{8-2}; -} - -// P[10] taken/not taken. -multiclass T_tnt_CJInst_Rn1<string op, bit np> { - let Defs = [PC, P0], Uses = [P0] in { - def NAME#p0_jump_nt : CJInst_Rn1<"p0", op, np, "nt">; - def NAME#p0_jump_t : CJInst_Rn1<"p0", op, np, "t">; - } - let Defs = [PC, P1], Uses = [P1] in { - def NAME#p1_jump_nt : CJInst_Rn1<"p1", op, np, "nt">; - def NAME#p1_jump_t : CJInst_Rn1<"p1", op, np, "t">; - } -} -// Predicate / !Predicate -multiclass T_pnp_CJInst_Rn1<string op>{ - defm J4_cmp#NAME#n1_t : T_tnt_CJInst_Rn1<op, 0>; - defm J4_cmp#NAME#n1_f : T_tnt_CJInst_Rn1<op, 1>; -} -// TypeCJ Instructions compare -1 and jump -defm eq : T_pnp_CJInst_Rn1<"eq">; -defm gt : T_pnp_CJInst_Rn1<"gt">; - -// J4_jumpseti: Direct unconditional jump and set register to immediate. -let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1, - isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11, - opExtentAlign = 2, opExtendable = 2 in -def J4_jumpseti: CJInst_JMPSET < - (outs IntRegs:$Rd), - (ins u6_0Imm:$U6, brtarget:$r9_2), - "$Rd = #$U6 ; jump $r9_2"> { - bits<4> Rd; - bits<6> U6; - bits<11> r9_2; - - let IClass = 0b0001; - let Inst{27-24} = 0b0110; - let Inst{21-20} = r9_2{10-9}; - let Inst{19-16} = Rd; - let Inst{13-8} = U6; - let Inst{7-1} = r9_2{8-2}; - } - -// J4_jumpsetr: Direct unconditional jump and transfer register. -let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1, - isExtentSigned = 1, opNewValue = 0, isExtendable = 1, opExtentBits = 11, - opExtentAlign = 2, opExtendable = 2 in -def J4_jumpsetr: CJInst_JMPSET < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs, brtarget:$r9_2), - "$Rd = $Rs ; jump $r9_2"> { - bits<4> Rd; - bits<4> Rs; - bits<11> r9_2; - - let IClass = 0b0001; - let Inst{27-24} = 0b0111; - let Inst{21-20} = r9_2{10-9}; - let Inst{11-8} = Rd; - let Inst{19-16} = Rs; - let Inst{7-1} = r9_2{8-2}; - } - -// Duplex instructions -//===----------------------------------------------------------------------===// -include "HexagonIsetDx.td" diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfoV5.td b/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfoV5.td deleted file mode 100644 index cd19b6916f21..000000000000 --- a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfoV5.td +++ /dev/null @@ -1,497 +0,0 @@ -//=- HexagonInstrInfoV5.td - Target Desc. for Hexagon Target -*- tablegen -*-=// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon V5 instructions in TableGen format. -// -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// XTYPE/MPY -//===----------------------------------------------------------------------===// - - //Rdd[+]=vrmpybsu(Rss,Rtt) -let Predicates = [HasV5T] in { - def M5_vrmpybsu: T_XTYPE_Vect<"vrmpybsu", 0b110, 0b001, 0>; - def M5_vrmacbsu: T_XTYPE_Vect_acc<"vrmpybsu", 0b110, 0b001, 0>; - - //Rdd[+]=vrmpybu(Rss,Rtt) - def M5_vrmpybuu: T_XTYPE_Vect<"vrmpybu", 0b100, 0b001, 0>; - def M5_vrmacbuu: T_XTYPE_Vect_acc<"vrmpybu", 0b100, 0b001, 0>; - - def M5_vdmpybsu: T_M2_vmpy<"vdmpybsu", 0b101, 0b001, 0, 0, 1>; - def M5_vdmacbsu: T_M2_vmpy_acc_sat <"vdmpybsu", 0b001, 0b001, 0, 0>; -} - -// Vector multiply bytes -// Rdd=vmpyb[s]u(Rs,Rt) -let Predicates = [HasV5T] in { - def M5_vmpybsu: T_XTYPE_mpy64 <"vmpybsu", 0b010, 0b001, 0, 0, 0>; - def M5_vmpybuu: T_XTYPE_mpy64 <"vmpybu", 0b100, 0b001, 0, 0, 0>; - - // Rxx+=vmpyb[s]u(Rs,Rt) - def M5_vmacbsu: T_XTYPE_mpy64_acc <"vmpybsu", "+", 0b110, 0b001, 0, 0, 0>; - def M5_vmacbuu: T_XTYPE_mpy64_acc <"vmpybu", "+", 0b100, 0b001, 0, 0, 0>; - - // Rd=vaddhub(Rss,Rtt):sat - let hasNewValue = 1, opNewValue = 0 in - def A5_vaddhubs: T_S3op_1 <"vaddhub", IntRegs, 0b01, 0b001, 0, 1>; -} - -def S2_asr_i_p_rnd : S_2OpInstImm<"asr", 0b110, 0b111, u6_0Imm, [], 1>, - Requires<[HasV5T]> { - bits<6> src2; - let Inst{13-8} = src2; -} - -let isAsmParserOnly = 1 in -def S2_asr_i_p_rnd_goodsyntax - : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6_0Imm:$src2), - "$dst = asrrnd($src1, #$src2)">; - -def C4_fastcorner9 : T_LOGICAL_2OP<"fastcorner9", 0b000, 0, 0>, - Requires<[HasV5T]> { - let Inst{13,7,4} = 0b111; -} - -def C4_fastcorner9_not : T_LOGICAL_2OP<"!fastcorner9", 0b000, 0, 0>, - Requires<[HasV5T]> { - let Inst{20,13,7,4} = 0b1111; -} - -let hasNewValue = 1, validSubTargets = HasV5SubT in -def S5_popcountp : ALU64_rr<(outs IntRegs:$Rd), (ins DoubleRegs:$Rss), - "$Rd = popcount($Rss)", [], "", S_2op_tc_2_SLOT23>, - Requires<[HasV5T]> { - bits<5> Rd; - bits<5> Rss; - - let IClass = 0b1000; - - let Inst{27-21} = 0b1000011; - let Inst{7-5} = 0b011; - let Inst{4-0} = Rd; - let Inst{20-16} = Rss; - } - -let isFP = 1, hasNewValue = 1, opNewValue = 0 in -class T_MInstFloat <string mnemonic, bits<3> MajOp, bits<3> MinOp> - : MInst<(outs IntRegs:$Rd), - (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd = "#mnemonic#"($Rs, $Rt)", [], - "" , M_tc_3or4x_SLOT23 > , - Requires<[HasV5T]> { - bits<5> Rd; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1110; - - let Inst{27-24} = 0b1011; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{13} = 0b0; - let Inst{12-8} = Rt; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rd; - } - -let isCommutable = 1 in { - def F2_sfadd : T_MInstFloat < "sfadd", 0b000, 0b000>; - def F2_sfmpy : T_MInstFloat < "sfmpy", 0b010, 0b000>; -} - -def F2_sfsub : T_MInstFloat < "sfsub", 0b000, 0b001>; - -let Itinerary = M_tc_3x_SLOT23 in { - def F2_sfmax : T_MInstFloat < "sfmax", 0b100, 0b000>; - def F2_sfmin : T_MInstFloat < "sfmin", 0b100, 0b001>; -} - -let Itinerary = M_tc_3or4x_SLOT23 in { -def F2_sffixupn : T_MInstFloat < "sffixupn", 0b110, 0b000>; -def F2_sffixupd : T_MInstFloat < "sffixupd", 0b110, 0b001>; -} - -// F2_sfrecipa: Reciprocal approximation for division. -let Uses = [USR], isPredicateLate = 1, isFP = 1, - hasSideEffects = 0, hasNewValue = 1, Itinerary = M_tc_3or4x_SLOT23 in -def F2_sfrecipa: MInst < - (outs IntRegs:$Rd, PredRegs:$Pe), - (ins IntRegs:$Rs, IntRegs:$Rt), - "$Rd, $Pe = sfrecipa($Rs, $Rt)">, - Requires<[HasV5T]> { - bits<5> Rd; - bits<2> Pe; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1110; - let Inst{27-21} = 0b1011111; - let Inst{20-16} = Rs; - let Inst{13} = 0b0; - let Inst{12-8} = Rt; - let Inst{7} = 0b1; - let Inst{6-5} = Pe; - let Inst{4-0} = Rd; - } - -// F2_dfcmpeq: Floating point compare for equal. -let Uses = [USR], isCompare = 1, isFP = 1 in -class T_fcmp <string mnemonic, RegisterClass RC, bits<3> MinOp, - list<dag> pattern = [] > - : ALU64Inst <(outs PredRegs:$dst), (ins RC:$src1, RC:$src2), - "$dst = "#mnemonic#"($src1, $src2)", pattern, - "" , ALU64_tc_2early_SLOT23 > , - Requires<[HasV5T]> { - bits<2> dst; - bits<5> src1; - bits<5> src2; - - let IClass = 0b1101; - - let Inst{27-21} = 0b0010111; - let Inst{20-16} = src1; - let Inst{12-8} = src2; - let Inst{7-5} = MinOp; - let Inst{1-0} = dst; - } - -class T_fcmp64 <string mnemonic, PatFrag OpNode, bits<3> MinOp> - : T_fcmp <mnemonic, DoubleRegs, MinOp, []> { - let IClass = 0b1101; - let Inst{27-21} = 0b0010111; -} - -class T_fcmp32 <string mnemonic, PatFrag OpNode, bits<3> MinOp> - : T_fcmp <mnemonic, IntRegs, MinOp, []> { - let IClass = 0b1100; - let Inst{27-21} = 0b0111111; -} - -def F2_dfcmpeq : T_fcmp64<"dfcmp.eq", setoeq, 0b000>; -def F2_dfcmpgt : T_fcmp64<"dfcmp.gt", setogt, 0b001>; -def F2_dfcmpge : T_fcmp64<"dfcmp.ge", setoge, 0b010>; -def F2_dfcmpuo : T_fcmp64<"dfcmp.uo", setuo, 0b011>; - -def F2_sfcmpge : T_fcmp32<"sfcmp.ge", setoge, 0b000>; -def F2_sfcmpuo : T_fcmp32<"sfcmp.uo", setuo, 0b001>; -def F2_sfcmpeq : T_fcmp32<"sfcmp.eq", setoeq, 0b011>; -def F2_sfcmpgt : T_fcmp32<"sfcmp.gt", setogt, 0b100>; - -// F2 convert template classes: -let Uses = [USR], isFP = 1 in -class F2_RDD_RSS_CONVERT<string mnemonic, bits<3> MinOp, - string chop =""> - : SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss), - "$Rdd = "#mnemonic#"($Rss)"#chop, [], "", - S_2op_tc_3or4x_SLOT23> { - bits<5> Rdd; - bits<5> Rss; - - let IClass = 0b1000; - - let Inst{27-21} = 0b0000111; - let Inst{20-16} = Rss; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rdd; - } - -let Uses = [USR], isFP = 1 in -class F2_RDD_RS_CONVERT<string mnemonic, bits<3> MinOp, - string chop =""> - : SInst <(outs DoubleRegs:$Rdd), (ins IntRegs:$Rs), - "$Rdd = "#mnemonic#"($Rs)"#chop, [], "", - S_2op_tc_3or4x_SLOT23> { - bits<5> Rdd; - bits<5> Rs; - - let IClass = 0b1000; - - let Inst{27-21} = 0b0100100; - let Inst{20-16} = Rs; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rdd; - } - -let Uses = [USR], isFP = 1, hasNewValue = 1 in -class F2_RD_RSS_CONVERT<string mnemonic, bits<3> MinOp, - string chop =""> - : SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss), - "$Rd = "#mnemonic#"($Rss)"#chop, [], "", - S_2op_tc_3or4x_SLOT23> { - bits<5> Rd; - bits<5> Rss; - - let IClass = 0b1000; - - let Inst{27-24} = 0b1000; - let Inst{23-21} = MinOp; - let Inst{20-16} = Rss; - let Inst{7-5} = 0b001; - let Inst{4-0} = Rd; - } - -let Uses = [USR], isFP = 1, hasNewValue = 1 in -class F2_RD_RS_CONVERT<string mnemonic, bits<3> MajOp, bits<3> MinOp, - string chop =""> - : SInst <(outs IntRegs:$Rd), (ins IntRegs:$Rs), - "$Rd = "#mnemonic#"($Rs)"#chop, [], "", - S_2op_tc_3or4x_SLOT23> { - bits<5> Rd; - bits<5> Rs; - - let IClass = 0b1000; - - let Inst{27-24} = 0b1011; - let Inst{23-21} = MajOp; - let Inst{20-16} = Rs; - let Inst{7-5} = MinOp; - let Inst{4-0} = Rd; - } - -// Convert single precision to double precision and vice-versa. -def F2_conv_sf2df : F2_RDD_RS_CONVERT <"convert_sf2df", 0b000>; -def F2_conv_df2sf : F2_RD_RSS_CONVERT <"convert_df2sf", 0b000>; - -// Convert Integer to Floating Point. -def F2_conv_d2sf : F2_RD_RSS_CONVERT <"convert_d2sf", 0b010>; -def F2_conv_ud2sf : F2_RD_RSS_CONVERT <"convert_ud2sf", 0b001>; -def F2_conv_uw2sf : F2_RD_RS_CONVERT <"convert_uw2sf", 0b001, 0b000>; -def F2_conv_w2sf : F2_RD_RS_CONVERT <"convert_w2sf", 0b010, 0b000>; -def F2_conv_d2df : F2_RDD_RSS_CONVERT <"convert_d2df", 0b011>; -def F2_conv_ud2df : F2_RDD_RSS_CONVERT <"convert_ud2df", 0b010>; -def F2_conv_uw2df : F2_RDD_RS_CONVERT <"convert_uw2df", 0b001>; -def F2_conv_w2df : F2_RDD_RS_CONVERT <"convert_w2df", 0b010>; - -// Convert Floating Point to Integer. -def F2_conv_df2uw_chop : F2_RD_RSS_CONVERT <"convert_df2uw", 0b101, ":chop">; -def F2_conv_df2w_chop : F2_RD_RSS_CONVERT <"convert_df2w", 0b111, ":chop">; -def F2_conv_sf2uw_chop : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b001, - ":chop">; -def F2_conv_sf2w_chop : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b001, - ":chop">; -def F2_conv_df2d_chop : F2_RDD_RSS_CONVERT <"convert_df2d", 0b110, ":chop">; -def F2_conv_df2ud_chop : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b111, ":chop">; -def F2_conv_sf2d_chop : F2_RDD_RS_CONVERT <"convert_sf2d", 0b110, ":chop">; -def F2_conv_sf2ud_chop : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b101, ":chop">; - -// Convert Floating Point to Integer: non-chopped. -let AddedComplexity = 20, Predicates = [HasV5T] in { - def F2_conv_df2d : F2_RDD_RSS_CONVERT <"convert_df2d", 0b000>; - def F2_conv_df2ud : F2_RDD_RSS_CONVERT <"convert_df2ud", 0b001>; - def F2_conv_sf2ud : F2_RDD_RS_CONVERT <"convert_sf2ud", 0b011>; - def F2_conv_sf2d : F2_RDD_RS_CONVERT <"convert_sf2d", 0b100>; - def F2_conv_df2uw : F2_RD_RSS_CONVERT <"convert_df2uw", 0b011>; - def F2_conv_df2w : F2_RD_RSS_CONVERT <"convert_df2w", 0b100>; - def F2_conv_sf2uw : F2_RD_RS_CONVERT <"convert_sf2uw", 0b011, 0b000>; - def F2_conv_sf2w : F2_RD_RS_CONVERT <"convert_sf2w", 0b100, 0b000>; -} - -// Fix up radicand. -let Uses = [USR], isFP = 1, hasNewValue = 1 in -def F2_sffixupr: SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs), - "$Rd = sffixupr($Rs)", - [], "" , S_2op_tc_3or4x_SLOT23>, Requires<[HasV5T]> { - bits<5> Rd; - bits<5> Rs; - - let IClass = 0b1000; - - let Inst{27-21} = 0b1011101; - let Inst{20-16} = Rs; - let Inst{7-5} = 0b000; - let Inst{4-0} = Rd; - } - -// F2_sffma: Floating-point fused multiply add. -let Uses = [USR], isFP = 1, hasNewValue = 1 in -class T_sfmpy_acc <bit isSub, bit isLib> - : MInst<(outs IntRegs:$Rx), - (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt), - "$Rx "#!if(isSub, "-=","+=")#" sfmpy($Rs, $Rt)"#!if(isLib, ":lib",""), - [], "$dst2 = $Rx" , M_tc_3or4x_SLOT23 > , - Requires<[HasV5T]> { - bits<5> Rx; - bits<5> Rs; - bits<5> Rt; - - let IClass = 0b1110; - - let Inst{27-21} = 0b1111000; - let Inst{20-16} = Rs; - let Inst{13} = 0b0; - let Inst{12-8} = Rt; - let Inst{7} = 0b1; - let Inst{6} = isLib; - let Inst{5} = isSub; - let Inst{4-0} = Rx; - } - -def F2_sffma: T_sfmpy_acc <0, 0>; -def F2_sffms: T_sfmpy_acc <1, 0>; -def F2_sffma_lib: T_sfmpy_acc <0, 1>; -def F2_sffms_lib: T_sfmpy_acc <1, 1>; - -// Floating-point fused multiply add w/ additional scaling (2**pu). -let Uses = [USR], isFP = 1, hasNewValue = 1 in -def F2_sffma_sc: MInst < - (outs IntRegs:$Rx), - (ins IntRegs:$dst2, IntRegs:$Rs, IntRegs:$Rt, PredRegs:$Pu), - "$Rx += sfmpy($Rs, $Rt, $Pu):scale" , - [], "$dst2 = $Rx" , M_tc_3or4x_SLOT23 > , - Requires<[HasV5T]> { - bits<5> Rx; - bits<5> Rs; - bits<5> Rt; - bits<2> Pu; - - let IClass = 0b1110; - - let Inst{27-21} = 0b1111011; - let Inst{20-16} = Rs; - let Inst{13} = 0b0; - let Inst{12-8} = Rt; - let Inst{7} = 0b1; - let Inst{6-5} = Pu; - let Inst{4-0} = Rx; - } - -//===----------------------------------------------------------------------===// -// :natural forms of vasrh and vasrhub insns -//===----------------------------------------------------------------------===// -// S5_asrhub_rnd_sat: Vector arithmetic shift right by immediate with round, -// saturate, and pack. -let Defs = [USR_OVF], hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -class T_ASRHUB<bit isSat> - : SInst <(outs IntRegs:$Rd), - (ins DoubleRegs:$Rss, u4_0Imm:$u4), - "$Rd = vasrhub($Rss, #$u4):"#!if(isSat, "sat", "raw"), - [], "", S_2op_tc_2_SLOT23>, - Requires<[HasV5T]> { - bits<5> Rd; - bits<5> Rss; - bits<4> u4; - - let IClass = 0b1000; - - let Inst{27-21} = 0b1000011; - let Inst{20-16} = Rss; - let Inst{13-12} = 0b00; - let Inst{11-8} = u4; - let Inst{7-6} = 0b10; - let Inst{5} = isSat; - let Inst{4-0} = Rd; - } - -def S5_asrhub_rnd_sat : T_ASRHUB <0>; -def S5_asrhub_sat : T_ASRHUB <1>; - -let isAsmParserOnly = 1 in -def S5_asrhub_rnd_sat_goodsyntax - : SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, u4_0Imm:$u4), - "$Rd = vasrhub($Rss, #$u4):rnd:sat">, Requires<[HasV5T]>; - -// S5_vasrhrnd: Vector arithmetic shift right by immediate with round. -let hasSideEffects = 0 in -def S5_vasrhrnd : SInst <(outs DoubleRegs:$Rdd), - (ins DoubleRegs:$Rss, u4_0Imm:$u4), - "$Rdd = vasrh($Rss, #$u4):raw">, - Requires<[HasV5T]> { - bits<5> Rdd; - bits<5> Rss; - bits<4> u4; - - let IClass = 0b1000; - - let Inst{27-21} = 0b0000001; - let Inst{20-16} = Rss; - let Inst{13-12} = 0b00; - let Inst{11-8} = u4; - let Inst{7-5} = 0b000; - let Inst{4-0} = Rdd; - } - -let isAsmParserOnly = 1 in -def S5_vasrhrnd_goodsyntax - : SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, u4_0Imm:$u4), - "$Rdd = vasrh($Rss,#$u4):rnd">, Requires<[HasV5T]>; - -// Floating point reciprocal square root approximation -let Uses = [USR], isPredicateLate = 1, isFP = 1, - hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, - validSubTargets = HasV5SubT in -def F2_sfinvsqrta: SInst < - (outs IntRegs:$Rd, PredRegs:$Pe), - (ins IntRegs:$Rs), - "$Rd, $Pe = sfinvsqrta($Rs)" > , - Requires<[HasV5T]> { - bits<5> Rd; - bits<2> Pe; - bits<5> Rs; - - let IClass = 0b1000; - - let Inst{27-21} = 0b1011111; - let Inst{20-16} = Rs; - let Inst{7} = 0b0; - let Inst{6-5} = Pe; - let Inst{4-0} = Rd; - } - -// Complex multiply 32x16 -let Defs = [USR_OVF], Itinerary = S_3op_tc_3x_SLOT23 in { - def M4_cmpyi_whc : T_S3op_8<"cmpyiwh", 0b101, 1, 1, 1, 1>; - def M4_cmpyr_whc : T_S3op_8<"cmpyrwh", 0b111, 1, 1, 1, 1>; -} - -// Classify floating-point value -let Uses = [USR], isFP = 1 in -def F2_sfclass : T_TEST_BIT_IMM<"sfclass", 0b111>, Requires<[HasV5T]>; - -let Uses = [USR], isFP = 1 in -def F2_dfclass: ALU64Inst<(outs PredRegs:$Pd), (ins DoubleRegs:$Rss, u5_0Imm:$u5), - "$Pd = dfclass($Rss, #$u5)", - [], "" , ALU64_tc_2early_SLOT23 > , Requires<[HasV5T]> { - bits<2> Pd; - bits<5> Rss; - bits<5> u5; - - let IClass = 0b1101; - let Inst{27-21} = 0b1100100; - let Inst{20-16} = Rss; - let Inst{12-10} = 0b000; - let Inst{9-5} = u5; - let Inst{4-3} = 0b10; - let Inst{1-0} = Pd; - } - -// Instructions to create floating point constant -class T_fimm <string mnemonic, RegisterClass RC, bits<4> RegType, bit isNeg> - : ALU64Inst<(outs RC:$dst), (ins u10_0Imm:$src), - "$dst = "#mnemonic#"(#$src)"#!if(isNeg, ":neg", ":pos"), - [], "", ALU64_tc_2_SLOT23>, Requires<[HasV5T]> { - bits<5> dst; - bits<10> src; - - let IClass = 0b1101; - let Inst{27-24} = RegType; - let Inst{23} = 0b0; - let Inst{22} = isNeg; - let Inst{21} = src{9}; - let Inst{13-5} = src{8-0}; - let Inst{4-0} = dst; - } - -let hasNewValue = 1, opNewValue = 0 in { - def F2_sfimm_p : T_fimm <"sfmake", IntRegs, 0b0110, 0>; - def F2_sfimm_n : T_fimm <"sfmake", IntRegs, 0b0110, 1>; -} - -def F2_dfimm_p : T_fimm <"dfmake", DoubleRegs, 0b1001, 0>; -def F2_dfimm_n : T_fimm <"dfmake", DoubleRegs, 0b1001, 1>; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfoV60.td b/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfoV60.td deleted file mode 100644 index c50141b18ead..000000000000 --- a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfoV60.td +++ /dev/null @@ -1,2068 +0,0 @@ -//=- HexagonInstrInfoV60.td - Target Desc. for Hexagon Target -*- tablegen -*-=// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon V60 instructions in TableGen format. -// -//===----------------------------------------------------------------------===// -// Vector load -let Predicates = [HasV60T, UseHVX] in -let mayLoad = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in - class V6_LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = CVI_VM_LD, - IType type = TypeCVI_VM_LD> - : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>; - -// Vector store -let Predicates = [HasV60T, UseHVX] in -let mayStore = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in -class V6_STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = CVI_VM_ST, - IType type = TypeCVI_VM_ST> -: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>; - -//===----------------------------------------------------------------------===// -// Vector loads with base + immediate offset -//===----------------------------------------------------------------------===// -let addrMode = BaseImmOffset, accessSize = Vector64Access in -class T_vload_ai<string asmStr> - : V6_LDInst <(outs VectorRegs:$dst), (ins IntRegs:$src1, s4_6Imm:$src2), - asmStr>; - -let isCodeGenOnly = 1, addrMode = BaseImmOffset, accessSize = Vector128Access in -class T_vload_ai_128B<string asmStr> - : V6_LDInst <(outs VectorRegs128B:$dst), (ins IntRegs:$src1, s4_7Imm:$src2), - asmStr>; - -let isCVLoadable = 1, hasNewValue = 1 in { - def V6_vL32b_ai : T_vload_ai <"$dst = vmem($src1+#$src2)">, - V6_vL32b_ai_enc; - def V6_vL32b_nt_ai : T_vload_ai <"$dst = vmem($src1+#$src2):nt">, - V6_vL32b_nt_ai_enc; - // 128B - def V6_vL32b_ai_128B : T_vload_ai_128B <"$dst = vmem($src1+#$src2)">, - V6_vL32b_ai_128B_enc; - def V6_vL32b_nt_ai_128B : T_vload_ai_128B <"$dst = vmem($src1+#$src2):nt">, - V6_vL32b_nt_ai_128B_enc; -} - -let Itinerary = CVI_VM_VP_LDU, Type = TypeCVI_VM_VP_LDU, hasNewValue = 1 in { - def V6_vL32Ub_ai : T_vload_ai <"$dst = vmemu($src1+#$src2)">, - V6_vL32Ub_ai_enc; - def V6_vL32Ub_ai_128B : T_vload_ai_128B <"$dst = vmemu($src1+#$src2)">, - V6_vL32Ub_ai_128B_enc; -} - -let Itinerary = CVI_VM_LD, Type = TypeCVI_VM_LD, isCVLoad = 1, - hasNewValue = 1 in { - def V6_vL32b_cur_ai : T_vload_ai <"$dst.cur = vmem($src1+#$src2)">, - V6_vL32b_cur_ai_enc; - def V6_vL32b_nt_cur_ai : T_vload_ai <"$dst.cur = vmem($src1+#$src2):nt">, - V6_vL32b_nt_cur_ai_enc; - // 128B - def V6_vL32b_cur_ai_128B : T_vload_ai_128B - <"$dst.cur = vmem($src1+#$src2)">, - V6_vL32b_cur_ai_128B_enc; - def V6_vL32b_nt_cur_ai_128B : T_vload_ai_128B - <"$dst.cur = vmem($src1+#$src2):nt">, - V6_vL32b_nt_cur_ai_128B_enc; -} - - -let Itinerary = CVI_VM_TMP_LD, Type = TypeCVI_VM_TMP_LD, hasNewValue = 1 in { - def V6_vL32b_tmp_ai : T_vload_ai <"$dst.tmp = vmem($src1+#$src2)">, - V6_vL32b_tmp_ai_enc; - def V6_vL32b_nt_tmp_ai : T_vload_ai <"$dst.tmp = vmem($src1+#$src2):nt">, - V6_vL32b_nt_tmp_ai_enc; - // 128B - def V6_vL32b_tmp_ai_128B : T_vload_ai_128B - <"$dst.tmp = vmem($src1+#$src2)">, - V6_vL32b_tmp_ai_128B_enc; - def V6_vL32b_nt_tmp_ai_128B : T_vload_ai_128B - <"$dst.tmp = vmem($src1+#$src2)">, - V6_vL32b_nt_tmp_ai_128B_enc; -} - -//===----------------------------------------------------------------------===// -// Vector stores with base + immediate offset - unconditional -//===----------------------------------------------------------------------===// -let addrMode = BaseImmOffset, accessSize = Vector64Access, isPredicable = 1 in -class T_vstore_ai <string mnemonic, string baseOp, Operand ImmOp, - RegisterClass RC, bit isNT> - : V6_STInst <(outs), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3), - mnemonic#"($src1+#$src2)"#!if(isNT, ":nt", "")#" = $src3">, NewValueRel { - let BaseOpcode = baseOp; -} - -let accessSize = Vector64Access in -class T_vstore_ai_64B <string mnemonic, string baseOp, bit isNT = 0> - : T_vstore_ai <mnemonic, baseOp, s4_6Imm, VectorRegs, isNT>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vstore_ai_128B <string mnemonic, string baseOp, bit isNT = 0> - : T_vstore_ai <mnemonic, baseOp#"128B", s4_7Imm, VectorRegs128B, isNT>; - -let isNVStorable = 1 in { - def V6_vS32b_ai : T_vstore_ai_64B <"vmem", "vS32b_ai">, - V6_vS32b_ai_enc; - def V6_vS32b_ai_128B : T_vstore_ai_128B <"vmem", "vS32b_ai">, - V6_vS32b_ai_128B_enc; -} - -let isNVStorable = 1, isNonTemporal = 1 in { - def V6_vS32b_nt_ai : T_vstore_ai_64B <"vmem", "vS32b_ai", 1>, - V6_vS32b_nt_ai_enc; - def V6_vS32b_nt_ai_128B : T_vstore_ai_128B <"vmem", "vS32b_ai", 1>, - V6_vS32b_nt_ai_128B_enc; -} - -let Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in { - def V6_vS32Ub_ai : T_vstore_ai_64B <"vmemu", "vS32Ub_ai">, - V6_vS32Ub_ai_enc; - def V6_vS32Ub_ai_128B : T_vstore_ai_128B <"vmemu", "vS32Ub_ai">, - V6_vS32Ub_ai_128B_enc; -} -//===----------------------------------------------------------------------===// -// Vector stores with base + immediate offset - unconditional new -//===----------------------------------------------------------------------===// -let addrMode = BaseImmOffset, isNewValue = 1, opNewValue = 2, isNVStore = 1, - isPredicable = 1, Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST in -class T_vstore_new_ai <string baseOp, Operand ImmOp, RegisterClass RC, bit isNT> - : V6_STInst <(outs ), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3), - "vmem($src1+#$src2)"#!if(isNT, ":nt", "")#" = $src3.new">, NewValueRel { - let BaseOpcode = baseOp; -} - -let accessSize = Vector64Access in -class T_vstore_new_ai_64B <string baseOp, bit isNT = 0> - : T_vstore_new_ai <baseOp, s4_6Imm, VectorRegs, isNT>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vstore_new_ai_128B <string baseOp, bit isNT = 0> - : T_vstore_new_ai <baseOp#"128B", s4_7Imm, VectorRegs128B, isNT>; - -def V6_vS32b_new_ai : T_vstore_new_ai_64B <"vS32b_ai">, V6_vS32b_new_ai_enc; -def V6_vS32b_new_ai_128B : T_vstore_new_ai_128B <"vS32b_ai">, - V6_vS32b_new_ai_128B_enc; - -let isNonTemporal = 1 in { - def V6_vS32b_nt_new_ai : T_vstore_new_ai_64B<"vS32b_ai", 1>, - V6_vS32b_nt_new_ai_enc; - def V6_vS32b_nt_new_ai_128B : T_vstore_new_ai_128B<"vS32b_ai", 1>, - V6_vS32b_nt_new_ai_128B_enc; -} - -//===----------------------------------------------------------------------===// -// Vector stores with base + immediate offset - conditional -//===----------------------------------------------------------------------===// -let addrMode = BaseImmOffset, isPredicated = 1 in -class T_vstore_pred_ai <string mnemonic, string baseOp, Operand ImmOp, - RegisterClass RC, bit isPredNot = 0, bit isNT = 0> - : V6_STInst <(outs), - (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4), - "if ("#!if(isPredNot, "!", "")#"$src1) " - #mnemonic#"($src2+#$src3)"#!if(isNT, ":nt", "")#" = $src4">, NewValueRel { - let isPredicatedFalse = isPredNot; - let BaseOpcode = baseOp; -} - -let accessSize = Vector64Access in -class T_vstore_pred_ai_64B <string mnemonic, string baseOp, - bit isPredNot = 0, bit isNT = 0> - : T_vstore_pred_ai <mnemonic, baseOp, s4_6Imm, VectorRegs, isPredNot, isNT>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vstore_pred_ai_128B <string mnemonic, string baseOp, - bit isPredNot = 0, bit isNT = 0> - : T_vstore_pred_ai <mnemonic, baseOp#"128B", s4_7Imm, VectorRegs128B, - isPredNot, isNT>; - -let isNVStorable = 1 in { - def V6_vS32b_pred_ai : T_vstore_pred_ai_64B <"vmem", "vS32b_ai">, - V6_vS32b_pred_ai_enc; - def V6_vS32b_npred_ai : T_vstore_pred_ai_64B <"vmem", "vS32b_ai", 1>, - V6_vS32b_npred_ai_enc; - // 128B - def V6_vS32b_pred_ai_128B : T_vstore_pred_ai_128B <"vmem", "vS32b_ai">, - V6_vS32b_pred_ai_128B_enc; - def V6_vS32b_npred_ai_128B : T_vstore_pred_ai_128B <"vmem", "vS32b_ai", 1>, - V6_vS32b_npred_ai_128B_enc; -} - - -let isNVStorable = 1, isNonTemporal = 1 in { - def V6_vS32b_nt_pred_ai : T_vstore_pred_ai_64B <"vmem", "vS32b_ai", 0, 1>, - V6_vS32b_nt_pred_ai_enc; - def V6_vS32b_nt_npred_ai : T_vstore_pred_ai_64B <"vmem", "vS32b_ai", 1, 1>, - V6_vS32b_nt_npred_ai_enc; - // 128B - def V6_vS32b_nt_pred_ai_128B : T_vstore_pred_ai_128B - <"vmem", "vS32b_ai", 0, 1>, - V6_vS32b_nt_pred_ai_128B_enc; - def V6_vS32b_nt_npred_ai_128B : T_vstore_pred_ai_128B - <"vmem", "vS32b_ai", 1, 1>, - V6_vS32b_nt_npred_ai_128B_enc; -} - -let Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in { - def V6_vS32Ub_pred_ai : T_vstore_pred_ai_64B <"vmemu", "vS32Ub_ai">, - V6_vS32Ub_pred_ai_enc; - def V6_vS32Ub_npred_ai : T_vstore_pred_ai_64B <"vmemu", "vS32Ub_ai", 1>, - V6_vS32Ub_npred_ai_enc; - // 128B - def V6_vS32Ub_pred_ai_128B :T_vstore_pred_ai_128B <"vmemu", "vS32Ub_ai">, - V6_vS32Ub_pred_ai_128B_enc; - def V6_vS32Ub_npred_ai_128B :T_vstore_pred_ai_128B <"vmemu", "vS32Ub_ai", 1>, - V6_vS32Ub_npred_ai_128B_enc; -} - -//===----------------------------------------------------------------------===// -// Vector stores with base + immediate offset - byte-enabled aligned -//===----------------------------------------------------------------------===// -let addrMode = BaseImmOffset in -class T_vstore_qpred_ai <Operand ImmOp, RegisterClass RC, - bit isPredNot = 0, bit isNT = 0> - : V6_STInst <(outs), - (ins VecPredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4), - "if ("#!if(isPredNot, "!", "")#"$src1) vmem($src2+#$src3)" - #!if(isNT, ":nt", "")#" = $src4"> { - let isPredicatedFalse = isPredNot; -} - -let accessSize = Vector64Access in -class T_vstore_qpred_ai_64B <bit isPredNot = 0, bit isNT = 0> - : T_vstore_qpred_ai <s4_6Imm, VectorRegs, isPredNot, isNT>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vstore_qpred_ai_128B <bit isPredNot = 0, bit isNT = 0> - : T_vstore_qpred_ai <s4_7Imm, VectorRegs128B, isPredNot, isNT>; - -def V6_vS32b_qpred_ai : T_vstore_qpred_ai_64B, V6_vS32b_qpred_ai_enc; -def V6_vS32b_nqpred_ai : T_vstore_qpred_ai_64B <1>, - V6_vS32b_nqpred_ai_enc; -def V6_vS32b_nt_qpred_ai : T_vstore_qpred_ai_64B <0, 1>, - V6_vS32b_nt_qpred_ai_enc; -def V6_vS32b_nt_nqpred_ai : T_vstore_qpred_ai_64B <1, 1>, - V6_vS32b_nt_nqpred_ai_enc; -// 128B -def V6_vS32b_qpred_ai_128B : T_vstore_qpred_ai_128B, V6_vS32b_qpred_ai_128B_enc; -def V6_vS32b_nqpred_ai_128B : T_vstore_qpred_ai_128B<1>, - V6_vS32b_nqpred_ai_128B_enc; -def V6_vS32b_nt_qpred_ai_128B : T_vstore_qpred_ai_128B<0, 1>, - V6_vS32b_nt_qpred_ai_128B_enc; -def V6_vS32b_nt_nqpred_ai_128B : T_vstore_qpred_ai_128B<1, 1>, - V6_vS32b_nt_nqpred_ai_128B_enc; - - -//===----------------------------------------------------------------------===// -// Vector stores with base + immediate offset - conditional new -//===----------------------------------------------------------------------===// -let addrMode = BaseImmOffset, isPredicated = 1, isNewValue = 1, opNewValue = 3, - isNVStore = 1, Type = TypeCVI_VM_NEW_ST, Itinerary = CVI_VM_NEW_ST in -class T_vstore_new_pred_ai <string baseOp, Operand ImmOp, RegisterClass RC, - bit isPredNot, bit isNT> - : V6_STInst <(outs), - (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4), - "if("#!if(isPredNot, "!", "")#"$src1) vmem($src2+#$src3)" - #!if(isNT, ":nt", "")#" = $src4.new">, NewValueRel { - let isPredicatedFalse = isPredNot; - let BaseOpcode = baseOp; -} - -let accessSize = Vector64Access in -class T_vstore_new_pred_ai_64B <string baseOp, bit isPredNot = 0, bit isNT = 0> - : T_vstore_new_pred_ai <baseOp, s4_6Imm, VectorRegs, isPredNot, isNT>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vstore_new_pred_ai_128B <string baseOp, bit isPredNot = 0, bit isNT = 0> - : T_vstore_new_pred_ai <baseOp#"128B", s4_7Imm, VectorRegs128B, - isPredNot, isNT>; - - -def V6_vS32b_new_pred_ai : T_vstore_new_pred_ai_64B <"vS32b_ai">, - V6_vS32b_new_pred_ai_enc; -def V6_vS32b_new_npred_ai : T_vstore_new_pred_ai_64B <"vS32b_ai", 1>, - V6_vS32b_new_npred_ai_enc; -// 128B -def V6_vS32b_new_pred_ai_128B : T_vstore_new_pred_ai_128B <"vS32b_ai">, - V6_vS32b_new_pred_ai_128B_enc; -def V6_vS32b_new_npred_ai_128B : T_vstore_new_pred_ai_128B <"vS32b_ai", 1>, - V6_vS32b_new_npred_ai_128B_enc; -let isNonTemporal = 1 in { - def V6_vS32b_nt_new_pred_ai : T_vstore_new_pred_ai_64B <"vS32b_ai", 0, 1>, - V6_vS32b_nt_new_pred_ai_enc; - def V6_vS32b_nt_new_npred_ai : T_vstore_new_pred_ai_64B <"vS32b_ai", 1, 1>, - V6_vS32b_nt_new_npred_ai_enc; - // 128B - def V6_vS32b_nt_new_pred_ai_128B : T_vstore_new_pred_ai_128B - <"vS32b_ai", 0, 1>, - V6_vS32b_nt_new_pred_ai_128B_enc; - def V6_vS32b_nt_new_npred_ai_128B : T_vstore_new_pred_ai_128B - <"vS32b_ai", 1, 1>, - V6_vS32b_nt_new_npred_ai_128B_enc; -} - -//===----------------------------------------------------------------------===// -// Post increment vector loads with immediate offset. -//===----------------------------------------------------------------------===// -let addrMode = PostInc, hasNewValue = 1 in -class T_vload_pi<string asmStr, Operand ImmOp, RegisterClass RC> - : V6_LDInst <(outs RC:$dst, IntRegs:$_dst_), - (ins IntRegs:$src1, ImmOp:$src2), asmStr, [], - "$src1 = $_dst_">; - -let accessSize = Vector64Access in -class T_vload_pi_64B <string asmStr> - : T_vload_pi <asmStr, s3_6Imm, VectorRegs>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vload_pi_128B <string asmStr> - : T_vload_pi <asmStr, s3_7Imm, VectorRegs128B>; - -let isCVLoadable = 1 in { - def V6_vL32b_pi : T_vload_pi_64B <"$dst = vmem($src1++#$src2)">, - V6_vL32b_pi_enc; - def V6_vL32b_nt_pi : T_vload_pi_64B <"$dst = vmem($src1++#$src2):nt">, - V6_vL32b_nt_pi_enc; - // 128B - def V6_vL32b_pi_128B : T_vload_pi_128B <"$dst = vmem($src1++#$src2)">, - V6_vL32b_pi_128B_enc; - def V6_vL32b_nt_pi_128B : T_vload_pi_128B <"$dst = vmem($src1++#$src2):nt">, - V6_vL32b_nt_pi_128B_enc; -} - -let Itinerary = CVI_VM_VP_LDU, Type = TypeCVI_VM_VP_LDU in { - def V6_vL32Ub_pi : T_vload_pi_64B <"$dst = vmemu($src1++#$src2)">, - V6_vL32Ub_pi_enc; - // 128B - def V6_vL32Ub_pi_128B : T_vload_pi_128B <"$dst = vmemu($src1++#$src2)">, - V6_vL32Ub_pi_128B_enc; -} - -let isCVLoad = 1, Itinerary = CVI_VM_LD, Type = TypeCVI_VM_LD in { - def V6_vL32b_cur_pi : T_vload_pi_64B <"$dst.cur = vmem($src1++#$src2)">, - V6_vL32b_cur_pi_enc; - def V6_vL32b_nt_cur_pi : T_vload_pi_64B <"$dst.cur = vmem($src1++#$src2):nt">, - V6_vL32b_nt_cur_pi_enc; - // 128B - def V6_vL32b_cur_pi_128B : T_vload_pi_128B - <"$dst.cur = vmem($src1++#$src2)">, - V6_vL32b_cur_pi_128B_enc; - def V6_vL32b_nt_cur_pi_128B : T_vload_pi_128B - <"$dst.cur = vmem($src1++#$src2):nt">, - V6_vL32b_nt_cur_pi_128B_enc; -} - -let Itinerary = CVI_VM_TMP_LD, Type = TypeCVI_VM_TMP_LD in { - def V6_vL32b_tmp_pi : T_vload_pi_64B <"$dst.tmp = vmem($src1++#$src2)">, - V6_vL32b_tmp_pi_enc; - def V6_vL32b_nt_tmp_pi : T_vload_pi_64B <"$dst.tmp = vmem($src1++#$src2):nt">, - V6_vL32b_nt_tmp_pi_enc; - //128B - def V6_vL32b_tmp_pi_128B : T_vload_pi_128B - <"$dst.tmp = vmem($src1++#$src2)">, - V6_vL32b_tmp_pi_128B_enc; - def V6_vL32b_nt_tmp_pi_128B : T_vload_pi_128B - <"$dst.tmp = vmem($src1++#$src2):nt">, - V6_vL32b_nt_tmp_pi_128B_enc; -} - -//===----------------------------------------------------------------------===// -// Post increment vector stores with immediate offset. -//===----------------------------------------------------------------------===// -let addrMode = PostInc, isPredicable = 1 in -class T_vstore_pi <string mnemonic, string baseOp, Operand ImmOp, - RegisterClass RC, bit isNT> - : V6_STInst <(outs IntRegs:$_dst_), - (ins IntRegs:$src1, ImmOp:$src2, RC:$src3), - mnemonic#"($src1++#$src2)"#!if(isNT, ":nt", "")#" = $src3", [], - "$src1 = $_dst_">, NewValueRel { - let BaseOpcode = baseOp; -} - -let accessSize = Vector64Access in -class T_vstore_pi_64B <string mnemonic, string baseOp, bit isNT = 0> - : T_vstore_pi <mnemonic, baseOp, s3_6Imm, VectorRegs, isNT>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vstore_pi_128B <string mnemonic, string baseOp, bit isNT = 0> - : T_vstore_pi <mnemonic, baseOp#"128B", s3_7Imm, VectorRegs128B, isNT>; - -let isNVStorable = 1 in { - def V6_vS32b_pi : T_vstore_pi_64B <"vmem", "vS32b_pi">, V6_vS32b_pi_enc; - def V6_vS32b_pi_128B : T_vstore_pi_128B <"vmem", "vS32b_pi">, - V6_vS32b_pi_128B_enc; -} - -let isNVStorable = 1 , isNonTemporal = 1 in { - def V6_vS32b_nt_pi : T_vstore_pi_64B <"vmem", "vS32b_pi", 1>, - V6_vS32b_nt_pi_enc; - def V6_vS32b_nt_pi_128B : T_vstore_pi_128B <"vmem", "vS32b_pi", 1>, - V6_vS32b_nt_pi_128B_enc; -} - - -let Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in { - def V6_vS32Ub_pi : T_vstore_pi_64B <"vmemu", "vS32Ub_pi">, - V6_vS32Ub_pi_enc; - def V6_vS32Ub_pi_128B : T_vstore_pi_128B <"vmemu", "vS32Ub_pi">, - V6_vS32Ub_pi_128B_enc; -} - -//===----------------------------------------------------------------------===// -// Post increment unconditional .new vector stores with immediate offset. -//===----------------------------------------------------------------------===// -let addrMode = PostInc, isNVStore = 1 in -let Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST, isNewValue = 1, - isPredicable = 1, opNewValue = 3, isNVStore = 1 in -class T_vstore_new_pi <string baseOp, Operand ImmOp, RegisterClass RC, bit isNT> - : V6_STInst <(outs IntRegs:$_dst_), - (ins IntRegs:$src1, ImmOp:$src2, RC:$src3), - "vmem($src1++#$src2)"#!if(isNT, ":nt", "")#" = $src3.new", [], - "$src1 = $_dst_">, NewValueRel { - let BaseOpcode = baseOp; -} - -let accessSize = Vector64Access in -class T_vstore_new_pi_64B <string baseOp, bit isNT = 0> - : T_vstore_new_pi <baseOp, s3_6Imm, VectorRegs, isNT>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vstore_new_pi_128B <string baseOp, bit isNT = 0> - : T_vstore_new_pi <baseOp#"128B", s3_7Imm, VectorRegs128B, isNT>; - - -def V6_vS32b_new_pi : T_vstore_new_pi_64B <"vS32b_pi">, - V6_vS32b_new_pi_enc; -def V6_vS32b_new_pi_128B : T_vstore_new_pi_128B <"vS32b_pi">, - V6_vS32b_new_pi_128B_enc; - -let isNonTemporal = 1 in { - def V6_vS32b_nt_new_pi : T_vstore_new_pi_64B <"vS32b_pi", 1>, - V6_vS32b_nt_new_pi_enc; - def V6_vS32b_nt_new_pi_128B : T_vstore_new_pi_128B <"vS32b_pi", 1>, - V6_vS32b_nt_new_pi_128B_enc; -} - -//===----------------------------------------------------------------------===// -// Post increment conditional vector stores with immediate offset -//===----------------------------------------------------------------------===// -let isPredicated = 1, addrMode = PostInc in -class T_vstore_pred_pi <string mnemonic, string baseOp, Operand ImmOp, - RegisterClass RC, bit isPredNot, bit isNT> - : V6_STInst<(outs IntRegs:$_dst_), - (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4), - "if ("#!if(isPredNot, "!", "")#"$src1) "#mnemonic#"($src2++#$src3)" - #!if(isNT, ":nt", "")#" = $src4", [], - "$src2 = $_dst_">, NewValueRel { - let isPredicatedFalse = isPredNot; - let BaseOpcode = baseOp; -} - -let accessSize = Vector64Access in -class T_vstore_pred_pi_64B <string mnemonic, string baseOp, - bit isPredNot = 0, bit isNT = 0> - : T_vstore_pred_pi <mnemonic, baseOp, s3_6Imm, VectorRegs, isPredNot, isNT>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vstore_pred_pi_128B <string mnemonic, string baseOp, - bit isPredNot = 0, bit isNT = 0> - : T_vstore_pred_pi <mnemonic, baseOp#"128B", s3_7Imm, VectorRegs128B, - isPredNot, isNT>; - -let isNVStorable = 1 in { - def V6_vS32b_pred_pi : T_vstore_pred_pi_64B <"vmem", "vS32b_pi">, - V6_vS32b_pred_pi_enc; - def V6_vS32b_npred_pi : T_vstore_pred_pi_64B <"vmem", "vS32b_pi", 1>, - V6_vS32b_npred_pi_enc; - // 128B - def V6_vS32b_pred_pi_128B : T_vstore_pred_pi_128B <"vmem", "vS32b_pi">, - V6_vS32b_pred_pi_128B_enc; - def V6_vS32b_npred_pi_128B : T_vstore_pred_pi_128B <"vmem", "vS32b_pi", 1>, - V6_vS32b_npred_pi_128B_enc; -} -let isNVStorable = 1, isNonTemporal = 1 in { - def V6_vS32b_nt_pred_pi : T_vstore_pred_pi_64B <"vmem", "vS32b_pi", 0, 1>, - V6_vS32b_nt_pred_pi_enc; - def V6_vS32b_nt_npred_pi : T_vstore_pred_pi_64B <"vmem", "vS32b_pi", 1, 1>, - V6_vS32b_nt_npred_pi_enc; - // 128B - def V6_vS32b_nt_pred_pi_128B : T_vstore_pred_pi_128B - <"vmem", "vS32b_pi", 0, 1>, - V6_vS32b_nt_pred_pi_128B_enc; - def V6_vS32b_nt_npred_pi_128B : T_vstore_pred_pi_128B - <"vmem", "vS32b_pi", 1, 1>, - V6_vS32b_nt_npred_pi_128B_enc; -} - -let Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in { - def V6_vS32Ub_pred_pi : T_vstore_pred_pi_64B <"vmemu", "vS32Ub_pi">, - V6_vS32Ub_pred_pi_enc; - def V6_vS32Ub_npred_pi : T_vstore_pred_pi_64B <"vmemu", "vS32Ub_pi", 1>, - V6_vS32Ub_npred_pi_enc; - // 128B - def V6_vS32Ub_pred_pi_128B : T_vstore_pred_pi_128B <"vmemu", "vS32Ub_pi">, - V6_vS32Ub_pred_pi_128B_enc; - def V6_vS32Ub_npred_pi_128B : T_vstore_pred_pi_128B <"vmemu", "vS32Ub_pi", 1>, - V6_vS32Ub_npred_pi_128B_enc; -} - -//===----------------------------------------------------------------------===// -// Post increment vector stores with immediate offset - byte-enabled aligned -//===----------------------------------------------------------------------===// -let addrMode = PostInc in -class T_vstore_qpred_pi <Operand ImmOp, RegisterClass RC, bit isPredNot = 0, - bit isNT = 0> - : V6_STInst <(outs IntRegs:$_dst_), - (ins VecPredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4), - "if ("#!if(isPredNot, "!", "")#"$src1) vmem($src2++#$src3)" - #!if(isNT, ":nt", "")#" = $src4", [], - "$src2 = $_dst_">; - -let accessSize = Vector64Access in -class T_vstore_qpred_pi_64B <bit isPredNot = 0, bit isNT = 0> - : T_vstore_qpred_pi <s3_6Imm, VectorRegs, isPredNot, isNT>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vstore_qpred_pi_128B <bit isPredNot = 0, bit isNT = 0> - : T_vstore_qpred_pi <s3_7Imm, VectorRegs128B, isPredNot, isNT>; - -def V6_vS32b_qpred_pi : T_vstore_qpred_pi_64B, V6_vS32b_qpred_pi_enc; -def V6_vS32b_nqpred_pi : T_vstore_qpred_pi_64B <1>, V6_vS32b_nqpred_pi_enc; -// 128B -def V6_vS32b_qpred_pi_128B : T_vstore_qpred_pi_128B, - V6_vS32b_qpred_pi_128B_enc; -def V6_vS32b_nqpred_pi_128B : T_vstore_qpred_pi_128B<1>, - V6_vS32b_nqpred_pi_128B_enc; - -let isNonTemporal = 1 in { - def V6_vS32b_nt_qpred_pi : T_vstore_qpred_pi_64B <0, 1>, - V6_vS32b_nt_qpred_pi_enc; - def V6_vS32b_nt_nqpred_pi : T_vstore_qpred_pi_64B <1, 1>, - V6_vS32b_nt_nqpred_pi_enc; - // 128B - def V6_vS32b_nt_qpred_pi_128B : T_vstore_qpred_pi_128B<0, 1>, - V6_vS32b_nt_qpred_pi_128B_enc; - def V6_vS32b_nt_nqpred_pi_128B : T_vstore_qpred_pi_128B<1, 1>, - V6_vS32b_nt_nqpred_pi_128B_enc; -} - -//===----------------------------------------------------------------------===// -// Post increment conditional .new vector stores with immediate offset -//===----------------------------------------------------------------------===// -let Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST, isPredicated = 1, - isNewValue = 1, opNewValue = 4, addrMode = PostInc, isNVStore = 1 in -class T_vstore_new_pred_pi <string baseOp, Operand ImmOp, RegisterClass RC, - bit isPredNot, bit isNT> - : V6_STInst <(outs IntRegs:$_dst_), - (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$src3, RC:$src4), - "if("#!if(isPredNot, "!", "")#"$src1) vmem($src2++#$src3)" - #!if(isNT, ":nt", "")#" = $src4.new", [], - "$src2 = $_dst_"> , NewValueRel { - let isPredicatedFalse = isPredNot; - let BaseOpcode = baseOp; -} - -let accessSize = Vector64Access in -class T_vstore_new_pred_pi_64B <string baseOp, bit isPredNot = 0, bit isNT = 0> - : T_vstore_new_pred_pi <baseOp, s3_6Imm, VectorRegs, isPredNot, isNT>; - -let isCodeGenOnly = 1, accessSize = Vector128Access in -class T_vstore_new_pred_pi_128B <string baseOp, bit isPredNot = 0, bit isNT = 0> - : T_vstore_new_pred_pi <baseOp#"128B", s3_7Imm, VectorRegs128B, - isPredNot, isNT>; - -def V6_vS32b_new_pred_pi : T_vstore_new_pred_pi_64B <"vS32b_pi">, - V6_vS32b_new_pred_pi_enc; -def V6_vS32b_new_npred_pi : T_vstore_new_pred_pi_64B <"vS32b_pi", 1>, - V6_vS32b_new_npred_pi_enc; -// 128B -def V6_vS32b_new_pred_pi_128B : T_vstore_new_pred_pi_128B <"vS32b_pi">, - V6_vS32b_new_pred_pi_128B_enc; -def V6_vS32b_new_npred_pi_128B : T_vstore_new_pred_pi_128B <"vS32b_pi", 1>, - V6_vS32b_new_npred_pi_128B_enc; -let isNonTemporal = 1 in { - def V6_vS32b_nt_new_pred_pi : T_vstore_new_pred_pi_64B <"vS32b_pi", 0, 1>, - V6_vS32b_nt_new_pred_pi_enc; - def V6_vS32b_nt_new_npred_pi : T_vstore_new_pred_pi_64B <"vS32b_pi", 1, 1>, - V6_vS32b_nt_new_npred_pi_enc; - // 128B - def V6_vS32b_nt_new_pred_pi_128B : T_vstore_new_pred_pi_128B - <"vS32b_pi", 0, 1>, - V6_vS32b_nt_new_pred_pi_128B_enc; - def V6_vS32b_nt_new_npred_pi_128B : T_vstore_new_pred_pi_128B - <"vS32b_pi", 1, 1>, - V6_vS32b_nt_new_npred_pi_128B_enc; -} - -//===----------------------------------------------------------------------===// -// Post increment vector loads with register offset -//===----------------------------------------------------------------------===// -let hasNewValue = 1 in -class T_vload_ppu<string asmStr> - : V6_LDInst <(outs VectorRegs:$dst, IntRegs:$_dst_), - (ins IntRegs:$src1, ModRegs:$src2), asmStr, [], - "$src1 = $_dst_">, NewValueRel; - -let isCVLoadable = 1 in { - def V6_vL32b_ppu : T_vload_ppu <"$dst = vmem($src1++$src2)">, - V6_vL32b_ppu_enc; - def V6_vL32b_nt_ppu : T_vload_ppu <"$dst = vmem($src1++$src2):nt">, - V6_vL32b_nt_ppu_enc; -} - -let Itinerary = CVI_VM_VP_LDU, Type = TypeCVI_VM_VP_LDU in -def V6_vL32Ub_ppu : T_vload_ppu <"$dst = vmemu($src1++$src2)">, - V6_vL32Ub_ppu_enc; - -let isCVLoad = 1, Itinerary = CVI_VM_CUR_LD, Type = TypeCVI_VM_CUR_LD in { - def V6_vL32b_cur_ppu : T_vload_ppu <"$dst.cur = vmem($src1++$src2)">, - V6_vL32b_cur_ppu_enc; - def V6_vL32b_nt_cur_ppu : T_vload_ppu <"$dst.cur = vmem($src1++$src2):nt">, - V6_vL32b_nt_cur_ppu_enc; -} - -let Itinerary = CVI_VM_TMP_LD, Type = TypeCVI_VM_TMP_LD in { - def V6_vL32b_tmp_ppu : T_vload_ppu <"$dst.tmp = vmem($src1++$src2)">, - V6_vL32b_tmp_ppu_enc; - def V6_vL32b_nt_tmp_ppu : T_vload_ppu <"$dst.tmp = vmem($src1++$src2):nt">, - V6_vL32b_nt_tmp_ppu_enc; -} - -//===----------------------------------------------------------------------===// -// Post increment vector stores with register offset -//===----------------------------------------------------------------------===// -let isPredicable = 1 in -class T_vstore_ppu <string mnemonic, bit isNT = 0> - : V6_STInst <(outs IntRegs:$_dst_), - (ins IntRegs:$src1, ModRegs:$src2, VectorRegs:$src3), - mnemonic#"($src1++$src2)"#!if(isNT, ":nt", "")#" = $src3", [], - "$src1 = $_dst_">, NewValueRel; - -let isNVStorable = 1, BaseOpcode = "vS32b_ppu" in { - def V6_vS32b_ppu : T_vstore_ppu <"vmem">, - V6_vS32b_ppu_enc; - let isNonTemporal = 1, BaseOpcode = "vS32b_ppu" in - def V6_vS32b_nt_ppu : T_vstore_ppu <"vmem", 1>, - V6_vS32b_nt_ppu_enc; -} - -let BaseOpcode = "vS32Ub_ppu", Itinerary = CVI_VM_STU, Type = TypeCVI_VM_STU in -def V6_vS32Ub_ppu : T_vstore_ppu <"vmemu">, V6_vS32Ub_ppu_enc; - -//===----------------------------------------------------------------------===// -// Post increment .new vector stores with register offset -//===----------------------------------------------------------------------===// -let Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST, isNewValue = 1, - isPredicable = 1, opNewValue = 3, isNVStore = 1 in -class T_vstore_new_ppu <bit isNT = 0> - : V6_STInst <(outs IntRegs:$_dst_), - (ins IntRegs:$src1, ModRegs:$src2, VectorRegs:$src3), - "vmem($src1++$src2)"#!if(isNT, ":nt", "")#" = $src3.new", [], - "$src1 = $_dst_">, NewValueRel; - -let BaseOpcode = "vS32b_ppu" in -def V6_vS32b_new_ppu : T_vstore_new_ppu, V6_vS32b_new_ppu_enc; - -let BaseOpcode = "vS32b_ppu", isNonTemporal = 1 in -def V6_vS32b_nt_new_ppu : T_vstore_new_ppu<1>, V6_vS32b_nt_new_ppu_enc; - -//===----------------------------------------------------------------------===// -// Post increment conditional .new vector stores with register offset -//===----------------------------------------------------------------------===// -let isPredicated = 1 in -class T_vstore_pred_ppu <string mnemonic, bit isPredNot = 0, bit isNT = 0> - : V6_STInst<(outs IntRegs:$_dst_), - (ins PredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4), - "if ("#!if(isPredNot, "!", "")#"$src1) "#mnemonic#"($src2++$src3)" - #!if(isNT, ":nt", "")#" = $src4", [], - "$src2 = $_dst_">, NewValueRel { - let isPredicatedFalse = isPredNot; -} - -let isNVStorable = 1, BaseOpcode = "vS32b_ppu" in { - def V6_vS32b_pred_ppu : T_vstore_pred_ppu<"vmem">, V6_vS32b_pred_ppu_enc; - def V6_vS32b_npred_ppu: T_vstore_pred_ppu<"vmem", 1>, V6_vS32b_npred_ppu_enc; -} - -let isNVStorable = 1, BaseOpcode = "vS32b_ppu", isNonTemporal = 1 in { - def V6_vS32b_nt_pred_ppu : T_vstore_pred_ppu <"vmem", 0, 1>, - V6_vS32b_nt_pred_ppu_enc; - def V6_vS32b_nt_npred_ppu : T_vstore_pred_ppu <"vmem", 1, 1>, - V6_vS32b_nt_npred_ppu_enc; -} - -let BaseOpcode = "vS32Ub_ppu", Itinerary = CVI_VM_STU, - Type = TypeCVI_VM_STU in { - def V6_vS32Ub_pred_ppu : T_vstore_pred_ppu <"vmemu">, - V6_vS32Ub_pred_ppu_enc; - def V6_vS32Ub_npred_ppu : T_vstore_pred_ppu <"vmemu", 1>, - V6_vS32Ub_npred_ppu_enc; -} - -//===----------------------------------------------------------------------===// -// Post increment vector stores with register offset - byte-enabled aligned -//===----------------------------------------------------------------------===// -class T_vstore_qpred_ppu <bit isPredNot = 0, bit isNT = 0> - : V6_STInst <(outs IntRegs:$_dst_), - (ins VecPredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4), - "if ("#!if(isPredNot, "!", "")#"$src1) vmem($src2++$src3)" - #!if(isNT, ":nt", "")#" = $src4", [], - "$src2 = $_dst_">, NewValueRel; - -def V6_vS32b_qpred_ppu : T_vstore_qpred_ppu, V6_vS32b_qpred_ppu_enc; -def V6_vS32b_nqpred_ppu : T_vstore_qpred_ppu<1>, V6_vS32b_nqpred_ppu_enc; -def V6_vS32b_nt_qpred_ppu : T_vstore_qpred_ppu<0, 1>, - V6_vS32b_nt_qpred_ppu_enc; -def V6_vS32b_nt_nqpred_ppu : T_vstore_qpred_ppu<1, 1>, - V6_vS32b_nt_nqpred_ppu_enc; - -//===----------------------------------------------------------------------===// -// Post increment conditional .new vector stores with register offset -//===----------------------------------------------------------------------===// -let Itinerary = CVI_VM_NEW_ST, Type = TypeCVI_VM_NEW_ST, isPredicated = 1, - isNewValue = 1, opNewValue = 4, isNVStore = 1 in -class T_vstore_new_pred_ppu <bit isPredNot = 0, bit isNT = 0> - : V6_STInst <(outs IntRegs:$_dst_), - (ins PredRegs:$src1, IntRegs:$src2, ModRegs:$src3, VectorRegs:$src4), - "if("#!if(isPredNot, "!", "")#"$src1) vmem($src2++$src3)" - #!if(isNT, ":nt", "")#" = $src4.new", [], - "$src2 = $_dst_">, NewValueRel { - let isPredicatedFalse = isPredNot; -} - -let BaseOpcode = "vS32b_ppu" in { - def V6_vS32b_new_pred_ppu : T_vstore_new_pred_ppu, - V6_vS32b_new_pred_ppu_enc; - def V6_vS32b_new_npred_ppu : T_vstore_new_pred_ppu<1>, - V6_vS32b_new_npred_ppu_enc; -} - -let BaseOpcode = "vS32b_ppu", isNonTemporal = 1 in { -def V6_vS32b_nt_new_pred_ppu : T_vstore_new_pred_ppu<0, 1>, - V6_vS32b_nt_new_pred_ppu_enc; -def V6_vS32b_nt_new_npred_ppu : T_vstore_new_pred_ppu<1, 1>, - V6_vS32b_nt_new_npred_ppu_enc; -} - - -// Vector load/store pseudos - -let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in -class STrivv_template<RegisterClass RC> - : V6_STInst<(outs), (ins IntRegs:$addr, s32_0Imm:$off, RC:$src), "", []>; - -def PS_vstorerw_ai: STrivv_template<VecDblRegs>, - Requires<[HasV60T,UseHVXSgl]>; -def PS_vstorerwu_ai: STrivv_template<VecDblRegs>, - Requires<[HasV60T,UseHVXSgl]>; -def PS_vstorerw_ai_128B: STrivv_template<VecDblRegs128B>, - Requires<[HasV60T,UseHVXDbl]>; -def PS_vstorerwu_ai_128B: STrivv_template<VecDblRegs128B>, - Requires<[HasV60T,UseHVXDbl]>; - - -let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in -class LDrivv_template<RegisterClass RC> - : V6_LDInst<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off), "", []>; - -def PS_vloadrw_ai: LDrivv_template<VecDblRegs>, - Requires<[HasV60T,UseHVXSgl]>; -def PS_vloadrwu_ai: LDrivv_template<VecDblRegs>, - Requires<[HasV60T,UseHVXSgl]>; -def PS_vloadrw_ai_128B: LDrivv_template<VecDblRegs128B>, - Requires<[HasV60T,UseHVXDbl]>; -def PS_vloadrwu_ai_128B: LDrivv_template<VecDblRegs128B>, - Requires<[HasV60T,UseHVXDbl]>; - -// Store vector predicate pseudo. -let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13, - isCodeGenOnly = 1, isPseudo = 1, mayStore = 1, hasSideEffects = 0 in { - def PS_vstorerq_ai : STInst<(outs), - (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs:$src1), - ".error \"should not emit\"", []>, - Requires<[HasV60T,UseHVXSgl]>; - def PS_vstorerq_ai_128B : STInst<(outs), - (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs128B:$src1), - ".error \"should not emit\"", []>, - Requires<[HasV60T,UseHVXDbl]>; -} - -// Load vector predicate pseudo. -let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13, - opExtentAlign = 2, isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in { - def PS_vloadrq_ai : LDInst<(outs VecPredRegs:$dst), - (ins IntRegs:$base, s32_0Imm:$offset), - ".error \"should not emit\"", []>, - Requires<[HasV60T,UseHVXSgl]>; - def PS_vloadrq_ai_128B : LDInst<(outs VecPredRegs128B:$dst), - (ins IntRegs:$base, s32_0Imm:$offset), - ".error \"should not emit\"", []>, - Requires<[HasV60T,UseHVXDbl]>; -} - -class VSELInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], - string cstr = "", InstrItinClass itin = CVI_VA_DV, - IType type = TypeCVI_VA_DV> - : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>; - -let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in { - def PS_vselect: VSELInst<(outs VectorRegs:$dst), - (ins PredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), "", []>, - Requires<[HasV60T,UseHVXSgl]>; - def PS_vselect_128B: VSELInst<(outs VectorRegs128B:$dst), - (ins PredRegs:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3), - "", []>, Requires<[HasV60T,UseHVXDbl]>; - def PS_wselect: VSELInst<(outs VecDblRegs:$dst), - (ins PredRegs:$src1, VecDblRegs:$src2, VecDblRegs:$src3), "", []>, - Requires<[HasV60T,UseHVXSgl]>; - def PS_wselect_128B: VSELInst<(outs VecDblRegs128B:$dst), - (ins PredRegs:$src1, VecDblRegs128B:$src2, VecDblRegs128B:$src3), - "", []>, Requires<[HasV60T,UseHVXDbl]>; -} - -let hasNewValue = 1 in -class T_vmpy <string asmString, RegisterClass RCout, RegisterClass RCin> - : CVI_VX_DV_Resource1<(outs RCout:$dst), (ins RCin:$src1, IntRegs:$src2), - asmString >; - -multiclass T_vmpy <string asmString, RegisterClass RCout, - RegisterClass RCin> { - def NAME : T_vmpy <asmString, RCout, RCin>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_vmpy <asmString, !cast<RegisterClass>(RCout#"128B"), - !cast<RegisterClass>(RCin#"128B")>; -} - -multiclass T_vmpy_VV <string asmString>: - T_vmpy <asmString, VectorRegs, VectorRegs>; - -multiclass T_vmpy_WW <string asmString>: - T_vmpy <asmString, VecDblRegs, VecDblRegs>; - -multiclass T_vmpy_VW <string asmString>: - T_vmpy <asmString, VectorRegs, VecDblRegs>; - -multiclass T_vmpy_WV <string asmString>: - T_vmpy <asmString, VecDblRegs, VectorRegs>; - -defm V6_vtmpyb :T_vmpy_WW<"$dst.h = vtmpy($src1.b,$src2.b)">, V6_vtmpyb_enc; -defm V6_vtmpybus :T_vmpy_WW<"$dst.h = vtmpy($src1.ub,$src2.b)">, V6_vtmpybus_enc; -defm V6_vdsaduh :T_vmpy_WW<"$dst.uw = vdsad($src1.uh,$src2.uh)">, V6_vdsaduh_enc; -defm V6_vmpybus :T_vmpy_WV<"$dst.h = vmpy($src1.ub,$src2.b)">, V6_vmpybus_enc; -defm V6_vmpabus :T_vmpy_WW<"$dst.h = vmpa($src1.ub,$src2.b)">, V6_vmpabus_enc; -defm V6_vmpahb :T_vmpy_WW<"$dst.w = vmpa($src1.h,$src2.b)">, V6_vmpahb_enc; -defm V6_vmpyh :T_vmpy_WV<"$dst.w = vmpy($src1.h,$src2.h)">, V6_vmpyh_enc; -defm V6_vmpyuh :T_vmpy_WV<"$dst.uw = vmpy($src1.uh,$src2.uh)">, V6_vmpyuh_enc; -defm V6_vmpyiwh :T_vmpy_VV<"$dst.w = vmpyi($src1.w,$src2.h)">, V6_vmpyiwh_enc; -defm V6_vtmpyhb :T_vmpy_WW<"$dst.w = vtmpy($src1.h,$src2.b)">, V6_vtmpyhb_enc; -defm V6_vmpyub :T_vmpy_WV<"$dst.uh = vmpy($src1.ub,$src2.ub)">, V6_vmpyub_enc; - -let Itinerary = CVI_VX_LONG, Type = TypeCVI_VX in -defm V6_vmpyihb :T_vmpy_VV<"$dst.h = vmpyi($src1.h,$src2.b)">, V6_vmpyihb_enc; - -defm V6_vdmpybus_dv : - T_vmpy_WW <"$dst.h = vdmpy($src1.ub,$src2.b)">, V6_vdmpybus_dv_enc; -defm V6_vdmpyhsusat : - T_vmpy_VV <"$dst.w = vdmpy($src1.h,$src2.uh):sat">, V6_vdmpyhsusat_enc; -defm V6_vdmpyhsuisat : - T_vmpy_VW <"$dst.w = vdmpy($src1.h,$src2.uh,#1):sat">, V6_vdmpyhsuisat_enc; -defm V6_vdmpyhsat : - T_vmpy_VV <"$dst.w = vdmpy($src1.h,$src2.h):sat">, V6_vdmpyhsat_enc; -defm V6_vdmpyhisat : - T_vmpy_VW <"$dst.w = vdmpy($src1.h,$src2.h):sat">, V6_vdmpyhisat_enc; -defm V6_vdmpyhb_dv : - T_vmpy_WW <"$dst.w = vdmpy($src1.h,$src2.b)">, V6_vdmpyhb_dv_enc; -defm V6_vmpyhss : - T_vmpy_VV <"$dst.h = vmpy($src1.h,$src2.h):<<1:sat">, V6_vmpyhss_enc; -defm V6_vmpyhsrs : - T_vmpy_VV <"$dst.h = vmpy($src1.h,$src2.h):<<1:rnd:sat">, V6_vmpyhsrs_enc; - -let Itinerary = CVI_VP, Type = TypeCVI_VP in -defm V6_vror : T_vmpy_VV <"$dst = vror($src1,$src2)">, V6_vror_enc; - -let Itinerary = CVI_VX, Type = TypeCVI_VX in { -defm V6_vdmpyhb : T_vmpy_VV<"$dst.w = vdmpy($src1.h,$src2.b)">, V6_vdmpyhb_enc; -defm V6_vrmpybus : T_vmpy_VV<"$dst.w = vrmpy($src1.ub,$src2.b)">, V6_vrmpybus_enc; -defm V6_vdmpybus : T_vmpy_VV<"$dst.h = vdmpy($src1.ub,$src2.b)">, V6_vdmpybus_enc; -defm V6_vmpyiwb : T_vmpy_VV<"$dst.w = vmpyi($src1.w,$src2.b)">, V6_vmpyiwb_enc; -defm V6_vrmpyub : T_vmpy_VV<"$dst.uw = vrmpy($src1.ub,$src2.ub)">, V6_vrmpyub_enc; -} - -let Itinerary = CVI_VS, Type = TypeCVI_VS in { -defm V6_vasrw : T_vmpy_VV <"$dst.w = vasr($src1.w,$src2)">, V6_vasrw_enc; -defm V6_vasrh : T_vmpy_VV <"$dst.h = vasr($src1.h,$src2)">, V6_vasrh_enc; -defm V6_vaslw : T_vmpy_VV <"$dst.w = vasl($src1.w,$src2)">, V6_vaslw_enc; -defm V6_vaslh : T_vmpy_VV <"$dst.h = vasl($src1.h,$src2)">, V6_vaslh_enc; -defm V6_vlsrw : T_vmpy_VV <"$dst.uw = vlsr($src1.uw,$src2)">, V6_vlsrw_enc; -defm V6_vlsrh : T_vmpy_VV <"$dst.uh = vlsr($src1.uh,$src2)">, V6_vlsrh_enc; -} - -let hasNewValue = 1 in -class T_HVX_alu <string asmString, InstrItinClass itin, - RegisterClass RCout, RegisterClass RCin> - : CVI_VA_Resource1 <(outs RCout:$dst), (ins RCin:$src1, RCin:$src2), - asmString >{ - let Itinerary = itin; - let Type = !cast<IType>("Type"#itin); -} - -multiclass T_HVX_alu <string asmString, RegisterClass RCout, - RegisterClass RCin, InstrItinClass itin> { - def NAME : T_HVX_alu <asmString, itin, RCout, RCin>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_alu <asmString, itin, - !cast<RegisterClass>(RCout#"128B"), - !cast<RegisterClass>(RCin#"128B")>; -} - -multiclass T_HVX_alu_VV <string asmString>: - T_HVX_alu <asmString, VectorRegs, VectorRegs, CVI_VA>; - -multiclass T_HVX_alu_WW <string asmString>: - T_HVX_alu <asmString, VecDblRegs, VecDblRegs, CVI_VA_DV>; - -multiclass T_HVX_alu_WV <string asmString>: - T_HVX_alu <asmString, VecDblRegs, VectorRegs, CVI_VX_DV>; - - -let Itinerary = CVI_VX, Type = TypeCVI_VX in { -defm V6_vrmpyubv : - T_HVX_alu_VV <"$dst.uw = vrmpy($src1.ub,$src2.ub)">, V6_vrmpyubv_enc; -defm V6_vrmpybv : - T_HVX_alu_VV <"$dst.w = vrmpy($src1.b,$src2.b)">, V6_vrmpybv_enc; -defm V6_vrmpybusv : - T_HVX_alu_VV <"$dst.w = vrmpy($src1.ub,$src2.b)">, V6_vrmpybusv_enc; -defm V6_vabsdiffub : - T_HVX_alu_VV <"$dst.ub = vabsdiff($src1.ub,$src2.ub)">, V6_vabsdiffub_enc; -defm V6_vabsdiffh : - T_HVX_alu_VV <"$dst.uh = vabsdiff($src1.h,$src2.h)">, V6_vabsdiffh_enc; -defm V6_vabsdiffuh : - T_HVX_alu_VV <"$dst.uh = vabsdiff($src1.uh,$src2.uh)">, V6_vabsdiffuh_enc; -defm V6_vabsdiffw : - T_HVX_alu_VV <"$dst.uw = vabsdiff($src1.w,$src2.w)">, V6_vabsdiffw_enc; -} - -let Itinerary = CVI_VX_DV, Type = TypeCVI_VX_DV in { -defm V6_vdmpyhvsat : - T_HVX_alu_VV <"$dst.w = vdmpy($src1.h,$src2.h):sat">, V6_vdmpyhvsat_enc; -defm V6_vmpyhvsrs : - T_HVX_alu_VV<"$dst.h = vmpy($src1.h,$src2.h):<<1:rnd:sat">, V6_vmpyhvsrs_enc; -defm V6_vmpyih : - T_HVX_alu_VV <"$dst.h = vmpyi($src1.h,$src2.h)">, V6_vmpyih_enc; -} - -defm V6_vand : - T_HVX_alu_VV <"$dst = vand($src1,$src2)">, V6_vand_enc; -defm V6_vor : - T_HVX_alu_VV <"$dst = vor($src1,$src2)">, V6_vor_enc; -defm V6_vxor : - T_HVX_alu_VV <"$dst = vxor($src1,$src2)">, V6_vxor_enc; -defm V6_vaddw : - T_HVX_alu_VV <"$dst.w = vadd($src1.w,$src2.w)">, V6_vaddw_enc; -defm V6_vaddubsat : - T_HVX_alu_VV <"$dst.ub = vadd($src1.ub,$src2.ub):sat">, V6_vaddubsat_enc; -defm V6_vadduhsat : - T_HVX_alu_VV <"$dst.uh = vadd($src1.uh,$src2.uh):sat">, V6_vadduhsat_enc; -defm V6_vaddhsat : - T_HVX_alu_VV <"$dst.h = vadd($src1.h,$src2.h):sat">, V6_vaddhsat_enc; -defm V6_vaddwsat : - T_HVX_alu_VV <"$dst.w = vadd($src1.w,$src2.w):sat">, V6_vaddwsat_enc; -defm V6_vsubb : - T_HVX_alu_VV <"$dst.b = vsub($src1.b,$src2.b)">, V6_vsubb_enc; -defm V6_vsubh : - T_HVX_alu_VV <"$dst.h = vsub($src1.h,$src2.h)">, V6_vsubh_enc; -defm V6_vsubw : - T_HVX_alu_VV <"$dst.w = vsub($src1.w,$src2.w)">, V6_vsubw_enc; -defm V6_vsububsat : - T_HVX_alu_VV <"$dst.ub = vsub($src1.ub,$src2.ub):sat">, V6_vsububsat_enc; -defm V6_vsubuhsat : - T_HVX_alu_VV <"$dst.uh = vsub($src1.uh,$src2.uh):sat">, V6_vsubuhsat_enc; -defm V6_vsubhsat : - T_HVX_alu_VV <"$dst.h = vsub($src1.h,$src2.h):sat">, V6_vsubhsat_enc; -defm V6_vsubwsat : - T_HVX_alu_VV <"$dst.w = vsub($src1.w,$src2.w):sat">, V6_vsubwsat_enc; -defm V6_vavgub : - T_HVX_alu_VV <"$dst.ub = vavg($src1.ub,$src2.ub)">, V6_vavgub_enc; -defm V6_vavguh : - T_HVX_alu_VV <"$dst.uh = vavg($src1.uh,$src2.uh)">, V6_vavguh_enc; -defm V6_vavgh : - T_HVX_alu_VV <"$dst.h = vavg($src1.h,$src2.h)">, V6_vavgh_enc; -defm V6_vavgw : - T_HVX_alu_VV <"$dst.w = vavg($src1.w,$src2.w)">, V6_vavgw_enc; -defm V6_vnavgub : - T_HVX_alu_VV <"$dst.b = vnavg($src1.ub,$src2.ub)">, V6_vnavgub_enc; -defm V6_vnavgh : - T_HVX_alu_VV <"$dst.h = vnavg($src1.h,$src2.h)">, V6_vnavgh_enc; -defm V6_vnavgw : - T_HVX_alu_VV <"$dst.w = vnavg($src1.w,$src2.w)">, V6_vnavgw_enc; -defm V6_vavgubrnd : - T_HVX_alu_VV <"$dst.ub = vavg($src1.ub,$src2.ub):rnd">, V6_vavgubrnd_enc; -defm V6_vavguhrnd : - T_HVX_alu_VV <"$dst.uh = vavg($src1.uh,$src2.uh):rnd">, V6_vavguhrnd_enc; -defm V6_vavghrnd : - T_HVX_alu_VV <"$dst.h = vavg($src1.h,$src2.h):rnd">, V6_vavghrnd_enc; -defm V6_vavgwrnd : - T_HVX_alu_VV <"$dst.w = vavg($src1.w,$src2.w):rnd">, V6_vavgwrnd_enc; - -defm V6_vmpybv : - T_HVX_alu_WV <"$dst.h = vmpy($src1.b,$src2.b)">, V6_vmpybv_enc; -defm V6_vmpyubv : - T_HVX_alu_WV <"$dst.uh = vmpy($src1.ub,$src2.ub)">, V6_vmpyubv_enc; -defm V6_vmpybusv : - T_HVX_alu_WV <"$dst.h = vmpy($src1.ub,$src2.b)">, V6_vmpybusv_enc; -defm V6_vmpyhv : - T_HVX_alu_WV <"$dst.w = vmpy($src1.h,$src2.h)">, V6_vmpyhv_enc; -defm V6_vmpyuhv : - T_HVX_alu_WV <"$dst.uw = vmpy($src1.uh,$src2.uh)">, V6_vmpyuhv_enc; -defm V6_vmpyhus : - T_HVX_alu_WV <"$dst.w = vmpy($src1.h,$src2.uh)">, V6_vmpyhus_enc; -defm V6_vaddubh : - T_HVX_alu_WV <"$dst.h = vadd($src1.ub,$src2.ub)">, V6_vaddubh_enc; -defm V6_vadduhw : - T_HVX_alu_WV <"$dst.w = vadd($src1.uh,$src2.uh)">, V6_vadduhw_enc; -defm V6_vaddhw : - T_HVX_alu_WV <"$dst.w = vadd($src1.h,$src2.h)">, V6_vaddhw_enc; -defm V6_vsububh : - T_HVX_alu_WV <"$dst.h = vsub($src1.ub,$src2.ub)">, V6_vsububh_enc; -defm V6_vsubuhw : - T_HVX_alu_WV <"$dst.w = vsub($src1.uh,$src2.uh)">, V6_vsubuhw_enc; -defm V6_vsubhw : - T_HVX_alu_WV <"$dst.w = vsub($src1.h,$src2.h)">, V6_vsubhw_enc; - -defm V6_vaddb_dv : - T_HVX_alu_WW <"$dst.b = vadd($src1.b,$src2.b)">, V6_vaddb_dv_enc; -defm V6_vaddh_dv : - T_HVX_alu_WW <"$dst.h = vadd($src1.h,$src2.h)">, V6_vaddh_dv_enc; -defm V6_vaddw_dv : - T_HVX_alu_WW <"$dst.w = vadd($src1.w,$src2.w)">, V6_vaddw_dv_enc; -defm V6_vaddubsat_dv : - T_HVX_alu_WW <"$dst.ub = vadd($src1.ub,$src2.ub):sat">, V6_vaddubsat_dv_enc; -defm V6_vadduhsat_dv : - T_HVX_alu_WW <"$dst.uh = vadd($src1.uh,$src2.uh):sat">, V6_vadduhsat_dv_enc; -defm V6_vaddhsat_dv : - T_HVX_alu_WW <"$dst.h = vadd($src1.h,$src2.h):sat">, V6_vaddhsat_dv_enc; -defm V6_vaddwsat_dv : - T_HVX_alu_WW <"$dst.w = vadd($src1.w,$src2.w):sat">, V6_vaddwsat_dv_enc; -defm V6_vsubb_dv : - T_HVX_alu_WW <"$dst.b = vsub($src1.b,$src2.b)">, V6_vsubb_dv_enc; -defm V6_vsubh_dv : - T_HVX_alu_WW <"$dst.h = vsub($src1.h,$src2.h)">, V6_vsubh_dv_enc; -defm V6_vsubw_dv : - T_HVX_alu_WW <"$dst.w = vsub($src1.w,$src2.w)">, V6_vsubw_dv_enc; -defm V6_vsububsat_dv : - T_HVX_alu_WW <"$dst.ub = vsub($src1.ub,$src2.ub):sat">, V6_vsububsat_dv_enc; -defm V6_vsubuhsat_dv : - T_HVX_alu_WW <"$dst.uh = vsub($src1.uh,$src2.uh):sat">, V6_vsubuhsat_dv_enc; -defm V6_vsubhsat_dv : - T_HVX_alu_WW <"$dst.h = vsub($src1.h,$src2.h):sat">, V6_vsubhsat_dv_enc; -defm V6_vsubwsat_dv : - T_HVX_alu_WW <"$dst.w = vsub($src1.w,$src2.w):sat">, V6_vsubwsat_dv_enc; - -let Itinerary = CVI_VX_DV_LONG, Type = TypeCVI_VX_DV in { -defm V6_vmpabusv : - T_HVX_alu_WW <"$dst.h = vmpa($src1.ub,$src2.b)">, V6_vmpabusv_enc; -defm V6_vmpabuuv : - T_HVX_alu_WW <"$dst.h = vmpa($src1.ub,$src2.ub)">, V6_vmpabuuv_enc; -} - -let isAccumulator = 1, hasNewValue = 1 in -class T_HVX_vmpyacc <string asmString, InstrItinClass itin, RegisterClass RCout, - RegisterClass RCin1, RegisterClass RCin2> - : CVI_VA_Resource1 <(outs RCout:$dst), - (ins RCout:$_src_, RCin1:$src1, RCin2:$src2), asmString, - [], "$dst = $_src_" > { - let Itinerary = itin; - let Type = !cast<IType>("Type"#itin); -} - -multiclass T_HVX_vmpyacc_both <string asmString, RegisterClass RCout, - RegisterClass RCin1, RegisterClass RCin2, InstrItinClass itin > { - def NAME : T_HVX_vmpyacc <asmString, itin, RCout, RCin1, RCin2>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_vmpyacc <asmString, itin, - !cast<RegisterClass>(RCout#"128B"), - !cast<RegisterClass>(RCin1#"128B"), - !cast<RegisterClass>(RCin2# - !if(!eq (!cast<string>(RCin2), "IntRegs"), "", "128B"))>; -} - -multiclass T_HVX_vmpyacc_VVR <string asmString>: - T_HVX_vmpyacc_both <asmString, VectorRegs, VectorRegs, IntRegs, CVI_VX>; - -multiclass T_HVX_vmpyacc_VWR <string asmString>: - T_HVX_vmpyacc_both <asmString, VectorRegs, VecDblRegs, IntRegs, CVI_VX_DV>; - -multiclass T_HVX_vmpyacc_WVR <string asmString>: - T_HVX_vmpyacc_both <asmString, VecDblRegs, VectorRegs, IntRegs, CVI_VX_DV>; - -multiclass T_HVX_vmpyacc_WWR <string asmString>: - T_HVX_vmpyacc_both <asmString, VecDblRegs, VecDblRegs, IntRegs, CVI_VX_DV>; - -multiclass T_HVX_vmpyacc_VVV <string asmString>: - T_HVX_vmpyacc_both <asmString, VectorRegs, VectorRegs, VectorRegs, CVI_VX_DV>; - -multiclass T_HVX_vmpyacc_WVV <string asmString>: - T_HVX_vmpyacc_both <asmString, VecDblRegs, VectorRegs, VectorRegs, CVI_VX_DV>; - - -defm V6_vtmpyb_acc : - T_HVX_vmpyacc_WWR <"$dst.h += vtmpy($src1.b,$src2.b)">, - V6_vtmpyb_acc_enc; -defm V6_vtmpybus_acc : - T_HVX_vmpyacc_WWR <"$dst.h += vtmpy($src1.ub,$src2.b)">, - V6_vtmpybus_acc_enc; -defm V6_vtmpyhb_acc : - T_HVX_vmpyacc_WWR <"$dst.w += vtmpy($src1.h,$src2.b)">, - V6_vtmpyhb_acc_enc; -defm V6_vdmpyhb_acc : - T_HVX_vmpyacc_VVR <"$dst.w += vdmpy($src1.h,$src2.b)">, - V6_vdmpyhb_acc_enc; -defm V6_vrmpyub_acc : - T_HVX_vmpyacc_VVR <"$dst.uw += vrmpy($src1.ub,$src2.ub)">, - V6_vrmpyub_acc_enc; -defm V6_vrmpybus_acc : - T_HVX_vmpyacc_VVR <"$dst.w += vrmpy($src1.ub,$src2.b)">, - V6_vrmpybus_acc_enc; -defm V6_vdmpybus_acc : - T_HVX_vmpyacc_VVR <"$dst.h += vdmpy($src1.ub,$src2.b)">, - V6_vdmpybus_acc_enc; -defm V6_vdmpybus_dv_acc : - T_HVX_vmpyacc_WWR <"$dst.h += vdmpy($src1.ub,$src2.b)">, - V6_vdmpybus_dv_acc_enc; -defm V6_vdmpyhsuisat_acc : - T_HVX_vmpyacc_VWR <"$dst.w += vdmpy($src1.h,$src2.uh,#1):sat">, - V6_vdmpyhsuisat_acc_enc; -defm V6_vdmpyhisat_acc : - T_HVX_vmpyacc_VWR <"$dst.w += vdmpy($src1.h,$src2.h):sat">, - V6_vdmpyhisat_acc_enc; -defm V6_vdmpyhb_dv_acc : - T_HVX_vmpyacc_WWR <"$dst.w += vdmpy($src1.h,$src2.b)">, - V6_vdmpyhb_dv_acc_enc; -defm V6_vmpybus_acc : - T_HVX_vmpyacc_WVR <"$dst.h += vmpy($src1.ub,$src2.b)">, - V6_vmpybus_acc_enc; -defm V6_vmpabus_acc : - T_HVX_vmpyacc_WWR <"$dst.h += vmpa($src1.ub,$src2.b)">, - V6_vmpabus_acc_enc; -defm V6_vmpahb_acc : - T_HVX_vmpyacc_WWR <"$dst.w += vmpa($src1.h,$src2.b)">, - V6_vmpahb_acc_enc; -defm V6_vmpyhsat_acc : - T_HVX_vmpyacc_WVR <"$dst.w += vmpy($src1.h,$src2.h):sat">, - V6_vmpyhsat_acc_enc; -defm V6_vmpyuh_acc : - T_HVX_vmpyacc_WVR <"$dst.uw += vmpy($src1.uh,$src2.uh)">, - V6_vmpyuh_acc_enc; -defm V6_vmpyiwb_acc : - T_HVX_vmpyacc_VVR <"$dst.w += vmpyi($src1.w,$src2.b)">, - V6_vmpyiwb_acc_enc; -defm V6_vdsaduh_acc : - T_HVX_vmpyacc_WWR <"$dst.uw += vdsad($src1.uh,$src2.uh)">, - V6_vdsaduh_acc_enc; -defm V6_vmpyihb_acc : - T_HVX_vmpyacc_VVR <"$dst.h += vmpyi($src1.h,$src2.b)">, - V6_vmpyihb_acc_enc; -defm V6_vmpyub_acc : - T_HVX_vmpyacc_WVR <"$dst.uh += vmpy($src1.ub,$src2.ub)">, - V6_vmpyub_acc_enc; - -let Itinerary = CVI_VX_DV, Type = TypeCVI_VX_DV in { -defm V6_vdmpyhsusat_acc : - T_HVX_vmpyacc_VVR <"$dst.w += vdmpy($src1.h,$src2.uh):sat">, - V6_vdmpyhsusat_acc_enc; -defm V6_vdmpyhsat_acc : - T_HVX_vmpyacc_VVR <"$dst.w += vdmpy($src1.h,$src2.h):sat">, - V6_vdmpyhsat_acc_enc; -defm V6_vmpyiwh_acc : T_HVX_vmpyacc_VVR - <"$dst.w += vmpyi($src1.w,$src2.h)">, V6_vmpyiwh_acc_enc; -} - -let Itinerary = CVI_VS, Type = TypeCVI_VS in { -defm V6_vaslw_acc : - T_HVX_vmpyacc_VVR <"$dst.w += vasl($src1.w,$src2)">, V6_vaslw_acc_enc; -defm V6_vasrw_acc : - T_HVX_vmpyacc_VVR <"$dst.w += vasr($src1.w,$src2)">, V6_vasrw_acc_enc; -} - -defm V6_vdmpyhvsat_acc : - T_HVX_vmpyacc_VVV <"$dst.w += vdmpy($src1.h,$src2.h):sat">, - V6_vdmpyhvsat_acc_enc; -defm V6_vmpybusv_acc : - T_HVX_vmpyacc_WVV <"$dst.h += vmpy($src1.ub,$src2.b)">, - V6_vmpybusv_acc_enc; -defm V6_vmpybv_acc : - T_HVX_vmpyacc_WVV <"$dst.h += vmpy($src1.b,$src2.b)">, V6_vmpybv_acc_enc; -defm V6_vmpyhus_acc : - T_HVX_vmpyacc_WVV <"$dst.w += vmpy($src1.h,$src2.uh)">, V6_vmpyhus_acc_enc; -defm V6_vmpyhv_acc : - T_HVX_vmpyacc_WVV <"$dst.w += vmpy($src1.h,$src2.h)">, V6_vmpyhv_acc_enc; -defm V6_vmpyiewh_acc : - T_HVX_vmpyacc_VVV <"$dst.w += vmpyie($src1.w,$src2.h)">, - V6_vmpyiewh_acc_enc; -defm V6_vmpyiewuh_acc : - T_HVX_vmpyacc_VVV <"$dst.w += vmpyie($src1.w,$src2.uh)">, - V6_vmpyiewuh_acc_enc; -defm V6_vmpyih_acc : - T_HVX_vmpyacc_VVV <"$dst.h += vmpyi($src1.h,$src2.h)">, V6_vmpyih_acc_enc; -defm V6_vmpyowh_rnd_sacc : - T_HVX_vmpyacc_VVV <"$dst.w += vmpyo($src1.w,$src2.h):<<1:rnd:sat:shift">, - V6_vmpyowh_rnd_sacc_enc; -defm V6_vmpyowh_sacc : - T_HVX_vmpyacc_VVV <"$dst.w += vmpyo($src1.w,$src2.h):<<1:sat:shift">, - V6_vmpyowh_sacc_enc; -defm V6_vmpyubv_acc : - T_HVX_vmpyacc_WVV <"$dst.uh += vmpy($src1.ub,$src2.ub)">, - V6_vmpyubv_acc_enc; -defm V6_vmpyuhv_acc : - T_HVX_vmpyacc_WVV <"$dst.uw += vmpy($src1.uh,$src2.uh)">, - V6_vmpyuhv_acc_enc; -defm V6_vrmpybusv_acc : - T_HVX_vmpyacc_VVV <"$dst.w += vrmpy($src1.ub,$src2.b)">, - V6_vrmpybusv_acc_enc; -defm V6_vrmpybv_acc : - T_HVX_vmpyacc_VVV <"$dst.w += vrmpy($src1.b,$src2.b)">, V6_vrmpybv_acc_enc; -defm V6_vrmpyubv_acc : - T_HVX_vmpyacc_VVV <"$dst.uw += vrmpy($src1.ub,$src2.ub)">, - V6_vrmpyubv_acc_enc; - - -class T_HVX_vcmp <string asmString, RegisterClass RCout, RegisterClass RCin> - : CVI_VA_Resource1 <(outs RCout:$dst), - (ins RCout:$_src_, RCin:$src1, RCin:$src2), asmString, - [], "$dst = $_src_" > { - let Itinerary = CVI_VA; - let Type = TypeCVI_VA; -} - -multiclass T_HVX_vcmp <string asmString> { - def NAME : T_HVX_vcmp <asmString, VecPredRegs, VectorRegs>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_vcmp <asmString, VecPredRegs128B, VectorRegs128B>; -} - -defm V6_veqb_and : - T_HVX_vcmp <"$dst &= vcmp.eq($src1.b,$src2.b)">, V6_veqb_and_enc; -defm V6_veqh_and : - T_HVX_vcmp <"$dst &= vcmp.eq($src1.h,$src2.h)">, V6_veqh_and_enc; -defm V6_veqw_and : - T_HVX_vcmp <"$dst &= vcmp.eq($src1.w,$src2.w)">, V6_veqw_and_enc; -defm V6_vgtb_and : - T_HVX_vcmp <"$dst &= vcmp.gt($src1.b,$src2.b)">, V6_vgtb_and_enc; -defm V6_vgth_and : - T_HVX_vcmp <"$dst &= vcmp.gt($src1.h,$src2.h)">, V6_vgth_and_enc; -defm V6_vgtw_and : - T_HVX_vcmp <"$dst &= vcmp.gt($src1.w,$src2.w)">, V6_vgtw_and_enc; -defm V6_vgtub_and : - T_HVX_vcmp <"$dst &= vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_and_enc; -defm V6_vgtuh_and : - T_HVX_vcmp <"$dst &= vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_and_enc; -defm V6_vgtuw_and : - T_HVX_vcmp <"$dst &= vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_and_enc; -defm V6_veqb_or : - T_HVX_vcmp <"$dst |= vcmp.eq($src1.b,$src2.b)">, V6_veqb_or_enc; -defm V6_veqh_or : - T_HVX_vcmp <"$dst |= vcmp.eq($src1.h,$src2.h)">, V6_veqh_or_enc; -defm V6_veqw_or : - T_HVX_vcmp <"$dst |= vcmp.eq($src1.w,$src2.w)">, V6_veqw_or_enc; -defm V6_vgtb_or : - T_HVX_vcmp <"$dst |= vcmp.gt($src1.b,$src2.b)">, V6_vgtb_or_enc; -defm V6_vgth_or : - T_HVX_vcmp <"$dst |= vcmp.gt($src1.h,$src2.h)">, V6_vgth_or_enc; -defm V6_vgtw_or : - T_HVX_vcmp <"$dst |= vcmp.gt($src1.w,$src2.w)">, V6_vgtw_or_enc; -defm V6_vgtub_or : - T_HVX_vcmp <"$dst |= vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_or_enc; -defm V6_vgtuh_or : - T_HVX_vcmp <"$dst |= vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_or_enc; -defm V6_vgtuw_or : - T_HVX_vcmp <"$dst |= vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_or_enc; -defm V6_veqb_xor : - T_HVX_vcmp <"$dst ^= vcmp.eq($src1.b,$src2.b)">, V6_veqb_xor_enc; -defm V6_veqh_xor : - T_HVX_vcmp <"$dst ^= vcmp.eq($src1.h,$src2.h)">, V6_veqh_xor_enc; -defm V6_veqw_xor : - T_HVX_vcmp <"$dst ^= vcmp.eq($src1.w,$src2.w)">, V6_veqw_xor_enc; -defm V6_vgtb_xor : - T_HVX_vcmp <"$dst ^= vcmp.gt($src1.b,$src2.b)">, V6_vgtb_xor_enc; -defm V6_vgth_xor : - T_HVX_vcmp <"$dst ^= vcmp.gt($src1.h,$src2.h)">, V6_vgth_xor_enc; -defm V6_vgtw_xor : - T_HVX_vcmp <"$dst ^= vcmp.gt($src1.w,$src2.w)">, V6_vgtw_xor_enc; -defm V6_vgtub_xor : - T_HVX_vcmp <"$dst ^= vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_xor_enc; -defm V6_vgtuh_xor : - T_HVX_vcmp <"$dst ^= vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_xor_enc; -defm V6_vgtuw_xor : - T_HVX_vcmp <"$dst ^= vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_xor_enc; - -defm V6_vminub : - T_HVX_alu_VV <"$dst.ub = vmin($src1.ub,$src2.ub)">, V6_vminub_enc; -defm V6_vminuh : - T_HVX_alu_VV <"$dst.uh = vmin($src1.uh,$src2.uh)">, V6_vminuh_enc; -defm V6_vminh : - T_HVX_alu_VV <"$dst.h = vmin($src1.h,$src2.h)">, V6_vminh_enc; -defm V6_vminw : - T_HVX_alu_VV <"$dst.w = vmin($src1.w,$src2.w)">, V6_vminw_enc; -defm V6_vmaxub : - T_HVX_alu_VV <"$dst.ub = vmax($src1.ub,$src2.ub)">, V6_vmaxub_enc; -defm V6_vmaxuh : - T_HVX_alu_VV <"$dst.uh = vmax($src1.uh,$src2.uh)">, V6_vmaxuh_enc; -defm V6_vmaxh : - T_HVX_alu_VV <"$dst.h = vmax($src1.h,$src2.h)">, V6_vmaxh_enc; -defm V6_vmaxw : - T_HVX_alu_VV <"$dst.w = vmax($src1.w,$src2.w)">, V6_vmaxw_enc; -defm V6_vshuffeb : - T_HVX_alu_VV <"$dst.b = vshuffe($src1.b,$src2.b)">, V6_vshuffeb_enc; -defm V6_vshuffob : - T_HVX_alu_VV <"$dst.b = vshuffo($src1.b,$src2.b)">, V6_vshuffob_enc; -defm V6_vshufeh : - T_HVX_alu_VV <"$dst.h = vshuffe($src1.h,$src2.h)">, V6_vshufeh_enc; -defm V6_vshufoh : - T_HVX_alu_VV <"$dst.h = vshuffo($src1.h,$src2.h)">, V6_vshufoh_enc; - -let Itinerary = CVI_VX_DV, Type = TypeCVI_VX_DV in { -defm V6_vmpyowh_rnd : - T_HVX_alu_VV <"$dst.w = vmpyo($src1.w,$src2.h):<<1:rnd:sat">, - V6_vmpyowh_rnd_enc; -defm V6_vmpyiewuh : - T_HVX_alu_VV <"$dst.w = vmpyie($src1.w,$src2.uh)">, V6_vmpyiewuh_enc; -defm V6_vmpyewuh : - T_HVX_alu_VV <"$dst.w = vmpye($src1.w,$src2.uh)">, V6_vmpyewuh_enc; -defm V6_vmpyowh : - T_HVX_alu_VV <"$dst.w = vmpyo($src1.w,$src2.h):<<1:sat">, V6_vmpyowh_enc; -defm V6_vmpyiowh : - T_HVX_alu_VV <"$dst.w = vmpyio($src1.w,$src2.h)">, V6_vmpyiowh_enc; -} -let Itinerary = CVI_VX, Type = TypeCVI_VX in -defm V6_vmpyieoh : - T_HVX_alu_VV <"$dst.w = vmpyieo($src1.h,$src2.h)">, V6_vmpyieoh_enc; - -let Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV in { -defm V6_vshufoeh : - T_HVX_alu_WV <"$dst.h = vshuffoe($src1.h,$src2.h)">, V6_vshufoeh_enc; -defm V6_vshufoeb : - T_HVX_alu_WV <"$dst.b = vshuffoe($src1.b,$src2.b)">, V6_vshufoeb_enc; -} - -let isRegSequence = 1, Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV in -defm V6_vcombine : - T_HVX_alu_WV <"$dst = vcombine($src1,$src2)">, V6_vcombine_enc; - -let Itinerary = CVI_VINLANESAT, Type = TypeCVI_VINLANESAT in { -defm V6_vsathub : - T_HVX_alu_VV <"$dst.ub = vsat($src1.h,$src2.h)">, V6_vsathub_enc; -defm V6_vsatwh : - T_HVX_alu_VV <"$dst.h = vsat($src1.w,$src2.w)">, V6_vsatwh_enc; -} - -let Itinerary = CVI_VS, Type = TypeCVI_VS in { -defm V6_vroundwh : - T_HVX_alu_VV <"$dst.h = vround($src1.w,$src2.w):sat">, V6_vroundwh_enc; -defm V6_vroundwuh : - T_HVX_alu_VV <"$dst.uh = vround($src1.w,$src2.w):sat">, V6_vroundwuh_enc; -defm V6_vroundhb : - T_HVX_alu_VV <"$dst.b = vround($src1.h,$src2.h):sat">, V6_vroundhb_enc; -defm V6_vroundhub : - T_HVX_alu_VV <"$dst.ub = vround($src1.h,$src2.h):sat">, V6_vroundhub_enc; -defm V6_vasrwv : - T_HVX_alu_VV <"$dst.w = vasr($src1.w,$src2.w)">, V6_vasrwv_enc; -defm V6_vlsrwv : - T_HVX_alu_VV <"$dst.w = vlsr($src1.w,$src2.w)">, V6_vlsrwv_enc; -defm V6_vlsrhv : - T_HVX_alu_VV <"$dst.h = vlsr($src1.h,$src2.h)">, V6_vlsrhv_enc; -defm V6_vasrhv : - T_HVX_alu_VV <"$dst.h = vasr($src1.h,$src2.h)">, V6_vasrhv_enc; -defm V6_vaslwv : - T_HVX_alu_VV <"$dst.w = vasl($src1.w,$src2.w)">, V6_vaslwv_enc; -defm V6_vaslhv : - T_HVX_alu_VV <"$dst.h = vasl($src1.h,$src2.h)">, V6_vaslhv_enc; -} - -defm V6_vaddb : - T_HVX_alu_VV <"$dst.b = vadd($src1.b,$src2.b)">, V6_vaddb_enc; -defm V6_vaddh : - T_HVX_alu_VV <"$dst.h = vadd($src1.h,$src2.h)">, V6_vaddh_enc; - -let Itinerary = CVI_VP, Type = TypeCVI_VP in { -defm V6_vdelta : - T_HVX_alu_VV <"$dst = vdelta($src1,$src2)">, V6_vdelta_enc; -defm V6_vrdelta : - T_HVX_alu_VV <"$dst = vrdelta($src1,$src2)">, V6_vrdelta_enc; -defm V6_vdealb4w : - T_HVX_alu_VV <"$dst.b = vdeale($src1.b,$src2.b)">, V6_vdealb4w_enc; -defm V6_vpackeb : - T_HVX_alu_VV <"$dst.b = vpacke($src1.h,$src2.h)">, V6_vpackeb_enc; -defm V6_vpackeh : - T_HVX_alu_VV <"$dst.h = vpacke($src1.w,$src2.w)">, V6_vpackeh_enc; -defm V6_vpackhub_sat : - T_HVX_alu_VV <"$dst.ub = vpack($src1.h,$src2.h):sat">, V6_vpackhub_sat_enc; -defm V6_vpackhb_sat : - T_HVX_alu_VV <"$dst.b = vpack($src1.h,$src2.h):sat">, V6_vpackhb_sat_enc; -defm V6_vpackwuh_sat : - T_HVX_alu_VV <"$dst.uh = vpack($src1.w,$src2.w):sat">, V6_vpackwuh_sat_enc; -defm V6_vpackwh_sat : - T_HVX_alu_VV <"$dst.h = vpack($src1.w,$src2.w):sat">, V6_vpackwh_sat_enc; -defm V6_vpackob : - T_HVX_alu_VV <"$dst.b = vpacko($src1.h,$src2.h)">, V6_vpackob_enc; -defm V6_vpackoh : - T_HVX_alu_VV <"$dst.h = vpacko($src1.w,$src2.w)">, V6_vpackoh_enc; -} - -let hasNewValue = 1, hasSideEffects = 0 in -class T_HVX_condALU <string asmString, RegisterClass RC1, RegisterClass RC2> - : CVI_VA_Resource1 <(outs RC2:$dst), - (ins RC1:$src1, RC2:$_src_, RC2:$src2), asmString, - [], "$dst = $_src_" > { - let Itinerary = CVI_VA; - let Type = TypeCVI_VA; -} - -multiclass T_HVX_condALU <string asmString> { - def NAME : T_HVX_condALU <asmString, VecPredRegs, VectorRegs>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_condALU <asmString, VecPredRegs128B, VectorRegs128B>; -} - -defm V6_vaddbq : T_HVX_condALU <"if ($src1) $dst.b += $src2.b">, - V6_vaddbq_enc; -defm V6_vaddhq : T_HVX_condALU <"if ($src1) $dst.h += $src2.h">, - V6_vaddhq_enc; -defm V6_vaddwq : T_HVX_condALU <"if ($src1) $dst.w += $src2.w">, - V6_vaddwq_enc; -defm V6_vsubbq : T_HVX_condALU <"if ($src1) $dst.b -= $src2.b">, - V6_vsubbq_enc; -defm V6_vsubhq : T_HVX_condALU <"if ($src1) $dst.h -= $src2.h">, - V6_vsubhq_enc; -defm V6_vsubwq : T_HVX_condALU <"if ($src1) $dst.w -= $src2.w">, - V6_vsubwq_enc; -defm V6_vaddbnq : T_HVX_condALU <"if (!$src1) $dst.b += $src2.b">, - V6_vaddbnq_enc; -defm V6_vaddhnq : T_HVX_condALU <"if (!$src1) $dst.h += $src2.h">, - V6_vaddhnq_enc; -defm V6_vaddwnq : T_HVX_condALU <"if (!$src1) $dst.w += $src2.w">, - V6_vaddwnq_enc; -defm V6_vsubbnq : T_HVX_condALU <"if (!$src1) $dst.b -= $src2.b">, - V6_vsubbnq_enc; -defm V6_vsubhnq : T_HVX_condALU <"if (!$src1) $dst.h -= $src2.h">, - V6_vsubhnq_enc; -defm V6_vsubwnq : T_HVX_condALU <"if (!$src1) $dst.w -= $src2.w">, - V6_vsubwnq_enc; - -let hasNewValue = 1 in -class T_HVX_alu_2op <string asmString, InstrItinClass itin, - RegisterClass RCout, RegisterClass RCin> - : CVI_VA_Resource1 <(outs RCout:$dst), (ins RCin:$src1), - asmString >{ - let Itinerary = itin; - let Type = !cast<IType>("Type"#itin); -} - -multiclass T_HVX_alu_2op <string asmString, RegisterClass RCout, - RegisterClass RCin, InstrItinClass itin> { - def NAME : T_HVX_alu_2op <asmString, itin, RCout, RCin>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_alu_2op <asmString, itin, - !cast<RegisterClass>(RCout#"128B"), - !cast<RegisterClass>(RCin#"128B")>; -} - -let hasNewValue = 1 in -multiclass T_HVX_alu_2op_VV <string asmString>: - T_HVX_alu_2op <asmString, VectorRegs, VectorRegs, CVI_VA>; - -multiclass T_HVX_alu_2op_WV <string asmString>: - T_HVX_alu_2op <asmString, VecDblRegs, VectorRegs, CVI_VA_DV>; - - -defm V6_vabsh : T_HVX_alu_2op_VV <"$dst.h = vabs($src1.h)">, - V6_vabsh_enc; -defm V6_vabsw : T_HVX_alu_2op_VV <"$dst.w = vabs($src1.w)">, - V6_vabsw_enc; -defm V6_vabsh_sat : T_HVX_alu_2op_VV <"$dst.h = vabs($src1.h):sat">, - V6_vabsh_sat_enc; -defm V6_vabsw_sat : T_HVX_alu_2op_VV <"$dst.w = vabs($src1.w):sat">, - V6_vabsw_sat_enc; -defm V6_vnot : T_HVX_alu_2op_VV <"$dst = vnot($src1)">, - V6_vnot_enc; -defm V6_vassign : T_HVX_alu_2op_VV <"$dst = $src1">, - V6_vassign_enc; - -defm V6_vzb : T_HVX_alu_2op_WV <"$dst.uh = vzxt($src1.ub)">, - V6_vzb_enc; -defm V6_vzh : T_HVX_alu_2op_WV <"$dst.uw = vzxt($src1.uh)">, - V6_vzh_enc; -defm V6_vsb : T_HVX_alu_2op_WV <"$dst.h = vsxt($src1.b)">, - V6_vsb_enc; -defm V6_vsh : T_HVX_alu_2op_WV <"$dst.w = vsxt($src1.h)">, - V6_vsh_enc; - -let Itinerary = CVI_VP, Type = TypeCVI_VP in { -defm V6_vdealh : T_HVX_alu_2op_VV <"$dst.h = vdeal($src1.h)">, - V6_vdealh_enc; -defm V6_vdealb : T_HVX_alu_2op_VV <"$dst.b = vdeal($src1.b)">, - V6_vdealb_enc; -defm V6_vshuffh : T_HVX_alu_2op_VV <"$dst.h = vshuff($src1.h)">, - V6_vshuffh_enc; -defm V6_vshuffb : T_HVX_alu_2op_VV <"$dst.b = vshuff($src1.b)">, - V6_vshuffb_enc; -} - -let Itinerary = CVI_VP_VS, Type = TypeCVI_VP_VS in { -defm V6_vunpackub : T_HVX_alu_2op_WV <"$dst.uh = vunpack($src1.ub)">, - V6_vunpackub_enc; -defm V6_vunpackuh : T_HVX_alu_2op_WV <"$dst.uw = vunpack($src1.uh)">, - V6_vunpackuh_enc; -defm V6_vunpackb : T_HVX_alu_2op_WV <"$dst.h = vunpack($src1.b)">, - V6_vunpackb_enc; -defm V6_vunpackh : T_HVX_alu_2op_WV <"$dst.w = vunpack($src1.h)">, - V6_vunpackh_enc; -} - -let Itinerary = CVI_VS, Type = TypeCVI_VS in { -defm V6_vcl0w : T_HVX_alu_2op_VV <"$dst.uw = vcl0($src1.uw)">, - V6_vcl0w_enc; -defm V6_vcl0h : T_HVX_alu_2op_VV <"$dst.uh = vcl0($src1.uh)">, - V6_vcl0h_enc; -defm V6_vnormamtw : T_HVX_alu_2op_VV <"$dst.w = vnormamt($src1.w)">, - V6_vnormamtw_enc; -defm V6_vnormamth : T_HVX_alu_2op_VV <"$dst.h = vnormamt($src1.h)">, - V6_vnormamth_enc; -defm V6_vpopcounth : T_HVX_alu_2op_VV <"$dst.h = vpopcount($src1.h)">, - V6_vpopcounth_enc; -} - -let isAccumulator = 1, hasNewValue = 1, Itinerary = CVI_VX_DV_LONG, - Type = TypeCVI_VX_DV in -class T_HVX_vmpyacc2 <string asmString, RegisterClass RC> - : CVI_VA_Resource1 <(outs RC:$dst), - (ins RC:$_src_, RC:$src1, IntRegs:$src2, u1_0Imm:$src3), - asmString, [], "$dst = $_src_" > ; - - -multiclass T_HVX_vmpyacc2 <string asmString> { - def NAME : T_HVX_vmpyacc2 <asmString, VecDblRegs>; - - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_vmpyacc2 <asmString, VecDblRegs128B>; -} - -defm V6_vrmpybusi_acc : - T_HVX_vmpyacc2<"$dst.w += vrmpy($src1.ub,$src2.b,#$src3)">, - V6_vrmpybusi_acc_enc; -defm V6_vrsadubi_acc : - T_HVX_vmpyacc2<"$dst.uw += vrsad($src1.ub,$src2.ub,#$src3)">, - V6_vrsadubi_acc_enc; -defm V6_vrmpyubi_acc : - T_HVX_vmpyacc2<"$dst.uw += vrmpy($src1.ub,$src2.ub,#$src3)">, - V6_vrmpyubi_acc_enc; - - -let Itinerary = CVI_VX_DV_LONG, Type = TypeCVI_VX_DV, hasNewValue = 1 in -class T_HVX_vmpy2 <string asmString, RegisterClass RC> - : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, IntRegs:$src2, u1_0Imm:$src3), - asmString>; - - -multiclass T_HVX_vmpy2 <string asmString> { - def NAME : T_HVX_vmpy2 <asmString, VecDblRegs>; - - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_vmpy2 <asmString, VecDblRegs128B>; -} - -defm V6_vrmpybusi : - T_HVX_vmpy2 <"$dst.w = vrmpy($src1.ub,$src2.b,#$src3)">, V6_vrmpybusi_enc; -defm V6_vrsadubi : - T_HVX_vmpy2 <"$dst.uw = vrsad($src1.ub,$src2.ub,#$src3)">, V6_vrsadubi_enc; -defm V6_vrmpyubi : - T_HVX_vmpy2 <"$dst.uw = vrmpy($src1.ub,$src2.ub,#$src3)">, V6_vrmpyubi_enc; - - -let Itinerary = CVI_VP_VS_LONG_EARLY, Type = TypeCVI_VP_VS, - hasSideEffects = 0, hasNewValue2 = 1, opNewValue2 = 1 in -class T_HVX_perm <string asmString, RegisterClass RC> - : CVI_VA_Resource1 <(outs RC:$_dst1_, RC:$_dst2_), - (ins RC:$src1, RC:$src2, IntRegs:$src3), - asmString, [], "$_dst1_ = $src1, $_dst2_ = $src2" >; - -multiclass T_HVX_perm <string asmString> { - def NAME : T_HVX_perm <asmString, VectorRegs>; - - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_perm <asmString, VectorRegs128B>; -} - -let hasNewValue = 1, opNewValue = 0, hasNewValue2 = 1, opNewValue2 = 1 in { - defm V6_vshuff : T_HVX_perm <"vshuff($src1,$src2,$src3)">, V6_vshuff_enc; - defm V6_vdeal : T_HVX_perm <"vdeal($src1,$src2,$src3)">, V6_vdeal_enc; -} - -// Conditional vector move. -let isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -class T_HVX_cmov <bit isPredNot, RegisterClass RC> - : CVI_VA_Resource1 <(outs RC:$dst), (ins PredRegs:$src1, RC:$src2), - "if ("#!if(isPredNot, "!", "")#"$src1) $dst = $src2"> { - let isPredicatedFalse = isPredNot; -} - -multiclass T_HVX_cmov <bit isPredNot = 0> { - def NAME : T_HVX_cmov <isPredNot, VectorRegs>; - - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_cmov <isPredNot, VectorRegs128B>; -} - -defm V6_vcmov : T_HVX_cmov, V6_vcmov_enc; -defm V6_vncmov : T_HVX_cmov<1>, V6_vncmov_enc; - -// Conditional vector combine. -let Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV, isPredicated = 1, - hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -class T_HVX_ccombine <bit isPredNot, RegisterClass RCout, RegisterClass RCin> - : CVI_VA_Resource1 < (outs RCout:$dst), - (ins PredRegs:$src1, RCin:$src2, RCin:$src3), - "if ("#!if(isPredNot, "!", "")#"$src1) $dst = vcombine($src2,$src3)"> { - let isPredicatedFalse = isPredNot; -} - -multiclass T_HVX_ccombine <bit isPredNot = 0> { - def NAME : T_HVX_ccombine <isPredNot, VecDblRegs, VectorRegs>; - - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_ccombine <isPredNot, VecDblRegs128B, VectorRegs128B>; -} - -defm V6_vccombine : T_HVX_ccombine, V6_vccombine_enc; -defm V6_vnccombine : T_HVX_ccombine<1>, V6_vnccombine_enc; - -let hasNewValue = 1 in -class T_HVX_shift <string asmString, RegisterClass RCout, RegisterClass RCin> - : CVI_VX_DV_Resource1<(outs RCout:$dst), - (ins RCin:$src1, RCin:$src2, IntRegsLow8:$src3), - asmString >; - -multiclass T_HVX_shift <string asmString, RegisterClass RCout, - RegisterClass RCin> { - def NAME : T_HVX_shift <asmString, RCout, RCin>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_shift <asmString, !cast<RegisterClass>(RCout#"128B"), - !cast<RegisterClass>(RCin#"128B")>; -} - -multiclass T_HVX_shift_VV <string asmString>: - T_HVX_shift <asmString, VectorRegs, VectorRegs>; - -multiclass T_HVX_shift_WV <string asmString>: - T_HVX_shift <asmString, VecDblRegs, VectorRegs>; - -let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP in { -defm V6_valignb : - T_HVX_shift_VV <"$dst = valign($src1,$src2,$src3)">, V6_valignb_enc; -defm V6_vlalignb : - T_HVX_shift_VV <"$dst = vlalign($src1,$src2,$src3)">, V6_vlalignb_enc; -} - -let Itinerary = CVI_VS, Type = TypeCVI_VS in { -defm V6_vasrwh : - T_HVX_shift_VV <"$dst.h = vasr($src1.w,$src2.w,$src3)">, V6_vasrwh_enc; -defm V6_vasrwhsat : - T_HVX_shift_VV <"$dst.h = vasr($src1.w,$src2.w,$src3):sat">, - V6_vasrwhsat_enc; -defm V6_vasrwhrndsat : - T_HVX_shift_VV <"$dst.h = vasr($src1.w,$src2.w,$src3):rnd:sat">, - V6_vasrwhrndsat_enc; -defm V6_vasrwuhsat : - T_HVX_shift_VV <"$dst.uh = vasr($src1.w,$src2.w,$src3):sat">, - V6_vasrwuhsat_enc; -defm V6_vasrhubsat : - T_HVX_shift_VV <"$dst.ub = vasr($src1.h,$src2.h,$src3):sat">, - V6_vasrhubsat_enc; -defm V6_vasrhubrndsat : - T_HVX_shift_VV <"$dst.ub = vasr($src1.h,$src2.h,$src3):rnd:sat">, - V6_vasrhubrndsat_enc; -defm V6_vasrhbrndsat : - T_HVX_shift_VV <"$dst.b = vasr($src1.h,$src2.h,$src3):rnd:sat">, - V6_vasrhbrndsat_enc; -} - -// Assembler mapped -- alias? -//defm V6_vtran2x2vdd : T_HVX_shift_VV <"">, V6_vtran2x2vdd_enc; -let Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS in { -defm V6_vshuffvdd : - T_HVX_shift_WV <"$dst = vshuff($src1,$src2,$src3)">, V6_vshuffvdd_enc; -defm V6_vdealvdd : - T_HVX_shift_WV <"$dst = vdeal($src1,$src2,$src3)">, V6_vdealvdd_enc; -} - -let hasNewValue = 1, Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS in -class T_HVX_unpack <string asmString, RegisterClass RCout, RegisterClass RCin> - : CVI_VX_DV_Resource1<(outs RCout:$dst), (ins RCout:$_src_, RCin:$src1), - asmString, [], "$dst = $_src_">; - -multiclass T_HVX_unpack <string asmString> { - def NAME : T_HVX_unpack <asmString, VecDblRegs, VectorRegs>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_unpack <asmString, VecDblRegs128B, VectorRegs128B>; -} - -defm V6_vunpackob : T_HVX_unpack <"$dst.h |= vunpacko($src1.b)">, V6_vunpackob_enc; -defm V6_vunpackoh : T_HVX_unpack <"$dst.w |= vunpacko($src1.h)">, V6_vunpackoh_enc; - -let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP, hasNewValue = 1, - hasSideEffects = 0 in -class T_HVX_valign <string asmString, RegisterClass RC> - : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, RC:$src2, u3_0Imm:$src3), - asmString>; - -multiclass T_HVX_valign <string asmString> { - def NAME : T_HVX_valign <asmString, VectorRegs>; - - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_valign <asmString, VectorRegs128B>; -} - -defm V6_valignbi : - T_HVX_valign <"$dst = valign($src1,$src2,#$src3)">, V6_valignbi_enc; -defm V6_vlalignbi : - T_HVX_valign <"$dst = vlalign($src1,$src2,#$src3)">, V6_vlalignbi_enc; - -let Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV in -class T_HVX_predAlu <string asmString, RegisterClass RC> - : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, RC:$src2), - asmString>; - -multiclass T_HVX_predAlu <string asmString> { - def NAME : T_HVX_predAlu <asmString, VecPredRegs>; - - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_predAlu <asmString, VecPredRegs128B>; -} - -defm V6_pred_and : T_HVX_predAlu <"$dst = and($src1,$src2)">, V6_pred_and_enc; -defm V6_pred_or : T_HVX_predAlu <"$dst = or($src1,$src2)">, V6_pred_or_enc; -defm V6_pred_xor : T_HVX_predAlu <"$dst = xor($src1,$src2)">, V6_pred_xor_enc; -defm V6_pred_or_n : T_HVX_predAlu <"$dst = or($src1,!$src2)">, V6_pred_or_n_enc; -defm V6_pred_and_n : - T_HVX_predAlu <"$dst = and($src1,!$src2)">, V6_pred_and_n_enc; - -let Itinerary = CVI_VA, Type = TypeCVI_VA in -class T_HVX_prednot <RegisterClass RC> - : CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1), - "$dst = not($src1)">, V6_pred_not_enc; - -def V6_pred_not : T_HVX_prednot <VecPredRegs>; -let isCodeGenOnly = 1 in -def V6_pred_not_128B : T_HVX_prednot <VecPredRegs128B>; - -let Itinerary = CVI_VA, Type = TypeCVI_VA in -class T_HVX_vcmp2 <string asmString, RegisterClass RCout, RegisterClass RCin> - : CVI_VA_Resource1 <(outs RCout:$dst), (ins RCin:$src1, RCin:$src2), - asmString >; - -multiclass T_HVX_vcmp2 <string asmString> { - def NAME : T_HVX_vcmp2 <asmString, VecPredRegs, VectorRegs>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_vcmp2 <asmString, VecPredRegs128B, VectorRegs128B>; -} - -defm V6_veqb : T_HVX_vcmp2 <"$dst = vcmp.eq($src1.b,$src2.b)">, V6_veqb_enc; -defm V6_veqh : T_HVX_vcmp2 <"$dst = vcmp.eq($src1.h,$src2.h)">, V6_veqh_enc; -defm V6_veqw : T_HVX_vcmp2 <"$dst = vcmp.eq($src1.w,$src2.w)">, V6_veqw_enc; -defm V6_vgtb : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.b,$src2.b)">, V6_vgtb_enc; -defm V6_vgth : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.h,$src2.h)">, V6_vgth_enc; -defm V6_vgtw : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.w,$src2.w)">, V6_vgtw_enc; -defm V6_vgtub : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.ub,$src2.ub)">, V6_vgtub_enc; -defm V6_vgtuh : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.uh,$src2.uh)">, V6_vgtuh_enc; -defm V6_vgtuw : T_HVX_vcmp2 <"$dst = vcmp.gt($src1.uw,$src2.uw)">, V6_vgtuw_enc; - -let isAccumulator = 1, hasNewValue = 1, hasSideEffects = 0 in -class T_V6_vandqrt_acc <RegisterClass RCout, RegisterClass RCin> - : CVI_VX_Resource_late<(outs RCout:$dst), - (ins RCout:$_src_, RCin:$src1, IntRegs:$src2), - "$dst |= vand($src1,$src2)", [], "$dst = $_src_">, V6_vandqrt_acc_enc; - -def V6_vandqrt_acc : T_V6_vandqrt_acc <VectorRegs, VecPredRegs>; -let isCodeGenOnly = 1 in -def V6_vandqrt_acc_128B : T_V6_vandqrt_acc <VectorRegs128B, VecPredRegs128B>; - -let isAccumulator = 1 in -class T_V6_vandvrt_acc <RegisterClass RCout, RegisterClass RCin> - : CVI_VX_Resource_late<(outs RCout:$dst), - (ins RCout:$_src_, RCin:$src1, IntRegs:$src2), - "$dst |= vand($src1,$src2)", [], "$dst = $_src_">, V6_vandvrt_acc_enc; - -def V6_vandvrt_acc : T_V6_vandvrt_acc <VecPredRegs, VectorRegs>; -let isCodeGenOnly = 1 in -def V6_vandvrt_acc_128B : T_V6_vandvrt_acc <VecPredRegs128B, VectorRegs128B>; - -let hasNewValue = 1, hasSideEffects = 0 in -class T_V6_vandqrt <RegisterClass RCout, RegisterClass RCin> - : CVI_VX_Resource_late<(outs RCout:$dst), - (ins RCin:$src1, IntRegs:$src2), - "$dst = vand($src1,$src2)" >, V6_vandqrt_enc; - -def V6_vandqrt : T_V6_vandqrt <VectorRegs, VecPredRegs>; -let isCodeGenOnly = 1 in -def V6_vandqrt_128B : T_V6_vandqrt <VectorRegs128B, VecPredRegs128B>; - -let hasNewValue = 1, hasSideEffects = 0 in -class T_V6_lvsplatw <RegisterClass RC> - : CVI_VX_Resource_late<(outs RC:$dst), (ins IntRegs:$src1), - "$dst = vsplat($src1)" >, V6_lvsplatw_enc; - -def V6_lvsplatw : T_V6_lvsplatw <VectorRegs>; -let isCodeGenOnly = 1 in -def V6_lvsplatw_128B : T_V6_lvsplatw <VectorRegs128B>; - - -let hasNewValue = 1 in -class T_V6_vinsertwr <RegisterClass RC> - : CVI_VX_Resource_late<(outs RC:$dst), (ins RC:$_src_, IntRegs:$src1), - "$dst.w = vinsert($src1)", [], "$dst = $_src_">, - V6_vinsertwr_enc; - -def V6_vinsertwr : T_V6_vinsertwr <VectorRegs>; -let isCodeGenOnly = 1 in -def V6_vinsertwr_128B : T_V6_vinsertwr <VectorRegs128B>; - - -let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP in -class T_V6_pred_scalar2 <RegisterClass RC> - : CVI_VA_Resource1<(outs RC:$dst), (ins IntRegs:$src1), - "$dst = vsetq($src1)">, V6_pred_scalar2_enc; - -def V6_pred_scalar2 : T_V6_pred_scalar2 <VecPredRegs>; -let isCodeGenOnly = 1 in -def V6_pred_scalar2_128B : T_V6_pred_scalar2 <VecPredRegs128B>; - -class T_V6_vandvrt <RegisterClass RCout, RegisterClass RCin> - : CVI_VX_Resource_late<(outs RCout:$dst), (ins RCin:$src1, IntRegs:$src2), - "$dst = vand($src1,$src2)">, V6_vandvrt_enc; - -def V6_vandvrt : T_V6_vandvrt <VecPredRegs, VectorRegs>; -let isCodeGenOnly = 1 in -def V6_vandvrt_128B : T_V6_vandvrt <VecPredRegs128B, VectorRegs128B>; - -let validSubTargets = HasV60SubT in -class T_HVX_rol <string asmString, RegisterClass RC, Operand ImmOp > - : SInst2 <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2), asmString>; - -class T_HVX_rol_R <string asmString> - : T_HVX_rol <asmString, IntRegs, u5_0Imm>; -class T_HVX_rol_P <string asmString> - : T_HVX_rol <asmString, DoubleRegs, u6_0Imm>; - -def S6_rol_i_p : T_HVX_rol_P <"$dst = rol($src1,#$src2)">, S6_rol_i_p_enc; -let hasNewValue = 1, opNewValue = 0 in -def S6_rol_i_r : T_HVX_rol_R <"$dst = rol($src1,#$src2)">, S6_rol_i_r_enc; - -let validSubTargets = HasV60SubT in -class T_HVX_rol_acc <string asmString, RegisterClass RC, Operand ImmOp> - : SInst2 <(outs RC:$dst), (ins RC:$_src_, RC:$src1, ImmOp:$src2), - asmString, [], "$dst = $_src_" >; - -class T_HVX_rol_acc_P <string asmString> - : T_HVX_rol_acc <asmString, DoubleRegs, u6_0Imm>; - -class T_HVX_rol_acc_R <string asmString> - : T_HVX_rol_acc <asmString, IntRegs, u5_0Imm>; - -def S6_rol_i_p_nac : - T_HVX_rol_acc_P <"$dst -= rol($src1,#$src2)">, S6_rol_i_p_nac_enc; -def S6_rol_i_p_acc : - T_HVX_rol_acc_P <"$dst += rol($src1,#$src2)">, S6_rol_i_p_acc_enc; -def S6_rol_i_p_and : - T_HVX_rol_acc_P <"$dst &= rol($src1,#$src2)">, S6_rol_i_p_and_enc; -def S6_rol_i_p_or : - T_HVX_rol_acc_P <"$dst |= rol($src1,#$src2)">, S6_rol_i_p_or_enc; -def S6_rol_i_p_xacc : - T_HVX_rol_acc_P<"$dst ^= rol($src1,#$src2)">, S6_rol_i_p_xacc_enc; - -let hasNewValue = 1, opNewValue = 0 in { -def S6_rol_i_r_nac : - T_HVX_rol_acc_R <"$dst -= rol($src1,#$src2)">, S6_rol_i_r_nac_enc; -def S6_rol_i_r_acc : - T_HVX_rol_acc_R <"$dst += rol($src1,#$src2)">, S6_rol_i_r_acc_enc; -def S6_rol_i_r_and : - T_HVX_rol_acc_R <"$dst &= rol($src1,#$src2)">, S6_rol_i_r_and_enc; -def S6_rol_i_r_or : - T_HVX_rol_acc_R <"$dst |= rol($src1,#$src2)">, S6_rol_i_r_or_enc; -def S6_rol_i_r_xacc : - T_HVX_rol_acc_R <"$dst ^= rol($src1,#$src2)">, S6_rol_i_r_xacc_enc; -} - -let isSolo = 1, Itinerary = LD_tc_ld_SLOT0, Type = TypeLD in -class T_V6_extractw <RegisterClass RC> - : LD1Inst <(outs IntRegs:$dst), (ins RC:$src1, IntRegs:$src2), - "$dst = vextract($src1,$src2)">, V6_extractw_enc; - -def V6_extractw : T_V6_extractw <VectorRegs>; -let isCodeGenOnly = 1 in -def V6_extractw_128B : T_V6_extractw <VectorRegs128B>; - -let Itinerary = ST_tc_st_SLOT0, validSubTargets = HasV55SubT in -class T_sys0op <string asmString> - : ST1Inst <(outs), (ins), asmString>; - -let isSolo = 1, validSubTargets = HasV55SubT in { -def Y5_l2gunlock : T_sys0op <"l2gunlock">, Y5_l2gunlock_enc; -def Y5_l2gclean : T_sys0op <"l2gclean">, Y5_l2gclean_enc; -def Y5_l2gcleaninv : T_sys0op <"l2gcleaninv">, Y5_l2gcleaninv_enc; -} - -class T_sys1op <string asmString, RegisterClass RC> - : ST1Inst <(outs), (ins RC:$src1), asmString>; - -class T_sys1op_R <string asmString> : T_sys1op <asmString, IntRegs>; -class T_sys1op_P <string asmString> : T_sys1op <asmString, DoubleRegs>; - -let isSoloAX = 1, validSubTargets = HasV55SubT in -def Y5_l2unlocka : T_sys1op_R <"l2unlocka($src1)">, Y5_l2unlocka_enc; - -let isSolo = 1, validSubTargets = HasV60SubT in { -def Y6_l2gcleanpa : T_sys1op_P <"l2gclean($src1)">, Y6_l2gcleanpa_enc; -def Y6_l2gcleaninvpa : T_sys1op_P <"l2gcleaninv($src1)">, Y6_l2gcleaninvpa_enc; -} - -let Itinerary = ST_tc_3stall_SLOT0, isPredicateLate = 1, isSoloAX = 1, - validSubTargets = HasV55SubT in -def Y5_l2locka : ST1Inst <(outs PredRegs:$dst), (ins IntRegs:$src1), - "$dst = l2locka($src1)">, Y5_l2locka_enc; - -// not defined on etc side. why? -// defm S2_cabacencbin : _VV <"Rdd=encbin(Rss,$src2,Pu)">, S2_cabacencbin_enc; - -let Defs = [USR_OVF], Itinerary = M_tc_3stall_SLOT23, isPredicateLate = 1, - hasSideEffects = 0, -validSubTargets = HasV55SubT in -def A5_ACS : MInst2 <(outs DoubleRegs:$dst1, PredRegs:$dst2), - (ins DoubleRegs:$_src_, DoubleRegs:$src1, DoubleRegs:$src2), - "$dst1,$dst2 = vacsh($src1,$src2)", [], - "$dst1 = $_src_" >, Requires<[HasV55T]>, A5_ACS_enc; - -let Itinerary = CVI_VA_DV, Type = TypeCVI_VA_DV, hasNewValue = 1, - hasSideEffects = 0 in -class T_HVX_alu2 <string asmString, RegisterClass RCout, RegisterClass RCin1, - RegisterClass RCin2> - : CVI_VA_Resource1<(outs RCout:$dst), - (ins RCin1:$src1, RCin2:$src2, RCin2:$src3), asmString>; - -multiclass T_HVX_alu2 <string asmString, RegisterClass RC > { - def NAME : T_HVX_alu2 <asmString, RC, VecPredRegs, VectorRegs>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_alu2 <asmString, !cast<RegisterClass>(RC#"128B"), - VecPredRegs128B, VectorRegs128B>; -} - -multiclass T_HVX_alu2_V <string asmString> : - T_HVX_alu2 <asmString, VectorRegs>; - -multiclass T_HVX_alu2_W <string asmString> : - T_HVX_alu2 <asmString, VecDblRegs>; - -defm V6_vswap : T_HVX_alu2_W <"$dst = vswap($src1,$src2,$src3)">, V6_vswap_enc; - -let Itinerary = CVI_VA, Type = TypeCVI_VA, hasNewValue = 1, - hasSideEffects = 0 in -defm V6_vmux : T_HVX_alu2_V <"$dst = vmux($src1,$src2,$src3)">, V6_vmux_enc; - -class T_HVX_vlutb <string asmString, RegisterClass RCout, RegisterClass RCin> - : CVI_VA_Resource1<(outs RCout:$dst), - (ins RCin:$src1, RCin:$src2, IntRegsLow8:$src3), asmString>; - -multiclass T_HVX_vlutb <string asmString, RegisterClass RCout, - RegisterClass RCin> { - def NAME : T_HVX_vlutb <asmString, RCout, RCin>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_vlutb <asmString, !cast<RegisterClass>(RCout#"128B"), - !cast<RegisterClass>(RCin#"128B")>; -} - -multiclass T_HVX_vlutb_V <string asmString> : - T_HVX_vlutb <asmString, VectorRegs, VectorRegs>; - -multiclass T_HVX_vlutb_W <string asmString> : - T_HVX_vlutb <asmString, VecDblRegs, VectorRegs>; - -let Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS, isAccumulator = 1 in -class T_HVX_vlutb_acc <string asmString, RegisterClass RCout, - RegisterClass RCin> - : CVI_VA_Resource1<(outs RCout:$dst), - (ins RCout:$_src_, RCin:$src1, RCin:$src2, IntRegsLow8:$src3), - asmString, [], "$dst = $_src_">; - -multiclass T_HVX_vlutb_acc <string asmString, RegisterClass RCout, - RegisterClass RCin> { - def NAME : T_HVX_vlutb_acc <asmString, RCout, RCin>; - let isCodeGenOnly = 1 in - def NAME#_128B : T_HVX_vlutb_acc<asmString, - !cast<RegisterClass>(RCout#"128B"), - !cast<RegisterClass>(RCin#"128B")>; -} - -multiclass T_HVX_vlutb_acc_V <string asmString> : - T_HVX_vlutb_acc <asmString, VectorRegs, VectorRegs>; - -multiclass T_HVX_vlutb_acc_W <string asmString> : - T_HVX_vlutb_acc <asmString, VecDblRegs, VectorRegs>; - - -let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP, hasNewValue = 1 in -defm V6_vlutvvb: - T_HVX_vlutb_V <"$dst.b = vlut32($src1.b,$src2.b,$src3)">, V6_vlutvvb_enc; - -let Itinerary = CVI_VP_VS_LONG, Type = TypeCVI_VP_VS, hasNewValue = 1 in -defm V6_vlutvwh: - T_HVX_vlutb_W <"$dst.h = vlut16($src1.b,$src2.h,$src3)">, V6_vlutvwh_enc; - -let hasNewValue = 1 in { - defm V6_vlutvvb_oracc: - T_HVX_vlutb_acc_V <"$dst.b |= vlut32($src1.b,$src2.b,$src3)">, - V6_vlutvvb_oracc_enc; - defm V6_vlutvwh_oracc: - T_HVX_vlutb_acc_W <"$dst.h |= vlut16($src1.b,$src2.h,$src3)">, - V6_vlutvwh_oracc_enc; -} - -// It's a fake instruction and should not be defined? -def S2_cabacencbin - : SInst2<(outs DoubleRegs:$dst), - (ins DoubleRegs:$src1, DoubleRegs:$src2, PredRegs:$src3), - "$dst = encbin($src1,$src2,$src3)">, S2_cabacencbin_enc; - -// Vhist instructions -def V6_vhistq - : CVI_HIST_Resource1 <(outs), (ins VecPredRegs:$src1), - "vhist($src1)">, V6_vhistq_enc; - -def V6_vhist - : CVI_HIST_Resource1 <(outs), (ins), - "vhist" >, V6_vhist_enc; - - -let isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in { - def V6_vd0: CVI_VA_Resource<(outs VectorRegs:$dst), (ins), "$dst = #0", []>; - def V6_vd0_128B: CVI_VA_Resource<(outs VectorRegs128B:$dst), (ins), - "$dst = #0", []>; - - def V6_vassignp: CVI_VA_Resource<(outs VecDblRegs:$dst), - (ins VecDblRegs:$src), "", []>; - def V6_vassignp_128B : CVI_VA_Resource<(outs VecDblRegs128B:$dst), - (ins VecDblRegs128B:$src), "", []>; - - def V6_lo: CVI_VA_Resource<(outs VectorRegs:$dst), (ins VecDblRegs:$src1), - "", []>; - def V6_lo_128B: CVI_VA_Resource<(outs VectorRegs128B:$dst), - (ins VecDblRegs128B:$src1), "", []>; - - def V6_hi: CVI_VA_Resource<(outs VectorRegs:$dst), (ins VecDblRegs:$src1), - "", []>; - def V6_hi_128B: CVI_VA_Resource<(outs VectorRegs128B:$dst), - (ins VecDblRegs128B:$src1), "", []>; -} diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfoVector.td b/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfoVector.td deleted file mode 100644 index e3520bd6e515..000000000000 --- a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfoVector.td +++ /dev/null @@ -1,69 +0,0 @@ -//===- HexagonInstrInfoVector.td - Hexagon Vector Patterns -*- tablegen -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon Vector instructions in TableGen format. -// -//===----------------------------------------------------------------------===// - -// Vector shift support. Vector shifting in Hexagon is rather different -// from internal representation of LLVM. -// LLVM assumes all shifts (in vector case) will have the form -// <VT> = SHL/SRA/SRL <VT> by <VT> -// while Hexagon has the following format: -// <VT> = SHL/SRA/SRL <VT> by <IT/i32> -// As a result, special care is needed to guarantee correctness and -// performance. -class vshift_v4i16<SDNode Op, string Str, bits<3>MajOp, bits<3>MinOp> - : S_2OpInstImm<Str, MajOp, MinOp, u4_0Imm, []> { - bits<4> src2; - let Inst{11-8} = src2; -} - -class vshift_v2i32<SDNode Op, string Str, bits<3>MajOp, bits<3>MinOp> - : S_2OpInstImm<Str, MajOp, MinOp, u5_0Imm, []> { - bits<5> src2; - let Inst{12-8} = src2; -} - -def S2_asr_i_vw : vshift_v2i32<sra, "vasrw", 0b010, 0b000>; -def S2_lsr_i_vw : vshift_v2i32<srl, "vlsrw", 0b010, 0b001>; -def S2_asl_i_vw : vshift_v2i32<shl, "vaslw", 0b010, 0b010>; - -def S2_asr_i_vh : vshift_v4i16<sra, "vasrh", 0b100, 0b000>; -def S2_lsr_i_vh : vshift_v4i16<srl, "vlsrh", 0b100, 0b001>; -def S2_asl_i_vh : vshift_v4i16<shl, "vaslh", 0b100, 0b010>; - -// Vector shift words by register -def S2_asr_r_vw : T_S3op_shiftVect < "vasrw", 0b00, 0b00>; -def S2_lsr_r_vw : T_S3op_shiftVect < "vlsrw", 0b00, 0b01>; -def S2_asl_r_vw : T_S3op_shiftVect < "vaslw", 0b00, 0b10>; -def S2_lsl_r_vw : T_S3op_shiftVect < "vlslw", 0b00, 0b11>; - -// Vector shift halfwords by register -def S2_asr_r_vh : T_S3op_shiftVect < "vasrh", 0b01, 0b00>; -def S2_lsr_r_vh : T_S3op_shiftVect < "vlsrh", 0b01, 0b01>; -def S2_asl_r_vh : T_S3op_shiftVect < "vaslh", 0b01, 0b10>; -def S2_lsl_r_vh : T_S3op_shiftVect < "vlslh", 0b01, 0b11>; - - -// Hexagon doesn't have a vector multiply with C semantics. -// Instead, generate a pseudo instruction that gets expaneded into two -// scalar MPYI instructions. -// This is expanded by ExpandPostRAPseudos. -let isPseudo = 1 in -def PS_vmulw : PseudoM<(outs DoubleRegs:$Rd), - (ins DoubleRegs:$Rs, DoubleRegs:$Rt), "", []>; - -let isPseudo = 1 in -def PS_vmulw_acc : PseudoM<(outs DoubleRegs:$Rd), - (ins DoubleRegs:$Rx, DoubleRegs:$Rs, DoubleRegs:$Rt), "", [], - "$Rd = $Rx">; - - - diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonIntrinsics.td b/contrib/llvm/lib/Target/Hexagon/HexagonIntrinsics.td index d4f303bf6ff0..c611857ec26a 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonIntrinsics.td +++ b/contrib/llvm/lib/Target/Hexagon/HexagonIntrinsics.td @@ -1347,6 +1347,25 @@ def: T_stc_pat<S2_storeri_pci, int_hexagon_circ_stw, s4_2ImmPred, I32>; def: T_stc_pat<S2_storerd_pci, int_hexagon_circ_std, s4_3ImmPred, I64>; def: T_stc_pat<S2_storerf_pci, int_hexagon_circ_sthhi, s4_1ImmPred, I32>; +multiclass MaskedStore <InstHexagon MI, Intrinsic IntID> { + def : Pat<(IntID VecPredRegs:$src1, IntRegs:$src2, VectorRegs:$src3), + (MI VecPredRegs:$src1, IntRegs:$src2, #0, VectorRegs:$src3)>, + Requires<[UseHVXSgl]>; + + def : Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, + IntRegs:$src2, + VectorRegs128B:$src3), + (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, + IntRegs:$src2, #0, + VectorRegs128B:$src3)>, + Requires<[UseHVXDbl]>; +} + +defm : MaskedStore <V6_vS32b_qpred_ai, int_hexagon_V6_vmaskedstoreq>; +defm : MaskedStore <V6_vS32b_nqpred_ai, int_hexagon_V6_vmaskedstorenq>; +defm : MaskedStore <V6_vS32b_nt_qpred_ai, int_hexagon_V6_vmaskedstorentq>; +defm : MaskedStore <V6_vS32b_nt_nqpred_ai, int_hexagon_V6_vmaskedstorentnq>; + include "HexagonIntrinsicsV3.td" include "HexagonIntrinsicsV4.td" include "HexagonIntrinsicsV5.td" diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonIntrinsicsV60.td b/contrib/llvm/lib/Target/Hexagon/HexagonIntrinsicsV60.td index a45e1c9d7be4..f438b3e0368f 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonIntrinsicsV60.td +++ b/contrib/llvm/lib/Target/Hexagon/HexagonIntrinsicsV60.td @@ -790,7 +790,7 @@ def : T_RRI_pat <S6_rol_i_r_xacc, int_hexagon_S6_rol_i_r_xacc>; defm : T_VR_pat <V6_extractw, int_hexagon_V6_extractw>; defm : T_VR_pat <V6_vinsertwr, int_hexagon_V6_vinsertwr>; -def : T_PPQ_pat <S2_cabacencbin, int_hexagon_S2_cabacencbin>; +//def : T_PPQ_pat <S2_cabacencbin, int_hexagon_S2_cabacencbin>; def: Pat<(v64i16 (trunc v64i32:$Vdd)), (v64i16 (V6_vpackwh_sat_128B diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonIsetDx.td b/contrib/llvm/lib/Target/Hexagon/HexagonIsetDx.td deleted file mode 100644 index ebedf2cbaf17..000000000000 --- a/contrib/llvm/lib/Target/Hexagon/HexagonIsetDx.td +++ /dev/null @@ -1,728 +0,0 @@ -//=- HexagonIsetDx.td - Target Desc. for Hexagon Target -*- tablegen -*-=// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon duplex instructions. -// -//===----------------------------------------------------------------------===// - -// SA1_combine1i: Combines. -let isCodeGenOnly = 1, hasSideEffects = 0 in -def SA1_combine1i: SUBInst < - (outs DoubleRegs:$Rdd), - (ins u2_0Imm:$u2), - "$Rdd = combine(#1, #$u2)"> { - bits<3> Rdd; - bits<2> u2; - - let Inst{12-10} = 0b111; - let Inst{8} = 0b0; - let Inst{4-3} = 0b01; - let Inst{2-0} = Rdd; - let Inst{6-5} = u2; - } - -// SL2_jumpr31_f: Indirect conditional jump if false. -// SL2_jumpr31_f -> SL2_jumpr31_fnew -let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in -def SL2_jumpr31_f: SUBInst < - (outs ), - (ins ), - "if (!p0) jumpr r31"> { - let Inst{12-6} = 0b1111111; - let Inst{2-0} = 0b101; - } - -// SL2_deallocframe: Deallocate stack frame. -let Defs = [R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess in -def SL2_deallocframe: SUBInst < - (outs ), - (ins ), - "deallocframe"> { - let Inst{12-6} = 0b1111100; - let Inst{2} = 0b0; - } - -// SL2_return_f: Deallocate stack frame and return. -// SL2_return_f -> SL2_return_fnew -let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in -def SL2_return_f: SUBInst < - (outs ), - (ins ), - "if (!p0) dealloc_return"> { - let Inst{12-6} = 0b1111101; - let Inst{2-0} = 0b101; - } - -// SA1_combine3i: Combines. -let isCodeGenOnly = 1, hasSideEffects = 0 in -def SA1_combine3i: SUBInst < - (outs DoubleRegs:$Rdd), - (ins u2_0Imm:$u2), - "$Rdd = combine(#3, #$u2)"> { - bits<3> Rdd; - bits<2> u2; - - let Inst{12-10} = 0b111; - let Inst{8} = 0b0; - let Inst{4-3} = 0b11; - let Inst{2-0} = Rdd; - let Inst{6-5} = u2; - } - -// SS2_storebi0: Store byte. -let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in -def SS2_storebi0: SUBInst < - (outs ), - (ins IntRegs:$Rs, u4_0Imm:$u4_0), - "memb($Rs + #$u4_0)=#0"> { - bits<4> Rs; - bits<4> u4_0; - - let Inst{12-8} = 0b10010; - let Inst{7-4} = Rs; - let Inst{3-0} = u4_0; - } - -// SA1_clrtnew: Clear if true. -let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_clrtnew: SUBInst < - (outs IntRegs:$Rd), - (ins PredRegs:$Pu), - "if ($Pu.new) $Rd = #0"> { - bits<4> Rd; - - let Inst{12-9} = 0b1101; - let Inst{6-4} = 0b100; - let Inst{3-0} = Rd; - } - -// SL2_loadruh_io: Load half. -let isCodeGenOnly = 1, mayLoad = 1, accessSize = HalfWordAccess, hasNewValue = 1, opNewValue = 0 in -def SL2_loadruh_io: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs, u3_1Imm:$u3_1), - "$Rd = memuh($Rs + #$u3_1)"> { - bits<4> Rd; - bits<4> Rs; - bits<4> u3_1; - - let Inst{12-11} = 0b01; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - let Inst{10-8} = u3_1{3-1}; - } - -// SL2_jumpr31_tnew: Indirect conditional jump if true. -let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in -def SL2_jumpr31_tnew: SUBInst < - (outs ), - (ins ), - "if (p0.new) jumpr:nt r31"> { - let Inst{12-6} = 0b1111111; - let Inst{2-0} = 0b110; - } - -// SA1_addi: Add. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, isExtendable = 1, isExtentSigned = 1, opExtentBits = 7, opExtendable = 2 in -def SA1_addi: SUBInst < - (outs IntRegs:$Rx), - (ins IntRegs:$_src_, s7_0Ext:$s7), - "$Rx = add($_src_, #$s7)" , - [] , - "$_src_ = $Rx"> { - bits<4> Rx; - bits<7> s7; - - let Inst{12-11} = 0b00; - let Inst{3-0} = Rx; - let Inst{10-4} = s7; - } - -// SL1_loadrub_io: Load byte. -let isCodeGenOnly = 1, mayLoad = 1, accessSize = ByteAccess, hasNewValue = 1, opNewValue = 0 in -def SL1_loadrub_io: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs, u4_0Imm:$u4_0), - "$Rd = memub($Rs + #$u4_0)"> { - bits<4> Rd; - bits<4> Rs; - bits<4> u4_0; - - let Inst{12} = 0b1; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - let Inst{11-8} = u4_0; - } - -// SL1_loadri_io: Load word. -let isCodeGenOnly = 1, mayLoad = 1, accessSize = WordAccess, hasNewValue = 1, opNewValue = 0 in -def SL1_loadri_io: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs, u4_2Imm:$u4_2), - "$Rd = memw($Rs + #$u4_2)"> { - bits<4> Rd; - bits<4> Rs; - bits<6> u4_2; - - let Inst{12} = 0b0; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - let Inst{11-8} = u4_2{5-2}; - } - -// SA1_cmpeqi: Compareimmed. -let Defs = [P0], isCodeGenOnly = 1, hasSideEffects = 0 in -def SA1_cmpeqi: SUBInst < - (outs ), - (ins IntRegs:$Rs, u2_0Imm:$u2), - "p0 = cmp.eq($Rs, #$u2)"> { - bits<4> Rs; - bits<2> u2; - - let Inst{12-8} = 0b11001; - let Inst{7-4} = Rs; - let Inst{1-0} = u2; - } - -// SA1_combinerz: Combines. -let isCodeGenOnly = 1, hasSideEffects = 0 in -def SA1_combinerz: SUBInst < - (outs DoubleRegs:$Rdd), - (ins IntRegs:$Rs), - "$Rdd = combine($Rs, #0)"> { - bits<3> Rdd; - bits<4> Rs; - - let Inst{12-10} = 0b111; - let Inst{8} = 0b1; - let Inst{3} = 0b1; - let Inst{2-0} = Rdd; - let Inst{7-4} = Rs; - } - -// SL2_return_t: Deallocate stack frame and return. -// SL2_return_t -> SL2_return_tnew -let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in -def SL2_return_t: SUBInst < - (outs ), - (ins ), - "if (p0) dealloc_return"> { - let Inst{12-6} = 0b1111101; - let Inst{2-0} = 0b100; - } - -// SS2_allocframe: Allocate stack frame. -let Defs = [R29, R30], Uses = [R30, R31, R29], isCodeGenOnly = 1, mayStore = 1, accessSize = DoubleWordAccess in -def SS2_allocframe: SUBInst < - (outs ), - (ins u5_3Imm:$u5_3), - "allocframe(#$u5_3)"> { - bits<8> u5_3; - - let Inst{12-9} = 0b1110; - let Inst{8-4} = u5_3{7-3}; - } - -// SS2_storeh_io: Store half. -let isCodeGenOnly = 1, mayStore = 1, accessSize = HalfWordAccess in -def SS2_storeh_io: SUBInst < - (outs ), - (ins IntRegs:$Rs, u3_1Imm:$u3_1, IntRegs:$Rt), - "memh($Rs + #$u3_1) = $Rt"> { - bits<4> Rs; - bits<4> u3_1; - bits<4> Rt; - - let Inst{12-11} = 0b00; - let Inst{7-4} = Rs; - let Inst{10-8} = u3_1{3-1}; - let Inst{3-0} = Rt; - } - -// SS2_storewi0: Store word. -let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in -def SS2_storewi0: SUBInst < - (outs ), - (ins IntRegs:$Rs, u4_2Imm:$u4_2), - "memw($Rs + #$u4_2)=#0"> { - bits<4> Rs; - bits<6> u4_2; - - let Inst{12-8} = 0b10000; - let Inst{7-4} = Rs; - let Inst{3-0} = u4_2{5-2}; - } - -// SS2_storewi1: Store word. -let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in -def SS2_storewi1: SUBInst < - (outs ), - (ins IntRegs:$Rs, u4_2Imm:$u4_2), - "memw($Rs + #$u4_2)=#1"> { - bits<4> Rs; - bits<6> u4_2; - - let Inst{12-8} = 0b10001; - let Inst{7-4} = Rs; - let Inst{3-0} = u4_2{5-2}; - } - -// SL2_jumpr31: Indirect conditional jump if true. -let Defs = [PC], Uses = [R31], isCodeGenOnly = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in -def SL2_jumpr31: SUBInst < - (outs ), - (ins ), - "jumpr r31"> { - let Inst{12-6} = 0b1111111; - let Inst{2} = 0b0; - } - -// SA1_combinezr: Combines. -let isCodeGenOnly = 1, hasSideEffects = 0 in -def SA1_combinezr: SUBInst < - (outs DoubleRegs:$Rdd), - (ins IntRegs:$Rs), - "$Rdd = combine(#0, $Rs)"> { - bits<3> Rdd; - bits<4> Rs; - - let Inst{12-10} = 0b111; - let Inst{8} = 0b1; - let Inst{3} = 0b0; - let Inst{2-0} = Rdd; - let Inst{7-4} = Rs; - } - -// SL2_loadrh_io: Load half. -let isCodeGenOnly = 1, mayLoad = 1, accessSize = HalfWordAccess, hasNewValue = 1, opNewValue = 0 in -def SL2_loadrh_io: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs, u3_1Imm:$u3_1), - "$Rd = memh($Rs + #$u3_1)"> { - bits<4> Rd; - bits<4> Rs; - bits<4> u3_1; - - let Inst{12-11} = 0b00; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - let Inst{10-8} = u3_1{3-1}; - } - -// SA1_addrx: Add. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_addrx: SUBInst < - (outs IntRegs:$Rx), - (ins IntRegs:$_src_, IntRegs:$Rs), - "$Rx = add($_src_, $Rs)" , - [] , - "$_src_ = $Rx"> { - bits<4> Rx; - bits<4> Rs; - - let Inst{12-8} = 0b11000; - let Inst{3-0} = Rx; - let Inst{7-4} = Rs; - } - -// SA1_setin1: Set to -1. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_setin1: SUBInst < - (outs IntRegs:$Rd), - (ins ), - "$Rd = #{-1}"> { - bits<4> Rd; - - let Inst{12-9} = 0b1101; - let Inst{6} = 0b0; - let Inst{3-0} = Rd; - } - -// SA1_sxth: Sxth. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_sxth: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = sxth($Rs)"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10100; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SA1_combine0i: Combines. -let isCodeGenOnly = 1, hasSideEffects = 0 in -def SA1_combine0i: SUBInst < - (outs DoubleRegs:$Rdd), - (ins u2_0Imm:$u2), - "$Rdd = combine(#0, #$u2)"> { - bits<3> Rdd; - bits<2> u2; - - let Inst{12-10} = 0b111; - let Inst{8} = 0b0; - let Inst{4-3} = 0b00; - let Inst{2-0} = Rdd; - let Inst{6-5} = u2; - } - -// SA1_combine2i: Combines. -let isCodeGenOnly = 1, hasSideEffects = 0 in -def SA1_combine2i: SUBInst < - (outs DoubleRegs:$Rdd), - (ins u2_0Imm:$u2), - "$Rdd = combine(#2, #$u2)"> { - bits<3> Rdd; - bits<2> u2; - - let Inst{12-10} = 0b111; - let Inst{8} = 0b0; - let Inst{4-3} = 0b10; - let Inst{2-0} = Rdd; - let Inst{6-5} = u2; - } - -// SA1_sxtb: Sxtb. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_sxtb: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = sxtb($Rs)"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10101; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SA1_clrf: Clear if false. -// SA1_clrf -> SA1_clrfnew -let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_clrf: SUBInst < - (outs IntRegs:$Rd), - (ins PredRegs:$Pu), - "if (!$Pu) $Rd = #0"> { - bits<4> Rd; - - let Inst{12-9} = 0b1101; - let Inst{6-4} = 0b111; - let Inst{3-0} = Rd; - } - -// SL2_loadrb_io: Load byte. -let isCodeGenOnly = 1, mayLoad = 1, accessSize = ByteAccess, hasNewValue = 1, opNewValue = 0 in -def SL2_loadrb_io: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs, u3_0Imm:$u3_0), - "$Rd = memb($Rs + #$u3_0)"> { - bits<4> Rd; - bits<4> Rs; - bits<3> u3_0; - - let Inst{12-11} = 0b10; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - let Inst{10-8} = u3_0; - } - -// SA1_tfr: Tfr. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_tfr: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = $Rs"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10000; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SL2_loadrd_sp: Load dword. -let Uses = [R29], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess in -def SL2_loadrd_sp: SUBInst < - (outs DoubleRegs:$Rdd), - (ins u5_3Imm:$u5_3), - "$Rdd = memd(r29 + #$u5_3)"> { - bits<3> Rdd; - bits<8> u5_3; - - let Inst{12-8} = 0b11110; - let Inst{2-0} = Rdd; - let Inst{7-3} = u5_3{7-3}; - } - -// SA1_and1: And #1. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_and1: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = and($Rs, #1)"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10010; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SS2_storebi1: Store byte. -let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in -def SS2_storebi1: SUBInst < - (outs ), - (ins IntRegs:$Rs, u4_0Imm:$u4_0), - "memb($Rs + #$u4_0)=#1"> { - bits<4> Rs; - bits<4> u4_0; - - let Inst{12-8} = 0b10011; - let Inst{7-4} = Rs; - let Inst{3-0} = u4_0; - } - -// SA1_inc: Inc. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_inc: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = add($Rs, #1)"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10001; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SS2_stored_sp: Store dword. -let Uses = [R29], isCodeGenOnly = 1, mayStore = 1, accessSize = DoubleWordAccess in -def SS2_stored_sp: SUBInst < - (outs ), - (ins s6_3Imm:$s6_3, DoubleRegs:$Rtt), - "memd(r29 + #$s6_3) = $Rtt"> { - bits<9> s6_3; - bits<3> Rtt; - - let Inst{12-9} = 0b0101; - let Inst{8-3} = s6_3{8-3}; - let Inst{2-0} = Rtt; - } - -// SS2_storew_sp: Store word. -let Uses = [R29], isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in -def SS2_storew_sp: SUBInst < - (outs ), - (ins u5_2Imm:$u5_2, IntRegs:$Rt), - "memw(r29 + #$u5_2) = $Rt"> { - bits<7> u5_2; - bits<4> Rt; - - let Inst{12-9} = 0b0100; - let Inst{8-4} = u5_2{6-2}; - let Inst{3-0} = Rt; - } - -// SL2_jumpr31_fnew: Indirect conditional jump if false. -let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in -def SL2_jumpr31_fnew: SUBInst < - (outs ), - (ins ), - "if (!p0.new) jumpr:nt r31"> { - let Inst{12-6} = 0b1111111; - let Inst{2-0} = 0b111; - } - -// SA1_clrt: Clear if true. -// SA1_clrt -> SA1_clrtnew -let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_clrt: SUBInst < - (outs IntRegs:$Rd), - (ins PredRegs:$Pu), - "if ($Pu) $Rd = #0"> { - bits<4> Rd; - - let Inst{12-9} = 0b1101; - let Inst{6-4} = 0b110; - let Inst{3-0} = Rd; - } - -// SL2_return: Deallocate stack frame and return. -let Defs = [PC, R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in -def SL2_return: SUBInst < - (outs ), - (ins ), - "dealloc_return"> { - let Inst{12-6} = 0b1111101; - let Inst{2} = 0b0; - } - -// SA1_dec: Dec. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_dec: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = add($Rs,#{-1})"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10011; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SA1_seti: Set immed. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, isExtendable = 1, isExtentSigned = 0, opExtentBits = 6, opExtendable = 1 in -def SA1_seti: SUBInst < - (outs IntRegs:$Rd), - (ins u6_0Ext:$u6), - "$Rd = #$u6"> { - bits<4> Rd; - bits<6> u6; - - let Inst{12-10} = 0b010; - let Inst{3-0} = Rd; - let Inst{9-4} = u6; - } - -// SL2_jumpr31_t: Indirect conditional jump if true. -// SL2_jumpr31_t -> SL2_jumpr31_tnew -let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in -def SL2_jumpr31_t: SUBInst < - (outs ), - (ins ), - "if (p0) jumpr r31"> { - let Inst{12-6} = 0b1111111; - let Inst{2-0} = 0b100; - } - -// SA1_clrfnew: Clear if false. -let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_clrfnew: SUBInst < - (outs IntRegs:$Rd), - (ins PredRegs:$Pu), - "if (!$Pu.new) $Rd = #0"> { - bits<4> Rd; - - let Inst{12-9} = 0b1101; - let Inst{6-4} = 0b101; - let Inst{3-0} = Rd; - } - -// SS1_storew_io: Store word. -let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in -def SS1_storew_io: SUBInst < - (outs ), - (ins IntRegs:$Rs, u4_2Imm:$u4_2, IntRegs:$Rt), - "memw($Rs + #$u4_2) = $Rt"> { - bits<4> Rs; - bits<6> u4_2; - bits<4> Rt; - - let Inst{12} = 0b0; - let Inst{7-4} = Rs; - let Inst{11-8} = u4_2{5-2}; - let Inst{3-0} = Rt; - } - -// SA1_zxtb: Zxtb. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_zxtb: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = and($Rs, #255)"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10111; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - -// SA1_addsp: Add. -let Uses = [R29], isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_addsp: SUBInst < - (outs IntRegs:$Rd), - (ins u6_2Imm:$u6_2), - "$Rd = add(r29, #$u6_2)"> { - bits<4> Rd; - bits<8> u6_2; - - let Inst{12-10} = 0b011; - let Inst{3-0} = Rd; - let Inst{9-4} = u6_2{7-2}; - } - -// SL2_loadri_sp: Load word. -let Uses = [R29], isCodeGenOnly = 1, mayLoad = 1, accessSize = WordAccess, hasNewValue = 1, opNewValue = 0 in -def SL2_loadri_sp: SUBInst < - (outs IntRegs:$Rd), - (ins u5_2Imm:$u5_2), - "$Rd = memw(r29 + #$u5_2)"> { - bits<4> Rd; - bits<7> u5_2; - - let Inst{12-9} = 0b1110; - let Inst{3-0} = Rd; - let Inst{8-4} = u5_2{6-2}; - } - -// SS1_storeb_io: Store byte. -let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in -def SS1_storeb_io: SUBInst < - (outs ), - (ins IntRegs:$Rs, u4_0Imm:$u4_0, IntRegs:$Rt), - "memb($Rs + #$u4_0) = $Rt"> { - bits<4> Rs; - bits<4> u4_0; - bits<4> Rt; - - let Inst{12} = 0b1; - let Inst{7-4} = Rs; - let Inst{11-8} = u4_0; - let Inst{3-0} = Rt; - } - -// SL2_return_tnew: Deallocate stack frame and return. -let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in -def SL2_return_tnew: SUBInst < - (outs ), - (ins ), - "if (p0.new) dealloc_return:nt"> { - let Inst{12-6} = 0b1111101; - let Inst{2-0} = 0b110; - } - -// SL2_return_fnew: Deallocate stack frame and return. -let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in -def SL2_return_fnew: SUBInst < - (outs ), - (ins ), - "if (!p0.new) dealloc_return:nt"> { - let Inst{12-6} = 0b1111101; - let Inst{2-0} = 0b111; - } - -// SA1_zxth: Zxth. -let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in -def SA1_zxth: SUBInst < - (outs IntRegs:$Rd), - (ins IntRegs:$Rs), - "$Rd = zxth($Rs)"> { - bits<4> Rd; - bits<4> Rs; - - let Inst{12-8} = 0b10110; - let Inst{3-0} = Rd; - let Inst{7-4} = Rs; - } - diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp new file mode 100644 index 000000000000..b5948475e1f7 --- /dev/null +++ b/contrib/llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp @@ -0,0 +1,2338 @@ +//===--- HexagonLoopIdiomRecognition.cpp ----------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "hexagon-lir" + +#include "llvm/ADT/SetVector.h" +#include "llvm/ADT/SmallSet.h" +#include "llvm/Analysis/AliasAnalysis.h" +#include "llvm/Analysis/InstructionSimplify.h" +#include "llvm/Analysis/LoopPass.h" +#include "llvm/Analysis/ScalarEvolution.h" +#include "llvm/Analysis/ScalarEvolutionExpander.h" +#include "llvm/Analysis/ScalarEvolutionExpressions.h" +#include "llvm/Analysis/TargetLibraryInfo.h" +#include "llvm/Analysis/ValueTracking.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/IR/Dominators.h" +#include "llvm/IR/IRBuilder.h" +#include "llvm/IR/PatternMatch.h" +#include "llvm/Transforms/Scalar.h" +#include "llvm/Transforms/Utils/Local.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" + +#include <algorithm> +#include <array> + +using namespace llvm; + +static cl::opt<bool> DisableMemcpyIdiom("disable-memcpy-idiom", + cl::Hidden, cl::init(false), + cl::desc("Disable generation of memcpy in loop idiom recognition")); + +static cl::opt<bool> DisableMemmoveIdiom("disable-memmove-idiom", + cl::Hidden, cl::init(false), + cl::desc("Disable generation of memmove in loop idiom recognition")); + +static cl::opt<unsigned> RuntimeMemSizeThreshold("runtime-mem-idiom-threshold", + cl::Hidden, cl::init(0), cl::desc("Threshold (in bytes) for the runtime " + "check guarding the memmove.")); + +static cl::opt<unsigned> CompileTimeMemSizeThreshold( + "compile-time-mem-idiom-threshold", cl::Hidden, cl::init(64), + cl::desc("Threshold (in bytes) to perform the transformation, if the " + "runtime loop count (mem transfer size) is known at compile-time.")); + +static cl::opt<bool> OnlyNonNestedMemmove("only-nonnested-memmove-idiom", + cl::Hidden, cl::init(true), + cl::desc("Only enable generating memmove in non-nested loops")); + +cl::opt<bool> HexagonVolatileMemcpy("disable-hexagon-volatile-memcpy", + cl::Hidden, cl::init(false), + cl::desc("Enable Hexagon-specific memcpy for volatile destination.")); + +static const char *HexagonVolatileMemcpyName + = "hexagon_memcpy_forward_vp4cp4n2"; + + +namespace llvm { + void initializeHexagonLoopIdiomRecognizePass(PassRegistry&); + Pass *createHexagonLoopIdiomPass(); +} + +namespace { + class HexagonLoopIdiomRecognize : public LoopPass { + public: + static char ID; + explicit HexagonLoopIdiomRecognize() : LoopPass(ID) { + initializeHexagonLoopIdiomRecognizePass(*PassRegistry::getPassRegistry()); + } + StringRef getPassName() const override { + return "Recognize Hexagon-specific loop idioms"; + } + + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired<LoopInfoWrapperPass>(); + AU.addRequiredID(LoopSimplifyID); + AU.addRequiredID(LCSSAID); + AU.addRequired<AAResultsWrapperPass>(); + AU.addPreserved<AAResultsWrapperPass>(); + AU.addRequired<ScalarEvolutionWrapperPass>(); + AU.addRequired<DominatorTreeWrapperPass>(); + AU.addRequired<TargetLibraryInfoWrapperPass>(); + AU.addPreserved<TargetLibraryInfoWrapperPass>(); + } + + bool runOnLoop(Loop *L, LPPassManager &LPM) override; + + private: + unsigned getStoreSizeInBytes(StoreInst *SI); + int getSCEVStride(const SCEVAddRecExpr *StoreEv); + bool isLegalStore(Loop *CurLoop, StoreInst *SI); + void collectStores(Loop *CurLoop, BasicBlock *BB, + SmallVectorImpl<StoreInst*> &Stores); + bool processCopyingStore(Loop *CurLoop, StoreInst *SI, const SCEV *BECount); + bool coverLoop(Loop *L, SmallVectorImpl<Instruction*> &Insts) const; + bool runOnLoopBlock(Loop *CurLoop, BasicBlock *BB, const SCEV *BECount, + SmallVectorImpl<BasicBlock*> &ExitBlocks); + bool runOnCountableLoop(Loop *L); + + AliasAnalysis *AA; + const DataLayout *DL; + DominatorTree *DT; + LoopInfo *LF; + const TargetLibraryInfo *TLI; + ScalarEvolution *SE; + bool HasMemcpy, HasMemmove; + }; +} + +char HexagonLoopIdiomRecognize::ID = 0; + +INITIALIZE_PASS_BEGIN(HexagonLoopIdiomRecognize, "hexagon-loop-idiom", + "Recognize Hexagon-specific loop idioms", false, false) +INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass) +INITIALIZE_PASS_DEPENDENCY(LoopSimplify) +INITIALIZE_PASS_DEPENDENCY(LCSSAWrapperPass) +INITIALIZE_PASS_DEPENDENCY(ScalarEvolutionWrapperPass) +INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass) +INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfoWrapperPass) +INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass) +INITIALIZE_PASS_END(HexagonLoopIdiomRecognize, "hexagon-loop-idiom", + "Recognize Hexagon-specific loop idioms", false, false) + + +namespace { + struct Simplifier { + typedef std::function<Value* (Instruction*, LLVMContext&)> Rule; + + void addRule(const Rule &R) { Rules.push_back(R); } + + private: + struct WorkListType { + WorkListType() = default; + + void push_back(Value* V) { + // Do not push back duplicates. + if (!S.count(V)) { Q.push_back(V); S.insert(V); } + } + Value *pop_front_val() { + Value *V = Q.front(); Q.pop_front(); S.erase(V); + return V; + } + bool empty() const { return Q.empty(); } + + private: + std::deque<Value*> Q; + std::set<Value*> S; + }; + + typedef std::set<Value*> ValueSetType; + std::vector<Rule> Rules; + + public: + struct Context { + typedef DenseMap<Value*,Value*> ValueMapType; + + Value *Root; + ValueSetType Used; // The set of all cloned values used by Root. + ValueSetType Clones; // The set of all cloned values. + LLVMContext &Ctx; + + Context(Instruction *Exp) + : Ctx(Exp->getParent()->getParent()->getContext()) { + initialize(Exp); + } + ~Context() { cleanup(); } + void print(raw_ostream &OS, const Value *V) const; + + Value *materialize(BasicBlock *B, BasicBlock::iterator At); + + private: + void initialize(Instruction *Exp); + void cleanup(); + + template <typename FuncT> void traverse(Value *V, FuncT F); + void record(Value *V); + void use(Value *V); + void unuse(Value *V); + + bool equal(const Instruction *I, const Instruction *J) const; + Value *find(Value *Tree, Value *Sub) const; + Value *subst(Value *Tree, Value *OldV, Value *NewV); + void replace(Value *OldV, Value *NewV); + void link(Instruction *I, BasicBlock *B, BasicBlock::iterator At); + + friend struct Simplifier; + }; + + Value *simplify(Context &C); + }; + + struct PE { + PE(const Simplifier::Context &c, Value *v = nullptr) : C(c), V(v) {} + const Simplifier::Context &C; + const Value *V; + }; + + raw_ostream &operator<< (raw_ostream &OS, const PE &P) LLVM_ATTRIBUTE_USED; + raw_ostream &operator<< (raw_ostream &OS, const PE &P) { + P.C.print(OS, P.V ? P.V : P.C.Root); + return OS; + } +} + + +template <typename FuncT> +void Simplifier::Context::traverse(Value *V, FuncT F) { + WorkListType Q; + Q.push_back(V); + + while (!Q.empty()) { + Instruction *U = dyn_cast<Instruction>(Q.pop_front_val()); + if (!U || U->getParent()) + continue; + if (!F(U)) + continue; + for (Value *Op : U->operands()) + Q.push_back(Op); + } +} + + +void Simplifier::Context::print(raw_ostream &OS, const Value *V) const { + const auto *U = dyn_cast<const Instruction>(V); + if (!U) { + OS << V << '(' << *V << ')'; + return; + } + + if (U->getParent()) { + OS << U << '('; + U->printAsOperand(OS, true); + OS << ')'; + return; + } + + unsigned N = U->getNumOperands(); + if (N != 0) + OS << U << '('; + OS << U->getOpcodeName(); + for (const Value *Op : U->operands()) { + OS << ' '; + print(OS, Op); + } + if (N != 0) + OS << ')'; +} + + +void Simplifier::Context::initialize(Instruction *Exp) { + // Perform a deep clone of the expression, set Root to the root + // of the clone, and build a map from the cloned values to the + // original ones. + ValueMapType M; + BasicBlock *Block = Exp->getParent(); + WorkListType Q; + Q.push_back(Exp); + + while (!Q.empty()) { + Value *V = Q.pop_front_val(); + if (M.find(V) != M.end()) + continue; + if (Instruction *U = dyn_cast<Instruction>(V)) { + if (isa<PHINode>(U) || U->getParent() != Block) + continue; + for (Value *Op : U->operands()) + Q.push_back(Op); + M.insert({U, U->clone()}); + } + } + + for (std::pair<Value*,Value*> P : M) { + Instruction *U = cast<Instruction>(P.second); + for (unsigned i = 0, n = U->getNumOperands(); i != n; ++i) { + auto F = M.find(U->getOperand(i)); + if (F != M.end()) + U->setOperand(i, F->second); + } + } + + auto R = M.find(Exp); + assert(R != M.end()); + Root = R->second; + + record(Root); + use(Root); +} + + +void Simplifier::Context::record(Value *V) { + auto Record = [this](Instruction *U) -> bool { + Clones.insert(U); + return true; + }; + traverse(V, Record); +} + + +void Simplifier::Context::use(Value *V) { + auto Use = [this](Instruction *U) -> bool { + Used.insert(U); + return true; + }; + traverse(V, Use); +} + + +void Simplifier::Context::unuse(Value *V) { + if (!isa<Instruction>(V) || cast<Instruction>(V)->getParent() != nullptr) + return; + + auto Unuse = [this](Instruction *U) -> bool { + if (!U->use_empty()) + return false; + Used.erase(U); + return true; + }; + traverse(V, Unuse); +} + + +Value *Simplifier::Context::subst(Value *Tree, Value *OldV, Value *NewV) { + if (Tree == OldV) + return NewV; + if (OldV == NewV) + return Tree; + + WorkListType Q; + Q.push_back(Tree); + while (!Q.empty()) { + Instruction *U = dyn_cast<Instruction>(Q.pop_front_val()); + // If U is not an instruction, or it's not a clone, skip it. + if (!U || U->getParent()) + continue; + for (unsigned i = 0, n = U->getNumOperands(); i != n; ++i) { + Value *Op = U->getOperand(i); + if (Op == OldV) { + U->setOperand(i, NewV); + unuse(OldV); + } else { + Q.push_back(Op); + } + } + } + return Tree; +} + + +void Simplifier::Context::replace(Value *OldV, Value *NewV) { + if (Root == OldV) { + Root = NewV; + use(Root); + return; + } + + // NewV may be a complex tree that has just been created by one of the + // transformation rules. We need to make sure that it is commoned with + // the existing Root to the maximum extent possible. + // Identify all subtrees of NewV (including NewV itself) that have + // equivalent counterparts in Root, and replace those subtrees with + // these counterparts. + WorkListType Q; + Q.push_back(NewV); + while (!Q.empty()) { + Value *V = Q.pop_front_val(); + Instruction *U = dyn_cast<Instruction>(V); + if (!U || U->getParent()) + continue; + if (Value *DupV = find(Root, V)) { + if (DupV != V) + NewV = subst(NewV, V, DupV); + } else { + for (Value *Op : U->operands()) + Q.push_back(Op); + } + } + + // Now, simply replace OldV with NewV in Root. + Root = subst(Root, OldV, NewV); + use(Root); +} + + +void Simplifier::Context::cleanup() { + for (Value *V : Clones) { + Instruction *U = cast<Instruction>(V); + if (!U->getParent()) + U->dropAllReferences(); + } + + for (Value *V : Clones) { + Instruction *U = cast<Instruction>(V); + if (!U->getParent()) + delete U; + } +} + + +bool Simplifier::Context::equal(const Instruction *I, + const Instruction *J) const { + if (I == J) + return true; + if (!I->isSameOperationAs(J)) + return false; + if (isa<PHINode>(I)) + return I->isIdenticalTo(J); + + for (unsigned i = 0, n = I->getNumOperands(); i != n; ++i) { + Value *OpI = I->getOperand(i), *OpJ = J->getOperand(i); + if (OpI == OpJ) + continue; + auto *InI = dyn_cast<const Instruction>(OpI); + auto *InJ = dyn_cast<const Instruction>(OpJ); + if (InI && InJ) { + if (!equal(InI, InJ)) + return false; + } else if (InI != InJ || !InI) + return false; + } + return true; +} + + +Value *Simplifier::Context::find(Value *Tree, Value *Sub) const { + Instruction *SubI = dyn_cast<Instruction>(Sub); + WorkListType Q; + Q.push_back(Tree); + + while (!Q.empty()) { + Value *V = Q.pop_front_val(); + if (V == Sub) + return V; + Instruction *U = dyn_cast<Instruction>(V); + if (!U || U->getParent()) + continue; + if (SubI && equal(SubI, U)) + return U; + assert(!isa<PHINode>(U)); + for (Value *Op : U->operands()) + Q.push_back(Op); + } + return nullptr; +} + + +void Simplifier::Context::link(Instruction *I, BasicBlock *B, + BasicBlock::iterator At) { + if (I->getParent()) + return; + + for (Value *Op : I->operands()) { + if (Instruction *OpI = dyn_cast<Instruction>(Op)) + link(OpI, B, At); + } + + B->getInstList().insert(At, I); +} + + +Value *Simplifier::Context::materialize(BasicBlock *B, + BasicBlock::iterator At) { + if (Instruction *RootI = dyn_cast<Instruction>(Root)) + link(RootI, B, At); + return Root; +} + + +Value *Simplifier::simplify(Context &C) { + WorkListType Q; + Q.push_back(C.Root); + unsigned Count = 0; + const unsigned Limit = 100000; + + while (!Q.empty()) { + if (Count++ >= Limit) + break; + Instruction *U = dyn_cast<Instruction>(Q.pop_front_val()); + if (!U || U->getParent() || !C.Used.count(U)) + continue; + bool Changed = false; + for (Rule &R : Rules) { + Value *W = R(U, C.Ctx); + if (!W) + continue; + Changed = true; + C.record(W); + C.replace(U, W); + Q.push_back(C.Root); + break; + } + if (!Changed) { + for (Value *Op : U->operands()) + Q.push_back(Op); + } + } + assert(Count < Limit && "Infinite loop in HLIR/simplify?"); + return C.Root; +} + + +//===----------------------------------------------------------------------===// +// +// Implementation of PolynomialMultiplyRecognize +// +//===----------------------------------------------------------------------===// + +namespace { + class PolynomialMultiplyRecognize { + public: + explicit PolynomialMultiplyRecognize(Loop *loop, const DataLayout &dl, + const DominatorTree &dt, const TargetLibraryInfo &tli, + ScalarEvolution &se) + : CurLoop(loop), DL(dl), DT(dt), TLI(tli), SE(se) {} + + bool recognize(); + private: + typedef SetVector<Value*> ValueSeq; + + IntegerType *getPmpyType() const { + LLVMContext &Ctx = CurLoop->getHeader()->getParent()->getContext(); + return IntegerType::get(Ctx, 32); + } + bool isPromotableTo(Value *V, IntegerType *Ty); + void promoteTo(Instruction *In, IntegerType *DestTy, BasicBlock *LoopB); + bool promoteTypes(BasicBlock *LoopB, BasicBlock *ExitB); + + Value *getCountIV(BasicBlock *BB); + bool findCycle(Value *Out, Value *In, ValueSeq &Cycle); + void classifyCycle(Instruction *DivI, ValueSeq &Cycle, ValueSeq &Early, + ValueSeq &Late); + bool classifyInst(Instruction *UseI, ValueSeq &Early, ValueSeq &Late); + bool commutesWithShift(Instruction *I); + bool highBitsAreZero(Value *V, unsigned IterCount); + bool keepsHighBitsZero(Value *V, unsigned IterCount); + bool isOperandShifted(Instruction *I, Value *Op); + bool convertShiftsToLeft(BasicBlock *LoopB, BasicBlock *ExitB, + unsigned IterCount); + void cleanupLoopBody(BasicBlock *LoopB); + + struct ParsedValues { + ParsedValues() : M(nullptr), P(nullptr), Q(nullptr), R(nullptr), + X(nullptr), Res(nullptr), IterCount(0), Left(false), Inv(false) {} + Value *M, *P, *Q, *R, *X; + Instruction *Res; + unsigned IterCount; + bool Left, Inv; + }; + + bool matchLeftShift(SelectInst *SelI, Value *CIV, ParsedValues &PV); + bool matchRightShift(SelectInst *SelI, ParsedValues &PV); + bool scanSelect(SelectInst *SI, BasicBlock *LoopB, BasicBlock *PrehB, + Value *CIV, ParsedValues &PV, bool PreScan); + unsigned getInverseMxN(unsigned QP); + Value *generate(BasicBlock::iterator At, ParsedValues &PV); + + void setupSimplifier(); + + Simplifier Simp; + Loop *CurLoop; + const DataLayout &DL; + const DominatorTree &DT; + const TargetLibraryInfo &TLI; + ScalarEvolution &SE; + }; +} + + +Value *PolynomialMultiplyRecognize::getCountIV(BasicBlock *BB) { + pred_iterator PI = pred_begin(BB), PE = pred_end(BB); + if (std::distance(PI, PE) != 2) + return nullptr; + BasicBlock *PB = (*PI == BB) ? *std::next(PI) : *PI; + + for (auto I = BB->begin(), E = BB->end(); I != E && isa<PHINode>(I); ++I) { + auto *PN = cast<PHINode>(I); + Value *InitV = PN->getIncomingValueForBlock(PB); + if (!isa<ConstantInt>(InitV) || !cast<ConstantInt>(InitV)->isZero()) + continue; + Value *IterV = PN->getIncomingValueForBlock(BB); + if (!isa<BinaryOperator>(IterV)) + continue; + auto *BO = dyn_cast<BinaryOperator>(IterV); + if (BO->getOpcode() != Instruction::Add) + continue; + Value *IncV = nullptr; + if (BO->getOperand(0) == PN) + IncV = BO->getOperand(1); + else if (BO->getOperand(1) == PN) + IncV = BO->getOperand(0); + if (IncV == nullptr) + continue; + + if (auto *T = dyn_cast<ConstantInt>(IncV)) + if (T->getZExtValue() == 1) + return PN; + } + return nullptr; +} + + +static void replaceAllUsesOfWithIn(Value *I, Value *J, BasicBlock *BB) { + for (auto UI = I->user_begin(), UE = I->user_end(); UI != UE;) { + Use &TheUse = UI.getUse(); + ++UI; + if (auto *II = dyn_cast<Instruction>(TheUse.getUser())) + if (BB == II->getParent()) + II->replaceUsesOfWith(I, J); + } +} + + +bool PolynomialMultiplyRecognize::matchLeftShift(SelectInst *SelI, + Value *CIV, ParsedValues &PV) { + // Match the following: + // select (X & (1 << i)) != 0 ? R ^ (Q << i) : R + // select (X & (1 << i)) == 0 ? R : R ^ (Q << i) + // The condition may also check for equality with the masked value, i.e + // select (X & (1 << i)) == (1 << i) ? R ^ (Q << i) : R + // select (X & (1 << i)) != (1 << i) ? R : R ^ (Q << i); + + Value *CondV = SelI->getCondition(); + Value *TrueV = SelI->getTrueValue(); + Value *FalseV = SelI->getFalseValue(); + + using namespace PatternMatch; + + CmpInst::Predicate P; + Value *A = nullptr, *B = nullptr, *C = nullptr; + + if (!match(CondV, m_ICmp(P, m_And(m_Value(A), m_Value(B)), m_Value(C))) && + !match(CondV, m_ICmp(P, m_Value(C), m_And(m_Value(A), m_Value(B))))) + return false; + if (P != CmpInst::ICMP_EQ && P != CmpInst::ICMP_NE) + return false; + // Matched: select (A & B) == C ? ... : ... + // select (A & B) != C ? ... : ... + + Value *X = nullptr, *Sh1 = nullptr; + // Check (A & B) for (X & (1 << i)): + if (match(A, m_Shl(m_One(), m_Specific(CIV)))) { + Sh1 = A; + X = B; + } else if (match(B, m_Shl(m_One(), m_Specific(CIV)))) { + Sh1 = B; + X = A; + } else { + // TODO: Could also check for an induction variable containing single + // bit shifted left by 1 in each iteration. + return false; + } + + bool TrueIfZero; + + // Check C against the possible values for comparison: 0 and (1 << i): + if (match(C, m_Zero())) + TrueIfZero = (P == CmpInst::ICMP_EQ); + else if (C == Sh1) + TrueIfZero = (P == CmpInst::ICMP_NE); + else + return false; + + // So far, matched: + // select (X & (1 << i)) ? ... : ... + // including variations of the check against zero/non-zero value. + + Value *ShouldSameV = nullptr, *ShouldXoredV = nullptr; + if (TrueIfZero) { + ShouldSameV = TrueV; + ShouldXoredV = FalseV; + } else { + ShouldSameV = FalseV; + ShouldXoredV = TrueV; + } + + Value *Q = nullptr, *R = nullptr, *Y = nullptr, *Z = nullptr; + Value *T = nullptr; + if (match(ShouldXoredV, m_Xor(m_Value(Y), m_Value(Z)))) { + // Matched: select +++ ? ... : Y ^ Z + // select +++ ? Y ^ Z : ... + // where +++ denotes previously checked matches. + if (ShouldSameV == Y) + T = Z; + else if (ShouldSameV == Z) + T = Y; + else + return false; + R = ShouldSameV; + // Matched: select +++ ? R : R ^ T + // select +++ ? R ^ T : R + // depending on TrueIfZero. + + } else if (match(ShouldSameV, m_Zero())) { + // Matched: select +++ ? 0 : ... + // select +++ ? ... : 0 + if (!SelI->hasOneUse()) + return false; + T = ShouldXoredV; + // Matched: select +++ ? 0 : T + // select +++ ? T : 0 + + Value *U = *SelI->user_begin(); + if (!match(U, m_Xor(m_Specific(SelI), m_Value(R))) && + !match(U, m_Xor(m_Value(R), m_Specific(SelI)))) + return false; + // Matched: xor (select +++ ? 0 : T), R + // xor (select +++ ? T : 0), R + } else + return false; + + // The xor input value T is isolated into its own match so that it could + // be checked against an induction variable containing a shifted bit + // (todo). + // For now, check against (Q << i). + if (!match(T, m_Shl(m_Value(Q), m_Specific(CIV))) && + !match(T, m_Shl(m_ZExt(m_Value(Q)), m_ZExt(m_Specific(CIV))))) + return false; + // Matched: select +++ ? R : R ^ (Q << i) + // select +++ ? R ^ (Q << i) : R + + PV.X = X; + PV.Q = Q; + PV.R = R; + PV.Left = true; + return true; +} + + +bool PolynomialMultiplyRecognize::matchRightShift(SelectInst *SelI, + ParsedValues &PV) { + // Match the following: + // select (X & 1) != 0 ? (R >> 1) ^ Q : (R >> 1) + // select (X & 1) == 0 ? (R >> 1) : (R >> 1) ^ Q + // The condition may also check for equality with the masked value, i.e + // select (X & 1) == 1 ? (R >> 1) ^ Q : (R >> 1) + // select (X & 1) != 1 ? (R >> 1) : (R >> 1) ^ Q + + Value *CondV = SelI->getCondition(); + Value *TrueV = SelI->getTrueValue(); + Value *FalseV = SelI->getFalseValue(); + + using namespace PatternMatch; + + Value *C = nullptr; + CmpInst::Predicate P; + bool TrueIfZero; + + if (match(CondV, m_ICmp(P, m_Value(C), m_Zero())) || + match(CondV, m_ICmp(P, m_Zero(), m_Value(C)))) { + if (P != CmpInst::ICMP_EQ && P != CmpInst::ICMP_NE) + return false; + // Matched: select C == 0 ? ... : ... + // select C != 0 ? ... : ... + TrueIfZero = (P == CmpInst::ICMP_EQ); + } else if (match(CondV, m_ICmp(P, m_Value(C), m_One())) || + match(CondV, m_ICmp(P, m_One(), m_Value(C)))) { + if (P != CmpInst::ICMP_EQ && P != CmpInst::ICMP_NE) + return false; + // Matched: select C == 1 ? ... : ... + // select C != 1 ? ... : ... + TrueIfZero = (P == CmpInst::ICMP_NE); + } else + return false; + + Value *X = nullptr; + if (!match(C, m_And(m_Value(X), m_One())) && + !match(C, m_And(m_One(), m_Value(X)))) + return false; + // Matched: select (X & 1) == +++ ? ... : ... + // select (X & 1) != +++ ? ... : ... + + Value *R = nullptr, *Q = nullptr; + if (TrueIfZero) { + // The select's condition is true if the tested bit is 0. + // TrueV must be the shift, FalseV must be the xor. + if (!match(TrueV, m_LShr(m_Value(R), m_One()))) + return false; + // Matched: select +++ ? (R >> 1) : ... + if (!match(FalseV, m_Xor(m_Specific(TrueV), m_Value(Q))) && + !match(FalseV, m_Xor(m_Value(Q), m_Specific(TrueV)))) + return false; + // Matched: select +++ ? (R >> 1) : (R >> 1) ^ Q + // with commuting ^. + } else { + // The select's condition is true if the tested bit is 1. + // TrueV must be the xor, FalseV must be the shift. + if (!match(FalseV, m_LShr(m_Value(R), m_One()))) + return false; + // Matched: select +++ ? ... : (R >> 1) + if (!match(TrueV, m_Xor(m_Specific(FalseV), m_Value(Q))) && + !match(TrueV, m_Xor(m_Value(Q), m_Specific(FalseV)))) + return false; + // Matched: select +++ ? (R >> 1) ^ Q : (R >> 1) + // with commuting ^. + } + + PV.X = X; + PV.Q = Q; + PV.R = R; + PV.Left = false; + return true; +} + + +bool PolynomialMultiplyRecognize::scanSelect(SelectInst *SelI, + BasicBlock *LoopB, BasicBlock *PrehB, Value *CIV, ParsedValues &PV, + bool PreScan) { + using namespace PatternMatch; + // The basic pattern for R = P.Q is: + // for i = 0..31 + // R = phi (0, R') + // if (P & (1 << i)) ; test-bit(P, i) + // R' = R ^ (Q << i) + // + // Similarly, the basic pattern for R = (P/Q).Q - P + // for i = 0..31 + // R = phi(P, R') + // if (R & (1 << i)) + // R' = R ^ (Q << i) + + // There exist idioms, where instead of Q being shifted left, P is shifted + // right. This produces a result that is shifted right by 32 bits (the + // non-shifted result is 64-bit). + // + // For R = P.Q, this would be: + // for i = 0..31 + // R = phi (0, R') + // if ((P >> i) & 1) + // R' = (R >> 1) ^ Q ; R is cycled through the loop, so it must + // else ; be shifted by 1, not i. + // R' = R >> 1 + // + // And for the inverse: + // for i = 0..31 + // R = phi (P, R') + // if (R & 1) + // R' = (R >> 1) ^ Q + // else + // R' = R >> 1 + + // The left-shifting idioms share the same pattern: + // select (X & (1 << i)) ? R ^ (Q << i) : R + // Similarly for right-shifting idioms: + // select (X & 1) ? (R >> 1) ^ Q + + if (matchLeftShift(SelI, CIV, PV)) { + // If this is a pre-scan, getting this far is sufficient. + if (PreScan) + return true; + + // Need to make sure that the SelI goes back into R. + auto *RPhi = dyn_cast<PHINode>(PV.R); + if (!RPhi) + return false; + if (SelI != RPhi->getIncomingValueForBlock(LoopB)) + return false; + PV.Res = SelI; + + // If X is loop invariant, it must be the input polynomial, and the + // idiom is the basic polynomial multiply. + if (CurLoop->isLoopInvariant(PV.X)) { + PV.P = PV.X; + PV.Inv = false; + } else { + // X is not loop invariant. If X == R, this is the inverse pmpy. + // Otherwise, check for an xor with an invariant value. If the + // variable argument to the xor is R, then this is still a valid + // inverse pmpy. + PV.Inv = true; + if (PV.X != PV.R) { + Value *Var = nullptr, *Inv = nullptr, *X1 = nullptr, *X2 = nullptr; + if (!match(PV.X, m_Xor(m_Value(X1), m_Value(X2)))) + return false; + auto *I1 = dyn_cast<Instruction>(X1); + auto *I2 = dyn_cast<Instruction>(X2); + if (!I1 || I1->getParent() != LoopB) { + Var = X2; + Inv = X1; + } else if (!I2 || I2->getParent() != LoopB) { + Var = X1; + Inv = X2; + } else + return false; + if (Var != PV.R) + return false; + PV.M = Inv; + } + // The input polynomial P still needs to be determined. It will be + // the entry value of R. + Value *EntryP = RPhi->getIncomingValueForBlock(PrehB); + PV.P = EntryP; + } + + return true; + } + + if (matchRightShift(SelI, PV)) { + // If this is an inverse pattern, the Q polynomial must be known at + // compile time. + if (PV.Inv && !isa<ConstantInt>(PV.Q)) + return false; + if (PreScan) + return true; + // There is no exact matching of right-shift pmpy. + return false; + } + + return false; +} + + +bool PolynomialMultiplyRecognize::isPromotableTo(Value *Val, + IntegerType *DestTy) { + IntegerType *T = dyn_cast<IntegerType>(Val->getType()); + if (!T || T->getBitWidth() > DestTy->getBitWidth()) + return false; + if (T->getBitWidth() == DestTy->getBitWidth()) + return true; + // Non-instructions are promotable. The reason why an instruction may not + // be promotable is that it may produce a different result if its operands + // and the result are promoted, for example, it may produce more non-zero + // bits. While it would still be possible to represent the proper result + // in a wider type, it may require adding additional instructions (which + // we don't want to do). + Instruction *In = dyn_cast<Instruction>(Val); + if (!In) + return true; + // The bitwidth of the source type is smaller than the destination. + // Check if the individual operation can be promoted. + switch (In->getOpcode()) { + case Instruction::PHI: + case Instruction::ZExt: + case Instruction::And: + case Instruction::Or: + case Instruction::Xor: + case Instruction::LShr: // Shift right is ok. + case Instruction::Select: + return true; + case Instruction::ICmp: + if (CmpInst *CI = cast<CmpInst>(In)) + return CI->isEquality() || CI->isUnsigned(); + llvm_unreachable("Cast failed unexpectedly"); + case Instruction::Add: + return In->hasNoSignedWrap() && In->hasNoUnsignedWrap(); + } + return false; +} + + +void PolynomialMultiplyRecognize::promoteTo(Instruction *In, + IntegerType *DestTy, BasicBlock *LoopB) { + // Leave boolean values alone. + if (!In->getType()->isIntegerTy(1)) + In->mutateType(DestTy); + unsigned DestBW = DestTy->getBitWidth(); + + // Handle PHIs. + if (PHINode *P = dyn_cast<PHINode>(In)) { + unsigned N = P->getNumIncomingValues(); + for (unsigned i = 0; i != N; ++i) { + BasicBlock *InB = P->getIncomingBlock(i); + if (InB == LoopB) + continue; + Value *InV = P->getIncomingValue(i); + IntegerType *Ty = cast<IntegerType>(InV->getType()); + // Do not promote values in PHI nodes of type i1. + if (Ty != P->getType()) { + // If the value type does not match the PHI type, the PHI type + // must have been promoted. + assert(Ty->getBitWidth() < DestBW); + InV = IRBuilder<>(InB->getTerminator()).CreateZExt(InV, DestTy); + P->setIncomingValue(i, InV); + } + } + } else if (ZExtInst *Z = dyn_cast<ZExtInst>(In)) { + Value *Op = Z->getOperand(0); + if (Op->getType() == Z->getType()) + Z->replaceAllUsesWith(Op); + Z->eraseFromParent(); + return; + } + + // Promote immediates. + for (unsigned i = 0, n = In->getNumOperands(); i != n; ++i) { + if (ConstantInt *CI = dyn_cast<ConstantInt>(In->getOperand(i))) + if (CI->getType()->getBitWidth() < DestBW) + In->setOperand(i, ConstantInt::get(DestTy, CI->getZExtValue())); + } +} + + +bool PolynomialMultiplyRecognize::promoteTypes(BasicBlock *LoopB, + BasicBlock *ExitB) { + assert(LoopB); + // Skip loops where the exit block has more than one predecessor. The values + // coming from the loop block will be promoted to another type, and so the + // values coming into the exit block from other predecessors would also have + // to be promoted. + if (!ExitB || (ExitB->getSinglePredecessor() != LoopB)) + return false; + IntegerType *DestTy = getPmpyType(); + // Check if the exit values have types that are no wider than the type + // that we want to promote to. + unsigned DestBW = DestTy->getBitWidth(); + for (Instruction &In : *ExitB) { + PHINode *P = dyn_cast<PHINode>(&In); + if (!P) + break; + if (P->getNumIncomingValues() != 1) + return false; + assert(P->getIncomingBlock(0) == LoopB); + IntegerType *T = dyn_cast<IntegerType>(P->getType()); + if (!T || T->getBitWidth() > DestBW) + return false; + } + + // Check all instructions in the loop. + for (Instruction &In : *LoopB) + if (!In.isTerminator() && !isPromotableTo(&In, DestTy)) + return false; + + // Perform the promotion. + std::vector<Instruction*> LoopIns; + std::transform(LoopB->begin(), LoopB->end(), std::back_inserter(LoopIns), + [](Instruction &In) { return &In; }); + for (Instruction *In : LoopIns) + promoteTo(In, DestTy, LoopB); + + // Fix up the PHI nodes in the exit block. + Instruction *EndI = ExitB->getFirstNonPHI(); + BasicBlock::iterator End = EndI ? EndI->getIterator() : ExitB->end(); + for (auto I = ExitB->begin(); I != End; ++I) { + PHINode *P = dyn_cast<PHINode>(I); + if (!P) + break; + Type *Ty0 = P->getIncomingValue(0)->getType(); + Type *PTy = P->getType(); + if (PTy != Ty0) { + assert(Ty0 == DestTy); + // In order to create the trunc, P must have the promoted type. + P->mutateType(Ty0); + Value *T = IRBuilder<>(ExitB, End).CreateTrunc(P, PTy); + // In order for the RAUW to work, the types of P and T must match. + P->mutateType(PTy); + P->replaceAllUsesWith(T); + // Final update of the P's type. + P->mutateType(Ty0); + cast<Instruction>(T)->setOperand(0, P); + } + } + + return true; +} + + +bool PolynomialMultiplyRecognize::findCycle(Value *Out, Value *In, + ValueSeq &Cycle) { + // Out = ..., In, ... + if (Out == In) + return true; + + auto *BB = cast<Instruction>(Out)->getParent(); + bool HadPhi = false; + + for (auto U : Out->users()) { + auto *I = dyn_cast<Instruction>(&*U); + if (I == nullptr || I->getParent() != BB) + continue; + // Make sure that there are no multi-iteration cycles, e.g. + // p1 = phi(p2) + // p2 = phi(p1) + // The cycle p1->p2->p1 would span two loop iterations. + // Check that there is only one phi in the cycle. + bool IsPhi = isa<PHINode>(I); + if (IsPhi && HadPhi) + return false; + HadPhi |= IsPhi; + if (Cycle.count(I)) + return false; + Cycle.insert(I); + if (findCycle(I, In, Cycle)) + break; + Cycle.remove(I); + } + return !Cycle.empty(); +} + + +void PolynomialMultiplyRecognize::classifyCycle(Instruction *DivI, + ValueSeq &Cycle, ValueSeq &Early, ValueSeq &Late) { + // All the values in the cycle that are between the phi node and the + // divider instruction will be classified as "early", all other values + // will be "late". + + bool IsE = true; + unsigned I, N = Cycle.size(); + for (I = 0; I < N; ++I) { + Value *V = Cycle[I]; + if (DivI == V) + IsE = false; + else if (!isa<PHINode>(V)) + continue; + // Stop if found either. + break; + } + // "I" is the index of either DivI or the phi node, whichever was first. + // "E" is "false" or "true" respectively. + ValueSeq &First = !IsE ? Early : Late; + for (unsigned J = 0; J < I; ++J) + First.insert(Cycle[J]); + + ValueSeq &Second = IsE ? Early : Late; + Second.insert(Cycle[I]); + for (++I; I < N; ++I) { + Value *V = Cycle[I]; + if (DivI == V || isa<PHINode>(V)) + break; + Second.insert(V); + } + + for (; I < N; ++I) + First.insert(Cycle[I]); +} + + +bool PolynomialMultiplyRecognize::classifyInst(Instruction *UseI, + ValueSeq &Early, ValueSeq &Late) { + // Select is an exception, since the condition value does not have to be + // classified in the same way as the true/false values. The true/false + // values do have to be both early or both late. + if (UseI->getOpcode() == Instruction::Select) { + Value *TV = UseI->getOperand(1), *FV = UseI->getOperand(2); + if (Early.count(TV) || Early.count(FV)) { + if (Late.count(TV) || Late.count(FV)) + return false; + Early.insert(UseI); + } else if (Late.count(TV) || Late.count(FV)) { + if (Early.count(TV) || Early.count(FV)) + return false; + Late.insert(UseI); + } + return true; + } + + // Not sure what would be the example of this, but the code below relies + // on having at least one operand. + if (UseI->getNumOperands() == 0) + return true; + + bool AE = true, AL = true; + for (auto &I : UseI->operands()) { + if (Early.count(&*I)) + AL = false; + else if (Late.count(&*I)) + AE = false; + } + // If the operands appear "all early" and "all late" at the same time, + // then it means that none of them are actually classified as either. + // This is harmless. + if (AE && AL) + return true; + // Conversely, if they are neither "all early" nor "all late", then + // we have a mixture of early and late operands that is not a known + // exception. + if (!AE && !AL) + return false; + + // Check that we have covered the two special cases. + assert(AE != AL); + + if (AE) + Early.insert(UseI); + else + Late.insert(UseI); + return true; +} + + +bool PolynomialMultiplyRecognize::commutesWithShift(Instruction *I) { + switch (I->getOpcode()) { + case Instruction::And: + case Instruction::Or: + case Instruction::Xor: + case Instruction::LShr: + case Instruction::Shl: + case Instruction::Select: + case Instruction::ICmp: + case Instruction::PHI: + break; + default: + return false; + } + return true; +} + + +bool PolynomialMultiplyRecognize::highBitsAreZero(Value *V, + unsigned IterCount) { + auto *T = dyn_cast<IntegerType>(V->getType()); + if (!T) + return false; + + unsigned BW = T->getBitWidth(); + APInt K0(BW, 0), K1(BW, 0); + computeKnownBits(V, K0, K1, DL); + return K0.countLeadingOnes() >= IterCount; +} + + +bool PolynomialMultiplyRecognize::keepsHighBitsZero(Value *V, + unsigned IterCount) { + // Assume that all inputs to the value have the high bits zero. + // Check if the value itself preserves the zeros in the high bits. + if (auto *C = dyn_cast<ConstantInt>(V)) + return C->getValue().countLeadingZeros() >= IterCount; + + if (auto *I = dyn_cast<Instruction>(V)) { + switch (I->getOpcode()) { + case Instruction::And: + case Instruction::Or: + case Instruction::Xor: + case Instruction::LShr: + case Instruction::Select: + case Instruction::ICmp: + case Instruction::PHI: + case Instruction::ZExt: + return true; + } + } + + return false; +} + + +bool PolynomialMultiplyRecognize::isOperandShifted(Instruction *I, Value *Op) { + unsigned Opc = I->getOpcode(); + if (Opc == Instruction::Shl || Opc == Instruction::LShr) + return Op != I->getOperand(1); + return true; +} + + +bool PolynomialMultiplyRecognize::convertShiftsToLeft(BasicBlock *LoopB, + BasicBlock *ExitB, unsigned IterCount) { + Value *CIV = getCountIV(LoopB); + if (CIV == nullptr) + return false; + auto *CIVTy = dyn_cast<IntegerType>(CIV->getType()); + if (CIVTy == nullptr) + return false; + + ValueSeq RShifts; + ValueSeq Early, Late, Cycled; + + // Find all value cycles that contain logical right shifts by 1. + for (Instruction &I : *LoopB) { + using namespace PatternMatch; + Value *V = nullptr; + if (!match(&I, m_LShr(m_Value(V), m_One()))) + continue; + ValueSeq C; + if (!findCycle(&I, V, C)) + continue; + + // Found a cycle. + C.insert(&I); + classifyCycle(&I, C, Early, Late); + Cycled.insert(C.begin(), C.end()); + RShifts.insert(&I); + } + + // Find the set of all values affected by the shift cycles, i.e. all + // cycled values, and (recursively) all their users. + ValueSeq Users(Cycled.begin(), Cycled.end()); + for (unsigned i = 0; i < Users.size(); ++i) { + Value *V = Users[i]; + if (!isa<IntegerType>(V->getType())) + return false; + auto *R = cast<Instruction>(V); + // If the instruction does not commute with shifts, the loop cannot + // be unshifted. + if (!commutesWithShift(R)) + return false; + for (auto I = R->user_begin(), E = R->user_end(); I != E; ++I) { + auto *T = cast<Instruction>(*I); + // Skip users from outside of the loop. They will be handled later. + // Also, skip the right-shifts and phi nodes, since they mix early + // and late values. + if (T->getParent() != LoopB || RShifts.count(T) || isa<PHINode>(T)) + continue; + + Users.insert(T); + if (!classifyInst(T, Early, Late)) + return false; + } + } + + if (Users.size() == 0) + return false; + + // Verify that high bits remain zero. + ValueSeq Internal(Users.begin(), Users.end()); + ValueSeq Inputs; + for (unsigned i = 0; i < Internal.size(); ++i) { + auto *R = dyn_cast<Instruction>(Internal[i]); + if (!R) + continue; + for (Value *Op : R->operands()) { + auto *T = dyn_cast<Instruction>(Op); + if (T && T->getParent() != LoopB) + Inputs.insert(Op); + else + Internal.insert(Op); + } + } + for (Value *V : Inputs) + if (!highBitsAreZero(V, IterCount)) + return false; + for (Value *V : Internal) + if (!keepsHighBitsZero(V, IterCount)) + return false; + + // Finally, the work can be done. Unshift each user. + IRBuilder<> IRB(LoopB); + std::map<Value*,Value*> ShiftMap; + typedef std::map<std::pair<Value*,Type*>,Value*> CastMapType; + CastMapType CastMap; + + auto upcast = [] (CastMapType &CM, IRBuilder<> &IRB, Value *V, + IntegerType *Ty) -> Value* { + auto H = CM.find(std::make_pair(V, Ty)); + if (H != CM.end()) + return H->second; + Value *CV = IRB.CreateIntCast(V, Ty, false); + CM.insert(std::make_pair(std::make_pair(V, Ty), CV)); + return CV; + }; + + for (auto I = LoopB->begin(), E = LoopB->end(); I != E; ++I) { + if (isa<PHINode>(I) || !Users.count(&*I)) + continue; + using namespace PatternMatch; + // Match lshr x, 1. + Value *V = nullptr; + if (match(&*I, m_LShr(m_Value(V), m_One()))) { + replaceAllUsesOfWithIn(&*I, V, LoopB); + continue; + } + // For each non-cycled operand, replace it with the corresponding + // value shifted left. + for (auto &J : I->operands()) { + Value *Op = J.get(); + if (!isOperandShifted(&*I, Op)) + continue; + if (Users.count(Op)) + continue; + // Skip shifting zeros. + if (isa<ConstantInt>(Op) && cast<ConstantInt>(Op)->isZero()) + continue; + // Check if we have already generated a shift for this value. + auto F = ShiftMap.find(Op); + Value *W = (F != ShiftMap.end()) ? F->second : nullptr; + if (W == nullptr) { + IRB.SetInsertPoint(&*I); + // First, the shift amount will be CIV or CIV+1, depending on + // whether the value is early or late. Instead of creating CIV+1, + // do a single shift of the value. + Value *ShAmt = CIV, *ShVal = Op; + auto *VTy = cast<IntegerType>(ShVal->getType()); + auto *ATy = cast<IntegerType>(ShAmt->getType()); + if (Late.count(&*I)) + ShVal = IRB.CreateShl(Op, ConstantInt::get(VTy, 1)); + // Second, the types of the shifted value and the shift amount + // must match. + if (VTy != ATy) { + if (VTy->getBitWidth() < ATy->getBitWidth()) + ShVal = upcast(CastMap, IRB, ShVal, ATy); + else + ShAmt = upcast(CastMap, IRB, ShAmt, VTy); + } + // Ready to generate the shift and memoize it. + W = IRB.CreateShl(ShVal, ShAmt); + ShiftMap.insert(std::make_pair(Op, W)); + } + I->replaceUsesOfWith(Op, W); + } + } + + // Update the users outside of the loop to account for having left + // shifts. They would normally be shifted right in the loop, so shift + // them right after the loop exit. + // Take advantage of the loop-closed SSA form, which has all the post- + // loop values in phi nodes. + IRB.SetInsertPoint(ExitB, ExitB->getFirstInsertionPt()); + for (auto P = ExitB->begin(), Q = ExitB->end(); P != Q; ++P) { + if (!isa<PHINode>(P)) + break; + auto *PN = cast<PHINode>(P); + Value *U = PN->getIncomingValueForBlock(LoopB); + if (!Users.count(U)) + continue; + Value *S = IRB.CreateLShr(PN, ConstantInt::get(PN->getType(), IterCount)); + PN->replaceAllUsesWith(S); + // The above RAUW will create + // S = lshr S, IterCount + // so we need to fix it back into + // S = lshr PN, IterCount + cast<User>(S)->replaceUsesOfWith(S, PN); + } + + return true; +} + + +void PolynomialMultiplyRecognize::cleanupLoopBody(BasicBlock *LoopB) { + for (auto &I : *LoopB) + if (Value *SV = SimplifyInstruction(&I, DL, &TLI, &DT)) + I.replaceAllUsesWith(SV); + + for (auto I = LoopB->begin(), N = I; I != LoopB->end(); I = N) { + N = std::next(I); + RecursivelyDeleteTriviallyDeadInstructions(&*I, &TLI); + } +} + + +unsigned PolynomialMultiplyRecognize::getInverseMxN(unsigned QP) { + // Arrays of coefficients of Q and the inverse, C. + // Q[i] = coefficient at x^i. + std::array<char,32> Q, C; + + for (unsigned i = 0; i < 32; ++i) { + Q[i] = QP & 1; + QP >>= 1; + } + assert(Q[0] == 1); + + // Find C, such that + // (Q[n]*x^n + ... + Q[1]*x + Q[0]) * (C[n]*x^n + ... + C[1]*x + C[0]) = 1 + // + // For it to have a solution, Q[0] must be 1. Since this is Z2[x], the + // operations * and + are & and ^ respectively. + // + // Find C[i] recursively, by comparing i-th coefficient in the product + // with 0 (or 1 for i=0). + // + // C[0] = 1, since C[0] = Q[0], and Q[0] = 1. + C[0] = 1; + for (unsigned i = 1; i < 32; ++i) { + // Solve for C[i] in: + // C[0]Q[i] ^ C[1]Q[i-1] ^ ... ^ C[i-1]Q[1] ^ C[i]Q[0] = 0 + // This is equivalent to + // C[0]Q[i] ^ C[1]Q[i-1] ^ ... ^ C[i-1]Q[1] ^ C[i] = 0 + // which is + // C[0]Q[i] ^ C[1]Q[i-1] ^ ... ^ C[i-1]Q[1] = C[i] + unsigned T = 0; + for (unsigned j = 0; j < i; ++j) + T = T ^ (C[j] & Q[i-j]); + C[i] = T; + } + + unsigned QV = 0; + for (unsigned i = 0; i < 32; ++i) + if (C[i]) + QV |= (1 << i); + + return QV; +} + + +Value *PolynomialMultiplyRecognize::generate(BasicBlock::iterator At, + ParsedValues &PV) { + IRBuilder<> B(&*At); + Module *M = At->getParent()->getParent()->getParent(); + Value *PMF = Intrinsic::getDeclaration(M, Intrinsic::hexagon_M4_pmpyw); + + Value *P = PV.P, *Q = PV.Q, *P0 = P; + unsigned IC = PV.IterCount; + + if (PV.M != nullptr) + P0 = P = B.CreateXor(P, PV.M); + + // Create a bit mask to clear the high bits beyond IterCount. + auto *BMI = ConstantInt::get(P->getType(), APInt::getLowBitsSet(32, IC)); + + if (PV.IterCount != 32) + P = B.CreateAnd(P, BMI); + + if (PV.Inv) { + auto *QI = dyn_cast<ConstantInt>(PV.Q); + assert(QI && QI->getBitWidth() <= 32); + + // Again, clearing bits beyond IterCount. + unsigned M = (1 << PV.IterCount) - 1; + unsigned Tmp = (QI->getZExtValue() | 1) & M; + unsigned QV = getInverseMxN(Tmp) & M; + auto *QVI = ConstantInt::get(QI->getType(), QV); + P = B.CreateCall(PMF, {P, QVI}); + P = B.CreateTrunc(P, QI->getType()); + if (IC != 32) + P = B.CreateAnd(P, BMI); + } + + Value *R = B.CreateCall(PMF, {P, Q}); + + if (PV.M != nullptr) + R = B.CreateXor(R, B.CreateIntCast(P0, R->getType(), false)); + + return R; +} + + +void PolynomialMultiplyRecognize::setupSimplifier() { + Simp.addRule( + // Sink zext past bitwise operations. + [](Instruction *I, LLVMContext &Ctx) -> Value* { + if (I->getOpcode() != Instruction::ZExt) + return nullptr; + Instruction *T = dyn_cast<Instruction>(I->getOperand(0)); + if (!T) + return nullptr; + switch (T->getOpcode()) { + case Instruction::And: + case Instruction::Or: + case Instruction::Xor: + break; + default: + return nullptr; + } + IRBuilder<> B(Ctx); + return B.CreateBinOp(cast<BinaryOperator>(T)->getOpcode(), + B.CreateZExt(T->getOperand(0), I->getType()), + B.CreateZExt(T->getOperand(1), I->getType())); + }); + Simp.addRule( + // (xor (and x a) (and y a)) -> (and (xor x y) a) + [](Instruction *I, LLVMContext &Ctx) -> Value* { + if (I->getOpcode() != Instruction::Xor) + return nullptr; + Instruction *And0 = dyn_cast<Instruction>(I->getOperand(0)); + Instruction *And1 = dyn_cast<Instruction>(I->getOperand(1)); + if (!And0 || !And1) + return nullptr; + if (And0->getOpcode() != Instruction::And || + And1->getOpcode() != Instruction::And) + return nullptr; + if (And0->getOperand(1) != And1->getOperand(1)) + return nullptr; + IRBuilder<> B(Ctx); + return B.CreateAnd(B.CreateXor(And0->getOperand(0), And1->getOperand(0)), + And0->getOperand(1)); + }); + Simp.addRule( + // (Op (select c x y) z) -> (select c (Op x z) (Op y z)) + // (Op x (select c y z)) -> (select c (Op x y) (Op x z)) + [](Instruction *I, LLVMContext &Ctx) -> Value* { + BinaryOperator *BO = dyn_cast<BinaryOperator>(I); + if (!BO) + return nullptr; + Instruction::BinaryOps Op = BO->getOpcode(); + if (SelectInst *Sel = dyn_cast<SelectInst>(BO->getOperand(0))) { + IRBuilder<> B(Ctx); + Value *X = Sel->getTrueValue(), *Y = Sel->getFalseValue(); + Value *Z = BO->getOperand(1); + return B.CreateSelect(Sel->getCondition(), + B.CreateBinOp(Op, X, Z), + B.CreateBinOp(Op, Y, Z)); + } + if (SelectInst *Sel = dyn_cast<SelectInst>(BO->getOperand(1))) { + IRBuilder<> B(Ctx); + Value *X = BO->getOperand(0); + Value *Y = Sel->getTrueValue(), *Z = Sel->getFalseValue(); + return B.CreateSelect(Sel->getCondition(), + B.CreateBinOp(Op, X, Y), + B.CreateBinOp(Op, X, Z)); + } + return nullptr; + }); + Simp.addRule( + // (select c (select c x y) z) -> (select c x z) + // (select c x (select c y z)) -> (select c x z) + [](Instruction *I, LLVMContext &Ctx) -> Value* { + SelectInst *Sel = dyn_cast<SelectInst>(I); + if (!Sel) + return nullptr; + IRBuilder<> B(Ctx); + Value *C = Sel->getCondition(); + if (SelectInst *Sel0 = dyn_cast<SelectInst>(Sel->getTrueValue())) { + if (Sel0->getCondition() == C) + return B.CreateSelect(C, Sel0->getTrueValue(), Sel->getFalseValue()); + } + if (SelectInst *Sel1 = dyn_cast<SelectInst>(Sel->getFalseValue())) { + if (Sel1->getCondition() == C) + return B.CreateSelect(C, Sel->getTrueValue(), Sel1->getFalseValue()); + } + return nullptr; + }); + Simp.addRule( + // (or (lshr x 1) 0x800.0) -> (xor (lshr x 1) 0x800.0) + [](Instruction *I, LLVMContext &Ctx) -> Value* { + if (I->getOpcode() != Instruction::Or) + return nullptr; + Instruction *LShr = dyn_cast<Instruction>(I->getOperand(0)); + if (!LShr || LShr->getOpcode() != Instruction::LShr) + return nullptr; + ConstantInt *One = dyn_cast<ConstantInt>(LShr->getOperand(1)); + if (!One || One->getZExtValue() != 1) + return nullptr; + ConstantInt *Msb = dyn_cast<ConstantInt>(I->getOperand(1)); + if (!Msb || Msb->getZExtValue() != Msb->getType()->getSignBit()) + return nullptr; + return IRBuilder<>(Ctx).CreateXor(LShr, Msb); + }); + Simp.addRule( + // (lshr (BitOp x y) c) -> (BitOp (lshr x c) (lshr y c)) + [](Instruction *I, LLVMContext &Ctx) -> Value* { + if (I->getOpcode() != Instruction::LShr) + return nullptr; + BinaryOperator *BitOp = dyn_cast<BinaryOperator>(I->getOperand(0)); + if (!BitOp) + return nullptr; + switch (BitOp->getOpcode()) { + case Instruction::And: + case Instruction::Or: + case Instruction::Xor: + break; + default: + return nullptr; + } + IRBuilder<> B(Ctx); + Value *S = I->getOperand(1); + return B.CreateBinOp(BitOp->getOpcode(), + B.CreateLShr(BitOp->getOperand(0), S), + B.CreateLShr(BitOp->getOperand(1), S)); + }); + Simp.addRule( + // (BitOp1 (BitOp2 x a) b) -> (BitOp2 x (BitOp1 a b)) + [](Instruction *I, LLVMContext &Ctx) -> Value* { + auto IsBitOp = [](unsigned Op) -> bool { + switch (Op) { + case Instruction::And: + case Instruction::Or: + case Instruction::Xor: + return true; + } + return false; + }; + BinaryOperator *BitOp1 = dyn_cast<BinaryOperator>(I); + if (!BitOp1 || !IsBitOp(BitOp1->getOpcode())) + return nullptr; + BinaryOperator *BitOp2 = dyn_cast<BinaryOperator>(BitOp1->getOperand(0)); + if (!BitOp2 || !IsBitOp(BitOp2->getOpcode())) + return nullptr; + ConstantInt *CA = dyn_cast<ConstantInt>(BitOp2->getOperand(1)); + ConstantInt *CB = dyn_cast<ConstantInt>(BitOp1->getOperand(1)); + if (!CA || !CB) + return nullptr; + IRBuilder<> B(Ctx); + Value *X = BitOp2->getOperand(0); + return B.CreateBinOp(BitOp2->getOpcode(), X, + B.CreateBinOp(BitOp1->getOpcode(), CA, CB)); + }); +} + + +bool PolynomialMultiplyRecognize::recognize() { + DEBUG(dbgs() << "Starting PolynomialMultiplyRecognize on loop\n" + << *CurLoop << '\n'); + // Restrictions: + // - The loop must consist of a single block. + // - The iteration count must be known at compile-time. + // - The loop must have an induction variable starting from 0, and + // incremented in each iteration of the loop. + BasicBlock *LoopB = CurLoop->getHeader(); + DEBUG(dbgs() << "Loop header:\n" << *LoopB); + + if (LoopB != CurLoop->getLoopLatch()) + return false; + BasicBlock *ExitB = CurLoop->getExitBlock(); + if (ExitB == nullptr) + return false; + BasicBlock *EntryB = CurLoop->getLoopPreheader(); + if (EntryB == nullptr) + return false; + + unsigned IterCount = 0; + const SCEV *CT = SE.getBackedgeTakenCount(CurLoop); + if (isa<SCEVCouldNotCompute>(CT)) + return false; + if (auto *CV = dyn_cast<SCEVConstant>(CT)) + IterCount = CV->getValue()->getZExtValue() + 1; + + Value *CIV = getCountIV(LoopB); + ParsedValues PV; + PV.IterCount = IterCount; + DEBUG(dbgs() << "Loop IV: " << *CIV << "\nIterCount: " << IterCount << '\n'); + + setupSimplifier(); + + // Perform a preliminary scan of select instructions to see if any of them + // looks like a generator of the polynomial multiply steps. Assume that a + // loop can only contain a single transformable operation, so stop the + // traversal after the first reasonable candidate was found. + // XXX: Currently this approach can modify the loop before being 100% sure + // that the transformation can be carried out. + bool FoundPreScan = false; + for (Instruction &In : *LoopB) { + SelectInst *SI = dyn_cast<SelectInst>(&In); + if (!SI) + continue; + + Simplifier::Context C(SI); + Value *T = Simp.simplify(C); + SelectInst *SelI = (T && isa<SelectInst>(T)) ? cast<SelectInst>(T) : SI; + DEBUG(dbgs() << "scanSelect(pre-scan): " << PE(C, SelI) << '\n'); + if (scanSelect(SelI, LoopB, EntryB, CIV, PV, true)) { + FoundPreScan = true; + if (SelI != SI) { + Value *NewSel = C.materialize(LoopB, SI->getIterator()); + SI->replaceAllUsesWith(NewSel); + RecursivelyDeleteTriviallyDeadInstructions(SI, &TLI); + } + break; + } + } + + if (!FoundPreScan) { + DEBUG(dbgs() << "Have not found candidates for pmpy\n"); + return false; + } + + if (!PV.Left) { + // The right shift version actually only returns the higher bits of + // the result (each iteration discards the LSB). If we want to convert it + // to a left-shifting loop, the working data type must be at least as + // wide as the target's pmpy instruction. + if (!promoteTypes(LoopB, ExitB)) + return false; + convertShiftsToLeft(LoopB, ExitB, IterCount); + cleanupLoopBody(LoopB); + } + + // Scan the loop again, find the generating select instruction. + bool FoundScan = false; + for (Instruction &In : *LoopB) { + SelectInst *SelI = dyn_cast<SelectInst>(&In); + if (!SelI) + continue; + DEBUG(dbgs() << "scanSelect: " << *SelI << '\n'); + FoundScan = scanSelect(SelI, LoopB, EntryB, CIV, PV, false); + if (FoundScan) + break; + } + assert(FoundScan); + + DEBUG({ + StringRef PP = (PV.M ? "(P+M)" : "P"); + if (!PV.Inv) + dbgs() << "Found pmpy idiom: R = " << PP << ".Q\n"; + else + dbgs() << "Found inverse pmpy idiom: R = (" << PP << "/Q).Q) + " + << PP << "\n"; + dbgs() << " Res:" << *PV.Res << "\n P:" << *PV.P << "\n"; + if (PV.M) + dbgs() << " M:" << *PV.M << "\n"; + dbgs() << " Q:" << *PV.Q << "\n"; + dbgs() << " Iteration count:" << PV.IterCount << "\n"; + }); + + BasicBlock::iterator At(EntryB->getTerminator()); + Value *PM = generate(At, PV); + if (PM == nullptr) + return false; + + if (PM->getType() != PV.Res->getType()) + PM = IRBuilder<>(&*At).CreateIntCast(PM, PV.Res->getType(), false); + + PV.Res->replaceAllUsesWith(PM); + PV.Res->eraseFromParent(); + return true; +} + + +unsigned HexagonLoopIdiomRecognize::getStoreSizeInBytes(StoreInst *SI) { + uint64_t SizeInBits = DL->getTypeSizeInBits(SI->getValueOperand()->getType()); + assert(((SizeInBits & 7) || (SizeInBits >> 32) == 0) && + "Don't overflow unsigned."); + return (unsigned)SizeInBits >> 3; +} + + +int HexagonLoopIdiomRecognize::getSCEVStride(const SCEVAddRecExpr *S) { + if (const SCEVConstant *SC = dyn_cast<SCEVConstant>(S->getOperand(1))) + return SC->getAPInt().getSExtValue(); + return 0; +} + + +bool HexagonLoopIdiomRecognize::isLegalStore(Loop *CurLoop, StoreInst *SI) { + // Allow volatile stores if HexagonVolatileMemcpy is enabled. + if (!(SI->isVolatile() && HexagonVolatileMemcpy) && !SI->isSimple()) + return false; + + Value *StoredVal = SI->getValueOperand(); + Value *StorePtr = SI->getPointerOperand(); + + // Reject stores that are so large that they overflow an unsigned. + uint64_t SizeInBits = DL->getTypeSizeInBits(StoredVal->getType()); + if ((SizeInBits & 7) || (SizeInBits >> 32) != 0) + return false; + + // See if the pointer expression is an AddRec like {base,+,1} on the current + // loop, which indicates a strided store. If we have something else, it's a + // random store we can't handle. + auto *StoreEv = dyn_cast<SCEVAddRecExpr>(SE->getSCEV(StorePtr)); + if (!StoreEv || StoreEv->getLoop() != CurLoop || !StoreEv->isAffine()) + return false; + + // Check to see if the stride matches the size of the store. If so, then we + // know that every byte is touched in the loop. + int Stride = getSCEVStride(StoreEv); + if (Stride == 0) + return false; + unsigned StoreSize = getStoreSizeInBytes(SI); + if (StoreSize != unsigned(std::abs(Stride))) + return false; + + // The store must be feeding a non-volatile load. + LoadInst *LI = dyn_cast<LoadInst>(SI->getValueOperand()); + if (!LI || !LI->isSimple()) + return false; + + // See if the pointer expression is an AddRec like {base,+,1} on the current + // loop, which indicates a strided load. If we have something else, it's a + // random load we can't handle. + Value *LoadPtr = LI->getPointerOperand(); + auto *LoadEv = dyn_cast<SCEVAddRecExpr>(SE->getSCEV(LoadPtr)); + if (!LoadEv || LoadEv->getLoop() != CurLoop || !LoadEv->isAffine()) + return false; + + // The store and load must share the same stride. + if (StoreEv->getOperand(1) != LoadEv->getOperand(1)) + return false; + + // Success. This store can be converted into a memcpy. + return true; +} + + +/// mayLoopAccessLocation - Return true if the specified loop might access the +/// specified pointer location, which is a loop-strided access. The 'Access' +/// argument specifies what the verboten forms of access are (read or write). +static bool +mayLoopAccessLocation(Value *Ptr, ModRefInfo Access, Loop *L, + const SCEV *BECount, unsigned StoreSize, + AliasAnalysis &AA, + SmallPtrSetImpl<Instruction *> &Ignored) { + // Get the location that may be stored across the loop. Since the access + // is strided positively through memory, we say that the modified location + // starts at the pointer and has infinite size. + uint64_t AccessSize = MemoryLocation::UnknownSize; + + // If the loop iterates a fixed number of times, we can refine the access + // size to be exactly the size of the memset, which is (BECount+1)*StoreSize + if (const SCEVConstant *BECst = dyn_cast<SCEVConstant>(BECount)) + AccessSize = (BECst->getValue()->getZExtValue() + 1) * StoreSize; + + // TODO: For this to be really effective, we have to dive into the pointer + // operand in the store. Store to &A[i] of 100 will always return may alias + // with store of &A[100], we need to StoreLoc to be "A" with size of 100, + // which will then no-alias a store to &A[100]. + MemoryLocation StoreLoc(Ptr, AccessSize); + + for (auto *B : L->blocks()) + for (auto &I : *B) + if (Ignored.count(&I) == 0 && (AA.getModRefInfo(&I, StoreLoc) & Access)) + return true; + + return false; +} + + +void HexagonLoopIdiomRecognize::collectStores(Loop *CurLoop, BasicBlock *BB, + SmallVectorImpl<StoreInst*> &Stores) { + Stores.clear(); + for (Instruction &I : *BB) + if (StoreInst *SI = dyn_cast<StoreInst>(&I)) + if (isLegalStore(CurLoop, SI)) + Stores.push_back(SI); +} + + +bool HexagonLoopIdiomRecognize::processCopyingStore(Loop *CurLoop, + StoreInst *SI, const SCEV *BECount) { + assert((SI->isSimple() || (SI->isVolatile() && HexagonVolatileMemcpy)) && + "Expected only non-volatile stores, or Hexagon-specific memcpy" + "to volatile destination."); + + Value *StorePtr = SI->getPointerOperand(); + auto *StoreEv = cast<SCEVAddRecExpr>(SE->getSCEV(StorePtr)); + unsigned Stride = getSCEVStride(StoreEv); + unsigned StoreSize = getStoreSizeInBytes(SI); + if (Stride != StoreSize) + return false; + + // See if the pointer expression is an AddRec like {base,+,1} on the current + // loop, which indicates a strided load. If we have something else, it's a + // random load we can't handle. + LoadInst *LI = dyn_cast<LoadInst>(SI->getValueOperand()); + auto *LoadEv = cast<SCEVAddRecExpr>(SE->getSCEV(LI->getPointerOperand())); + + // The trip count of the loop and the base pointer of the addrec SCEV is + // guaranteed to be loop invariant, which means that it should dominate the + // header. This allows us to insert code for it in the preheader. + BasicBlock *Preheader = CurLoop->getLoopPreheader(); + Instruction *ExpPt = Preheader->getTerminator(); + IRBuilder<> Builder(ExpPt); + SCEVExpander Expander(*SE, *DL, "hexagon-loop-idiom"); + + Type *IntPtrTy = Builder.getIntPtrTy(*DL, SI->getPointerAddressSpace()); + + // Okay, we have a strided store "p[i]" of a loaded value. We can turn + // this into a memcpy/memmove in the loop preheader now if we want. However, + // this would be unsafe to do if there is anything else in the loop that may + // read or write the memory region we're storing to. For memcpy, this + // includes the load that feeds the stores. Check for an alias by generating + // the base address and checking everything. + Value *StoreBasePtr = Expander.expandCodeFor(StoreEv->getStart(), + Builder.getInt8PtrTy(SI->getPointerAddressSpace()), ExpPt); + Value *LoadBasePtr = nullptr; + + bool Overlap = false; + bool DestVolatile = SI->isVolatile(); + Type *BECountTy = BECount->getType(); + + if (DestVolatile) { + // The trip count must fit in i32, since it is the type of the "num_words" + // argument to hexagon_memcpy_forward_vp4cp4n2. + if (StoreSize != 4 || DL->getTypeSizeInBits(BECountTy) > 32) { +CleanupAndExit: + // If we generated new code for the base pointer, clean up. + Expander.clear(); + if (StoreBasePtr && (LoadBasePtr != StoreBasePtr)) { + RecursivelyDeleteTriviallyDeadInstructions(StoreBasePtr, TLI); + StoreBasePtr = nullptr; + } + if (LoadBasePtr) { + RecursivelyDeleteTriviallyDeadInstructions(LoadBasePtr, TLI); + LoadBasePtr = nullptr; + } + return false; + } + } + + SmallPtrSet<Instruction*, 2> Ignore1; + Ignore1.insert(SI); + if (mayLoopAccessLocation(StoreBasePtr, MRI_ModRef, CurLoop, BECount, + StoreSize, *AA, Ignore1)) { + // Check if the load is the offending instruction. + Ignore1.insert(LI); + if (mayLoopAccessLocation(StoreBasePtr, MRI_ModRef, CurLoop, BECount, + StoreSize, *AA, Ignore1)) { + // Still bad. Nothing we can do. + goto CleanupAndExit; + } + // It worked with the load ignored. + Overlap = true; + } + + if (!Overlap) { + if (DisableMemcpyIdiom || !HasMemcpy) + goto CleanupAndExit; + } else { + // Don't generate memmove if this function will be inlined. This is + // because the caller will undergo this transformation after inlining. + Function *Func = CurLoop->getHeader()->getParent(); + if (Func->hasFnAttribute(Attribute::AlwaysInline)) + goto CleanupAndExit; + + // In case of a memmove, the call to memmove will be executed instead + // of the loop, so we need to make sure that there is nothing else in + // the loop than the load, store and instructions that these two depend + // on. + SmallVector<Instruction*,2> Insts; + Insts.push_back(SI); + Insts.push_back(LI); + if (!coverLoop(CurLoop, Insts)) + goto CleanupAndExit; + + if (DisableMemmoveIdiom || !HasMemmove) + goto CleanupAndExit; + bool IsNested = CurLoop->getParentLoop() != 0; + if (IsNested && OnlyNonNestedMemmove) + goto CleanupAndExit; + } + + // For a memcpy, we have to make sure that the input array is not being + // mutated by the loop. + LoadBasePtr = Expander.expandCodeFor(LoadEv->getStart(), + Builder.getInt8PtrTy(LI->getPointerAddressSpace()), ExpPt); + + SmallPtrSet<Instruction*, 2> Ignore2; + Ignore2.insert(SI); + if (mayLoopAccessLocation(LoadBasePtr, MRI_Mod, CurLoop, BECount, StoreSize, + *AA, Ignore2)) + goto CleanupAndExit; + + // Check the stride. + bool StridePos = getSCEVStride(LoadEv) >= 0; + + // Currently, the volatile memcpy only emulates traversing memory forward. + if (!StridePos && DestVolatile) + goto CleanupAndExit; + + bool RuntimeCheck = (Overlap || DestVolatile); + + BasicBlock *ExitB; + if (RuntimeCheck) { + // The runtime check needs a single exit block. + SmallVector<BasicBlock*, 8> ExitBlocks; + CurLoop->getUniqueExitBlocks(ExitBlocks); + if (ExitBlocks.size() != 1) + goto CleanupAndExit; + ExitB = ExitBlocks[0]; + } + + // The # stored bytes is (BECount+1)*Size. Expand the trip count out to + // pointer size if it isn't already. + LLVMContext &Ctx = SI->getContext(); + BECount = SE->getTruncateOrZeroExtend(BECount, IntPtrTy); + unsigned Alignment = std::min(SI->getAlignment(), LI->getAlignment()); + DebugLoc DLoc = SI->getDebugLoc(); + + const SCEV *NumBytesS = + SE->getAddExpr(BECount, SE->getOne(IntPtrTy), SCEV::FlagNUW); + if (StoreSize != 1) + NumBytesS = SE->getMulExpr(NumBytesS, SE->getConstant(IntPtrTy, StoreSize), + SCEV::FlagNUW); + Value *NumBytes = Expander.expandCodeFor(NumBytesS, IntPtrTy, ExpPt); + if (Instruction *In = dyn_cast<Instruction>(NumBytes)) + if (Value *Simp = SimplifyInstruction(In, *DL, TLI, DT)) + NumBytes = Simp; + + CallInst *NewCall; + + if (RuntimeCheck) { + unsigned Threshold = RuntimeMemSizeThreshold; + if (ConstantInt *CI = dyn_cast<ConstantInt>(NumBytes)) { + uint64_t C = CI->getZExtValue(); + if (Threshold != 0 && C < Threshold) + goto CleanupAndExit; + if (C < CompileTimeMemSizeThreshold) + goto CleanupAndExit; + } + + BasicBlock *Header = CurLoop->getHeader(); + Function *Func = Header->getParent(); + Loop *ParentL = LF->getLoopFor(Preheader); + StringRef HeaderName = Header->getName(); + + // Create a new (empty) preheader, and update the PHI nodes in the + // header to use the new preheader. + BasicBlock *NewPreheader = BasicBlock::Create(Ctx, HeaderName+".rtli.ph", + Func, Header); + if (ParentL) + ParentL->addBasicBlockToLoop(NewPreheader, *LF); + IRBuilder<>(NewPreheader).CreateBr(Header); + for (auto &In : *Header) { + PHINode *PN = dyn_cast<PHINode>(&In); + if (!PN) + break; + int bx = PN->getBasicBlockIndex(Preheader); + if (bx >= 0) + PN->setIncomingBlock(bx, NewPreheader); + } + DT->addNewBlock(NewPreheader, Preheader); + DT->changeImmediateDominator(Header, NewPreheader); + + // Check for safe conditions to execute memmove. + // If stride is positive, copying things from higher to lower addresses + // is equivalent to memmove. For negative stride, it's the other way + // around. Copying forward in memory with positive stride may not be + // same as memmove since we may be copying values that we just stored + // in some previous iteration. + Value *LA = Builder.CreatePtrToInt(LoadBasePtr, IntPtrTy); + Value *SA = Builder.CreatePtrToInt(StoreBasePtr, IntPtrTy); + Value *LowA = StridePos ? SA : LA; + Value *HighA = StridePos ? LA : SA; + Value *CmpA = Builder.CreateICmpULT(LowA, HighA); + Value *Cond = CmpA; + + // Check for distance between pointers. + Value *Dist = Builder.CreateSub(HighA, LowA); + Value *CmpD = Builder.CreateICmpSLT(NumBytes, Dist); + Value *CmpEither = Builder.CreateOr(Cond, CmpD); + Cond = CmpEither; + + if (Threshold != 0) { + Type *Ty = NumBytes->getType(); + Value *Thr = ConstantInt::get(Ty, Threshold); + Value *CmpB = Builder.CreateICmpULT(Thr, NumBytes); + Value *CmpBoth = Builder.CreateAnd(Cond, CmpB); + Cond = CmpBoth; + } + BasicBlock *MemmoveB = BasicBlock::Create(Ctx, Header->getName()+".rtli", + Func, NewPreheader); + if (ParentL) + ParentL->addBasicBlockToLoop(MemmoveB, *LF); + Instruction *OldT = Preheader->getTerminator(); + Builder.CreateCondBr(Cond, MemmoveB, NewPreheader); + OldT->eraseFromParent(); + Preheader->setName(Preheader->getName()+".old"); + DT->addNewBlock(MemmoveB, Preheader); + // Find the new immediate dominator of the exit block. + BasicBlock *ExitD = Preheader; + for (auto PI = pred_begin(ExitB), PE = pred_end(ExitB); PI != PE; ++PI) { + BasicBlock *PB = *PI; + ExitD = DT->findNearestCommonDominator(ExitD, PB); + if (!ExitD) + break; + } + // If the prior immediate dominator of ExitB was dominated by the + // old preheader, then the old preheader becomes the new immediate + // dominator. Otherwise don't change anything (because the newly + // added blocks are dominated by the old preheader). + if (ExitD && DT->dominates(Preheader, ExitD)) { + DomTreeNode *BN = DT->getNode(ExitB); + DomTreeNode *DN = DT->getNode(ExitD); + BN->setIDom(DN); + } + + // Add a call to memmove to the conditional block. + IRBuilder<> CondBuilder(MemmoveB); + CondBuilder.CreateBr(ExitB); + CondBuilder.SetInsertPoint(MemmoveB->getTerminator()); + + if (DestVolatile) { + Type *Int32Ty = Type::getInt32Ty(Ctx); + Type *Int32PtrTy = Type::getInt32PtrTy(Ctx); + Type *VoidTy = Type::getVoidTy(Ctx); + Module *M = Func->getParent(); + Constant *CF = M->getOrInsertFunction(HexagonVolatileMemcpyName, VoidTy, + Int32PtrTy, Int32PtrTy, Int32Ty); + Function *Fn = cast<Function>(CF); + Fn->setLinkage(Function::ExternalLinkage); + + const SCEV *OneS = SE->getConstant(Int32Ty, 1); + const SCEV *BECount32 = SE->getTruncateOrZeroExtend(BECount, Int32Ty); + const SCEV *NumWordsS = SE->getAddExpr(BECount32, OneS, SCEV::FlagNUW); + Value *NumWords = Expander.expandCodeFor(NumWordsS, Int32Ty, + MemmoveB->getTerminator()); + if (Instruction *In = dyn_cast<Instruction>(NumWords)) + if (Value *Simp = SimplifyInstruction(In, *DL, TLI, DT)) + NumWords = Simp; + + Value *Op0 = (StoreBasePtr->getType() == Int32PtrTy) + ? StoreBasePtr + : CondBuilder.CreateBitCast(StoreBasePtr, Int32PtrTy); + Value *Op1 = (LoadBasePtr->getType() == Int32PtrTy) + ? LoadBasePtr + : CondBuilder.CreateBitCast(LoadBasePtr, Int32PtrTy); + NewCall = CondBuilder.CreateCall(Fn, {Op0, Op1, NumWords}); + } else { + NewCall = CondBuilder.CreateMemMove(StoreBasePtr, LoadBasePtr, + NumBytes, Alignment); + } + } else { + NewCall = Builder.CreateMemCpy(StoreBasePtr, LoadBasePtr, + NumBytes, Alignment); + // Okay, the memcpy has been formed. Zap the original store and + // anything that feeds into it. + RecursivelyDeleteTriviallyDeadInstructions(SI, TLI); + } + + NewCall->setDebugLoc(DLoc); + + DEBUG(dbgs() << " Formed " << (Overlap ? "memmove: " : "memcpy: ") + << *NewCall << "\n" + << " from load ptr=" << *LoadEv << " at: " << *LI << "\n" + << " from store ptr=" << *StoreEv << " at: " << *SI << "\n"); + + return true; +} + + +// \brief Check if the instructions in Insts, together with their dependencies +// cover the loop in the sense that the loop could be safely eliminated once +// the instructions in Insts are removed. +bool HexagonLoopIdiomRecognize::coverLoop(Loop *L, + SmallVectorImpl<Instruction*> &Insts) const { + SmallSet<BasicBlock*,8> LoopBlocks; + for (auto *B : L->blocks()) + LoopBlocks.insert(B); + + SetVector<Instruction*> Worklist(Insts.begin(), Insts.end()); + + // Collect all instructions from the loop that the instructions in Insts + // depend on (plus their dependencies, etc.). These instructions will + // constitute the expression trees that feed those in Insts, but the trees + // will be limited only to instructions contained in the loop. + for (unsigned i = 0; i < Worklist.size(); ++i) { + Instruction *In = Worklist[i]; + for (auto I = In->op_begin(), E = In->op_end(); I != E; ++I) { + Instruction *OpI = dyn_cast<Instruction>(I); + if (!OpI) + continue; + BasicBlock *PB = OpI->getParent(); + if (!LoopBlocks.count(PB)) + continue; + Worklist.insert(OpI); + } + } + + // Scan all instructions in the loop, if any of them have a user outside + // of the loop, or outside of the expressions collected above, then either + // the loop has a side-effect visible outside of it, or there are + // instructions in it that are not involved in the original set Insts. + for (auto *B : L->blocks()) { + for (auto &In : *B) { + if (isa<BranchInst>(In) || isa<DbgInfoIntrinsic>(In)) + continue; + if (!Worklist.count(&In) && In.mayHaveSideEffects()) + return false; + for (const auto &K : In.users()) { + Instruction *UseI = dyn_cast<Instruction>(K); + if (!UseI) + continue; + BasicBlock *UseB = UseI->getParent(); + if (LF->getLoopFor(UseB) != L) + return false; + } + } + } + + return true; +} + +/// runOnLoopBlock - Process the specified block, which lives in a counted loop +/// with the specified backedge count. This block is known to be in the current +/// loop and not in any subloops. +bool HexagonLoopIdiomRecognize::runOnLoopBlock(Loop *CurLoop, BasicBlock *BB, + const SCEV *BECount, SmallVectorImpl<BasicBlock*> &ExitBlocks) { + // We can only promote stores in this block if they are unconditionally + // executed in the loop. For a block to be unconditionally executed, it has + // to dominate all the exit blocks of the loop. Verify this now. + auto DominatedByBB = [this,BB] (BasicBlock *EB) -> bool { + return DT->dominates(BB, EB); + }; + if (!std::all_of(ExitBlocks.begin(), ExitBlocks.end(), DominatedByBB)) + return false; + + bool MadeChange = false; + // Look for store instructions, which may be optimized to memset/memcpy. + SmallVector<StoreInst*,8> Stores; + collectStores(CurLoop, BB, Stores); + + // Optimize the store into a memcpy, if it feeds an similarly strided load. + for (auto &SI : Stores) + MadeChange |= processCopyingStore(CurLoop, SI, BECount); + + return MadeChange; +} + + +bool HexagonLoopIdiomRecognize::runOnCountableLoop(Loop *L) { + PolynomialMultiplyRecognize PMR(L, *DL, *DT, *TLI, *SE); + if (PMR.recognize()) + return true; + + if (!HasMemcpy && !HasMemmove) + return false; + + const SCEV *BECount = SE->getBackedgeTakenCount(L); + assert(!isa<SCEVCouldNotCompute>(BECount) && + "runOnCountableLoop() called on a loop without a predictable" + "backedge-taken count"); + + SmallVector<BasicBlock *, 8> ExitBlocks; + L->getUniqueExitBlocks(ExitBlocks); + + bool Changed = false; + + // Scan all the blocks in the loop that are not in subloops. + for (auto *BB : L->getBlocks()) { + // Ignore blocks in subloops. + if (LF->getLoopFor(BB) != L) + continue; + Changed |= runOnLoopBlock(L, BB, BECount, ExitBlocks); + } + + return Changed; +} + + +bool HexagonLoopIdiomRecognize::runOnLoop(Loop *L, LPPassManager &LPM) { + const Module &M = *L->getHeader()->getParent()->getParent(); + if (Triple(M.getTargetTriple()).getArch() != Triple::hexagon) + return false; + + if (skipLoop(L)) + return false; + + // If the loop could not be converted to canonical form, it must have an + // indirectbr in it, just give up. + if (!L->getLoopPreheader()) + return false; + + // Disable loop idiom recognition if the function's name is a common idiom. + StringRef Name = L->getHeader()->getParent()->getName(); + if (Name == "memset" || Name == "memcpy" || Name == "memmove") + return false; + + AA = &getAnalysis<AAResultsWrapperPass>().getAAResults(); + DL = &L->getHeader()->getModule()->getDataLayout(); + DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree(); + LF = &getAnalysis<LoopInfoWrapperPass>().getLoopInfo(); + TLI = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(); + SE = &getAnalysis<ScalarEvolutionWrapperPass>().getSE(); + + HasMemcpy = TLI->has(LibFunc_memcpy); + HasMemmove = TLI->has(LibFunc_memmove); + + if (SE->hasLoopInvariantBackedgeTakenCount(L)) + return runOnCountableLoop(L); + return false; +} + + +Pass *llvm::createHexagonLoopIdiomPass() { + return new HexagonLoopIdiomRecognize(); +} + diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp index a5dc002642c8..7189b5a52c42 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp @@ -109,11 +109,14 @@ void llvm::HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI, switch (MO.getType()) { default: - MI->dump(); + MI->print(errs()); llvm_unreachable("unknown operand type"); + case MachineOperand::MO_RegisterMask: + continue; case MachineOperand::MO_Register: // Ignore all implicit register operands. - if (MO.isImplicit()) continue; + if (MO.isImplicit()) + continue; MCO = MCOperand::createReg(MO.getReg()); break; case MachineOperand::MO_FPImmediate: { diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp index 9ff9d93ea0c3..20dc9b0da1db 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp @@ -74,7 +74,9 @@ bool HexagonCallMutation::shouldTFRICallBind(const HexagonInstrInfo &HII, return false; // TypeXTYPE are 64 bit operations. - if (HII.getType(*Inst2.getInstr()) == HexagonII::TypeXTYPE) + unsigned Type = HII.getType(*Inst2.getInstr()); + if (Type == HexagonII::TypeS_2op || Type == HexagonII::TypeS_3op || + Type == HexagonII::TypeALU64 || Type == HexagonII::TypeM) return true; return false; } diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td b/contrib/llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td new file mode 100644 index 000000000000..0b4ac14c7a47 --- /dev/null +++ b/contrib/llvm/lib/Target/Hexagon/HexagonMapAsm2IntrinV62.gen.td @@ -0,0 +1,204 @@ +//===--- HexagonMapAsm2IntrinV62.gen.td -----------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +multiclass T_VR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID VectorRegs:$src1, IntRegs:$src2), + (MI VectorRegs:$src1, IntRegs:$src2)>, + Requires<[UseHVXSgl]>; + def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, IntRegs:$src2), + (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, IntRegs:$src2)>, + Requires<[UseHVXDbl]>; +} + +multiclass T_VVL_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegsLow8:$src3), + (MI VectorRegs:$src1, VectorRegs:$src2, IntRegsLow8:$src3)>, + Requires<[UseHVXSgl]>; + def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegsLow8:$src3), + (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegsLow8:$src3)>, + Requires<[UseHVXDbl]>; +} + +multiclass T_VV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2), + (MI VectorRegs:$src1, VectorRegs:$src2)>, + Requires<[UseHVXSgl]>; + def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2), + (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2)>, + Requires<[UseHVXDbl]>; +} + +multiclass T_WW_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2), + (MI VecDblRegs:$src1, VecDblRegs:$src2)>, + Requires<[UseHVXSgl]>; + def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2), + (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2)>, + Requires<[UseHVXDbl]>; +} + +multiclass T_WVV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), + (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>, + Requires<[UseHVXSgl]>; + def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3), + (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3)>, + Requires<[UseHVXDbl]>; +} + +multiclass T_WR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2), + (MI VecDblRegs:$src1, IntRegs:$src2)>, + Requires<[UseHVXSgl]>; + def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, IntRegs:$src2), + (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, IntRegs:$src2)>, + Requires<[UseHVXDbl]>; +} + +multiclass T_WWR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3), + (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>, + Requires<[UseHVXSgl]>; + def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2, IntRegs:$src3), + (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, VecDblRegs128B:$src2, IntRegs:$src3)>, + Requires<[UseHVXDbl]>; +} + +multiclass T_VVR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3), + (MI VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>, + Requires<[UseHVXSgl]>; + def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegs:$src3), + (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, IntRegs:$src3)>, + Requires<[UseHVXDbl]>; +} + +multiclass T_ZR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID VecPredRegs:$src1, IntRegs:$src2), + (MI VecPredRegs:$src1, IntRegs:$src2)>, + Requires<[UseHVXSgl]>; + def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, IntRegs:$src2), + (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, IntRegs:$src2)>, + Requires<[UseHVXDbl]>; +} + +multiclass T_VZR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3), + (MI VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3)>, + Requires<[UseHVXSgl]>; + def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VecPredRegs128B:$src2, IntRegs:$src3), + (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VecPredRegs128B:$src2, IntRegs:$src3)>, + Requires<[UseHVXDbl]>; +} + +multiclass T_ZV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2), + (MI VecPredRegs:$src1, VectorRegs:$src2)>, + Requires<[UseHVXSgl]>; + def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, VectorRegs128B:$src2), + (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, VectorRegs128B:$src2)>, + Requires<[UseHVXDbl]>; +} + +multiclass T_R_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID IntRegs:$src1), + (MI IntRegs:$src1)>, + Requires<[UseHVXSgl]>; + def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1), + (!cast<InstHexagon>(MI#"_128B") IntRegs:$src1)>, + Requires<[UseHVXDbl]>; +} + +multiclass T_ZZ_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID VecPredRegs:$src1, VecPredRegs:$src2), + (MI VecPredRegs:$src1, VecPredRegs:$src2)>, + Requires<[UseHVXSgl]>; + def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1, VecPredRegs128B:$src2), + (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1, VecPredRegs128B:$src2)>, + Requires<[UseHVXDbl]>; +} + +multiclass T_VVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, imm:$src3), + (MI VectorRegs:$src1, VectorRegs:$src2, imm:$src3)>, + Requires<[UseHVXSgl]>; + def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, imm:$src3), + (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, imm:$src3)>, + Requires<[UseHVXDbl]>; +} + +multiclass T_VVVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4), + (MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4)>, + Requires<[UseHVXSgl]>; + def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4), + (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4)>, + Requires<[UseHVXDbl]>; +} + +multiclass T_WVVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> { + def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4), + (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3, imm:$src4)>, + Requires<[UseHVXSgl]>; + def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4), + (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3, imm:$src4)>, + Requires<[UseHVXDbl]>; +} + +def : T_R_pat <S6_vsplatrbp, int_hexagon_S6_vsplatrbp>; +def : T_PP_pat <M6_vabsdiffb, int_hexagon_M6_vabsdiffb>; +def : T_PP_pat <M6_vabsdiffub, int_hexagon_M6_vabsdiffub>; +def : T_PP_pat <S6_vtrunehb_ppp, int_hexagon_S6_vtrunehb_ppp>; +def : T_PP_pat <S6_vtrunohb_ppp, int_hexagon_S6_vtrunohb_ppp>; + +defm : T_VR_HVX_gen_pat <V6_vlsrb, int_hexagon_V6_vlsrb>; +defm : T_VR_HVX_gen_pat <V6_vmpyiwub, int_hexagon_V6_vmpyiwub>; +defm : T_VVL_HVX_gen_pat <V6_vasrwuhrndsat, int_hexagon_V6_vasrwuhrndsat>; +defm : T_VVL_HVX_gen_pat <V6_vasruwuhrndsat, int_hexagon_V6_vasruwuhrndsat>; +defm : T_VVL_HVX_gen_pat <V6_vasrhbsat, int_hexagon_V6_vasrhbsat>; +defm : T_VVL_HVX_gen_pat <V6_vlutvvb_nm, int_hexagon_V6_vlutvvb_nm>; +defm : T_VVL_HVX_gen_pat <V6_vlutvwh_nm, int_hexagon_V6_vlutvwh_nm>; +defm : T_VV_HVX_gen_pat <V6_vrounduwuh, int_hexagon_V6_vrounduwuh>; +defm : T_VV_HVX_gen_pat <V6_vrounduhub, int_hexagon_V6_vrounduhub>; +defm : T_VV_HVX_gen_pat <V6_vadduwsat, int_hexagon_V6_vadduwsat>; +defm : T_VV_HVX_gen_pat <V6_vsubuwsat, int_hexagon_V6_vsubuwsat>; +defm : T_VV_HVX_gen_pat <V6_vaddbsat, int_hexagon_V6_vaddbsat>; +defm : T_VV_HVX_gen_pat <V6_vsubbsat, int_hexagon_V6_vsubbsat>; +defm : T_VV_HVX_gen_pat <V6_vaddububb_sat, int_hexagon_V6_vaddububb_sat>; +defm : T_VV_HVX_gen_pat <V6_vsubububb_sat, int_hexagon_V6_vsubububb_sat>; +defm : T_VV_HVX_gen_pat <V6_vmpyewuh_64, int_hexagon_V6_vmpyewuh_64>; +defm : T_VV_HVX_gen_pat <V6_vmaxb, int_hexagon_V6_vmaxb>; +defm : T_VV_HVX_gen_pat <V6_vminb, int_hexagon_V6_vminb>; +defm : T_VV_HVX_gen_pat <V6_vsatuwuh, int_hexagon_V6_vsatuwuh>; +defm : T_VV_HVX_gen_pat <V6_vaddclbw, int_hexagon_V6_vaddclbw>; +defm : T_VV_HVX_gen_pat <V6_vaddclbh, int_hexagon_V6_vaddclbh>; +defm : T_WW_HVX_gen_pat <V6_vadduwsat_dv, int_hexagon_V6_vadduwsat_dv>; +defm : T_WW_HVX_gen_pat <V6_vsubuwsat_dv, int_hexagon_V6_vsubuwsat_dv>; +defm : T_WW_HVX_gen_pat <V6_vaddbsat_dv, int_hexagon_V6_vaddbsat_dv>; +defm : T_WW_HVX_gen_pat <V6_vsubbsat_dv, int_hexagon_V6_vsubbsat_dv>; +defm : T_WVV_HVX_gen_pat <V6_vaddhw_acc, int_hexagon_V6_vaddhw_acc>; +defm : T_WVV_HVX_gen_pat <V6_vadduhw_acc, int_hexagon_V6_vadduhw_acc>; +defm : T_WVV_HVX_gen_pat <V6_vaddubh_acc, int_hexagon_V6_vaddubh_acc>; +defm : T_WVV_HVX_gen_pat <V6_vmpyowh_64_acc, int_hexagon_V6_vmpyowh_64_acc>; +defm : T_WR_HVX_gen_pat <V6_vmpauhb, int_hexagon_V6_vmpauhb>; +defm : T_WWR_HVX_gen_pat <V6_vmpauhb_acc, int_hexagon_V6_vmpauhb_acc>; +defm : T_VVR_HVX_gen_pat <V6_vmpyiwub_acc, int_hexagon_V6_vmpyiwub_acc>; +defm : T_ZR_HVX_gen_pat <V6_vandnqrt, int_hexagon_V6_vandnqrt>; +defm : T_VZR_HVX_gen_pat <V6_vandnqrt_acc, int_hexagon_V6_vandnqrt_acc>; +defm : T_ZV_HVX_gen_pat <V6_vandvqv, int_hexagon_V6_vandvqv>; +defm : T_ZV_HVX_gen_pat <V6_vandvnqv, int_hexagon_V6_vandvnqv>; +defm : T_R_HVX_gen_pat <V6_pred_scalar2v2, int_hexagon_V6_pred_scalar2v2>; +defm : T_R_HVX_gen_pat <V6_lvsplath, int_hexagon_V6_lvsplath>; +defm : T_R_HVX_gen_pat <V6_lvsplatb, int_hexagon_V6_lvsplatb>; +defm : T_ZZ_HVX_gen_pat <V6_shuffeqw, int_hexagon_V6_shuffeqw>; +defm : T_ZZ_HVX_gen_pat <V6_shuffeqh, int_hexagon_V6_shuffeqh>; +defm : T_VVI_HVX_gen_pat <V6_vlutvvbi, int_hexagon_V6_vlutvvbi>; +defm : T_VVI_HVX_gen_pat <V6_vlutvwhi, int_hexagon_V6_vlutvwhi>; +defm : T_VVVI_HVX_gen_pat <V6_vlutvvb_oracci, int_hexagon_V6_vlutvvb_oracci>; +defm : T_WVVI_HVX_gen_pat <V6_vlutvwh_oracci, int_hexagon_V6_vlutvwh_oracci>; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp index 72d8011277e6..d73fc7c73185 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -130,6 +130,8 @@ static bool canBeFeederToNewValueJump(const HexagonInstrInfo *QII, if (II->getOpcode() == TargetOpcode::KILL) return false; + if (II->isImplicitDef()) + return false; // Make sure there there is no 'def' or 'use' of any of the uses of // feeder insn between it's definition, this MI and jump, jmpInst diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonOperands.td b/contrib/llvm/lib/Target/Hexagon/HexagonOperands.td index 983310571563..f87a1b8e424d 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonOperands.td +++ b/contrib/llvm/lib/Target/Hexagon/HexagonOperands.td @@ -1,298 +1,33 @@ -//===- HexagonImmediates.td - Hexagon immediate processing -*- tablegen -*-===// +//===--- HexagonOperands.td -----------------------------------------------===// // // The LLVM Compiler Infrastructure // -// This file is distributed under the University of Illnois Open Source +// This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -def s32_0ImmOperand : AsmOperandClass { let Name = "s32_0Imm"; } -def s23_2ImmOperand : AsmOperandClass { let Name = "s23_2Imm"; } -def s8_0ImmOperand : AsmOperandClass { let Name = "s8_0Imm"; } -def s8_0Imm64Operand : AsmOperandClass { let Name = "s8_0Imm64"; } -def s6_0ImmOperand : AsmOperandClass { let Name = "s6_0Imm"; } -def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; } -def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; } -def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; } -def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; } -def s4_6ImmOperand : AsmOperandClass { let Name = "s4_6Imm"; } -def s3_6ImmOperand : AsmOperandClass { let Name = "s3_6Imm"; } -def u64_0ImmOperand : AsmOperandClass { let Name = "u64_0Imm"; } -def u32_0ImmOperand : AsmOperandClass { let Name = "u32_0Imm"; } -def u26_6ImmOperand : AsmOperandClass { let Name = "u26_6Imm"; } -def u16_0ImmOperand : AsmOperandClass { let Name = "u16_0Imm"; } -def u16_1ImmOperand : AsmOperandClass { let Name = "u16_1Imm"; } -def u16_2ImmOperand : AsmOperandClass { let Name = "u16_2Imm"; } -def u16_3ImmOperand : AsmOperandClass { let Name = "u16_3Imm"; } -def u11_3ImmOperand : AsmOperandClass { let Name = "u11_3Imm"; } -def u10_0ImmOperand : AsmOperandClass { let Name = "u10_0Imm"; } -def u9_0ImmOperand : AsmOperandClass { let Name = "u9_0Imm"; } -def u8_0ImmOperand : AsmOperandClass { let Name = "u8_0Imm"; } -def u7_0ImmOperand : AsmOperandClass { let Name = "u7_0Imm"; } -def u6_0ImmOperand : AsmOperandClass { let Name = "u6_0Imm"; } -def u6_1ImmOperand : AsmOperandClass { let Name = "u6_1Imm"; } -def u6_2ImmOperand : AsmOperandClass { let Name = "u6_2Imm"; } -def u6_3ImmOperand : AsmOperandClass { let Name = "u6_3Imm"; } -def u5_0ImmOperand : AsmOperandClass { let Name = "u5_0Imm"; } -def u4_0ImmOperand : AsmOperandClass { let Name = "u4_0Imm"; } -def u3_0ImmOperand : AsmOperandClass { let Name = "u3_0Imm"; } -def u2_0ImmOperand : AsmOperandClass { let Name = "u2_0Imm"; } -def u1_0ImmOperand : AsmOperandClass { let Name = "u1_0Imm"; } -def n8_0ImmOperand : AsmOperandClass { let Name = "n8_0Imm"; } -// Immediate operands. - -let OperandType = "OPERAND_IMMEDIATE", - DecoderMethod = "unsignedImmDecoder" in { - def s32_0Imm : Operand<i32> { let ParserMatchClass = s32_0ImmOperand; - let DecoderMethod = "s32_0ImmDecoder"; } - def s23_2Imm : Operand<i32> { let ParserMatchClass = s23_2ImmOperand; } - def s8_0Imm : Operand<i32> { let ParserMatchClass = s8_0ImmOperand; - let DecoderMethod = "s8_0ImmDecoder"; } - def s8_0Imm64 : Operand<i64> { let ParserMatchClass = s8_0Imm64Operand; - let DecoderMethod = "s8_0ImmDecoder"; } - def s6_0Imm : Operand<i32> { let ParserMatchClass = s6_0ImmOperand; - let DecoderMethod = "s6_0ImmDecoder"; } - def s6_3Imm : Operand<i32>; - def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand; - let DecoderMethod = "s4_0ImmDecoder"; } - def s4_1Imm : Operand<i32> { let ParserMatchClass = s4_1ImmOperand; - let DecoderMethod = "s4_1ImmDecoder"; } - def s4_2Imm : Operand<i32> { let ParserMatchClass = s4_2ImmOperand; - let DecoderMethod = "s4_2ImmDecoder"; } - def s4_3Imm : Operand<i32> { let ParserMatchClass = s4_3ImmOperand; - let DecoderMethod = "s4_3ImmDecoder"; } - def u64_0Imm : Operand<i64> { let ParserMatchClass = u64_0ImmOperand; } - def u32_0Imm : Operand<i32> { let ParserMatchClass = u32_0ImmOperand; } - def u26_6Imm : Operand<i32> { let ParserMatchClass = u26_6ImmOperand; } - def u16_0Imm : Operand<i32> { let ParserMatchClass = u16_0ImmOperand; } - def u16_1Imm : Operand<i32> { let ParserMatchClass = u16_1ImmOperand; } - def u16_2Imm : Operand<i32> { let ParserMatchClass = u16_2ImmOperand; } - def u16_3Imm : Operand<i32> { let ParserMatchClass = u16_3ImmOperand; } - def u11_3Imm : Operand<i32> { let ParserMatchClass = u11_3ImmOperand; } - def u10_0Imm : Operand<i32> { let ParserMatchClass = u10_0ImmOperand; } - def u9_0Imm : Operand<i32> { let ParserMatchClass = u9_0ImmOperand; } - def u8_0Imm : Operand<i32> { let ParserMatchClass = u8_0ImmOperand; } - def u7_0Imm : Operand<i32> { let ParserMatchClass = u7_0ImmOperand; } - def u6_0Imm : Operand<i32> { let ParserMatchClass = u6_0ImmOperand; } - def u6_1Imm : Operand<i32> { let ParserMatchClass = u6_1ImmOperand; } - def u6_2Imm : Operand<i32> { let ParserMatchClass = u6_2ImmOperand; } - def u6_3Imm : Operand<i32> { let ParserMatchClass = u6_3ImmOperand; } - def u5_0Imm : Operand<i32> { let ParserMatchClass = u5_0ImmOperand; } - def u5_1Imm : Operand<i32>; - def u5_2Imm : Operand<i32>; - def u5_3Imm : Operand<i32>; - def u4_0Imm : Operand<i32> { let ParserMatchClass = u4_0ImmOperand; } - def u4_1Imm : Operand<i32>; - def u4_2Imm : Operand<i32>; - def u4_3Imm : Operand<i32>; - def u3_0Imm : Operand<i32> { let ParserMatchClass = u3_0ImmOperand; } - def u3_1Imm : Operand<i32>; - def u3_2Imm : Operand<i32>; - def u3_3Imm : Operand<i32>; - def u2_0Imm : Operand<i32> { let ParserMatchClass = u2_0ImmOperand; } - def u1_0Imm : Operand<i32> { let ParserMatchClass = u1_0ImmOperand; } - def n8_0Imm : Operand<i32> { let ParserMatchClass = n8_0ImmOperand; } -} - -let OperandType = "OPERAND_IMMEDIATE" in { - def s4_6Imm : Operand<i32> { let ParserMatchClass = s4_6ImmOperand; - let PrintMethod = "prints4_6ImmOperand"; - let DecoderMethod = "s4_6ImmDecoder";} - def s4_7Imm : Operand<i32> { let PrintMethod = "prints4_7ImmOperand"; - let DecoderMethod = "s4_6ImmDecoder";} - def s3_6Imm : Operand<i32> { let ParserMatchClass = s3_6ImmOperand; - let PrintMethod = "prints3_6ImmOperand"; - let DecoderMethod = "s3_6ImmDecoder";} - def s3_7Imm : Operand<i32> { let PrintMethod = "prints3_7ImmOperand"; - let DecoderMethod = "s3_6ImmDecoder";} -} -def n1ConstOperand : AsmOperandClass { let Name = "n1Const"; } -def n1Const : Operand<i32> { let ParserMatchClass = n1ConstOperand; } - -// -// Immediate predicates -// -def s32_0ImmPred : PatLeaf<(i32 imm), [{ +def f32ImmOperand : AsmOperandClass { let Name = "f32Imm"; } +def f32Imm : Operand<f32> { let ParserMatchClass = f32ImmOperand; } +def f64ImmOperand : AsmOperandClass { let Name = "f64Imm"; } +def f64Imm : Operand<f64> { let ParserMatchClass = f64ImmOperand; } +def s8_0Imm64Pred : PatLeaf<(i64 imm), [{ return isInt<8>(N->getSExtValue()); }]>; +def s9_0ImmOperand : AsmOperandClass { let Name = "s9_0Imm"; } +def s9_0Imm : Operand<i32> { let ParserMatchClass = s9_0ImmOperand; } +def s23_2ImmOperand : AsmOperandClass { let Name = "s23_2Imm"; let RenderMethod = "addSignedImmOperands"; } +def s23_2Imm : Operand<i32> { let ParserMatchClass = s23_2ImmOperand; } +def r32_0ImmPred : PatLeaf<(i32 imm), [{ int64_t v = (int64_t)N->getSExtValue(); return isInt<32>(v); }]>; - -def s31_1ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedInt<31,1>(v); -}]>; - -def s30_2ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedInt<30,2>(v); -}]>; - -def s29_3ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedInt<29,3>(v); -}]>; - -def s10_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isInt<10>(v); -}]>; - -def s8_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isInt<8>(v); -}]>; - -def s8_0Imm64Pred : PatLeaf<(i64 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isInt<8>(v); -}]>; - -def s6_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isInt<6>(v); -}]>; - -def s4_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isInt<4>(v); -}]>; - -def s4_1ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedInt<4,1>(v); -}]>; - -def s4_2ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedInt<4,2>(v); -}]>; - -def s4_3ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedInt<4,3>(v); -}]>; - -def u32_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isUInt<32>(v); -}]>; - -def u16_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isUInt<16>(v); -}]>; - -def u11_3ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedUInt<11,3>(v); -}]>; - def u9_0ImmPred : PatLeaf<(i32 imm), [{ int64_t v = (int64_t)N->getSExtValue(); return isUInt<9>(v); }]>; - -def u8_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isUInt<8>(v); -}]>; - -def u6_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isUInt<6>(v); -}]>; - -def u6_1ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedUInt<6,1>(v); -}]>; - -def u6_2ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isShiftedUInt<6,2>(v); -}]>; - -def u5_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isUInt<5>(v); -}]>; - -def u4_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isUInt<4>(v); -}]>; - -def u3_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isUInt<3>(v); -}]>; - -def u2_0ImmPred : PatLeaf<(i32 imm), [{ - int64_t v = (int64_t)N->getSExtValue(); - return isUInt<2>(v); -}]>; - -// Extendable immediate operands. -def f32ExtOperand : AsmOperandClass { let Name = "f32Ext"; } -def s16_0ExtOperand : AsmOperandClass { let Name = "s16_0Ext"; } -def s12_0ExtOperand : AsmOperandClass { let Name = "s12_0Ext"; } -def s10_0ExtOperand : AsmOperandClass { let Name = "s10_0Ext"; } -def s9_0ExtOperand : AsmOperandClass { let Name = "s9_0Ext"; } -def s8_0ExtOperand : AsmOperandClass { let Name = "s8_0Ext"; } -def s7_0ExtOperand : AsmOperandClass { let Name = "s7_0Ext"; } -def s6_0ExtOperand : AsmOperandClass { let Name = "s6_0Ext"; } -def s11_0ExtOperand : AsmOperandClass { let Name = "s11_0Ext"; } -def s11_1ExtOperand : AsmOperandClass { let Name = "s11_1Ext"; } -def s11_2ExtOperand : AsmOperandClass { let Name = "s11_2Ext"; } -def s11_3ExtOperand : AsmOperandClass { let Name = "s11_3Ext"; } -def u6_0ExtOperand : AsmOperandClass { let Name = "u6_0Ext"; } -def u7_0ExtOperand : AsmOperandClass { let Name = "u7_0Ext"; } -def u8_0ExtOperand : AsmOperandClass { let Name = "u8_0Ext"; } -def u9_0ExtOperand : AsmOperandClass { let Name = "u9_0Ext"; } -def u10_0ExtOperand : AsmOperandClass { let Name = "u10_0Ext"; } -def u6_1ExtOperand : AsmOperandClass { let Name = "u6_1Ext"; } -def u6_2ExtOperand : AsmOperandClass { let Name = "u6_2Ext"; } -def u6_3ExtOperand : AsmOperandClass { let Name = "u6_3Ext"; } -def u32_0MustExtOperand : AsmOperandClass { let Name = "u32_0MustExt"; } - - - -let OperandType = "OPERAND_IMMEDIATE", PrintMethod = "printExtOperand", - DecoderMethod = "unsignedImmDecoder" in { - def f32Ext : Operand<f32> { let ParserMatchClass = f32ExtOperand; } - def s16_0Ext : Operand<i32> { let ParserMatchClass = s16_0ExtOperand; - let DecoderMethod = "s16_0ImmDecoder"; } - def s12_0Ext : Operand<i32> { let ParserMatchClass = s12_0ExtOperand; - let DecoderMethod = "s12_0ImmDecoder"; } - def s11_0Ext : Operand<i32> { let ParserMatchClass = s11_0ExtOperand; - let DecoderMethod = "s11_0ImmDecoder"; } - def s11_1Ext : Operand<i32> { let ParserMatchClass = s11_1ExtOperand; - let DecoderMethod = "s11_1ImmDecoder"; } - def s11_2Ext : Operand<i32> { let ParserMatchClass = s11_2ExtOperand; - let DecoderMethod = "s11_2ImmDecoder"; } - def s11_3Ext : Operand<i32> { let ParserMatchClass = s11_3ExtOperand; - let DecoderMethod = "s11_3ImmDecoder"; } - def s10_0Ext : Operand<i32> { let ParserMatchClass = s10_0ExtOperand; - let DecoderMethod = "s10_0ImmDecoder"; } - def s9_0Ext : Operand<i32> { let ParserMatchClass = s9_0ExtOperand; - let DecoderMethod = "s9_0ImmDecoder"; } - def s8_0Ext : Operand<i32> { let ParserMatchClass = s8_0ExtOperand; - let DecoderMethod = "s8_0ImmDecoder"; } - def s7_0Ext : Operand<i32> { let ParserMatchClass = s7_0ExtOperand; } - def s6_0Ext : Operand<i32> { let ParserMatchClass = s6_0ExtOperand; - let DecoderMethod = "s6_0ImmDecoder"; } - def u7_0Ext : Operand<i32> { let ParserMatchClass = u7_0ExtOperand; } - def u8_0Ext : Operand<i32> { let ParserMatchClass = u8_0ExtOperand; } - def u9_0Ext : Operand<i32> { let ParserMatchClass = u9_0ExtOperand; } - def u10_0Ext : Operand<i32> { let ParserMatchClass = u10_0ExtOperand; } - def u6_0Ext : Operand<i32> { let ParserMatchClass = u6_0ExtOperand; } - def u6_1Ext : Operand<i32> { let ParserMatchClass = u6_1ExtOperand; } - def u6_2Ext : Operand<i32> { let ParserMatchClass = u6_2ExtOperand; } - def u6_3Ext : Operand<i32> { let ParserMatchClass = u6_3ExtOperand; } - def u32_0MustExt : Operand<i32> { let ParserMatchClass = u32_0MustExtOperand; } -} - +def u64_0ImmOperand : AsmOperandClass { let Name = "u64_0Imm"; let RenderMethod = "addImmOperands"; } +def u64_0Imm : Operand<i64> { let ParserMatchClass = u64_0ImmOperand; } +def n1ConstOperand : AsmOperandClass { let Name = "n1Const"; } +def n1Const : Operand<i32> { let ParserMatchClass = n1ConstOperand; } // This complex pattern exists only to create a machine instruction operand // of type "frame index". There doesn't seem to be a way to do that directly @@ -305,28 +40,6 @@ def AddrFI : ComplexPattern<i32, 1, "SelectAddrFI", [frameindex], []>; def AddrGA : ComplexPattern<i32, 1, "SelectAddrGA", [], []>; def AddrGP : ComplexPattern<i32, 1, "SelectAddrGP", [], []>; -// Address operands. - -let PrintMethod = "printGlobalOperand" in { - def globaladdress : Operand<i32>; - def globaladdressExt : Operand<i32>; -} - -let PrintMethod = "printJumpTable" in -def jumptablebase : Operand<i32>; - -def brtarget : Operand<OtherVT> { - let DecoderMethod = "brtargetDecoder"; - let PrintMethod = "printBrtarget"; -} -def brtargetExt : Operand<OtherVT> { - let DecoderMethod = "brtargetDecoder"; - let PrintMethod = "printBrtarget"; -} -def calltarget : Operand<i32> { - let DecoderMethod = "brtargetDecoder"; - let PrintMethod = "printBrtarget"; -} def bblabel : Operand<i32>; def bbl : SDNode<"ISD::BasicBlock", SDTPtrLeaf, [], "BasicBlockSDNode">; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp index 89db46799cb3..b243de317dc5 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp @@ -208,7 +208,16 @@ bool HexagonOptAddrMode::allValidCandidates(NodeAddr<StmtNode *> SA, NodeAddr<UseNode *> UN = *I; RegisterRef UR = UN.Addr->getRegRef(*DFG); NodeSet Visited, Defs; - const auto &ReachingDefs = LV->getAllReachingDefsRec(UR, UN, Visited, Defs); + const auto &P = LV->getAllReachingDefsRec(UR, UN, Visited, Defs); + if (!P.second) { + DEBUG({ + dbgs() << "*** Unable to collect all reaching defs for use ***\n" + << PrintNode<UseNode*>(UN, *DFG) << '\n' + << "The program's complexity may exceed the limits.\n"; + }); + return false; + } + const auto &ReachingDefs = P.first; if (ReachingDefs.size() > 1) { DEBUG({ dbgs() << "*** Multiple Reaching Defs found!!! ***\n"; @@ -230,7 +239,7 @@ void HexagonOptAddrMode::getAllRealUses(NodeAddr<StmtNode *> SA, for (NodeAddr<DefNode *> DA : SA.Addr->members_if(DFG->IsDef, *DFG)) { DEBUG(dbgs() << "\t\t[DefNode]: " << Print<NodeAddr<DefNode *>>(DA, *DFG) << "\n"); - RegisterRef DR = DFG->normalizeRef(DA.Addr->getRegRef(*DFG)); + RegisterRef DR = DFG->getPRI().normalize(DA.Addr->getRegRef(*DFG)); auto UseSet = LV->getAllReachedUses(DR, DA); @@ -250,7 +259,7 @@ void HexagonOptAddrMode::getAllRealUses(NodeAddr<StmtNode *> SA, << Print<Liveness::RefMap>(phiUse, *DFG) << "\n"); if (!phiUse.empty()) { for (auto I : phiUse) { - if (DR.Reg != I.first) + if (!DFG->getPRI().alias(RegisterRef(I.first), DR)) continue; auto phiUseSet = I.second; for (auto phiUI : phiUseSet) { @@ -333,17 +342,17 @@ bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, short NewOpCode = HII->getBaseWithLongOffset(*OldMI); assert(NewOpCode >= 0 && "Invalid New opcode\n"); MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); - MIB.addOperand(OldMI->getOperand(0)); - MIB.addOperand(OldMI->getOperand(2)); - MIB.addOperand(OldMI->getOperand(3)); - MIB.addOperand(ImmOp); + MIB.add(OldMI->getOperand(0)); + MIB.add(OldMI->getOperand(2)); + MIB.add(OldMI->getOperand(3)); + MIB.add(ImmOp); OpStart = 4; Changed = true; } else if (HII->getAddrMode(*OldMI) == HexagonII::BaseImmOffset) { short NewOpCode = HII->getAbsoluteForm(*OldMI); assert(NewOpCode >= 0 && "Invalid New opcode\n"); MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)) - .addOperand(OldMI->getOperand(0)); + .add(OldMI->getOperand(0)); const GlobalValue *GV = ImmOp.getGlobal(); int64_t Offset = ImmOp.getOffset() + OldMI->getOperand(2).getImm(); @@ -359,9 +368,9 @@ bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, short NewOpCode = HII->xformRegToImmOffset(*OldMI); assert(NewOpCode >= 0 && "Invalid New opcode\n"); MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); - MIB.addOperand(OldMI->getOperand(0)); - MIB.addOperand(OldMI->getOperand(1)); - MIB.addOperand(ImmOp); + MIB.add(OldMI->getOperand(0)); + MIB.add(OldMI->getOperand(1)); + MIB.add(ImmOp); OpStart = 4; Changed = true; DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); @@ -370,7 +379,7 @@ bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, if (Changed) for (unsigned i = OpStart; i < OpEnd; ++i) - MIB.addOperand(OldMI->getOperand(i)); + MIB.add(OldMI->getOperand(i)); return Changed; } @@ -390,10 +399,10 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp, short NewOpCode = HII->getBaseWithLongOffset(*OldMI); assert(NewOpCode >= 0 && "Invalid New opcode\n"); MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); - MIB.addOperand(OldMI->getOperand(1)); - MIB.addOperand(OldMI->getOperand(2)); - MIB.addOperand(ImmOp); - MIB.addOperand(OldMI->getOperand(3)); + MIB.add(OldMI->getOperand(1)); + MIB.add(OldMI->getOperand(2)); + MIB.add(ImmOp); + MIB.add(OldMI->getOperand(3)); OpStart = 4; } else if (HII->getAddrMode(*OldMI) == HexagonII::BaseImmOffset) { short NewOpCode = HII->getAbsoluteForm(*OldMI); @@ -402,7 +411,7 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp, const GlobalValue *GV = ImmOp.getGlobal(); int64_t Offset = ImmOp.getOffset() + OldMI->getOperand(1).getImm(); MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags()); - MIB.addOperand(OldMI->getOperand(2)); + MIB.add(OldMI->getOperand(2)); OpStart = 3; } Changed = true; @@ -412,9 +421,9 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp, short NewOpCode = HII->xformRegToImmOffset(*OldMI); assert(NewOpCode >= 0 && "Invalid New opcode\n"); MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); - MIB.addOperand(OldMI->getOperand(0)); - MIB.addOperand(ImmOp); - MIB.addOperand(OldMI->getOperand(1)); + MIB.add(OldMI->getOperand(0)); + MIB.add(ImmOp); + MIB.add(OldMI->getOperand(1)); OpStart = 2; Changed = true; DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n"); @@ -422,7 +431,7 @@ bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp, } if (Changed) for (unsigned i = OpStart; i < OpEnd; ++i) - MIB.addOperand(OldMI->getOperand(i)); + MIB.add(OldMI->getOperand(i)); return Changed; } @@ -473,26 +482,26 @@ bool HexagonOptAddrMode::changeAddAsl(NodeAddr<UseNode *> AddAslUN, BuildMI(*BB, InsertPt, UseMI->getDebugLoc(), HII->get(NewOpCode)); // change mem(Rs + # ) -> mem(Rt << # + ##) if (UseMID.mayLoad()) { - MIB.addOperand(UseMI->getOperand(0)); - MIB.addOperand(AddAslMI->getOperand(2)); - MIB.addOperand(AddAslMI->getOperand(3)); + MIB.add(UseMI->getOperand(0)); + MIB.add(AddAslMI->getOperand(2)); + MIB.add(AddAslMI->getOperand(3)); const GlobalValue *GV = ImmOp.getGlobal(); MIB.addGlobalAddress(GV, UseMI->getOperand(2).getImm(), ImmOp.getTargetFlags()); OpStart = 3; } else if (UseMID.mayStore()) { - MIB.addOperand(AddAslMI->getOperand(2)); - MIB.addOperand(AddAslMI->getOperand(3)); + MIB.add(AddAslMI->getOperand(2)); + MIB.add(AddAslMI->getOperand(3)); const GlobalValue *GV = ImmOp.getGlobal(); MIB.addGlobalAddress(GV, UseMI->getOperand(1).getImm(), ImmOp.getTargetFlags()); - MIB.addOperand(UseMI->getOperand(2)); + MIB.add(UseMI->getOperand(2)); OpStart = 3; } else llvm_unreachable("Unhandled instruction"); for (unsigned i = OpStart; i < OpEnd; ++i) - MIB.addOperand(UseMI->getOperand(i)); + MIB.add(UseMI->getOperand(i)); Deleted.insert(UseMI); } @@ -617,7 +626,7 @@ bool HexagonOptAddrMode::constructDefMap(MachineBasicBlock *B) { for (NodeAddr<InstrNode *> IA : BA.Addr->members(*DFG)) { updateMap(IA); - DFG->pushDefs(IA, DefM); + DFG->pushAllDefs(IA, DefM); } MachineDomTreeNode *N = MDT->getNode(B); @@ -629,6 +638,9 @@ bool HexagonOptAddrMode::constructDefMap(MachineBasicBlock *B) { } bool HexagonOptAddrMode::runOnMachineFunction(MachineFunction &MF) { + if (skipFunction(*MF.getFunction())) + return false; + bool Changed = false; auto &HST = MF.getSubtarget<HexagonSubtarget>(); auto &MRI = MF.getRegInfo(); diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonPatterns.td b/contrib/llvm/lib/Target/Hexagon/HexagonPatterns.td index ad81287007e6..b8c3bf0745ce 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonPatterns.td +++ b/contrib/llvm/lib/Target/Hexagon/HexagonPatterns.td @@ -17,6 +17,16 @@ def HiReg: OutPatFrag<(ops node:$Rs), (EXTRACT_SUBREG (i64 $Rs), isub_hi)>; def IsOrAdd: PatFrag<(ops node:$Addr, node:$off), (or node:$Addr, node:$off), [{ return isOrEquivalentToAdd(N); }]>; +def Iss4_6 : PatLeaf<(i32 imm), [{ + int32_t V = N->getSExtValue(); + return isShiftedInt<4,6>(V); +}]>; + +def Iss4_7 : PatLeaf<(i32 imm), [{ + int32_t V = N->getSExtValue(); + return isShiftedInt<4,7>(V); +}]>; + def IsPow2_32 : PatLeaf<(i32 imm), [{ uint32_t V = N->getZExtValue(); return isPowerOf2_32(V); @@ -89,6 +99,11 @@ def LogN2_64 : SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(Log2_64(NV), SDLoc(N), MVT::i32); }]>; +def ToZext64: OutPatFrag<(ops node:$Rs), + (i64 (A4_combineir 0, (i32 $Rs)))>; +def ToSext64: OutPatFrag<(ops node:$Rs), + (i64 (A2_sxtw (i32 $Rs)))>; + class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred> : Pat<(i1 (OpNode I32:$src1, ImmPred:$src2)), @@ -153,8 +168,12 @@ def: Pat<(sub s32_0ImmPred:$s10, IntRegs:$Rs), def: Pat<(not I32:$src1), (A2_subri -1, IntRegs:$src1)>; +def TruncI64ToI32: SDNodeXForm<imm, [{ + return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32); +}]>; + def: Pat<(s32_0ImmPred:$s16), (A2_tfrsi imm:$s16)>; -def: Pat<(s8_0Imm64Pred:$s8), (A2_tfrpi imm:$s8)>; +def: Pat<(s8_0Imm64Pred:$s8), (A2_tfrpi (TruncI64ToI32 $s8))>; def : Pat<(select I1:$Pu, s32_0ImmPred:$s8, I32:$Rs), (C2_muxri I1:$Pu, imm:$s8, I32:$Rs)>; @@ -274,7 +293,7 @@ def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>; -def: Pat<(br bb:$dst), (J2_jump brtarget:$dst)>; +def: Pat<(br bb:$dst), (J2_jump b30_2Imm:$dst)>; def: Pat<(brcond I1:$src1, bb:$block), (J2_jumpt PredRegs:$src1, bb:$block)>; def: Pat<(brind I32:$dst), (J2_jumpr IntRegs:$dst)>; @@ -695,8 +714,8 @@ def HexagonCONST32 : SDNode<"HexagonISD::CONST32", SDTHexagonCONST32>; def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>; // Map TLS addressses to A2_tfrsi. -def: Pat<(HexagonCONST32 tglobaltlsaddr:$addr), (A2_tfrsi s16_0Ext:$addr)>; -def: Pat<(HexagonCONST32 bbl:$label), (A2_tfrsi s16_0Ext:$label)>; +def: Pat<(HexagonCONST32 tglobaltlsaddr:$addr), (A2_tfrsi s32_0Imm:$addr)>; +def: Pat<(HexagonCONST32 bbl:$label), (A2_tfrsi s32_0Imm:$label)>; def: Pat<(i64 imm:$v), (CONST64 imm:$v)>; def: Pat<(i1 0), (PS_false)>; @@ -898,26 +917,35 @@ def: Pat<(i1 (setule I64:$src1, I64:$src2)), (C2_not (C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2))>; // Sign extends. -// i1 -> i32 -def: Pat<(i32 (sext I1:$src1)), - (C2_muxii PredRegs:$src1, -1, 0)>; +// sext i1->i32 +def: Pat<(i32 (sext I1:$Pu)), + (C2_muxii I1:$Pu, -1, 0)>; -// i1 -> i64 -def: Pat<(i64 (sext I1:$src1)), - (A2_combinew (A2_tfrsi -1), (C2_muxii PredRegs:$src1, -1, 0))>; +// sext i1->i64 +def: Pat<(i64 (sext I1:$Pu)), + (A2_combinew (C2_muxii PredRegs:$Pu, -1, 0), + (C2_muxii PredRegs:$Pu, -1, 0))>; // Zero extends. -// i1 -> i32 -def: Pat<(i32 (zext I1:$src1)), - (C2_muxii PredRegs:$src1, 1, 0)>; +// zext i1->i32 +def: Pat<(i32 (zext I1:$Pu)), + (C2_muxii PredRegs:$Pu, 1, 0)>; + +// zext i1->i64 +def: Pat<(i64 (zext I1:$Pu)), + (ToZext64 (C2_muxii PredRegs:$Pu, 1, 0))>; + +// zext i32->i64 +def: Pat<(Zext64 I32:$Rs), + (ToZext64 IntRegs:$Rs)>; // Map from Rs = Pd to Pd = mux(Pd, #1, #0) -def: Pat<(i32 (anyext I1:$src1)), - (C2_muxii PredRegs:$src1, 1, 0)>; +def: Pat<(i32 (anyext I1:$Pu)), + (C2_muxii PredRegs:$Pu, 1, 0)>; -// Map from Rss = Pd to Rdd = sxtw (mux(Pd, #1, #0)) -def: Pat<(i64 (anyext I1:$src1)), - (A2_sxtw (C2_muxii PredRegs:$src1, 1, 0))>; +// Map from Rss = Pd to Rdd = combine(#0, (mux(Pd, #1, #0))) +def: Pat<(i64 (anyext I1:$Pu)), + (ToZext64 (C2_muxii PredRegs:$Pu, 1, 0))>; // Clear the sign bit in a 64-bit register. def ClearSign : OutPatFrag<(ops node:$Rss), @@ -1244,11 +1272,6 @@ def: Pat<(HexagonCOMBINE s32_0ImmPred:$s8, s8_0ImmPred:$S8), } -def ToZext64: OutPatFrag<(ops node:$Rs), - (i64 (A4_combineir 0, (i32 $Rs)))>; -def ToSext64: OutPatFrag<(ops node:$Rs), - (i64 (A2_sxtw (i32 $Rs)))>; - // Patterns to generate indexed loads with different forms of the address: // - frameindex, // - base + offset, @@ -1349,14 +1372,6 @@ let AddedComplexity = 20 in { def: Loadxs_simple_pat<load, i64, L4_loadrd_rr>; } -// zext i1->i64 -def: Pat<(i64 (zext I1:$src1)), - (ToZext64 (C2_muxii PredRegs:$src1, 1, 0))>; - -// zext i32->i64 -def: Pat<(Zext64 I32:$src1), - (ToZext64 IntRegs:$src1)>; - let AddedComplexity = 40 in multiclass T_StoreAbsReg_Pats <InstHexagon MI, RegisterClass RC, ValueType VT, PatFrag stOp> { @@ -1587,6 +1602,15 @@ def: Pat<(i64 (cttz I64:$Rss)), (ToZext64 (S2_ct0p I64:$Rss))>; def: Pat<(i64 (ctlz (not I64:$Rss))), (ToZext64 (S2_cl1p I64:$Rss))>; def: Pat<(i64 (cttz (not I64:$Rss))), (ToZext64 (S2_ct1p I64:$Rss))>; +def: Pat<(i64 (ctpop I64:$Rss)), (ToZext64 (S5_popcountp I64:$Rss))>; +def: Pat<(i32 (ctpop I32:$Rs)), (S5_popcountp (A4_combineir 0, I32:$Rs))>; + +def: Pat<(bitreverse I32:$Rs), (S2_brev I32:$Rs)>; +def: Pat<(bitreverse I64:$Rss), (S2_brevp I64:$Rss)>; + +def: Pat<(bswap I32:$Rs), (A2_swiz I32:$Rs)>; +def: Pat<(bswap I64:$Rss), (A2_combinew (A2_swiz (LoReg $Rss)), + (A2_swiz (HiReg $Rss)))>; let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. def: Pat<(i1 (seteq (and (shl 1, u5_0ImmPred:$u5), I32:$Rs), 0)), @@ -2235,12 +2259,6 @@ def ftoi : SDNodeXForm<fpimm, [{ def: Pat<(sra (i64 (add (sra I64:$src1, u6_0ImmPred:$src2), 1)), (i32 1)), (S2_asr_i_p_rnd I64:$src1, imm:$src2)>; -def SDTHexagonI32I64: SDTypeProfile<1, 1, [SDTCisVT<0, i32>, - SDTCisVT<1, i64>]>; -def HexagonPOPCOUNT: SDNode<"HexagonISD::POPCOUNT", SDTHexagonI32I64>; - -def: Pat<(HexagonPOPCOUNT I64:$Rss), (S5_popcountp I64:$Rss)>; - let AddedComplexity = 20 in { defm: Loadx_pat<load, f32, s30_2ImmPred, L2_loadri_io>; defm: Loadx_pat<load, f64, s29_3ImmPred, L2_loadrd_io>; @@ -2718,17 +2736,6 @@ def unalignedstore : PatFrag<(ops node:$val, node:$addr), (store $val, $addr), [ }]>; -def s4_6ImmPred: PatLeaf<(i32 imm), [{ - int64_t V = N->getSExtValue(); - return isShiftedInt<4,6>(V); -}]>; - -def s4_7ImmPred: PatLeaf<(i32 imm), [{ - int64_t V = N->getSExtValue(); - return isShiftedInt<4,7>(V); -}]>; - - multiclass vS32b_ai_pats <ValueType VTSgl, ValueType VTDbl> { // Aligned stores def : Pat<(alignedstore (VTSgl VectorRegs:$src1), IntRegs:$addr), @@ -2749,25 +2756,25 @@ multiclass vS32b_ai_pats <ValueType VTSgl, ValueType VTDbl> { // Fold Add R+OFF into vector store. let AddedComplexity = 10 in { def : Pat<(alignedstore (VTSgl VectorRegs:$src1), - (add IntRegs:$src2, s4_6ImmPred:$offset)), - (V6_vS32b_ai IntRegs:$src2, s4_6ImmPred:$offset, + (add IntRegs:$src2, Iss4_6:$offset)), + (V6_vS32b_ai IntRegs:$src2, Iss4_6:$offset, (VTSgl VectorRegs:$src1))>, Requires<[UseHVXSgl]>; def : Pat<(unalignedstore (VTSgl VectorRegs:$src1), - (add IntRegs:$src2, s4_6ImmPred:$offset)), - (V6_vS32Ub_ai IntRegs:$src2, s4_6ImmPred:$offset, + (add IntRegs:$src2, Iss4_6:$offset)), + (V6_vS32Ub_ai IntRegs:$src2, Iss4_6:$offset, (VTSgl VectorRegs:$src1))>, Requires<[UseHVXSgl]>; // Fold Add R+OFF into vector store 128B. def : Pat<(alignedstore (VTDbl VectorRegs128B:$src1), - (add IntRegs:$src2, s4_7ImmPred:$offset)), - (V6_vS32b_ai_128B IntRegs:$src2, s4_7ImmPred:$offset, + (add IntRegs:$src2, Iss4_7:$offset)), + (V6_vS32b_ai_128B IntRegs:$src2, Iss4_7:$offset, (VTDbl VectorRegs128B:$src1))>, Requires<[UseHVXDbl]>; def : Pat<(unalignedstore (VTDbl VectorRegs128B:$src1), - (add IntRegs:$src2, s4_7ImmPred:$offset)), - (V6_vS32Ub_ai_128B IntRegs:$src2, s4_7ImmPred:$offset, + (add IntRegs:$src2, Iss4_7:$offset)), + (V6_vS32Ub_ai_128B IntRegs:$src2, Iss4_7:$offset, (VTDbl VectorRegs128B:$src1))>, Requires<[UseHVXDbl]>; } @@ -2798,18 +2805,18 @@ multiclass vL32b_ai_pats <ValueType VTSgl, ValueType VTDbl> { // Fold Add R+OFF into vector load. let AddedComplexity = 10 in { - def : Pat<(VTDbl (alignedload (add IntRegs:$src2, s4_7ImmPred:$offset))), - (V6_vL32b_ai_128B IntRegs:$src2, s4_7ImmPred:$offset)>, + def : Pat<(VTDbl (alignedload (add IntRegs:$src2, Iss4_7:$offset))), + (V6_vL32b_ai_128B IntRegs:$src2, Iss4_7:$offset)>, Requires<[UseHVXDbl]>; - def : Pat<(VTDbl (unalignedload (add IntRegs:$src2, s4_7ImmPred:$offset))), - (V6_vL32Ub_ai_128B IntRegs:$src2, s4_7ImmPred:$offset)>, + def : Pat<(VTDbl (unalignedload (add IntRegs:$src2, Iss4_7:$offset))), + (V6_vL32Ub_ai_128B IntRegs:$src2, Iss4_7:$offset)>, Requires<[UseHVXDbl]>; - def : Pat<(VTSgl (alignedload (add IntRegs:$src2, s4_6ImmPred:$offset))), - (V6_vL32b_ai IntRegs:$src2, s4_6ImmPred:$offset)>, + def : Pat<(VTSgl (alignedload (add IntRegs:$src2, Iss4_6:$offset))), + (V6_vL32b_ai IntRegs:$src2, Iss4_6:$offset)>, Requires<[UseHVXSgl]>; - def : Pat<(VTSgl (unalignedload (add IntRegs:$src2, s4_6ImmPred:$offset))), - (V6_vL32Ub_ai IntRegs:$src2, s4_6ImmPred:$offset)>, + def : Pat<(VTSgl (unalignedload (add IntRegs:$src2, Iss4_6:$offset))), + (V6_vL32Ub_ai IntRegs:$src2, Iss4_6:$offset)>, Requires<[UseHVXSgl]>; } } @@ -3253,8 +3260,8 @@ def vmpyh: OutPatFrag<(ops node:$Rs, node:$Rt), (M2_vmpy2s_s0 (i32 $Rs), (i32 $Rt))>; def: Pat<(v2i16 (mul V2I16:$Rs, V2I16:$Rt)), - (LoReg (S2_vtrunewh (v2i32 (A2_combineii 0, 0)), - (v2i32 (vmpyh V2I16:$Rs, V2I16:$Rt))))>; + (LoReg (S2_vtrunewh (A2_combineii 0, 0), + (vmpyh V2I16:$Rs, V2I16:$Rt)))>; // Multiplies two v4i16 vectors. def: Pat<(v4i16 (mul V4I16:$Rs, V4I16:$Rt)), @@ -3345,3 +3352,11 @@ def: Pat<(v2i32 (zextloadv2i8 I32:$Rs)), def: Pat<(v2i32 (sextloadv2i8 I32:$Rs)), (S2_vsxthw (LoReg (v4i16 (S2_vsxtbh (L2_loadrh_io I32:$Rs, 0)))))>; + +// Read cycle counter. +// +def SDTInt64Leaf: SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>; +def HexagonREADCYCLE: SDNode<"HexagonISD::READCYCLE", SDTInt64Leaf, + [SDNPHasChain]>; + +def: Pat<(HexagonREADCYCLE), (A4_tfrcpp UPCYCLE)>; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonPseudo.td b/contrib/llvm/lib/Target/Hexagon/HexagonPseudo.td new file mode 100644 index 000000000000..5a720e794562 --- /dev/null +++ b/contrib/llvm/lib/Target/Hexagon/HexagonPseudo.td @@ -0,0 +1,537 @@ +//===--- HexagonPseudo.td -------------------------------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +let PrintMethod = "printGlobalOperand" in { + def globaladdress : Operand<i32>; + def globaladdressExt : Operand<i32>; +} + +let isPseudo = 1 in { +let isCodeGenOnly = 0 in +def A2_iconst : Pseudo<(outs IntRegs:$Rd32), (ins s23_2Imm:$Ii), "${Rd32}=iconst(#${Ii})">; +def DUPLEX_Pseudo : InstHexagon<(outs), (ins s32_0Imm:$offset), "DUPLEX", [], "", DUPLEX, TypePSEUDO>; +} + +let isExtendable = 1, opExtendable = 1, opExtentBits = 6, + isAsmParserOnly = 1 in +def TFRI64_V2_ext : ALU64_rr<(outs DoubleRegs:$dst), + (ins s32_0Imm:$src1, s8_0Imm:$src2), + "$dst=combine(#$src1,#$src2)">; + +// HI/LO Instructions +let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0, + hasNewValue = 1, opNewValue = 0 in +class REG_IMMED<string RegHalf, bit Rs, bits<3> MajOp, bit MinOp> + : InstHexagon<(outs IntRegs:$dst), + (ins u16_0Imm:$imm_value), + "$dst"#RegHalf#"=#$imm_value", [], "", ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, OpcodeHexagon { + bits<5> dst; + bits<32> imm_value; + + let Inst{27} = Rs; + let Inst{26-24} = MajOp; + let Inst{21} = MinOp; + let Inst{20-16} = dst; + let Inst{23-22} = imm_value{15-14}; + let Inst{13-0} = imm_value{13-0}; +} + +let isAsmParserOnly = 1 in { + def LO : REG_IMMED<".l", 0b0, 0b001, 0b1>; + def HI : REG_IMMED<".h", 0b0, 0b010, 0b1>; +} + +let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in { + def CONST32 : CONSTLDInst<(outs IntRegs:$Rd), (ins i32imm:$v), + "$Rd = CONST32(#$v)", []>; + def CONST64 : CONSTLDInst<(outs DoubleRegs:$Rd), (ins i64imm:$v), + "$Rd = CONST64(#$v)", []>; +} + +let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1, + isCodeGenOnly = 1 in +def PS_true : SInst<(outs PredRegs:$dst), (ins), "", []>; + +let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1, + isCodeGenOnly = 1 in +def PS_false : SInst<(outs PredRegs:$dst), (ins), "", []>; + +let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in +def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), + ".error \"should not emit\" ", []>; + +let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in +def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), + ".error \"should not emit\" ", []>; + + +let isBranch = 1, isTerminator = 1, hasSideEffects = 0, + Defs = [PC, LC0], Uses = [SA0, LC0] in { +def ENDLOOP0 : Endloop<(outs), (ins b30_2Imm:$offset), + ":endloop0", + []>; +} + +let isBranch = 1, isTerminator = 1, hasSideEffects = 0, + Defs = [PC, LC1], Uses = [SA1, LC1] in { +def ENDLOOP1 : Endloop<(outs), (ins b30_2Imm:$offset), + ":endloop1", + []>; +} + +let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2, + opExtendable = 0, hasSideEffects = 0 in +class LOOP_iBase<string mnemonic, Operand brOp, bit mustExtend = 0> + : CRInst<(outs), (ins brOp:$offset, u10_0Imm:$src2), + #mnemonic#"($offset,#$src2)", + [], "" , CR_tc_3x_SLOT3> { + bits<9> offset; + bits<10> src2; + + let IClass = 0b0110; + + let Inst{27-22} = 0b100100; + let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1); + let Inst{20-16} = src2{9-5}; + let Inst{12-8} = offset{8-4}; + let Inst{7-5} = src2{4-2}; + let Inst{4-3} = offset{3-2}; + let Inst{1-0} = src2{1-0}; +} + +let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2, + opExtendable = 0, hasSideEffects = 0 in +class LOOP_rBase<string mnemonic, Operand brOp, bit mustExtend = 0> + : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2), + #mnemonic#"($offset,$src2)", + [], "" ,CR_tc_3x_SLOT3> { + bits<9> offset; + bits<5> src2; + + let IClass = 0b0110; + + let Inst{27-22} = 0b000000; + let Inst{21} = !if (!eq(mnemonic, "loop0"), 0b0, 0b1); + let Inst{20-16} = src2; + let Inst{12-8} = offset{8-4}; + let Inst{4-3} = offset{3-2}; + } + +multiclass LOOP_ri<string mnemonic> { + let isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in { + def iext: LOOP_iBase<mnemonic, b30_2Imm, 1>; + def rext: LOOP_rBase<mnemonic, b30_2Imm, 1>; + } +} + + +let Defs = [SA0, LC0, USR] in +defm J2_loop0 : LOOP_ri<"loop0">; + +// Interestingly only loop0's appear to set usr.lpcfg +let Defs = [SA1, LC1] in +defm J2_loop1 : LOOP_ri<"loop1">; + +let isCall = 1, hasSideEffects = 1, isPredicable = 0, + isExtended = 0, isExtendable = 1, opExtendable = 0, + isExtentSigned = 1, opExtentBits = 24, opExtentAlign = 2 in +class T_Call<string ExtStr> + : JInst<(outs), (ins a30_2Imm:$dst), + "call " # ExtStr # "$dst", [], "", J_tc_2early_SLOT23> { + let BaseOpcode = "call"; + bits<24> dst; + + let IClass = 0b0101; + let Inst{27-25} = 0b101; + let Inst{24-16,13-1} = dst{23-2}; + let Inst{0} = 0b0; +} + +let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = [R16], + isPredicable = 0 in +def CALLProfile : T_Call<"">; + +let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, + Defs = [PC, R31, R6, R7, P0] in +def PS_call_stk : T_Call<"">; + +let isCall = 1, hasSideEffects = 1, cofMax1 = 1 in +class JUMPR_MISC_CALLR<bit isPred, bit isPredNot, + dag InputDag = (ins IntRegs:$Rs)> + : JInst<(outs), InputDag, + !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs", + "if ($Pu) callr $Rs"), + "callr $Rs"), + [], "", J_tc_2early_SLOT2> { + bits<5> Rs; + bits<2> Pu; + let isPredicated = isPred; + let isPredicatedFalse = isPredNot; + + let IClass = 0b0101; + let Inst{27-25} = 0b000; + let Inst{24-23} = !if (isPred, 0b10, 0b01); + let Inst{22} = 0; + let Inst{21} = isPredNot; + let Inst{9-8} = !if (isPred, Pu, 0b00); + let Inst{20-16} = Rs; + + } + +let isCodeGenOnly = 1 in { + def PS_callr_nr : JUMPR_MISC_CALLR<0, 1>; // Call, no return. +} + +let isCall = 1, hasSideEffects = 1, + isExtended = 0, isExtendable = 1, opExtendable = 0, isCodeGenOnly = 1, + BaseOpcode = "PS_call_nr", isExtentSigned = 1, opExtentAlign = 2, + Itinerary = J_tc_2early_SLOT23 in +class Call_nr<bits<5> nbits, bit isPred, bit isFalse, dag iops> + : Pseudo<(outs), iops, "">, PredRel { + bits<2> Pu; + bits<17> dst; + let opExtentBits = nbits; + let isPredicable = 0; // !if(isPred, 0, 1); + let isPredicated = 0; // isPred; + let isPredicatedFalse = isFalse; +} + +def PS_call_nr : Call_nr<24, 0, 0, (ins s32_0Imm:$Ii)>; +//def PS_call_nrt: Call_nr<17, 1, 0, (ins PredRegs:$Pu, s32_0Imm:$dst)>; +//def PS_call_nrf: Call_nr<17, 1, 1, (ins PredRegs:$Pu, s32_0Imm:$dst)>; + +let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC], + isPredicable = 1, hasSideEffects = 0, InputType = "reg", + cofMax1 = 1 in +class T_JMPr + : InstHexagon<(outs), (ins IntRegs:$dst), "jumpr $dst", [], + "", J_tc_2early_SLOT2, TypeJ>, OpcodeHexagon { + bits<5> dst; + + let IClass = 0b0101; + let Inst{27-21} = 0b0010100; + let Inst{20-16} = dst; +} + +// A return through builtin_eh_return. +let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0, + isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in +def EH_RETURN_JMPR : T_JMPr; + +// Indirect tail-call. +let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, + isTerminator = 1, isCodeGenOnly = 1 in +def PS_tailcall_r : T_JMPr; + +// +// Direct tail-calls. +let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, + isTerminator = 1, isCodeGenOnly = 1 in +def PS_tailcall_i : Pseudo<(outs), (ins a30_2Imm:$dst), "", []>; + +let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in +def PS_aligna : Pseudo<(outs IntRegs:$Rd), (ins u32_0Imm:$A), "", []>; + +// Generate frameindex addresses. The main reason for the offset operand is +// that every instruction that is allowed to have frame index as an operand +// will then have that operand followed by an immediate operand (the offset). +// This simplifies the frame-index elimination code. +// +let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1, + isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in { + def PS_fi : Pseudo<(outs IntRegs:$Rd), + (ins IntRegs:$fi, s32_0Imm:$off), "">; + def PS_fia : Pseudo<(outs IntRegs:$Rd), + (ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">; +} + +class CondStr<string CReg, bit True, bit New> { + string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") "; +} +class JumpOpcStr<string Mnemonic, bit New, bit Taken> { + string S = Mnemonic # !if(Taken, ":t", ":nt"); +} +let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1, + hasSideEffects = 0, InputType = "reg", cofMax1 = 1 in +class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak> + : InstHexagon<(outs), (ins PredRegs:$src, IntRegs:$dst), + CondStr<"$src", !if(PredNot,0,1), isPredNew>.S # + JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst", + [], "", J_tc_2early_SLOT2, TypeJ>, OpcodeHexagon { + + let isTaken = isTak; + let isPredicatedFalse = PredNot; + let isPredicatedNew = isPredNew; + bits<2> src; + bits<5> dst; + + let IClass = 0b0101; + + let Inst{27-22} = 0b001101; + let Inst{21} = PredNot; + let Inst{20-16} = dst; + let Inst{12} = isTak; + let Inst{11} = isPredNew; + let Inst{9-8} = src; +} +multiclass JMPR_Pred<bit PredNot> { + def NAME : T_JMPr_c<PredNot, 0, 0>; // not taken + // Predicate new + def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken + def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken +} +multiclass JMPR_base<string BaseOp> { + let BaseOpcode = BaseOp in { + def NAME : T_JMPr; + defm t : JMPR_Pred<0>; + defm f : JMPR_Pred<1>; + } +} +let isTerminator = 1, hasSideEffects = 0, isReturn = 1, isCodeGenOnly = 1, isBarrier = 1 in +defm PS_jmpret : JMPR_base<"JMPret">, PredNewRel; + +//defm V6_vtran2x2_map : HexagonMapping<(outs VectorRegs:$Vy32, VectorRegs:$Vx32), (ins VectorRegs:$Vx32in, IntRegs:$Rt32), "vtrans2x2(${Vy32},${Vx32},${Rt32})", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, VectorRegs:$Vx32in, IntRegs:$Rt32)>; + +// The reason for the custom inserter is to record all ALLOCA instructions +// in MachineFunctionInfo. +let Defs = [R29], isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 1 in +def PS_alloca: InstHexagon<(outs IntRegs:$Rd), + (ins IntRegs:$Rs, u32_0Imm:$A), "", + [], "", ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>; + +// Load predicate. +let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13, + isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in +def LDriw_pred : LDInst<(outs PredRegs:$dst), + (ins IntRegs:$addr, s32_0Imm:$off), + ".error \"should not emit\"", []>; + +// Load modifier. +let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13, + isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in +def LDriw_mod : LDInst<(outs ModRegs:$dst), + (ins IntRegs:$addr, s32_0Imm:$off), + ".error \"should not emit\"", []>; + +// Vector load +let Predicates = [HasV60T, UseHVX] in +let mayLoad = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in + class V6_LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = CVI_VM_LD, + IType type = TypeCVI_VM_LD> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>; + +// Vector store +let Predicates = [HasV60T, UseHVX] in +let mayStore = 1, validSubTargets = HasV60SubT, hasSideEffects = 0 in +class V6_STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = CVI_VM_ST, + IType type = TypeCVI_VM_ST> +: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>; + +let isCodeGenOnly = 1, isPseudo = 1 in +def PS_pselect : ALU64_rr<(outs DoubleRegs:$Rd), + (ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt), + ".error \"should not emit\" ", []>; + +let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0, + isPredicable = 1, + isExtendable = 1, opExtendable = 0, isExtentSigned = 1, + opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in +class T_JMP<string ExtStr> + : JInst_CJUMP_UCJUMP<(outs), (ins b30_2Imm:$dst), + "jump " # ExtStr # "$dst", + [], "", J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT> { + bits<24> dst; + let IClass = 0b0101; + + let Inst{27-25} = 0b100; + let Inst{24-16} = dst{23-15}; + let Inst{13-1} = dst{14-2}; +} + +// Restore registers and dealloc return function call. +let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1, + Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in { + def RESTORE_DEALLOC_RET_JMP_V4 : T_JMP<"">; + + let isExtended = 1, opExtendable = 0 in + def RESTORE_DEALLOC_RET_JMP_V4_EXT : T_JMP<"">; + + let Defs = [R14, R15, R28, R29, R30, R31, PC] in { + def RESTORE_DEALLOC_RET_JMP_V4_PIC : T_JMP<"">; + + let isExtended = 1, opExtendable = 0 in + def RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC : T_JMP<"">; + } +} + +// Restore registers and dealloc frame before a tail call. +let isCall = 1, Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in { + def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : T_Call<"">, PredRel; + + let isExtended = 1, opExtendable = 0 in + def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT : T_Call<"">, PredRel; + + let Defs = [R14, R15, R28, R29, R30, R31, PC] in { + def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_PIC : T_Call<"">, PredRel; + + let isExtended = 1, opExtendable = 0 in + def RESTORE_DEALLOC_BEFORE_TAILCALL_V4_EXT_PIC : T_Call<"">, PredRel; + } +} + +// Save registers function call. +let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in { + def SAVE_REGISTERS_CALL_V4 : T_Call<"">, PredRel; + + let isExtended = 1, opExtendable = 0 in + def SAVE_REGISTERS_CALL_V4_EXT : T_Call<"">, PredRel; + + let Defs = [P0] in + def SAVE_REGISTERS_CALL_V4STK : T_Call<"">, PredRel; + + let Defs = [P0], isExtended = 1, opExtendable = 0 in + def SAVE_REGISTERS_CALL_V4STK_EXT : T_Call<"">, PredRel; + + let Defs = [R14, R15, R28] in + def SAVE_REGISTERS_CALL_V4_PIC : T_Call<"">, PredRel; + + let Defs = [R14, R15, R28], isExtended = 1, opExtendable = 0 in + def SAVE_REGISTERS_CALL_V4_EXT_PIC : T_Call<"">, PredRel; + + let Defs = [R14, R15, R28, P0] in + def SAVE_REGISTERS_CALL_V4STK_PIC : T_Call<"">, PredRel; + + let Defs = [R14, R15, R28, P0], isExtended = 1, opExtendable = 0 in + def SAVE_REGISTERS_CALL_V4STK_EXT_PIC : T_Call<"">, PredRel; +} + +// Vector load/store pseudos + +let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in +class STrivv_template<RegisterClass RC> + : V6_STInst<(outs), (ins IntRegs:$addr, s32_0Imm:$off, RC:$src), "", []>; + +def PS_vstorerw_ai: STrivv_template<VecDblRegs>, + Requires<[HasV60T,UseHVXSgl]>; +def PS_vstorerwu_ai: STrivv_template<VecDblRegs>, + Requires<[HasV60T,UseHVXSgl]>; +def PS_vstorerw_ai_128B: STrivv_template<VecDblRegs128B>, + Requires<[HasV60T,UseHVXDbl]>; +def PS_vstorerwu_ai_128B: STrivv_template<VecDblRegs128B>, + Requires<[HasV60T,UseHVXDbl]>; + + +let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in +class LDrivv_template<RegisterClass RC> + : V6_LDInst<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off), "", []>; + +def PS_vloadrw_ai: LDrivv_template<VecDblRegs>, + Requires<[HasV60T,UseHVXSgl]>; +def PS_vloadrwu_ai: LDrivv_template<VecDblRegs>, + Requires<[HasV60T,UseHVXSgl]>; +def PS_vloadrw_ai_128B: LDrivv_template<VecDblRegs128B>, + Requires<[HasV60T,UseHVXDbl]>; +def PS_vloadrwu_ai_128B: LDrivv_template<VecDblRegs128B>, + Requires<[HasV60T,UseHVXDbl]>; + +// Store vector predicate pseudo. +let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13, + isCodeGenOnly = 1, isPseudo = 1, mayStore = 1, hasSideEffects = 0 in { + def PS_vstorerq_ai : STInst<(outs), + (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs:$src1), + ".error \"should not emit\" ", []>, + Requires<[HasV60T,UseHVXSgl]>; + + def PS_vstorerq_ai_128B : STInst<(outs), + (ins IntRegs:$base, s32_0Imm:$offset, VectorRegs:$src1), + ".error \"should not emit\" ", []>, + Requires<[HasV60T,UseHVXSgl]>; + + def PS_vloadrq_ai : STInst<(outs), + (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs128B:$src1), + ".error \"should not emit\" ", []>, + Requires<[HasV60T,UseHVXDbl]>; + + def PS_vloadrq_ai_128B : STInst<(outs), + (ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs128B:$src1), + ".error \"should not emit\" ", []>, + Requires<[HasV60T,UseHVXDbl]>; +} + +class VSELInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], + string cstr = "", InstrItinClass itin = CVI_VA_DV, + IType type = TypeCVI_VA_DV> + : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>; + +let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in { + def PS_vselect: VSELInst<(outs VectorRegs:$dst), + (ins PredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), "", []>, + Requires<[HasV60T,UseHVXSgl]>; + def PS_vselect_128B: VSELInst<(outs VectorRegs128B:$dst), + (ins PredRegs:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3), + "", []>, Requires<[HasV60T,UseHVXDbl]>; + def PS_wselect: VSELInst<(outs VecDblRegs:$dst), + (ins PredRegs:$src1, VecDblRegs:$src2, VecDblRegs:$src3), "", []>, + Requires<[HasV60T,UseHVXSgl]>; + def PS_wselect_128B: VSELInst<(outs VecDblRegs128B:$dst), + (ins PredRegs:$src1, VecDblRegs128B:$src2, VecDblRegs128B:$src3), + "", []>, Requires<[HasV60T,UseHVXDbl]>; +} + +// Store predicate. +let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13, + isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in +def STriw_pred : STInst<(outs), + (ins IntRegs:$addr, s32_0Imm:$off, PredRegs:$src1), + ".error \"should not emit\"", []>; +// Store modifier. +let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13, + isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in +def STriw_mod : STInst<(outs), + (ins IntRegs:$addr, s32_0Imm:$off, ModRegs:$src1), + ".error \"should not emit\"", []>; + +let isExtendable = 1, opExtendable = 1, opExtentBits = 6, + isAsmParserOnly = 1 in +def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u64_0Imm:$src1), + "$dst = #$src1">; + +// Hexagon doesn't have a vector multiply with C semantics. +// Instead, generate a pseudo instruction that gets expaneded into two +// scalar MPYI instructions. +// This is expanded by ExpandPostRAPseudos. +let isPseudo = 1 in +def PS_vmulw : PseudoM<(outs DoubleRegs:$Rd), + (ins DoubleRegs:$Rs, DoubleRegs:$Rt), "", []>; + +let isPseudo = 1 in +def PS_vmulw_acc : PseudoM<(outs DoubleRegs:$Rd), + (ins DoubleRegs:$Rx, DoubleRegs:$Rs, DoubleRegs:$Rt), "", [], + "$Rd = $Rx">; + +def DuplexIClass0: InstDuplex < 0 >; +def DuplexIClass1: InstDuplex < 1 >; +def DuplexIClass2: InstDuplex < 2 >; +let isExtendable = 1 in { + def DuplexIClass3: InstDuplex < 3 >; + def DuplexIClass4: InstDuplex < 4 >; + def DuplexIClass5: InstDuplex < 5 >; + def DuplexIClass6: InstDuplex < 6 >; + def DuplexIClass7: InstDuplex < 7 >; +} +def DuplexIClass8: InstDuplex < 8 >; +def DuplexIClass9: InstDuplex < 9 >; +def DuplexIClassA: InstDuplex < 0xA >; +def DuplexIClassB: InstDuplex < 0xB >; +def DuplexIClassC: InstDuplex < 0xC >; +def DuplexIClassD: InstDuplex < 0xD >; +def DuplexIClassE: InstDuplex < 0xE >; +def DuplexIClassF: InstDuplex < 0xF >; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp index 30640e19ebac..b3aba50b5625 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp @@ -94,7 +94,7 @@ struct HexagonDCE : public DeadCodeElimination { bool HexagonCP::interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) { - auto mapRegs = [MI,&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { + auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { EM.insert(std::make_pair(DstR, SrcR)); }; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp index d3f230d3f8a6..2a1bb63af789 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -36,6 +36,9 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" +#define GET_REGINFO_TARGET_DESC +#include "HexagonGenRegisterInfo.inc" + using namespace llvm; HexagonRegisterInfo::HexagonRegisterInfo() @@ -125,6 +128,7 @@ HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { case HexagonSubtarget::V5: case HexagonSubtarget::V55: case HexagonSubtarget::V60: + case HexagonSubtarget::V62: return HasEHReturn ? CalleeSavedRegsV3EHReturn : CalleeSavedRegsV3; } @@ -133,25 +137,47 @@ HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { } +const uint32_t *HexagonRegisterInfo::getCallPreservedMask( + const MachineFunction &MF, CallingConv::ID) const { + return HexagonCSR_RegMask; +} + + BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); Reserved.set(Hexagon::R29); Reserved.set(Hexagon::R30); Reserved.set(Hexagon::R31); - Reserved.set(Hexagon::PC); - Reserved.set(Hexagon::D14); - Reserved.set(Hexagon::D15); - Reserved.set(Hexagon::LC0); - Reserved.set(Hexagon::LC1); - Reserved.set(Hexagon::SA0); - Reserved.set(Hexagon::SA1); - Reserved.set(Hexagon::UGP); - Reserved.set(Hexagon::GP); - Reserved.set(Hexagon::CS0); - Reserved.set(Hexagon::CS1); - Reserved.set(Hexagon::CS); - Reserved.set(Hexagon::USR); + // Control registers. + Reserved.set(Hexagon::SA0); // C0 + Reserved.set(Hexagon::LC0); // C1 + Reserved.set(Hexagon::SA1); // C2 + Reserved.set(Hexagon::LC1); // C3 + Reserved.set(Hexagon::P3_0); // C4 + Reserved.set(Hexagon::USR); // C8 + Reserved.set(Hexagon::PC); // C9 + Reserved.set(Hexagon::UGP); // C10 + Reserved.set(Hexagon::GP); // C11 + Reserved.set(Hexagon::CS0); // C12 + Reserved.set(Hexagon::CS1); // C13 + Reserved.set(Hexagon::UPCYCLELO); // C14 + Reserved.set(Hexagon::UPCYCLEHI); // C15 + Reserved.set(Hexagon::FRAMELIMIT); // C16 + Reserved.set(Hexagon::FRAMEKEY); // C17 + Reserved.set(Hexagon::PKTCOUNTLO); // C18 + Reserved.set(Hexagon::PKTCOUNTHI); // C19 + Reserved.set(Hexagon::UTIMERLO); // C30 + Reserved.set(Hexagon::UTIMERHI); // C31 + // Out of the control registers, only C8 is explicitly defined in + // HexagonRegisterInfo.td. If others are defined, make sure to add + // them here as well. + Reserved.set(Hexagon::C8); + Reserved.set(Hexagon::USR_OVF); + + for (int x = Reserved.find_first(); x >= 0; x = Reserved.find_next(x)) + markSuperRegs(Reserved, x); + return Reserved; } @@ -267,6 +293,3 @@ unsigned HexagonRegisterInfo::getFirstCallerSavedNonParamReg() const { return Hexagon::R6; } - -#define GET_REGINFO_TARGET_DESC -#include "HexagonGenRegisterInfo.inc" diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h b/contrib/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h index 1fb295b5bd8c..8a3f175b8488 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h +++ b/contrib/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h @@ -35,7 +35,8 @@ public: /// Code Generation virtual methods... const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override; - + const uint32_t *getCallPreservedMask(const MachineFunction &MF, + CallingConv::ID) const override; BitVector getReservedRegs(const MachineFunction &MF) const override; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td b/contrib/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td index a75f3514dbd2..93ab2f731207 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td +++ b/contrib/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td @@ -140,41 +140,54 @@ let Namespace = "Hexagon" in { } // Control registers. - def SA0 : Rc<0, "sa0", ["c0"]>, DwarfRegNum<[67]>; - def LC0 : Rc<1, "lc0", ["c1"]>, DwarfRegNum<[68]>; - def SA1 : Rc<2, "sa1", ["c2"]>, DwarfRegNum<[69]>; - def LC1 : Rc<3, "lc1", ["c3"]>, DwarfRegNum<[70]>; - def P3_0 : Rc<4, "p3:0", ["c4"], [P0, P1, P2, P3]>, - DwarfRegNum<[71]>; - def C5 : Rc<5, "c5", ["c5"]>, DwarfRegNum<[72]>; // future use - def C6 : Rc<6, "c6", [], [M0]>, DwarfRegNum<[73]>; - def C7 : Rc<7, "c7", [], [M1]>, DwarfRegNum<[74]>; + def SA0: Rc<0, "sa0", ["c0"]>, DwarfRegNum<[67]>; + def LC0: Rc<1, "lc0", ["c1"]>, DwarfRegNum<[68]>; + def SA1: Rc<2, "sa1", ["c2"]>, DwarfRegNum<[69]>; + def LC1: Rc<3, "lc1", ["c3"]>, DwarfRegNum<[70]>; + def P3_0: Rc<4, "p3:0", ["c4"], [P0, P1, P2, P3]>, + DwarfRegNum<[71]>; + // When defining more Cn registers, make sure to explicitly mark them + // as reserved in HexagonRegisterInfo.cpp. + def C5: Rc<5, "c5", ["c5"]>, DwarfRegNum<[72]>; + def C6: Rc<6, "c6", [], [M0]>, DwarfRegNum<[73]>; + def C7: Rc<7, "c7", [], [M1]>, DwarfRegNum<[74]>; // Define C8 separately and make it aliased with USR. // The problem is that USR has subregisters (e.g. overflow). If USR was // specified as a subregister of C9_8, it would imply that subreg_overflow // and isub_lo can be composed, which leads to all kinds of issues // with lane masks. - def C8 : Rc<8, "c8", [], [USR]>, DwarfRegNum<[75]>; - def PC : Rc<9, "pc">, DwarfRegNum<[76]>; - def UGP : Rc<10, "ugp", ["c10"]>, DwarfRegNum<[77]>; - def GP : Rc<11, "gp", ["c11"]>, DwarfRegNum<[78]>; - def CS0 : Rc<12, "cs0", ["c12"]>, DwarfRegNum<[79]>; - def CS1 : Rc<13, "cs1", ["c13"]>, DwarfRegNum<[80]>; - def UPCL : Rc<14, "upcyclelo", ["c14"]>, DwarfRegNum<[81]>; - def UPCH : Rc<15, "upcyclehi", ["c15"]>, DwarfRegNum<[82]>; + def C8: Rc<8, "c8", [], [USR]>, DwarfRegNum<[75]>; + def PC: Rc<9, "pc">, DwarfRegNum<[76]>; + def UGP: Rc<10, "ugp", ["c10"]>, DwarfRegNum<[77]>; + def GP: Rc<11, "gp", ["c11"]>, DwarfRegNum<[78]>; + def CS0: Rc<12, "cs0", ["c12"]>, DwarfRegNum<[79]>; + def CS1: Rc<13, "cs1", ["c13"]>, DwarfRegNum<[80]>; + def UPCYCLELO: Rc<14, "upcyclelo", ["c14"]>, DwarfRegNum<[81]>; + def UPCYCLEHI: Rc<15, "upcyclehi", ["c15"]>, DwarfRegNum<[82]>; + def FRAMELIMIT: Rc<16, "framelimit", ["c16"]>, DwarfRegNum<[83]>; + def FRAMEKEY: Rc<17, "framekey", ["c17"]>, DwarfRegNum<[84]>; + def PKTCOUNTLO: Rc<18, "pktcountlo", ["c18"]>, DwarfRegNum<[85]>; + def PKTCOUNTHI: Rc<19, "pktcounthi", ["c19"]>, DwarfRegNum<[86]>; + def UTIMERLO: Rc<30, "utimerlo", ["c30"]>, DwarfRegNum<[97]>; + def UTIMERHI: Rc<31, "utimerhi", ["c31"]>, DwarfRegNum<[98]>; } // Control registers pairs. let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in { - def C1_0 : Rcc<0, "c1:0", [SA0, LC0], ["lc0:sa0"]>, DwarfRegNum<[67]>; - def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>; - def C5_4 : Rcc<4, "c5:4", [P3_0, C5]>, DwarfRegNum<[71]>; - def C7_6 : Rcc<6, "c7:6", [C6, C7], ["m1:0"]>, DwarfRegNum<[72]>; + def C1_0: Rcc<0, "c1:0", [SA0, LC0], ["lc0:sa0"]>, DwarfRegNum<[67]>; + def C3_2: Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>; + def C5_4: Rcc<4, "c5:4", [P3_0, C5]>, DwarfRegNum<[71]>; + def C7_6: Rcc<6, "c7:6", [C6, C7], ["m1:0"]>, DwarfRegNum<[72]>; // Use C8 instead of USR as a subregister of C9_8. - def C9_8 : Rcc<8, "c9:8", [C8, PC]>, DwarfRegNum<[74]>; - def C11_10 : Rcc<10, "c11:10", [UGP, GP]>, DwarfRegNum<[76]>; - def CS : Rcc<12, "c13:12", [CS0, CS1], ["cs1:0"]>, DwarfRegNum<[78]>; - def UPC : Rcc<14, "c15:14", [UPCL, UPCH]>, DwarfRegNum<[80]>; + def C9_8: Rcc<8, "c9:8", [C8, PC]>, DwarfRegNum<[74]>; + def C11_10: Rcc<10, "c11:10", [UGP, GP]>, DwarfRegNum<[76]>; + def CS: Rcc<12, "c13:12", [CS0, CS1], ["cs1:0"]>, DwarfRegNum<[78]>; + def UPCYCLE: Rcc<14, "c15:14", [UPCYCLELO, UPCYCLEHI]>, DwarfRegNum<[80]>; + def C17_16: Rcc<16, "c17:16", [FRAMELIMIT, FRAMEKEY]>, DwarfRegNum<[83]>; + def PKTCOUNT: Rcc<18, "c19:18", [PKTCOUNTLO, PKTCOUNTHI], ["pktcount"]>, + DwarfRegNum<[85]>; + def UTIMER: Rcc<30, "c31:30", [UTIMERLO, UTIMERHI], ["utimer"]>, + DwarfRegNum<[97]>; } foreach i = 0-31 in { @@ -219,6 +232,10 @@ def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32, } // Registers are listed in reverse order for allocation preference reasons. +def GeneralSubRegs : RegisterClass<"Hexagon", [i32], 32, + (add R23, R22, R21, R20, R19, R18, R17, + R16, R7, R6, R5, R4, R3, R2, R1, R0)>; + def IntRegsLow8 : RegisterClass<"Hexagon", [i32], 32, (add R7, R6, R5, R4, R3, R2, R1, R0)> ; @@ -226,6 +243,10 @@ def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64, (add (sequence "D%u", 0, 4), (sequence "D%u", 6, 13), D5, D14, D15)>; +def GeneralDoubleLow8Regs : RegisterClass<"Hexagon", [i64], 64, + (add D11, D10, D9, D8, D3, D2, D1, + D0)>; + def VectorRegs : RegisterClass<"Hexagon", [v64i8, v32i16, v16i32, v8i64], 512, (add (sequence "V%u", 0, 31))>; @@ -259,28 +280,28 @@ def ModRegs : RegisterClass<"Hexagon", [i32], 32, (add M0, M1)>; let Size = 32, isAllocatable = 0 in def CtrRegs : RegisterClass<"Hexagon", [i32], 32, - (add LC0, SA0, LC1, SA1, - P3_0, C5, - M0, M1, C6, C7, C8, CS0, CS1, UPCL, UPCH, - USR, UGP, GP, PC)>; + (add LC0, SA0, LC1, SA1, P3_0, C5, C6, C7, + C8, PC, UGP, GP, CS0, CS1, UPCYCLELO, UPCYCLEHI, + FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI, UTIMERLO, UTIMERHI, + M0, M1, USR)>; let isAllocatable = 0 in def UsrBits : RegisterClass<"Hexagon", [i1], 0, (add USR_OVF)>; let Size = 64, isAllocatable = 0 in def CtrRegs64 : RegisterClass<"Hexagon", [i64], 64, - (add C1_0, C3_2, C7_6, C9_8, C11_10, CS, UPC)>; - -def VolatileV3 { - list<Register> Regs = [D0, D1, D2, D3, D4, D5, D6, D7, - R28, R31, - P0, P1, P2, P3, - M0, M1, - LC0, LC1, SA0, SA1, USR, USR_OVF, CS0, CS1, - V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, - V12, V13, V14, V15, V16, V17, V18, V19, V20, V21, - V22, V23, V24, V25, V26, V27, V28, V29, V30, V31, - W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, - W12, W13, W14, W15, - Q0, Q1, Q2, Q3]; -} + (add C1_0, C3_2, C5_4, C7_6, C9_8, C11_10, CS, UPCYCLE, C17_16, + PKTCOUNT, UTIMER)>; + +// These registers are new for v62 and onward. +// The function RegisterMatchesArch() uses this list for validation. +let isAllocatable = 0 in +def V62Regs : RegisterClass<"Hexagon", [i32], 32, + (add FRAMELIMIT, FRAMEKEY, C17_16, + PKTCOUNTLO, PKTCOUNTHI, PKTCOUNT, + UTIMERLO, UTIMERHI, UTIMER)>; + + +def HexagonCSR + : CalleeSavedRegs<(add R16, R17, R18, R19, R20, R21, R22, R23, + R24, R25, R26, R27)>; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonSchedule.td b/contrib/llvm/lib/Target/Hexagon/HexagonSchedule.td index 6e4987b7e4e3..9b5fbea04d18 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonSchedule.td +++ b/contrib/llvm/lib/Target/Hexagon/HexagonSchedule.td @@ -21,4 +21,12 @@ include "HexagonScheduleV55.td" //===----------------------------------------------------------------------===// include "HexagonScheduleV60.td" +include "HexagonIICScalar.td" +include "HexagonIICHVX.td" + +//===----------------------------------------------------------------------===// +// V62 Machine Info + +//===----------------------------------------------------------------------===// + +include "HexagonScheduleV62.td" diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonScheduleV4.td b/contrib/llvm/lib/Target/Hexagon/HexagonScheduleV4.td index 7416baab392c..880cc0a02b6a 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonScheduleV4.td +++ b/contrib/llvm/lib/Target/Hexagon/HexagonScheduleV4.td @@ -61,15 +61,21 @@ def J_tc_2early_SLOT23 : InstrItinClass; def J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT : InstrItinClass; def J_tc_2early_SLOT2 : InstrItinClass; def LD_tc_ld_SLOT01 : InstrItinClass; +def LD_tc_ld_pi_SLOT01 : InstrItinClass; def LD_tc_ld_SLOT0 : InstrItinClass; def LD_tc_3or4stall_SLOT0 : InstrItinClass; def M_tc_2_SLOT23 : InstrItinClass; +def M_tc_2_acc_SLOT23 : InstrItinClass; def M_tc_3_SLOT23 : InstrItinClass; def M_tc_1_SLOT23 : InstrItinClass; def M_tc_3x_SLOT23 : InstrItinClass; +def M_tc_3x_acc_SLOT23 : InstrItinClass; def M_tc_3or4x_SLOT23 : InstrItinClass; +def M_tc_3or4x_acc_SLOT23 : InstrItinClass; def ST_tc_st_SLOT01 : InstrItinClass; +def ST_tc_st_pi_SLOT01 : InstrItinClass; def ST_tc_st_SLOT0 : InstrItinClass; +def ST_tc_st_pi_SLOT0 : InstrItinClass; def ST_tc_ld_SLOT0 : InstrItinClass; def ST_tc_3stall_SLOT0 : InstrItinClass; def S_2op_tc_1_SLOT23 : InstrItinClass; @@ -131,21 +137,27 @@ def HexagonItinerariesV4 : //Load InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData<LD_tc_ld_pi_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>]>, InstrItinData<LD_tc_3or4stall_SLOT0 , [InstrStage<1, [SLOT0]>]>, // M InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, InstrItinData<M_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<M_tc_2_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, InstrItinData<M_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, InstrItinData<M_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<M_tc_3x_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<M_tc_3or4x_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, // Store // ST InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData<ST_tc_st_pi_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, // ST0 InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>, + InstrItinData<ST_tc_st_pi_SLOT0 , [InstrStage<1, [SLOT0]>]>, InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>]>, // S diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonScheduleV55.td b/contrib/llvm/lib/Target/Hexagon/HexagonScheduleV55.td index b2a75f7200d7..06cbcb16abb7 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonScheduleV55.td +++ b/contrib/llvm/lib/Target/Hexagon/HexagonScheduleV55.td @@ -88,6 +88,8 @@ def HexagonItinerariesV55 : // Load InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], [2, 1]>, + InstrItinData<LD_tc_ld_pi_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], + [2, 1]>, InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<1, [SLOT0]>], [2, 1]>, InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>], [2, 1]>, @@ -96,21 +98,30 @@ def HexagonItinerariesV55 : [1, 1, 1]>, InstrItinData<M_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], [2, 1, 1]>, + InstrItinData<M_tc_2_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1]>, InstrItinData<M_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>, InstrItinData<M_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1]>, + InstrItinData<M_tc_3x_acc_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1, 1]>, InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1]>, + InstrItinData<M_tc_3or4x_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1]>, InstrItinData<M_tc_3stall_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1]>, // Store InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], [1, 1, 1]>, + InstrItinData<ST_tc_st_pi_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>], + [1, 1, 1]>, InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<1, [SLOT0]>], [2, 1, 1]>, InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>], [2, 1, 1]>, InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>], [1, 1, 1]>, + InstrItinData<ST_tc_st_pi_SLOT0 , [InstrStage<1, [SLOT0]>], [1, 1, 1]>, // S InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonScheduleV60.td b/contrib/llvm/lib/Target/Hexagon/HexagonScheduleV60.td index dc2ce43b0579..63784710f52b 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonScheduleV60.td +++ b/contrib/llvm/lib/Target/Hexagon/HexagonScheduleV60.td @@ -19,6 +19,8 @@ def CVI_LD : FuncUnit; def CVI_XLSHF : FuncUnit; def CVI_MPY01 : FuncUnit; def CVI_ALL : FuncUnit; +def CVI_XLMPY0 : FuncUnit; +def CVI_SHFMPY1: FuncUnit; // Combined functional unit data. def HexagonComboFuncsV60 : @@ -26,7 +28,9 @@ def HexagonComboFuncsV60 : ComboFuncData<CVI_XLSHF , [CVI_XLANE, CVI_SHIFT]>, ComboFuncData<CVI_MPY01 , [CVI_MPY0, CVI_MPY1]>, ComboFuncData<CVI_ALL , [CVI_ST, CVI_XLANE, CVI_SHIFT, - CVI_MPY0, CVI_MPY1, CVI_LD]> + CVI_MPY0, CVI_MPY1, CVI_LD]>, + ComboFuncData<CVI_XLMPY0 , [CVI_XLANE, CVI_MPY0]>, + ComboFuncData<CVI_SHFMPY1 , [CVI_SHIFT, CVI_MPY1]> ]>; // Note: When adding additional vector scheduling classes, add the @@ -39,6 +43,7 @@ def CVI_VX : InstrItinClass; def CVI_VX_DV_LONG : InstrItinClass; def CVI_VX_DV : InstrItinClass; def CVI_VX_DV_SLOT2 : InstrItinClass; +def CVI_VX_DV_SLOT2_LONG_EARLY : InstrItinClass; def CVI_VP : InstrItinClass; def CVI_VP_LONG : InstrItinClass; def CVI_VP_VS_EARLY : InstrItinClass; @@ -150,22 +155,28 @@ def HexagonItinerariesV60 : // Load InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>, + InstrItinData<LD_tc_ld_pi_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>, InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<4, [SLOT0]>]>, InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>, // M InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, InstrItinData<M_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>, + InstrItinData<M_tc_2_acc_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>, InstrItinData<M_tc_3_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>, InstrItinData<M_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>, + InstrItinData<M_tc_3x_acc_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>, InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<4, [SLOT2, SLOT3]>]>, + InstrItinData<M_tc_3or4x_acc_SLOT23 , [InstrStage<4, [SLOT2, SLOT3]>]>, InstrItinData<M_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>, // Store InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData<ST_tc_st_pi_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>, InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>, InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>, InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>, + InstrItinData<ST_tc_st_pi_SLOT0 , [InstrStage<1, [SLOT0]>]>, // S InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonScheduleV62.td b/contrib/llvm/lib/Target/Hexagon/HexagonScheduleV62.td new file mode 100644 index 000000000000..0758788a600b --- /dev/null +++ b/contrib/llvm/lib/Target/Hexagon/HexagonScheduleV62.td @@ -0,0 +1,129 @@ +//=-HexagonScheduleV62.td - HexagonV62 Scheduling Definitions *- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +// V62 follows the same schedule as V60 with following exceptions: +// Following instructions are permissible on any slot on V62: +// V4_J4_cmpeq_fp0_jump_nt +// V4_J4_cmpeq_fp0_jump_t +// V4_J4_cmpeq_fp1_jump_nt +// V4_J4_cmpeq_fp1_jump_t +// V4_J4_cmpeq_tp0_jump_nt +// V4_J4_cmpeq_tp0_jump_t +// V4_J4_cmpeq_tp1_jump_nt +// V4_J4_cmpeq_tp1_jump_t +// V4_J4_cmpeqi_fp0_jump_nt +// V4_J4_cmpeqi_fp0_jump_t +// V4_J4_cmpeqi_fp1_jump_nt +// V4_J4_cmpeqi_fp1_jump_t +// V4_J4_cmpeqi_tp0_jump_nt +// V4_J4_cmpeqi_tp0_jump_t +// V4_J4_cmpeqi_tp1_jump_nt +// V4_J4_cmpeqi_tp1_jump_t +// V4_J4_cmpeqn1_fp0_jump_nt +// V4_J4_cmpeqn1_fp0_jump_t +// V4_J4_cmpeqn1_fp1_jump_nt +// V4_J4_cmpeqn1_fp1_jump_t +// V4_J4_cmpeqn1_tp0_jump_nt +// V4_J4_cmpeqn1_tp0_jump_t +// V4_J4_cmpeqn1_tp1_jump_nt +// V4_J4_cmpeqn1_tp1_jump_t +// V4_J4_cmpgt_fp0_jump_nt +// V4_J4_cmpgt_fp0_jump_t +// V4_J4_cmpgt_fp1_jump_nt +// V4_J4_cmpgt_fp1_jump_t +// V4_J4_cmpgt_tp0_jump_nt +// V4_J4_cmpgt_tp0_jump_t +// V4_J4_cmpgt_tp1_jump_nt +// V4_J4_cmpgt_tp1_jump_t +// V4_J4_cmpgti_fp0_jump_nt +// V4_J4_cmpgti_fp0_jump_t +// V4_J4_cmpgti_fp1_jump_nt +// V4_J4_cmpgti_fp1_jump_t +// V4_J4_cmpgti_tp0_jump_nt +// V4_J4_cmpgti_tp0_jump_t +// V4_J4_cmpgti_tp1_jump_nt +// V4_J4_cmpgti_tp1_jump_t +// V4_J4_cmpgtn1_fp0_jump_nt +// V4_J4_cmpgtn1_fp0_jump_t +// V4_J4_cmpgtn1_fp1_jump_nt +// V4_J4_cmpgtn1_fp1_jump_t +// V4_J4_cmpgtn1_tp0_jump_nt +// V4_J4_cmpgtn1_tp0_jump_t +// V4_J4_cmpgtn1_tp1_jump_nt +// V4_J4_cmpgtn1_tp1_jump_t +// V4_J4_cmpgtu_fp0_jump_nt +// V4_J4_cmpgtu_fp0_jump_t +// V4_J4_cmpgtu_fp1_jump_nt +// V4_J4_cmpgtu_fp1_jump_t +// V4_J4_cmpgtu_tp0_jump_nt +// V4_J4_cmpgtu_tp0_jump_t +// V4_J4_cmpgtu_tp1_jump_nt +// V4_J4_cmpgtu_tp1_jump_t +// V4_J4_cmpgtui_fp0_jump_nt +// V4_J4_cmpgtui_fp0_jump_t +// V4_J4_cmpgtui_fp1_jump_nt +// V4_J4_cmpgtui_fp1_jump_t +// V4_J4_cmpgtui_tp0_jump_nt +// V4_J4_cmpgtui_tp0_jump_t +// V4_J4_cmpgtui_tp1_jump_nt +// V4_J4_cmpgtui_tp1_jump_t +// V4_J4_tstbit0_fp0_jump_nt +// V4_J4_tstbit0_fp0_jump_t +// V4_J4_tstbit0_fp1_jump_nt +// V4_J4_tstbit0_fp1_jump_t +// V4_J4_tstbit0_tp0_jump_nt +// V4_J4_tstbit0_tp0_jump_t +// V4_J4_tstbit0_tp1_jump_nt +// V4_J4_tstbit0_tp1_jump_t +// JMP +// JMPEXT +// JMPEXT_f +// JMPEXT_fnew_nt +// JMPEXT_fnew_t +// JMPEXT_t +// JMPEXT_tnew_nt +// JMPEXT_tnew_t +// JMPNOTEXT +// JMPNOTEXT_f +// JMPNOTEXT_fnew_nt +// JMPNOTEXT_fnew_t +// JMPNOTEXT_t +// JMPNOTEXT_tnew_nt +// JMPNOTEXT_tnew_t +// JMP_f +// JMP_fnew_nt +// JMP_fnew_t +// JMP_t +// JMP_tnew_nt +// JMP_tnew_t +// RESTORE_DEALLOC_RET_JMP_V4 +// RESTORE_DEALLOC_RET_JMP_V4_EXT + +def HexagonV62ItinList : ScalarItin, HVXV62Itin { + list<InstrItinData> ItinList = + !listconcat(ScalarItin_list, HVXV62Itin_list); +} + +def HexagonItinerariesV62 : + ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP, + CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1, + CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL], + [], HexagonV62ItinList.ItinList>; + +def HexagonModelV62 : SchedMachineModel { + // Max issue per cycle == bundle width. + let IssueWidth = 4; + let Itineraries = HexagonItinerariesV62; + let LoadLatency = 1; + let CompleteModel = 0; +} + +//===----------------------------------------------------------------------===// +// Hexagon V62 Resource Definitions - +//===----------------------------------------------------------------------===// diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp index 10730536080e..002e87fb32ce 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp @@ -51,11 +51,12 @@ SDValue HexagonSelectionDAGInfo::EmitTargetCodeForMemcpy( TargetLowering::CallLoweringInfo CLI(DAG); CLI.setDebugLoc(dl) .setChain(Chain) - .setCallee(TLI.getLibcallCallingConv(RTLIB::MEMCPY), - Type::getVoidTy(*DAG.getContext()), - DAG.getTargetExternalSymbol(SpecialMemcpyName, - TLI.getPointerTy(DAG.getDataLayout()), Flags), - std::move(Args)) + .setLibCallee( + TLI.getLibcallCallingConv(RTLIB::MEMCPY), + Type::getVoidTy(*DAG.getContext()), + DAG.getTargetExternalSymbol( + SpecialMemcpyName, TLI.getPointerTy(DAG.getDataLayout()), Flags), + std::move(Args)) .setDiscardResult(); std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI); diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp index 2c937216d463..471e32221b29 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp @@ -131,13 +131,15 @@ namespace { INITIALIZE_PASS(HexagonSplitDoubleRegs, "hexagon-split-double", "Hexagon Split Double Registers", false, false) -void HexagonSplitDoubleRegs::dump_partition(raw_ostream &os, +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) +LLVM_DUMP_METHOD void HexagonSplitDoubleRegs::dump_partition(raw_ostream &os, const USet &Part, const TargetRegisterInfo &TRI) { dbgs() << '{'; for (auto I : Part) dbgs() << ' ' << PrintReg(I, &TRI); dbgs() << " }"; } +#endif bool HexagonSplitDoubleRegs::isInduction(unsigned Reg, LoopRegMap &IRM) const { for (auto I : IRM) { @@ -391,7 +393,7 @@ int32_t HexagonSplitDoubleRegs::profit(const MachineInstr *MI) const { bool HexagonSplitDoubleRegs::isProfitable(const USet &Part, LoopRegMap &IRM) const { - unsigned FixedNum = 0, SplitNum = 0, LoopPhiNum = 0; + unsigned FixedNum = 0, LoopPhiNum = 0; int32_t TotalP = 0; for (unsigned DR : Part) { @@ -428,7 +430,6 @@ bool HexagonSplitDoubleRegs::isProfitable(const USet &Part, LoopRegMap &IRM) LoopPhiNum++; } // Splittable instruction. - SplitNum++; int32_t P = profit(UseI); if (P == std::numeric_limits<int>::min()) return false; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp index 8c23a2465dd6..033b93fc910a 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -88,6 +88,7 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { { "hexagonv5", V5 }, { "hexagonv55", V55 }, { "hexagonv60", V60 }, + { "hexagonv62", V62 }, }; auto foundIt = CpuTable.find(CPUString); diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/contrib/llvm/lib/Target/Hexagon/HexagonSubtarget.h index f2b9cdaad1ae..6a3e7f13be4c 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonSubtarget.h +++ b/contrib/llvm/lib/Target/Hexagon/HexagonSubtarget.h @@ -38,9 +38,7 @@ class HexagonSubtarget : public HexagonGenSubtargetInfo { bool ModeIEEERndNear; public: - enum HexagonArchEnum { - V4, V5, V55, V60 - }; +#include "HexagonDepArch.h" HexagonArchEnum HexagonArchVersion; /// True if the target should use Back-Skip-Back scheduling. This is the @@ -98,6 +96,9 @@ public: bool hasV55TOpsOnly() const { return getHexagonArchVersion() == V55; } bool hasV60TOps() const { return getHexagonArchVersion() >= V60; } bool hasV60TOpsOnly() const { return getHexagonArchVersion() == V60; } + bool hasV62TOps() const { return getHexagonArchVersion() >= V62; } + bool hasV62TOpsOnly() const { return getHexagonArchVersion() == V62; } + bool modeIEEERndNear() const { return ModeIEEERndNear; } bool useHVXOps() const { return UseHVXOps; } bool useHVXDblOps() const { return UseHVXOps && UseHVXDblOps; } diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonSystemInst.td b/contrib/llvm/lib/Target/Hexagon/HexagonSystemInst.td deleted file mode 100644 index 629a98749ee9..000000000000 --- a/contrib/llvm/lib/Target/Hexagon/HexagonSystemInst.td +++ /dev/null @@ -1,134 +0,0 @@ -//==- HexagonSystemInst.td - System Instructions for Hexagon -*- tablegen -*-==// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the Hexagon instructions in TableGen format. -// -//===----------------------------------------------------------------------===// - -//===----------------------------------------------------------------------===// -// Cache manipulation instructions. -//===----------------------------------------------------------------------===// -let mayStore = 1 in -class ST_MISC_CACHEOP<dag outs, dag ins, - string asmstr, list<dag> pattern = [], - bits<3> amode, bits<3> type, bits<1> un> - : ST0Inst<outs, ins, asmstr, pattern, "", ST_tc_ld_SLOT0> { - - bits<5> Rs; - bits<5> Rt; - bits<5> Rd; - let Inst{31-28} = 0b1010; - let Inst{27-25} = amode; - let Inst{24-22} = type; - let Inst{21} = un; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{4-0} = Rd; -} - -let mayStore = 1 in -class ST_MISC_CACHEOP_SYS<dag outs, dag ins, - string asmstr, list<dag> pattern = [], - bits<3> amode, bits<3> type, bits<1> un> - : SYSInst<outs, ins, asmstr, pattern, ""> { - - bits<5> Rs; - bits<5> Rt; - bits<5> Rd; - let Inst{31-28} = 0b1010; - let Inst{27-25} = amode; - let Inst{24-22} = type; - let Inst{21} = un; - let Inst{20-16} = Rs; - let Inst{12-8} = Rt; - let Inst{4-0} = Rd; -} - - -let isSolo = 1, Rs = 0, Rt = 0, Rd = 0 in { -def Y2_syncht: ST_MISC_CACHEOP <(outs), (ins), - "syncht" , [], 0b100, 0b001, 0b0>; -} - -let Rt = 0, Rd = 0 in { -let isSoloAin1 = 1 in { - def Y2_dccleana: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs), - "dccleana($Rs)", [], 0b000, 0b000, 0b0>; - def Y2_dcinva: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs), - "dcinva($Rs)", [], 0b000, 0b000, 0b1>; - def Y2_dccleaninva: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs), - "dccleaninva($Rs)", [], 0b000, 0b001, 0b0>; - } -} - -let isSoloAX = 1, hasSideEffects = 1, Rd = 0 in { - def Y4_l2fetch: ST_MISC_CACHEOP_SYS<(outs), (ins IntRegs:$Rs, IntRegs:$Rt), - "l2fetch($Rs, $Rt)", [], 0b011, 0b000, 0b0>; - def Y5_l2fetch: ST_MISC_CACHEOP_SYS<(outs), (ins IntRegs:$Rs, DoubleRegs:$Rt), - "l2fetch($Rs, $Rt)", [], 0b011, 0b010, 0b0>; -} - -let hasSideEffects = 0, isSolo = 1 in -class Y2_INVALIDATE_CACHE<string mnemonic, bit MajOp> - : JRInst < - (outs), (ins IntRegs:$Rs), - #mnemonic#"($Rs)" > { - bits<5> Rs; - - let IClass = 0b0101; - let Inst{27-21} = 0b0110110; - let Inst{20-16} = Rs; - let Inst{13-12} = 0b00; - let Inst{11} = MajOp; - } -// Instruction cache invalidate -def Y2_icinva : Y2_INVALIDATE_CACHE<"icinva", 0b0>; - -// Zero an aligned 32-byte cacheline. -let isSoloAin1 = 1 in -def Y2_dczeroa: ST0Inst <(outs), (ins IntRegs:$Rs), - "dczeroa($Rs)"> { - bits<5> Rs; - let IClass = 0b1010; - let Inst{27-21} = 0b0000110; - let Inst{13} = 0b0; - let Inst{20-16} = Rs; - } - -// Memory synchronization. -let hasSideEffects = 0, isSolo = 1 in -def Y2_isync: JRInst <(outs), (ins), - "isync"> { - let IClass = 0b0101; - let Inst{27-16} = 0b011111000000; - let Inst{13} = 0b0; - let Inst{9-0} = 0b0000000010; - } - -//===----------------------------------------------------------------------===// -// System/User instructions. -//===----------------------------------------------------------------------===// -// traps and pause -let hasSideEffects = 0, isSolo = 1 in -class J2_MISC_TRAP_PAUSE<string mnemonic, bits<2> MajOp> - : JRInst - <(outs), (ins u8_0Imm:$u8), - #mnemonic#"(#$u8)"> { - bits<8> u8; - - let IClass = 0b0101; - let Inst{27-24} = 0b0100; - let Inst{23-22} = MajOp; - let Inst{12-8} = u8{7-3}; - let Inst{4-2} = u8{2-0}; - } -def J2_trap0 : J2_MISC_TRAP_PAUSE<"trap0", 0b00>; -def J2_trap1 : J2_MISC_TRAP_PAUSE<"trap1", 0b10>; -def J2_pause : J2_MISC_TRAP_PAUSE<"pause", 0b01>; - diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp index 132d12a66d46..06fc9195fa67 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -24,6 +24,7 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Transforms/Scalar.h" +#include "llvm/Transforms/IPO/PassManagerBuilder.h" using namespace llvm; @@ -98,11 +99,6 @@ static cl::opt<bool> EnableVectorPrint("enable-hexagon-vector-print", extern "C" int HexagonTargetMachineModule; int HexagonTargetMachineModule = 0; -extern "C" void LLVMInitializeHexagonTarget() { - // Register the target. - RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget()); -} - static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) { return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>()); } @@ -114,6 +110,8 @@ SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", namespace llvm { extern char &HexagonExpandCondsetsID; void initializeHexagonExpandCondsetsPass(PassRegistry&); + void initializeHexagonLoopIdiomRecognizePass(PassRegistry&); + Pass *createHexagonLoopIdiomPass(); FunctionPass *createHexagonBitSimplify(); FunctionPass *createHexagonBranchRelaxation(); @@ -150,6 +148,12 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { return *RM; } +extern "C" void LLVMInitializeHexagonTarget() { + // Register the target. + RegisterTargetMachine<HexagonTargetMachine> X(getTheHexagonTarget()); + initializeHexagonLoopIdiomRecognizePass(*PassRegistry::getPassRegistry()); +} + HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, @@ -172,11 +176,11 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT, const HexagonSubtarget * HexagonTargetMachine::getSubtargetImpl(const Function &F) const { - AttributeSet FnAttrs = F.getAttributes(); + AttributeList FnAttrs = F.getAttributes(); Attribute CPUAttr = - FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu"); + FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-cpu"); Attribute FSAttr = - FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features"); + FnAttrs.getAttribute(AttributeList::FunctionIndex, "target-features"); std::string CPU = !CPUAttr.hasAttribute(Attribute::None) ? CPUAttr.getValueAsString().str() @@ -196,6 +200,14 @@ HexagonTargetMachine::getSubtargetImpl(const Function &F) const { return I.get(); } +void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) { + PMB.addExtension( + PassManagerBuilder::EP_LateLoopOptimizations, + [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) { + PM.add(createHexagonLoopIdiomPass()); + }); +} + TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() { return TargetIRAnalysis([this](const Function &F) { return TargetTransformInfo(HexagonTTIImpl(this, F)); diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonTargetMachine.h b/contrib/llvm/lib/Target/Hexagon/HexagonTargetMachine.h index 70835c0d4ac5..3d01929fbfb8 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonTargetMachine.h +++ b/contrib/llvm/lib/Target/Hexagon/HexagonTargetMachine.h @@ -37,6 +37,7 @@ public: static unsigned getModuleMatchQuality(const Module &M); + void adjustPassManager(PassManagerBuilder &PMB) override; TargetPassConfig *createPassConfig(PassManagerBase &PM) override; TargetIRAnalysis getTargetIRAnalysis() override; diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index 7b1247d815a5..3a789a5f7e0b 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -440,7 +440,7 @@ bool HexagonPacketizerList::promoteToDotNew(MachineInstr &MI, } bool HexagonPacketizerList::demoteToDotOld(MachineInstr &MI) { - int NewOpcode = HII->getDotOldOp(MI.getOpcode()); + int NewOpcode = HII->getDotOldOp(MI); MI.setDesc(HII->get(NewOpcode)); return true; } @@ -720,6 +720,8 @@ bool HexagonPacketizerList::canPromoteToNewValueStore(const MachineInstr &MI, // %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def> // S2_storerh_io %R8, 2, %R12<kill>; mem:ST2[%scevgep343] for (auto &MO : PacketMI.operands()) { + if (MO.isRegMask() && MO.clobbersPhysReg(DepReg)) + return false; if (!MO.isReg() || !MO.isDef() || !MO.isImplicit()) continue; unsigned R = MO.getReg(); @@ -759,9 +761,12 @@ bool HexagonPacketizerList::canPromoteToNewValue(const MachineInstr &MI, } static bool isImplicitDependency(const MachineInstr &I, unsigned DepReg) { - for (auto &MO : I.operands()) + for (auto &MO : I.operands()) { + if (MO.isRegMask() && MO.clobbersPhysReg(DepReg)) + return true; if (MO.isReg() && MO.isDef() && (MO.getReg() == DepReg) && MO.isImplicit()) return true; + } return false; } @@ -1046,7 +1051,9 @@ static bool cannotCoexistAsymm(const MachineInstr &MI, const MachineInstr &MJ, // XTYPE instructions. Since there is no convenient way of identifying fp // XTYPE instructions, only allow grouping with ALU32 for now. unsigned TJ = HII.getType(MJ); - if (TJ != HexagonII::TypeALU32) + if (TJ != HexagonII::TypeALU32_2op && + TJ != HexagonII::TypeALU32_3op && + TJ != HexagonII::TypeALU32_ADDI) return true; break; } @@ -1171,6 +1178,36 @@ bool HexagonPacketizerList::hasControlDependence(const MachineInstr &I, (J.isBranch() || J.isCall() || J.isBarrier()); } +bool HexagonPacketizerList::hasRegMaskDependence(const MachineInstr &I, + const MachineInstr &J) { + // Adding I to a packet that has J. + + // Regmasks are not reflected in the scheduling dependency graph, so + // we need to check them manually. This code assumes that regmasks only + // occur on calls, and the problematic case is when we add an instruction + // defining a register R to a packet that has a call that clobbers R via + // a regmask. Those cannot be packetized together, because the call will + // be executed last. That's also a reson why it is ok to add a call + // clobbering R to a packet that defines R. + + // Look for regmasks in J. + for (const MachineOperand &OpJ : J.operands()) { + if (!OpJ.isRegMask()) + continue; + assert((J.isCall() || HII->isTailCall(J)) && "Regmask on a non-call"); + for (const MachineOperand &OpI : I.operands()) { + if (OpI.isReg()) { + if (OpJ.clobbersPhysReg(OpI.getReg())) + return true; + } else if (OpI.isRegMask()) { + // Both are regmasks. Assume that they intersect. + return true; + } + } + } + return false; +} + bool HexagonPacketizerList::hasV4SpecificDependence(const MachineInstr &I, const MachineInstr &J) { bool SysI = isSystemInstr(I), SysJ = isSystemInstr(J); @@ -1217,6 +1254,14 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) { if (Dependence) return false; + // Regmasks are not accounted for in the scheduling graph, so we need + // to explicitly check for dependencies caused by them. They should only + // appear on calls, so it's not too pessimistic to reject all regmask + // dependencies. + Dependence = hasRegMaskDependence(I, J); + if (Dependence) + return false; + // V4 allows dual stores. It does not allow second store, if the first // store is not in SLOT0. New value store, new value jump, dealloc_return // and memop always take SLOT0. Arch spec 3.4.4.2. @@ -1465,13 +1510,19 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) { // R0 = ... ; SUI // Those cannot be packetized together, since the call will observe // the effect of the assignment to R0. - if (DepType == SDep::Anti && J.isCall()) { + if ((DepType == SDep::Anti || DepType == SDep::Output) && J.isCall()) { // Check if I defines any volatile register. We should also check // registers that the call may read, but these happen to be a // subset of the volatile register set. - for (const MCPhysReg *P = J.getDesc().ImplicitDefs; P && *P; ++P) { - if (!I.modifiesRegister(*P, HRI)) + for (const MachineOperand &Op : I.operands()) { + if (Op.isReg() && Op.isDef()) { + unsigned R = Op.getReg(); + if (!J.readsRegister(R, HRI) && !J.modifiesRegister(R, HRI)) + continue; + } else if (!Op.isRegMask()) { + // If I has a regmask assume dependency. continue; + } FoundSequentialDependence = true; break; } diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h b/contrib/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h index b28b926ec300..3f28dc5b79ce 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h +++ b/contrib/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h @@ -7,6 +7,9 @@ #include "llvm/CodeGen/ScheduleDAGInstrs.h" namespace llvm { +class HexagonInstrInfo; +class HexagonRegisterInfo; + class HexagonPacketizerList : public VLIWPacketizerList { // Vector of instructions assigned to the packet that has just been created. std::vector<MachineInstr*> OldPacketMIs; @@ -109,6 +112,7 @@ protected: void reserveResourcesForConstExt(); bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J); bool hasControlDependence(const MachineInstr &I, const MachineInstr &J); + bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J); bool hasV4SpecificDependence(const MachineInstr &I, const MachineInstr &J); bool producesStall(const MachineInstr &MI); }; diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp index c140bd1d7ee2..337af294eb86 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -9,10 +9,10 @@ #include "Hexagon.h" #include "HexagonFixupKinds.h" -#include "HexagonMCTargetDesc.h" #include "MCTargetDesc/HexagonBaseInfo.h" #include "MCTargetDesc/HexagonMCChecker.h" #include "MCTargetDesc/HexagonMCCodeEmitter.h" +#include "MCTargetDesc/HexagonMCTargetDesc.h" #include "MCTargetDesc/HexagonMCInstrInfo.h" #include "MCTargetDesc/HexagonMCShuffler.h" #include "llvm/MC/MCAsmBackend.h" @@ -59,9 +59,10 @@ class HexagonAsmBackend : public MCAsmBackend { RF.getFixups() = Fixups; } public: - HexagonAsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) : - OSABI(OSABI), MCII (T.createMCInstrInfo()), RelaxTarget(new MCInst *), - Extender(nullptr) {} + HexagonAsmBackend(const Target &T, const Triple &TT, uint8_t OSABI, + StringRef CPU) : + OSABI(OSABI), CPU(CPU), MCII(T.createMCInstrInfo()), + RelaxTarget(new MCInst *), Extender(nullptr) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { return createHexagonELFObjectWriter(OS, OSABI, CPU); @@ -88,101 +89,101 @@ public: // This table *must* be in same the order of fixup_* kinds in // HexagonFixupKinds.h. // - // namei offset bits flags - { "fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_Hexagon_LO16", 0, 32, 0 }, - { "fixup_Hexagon_HI16", 0, 32, 0 }, - { "fixup_Hexagon_32", 0, 32, 0 }, - { "fixup_Hexagon_16", 0, 32, 0 }, - { "fixup_Hexagon_8", 0, 32, 0 }, - { "fixup_Hexagon_GPREL16_0", 0, 32, 0 }, - { "fixup_Hexagon_GPREL16_1", 0, 32, 0 }, - { "fixup_Hexagon_GPREL16_2", 0, 32, 0 }, - { "fixup_Hexagon_GPREL16_3", 0, 32, 0 }, - { "fixup_Hexagon_HL16", 0, 32, 0 }, - { "fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_Hexagon_32_6_X", 0, 32, 0 }, - { "fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_Hexagon_16_X", 0, 32, 0 }, - { "fixup_Hexagon_12_X", 0, 32, 0 }, - { "fixup_Hexagon_11_X", 0, 32, 0 }, - { "fixup_Hexagon_10_X", 0, 32, 0 }, - { "fixup_Hexagon_9_X", 0, 32, 0 }, - { "fixup_Hexagon_8_X", 0, 32, 0 }, - { "fixup_Hexagon_7_X", 0, 32, 0 }, - { "fixup_Hexagon_6_X", 0, 32, 0 }, - { "fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_Hexagon_COPY", 0, 32, 0 }, - { "fixup_Hexagon_GLOB_DAT", 0, 32, 0 }, - { "fixup_Hexagon_JMP_SLOT", 0, 32, 0 }, - { "fixup_Hexagon_RELATIVE", 0, 32, 0 }, - { "fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_Hexagon_GOTREL_LO16", 0, 32, 0 }, - { "fixup_Hexagon_GOTREL_HI16", 0, 32, 0 }, - { "fixup_Hexagon_GOTREL_32", 0, 32, 0 }, - { "fixup_Hexagon_GOT_LO16", 0, 32, 0 }, - { "fixup_Hexagon_GOT_HI16", 0, 32, 0 }, - { "fixup_Hexagon_GOT_32", 0, 32, 0 }, - { "fixup_Hexagon_GOT_16", 0, 32, 0 }, - { "fixup_Hexagon_DTPMOD_32", 0, 32, 0 }, - { "fixup_Hexagon_DTPREL_LO16", 0, 32, 0 }, - { "fixup_Hexagon_DTPREL_HI16", 0, 32, 0 }, - { "fixup_Hexagon_DTPREL_32", 0, 32, 0 }, - { "fixup_Hexagon_DTPREL_16", 0, 32, 0 }, - { "fixup_Hexagon_GD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_Hexagon_LD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_Hexagon_GD_GOT_LO16", 0, 32, 0 }, - { "fixup_Hexagon_GD_GOT_HI16", 0, 32, 0 }, - { "fixup_Hexagon_GD_GOT_32", 0, 32, 0 }, - { "fixup_Hexagon_GD_GOT_16", 0, 32, 0 }, - { "fixup_Hexagon_LD_GOT_LO16", 0, 32, 0 }, - { "fixup_Hexagon_LD_GOT_HI16", 0, 32, 0 }, - { "fixup_Hexagon_LD_GOT_32", 0, 32, 0 }, - { "fixup_Hexagon_LD_GOT_16", 0, 32, 0 }, - { "fixup_Hexagon_IE_LO16", 0, 32, 0 }, - { "fixup_Hexagon_IE_HI16", 0, 32, 0 }, - { "fixup_Hexagon_IE_32", 0, 32, 0 }, - { "fixup_Hexagon_IE_16", 0, 32, 0 }, - { "fixup_Hexagon_IE_GOT_LO16", 0, 32, 0 }, - { "fixup_Hexagon_IE_GOT_HI16", 0, 32, 0 }, - { "fixup_Hexagon_IE_GOT_32", 0, 32, 0 }, - { "fixup_Hexagon_IE_GOT_16", 0, 32, 0 }, - { "fixup_Hexagon_TPREL_LO16", 0, 32, 0 }, - { "fixup_Hexagon_TPREL_HI16", 0, 32, 0 }, - { "fixup_Hexagon_TPREL_32", 0, 32, 0 }, - { "fixup_Hexagon_TPREL_16", 0, 32, 0 }, - { "fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, - { "fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0 }, - { "fixup_Hexagon_GOTREL_16_X", 0, 32, 0 }, - { "fixup_Hexagon_GOTREL_11_X", 0, 32, 0 }, - { "fixup_Hexagon_GOT_32_6_X", 0, 32, 0 }, - { "fixup_Hexagon_GOT_16_X", 0, 32, 0 }, - { "fixup_Hexagon_GOT_11_X", 0, 32, 0 }, - { "fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0 }, - { "fixup_Hexagon_DTPREL_16_X", 0, 32, 0 }, - { "fixup_Hexagon_DTPREL_11_X", 0, 32, 0 }, - { "fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0 }, - { "fixup_Hexagon_GD_GOT_16_X", 0, 32, 0 }, - { "fixup_Hexagon_GD_GOT_11_X", 0, 32, 0 }, - { "fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0 }, - { "fixup_Hexagon_LD_GOT_16_X", 0, 32, 0 }, - { "fixup_Hexagon_LD_GOT_11_X", 0, 32, 0 }, - { "fixup_Hexagon_IE_32_6_X", 0, 32, 0 }, - { "fixup_Hexagon_IE_16_X", 0, 32, 0 }, - { "fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0 }, - { "fixup_Hexagon_IE_GOT_16_X", 0, 32, 0 }, - { "fixup_Hexagon_IE_GOT_11_X", 0, 32, 0 }, - { "fixup_Hexagon_TPREL_32_6_X", 0, 32, 0 }, - { "fixup_Hexagon_TPREL_16_X", 0, 32, 0 }, - { "fixup_Hexagon_TPREL_11_X", 0, 32, 0 } + // namei offset bits flags + { "fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Hexagon_LO16", 0, 32, 0 }, + { "fixup_Hexagon_HI16", 0, 32, 0 }, + { "fixup_Hexagon_32", 0, 32, 0 }, + { "fixup_Hexagon_16", 0, 32, 0 }, + { "fixup_Hexagon_8", 0, 32, 0 }, + { "fixup_Hexagon_GPREL16_0", 0, 32, 0 }, + { "fixup_Hexagon_GPREL16_1", 0, 32, 0 }, + { "fixup_Hexagon_GPREL16_2", 0, 32, 0 }, + { "fixup_Hexagon_GPREL16_3", 0, 32, 0 }, + { "fixup_Hexagon_HL16", 0, 32, 0 }, + { "fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Hexagon_32_6_X", 0, 32, 0 }, + { "fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Hexagon_16_X", 0, 32, 0 }, + { "fixup_Hexagon_12_X", 0, 32, 0 }, + { "fixup_Hexagon_11_X", 0, 32, 0 }, + { "fixup_Hexagon_10_X", 0, 32, 0 }, + { "fixup_Hexagon_9_X", 0, 32, 0 }, + { "fixup_Hexagon_8_X", 0, 32, 0 }, + { "fixup_Hexagon_7_X", 0, 32, 0 }, + { "fixup_Hexagon_6_X", 0, 32, 0 }, + { "fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Hexagon_COPY", 0, 32, 0 }, + { "fixup_Hexagon_GLOB_DAT", 0, 32, 0 }, + { "fixup_Hexagon_JMP_SLOT", 0, 32, 0 }, + { "fixup_Hexagon_RELATIVE", 0, 32, 0 }, + { "fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Hexagon_GOTREL_LO16", 0, 32, 0 }, + { "fixup_Hexagon_GOTREL_HI16", 0, 32, 0 }, + { "fixup_Hexagon_GOTREL_32", 0, 32, 0 }, + { "fixup_Hexagon_GOT_LO16", 0, 32, 0 }, + { "fixup_Hexagon_GOT_HI16", 0, 32, 0 }, + { "fixup_Hexagon_GOT_32", 0, 32, 0 }, + { "fixup_Hexagon_GOT_16", 0, 32, 0 }, + { "fixup_Hexagon_DTPMOD_32", 0, 32, 0 }, + { "fixup_Hexagon_DTPREL_LO16", 0, 32, 0 }, + { "fixup_Hexagon_DTPREL_HI16", 0, 32, 0 }, + { "fixup_Hexagon_DTPREL_32", 0, 32, 0 }, + { "fixup_Hexagon_DTPREL_16", 0, 32, 0 }, + { "fixup_Hexagon_GD_PLT_B22_PCREL",0, 32, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Hexagon_LD_PLT_B22_PCREL",0, 32, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Hexagon_GD_GOT_LO16", 0, 32, 0 }, + { "fixup_Hexagon_GD_GOT_HI16", 0, 32, 0 }, + { "fixup_Hexagon_GD_GOT_32", 0, 32, 0 }, + { "fixup_Hexagon_GD_GOT_16", 0, 32, 0 }, + { "fixup_Hexagon_LD_GOT_LO16", 0, 32, 0 }, + { "fixup_Hexagon_LD_GOT_HI16", 0, 32, 0 }, + { "fixup_Hexagon_LD_GOT_32", 0, 32, 0 }, + { "fixup_Hexagon_LD_GOT_16", 0, 32, 0 }, + { "fixup_Hexagon_IE_LO16", 0, 32, 0 }, + { "fixup_Hexagon_IE_HI16", 0, 32, 0 }, + { "fixup_Hexagon_IE_32", 0, 32, 0 }, + { "fixup_Hexagon_IE_16", 0, 32, 0 }, + { "fixup_Hexagon_IE_GOT_LO16", 0, 32, 0 }, + { "fixup_Hexagon_IE_GOT_HI16", 0, 32, 0 }, + { "fixup_Hexagon_IE_GOT_32", 0, 32, 0 }, + { "fixup_Hexagon_IE_GOT_16", 0, 32, 0 }, + { "fixup_Hexagon_TPREL_LO16", 0, 32, 0 }, + { "fixup_Hexagon_TPREL_HI16", 0, 32, 0 }, + { "fixup_Hexagon_TPREL_32", 0, 32, 0 }, + { "fixup_Hexagon_TPREL_16", 0, 32, 0 }, + { "fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0 }, + { "fixup_Hexagon_GOTREL_16_X", 0, 32, 0 }, + { "fixup_Hexagon_GOTREL_11_X", 0, 32, 0 }, + { "fixup_Hexagon_GOT_32_6_X", 0, 32, 0 }, + { "fixup_Hexagon_GOT_16_X", 0, 32, 0 }, + { "fixup_Hexagon_GOT_11_X", 0, 32, 0 }, + { "fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0 }, + { "fixup_Hexagon_DTPREL_16_X", 0, 32, 0 }, + { "fixup_Hexagon_DTPREL_11_X", 0, 32, 0 }, + { "fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0 }, + { "fixup_Hexagon_GD_GOT_16_X", 0, 32, 0 }, + { "fixup_Hexagon_GD_GOT_11_X", 0, 32, 0 }, + { "fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0 }, + { "fixup_Hexagon_LD_GOT_16_X", 0, 32, 0 }, + { "fixup_Hexagon_LD_GOT_11_X", 0, 32, 0 }, + { "fixup_Hexagon_IE_32_6_X", 0, 32, 0 }, + { "fixup_Hexagon_IE_16_X", 0, 32, 0 }, + { "fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0 }, + { "fixup_Hexagon_IE_GOT_16_X", 0, 32, 0 }, + { "fixup_Hexagon_IE_GOT_11_X", 0, 32, 0 }, + { "fixup_Hexagon_TPREL_32_6_X", 0, 32, 0 }, + { "fixup_Hexagon_TPREL_16_X", 0, 32, 0 }, + { "fixup_Hexagon_TPREL_11_X", 0, 32, 0 } }; if (Kind < FirstTargetFixupKind) @@ -401,7 +402,8 @@ public: /// data fragment, at the offset specified by the fixup and following the /// fixup kind as appropriate. void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, - uint64_t FixupValue, bool IsPCRel) const override { + uint64_t FixupValue, bool IsPCRel, + MCContext &Ctx) const override { // When FixupValue is 0 the relocation is external and there // is nothing for us to do. @@ -524,10 +526,9 @@ public: bool Relaxable = false; // Branches and loop-setup insns are handled as necessary by relaxation. if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ || - (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == - HexagonII::TypeCOMPOUND && + (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCJ && MCID.isBranch()) || - (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNV && + (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNCJ && MCID.isBranch()) || (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR && HMI.getOpcode() != Hexagon::C4_addipc)) @@ -724,7 +725,8 @@ public: Size = 0; } } - bool Error = HexagonMCShuffle(*MCII, RF.getSubtargetInfo(), Inst); + bool Error = HexagonMCShuffle(true, *MCII, RF.getSubtargetInfo(), + Inst); //assert(!Error); (void)Error; ReplaceInstruction(Asm.getEmitter(), RF, Inst); @@ -739,15 +741,17 @@ public: } } } -}; -} // end anonymous namespace +}; // class HexagonAsmBackend -namespace llvm { -MCAsmBackend *createHexagonAsmBackend(Target const &T, +} // namespace + +// MCAsmBackend +MCAsmBackend *llvm::createHexagonAsmBackend(Target const &T, MCRegisterInfo const & /*MRI*/, const Triple &TT, StringRef CPU, const MCTargetOptions &Options) { uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); - return new HexagonAsmBackend(T, OSABI, CPU); -} + + StringRef CPUString = Hexagon_MC::selectHexagonCPU(TT, CPU); + return new HexagonAsmBackend(T, TT, OSABI, CPUString); } diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h index 4292f6b3faa4..9c80312b790d 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -17,6 +17,7 @@ #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H +#include "HexagonDepITypes.h" #include "HexagonMCTargetDesc.h" #include "llvm/Support/ErrorHandling.h" #include <stdint.h> @@ -27,57 +28,14 @@ namespace llvm { /// instruction info tracks. /// namespace HexagonII { - // *** The code below must match HexagonInstrFormat*.td *** // - - // Insn types. - // *** Must match HexagonInstrFormat*.td *** - enum Type { - TypePSEUDO = 0, - TypeALU32 = 1, - TypeCR = 2, - TypeJR = 3, - TypeJ = 4, - TypeLD = 5, - TypeST = 6, - TypeSYSTEM = 7, - TypeXTYPE = 8, - TypeV4LDST = 9, - TypeNV = 10, - TypeDUPLEX = 11, - TypeCOMPOUND = 12, - TypeCVI_FIRST = 13, - TypeCVI_VA = TypeCVI_FIRST, - TypeCVI_VA_DV = 14, - TypeCVI_VX = 15, - TypeCVI_VX_DV = 16, - TypeCVI_VP = 17, - TypeCVI_VP_VS = 18, - TypeCVI_VS = 19, - TypeCVI_VINLANESAT= 20, - TypeCVI_VM_LD = 21, - TypeCVI_VM_TMP_LD = 22, - TypeCVI_VM_CUR_LD = 23, - TypeCVI_VM_VP_LDU = 24, - TypeCVI_VM_ST = 25, - TypeCVI_VM_NEW_ST = 26, - TypeCVI_VM_STU = 27, - TypeCVI_HIST = 28, - TypeCVI_LAST = TypeCVI_HIST, - TypePREFIX = 30, // Such as extenders. - TypeENDLOOP = 31 // Such as end of a HW loop. - }; + unsigned const TypeCVI_FIRST = TypeCVI_HIST; + unsigned const TypeCVI_LAST = TypeCVI_VX_DV; enum SubTarget { - HasV2SubT = 0xf, - HasV2SubTOnly = 0x1, - NoV2SubT = 0x0, - HasV3SubT = 0xe, - HasV3SubTOnly = 0x2, - NoV3SubT = 0x1, - HasV4SubT = 0xc, - NoV4SubT = 0x3, - HasV5SubT = 0x8, - NoV5SubT = 0x7 + HasV4SubT = 0x3f, + HasV5SubT = 0x3e, + HasV55SubT = 0x3c, + HasV60SubT = 0x38, }; enum AddrMode { @@ -107,102 +65,101 @@ namespace HexagonII { enum { // This 5-bit field describes the insn type. TypePos = 0, - TypeMask = 0x1f, + TypeMask = 0x3f, // Solo instructions. - SoloPos = 5, + SoloPos = 6, SoloMask = 0x1, // Packed only with A or X-type instructions. - SoloAXPos = 6, + SoloAXPos = 7, SoloAXMask = 0x1, // Only A-type instruction in first slot or nothing. - SoloAin1Pos = 7, + SoloAin1Pos = 8, SoloAin1Mask = 0x1, // Predicated instructions. - PredicatedPos = 8, + PredicatedPos = 9, PredicatedMask = 0x1, - PredicatedFalsePos = 9, + PredicatedFalsePos = 10, PredicatedFalseMask = 0x1, - PredicatedNewPos = 10, + PredicatedNewPos = 11, PredicatedNewMask = 0x1, - PredicateLatePos = 11, + PredicateLatePos = 12, PredicateLateMask = 0x1, // New-Value consumer instructions. - NewValuePos = 12, + NewValuePos = 13, NewValueMask = 0x1, // New-Value producer instructions. - hasNewValuePos = 13, + hasNewValuePos = 14, hasNewValueMask = 0x1, // Which operand consumes or produces a new value. - NewValueOpPos = 14, + NewValueOpPos = 15, NewValueOpMask = 0x7, // Stores that can become new-value stores. - mayNVStorePos = 17, + mayNVStorePos = 18, mayNVStoreMask = 0x1, // New-value store instructions. - NVStorePos = 18, + NVStorePos = 19, NVStoreMask = 0x1, // Loads that can become current-value loads. - mayCVLoadPos = 19, + mayCVLoadPos = 20, mayCVLoadMask = 0x1, // Current-value load instructions. - CVLoadPos = 20, + CVLoadPos = 21, CVLoadMask = 0x1, // Extendable insns. - ExtendablePos = 21, + ExtendablePos = 22, ExtendableMask = 0x1, // Insns must be extended. - ExtendedPos = 22, + ExtendedPos = 23, ExtendedMask = 0x1, // Which operand may be extended. - ExtendableOpPos = 23, + ExtendableOpPos = 24, ExtendableOpMask = 0x7, // Signed or unsigned range. - ExtentSignedPos = 26, + ExtentSignedPos = 27, ExtentSignedMask = 0x1, // Number of bits of range before extending operand. - ExtentBitsPos = 27, + ExtentBitsPos = 28, ExtentBitsMask = 0x1f, // Alignment power-of-two before extending operand. - ExtentAlignPos = 32, + ExtentAlignPos = 33, ExtentAlignMask = 0x3, // Valid subtargets - validSubTargetPos = 34, - validSubTargetMask = 0xf, + validSubTargetPos = 35, + validSubTargetMask = 0x3f, // Addressing mode for load/store instructions. - AddrModePos = 40, + AddrModePos = 41, AddrModeMask = 0x7, // Access size for load/store instructions. - MemAccessSizePos = 43, + MemAccessSizePos = 44, MemAccesSizeMask = 0xf, // Branch predicted taken. - TakenPos = 47, + TakenPos = 48, TakenMask = 0x1, // Floating-point instructions. - FPPos = 48, + FPPos = 49, FPMask = 0x1, // New-Value producer-2 instructions. - hasNewValuePos2 = 50, + hasNewValuePos2 = 51, hasNewValueMask2 = 0x1, - // Which operand consumes or produces a new value. - NewValueOpPos2 = 51, + NewValueOpPos2 = 52, NewValueOpMask2 = 0x7, // Accumulator instructions. - AccumulatorPos = 54, + AccumulatorPos = 55, AccumulatorMask = 0x1, // Complex XU, prevent xu competition by preferring slot3 - PrefersSlot3Pos = 55, + PrefersSlot3Pos = 56, PrefersSlot3Mask = 0x1, CofMax1Pos = 60, @@ -217,8 +174,6 @@ namespace HexagonII { // Hexagon Specific MachineOperand flags. MO_NO_FLAG, - HMOTF_ConstExtended = 1, - /// MO_PCREL - On a symbol operand, indicates a PC-relative relocation /// Used for computing a global address for PIC compilations MO_PCREL, @@ -250,7 +205,13 @@ namespace HexagonII { // MO_TPREL - indicates relocation for TLS // local Executable method - MO_TPREL + MO_TPREL, + + // HMOTF_ConstExtended + // Addendum to abovem, indicates a const extended op + // Can be used as a mask. + HMOTF_ConstExtended = 0x80 + }; // Hexagon Sub-instruction classes. diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp index 42fcc5a6aa89..dd790fd41257 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp @@ -125,46 +125,6 @@ void HexagonInstPrinter::printNOneImmOperand(MCInst const *MI, unsigned OpNo, O << -1; } -void HexagonInstPrinter::prints3_6ImmOperand(MCInst const *MI, unsigned OpNo, - raw_ostream &O) const { - int64_t Imm; - bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm); - Imm = SignExtend64<9>(Imm); - assert(Success); (void)Success; - assert(((Imm & 0x3f) == 0) && "Lower 6 bits must be ZERO."); - O << formatImm(Imm/64); -} - -void HexagonInstPrinter::prints3_7ImmOperand(MCInst const *MI, unsigned OpNo, - raw_ostream &O) const { - int64_t Imm; - bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm); - Imm = SignExtend64<10>(Imm); - assert(Success); (void)Success; - assert(((Imm & 0x7f) == 0) && "Lower 7 bits must be ZERO."); - O << formatImm(Imm/128); -} - -void HexagonInstPrinter::prints4_6ImmOperand(MCInst const *MI, unsigned OpNo, - raw_ostream &O) const { - int64_t Imm; - bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm); - Imm = SignExtend64<10>(Imm); - assert(Success); (void)Success; - assert(((Imm & 0x3f) == 0) && "Lower 6 bits must be ZERO."); - O << formatImm(Imm/64); -} - -void HexagonInstPrinter::prints4_7ImmOperand(MCInst const *MI, unsigned OpNo, - raw_ostream &O) const { - int64_t Imm; - bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm); - Imm = SignExtend64<11>(Imm); - assert(Success); (void)Success; - assert(((Imm & 0x7f) == 0) && "Lower 7 bits must be ZERO."); - O << formatImm(Imm/128); -} - void HexagonInstPrinter::printGlobalOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const { printOperand(MI, OpNo, O); diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h index 5f421184b20a..ac8e391905e0 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h @@ -44,14 +44,6 @@ public: raw_ostream &O) const; void printNOneImmOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const; - void prints3_6ImmOperand(MCInst const *MI, unsigned OpNo, - raw_ostream &O) const; - void prints3_7ImmOperand(MCInst const *MI, unsigned OpNo, - raw_ostream &O) const; - void prints4_6ImmOperand(MCInst const *MI, unsigned OpNo, - raw_ostream &O) const; - void prints4_7ImmOperand(MCInst const *MI, unsigned OpNo, - raw_ostream &O) const; void printBranchOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const; void printCallOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const; diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp index c619c36164cf..446b3b2ce668 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp @@ -23,6 +23,7 @@ HexagonMCAsmInfo::HexagonMCAsmInfo(const Triple &TT) { Data32bitsDirective = "\t.word\t"; Data64bitsDirective = nullptr; // .xword is only supported by V9. CommentString = "//"; + SupportsDebugInformation = true; LCOMMDirectiveAlignmentType = LCOMM::ByteAlignment; InlineAsmStart = "# InlineAsm Start"; @@ -30,8 +31,8 @@ HexagonMCAsmInfo::HexagonMCAsmInfo(const Triple &TT) { ZeroDirective = "\t.space\t"; AscizDirective = "\t.string\t"; - SupportsDebugInformation = true; MinInstAlignment = 4; UsesELFSectionDirectiveForBSS = true; ExceptionsType = ExceptionHandling::DwarfCFI; + UseLogicalShr = false; } diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp index 07c9ad96a0d7..62b21c419f30 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp @@ -47,12 +47,40 @@ void HexagonMCChecker::init() { if (HexagonMCInstrInfo::isBundle(MCB)) // Unfurl a bundle. for (auto const&I : HexagonMCInstrInfo::bundleInstructions(MCB)) { - init(*I.getInst()); + MCInst const &Inst = *I.getInst(); + if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) { + init(*Inst.getOperand(0).getInst()); + init(*Inst.getOperand(1).getInst()); + } + else + init(Inst); } else init(MCB); } +void HexagonMCChecker::initReg(MCInst const &MCI, unsigned R, unsigned &PredReg, + bool &isTrue) { + if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && isPredicateRegister(R)) { + // Note an used predicate register. + PredReg = R; + isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI); + + // Note use of new predicate register. + if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) + NewPreds.insert(PredReg); + } + else + // Note register use. Super-registers are not tracked directly, + // but their components. + for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); + SRI.isValid(); + ++SRI) + if (!MCSubRegIterator(*SRI, &RI).isValid()) + // Skip super-registers used indirectly. + Uses.insert(*SRI); +} + void HexagonMCChecker::init(MCInst const& MCI) { const MCInstrDesc& MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); unsigned PredReg = Hexagon::NoRegister; @@ -60,28 +88,10 @@ void HexagonMCChecker::init(MCInst const& MCI) { // Get used registers. for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i) - if (MCI.getOperand(i).isReg()) { - unsigned R = MCI.getOperand(i).getReg(); - - if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && isPredicateRegister(R)) { - // Note an used predicate register. - PredReg = R; - isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI); - - // Note use of new predicate register. - if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) - NewPreds.insert(PredReg); - } - else - // Note register use. Super-registers are not tracked directly, - // but their components. - for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); - SRI.isValid(); - ++SRI) - if (!MCSubRegIterator(*SRI, &RI).isValid()) - // Skip super-registers used indirectly. - Uses.insert(*SRI); - } + if (MCI.getOperand(i).isReg()) + initReg(MCI, MCI.getOperand(i).getReg(), PredReg, isTrue); + for (unsigned i = 0; i < MCID.getNumImplicitUses(); ++i) + initReg(MCI, MCID.getImplicitUses()[i], PredReg, isTrue); // Get implicit register definitions. if (const MCPhysReg *ImpDef = MCID.getImplicitDefs()) @@ -216,9 +226,11 @@ void HexagonMCChecker::init(MCInst const& MCI) { if (!MCSubRegIterator(N, &RI).isValid()) { // Super-registers cannot use new values. if (MCID.isBranch()) - NewUses[N] = NewSense::Jmp(llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNV); + NewUses[N] = NewSense::Jmp( + llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNCJ); else - NewUses[N] = NewSense::Use(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI)); + NewUses[N] = NewSense::Use( + PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI)); } } } @@ -230,14 +242,18 @@ HexagonMCChecker::HexagonMCChecker(MCInstrInfo const &MCII, MCSubtargetInfo cons init(); } -bool HexagonMCChecker::check() { +bool HexagonMCChecker::check(bool FullCheck) { bool chkB = checkBranches(); bool chkP = checkPredicates(); bool chkNV = checkNewValues(); bool chkR = checkRegisters(); bool chkS = checkSolo(); - bool chkSh = checkShuffle(); - bool chkSl = checkSlots(); + bool chkSh = true; + if (FullCheck) + chkSh = checkShuffle(); + bool chkSl = true; + if (FullCheck) + chkSl = checkSlots(); bool chk = chkB && chkP && chkNV && chkR && chkS && chkSh && chkSl; return chk; @@ -271,8 +287,8 @@ bool HexagonMCChecker::checkBranches() { HexagonMCErrInfo errInfo; if (HexagonMCInstrInfo::isBundle(MCB)) { bool hasConditional = false; - unsigned Branches = 0, Returns = 0, NewIndirectBranches = 0, - NewValueBranches = 0, Conditional = HEXAGON_PRESHUFFLE_PACKET_SIZE, + unsigned Branches = 0, + Conditional = HEXAGON_PRESHUFFLE_PACKET_SIZE, Unconditional = HEXAGON_PRESHUFFLE_PACKET_SIZE; for (unsigned i = HexagonMCInstrInfo::bundleInstructionsOffset; @@ -284,12 +300,6 @@ bool HexagonMCChecker::checkBranches() { if (HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch() || HexagonMCInstrInfo::getDesc(MCII, MCI).isCall()) { ++Branches; - if (HexagonMCInstrInfo::getDesc(MCII, MCI).isIndirectBranch() && - HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) - ++NewIndirectBranches; - if (HexagonMCInstrInfo::isNewValue(MCII, MCI)) - ++NewValueBranches; - if (HexagonMCInstrInfo::isPredicated(MCII, MCI) || HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) { hasConditional = true; @@ -298,9 +308,6 @@ bool HexagonMCChecker::checkBranches() { Unconditional = i; // Record the position of the unconditional branch. } } - if (HexagonMCInstrInfo::getDesc(MCII, MCI).isReturn() && - HexagonMCInstrInfo::getDesc(MCII, MCI).mayLoad()) - ++Returns; } if (Branches) // FIXME: should "Defs.count(Hexagon::PC)" be here too? @@ -504,7 +511,7 @@ bool HexagonMCChecker::checkShuffle() { HexagonMCErrInfo errInfo; // Branch info is lost when duplexing. The unduplexed insns must be // checked and only branch errors matter for this case. - HexagonMCShuffler MCS(MCII, STI, MCB); + HexagonMCShuffler MCS(true, MCII, STI, MCB); if (!MCS.check()) { if (MCS.getError() == HexagonShuffler::SHUFFLE_ERROR_BRANCHES) { errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_SHUFFLE); @@ -513,7 +520,7 @@ bool HexagonMCChecker::checkShuffle() { return false; } } - HexagonMCShuffler MCSDX(MCII, STI, MCBDX); + HexagonMCShuffler MCSDX(true, MCII, STI, MCBDX); if (!MCSDX.check()) { errInfo.setError(HexagonMCErrInfo::CHECK_ERROR_SHUFFLE); errInfo.setShuffleError(MCSDX.getError()); diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h index 33e22798c954..c3b3d4c14c88 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h @@ -168,6 +168,7 @@ class HexagonMCChecker { void init(); void init(MCInst const&); + void initReg(MCInst const &, unsigned, unsigned &PredReg, bool &isTrue); // Checks performed. bool checkBranches(); @@ -177,6 +178,7 @@ class HexagonMCChecker { bool checkSolo(); bool checkShuffle(); bool checkSlots(); + bool checkSize(); static void compoundRegisterMap(unsigned&); @@ -196,7 +198,7 @@ class HexagonMCChecker { explicit HexagonMCChecker(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst& mcb, MCInst &mcbdx, const MCRegisterInfo& ri); - bool check(); + bool check(bool FullCheck = true); /// add a new error/warning void addErrInfo(HexagonMCErrInfo &err) { ErrInfoQ.push(err.s); }; diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp index 2645a17b9bd0..c0956520de73 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp @@ -35,38 +35,40 @@ STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII, MCContext &aMCT) : MCT(aMCT), MCII(aMII), Addend(new unsigned(0)), - Extended(new bool(false)), CurrentBundle(new MCInst const *) {} + Extended(new bool(false)), CurrentBundle(new MCInst const *), + CurrentIndex(new size_t(0)) {} -uint32_t HexagonMCCodeEmitter::parseBits(size_t Instruction, size_t Last, +uint32_t HexagonMCCodeEmitter::parseBits(size_t Last, MCInst const &MCB, MCInst const &MCI) const { bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI); - if (Instruction == 0) { + if (*CurrentIndex == 0) { if (HexagonMCInstrInfo::isInnerLoop(MCB)) { assert(!Duplex); - assert(Instruction != Last); + assert(*CurrentIndex != Last); return HexagonII::INST_PARSE_LOOP_END; } } - if (Instruction == 1) { + if (*CurrentIndex == 1) { if (HexagonMCInstrInfo::isOuterLoop(MCB)) { assert(!Duplex); - assert(Instruction != Last); + assert(*CurrentIndex != Last); return HexagonII::INST_PARSE_LOOP_END; } } if (Duplex) { - assert(Instruction == Last); + assert(*CurrentIndex == Last); return HexagonII::INST_PARSE_DUPLEX; } - if(Instruction == Last) + if(*CurrentIndex == Last) return HexagonII::INST_PARSE_PACKET_END; return HexagonII::INST_PARSE_NOT_END; } -void HexagonMCCodeEmitter::encodeInstruction(MCInst const &MI, raw_ostream &OS, +/// EncodeInstruction - Emit the bundle +void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, - MCSubtargetInfo const &STI) const { + const MCSubtargetInfo &STI) const { MCInst &HMB = const_cast<MCInst &>(MI); assert(HexagonMCInstrInfo::isBundle(HMB)); @@ -74,7 +76,7 @@ void HexagonMCCodeEmitter::encodeInstruction(MCInst const &MI, raw_ostream &OS, *Addend = 0; *Extended = false; *CurrentBundle = &MI; - size_t Instruction = 0; + *CurrentIndex = 0; size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1; for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) { MCInst &HMI = const_cast<MCInst &>(*I.getInst()); @@ -82,11 +84,10 @@ void HexagonMCCodeEmitter::encodeInstruction(MCInst const &MI, raw_ostream &OS, computeAvailableFeatures(STI.getFeatureBits())); EncodeSingleInstruction(HMI, OS, Fixups, STI, - parseBits(Instruction, Last, HMB, HMI), - Instruction); + parseBits(Last, HMB, HMI)); *Extended = HexagonMCInstrInfo::isImmext(HMI); *Addend += HEXAGON_INSTR_SIZE; - ++Instruction; + ++*CurrentIndex; } return; } @@ -107,165 +108,44 @@ static bool RegisterMatches(unsigned Consumer, unsigned Producer, /// EncodeSingleInstruction - Emit a single void HexagonMCCodeEmitter::EncodeSingleInstruction( const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, - const MCSubtargetInfo &STI, uint32_t Parse, size_t Index) const { - MCInst HMB = MI; - assert(!HexagonMCInstrInfo::isBundle(HMB)); + const MCSubtargetInfo &STI, uint32_t Parse) const { + assert(!HexagonMCInstrInfo::isBundle(MI)); uint64_t Binary; - // Compound instructions are limited to using registers 0-7 and 16-23 - // and here we make a map 16-23 to 8-15 so they can be correctly encoded. - static unsigned RegMap[8] = {Hexagon::R8, Hexagon::R9, Hexagon::R10, - Hexagon::R11, Hexagon::R12, Hexagon::R13, - Hexagon::R14, Hexagon::R15}; - // Pseudo instructions don't get encoded and shouldn't be here // in the first place! - assert(!HexagonMCInstrInfo::getDesc(MCII, HMB).isPseudo() && + assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo() && "pseudo-instruction found"); DEBUG(dbgs() << "Encoding insn" - " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'" + " `" << HexagonMCInstrInfo::getName(MCII, MI) << "'" "\n"); - if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCOMPOUND) { - for (unsigned i = 0; i < HMB.getNumOperands(); ++i) - if (HMB.getOperand(i).isReg()) { - unsigned Reg = - MCT.getRegisterInfo()->getEncodingValue(HMB.getOperand(i).getReg()); - if ((Reg <= 23) && (Reg >= 16)) - HMB.getOperand(i).setReg(RegMap[Reg - 16]); - } - } - - if (HexagonMCInstrInfo::isNewValue(MCII, HMB)) { - // Calculate the new value distance to the associated producer - MCOperand &MCO = - HMB.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, HMB)); - unsigned SOffset = 0; - unsigned VOffset = 0; - unsigned Register = MCO.getReg(); - unsigned Register1; - unsigned Register2; - auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); - auto i = Instructions.begin() + Index - 1; - for (;; --i) { - assert(i != Instructions.begin() - 1 && "Couldn't find producer"); - MCInst const &Inst = *i->getInst(); - if (HexagonMCInstrInfo::isImmext(Inst)) - continue; - ++SOffset; - if (HexagonMCInstrInfo::isVector(MCII, Inst)) - // Vector instructions don't count scalars - ++VOffset; - Register1 = - HexagonMCInstrInfo::hasNewValue(MCII, Inst) - ? HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg() - : static_cast<unsigned>(Hexagon::NoRegister); - Register2 = - HexagonMCInstrInfo::hasNewValue2(MCII, Inst) - ? HexagonMCInstrInfo::getNewValueOperand2(MCII, Inst).getReg() - : static_cast<unsigned>(Hexagon::NoRegister); - if (!RegisterMatches(Register, Register1, Register2)) - // This isn't the register we're looking for - continue; - if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) - // Producer is unpredicated - break; - assert(HexagonMCInstrInfo::isPredicated(MCII, HMB) && - "Unpredicated consumer depending on predicated producer"); - if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) == - HexagonMCInstrInfo::isPredicatedTrue(MCII, HMB)) - // Producer predicate sense matched ours - break; - } - // Hexagon PRM 10.11 Construct Nt from distance - unsigned Offset = - HexagonMCInstrInfo::isVector(MCII, HMB) ? VOffset : SOffset; - Offset <<= 1; - Offset |= - HexagonMCInstrInfo::SubregisterBit(Register, Register1, Register2); - MCO.setReg(Offset + Hexagon::R0); - } - - Binary = getBinaryCodeForInstr(HMB, Fixups, STI); + Binary = getBinaryCodeForInstr(MI, Fixups, STI); // Check for unimplemented instructions. Immediate extenders // are encoded as zero, so they need to be accounted for. - if ((!Binary) && - ((HMB.getOpcode() != DuplexIClass0) && (HMB.getOpcode() != A4_ext) && - (HMB.getOpcode() != A4_ext_b) && (HMB.getOpcode() != A4_ext_c) && - (HMB.getOpcode() != A4_ext_g))) { + if (!Binary && + MI.getOpcode() != DuplexIClass0 && + MI.getOpcode() != A4_ext) { DEBUG(dbgs() << "Unimplemented inst: " - " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'" + " `" << HexagonMCInstrInfo::getName(MCII, MI) << "'" "\n"); llvm_unreachable("Unimplemented Instruction"); } Binary |= Parse; // if we need to emit a duplexed instruction - if (HMB.getOpcode() >= Hexagon::DuplexIClass0 && - HMB.getOpcode() <= Hexagon::DuplexIClassF) { + if (MI.getOpcode() >= Hexagon::DuplexIClass0 && + MI.getOpcode() <= Hexagon::DuplexIClassF) { assert(Parse == HexagonII::INST_PARSE_DUPLEX && "Emitting duplex without duplex parse bits"); - unsigned dupIClass; - switch (HMB.getOpcode()) { - case Hexagon::DuplexIClass0: - dupIClass = 0; - break; - case Hexagon::DuplexIClass1: - dupIClass = 1; - break; - case Hexagon::DuplexIClass2: - dupIClass = 2; - break; - case Hexagon::DuplexIClass3: - dupIClass = 3; - break; - case Hexagon::DuplexIClass4: - dupIClass = 4; - break; - case Hexagon::DuplexIClass5: - dupIClass = 5; - break; - case Hexagon::DuplexIClass6: - dupIClass = 6; - break; - case Hexagon::DuplexIClass7: - dupIClass = 7; - break; - case Hexagon::DuplexIClass8: - dupIClass = 8; - break; - case Hexagon::DuplexIClass9: - dupIClass = 9; - break; - case Hexagon::DuplexIClassA: - dupIClass = 10; - break; - case Hexagon::DuplexIClassB: - dupIClass = 11; - break; - case Hexagon::DuplexIClassC: - dupIClass = 12; - break; - case Hexagon::DuplexIClassD: - dupIClass = 13; - break; - case Hexagon::DuplexIClassE: - dupIClass = 14; - break; - case Hexagon::DuplexIClassF: - dupIClass = 15; - break; - default: - llvm_unreachable("Unimplemented DuplexIClass"); - break; - } + unsigned dupIClass = MI.getOpcode() - Hexagon::DuplexIClass0; // 29 is the bit position. // 0b1110 =0xE bits are masked off and down shifted by 1 bit. // Last bit is moved to bit position 13 Binary = ((dupIClass & 0xE) << (29 - 1)) | ((dupIClass & 0x1) << 13); - const MCInst *subInst0 = HMB.getOperand(0).getInst(); - const MCInst *subInst1 = HMB.getOperand(1).getInst(); + const MCInst *subInst0 = MI.getOperand(0).getInst(); + const MCInst *subInst1 = MI.getOperand(1).getInst(); // get subinstruction slot 0 unsigned subInstSlot0Bits = getBinaryCodeForInstr(*subInst0, Fixups, STI); @@ -293,14 +173,13 @@ void raise_relocation_error(unsigned bits, unsigned kind) { /// getFixupNoBits - Some insns are not extended and thus have no /// bits. These cases require a more brute force method for determining /// the correct relocation. -namespace { -Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI, - const MCOperand &MO, - const MCSymbolRefExpr::VariantKind kind) { +Hexagon::Fixups HexagonMCCodeEmitter::getFixupNoBits( + MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO, + const MCSymbolRefExpr::VariantKind kind) const { const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI); unsigned insnType = llvm::HexagonMCInstrInfo::getType(MCII, MI); - if (insnType == HexagonII::TypePREFIX) { + if (insnType == HexagonII::TypeEXTENDER) { switch (kind) { case MCSymbolRefExpr::VK_GOTREL: return Hexagon::fixup_Hexagon_GOTREL_32_6_X; @@ -319,11 +198,21 @@ Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI, case MCSymbolRefExpr::VK_Hexagon_IE_GOT: return Hexagon::fixup_Hexagon_IE_GOT_32_6_X; case MCSymbolRefExpr::VK_Hexagon_PCREL: - case MCSymbolRefExpr::VK_None: - if (MCID.isBranch()) - return Hexagon::fixup_Hexagon_B32_PCREL_X; - else - return Hexagon::fixup_Hexagon_32_6_X; + return Hexagon::fixup_Hexagon_B32_PCREL_X; + case MCSymbolRefExpr::VK_None: { + auto Insts = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); + for (auto I = Insts.begin(), N = Insts.end(); I != N; ++I) { + if (I->getInst() == &MI) { + const MCInst &NextI = *(I+1)->getInst(); + const MCInstrDesc &D = HexagonMCInstrInfo::getDesc(MCII, NextI); + if (D.isBranch() || D.isCall() || + HexagonMCInstrInfo::getType(MCII, NextI) == HexagonII::TypeCR) + return Hexagon::fixup_Hexagon_B32_PCREL_X; + return Hexagon::fixup_Hexagon_32_6_X; + } + } + raise_relocation_error(0, kind); + } default: raise_relocation_error(0, kind); } @@ -406,7 +295,6 @@ Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI, } llvm_unreachable("Relocation exit not taken"); } -} namespace llvm { extern const MCInstrDesc HexagonInsts[]; @@ -450,7 +338,8 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI, int64_t Value; if (ME->evaluateAsAbsolute(Value)) return Value; - assert(ME->getKind() == MCExpr::SymbolRef || ME->getKind() == MCExpr::Binary); + assert(ME->getKind() == MCExpr::SymbolRef || + ME->getKind() == MCExpr::Binary); if (ME->getKind() == MCExpr::Binary) { MCBinaryExpr const *Binary = cast<MCBinaryExpr>(ME); getExprOpValue(MI, MO, Binary->getLHS(), Fixups, STI); @@ -581,7 +470,30 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI, if (HexagonMCInstrInfo::s23_2_reloc(*MO.getExpr())) FixupKind = Hexagon::fixup_Hexagon_23_REG; else - raise_relocation_error(bits, kind); + if (MCID.mayStore() || MCID.mayLoad()) { + for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses; + ++ImpUses) { + if (*ImpUses != Hexagon::GP) + continue; + switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) { + case HexagonII::MemAccessSize::ByteAccess: + FixupKind = fixup_Hexagon_GPREL16_0; + break; + case HexagonII::MemAccessSize::HalfWordAccess: + FixupKind = fixup_Hexagon_GPREL16_1; + break; + case HexagonII::MemAccessSize::WordAccess: + FixupKind = fixup_Hexagon_GPREL16_2; + break; + case HexagonII::MemAccessSize::DoubleWordAccess: + FixupKind = fixup_Hexagon_GPREL16_3; + break; + default: + raise_relocation_error(bits, kind); + } + } + } else + raise_relocation_error(bits, kind); break; } case MCSymbolRefExpr::VK_DTPREL: @@ -795,10 +707,71 @@ unsigned HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO, SmallVectorImpl<MCFixup> &Fixups, MCSubtargetInfo const &STI) const { +#ifndef NDEBUG + size_t OperandNumber = ~0U; + for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) + if (&MI.getOperand(i) == &MO) { + OperandNumber = i; + break; + } + assert((OperandNumber != ~0U) && "Operand not found"); +#endif + + if (HexagonMCInstrInfo::isNewValue(MCII, MI) && + &MO == &MI.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, MI))) { + // Calculate the new value distance to the associated producer + MCOperand const &MCO = + MI.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, MI)); + unsigned SOffset = 0; + unsigned VOffset = 0; + unsigned Register = MCO.getReg(); + unsigned Register1; + unsigned Register2; + auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); + auto i = Instructions.begin() + *CurrentIndex - 1; + for (;; --i) { + assert(i != Instructions.begin() - 1 && "Couldn't find producer"); + MCInst const &Inst = *i->getInst(); + if (HexagonMCInstrInfo::isImmext(Inst)) + continue; + ++SOffset; + if (HexagonMCInstrInfo::isVector(MCII, Inst)) + // Vector instructions don't count scalars + ++VOffset; + Register1 = + HexagonMCInstrInfo::hasNewValue(MCII, Inst) + ? HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg() + : static_cast<unsigned>(Hexagon::NoRegister); + Register2 = + HexagonMCInstrInfo::hasNewValue2(MCII, Inst) + ? HexagonMCInstrInfo::getNewValueOperand2(MCII, Inst).getReg() + : static_cast<unsigned>(Hexagon::NoRegister); + if (!RegisterMatches(Register, Register1, Register2)) + // This isn't the register we're looking for + continue; + if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) + // Producer is unpredicated + break; + assert(HexagonMCInstrInfo::isPredicated(MCII, MI) && + "Unpredicated consumer depending on predicated producer"); + if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) == + HexagonMCInstrInfo::isPredicatedTrue(MCII, MI)) + // Producer predicate sense matched ours + break; + } + // Hexagon PRM 10.11 Construct Nt from distance + unsigned Offset = + HexagonMCInstrInfo::isVector(MCII, MI) ? VOffset : SOffset; + Offset <<= 1; + Offset |= + HexagonMCInstrInfo::SubregisterBit(Register, Register1, Register2); + return Offset; + } assert(!MO.isImm()); if (MO.isReg()) { unsigned Reg = MO.getReg(); - if (HexagonMCInstrInfo::isSubInstruction(MI)) + if (HexagonMCInstrInfo::isSubInstruction(MI) || + llvm::HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCJ) return HexagonMCInstrInfo::getDuplexRegisterNumbering(Reg); switch(MI.getOpcode()){ case Hexagon::A2_tfrrcr: diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h index 8e0667d9ac8e..c3a4beec313f 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h @@ -15,6 +15,7 @@ #ifndef HEXAGONMCCODEEMITTER_H #define HEXAGONMCCODEEMITTER_H +#include "MCTargetDesc/HexagonFixupKinds.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" @@ -31,18 +32,22 @@ class HexagonMCCodeEmitter : public MCCodeEmitter { std::unique_ptr<unsigned> Addend; std::unique_ptr<bool> Extended; std::unique_ptr<MCInst const *> CurrentBundle; + std::unique_ptr<size_t> CurrentIndex; // helper routine for getMachineOpValue() unsigned getExprOpValue(const MCInst &MI, const MCOperand &MO, const MCExpr *ME, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; + Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI, + const MCOperand &MO, + const MCSymbolRefExpr::VariantKind kind) const; + public: HexagonMCCodeEmitter(MCInstrInfo const &aMII, MCContext &aMCT); // Return parse bits for instruction `MCI' inside bundle `MCB' - uint32_t parseBits(size_t Instruction, size_t Last, MCInst const &MCB, - MCInst const &MCI) const; + uint32_t parseBits(size_t Last, MCInst const &MCB, MCInst const &MCI) const; void encodeInstruction(MCInst const &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, @@ -51,7 +56,7 @@ public: void EncodeSingleInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI, - uint32_t Parse, size_t Index) const; + uint32_t Parse) const; // \brief TableGen'erated function for getting the // binary encoding for an instruction. diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp index 9a09a17767a6..ffa980ca6563 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp @@ -14,6 +14,7 @@ #include "Hexagon.h" #include "MCTargetDesc/HexagonBaseInfo.h" #include "MCTargetDesc/HexagonMCInstrInfo.h" +#include "MCTargetDesc/HexagonMCShuffler.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCInst.h" #include "llvm/Support/Debug.h" @@ -396,7 +397,7 @@ static bool lookForCompound(MCInstrInfo const &MCII, MCContext &Context, /// is found update the contents fo the bundle with the compound insn. /// If a compound instruction is found then the bundle will have one /// additional slot. -void HexagonMCInstrInfo::tryCompound(MCInstrInfo const &MCII, +void HexagonMCInstrInfo::tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCI) { assert(HexagonMCInstrInfo::isBundle(MCI) && "Non-Bundle where Bundle expected"); @@ -405,8 +406,23 @@ void HexagonMCInstrInfo::tryCompound(MCInstrInfo const &MCII, if (MCI.size() < 2) return; + bool StartedValid = llvm::HexagonMCShuffle(false, MCII, STI, MCI); + + // Create a vector, needed to keep the order of jump instructions. + MCInst CheckList(MCI); + // Look for compounds until none are found, only update the bundle when // a compound is found. - while (lookForCompound(MCII, Context, MCI)) - ; + while (lookForCompound(MCII, Context, CheckList)) { + // Keep the original bundle around in case the shuffle fails. + MCInst OriginalBundle(MCI); + + // Need to update the bundle. + MCI = CheckList; + + if (StartedValid && !llvm::HexagonMCShuffle(false, MCII, STI, MCI)) { + DEBUG(dbgs() << "Found ERROR\n"); + MCI = OriginalBundle; + } + } } diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp index 413f052aa4bd..e8f154a1fa53 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp @@ -15,6 +15,7 @@ #include "MCTargetDesc/HexagonMCInstrInfo.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" @@ -262,6 +263,7 @@ unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) { case Hexagon::EH_RETURN_JMPR: case Hexagon::J2_jumpr: + case Hexagon::PS_jmpret: // jumpr r31 // Actual form JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,internal>. DstReg = MCI.getOperand(0).getReg(); @@ -275,6 +277,12 @@ unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) { case Hexagon::J2_jumprfnew: case Hexagon::J2_jumprtnewpt: case Hexagon::J2_jumprfnewpt: + case Hexagon::PS_jmprett: + case Hexagon::PS_jmpretf: + case Hexagon::PS_jmprettnew: + case Hexagon::PS_jmpretfnew: + case Hexagon::PS_jmprettnewpt: + case Hexagon::PS_jmpretfnewpt: DstReg = MCI.getOperand(1).getReg(); SrcReg = MCI.getOperand(0).getReg(); // [if ([!]p0[.new])] jumpr r31 @@ -284,15 +292,10 @@ unsigned HexagonMCInstrInfo::getDuplexCandidateGroup(MCInst const &MCI) { } break; case Hexagon::L4_return_t: - case Hexagon::L4_return_f: - case Hexagon::L4_return_tnew_pnt: - case Hexagon::L4_return_fnew_pnt: - case Hexagon::L4_return_tnew_pt: - case Hexagon::L4_return_fnew_pt: // [if ([!]p0[.new])] dealloc_return SrcReg = MCI.getOperand(0).getReg(); @@ -565,7 +568,8 @@ bool HexagonMCInstrInfo::subInstWouldBeExtended(MCInst const &potentialDuplex) { bool HexagonMCInstrInfo::isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa, bool ExtendedA, MCInst const &MIb, bool ExtendedB, - bool bisReversable) { + bool bisReversable, + MCSubtargetInfo const &STI) { // Slot 1 cannot be extended in duplexes PRM 10.5 if (ExtendedA) return false; @@ -625,11 +629,16 @@ bool HexagonMCInstrInfo::isOrderedDuplexPair(MCInstrInfo const &MCII, return false; } - // If a store appears, it must be in slot 0 (MIa) 1st, and then slot 1 (MIb); - // therefore, not duplexable if slot 1 is a store, and slot 0 is not. - if ((MIbG == HexagonII::HSIG_S1) || (MIbG == HexagonII::HSIG_S2)) { - if ((MIaG != HexagonII::HSIG_S1) && (MIaG != HexagonII::HSIG_S2)) - return false; + if (STI.getCPU().equals_lower("hexagonv4") || + STI.getCPU().equals_lower("hexagonv5") || + STI.getCPU().equals_lower("hexagonv55") || + STI.getCPU().equals_lower("hexagonv60")) { + // If a store appears, it must be in slot 0 (MIa) 1st, and then slot 1 (MIb); + // therefore, not duplexable if slot 1 is a store, and slot 0 is not. + if ((MIbG == HexagonII::HSIG_S1) || (MIbG == HexagonII::HSIG_S2)) { + if ((MIaG != HexagonII::HSIG_S1) && (MIaG != HexagonII::HSIG_S2)) + return false; + } } return (isDuplexPairMatch(MIaG, MIbG)); @@ -703,6 +712,7 @@ MCInst HexagonMCInstrInfo::deriveSubInst(MCInst const &Inst) { Result.setOpcode(Hexagon::SA1_dec); addOps(Result, Inst, 0); addOps(Result, Inst, 1); + addOps(Result, Inst, 2); break; } // 1,2 SUBInst $Rd = add($Rs,#-1) else if (Inst.getOperand(1).getReg() == Hexagon::R29) { @@ -806,20 +816,27 @@ MCInst HexagonMCInstrInfo::deriveSubInst(MCInst const &Inst) { break; // none SUBInst deallocframe case Hexagon::EH_RETURN_JMPR: case Hexagon::J2_jumpr: + case Hexagon::PS_jmpret: Result.setOpcode(Hexagon::SL2_jumpr31); break; // none SUBInst jumpr r31 case Hexagon::J2_jumprf: + case Hexagon::PS_jmpretf: Result.setOpcode(Hexagon::SL2_jumpr31_f); break; // none SUBInst if (!p0) jumpr r31 case Hexagon::J2_jumprfnew: case Hexagon::J2_jumprfnewpt: + case Hexagon::PS_jmpretfnewpt: + case Hexagon::PS_jmpretfnew: Result.setOpcode(Hexagon::SL2_jumpr31_fnew); break; // none SUBInst if (!p0.new) jumpr:nt r31 case Hexagon::J2_jumprt: + case Hexagon::PS_jmprett: Result.setOpcode(Hexagon::SL2_jumpr31_t); break; // none SUBInst if (p0) jumpr r31 case Hexagon::J2_jumprtnew: case Hexagon::J2_jumprtnewpt: + case Hexagon::PS_jmprettnewpt: + case Hexagon::PS_jmprettnew: Result.setOpcode(Hexagon::SL2_jumpr31_tnew); break; // none SUBInst if (p0.new) jumpr:nt r31 case Hexagon::L2_loadrb_io: @@ -966,6 +983,7 @@ MCInst HexagonMCInstrInfo::deriveSubInst(MCInst const &Inst) { if (Absolute && Value == -1) { Result.setOpcode(Hexagon::SA1_setin1); addOps(Result, Inst, 0); + addOps(Result, Inst, 1); break; // 2 1 SUBInst $Rd = #-1 } else { Result.setOpcode(Hexagon::SA1_seti); @@ -1005,6 +1023,7 @@ static bool isStoreInst(unsigned opCode) { SmallVector<DuplexCandidate, 8> HexagonMCInstrInfo::getDuplexPossibilties(MCInstrInfo const &MCII, + MCSubtargetInfo const &STI, MCInst const &MCB) { assert(isBundle(MCB)); SmallVector<DuplexCandidate, 8> duplexToTry; @@ -1033,7 +1052,7 @@ HexagonMCInstrInfo::getDuplexPossibilties(MCInstrInfo const &MCII, HexagonMCInstrInfo::hasExtenderForIndex(MCB, k - 1), *MCB.getOperand(j).getInst(), HexagonMCInstrInfo::hasExtenderForIndex(MCB, j - 1), - bisReversable)) { + bisReversable, STI)) { // Get iClass. unsigned iClass = iClassOfDuplexPair( getDuplexCandidateGroup(*MCB.getOperand(k).getInst()), @@ -1058,7 +1077,7 @@ HexagonMCInstrInfo::getDuplexPossibilties(MCInstrInfo const &MCII, HexagonMCInstrInfo::hasExtenderForIndex(MCB, j - 1), *MCB.getOperand(k).getInst(), HexagonMCInstrInfo::hasExtenderForIndex(MCB, k - 1), - bisReversable)) { + bisReversable, STI)) { // Get iClass. unsigned iClass = iClassOfDuplexPair( getDuplexCandidateGroup(*MCB.getOperand(j).getInst()), diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp index 226470cfbced..9e1ff9ca35d7 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp @@ -37,30 +37,19 @@ using namespace llvm; -static cl::opt<unsigned> - GPSize("gpsize", cl::NotHidden, - cl::desc("Global Pointer Addressing Size. The default size is 8."), - cl::Prefix, cl::init(8)); - -void HexagonMCELFStreamer::EmitInstruction(const MCInst &MCK, - const MCSubtargetInfo &STI) { - MCInst HMI = HexagonMCInstrInfo::createBundle(); - MCInst *MCB; - - if (MCK.getOpcode() != Hexagon::BUNDLE) { - HMI.addOperand(MCOperand::createInst(&MCK)); - MCB = &HMI; - } else - MCB = const_cast<MCInst *>(&MCK); - - // Examines packet and pad the packet, if needed, when an - // end-loop is in the bundle. - HexagonMCInstrInfo::padEndloop(getContext(), *MCB); - HexagonMCShuffle(*MCII, STI, *MCB); - - assert(HexagonMCInstrInfo::bundleSize(*MCB) <= HEXAGON_PACKET_SIZE); +static cl::opt<unsigned> GPSize + ("gpsize", cl::NotHidden, + cl::desc("Global Pointer Addressing Size. The default size is 8."), + cl::Prefix, + cl::init(8)); + +void HexagonMCELFStreamer::EmitInstruction(const MCInst &MCB, + const MCSubtargetInfo &STI, bool) { + assert(MCB.getOpcode() == Hexagon::BUNDLE); + assert(HexagonMCInstrInfo::bundleSize(MCB) <= HEXAGON_PACKET_SIZE); + assert(HexagonMCInstrInfo::bundleSize(MCB) > 0); bool Extended = false; - for (auto &I : HexagonMCInstrInfo::bundleInstructions(*MCB)) { + for (auto &I : HexagonMCInstrInfo::bundleInstructions(MCB)) { MCInst *MCI = const_cast<MCInst *>(I.getInst()); if (Extended) { if (HexagonMCInstrInfo::isDuplex(*MCII, *MCI)) { @@ -77,11 +66,12 @@ void HexagonMCELFStreamer::EmitInstruction(const MCInst &MCK, // At this point, MCB is a bundle // Iterate through the bundle and assign addends for the instructions - for (auto const &I : HexagonMCInstrInfo::bundleInstructions(*MCB)) { + for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCB)) { MCInst *MCI = const_cast<MCInst *>(I.getInst()); EmitSymbol(*MCI); } - MCObjectStreamer::EmitInstruction(*MCB, STI); + + MCObjectStreamer::EmitInstruction(MCB, STI); } void HexagonMCELFStreamer::EmitSymbol(const MCInst &Inst) { @@ -119,9 +109,11 @@ void HexagonMCELFStreamer::HexagonMCEmitCommonSymbol(MCSymbol *Symbol, MCSectionSubPair P = getCurrentSection(); SwitchSection(&Section); - EmitValueToAlignment(ByteAlignment, 0, 1, 0); - EmitLabel(Symbol); - EmitZeros(Size); + if (ELFSymbol->isUndefined(false)) { + EmitValueToAlignment(ByteAlignment, 0, 1, 0); + EmitLabel(Symbol); + EmitZeros(Size); + } // Update the maximum alignment of the section if necessary. if (ByteAlignment > Section.getAlignment()) @@ -144,9 +136,10 @@ void HexagonMCELFStreamer::HexagonMCEmitCommonSymbol(MCSymbol *Symbol, ELFSymbol->setSize(MCConstantExpr::create(Size, getContext())); } -void HexagonMCELFStreamer::HexagonMCEmitLocalCommonSymbol( - MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, - unsigned AccessSize) { +void HexagonMCELFStreamer::HexagonMCEmitLocalCommonSymbol(MCSymbol *Symbol, + uint64_t Size, + unsigned ByteAlignment, + unsigned AccessSize) { getAssembler().registerSymbol(*Symbol); auto ELFSymbol = cast<MCSymbolELF>(Symbol); ELFSymbol->setBinding(ELF::STB_LOCAL); @@ -154,11 +147,12 @@ void HexagonMCELFStreamer::HexagonMCEmitLocalCommonSymbol( HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment, AccessSize); } -namespace llvm { -MCStreamer *createHexagonELFStreamer(MCContext &Context, MCAsmBackend &MAB, - raw_pwrite_stream &OS, MCCodeEmitter *CE) { - return new HexagonMCELFStreamer(Context, MAB, OS, CE); -} +namespace llvm { + MCStreamer *createHexagonELFStreamer(Triple const &TT, MCContext &Context, + MCAsmBackend &MAB, + raw_pwrite_stream &OS, MCCodeEmitter *CE) { + return new HexagonMCELFStreamer(Context, MAB, OS, CE); + } } // end namespace llvm diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h index 0ac1a68d4ef9..024dff1a2f97 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h @@ -27,7 +27,15 @@ public: : MCELFStreamer(Context, TAB, OS, Emitter), MCII(createHexagonMCInstrInfo()) {} - void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; + HexagonMCELFStreamer(MCContext &Context, + MCAsmBackend &TAB, + raw_pwrite_stream &OS, MCCodeEmitter *Emitter, + MCAssembler *Assembler) : + MCELFStreamer(Context, TAB, OS, Emitter), + MCII (createHexagonMCInstrInfo()) {} + + void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, + bool) override; void EmitSymbol(const MCInst &Inst); void HexagonMCEmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, @@ -36,8 +44,9 @@ public: unsigned ByteAlignment, unsigned AccessSize); }; -MCStreamer *createHexagonELFStreamer(MCContext &Context, MCAsmBackend &MAB, - raw_pwrite_stream &OS, MCCodeEmitter *CE); +MCStreamer *createHexagonELFStreamer(Triple const &TT, MCContext &Context, + MCAsmBackend &MAB, raw_pwrite_stream &OS, + MCCodeEmitter *CE); } // end namespace llvm diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.cpp b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.cpp index e93906a0a396..14300edc7e1b 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.cpp +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.cpp @@ -11,7 +11,9 @@ #include "HexagonMCExpr.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCStreamer.h" +#include "llvm/MC/MCSymbolELF.h" #include "llvm/MC/MCValue.h" +#include "llvm/Object/ELF.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; @@ -36,7 +38,47 @@ MCFragment *llvm::HexagonMCExpr::findAssociatedFragment() const { return Expr->findAssociatedFragment(); } -void HexagonMCExpr::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {} +static void fixELFSymbolsInTLSFixupsImpl(const MCExpr *Expr, MCAssembler &Asm) { + switch (Expr->getKind()) { + case MCExpr::Target: + llvm_unreachable("Cannot handle nested target MCExpr"); + break; + case MCExpr::Constant: + break; + + case MCExpr::Binary: { + const MCBinaryExpr *be = cast<MCBinaryExpr>(Expr); + fixELFSymbolsInTLSFixupsImpl(be->getLHS(), Asm); + fixELFSymbolsInTLSFixupsImpl(be->getRHS(), Asm); + break; + } + case MCExpr::SymbolRef: { + const MCSymbolRefExpr &symRef = *cast<MCSymbolRefExpr>(Expr); + switch (symRef.getKind()) { + default: + return; + case MCSymbolRefExpr::VK_Hexagon_GD_GOT: + case MCSymbolRefExpr::VK_Hexagon_LD_GOT: + case MCSymbolRefExpr::VK_Hexagon_GD_PLT: + case MCSymbolRefExpr::VK_Hexagon_LD_PLT: + case MCSymbolRefExpr::VK_Hexagon_IE: + case MCSymbolRefExpr::VK_Hexagon_IE_GOT: + case MCSymbolRefExpr::VK_TPREL: + break; + } + cast<MCSymbolELF>(symRef.getSymbol()).setType(ELF::STT_TLS); + break; + } + case MCExpr::Unary: + fixELFSymbolsInTLSFixupsImpl(cast<MCUnaryExpr>(Expr)->getSubExpr(), Asm); + break; + } +} + +void HexagonMCExpr::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const { + auto expr = getExpr(); + fixELFSymbolsInTLSFixupsImpl(expr, Asm); +} MCExpr const *HexagonMCExpr::getExpr() const { return Expr; } @@ -75,4 +117,4 @@ void HexagonMCExpr::setSignMismatch(bool Val) { bool HexagonMCExpr::signMismatch() const { return SignMismatch; -}
\ No newline at end of file +} diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp index e627f026c8ad..553ffba508a1 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp @@ -16,10 +16,9 @@ #include "Hexagon.h" #include "HexagonBaseInfo.h" #include "HexagonMCChecker.h" - #include "llvm/MC/MCContext.h" -#include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCInstrItineraries.h" #include "llvm/MC/MCSubtargetInfo.h" namespace llvm { @@ -59,31 +58,36 @@ bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Check) { - // Examine the packet and convert pairs of instructions to compound - // instructions when possible. - if (!HexagonDisableCompound) - HexagonMCInstrInfo::tryCompound(MCII, Context, MCB); // Check the bundle for errors. - bool CheckOk = Check ? Check->check() : true; + bool CheckOk = Check ? Check->check(false) : true; if (!CheckOk) return false; - HexagonMCShuffle(MCII, STI, MCB); + // Examine the packet and convert pairs of instructions to compound + // instructions when possible. + if (!HexagonDisableCompound) + HexagonMCInstrInfo::tryCompound(MCII, STI, Context, MCB); + HexagonMCShuffle(false, MCII, STI, MCB); // Examine the packet and convert pairs of instructions to duplex // instructions when possible. MCInst InstBundlePreDuplex = MCInst(MCB); if (!HexagonDisableDuplex) { SmallVector<DuplexCandidate, 8> possibleDuplexes; - possibleDuplexes = HexagonMCInstrInfo::getDuplexPossibilties(MCII, MCB); + possibleDuplexes = + HexagonMCInstrInfo::getDuplexPossibilties(MCII, STI, MCB); HexagonMCShuffle(MCII, STI, Context, MCB, possibleDuplexes); } // Examines packet and pad the packet, if needed, when an // end-loop is in the bundle. - HexagonMCInstrInfo::padEndloop(Context, MCB); + HexagonMCInstrInfo::padEndloop(MCB, Context); // If compounding and duplexing didn't reduce the size below // 4 or less we have a packet that is too big. if (HexagonMCInstrInfo::bundleSize(MCB) > HEXAGON_PACKET_SIZE) return false; - HexagonMCShuffle(MCII, STI, MCB); + // Check the bundle for errors. + CheckOk = Check ? Check->check(true) : true; + if (!CheckOk) + return false; + HexagonMCShuffle(true, MCII, STI, MCB); return true; } @@ -111,32 +115,14 @@ MCInst HexagonMCInstrInfo::createBundle() { return Result; } -MCInst *HexagonMCInstrInfo::deriveDuplex(MCContext &Context, unsigned iClass, - MCInst const &inst0, - MCInst const &inst1) { - assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf"); - MCInst *duplexInst = new (Context) MCInst; - duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass); - - MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0)); - MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1)); - duplexInst->addOperand(MCOperand::createInst(SubInst0)); - duplexInst->addOperand(MCOperand::createInst(SubInst1)); - return duplexInst; -} - MCInst HexagonMCInstrInfo::deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO) { assert(HexagonMCInstrInfo::isExtendable(MCII, Inst) || HexagonMCInstrInfo::isExtended(MCII, Inst)); - MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, Inst); MCInst XMI; - XMI.setOpcode((Desc.isBranch() || Desc.isCall() || - HexagonMCInstrInfo::getType(MCII, Inst) == HexagonII::TypeCR) - ? Hexagon::A4_ext_b - : Hexagon::A4_ext); + XMI.setOpcode(Hexagon::A4_ext); if (MO.isImm()) XMI.addOperand(MCOperand::createImm(MO.getImm() & (~0x3f))); else if (MO.isExpr()) @@ -146,6 +132,20 @@ MCInst HexagonMCInstrInfo::deriveExtender(MCInstrInfo const &MCII, return XMI; } +MCInst *HexagonMCInstrInfo::deriveDuplex(MCContext &Context, unsigned iClass, + MCInst const &inst0, + MCInst const &inst1) { + assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf"); + MCInst *duplexInst = new (Context) MCInst; + duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass); + + MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0)); + MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1)); + duplexInst->addOperand(MCOperand::createInst(SubInst0)); + duplexInst->addOperand(MCOperand::createInst(SubInst1)); + return duplexInst; +} + MCInst const *HexagonMCInstrInfo::extenderForIndex(MCInst const &MCB, size_t Index) { assert(Index <= bundleSize(MCB)); @@ -173,22 +173,9 @@ HexagonMCInstrInfo::getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI) { HexagonII::MemAccesSizeMask)); } -unsigned HexagonMCInstrInfo::getBitCount(MCInstrInfo const &MCII, - MCInst const &MCI) { - uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; - return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask); -} - -// Return constant extended operand number. -unsigned short HexagonMCInstrInfo::getCExtOpNum(MCInstrInfo const &MCII, - MCInst const &MCI) { - const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; - return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask); -} - MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII, MCInst const &MCI) { - return (MCII.get(MCI.getOpcode())); + return MCII.get(MCI.getOpcode()); } unsigned HexagonMCInstrInfo::getDuplexRegisterNumbering(unsigned Reg) { @@ -276,34 +263,32 @@ unsigned HexagonMCInstrInfo::getExtentBits(MCInstrInfo const &MCII, return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask); } -// Return the max value that a constant extendable operand can have -// without being extended. +/// Return the maximum value of an extendable operand. int HexagonMCInstrInfo::getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI) { - uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; - unsigned isSigned = - (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask; - unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask; + const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; + bool S = (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask; - if (isSigned) // if value is signed - return ~(-1U << (bits - 1)); - else - return ~(-1U << bits); + assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) || + HexagonMCInstrInfo::isExtended(MCII, MCI)); + + if (S) // if value is signed + return (1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1)) - 1; + return (1 << HexagonMCInstrInfo::getExtentBits(MCII, MCI)) - 1; } -// Return the min value that a constant extendable operand can have -// without being extended. +/// Return the minimum value of an extendable operand. int HexagonMCInstrInfo::getMinValue(MCInstrInfo const &MCII, MCInst const &MCI) { - uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; - unsigned isSigned = - (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask; - unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask; + const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; + bool S = (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask; - if (isSigned) // if value is signed - return -1U << (bits - 1); - else - return 0; + assert(HexagonMCInstrInfo::isExtendable(MCII, MCI) || + HexagonMCInstrInfo::isExtended(MCII, MCI)); + + if (S) // if value is signed + return -(1 << (HexagonMCInstrInfo::getExtentBits(MCII, MCI) - 1)); + return 0; } StringRef HexagonMCInstrInfo::getName(MCInstrInfo const &MCII, @@ -319,9 +304,7 @@ unsigned short HexagonMCInstrInfo::getNewValueOp(MCInstrInfo const &MCII, MCOperand const &HexagonMCInstrInfo::getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI) { - uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; - unsigned const O = - (F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask; + unsigned O = HexagonMCInstrInfo::getNewValueOp(MCII, MCI); MCOperand const &MCO = MCI.getOperand(O); assert((HexagonMCInstrInfo::isNewValue(MCII, MCI) || @@ -349,6 +332,13 @@ HexagonMCInstrInfo::getNewValueOperand2(MCInstrInfo const &MCII, return (MCO); } +/// Return the Hexagon ISA class for the insn. +unsigned HexagonMCInstrInfo::getType(MCInstrInfo const &MCII, + MCInst const &MCI) { + const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags; + return ((F >> HexagonII::TypePos) & HexagonII::TypeMask); +} + int HexagonMCInstrInfo::getSubTarget(MCInstrInfo const &MCII, MCInst const &MCI) { const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; @@ -361,33 +351,55 @@ int HexagonMCInstrInfo::getSubTarget(MCInstrInfo const &MCII, return Hexagon::ArchV4; case HexagonII::HasV5SubT: return Hexagon::ArchV5; + case HexagonII::HasV55SubT: + return Hexagon::ArchV55; + case HexagonII::HasV60SubT: + return Hexagon::ArchV60; } } -// Return the Hexagon ISA class for the insn. -unsigned HexagonMCInstrInfo::getType(MCInstrInfo const &MCII, - MCInst const &MCI) { - const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; - - return ((F >> HexagonII::TypePos) & HexagonII::TypeMask); -} - +/// Return the slots this instruction can execute out of unsigned HexagonMCInstrInfo::getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI) { - const InstrItinerary *II = STI.getSchedModel().InstrItineraries; int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); return ((II[SchedClass].FirstStage + HexagonStages)->getUnits()); } -bool HexagonMCInstrInfo::hasImmExt(MCInst const &MCI) { +/// Return the slots this instruction consumes in addition to +/// the slot(s) it can execute out of + +unsigned HexagonMCInstrInfo::getOtherReservedSlots(MCInstrInfo const &MCII, + MCSubtargetInfo const &STI, + MCInst const &MCI) { + const InstrItinerary *II = STI.getSchedModel().InstrItineraries; + int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); + unsigned Slots = 0; + + // FirstStage are slots that this instruction can execute in. + // FirstStage+1 are slots that are also consumed by this instruction. + // For example: vmemu can only execute in slot 0 but also consumes slot 1. + for (unsigned Stage = II[SchedClass].FirstStage + 1; + Stage < II[SchedClass].LastStage; ++Stage) { + unsigned Units = (Stage + HexagonStages)->getUnits(); + if (Units > HexagonGetLastSlot()) + break; + // fyi: getUnits() will return 0x1, 0x2, 0x4 or 0x8 + Slots |= Units; + } + + // if 0 is returned, then no additional slots are consumed by this inst. + return Slots; +} + +bool HexagonMCInstrInfo::hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI) { if (!HexagonMCInstrInfo::isBundle(MCI)) return false; for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCI)) { auto MI = I.getInst(); - if (isImmext(*MI)) + if (HexagonMCInstrInfo::isDuplex(MCII, *MI)) return true; } @@ -398,7 +410,20 @@ bool HexagonMCInstrInfo::hasExtenderForIndex(MCInst const &MCB, size_t Index) { return extenderForIndex(MCB, Index) != nullptr; } -// Return whether the instruction is a legal new-value producer. +bool HexagonMCInstrInfo::hasImmExt(MCInst const &MCI) { + if (!HexagonMCInstrInfo::isBundle(MCI)) + return false; + + for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCI)) { + auto MI = I.getInst(); + if (isImmext(*MI)) + return true; + } + + return false; +} + +/// Return whether the insn produces a value. bool HexagonMCInstrInfo::hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI) { const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; @@ -418,46 +443,19 @@ MCInst const &HexagonMCInstrInfo::instruction(MCInst const &MCB, size_t Index) { return *MCB.getOperand(bundleInstructionsOffset + Index).getInst(); } +/// Return where the instruction is an accumulator. +bool HexagonMCInstrInfo::isAccumulator(MCInstrInfo const &MCII, + MCInst const &MCI) { + const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; + return ((F >> HexagonII::AccumulatorPos) & HexagonII::AccumulatorMask); +} + bool HexagonMCInstrInfo::isBundle(MCInst const &MCI) { auto Result = Hexagon::BUNDLE == MCI.getOpcode(); assert(!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm())); return Result; } -// Return whether the insn is an actual insn. -bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) { - return (!HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() && - !HexagonMCInstrInfo::isPrefix(MCII, MCI) && - HexagonMCInstrInfo::getType(MCII, MCI) != HexagonII::TypeENDLOOP); -} - -bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) { - const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; - return ((F >> HexagonII::CofMax1Pos) & HexagonII::CofMax1Mask); -} - -bool HexagonMCInstrInfo::isCompound(MCInstrInfo const &MCII, - MCInst const &MCI) { - return (getType(MCII, MCI) == HexagonII::TypeCOMPOUND); -} - -bool HexagonMCInstrInfo::isDblRegForSubInst(unsigned Reg) { - return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) || - (Reg >= Hexagon::D8 && Reg <= Hexagon::D11)); -} - -bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) { - return HexagonII::TypeDUPLEX == HexagonMCInstrInfo::getType(MCII, MCI); -} - -// Return whether the instruction needs to be constant extended. -// 1) Always return true if the instruction has 'isExtended' flag set. -// -// isExtendable: -// 2) For immediate extended operands, return true only if the value is -// out-of-range. -// 3) For global address, always return true. - bool HexagonMCInstrInfo::isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI) { if (HexagonMCInstrInfo::isExtended(MCII, MCI)) @@ -470,9 +468,9 @@ bool HexagonMCInstrInfo::isConstExtended(MCInstrInfo const &MCII, return true; // Branch insns are handled as necessary by relaxation. if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) || - (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCOMPOUND && + (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCJ && HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) || - (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNV && + (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNCJ && HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch())) return false; // Otherwise loop instructions and other CR insts are handled by relaxation @@ -492,6 +490,30 @@ bool HexagonMCInstrInfo::isConstExtended(MCInstrInfo const &MCII, return (MinValue > Value || Value > MaxValue); } +bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) { + return !HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() && + !HexagonMCInstrInfo::isPrefix(MCII, MCI); +} + +bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) { + const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; + return ((F >> HexagonII::CofMax1Pos) & HexagonII::CofMax1Mask); +} + +bool HexagonMCInstrInfo::isCompound(MCInstrInfo const &MCII, + MCInst const &MCI) { + return (getType(MCII, MCI) == HexagonII::TypeCJ); +} + +bool HexagonMCInstrInfo::isDblRegForSubInst(unsigned Reg) { + return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) || + (Reg >= Hexagon::D8 && Reg <= Hexagon::D11)); +} + +bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) { + return HexagonII::TypeDUPLEX == HexagonMCInstrInfo::getType(MCII, MCI); +} + bool HexagonMCInstrInfo::isExtendable(MCInstrInfo const &MCII, MCInst const &MCI) { uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; @@ -510,9 +532,7 @@ bool HexagonMCInstrInfo::isFloat(MCInstrInfo const &MCII, MCInst const &MCI) { } bool HexagonMCInstrInfo::isImmext(MCInst const &MCI) { - auto Op = MCI.getOpcode(); - return (Op == Hexagon::A4_ext_b || Op == Hexagon::A4_ext_c || - Op == Hexagon::A4_ext_g || Op == Hexagon::A4_ext); + return MCI.getOpcode() == Hexagon::A4_ext; } bool HexagonMCInstrInfo::isInnerLoop(MCInst const &MCI) { @@ -530,20 +550,17 @@ bool HexagonMCInstrInfo::isIntRegForSubInst(unsigned Reg) { (Reg >= Hexagon::R16 && Reg <= Hexagon::R23)); } -// Return whether the insn is a new-value consumer. +/// Return whether the insn expects newly produced value. bool HexagonMCInstrInfo::isNewValue(MCInstrInfo const &MCII, MCInst const &MCI) { const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask); } -// Return whether the operand can be constant extended. -bool HexagonMCInstrInfo::isOperandExtended(MCInstrInfo const &MCII, - MCInst const &MCI, - unsigned short OperandNum) { - uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; - return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask) == - OperandNum; +/// Return whether the operand is extendable. +bool HexagonMCInstrInfo::isOpExtendable(MCInstrInfo const &MCII, + MCInst const &MCI, unsigned short O) { + return (O == HexagonMCInstrInfo::getExtendableOp(MCII, MCI)); } bool HexagonMCInstrInfo::isOuterLoop(MCInst const &MCI) { @@ -558,6 +575,10 @@ bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII, return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask); } +bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) { + return HexagonII::TypeEXTENDER == HexagonMCInstrInfo::getType(MCII, MCI); +} + bool HexagonMCInstrInfo::isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI) { const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; @@ -582,12 +603,22 @@ bool HexagonMCInstrInfo::isPredReg(unsigned Reg) { return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0); } -bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) { - return (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypePREFIX); +/// Return whether the insn can be packaged only with A and X-type insns. +bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) { + const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; + return ((F >> HexagonII::SoloAXPos) & HexagonII::SoloAXMask); } -bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) { +/// Return whether the insn can be packaged only with an A-type insn in slot #1. +bool HexagonMCInstrInfo::isSoloAin1(MCInstrInfo const &MCII, + MCInst const &MCI) { const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; + return ((F >> HexagonII::SoloAin1Pos) & HexagonII::SoloAin1Mask); +} + +/// Return whether the insn is solo, i.e., cannot be in a packet. +bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) { + const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags; return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask); } @@ -663,17 +694,6 @@ bool HexagonMCInstrInfo::isSubInstruction(MCInst const &MCI) { } } -bool HexagonMCInstrInfo::isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI) { - const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; - return ((F >> HexagonII::SoloAXPos) & HexagonII::SoloAXMask); -} - -bool HexagonMCInstrInfo::isSoloAin1(MCInstrInfo const &MCII, - MCInst const &MCI) { - const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; - return ((F >> HexagonII::SoloAin1Pos) & HexagonII::SoloAin1Mask); -} - bool HexagonMCInstrInfo::isVector(MCInstrInfo const &MCII, MCInst const &MCI) { if ((getType(MCII, MCI) <= HexagonII::TypeCVI_LAST) && (getType(MCII, MCI) >= HexagonII::TypeCVI_FIRST)) @@ -705,16 +725,26 @@ bool HexagonMCInstrInfo::mustExtend(MCExpr const &Expr) { return HExpr.mustExtend(); } void HexagonMCInstrInfo::setMustNotExtend(MCExpr const &Expr, bool Val) { - HexagonMCExpr &HExpr = - const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr)); + HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr)); HExpr.setMustNotExtend(Val); } bool HexagonMCInstrInfo::mustNotExtend(MCExpr const &Expr) { HexagonMCExpr const &HExpr = cast<HexagonMCExpr>(Expr); return HExpr.mustNotExtend(); } +void HexagonMCInstrInfo::setS23_2_reloc(MCExpr const &Expr, bool Val) { + HexagonMCExpr &HExpr = + const_cast<HexagonMCExpr &>(*llvm::cast<HexagonMCExpr>(&Expr)); + HExpr.setS23_2_reloc(Val); +} +bool HexagonMCInstrInfo::s23_2_reloc(MCExpr const &Expr) { + HexagonMCExpr const *HExpr = llvm::dyn_cast<HexagonMCExpr>(&Expr); + if (!HExpr) + return false; + return HExpr->s23_2_reloc(); +} -void HexagonMCInstrInfo::padEndloop(MCContext &Context, MCInst &MCB) { +void HexagonMCInstrInfo::padEndloop(MCInst &MCB, MCContext &Context) { MCInst Nop; Nop.setOpcode(Hexagon::A2_nop); assert(isBundle(MCB)); @@ -727,22 +757,8 @@ void HexagonMCInstrInfo::padEndloop(MCContext &Context, MCInst &MCB) { bool HexagonMCInstrInfo::prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI) { - if (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) - return false; - - unsigned SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); - switch (SchedClass) { - case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123: - case Hexagon::Sched::ALU64_tc_2_SLOT23: - case Hexagon::Sched::ALU64_tc_3x_SLOT23: - case Hexagon::Sched::M_tc_2_SLOT23: - case Hexagon::Sched::M_tc_3x_SLOT23: - case Hexagon::Sched::S_2op_tc_2_SLOT23: - case Hexagon::Sched::S_3op_tc_2_SLOT23: - case Hexagon::Sched::S_3op_tc_3x_SLOT23: - return true; - } - return false; + const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; + return (F >> HexagonII::PrefersSlot3Pos) & HexagonII::PrefersSlot3Mask; } void HexagonMCInstrInfo::replaceDuplex(MCContext &Context, MCInst &MCB, @@ -778,15 +794,6 @@ void HexagonMCInstrInfo::setMemStoreReorderEnabled(MCInst &MCI) { Operand.setImm(Operand.getImm() | memStoreReorderEnabledMask); assert(isMemStoreReorderEnabled(MCI)); } -void HexagonMCInstrInfo::setS23_2_reloc(MCExpr const &Expr, bool Val) { - HexagonMCExpr &HExpr = - const_cast<HexagonMCExpr &>(*llvm::cast<HexagonMCExpr>(&Expr)); - HExpr.setS23_2_reloc(Val); -} -bool HexagonMCInstrInfo::s23_2_reloc(MCExpr const &Expr) { - HexagonMCExpr const &HExpr = *llvm::cast<HexagonMCExpr>(&Expr); - return HExpr.s23_2_reloc(); -} void HexagonMCInstrInfo::setOuterLoop(MCInst &MCI) { assert(isBundle(MCI)); diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h index d701c3ade69e..2e989adb5ccb 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h @@ -19,11 +19,8 @@ namespace llvm { class HexagonMCChecker; -class MCContext; class MCInstrDesc; class MCInstrInfo; -class MCInst; -class MCOperand; class MCSubtargetInfo; namespace HexagonII { enum class MemAccessSize; @@ -67,16 +64,6 @@ bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &MCB, HexagonMCChecker *Checker); -// Clamp off upper 26 bits of extendable operand for emission -void clampExtended(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI); - -MCInst createBundle(); - -// Return the extender for instruction at Index or nullptr if none -MCInst const *extenderForIndex(MCInst const &MCB, size_t Index); -void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, - MCInst const &MCI); - // Create a duplex instruction given the two subinsts MCInst *deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0, MCInst const &inst1); @@ -86,27 +73,28 @@ MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, // Convert this instruction in to a duplex subinst MCInst deriveSubInst(MCInst const &Inst); +// Clamp off upper 26 bits of extendable operand for emission +void clampExtended(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI); + +MCInst createBundle(); + // Return the extender for instruction at Index or nullptr if none MCInst const *extenderForIndex(MCInst const &MCB, size_t Index); +void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, + MCInst const &MCI); // Return memory access size HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI); - -// Return number of bits in the constant extended operand. -unsigned getBitCount(MCInstrInfo const &MCII, MCInst const &MCI); - -// Return constant extended operand number. -unsigned short getCExtOpNum(MCInstrInfo const &MCII, MCInst const &MCI); - MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI); // Return which duplex group this instruction belongs to unsigned getDuplexCandidateGroup(MCInst const &MI); // Return a list of all possible instruction duplex combinations -SmallVector<DuplexCandidate, 8> getDuplexPossibilties(MCInstrInfo const &MCII, - MCInst const &MCB); +SmallVector<DuplexCandidate, 8> +getDuplexPossibilties(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, + MCInst const &MCB); unsigned getDuplexRegisterNumbering(unsigned Reg); MCExpr const &getExpr(MCExpr const &Expr); @@ -143,7 +131,6 @@ MCOperand const &getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI); unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI); MCOperand const &getNewValueOperand2(MCInstrInfo const &MCII, MCInst const &MCI); - int getSubTarget(MCInstrInfo const &MCII, MCInst const &MCI); // Return the Hexagon ISA class for the insn. @@ -152,6 +139,9 @@ unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI); /// Return the slots used by the insn. unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst const &MCI); +unsigned getOtherReservedSlots(MCInstrInfo const &MCII, + MCSubtargetInfo const &STI, MCInst const &MCI); +bool hasDuplex(MCInstrInfo const &MCII, MCInst const &MCI); // Does the packet have an extender for the instruction at Index bool hasExtenderForIndex(MCInst const &MCB, size_t Index); @@ -161,19 +151,6 @@ bool hasImmExt(MCInst const &MCI); // Return whether the instruction is a legal new-value producer. bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI); bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI); - -// Return the instruction at Index -MCInst const &instruction(MCInst const &MCB, size_t Index); - -// Returns whether this MCInst is a wellformed bundle -bool isBundle(MCInst const &MCI); - -// Return whether the insn is an actual insn. -bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI); -bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI); -bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI); - -// Return the duplex iclass given the two duplex classes unsigned iClassOfDuplexPair(unsigned Ga, unsigned Gb); int64_t minConstant(MCInst const &MCI, size_t Index); @@ -189,6 +166,18 @@ template <unsigned N> bool inRange(MCInst const &MCI, size_t Index) { return isUInt<N>(minConstant(MCI, Index)); } +// Return the instruction at Index +MCInst const &instruction(MCInst const &MCB, size_t Index); +bool isAccumulator(MCInstrInfo const &MCII, MCInst const &MCI); + +// Returns whether this MCInst is a wellformed bundle +bool isBundle(MCInst const &MCI); + +// Return whether the insn is an actual insn. +bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI); +bool isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI); +bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI); + // Return whether the instruction needs to be constant extended. bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI); @@ -229,15 +218,12 @@ bool isMemStoreReorderEnabled(MCInst const &MCI); // Return whether the insn is a new-value consumer. bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI); - -// Return true if the operand can be constant extended. -bool isOperandExtended(MCInstrInfo const &MCII, MCInst const &MCI, - unsigned short OperandNum); +bool isOpExtendable(MCInstrInfo const &MCII, MCInst const &MCI, unsigned short); // Can these two instructions be duplexed bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa, bool ExtendedA, MCInst const &MIb, bool ExtendedB, - bool bisReversable); + bool bisReversable, MCSubtargetInfo const &STI); // Returns whether this bundle is an endloop1 bool isOuterLoop(MCInst const &MCI); @@ -270,12 +256,11 @@ bool mustExtend(MCExpr const &Expr); bool mustNotExtend(MCExpr const &Expr); // Pad the bundle with nops to satisfy endloop requirements -void padEndloop(MCContext &Context, MCInst &MCI); - +void padEndloop(MCInst &MCI, MCContext &Context); bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI); // Replace the instructions inside MCB, represented by Candidate -void replaceDuplex(MCContext &Context, MCInst &MCB, DuplexCandidate Candidate); +void replaceDuplex(MCContext &Context, MCInst &MCI, DuplexCandidate Candidate); bool s23_2_reloc(MCExpr const &Expr); // Marks a bundle as endloop0 @@ -295,7 +280,8 @@ unsigned SubregisterBit(unsigned Consumer, unsigned Producer, unsigned Producer2); // Attempt to find and replace compound pairs -void tryCompound(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI); +void tryCompound(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, + MCContext &Context, MCInst &MCI); } } diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp index 7f8e7a4edb0c..529a5fd5ed82 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp @@ -33,42 +33,39 @@ void HexagonMCShuffler::init(MCInst &MCB) { MCInst const *Extender = nullptr; // Copy the bundle for the shuffling. for (const auto &I : HexagonMCInstrInfo::bundleInstructions(MCB)) { - assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); - MCInst *MI = const_cast<MCInst *>(I.getInst()); + MCInst &MI = *const_cast<MCInst *>(I.getInst()); + DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode()) << '\n'); + assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo()); - if (!HexagonMCInstrInfo::isImmext(*MI)) { - append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, *MI), - false); + if (!HexagonMCInstrInfo::isImmext(MI)) { + append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, MI)); Extender = nullptr; } else - Extender = MI; + Extender = &MI; } } BundleFlags = MCB.getOperand(0).getImm(); } -void HexagonMCShuffler::init(MCInst &MCB, MCInst const *AddMI, +void HexagonMCShuffler::init(MCInst &MCB, MCInst const &AddMI, bool bInsertAtFront) { if (HexagonMCInstrInfo::isBundle(MCB)) { - if (bInsertAtFront && AddMI) - append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, *AddMI), - false); + if (bInsertAtFront) + append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, AddMI)); MCInst const *Extender = nullptr; // Copy the bundle for the shuffling. for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCB)) { assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); - MCInst *MI = const_cast<MCInst *>(I.getInst()); - if (!HexagonMCInstrInfo::isImmext(*MI)) { - append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, *MI), - false); + MCInst &MI = *const_cast<MCInst *>(I.getInst()); + if (!HexagonMCInstrInfo::isImmext(MI)) { + append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, MI)); Extender = nullptr; } else - Extender = MI; + Extender = &MI; } - if (!bInsertAtFront && AddMI) - append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, *AddMI), - false); + if (!bInsertAtFront) + append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, AddMI)); } BundleFlags = MCB.getOperand(0).getImm(); @@ -80,11 +77,11 @@ void HexagonMCShuffler::copyTo(MCInst &MCB) { // Copy the results into the bundle. for (HexagonShuffler::iterator I = begin(); I != end(); ++I) { - MCInst const *MI = I->getDesc(); + MCInst const &MI = I->getDesc(); MCInst const *Extender = I->getExtender(); if (Extender) MCB.addOperand(MCOperand::createInst(Extender)); - MCB.addOperand(MCOperand::createInst(MI)); + MCB.addOperand(MCOperand::createInst(&MI)); } } @@ -98,9 +95,9 @@ bool HexagonMCShuffler::reshuffleTo(MCInst &MCB) { return (!getError()); } -bool llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, - MCInst &MCB) { - HexagonMCShuffler MCS(MCII, STI, MCB); +bool llvm::HexagonMCShuffle(bool Fatal, MCInstrInfo const &MCII, + MCSubtargetInfo const &STI, MCInst &MCB) { + HexagonMCShuffler MCS(true, MCII, STI, MCB); if (DisableShuffle) // Ignore if user chose so. @@ -124,6 +121,18 @@ bool llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, if (!MCS.reshuffleTo(MCB)) { // Unless there is any error, which should not happen at this point. unsigned shuffleError = MCS.getError(); + + if (!Fatal && (shuffleError != HexagonShuffler::SHUFFLE_SUCCESS)) + return false; + if (shuffleError != HexagonShuffler::SHUFFLE_SUCCESS) { + errs() << "\nFailing packet:\n"; + for (const auto& I : HexagonMCInstrInfo::bundleInstructions(MCB)) { + MCInst *MI = const_cast<MCInst *>(I.getInst()); + errs() << HexagonMCInstrInfo::getName(MCII, *MI) << ' ' << HexagonMCInstrInfo::getDesc(MCII, *MI).getOpcode() << '\n'; + } + errs() << '\n'; + } + switch (shuffleError) { default: llvm_unreachable("unknown error"); @@ -176,7 +185,7 @@ llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, DuplexCandidate duplexToTry = possibleDuplexes.pop_back_val(); MCInst Attempt(MCB); HexagonMCInstrInfo::replaceDuplex(Context, Attempt, duplexToTry); - HexagonMCShuffler MCS(MCII, STI, Attempt); // copy packet to the shuffler + HexagonMCShuffler MCS(true, MCII, STI, Attempt); // copy packet to the shuffler if (MCS.size() == 1) { // case of one duplex // copy the created duplex in the shuffler to the bundle MCS.copyTo(MCB); @@ -191,7 +200,7 @@ llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, } if (doneShuffling == false) { - HexagonMCShuffler MCS(MCII, STI, MCB); + HexagonMCShuffler MCS(true, MCII, STI, MCB); doneShuffling = MCS.reshuffleTo(MCB); // shuffle shuffleError = MCS.getError(); } @@ -202,8 +211,8 @@ llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, } bool llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, - MCInst &MCB, MCInst const *AddMI, int fixupCount) { - if (!HexagonMCInstrInfo::isBundle(MCB) || !AddMI) + MCInst &MCB, MCInst const &AddMI, int fixupCount) { + if (!HexagonMCInstrInfo::isBundle(MCB)) return false; // if fixups present, make sure we don't insert too many nops that would @@ -211,8 +220,15 @@ bool llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, unsigned int bundleSize = HexagonMCInstrInfo::bundleSize(MCB); if (bundleSize >= HEXAGON_PACKET_SIZE) return false; + bool bhasDuplex = HexagonMCInstrInfo::hasDuplex(MCII, MCB); if (fixupCount >= 2) { - return false; + if (bhasDuplex) { + if (bundleSize >= HEXAGON_PACKET_SIZE - 1) { + return false; + } + } else { + return false; + } } else { if (bundleSize == HEXAGON_PACKET_SIZE - 1 && fixupCount) return false; @@ -221,7 +237,16 @@ bool llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, if (DisableShuffle) return false; - HexagonMCShuffler MCS(MCII, STI, MCB, AddMI); + // mgl: temporary code (shuffler doesn't take into account the fact that + // a duplex takes up two slots. for example, 3 nops can be put into a packet + // containing a duplex oversubscribing slots by 1). + unsigned maxBundleSize = (HexagonMCInstrInfo::hasImmExt(MCB)) + ? HEXAGON_PACKET_SIZE + : HEXAGON_PACKET_SIZE - 1; + if (bhasDuplex && bundleSize >= maxBundleSize) + return false; + + HexagonMCShuffler MCS(MCII, STI, MCB, AddMI, false); if (!MCS.reshuffleTo(MCB)) { unsigned shuffleError = MCS.getError(); switch (shuffleError) { diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.h b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.h index a21cce1fc240..14bbfda4c914 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.h +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.h @@ -27,16 +27,16 @@ class HexagonMCShuffler : public HexagonShuffler { bool duplex_present; public: - HexagonMCShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, - MCInst &MCB) + HexagonMCShuffler(bool Fatal, MCInstrInfo const &MCII, + MCSubtargetInfo const &STI, MCInst &MCB) : HexagonShuffler(MCII, STI) { init(MCB); }; HexagonMCShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, - MCInst &MCB, const MCInst *AddMI, - bool bInsertAtFront = false) + MCInst &MCB, MCInst const &AddMI, + bool InsertAtFront) : HexagonShuffler(MCII, STI) { - init(MCB, AddMI, bInsertAtFront); + init(MCB, AddMI, InsertAtFront); }; // Copy reordered bundle to another. @@ -49,14 +49,14 @@ public: private: void init(MCInst &MCB); - void init(MCInst &MCB, const MCInst *AddMI, bool bInsertAtFront = false); + void init(MCInst &MCB, MCInst const &AddMI, bool InsertAtFront); }; // Invocation of the shuffler. +bool HexagonMCShuffle(bool Fatal, MCInstrInfo const &MCII, + MCSubtargetInfo const &STI, MCInst &); bool HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, - MCInst &); -bool HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, - MCInst &, const MCInst *, int); + MCInst &, MCInst const &, int); unsigned HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCContext &Context, MCInst &, SmallVector<DuplexCandidate, 8>); diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index 694cf582f8d9..bb98c2bbef6d 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -22,6 +22,7 @@ #include "llvm/MC/MCContext.h" #include "llvm/MC/MCDwarf.h" #include "llvm/MC/MCELFStreamer.h" +#include "llvm/MC/MCInstrAnalysis.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" @@ -66,6 +67,12 @@ static cl::opt<bool> HexagonV55ArchVariant("mv55", cl::Hidden, cl::init(false), static cl::opt<bool> HexagonV60ArchVariant("mv60", cl::Hidden, cl::init(false), cl::desc("Build for Hexagon V60")); +static cl::opt<bool> HexagonV62ArchVariant("mv62", cl::Hidden, cl::init(false), + cl::desc("Build for Hexagon V62")); + +static cl::opt<bool> EnableHVX("mhvx", cl::Hidden, cl::init(false), + cl::desc("Enable Hexagon Vector Extension (HVX)")); + static StringRef DefaultArch = "hexagonv60"; static StringRef HexagonGetArchVariant() { @@ -77,6 +84,8 @@ static StringRef HexagonGetArchVariant() { return "hexagonv55"; if (HexagonV60ArchVariant) return "hexagonv60"; + if (HexagonV62ArchVariant) + return "hexagonv62"; return ""; } @@ -95,31 +104,16 @@ StringRef Hexagon_MC::selectHexagonCPU(const Triple &TT, StringRef CPU) { return ArchV; } -MCInstrInfo *llvm::createHexagonMCInstrInfo() { - MCInstrInfo *X = new MCInstrInfo(); - InitHexagonMCInstrInfo(X); - return X; -} - -static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) { - MCRegisterInfo *X = new MCRegisterInfo(); - InitHexagonMCRegisterInfo(X, Hexagon::R31); - return X; -} - -static MCSubtargetInfo * -createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { - CPU = Hexagon_MC::selectHexagonCPU(TT, CPU); - return createHexagonMCSubtargetInfoImpl(TT, CPU, FS); -} +unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV4FU::SLOT3; } namespace { class HexagonTargetAsmStreamer : public HexagonTargetStreamer { public: HexagonTargetAsmStreamer(MCStreamer &S, - formatted_raw_ostream &, bool, - MCInstPrinter &) + formatted_raw_ostream &OS, + bool isVerboseAsm, + MCInstPrinter &IP) : HexagonTargetStreamer(S) {} void prettyPrintAsm(MCInstPrinter &InstPrinter, raw_ostream &OS, @@ -156,24 +150,15 @@ public: class HexagonTargetELFStreamer : public HexagonTargetStreamer { public: + MCELFStreamer &getStreamer() { + return static_cast<MCELFStreamer &>(Streamer); + } HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI) : HexagonTargetStreamer(S) { - auto Bits = STI.getFeatureBits(); - unsigned Flags = 0; - if (Bits[Hexagon::ArchV60]) - Flags = ELF::EF_HEXAGON_MACH_V60; - else if (Bits[Hexagon::ArchV55]) - Flags = ELF::EF_HEXAGON_MACH_V55; - else if (Bits[Hexagon::ArchV5]) - Flags = ELF::EF_HEXAGON_MACH_V5; - else if (Bits[Hexagon::ArchV4]) - Flags = ELF::EF_HEXAGON_MACH_V4; - getStreamer().getAssembler().setELFHeaderEFlags(Flags); + MCAssembler &MCA = getStreamer().getAssembler(); + MCA.setELFHeaderEFlags(Hexagon_MC::GetELFFlags(STI)); } - MCELFStreamer &getStreamer() { - return static_cast<MCELFStreamer &>(Streamer); - } void EmitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment, @@ -196,13 +181,26 @@ public: } // end anonymous namespace +llvm::MCInstrInfo *llvm::createHexagonMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitHexagonMCInstrInfo(X); + return X; +} + +static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) { + MCRegisterInfo *X = new MCRegisterInfo(); + InitHexagonMCRegisterInfo(X, Hexagon::R31); + return X; +} + static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI, const Triple &TT) { MCAsmInfo *MAI = new HexagonMCAsmInfo(TT); // VirtualFP = (R30 + #0). MCCFIInstruction Inst = - MCCFIInstruction::createDefCfa(nullptr, Hexagon::R30, 0); + MCCFIInstruction::createDefCfa(nullptr, + MRI.getDwarfRegNum(Hexagon::R30, true), 0); MAI->addInitialFrameState(Inst); return MAI; @@ -212,31 +210,138 @@ static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) { + const MCRegisterInfo &MRI) +{ if (SyntaxVariant == 0) - return (new HexagonInstPrinter(MAI, MII, MRI)); + return new HexagonInstPrinter(MAI, MII, MRI); else return nullptr; } -static MCTargetStreamer *createMCAsmTargetStreamer(MCStreamer &S, - formatted_raw_ostream &OS, - MCInstPrinter *InstPrint, - bool IsVerboseAsm) { - return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *InstPrint); +static MCTargetStreamer * +createMCAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, + MCInstPrinter *IP, bool IsVerboseAsm) { + return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *IP); } -static MCStreamer *createMCStreamer(Triple const &T, MCContext &Context, - MCAsmBackend &MAB, raw_pwrite_stream &OS, - MCCodeEmitter *Emitter, bool RelaxAll) { - return createHexagonELFStreamer(Context, MAB, OS, Emitter); +static MCStreamer *createMCStreamer(Triple const &T, + MCContext &Context, + MCAsmBackend &MAB, + raw_pwrite_stream &OS, + MCCodeEmitter *Emitter, + bool RelaxAll) { + return createHexagonELFStreamer(T, Context, MAB, OS, Emitter); } static MCTargetStreamer * -createHexagonObjectTargetStreamer(MCStreamer &S, MCSubtargetInfo const &STI) { +createHexagonObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { return new HexagonTargetELFStreamer(S, STI); } +static void LLVM_ATTRIBUTE_UNUSED clearFeature(MCSubtargetInfo* STI, uint64_t F) { + uint64_t FB = STI->getFeatureBits().to_ullong(); + if (FB & (1ULL << F)) + STI->ToggleFeature(F); +} + +static bool LLVM_ATTRIBUTE_UNUSED checkFeature(MCSubtargetInfo* STI, uint64_t F) { + uint64_t FB = STI->getFeatureBits().to_ullong(); + return (FB & (1ULL << F)) != 0; +} + +StringRef Hexagon_MC::ParseHexagonTriple(const Triple &TT, StringRef CPU) { + StringRef CPUName = Hexagon_MC::selectHexagonCPU(TT, CPU); + StringRef FS = ""; + if (EnableHVX) { + if (CPUName.equals_lower("hexagonv60") || + CPUName.equals_lower("hexagonv62")) + FS = "+hvx"; + } + return FS; +} + +static bool isCPUValid(std::string CPU) +{ + std::vector<std::string> table + { + "hexagonv4", + "hexagonv5", + "hexagonv55", + "hexagonv60", + "hexagonv62", + }; + + return std::find(table.begin(), table.end(), CPU) != table.end(); +} + +MCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT, + StringRef CPU, + StringRef FS) { + StringRef ArchFS = (FS.size()) ? FS : Hexagon_MC::ParseHexagonTriple(TT, CPU); + StringRef CPUName = Hexagon_MC::selectHexagonCPU(TT, CPU); + if (!isCPUValid(CPUName.str())) { + errs() << "error: invalid CPU \"" << CPUName.str().c_str() + << "\" specified\n"; + return nullptr; + } + + MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS); + if (X->getFeatureBits()[Hexagon::ExtensionHVXDbl]) { + llvm::FeatureBitset Features = X->getFeatureBits(); + X->setFeatureBits(Features.set(Hexagon::ExtensionHVX)); + } + return X; +} + +unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) { + static std::map<StringRef,unsigned> ElfFlags = { + {"hexagonv4", ELF::EF_HEXAGON_MACH_V4}, + {"hexagonv5", ELF::EF_HEXAGON_MACH_V5}, + {"hexagonv55", ELF::EF_HEXAGON_MACH_V55}, + {"hexagonv60", ELF::EF_HEXAGON_MACH_V60}, + {"hexagonv62", ELF::EF_HEXAGON_MACH_V62}, + }; + + auto F = ElfFlags.find(STI.getCPU()); + assert(F != ElfFlags.end() && "Unrecognized Architecture"); + return F->second; +} + +namespace { +class HexagonMCInstrAnalysis : public MCInstrAnalysis { +public: + HexagonMCInstrAnalysis(MCInstrInfo const *Info) : MCInstrAnalysis(Info) {} + + bool isUnconditionalBranch(MCInst const &Inst) const override { + //assert(!HexagonMCInstrInfo::isBundle(Inst)); + return MCInstrAnalysis::isUnconditionalBranch(Inst); + } + + bool isConditionalBranch(MCInst const &Inst) const override { + //assert(!HexagonMCInstrInfo::isBundle(Inst)); + return MCInstrAnalysis::isConditionalBranch(Inst); + } + + bool evaluateBranch(MCInst const &Inst, uint64_t Addr, + uint64_t Size, uint64_t &Target) const override { + //assert(!HexagonMCInstrInfo::isBundle(Inst)); + if(!HexagonMCInstrInfo::isExtendable(*Info, Inst)) + return false; + auto const &Extended(HexagonMCInstrInfo::getExtendableOperand(*Info, Inst)); + assert(Extended.isExpr()); + int64_t Value; + if(!Extended.getExpr()->evaluateAsAbsolute(Value)) + return false; + Target = Value; + return true; + } +}; +} + +static MCInstrAnalysis *createHexagonMCInstrAnalysis(const MCInstrInfo *Info) { + return new HexagonMCInstrAnalysis(Info); +} + // Force static initialization. extern "C" void LLVMInitializeHexagonTargetMC() { // Register the MC asm info. @@ -252,7 +357,7 @@ extern "C" void LLVMInitializeHexagonTargetMC() { // Register the MC subtarget info. TargetRegistry::RegisterMCSubtargetInfo(getTheHexagonTarget(), - createHexagonMCSubtargetInfo); + Hexagon_MC::createHexagonMCSubtargetInfo); // Register the MC Code Emitter TargetRegistry::RegisterMCCodeEmitter(getTheHexagonTarget(), @@ -262,8 +367,18 @@ extern "C" void LLVMInitializeHexagonTargetMC() { TargetRegistry::RegisterMCAsmBackend(getTheHexagonTarget(), createHexagonAsmBackend); + + // Register the MC instruction analyzer. + TargetRegistry::RegisterMCInstrAnalysis(getTheHexagonTarget(), + createHexagonMCInstrAnalysis); + // Register the obj streamer - TargetRegistry::RegisterELFStreamer(getTheHexagonTarget(), createMCStreamer); + TargetRegistry::RegisterELFStreamer(getTheHexagonTarget(), + createMCStreamer); + + // Register the obj target streamer + TargetRegistry::RegisterObjectTargetStreamer(getTheHexagonTarget(), + createHexagonObjectTargetStreamer); // Register the asm streamer TargetRegistry::RegisterAsmTargetStreamer(getTheHexagonTarget(), @@ -272,7 +387,4 @@ extern "C" void LLVMInitializeHexagonTargetMC() { // Register the MC Inst Printer TargetRegistry::RegisterMCInstPrinter(getTheHexagonTarget(), createHexagonMCInstPrinter); - - TargetRegistry::RegisterObjectTargetStreamer( - getTheHexagonTarget(), createHexagonObjectTargetStreamer); } diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h index 6e677e9d9f86..6bb69be6142e 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h @@ -41,6 +41,18 @@ extern cl::opt<bool> HexagonDisableDuplex; extern const InstrStage HexagonStages[]; MCInstrInfo *createHexagonMCInstrInfo(); +MCRegisterInfo *createHexagonMCRegisterInfo(StringRef TT); + +namespace Hexagon_MC { + StringRef ParseHexagonTriple(const Triple &TT, StringRef CPU); + StringRef selectHexagonCPU(const Triple &TT, StringRef CPU); + + /// Create a Hexagon MCSubtargetInfo instance. This is exposed so Asm parser, + /// etc. do not need to go through TargetRegistry. + MCSubtargetInfo *createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, + StringRef FS); + unsigned GetELFFlags(const MCSubtargetInfo &STI); +} MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, @@ -54,13 +66,9 @@ MCAsmBackend *createHexagonAsmBackend(const Target &T, MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, StringRef CPU); -namespace Hexagon_MC { - - StringRef selectHexagonCPU(const Triple &TT, StringRef CPU); - -} // end namespace Hexagon_MC +unsigned HexagonGetLastSlot(); -} // end namespace llvm +} // End llvm namespace // Define symbolic names for Hexagon registers. This defines a mapping from // register name to register number. diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp index 88f37d620dcf..853f76213d38 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp @@ -22,6 +22,7 @@ #include "MCTargetDesc/HexagonMCInstrInfo.h" #include "HexagonShuffler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/Format.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" @@ -37,16 +38,16 @@ class HexagonBid { unsigned Bid; public: - HexagonBid() : Bid(0){}; - HexagonBid(unsigned B) { Bid = B ? MAX / countPopulation(B) : 0; }; + HexagonBid() : Bid(0){} + HexagonBid(unsigned B) { Bid = B ? MAX / countPopulation(B) : 0; } // Check if the insn priority is overflowed. - bool isSold() const { return (Bid >= MAX); }; + bool isSold() const { return (Bid >= MAX); } HexagonBid &operator+=(const HexagonBid &B) { Bid += B.Bid; return *this; - }; + } }; // Slot shuffling allocation. @@ -56,7 +57,7 @@ class HexagonUnitAuction { unsigned isSold : HEXAGON_PACKET_SIZE; public: - HexagonUnitAuction() : isSold(0){}; + HexagonUnitAuction(unsigned cs = 0) : isSold(cs){}; // Allocate slots. bool bid(unsigned B) { @@ -70,29 +71,29 @@ public: isSold |= Scores[i].isSold() << i; } return true; - ; } else // Error if the desired slots are already full. return false; - }; + } }; } // end anonymous namespace unsigned HexagonResource::setWeight(unsigned s) { const unsigned SlotWeight = 8; const unsigned MaskWeight = SlotWeight - 1; - bool Key = (1 << s) & getUnits(); - - // TODO: Improve this API so that we can prevent misuse statically. - assert(SlotWeight * s < 32 && "Argument to setWeight too large."); + unsigned Units = getUnits(); + unsigned Key = ((1u << s) & Units) != 0; // Calculate relative weight of the insn for the given slot, weighing it the // heavier the more restrictive the insn is and the lowest the slots that the // insn may be executed in. - Weight = - (Key << (SlotWeight * s)) * ((MaskWeight - countPopulation(getUnits())) - << countTrailingZeros(getUnits())); - return (Weight); + if (Key == 0 || Units == 0 || (SlotWeight*s >= 32)) + return Weight = 0; + + unsigned Ctpop = countPopulation(Units); + unsigned Cttz = countTrailingZeros(Units); + Weight = (1u << (SlotWeight * s)) * ((MaskWeight - Ctpop) << Cttz); + return Weight; } void HexagonCVIResource::SetupTUL(TypeUnitsAndLanes *TUL, StringRef CPU) { @@ -104,7 +105,10 @@ void HexagonCVIResource::SetupTUL(TypeUnitsAndLanes *TUL, StringRef CPU) { (*TUL)[HexagonII::TypeCVI_VP] = UnitsAndLanes(CVI_XLANE, 1); (*TUL)[HexagonII::TypeCVI_VP_VS] = UnitsAndLanes(CVI_XLANE, 2); (*TUL)[HexagonII::TypeCVI_VS] = UnitsAndLanes(CVI_SHIFT, 1); - (*TUL)[HexagonII::TypeCVI_VINLANESAT] = UnitsAndLanes(CVI_SHIFT, 1); + (*TUL)[HexagonII::TypeCVI_VINLANESAT] = + (CPU == "hexagonv60" || CPU == "hexagonv61" || CPU == "hexagonv61v1") ? + UnitsAndLanes(CVI_SHIFT, 1) : + UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1); (*TUL)[HexagonII::TypeCVI_VM_LD] = UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1); (*TUL)[HexagonII::TypeCVI_VM_TMP_LD] = UnitsAndLanes(CVI_NONE, 0); @@ -141,6 +145,40 @@ HexagonCVIResource::HexagonCVIResource(TypeUnitsAndLanes *TUL, } } +struct CVIUnits { + unsigned Units; + unsigned Lanes; +}; +typedef SmallVector<struct CVIUnits, 8> HVXInstsT; + +static unsigned makeAllBits(unsigned startBit, unsigned Lanes) + +{ + for (unsigned i = 1 ; i < Lanes ; ++i) + startBit = (startBit << 1) | startBit; + return startBit; +} + +static bool checkHVXPipes(const HVXInstsT& hvxInsts, unsigned startIdx, unsigned usedUnits) + +{ + if (startIdx < hvxInsts.size()) { + if (!hvxInsts[startIdx].Units) + return checkHVXPipes(hvxInsts, startIdx + 1, usedUnits); + for (unsigned b = 0x1 ; b <= 0x8 ; b <<= 1) { + if ((hvxInsts[startIdx].Units & b) == 0) + continue; + unsigned allBits = makeAllBits(b, hvxInsts[startIdx].Lanes); + if ((allBits & usedUnits) == 0) { + if (checkHVXPipes(hvxInsts, startIdx + 1, usedUnits | allBits)) + return true; + } + } + return false; + } + return true; +} + HexagonShuffler::HexagonShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI) : MCII(MCII), STI(STI) { @@ -154,21 +192,82 @@ void HexagonShuffler::reset() { Error = SHUFFLE_SUCCESS; } -void HexagonShuffler::append(MCInst const *ID, MCInst const *Extender, - unsigned S, bool X) { - HexagonInstr PI(&TUL, MCII, ID, Extender, S, X); +void HexagonShuffler::append(MCInst const &ID, MCInst const *Extender, + unsigned S) { + HexagonInstr PI(&TUL, MCII, &ID, Extender, S); Packet.push_back(PI); } +static struct { + unsigned first; + unsigned second; +} jumpSlots[] = { {8, 4}, {8, 2}, {8, 1}, {4, 2}, {4, 1}, {2, 1} }; +#define MAX_JUMP_SLOTS (sizeof(jumpSlots)/sizeof(jumpSlots[0])) + +namespace { +bool isDuplexAGroup(unsigned Opcode) { + switch (Opcode) { + case Hexagon::SA1_addi: + case Hexagon::SA1_addrx: + case Hexagon::SA1_addsp: + case Hexagon::SA1_and1: + case Hexagon::SA1_clrf: + case Hexagon::SA1_clrfnew: + case Hexagon::SA1_clrt: + case Hexagon::SA1_clrtnew: + case Hexagon::SA1_cmpeqi: + case Hexagon::SA1_combine0i: + case Hexagon::SA1_combine1i: + case Hexagon::SA1_combine2i: + case Hexagon::SA1_combine3i: + case Hexagon::SA1_combinerz: + case Hexagon::SA1_combinezr: + case Hexagon::SA1_dec: + case Hexagon::SA1_inc: + case Hexagon::SA1_seti: + case Hexagon::SA1_setin1: + case Hexagon::SA1_sxtb: + case Hexagon::SA1_sxth: + case Hexagon::SA1_tfr: + case Hexagon::SA1_zxtb: + case Hexagon::SA1_zxth: + return true; + break; + default: + return false; + } +} + +unsigned countNeitherAnorX(MCInstrInfo const &MCII, MCInst const &ID) { + unsigned Result = 0; + unsigned Type = HexagonMCInstrInfo::getType(MCII, ID); + if (Type == HexagonII::TypeDUPLEX) { + unsigned subInst0Opcode = ID.getOperand(0).getInst()->getOpcode(); + unsigned subInst1Opcode = ID.getOperand(1).getInst()->getOpcode(); + Result += !isDuplexAGroup(subInst0Opcode); + Result += !isDuplexAGroup(subInst1Opcode); + } else + Result += Type != HexagonII::TypeALU32_2op && + Type != HexagonII::TypeALU32_3op && + Type != HexagonII::TypeALU32_ADDI && + Type != HexagonII::TypeS_2op && + Type != HexagonII::TypeS_3op && + Type != HexagonII::TypeALU64 && + (Type != HexagonII::TypeM || + HexagonMCInstrInfo::isFloat(MCII, ID)); + return Result; +} +} + /// Check that the packet is legal and enforce relative insn order. bool HexagonShuffler::check() { // Descriptive slot masks. const unsigned slotSingleLoad = 0x1, slotSingleStore = 0x1, slotOne = 0x2, - slotThree = 0x8, slotFirstJump = 0x8, slotLastJump = 0x4, + slotThree = 0x8, //slotFirstJump = 0x8, slotFirstLoadStore = 0x2, slotLastLoadStore = 0x1; // Highest slots for branches and stores used to keep their original order. - unsigned slotJump = slotFirstJump; + //unsigned slotJump = slotFirstJump; unsigned slotLoadStore = slotFirstLoadStore; // Number of branches, solo branches, indirect branches. unsigned jumps = 0, jump1 = 0; @@ -188,36 +287,41 @@ bool HexagonShuffler::check() { unsigned onlyNo1 = 0; unsigned xtypeFloat = 0; unsigned pSlot3Cnt = 0; + unsigned memops = 0; + unsigned deallocs = 0; iterator slot3ISJ = end(); + std::vector<iterator> foundBranches; + unsigned reservedSlots = 0; // Collect information from the insns in the packet. for (iterator ISJ = begin(); ISJ != end(); ++ISJ) { - MCInst const *ID = ISJ->getDesc(); - - if (HexagonMCInstrInfo::isSolo(MCII, *ID)) - solo += !ISJ->isSoloException(); - else if (HexagonMCInstrInfo::isSoloAX(MCII, *ID)) - onlyAX += !ISJ->isSoloException(); - else if (HexagonMCInstrInfo::isSoloAin1(MCII, *ID)) - onlyAin1 += !ISJ->isSoloException(); - if (HexagonMCInstrInfo::getType(MCII, *ID) != HexagonII::TypeALU32 && - HexagonMCInstrInfo::getType(MCII, *ID) != HexagonII::TypeXTYPE) - ++neitherAnorX; - if (HexagonMCInstrInfo::prefersSlot3(MCII, *ID)) { + MCInst const &ID = ISJ->getDesc(); + + if (HexagonMCInstrInfo::isSolo(MCII, ID)) + solo++; + else if (HexagonMCInstrInfo::isSoloAX(MCII, ID)) + onlyAX++; + else if (HexagonMCInstrInfo::isSoloAin1(MCII, ID)) + onlyAin1++; + neitherAnorX += countNeitherAnorX(MCII, ID); + if (HexagonMCInstrInfo::prefersSlot3(MCII, ID)) { ++pSlot3Cnt; slot3ISJ = ISJ; } - if (HexagonMCInstrInfo::isCofMax1(MCII, *ID)) + reservedSlots |= HexagonMCInstrInfo::getOtherReservedSlots(MCII, STI, ID); + if (HexagonMCInstrInfo::isCofMax1(MCII, ID)) ++jump1; - switch (HexagonMCInstrInfo::getType(MCII, *ID)) { - case HexagonII::TypeXTYPE: - if (HexagonMCInstrInfo::isFloat(MCII, *ID)) + switch (HexagonMCInstrInfo::getType(MCII, ID)) { + case HexagonII::TypeS_2op: + case HexagonII::TypeS_3op: + case HexagonII::TypeALU64: + if (HexagonMCInstrInfo::isFloat(MCII, ID)) ++xtypeFloat; break; - case HexagonII::TypeJR: case HexagonII::TypeJ: ++jumps; + foundBranches.push_back(ISJ); break; case HexagonII::TypeCVI_VM_VP_LDU: ++onlyNo1; @@ -228,10 +332,14 @@ bool HexagonShuffler::check() { case HexagonII::TypeLD: ++loads; ++memory; - if (ISJ->Core.getUnits() == slotSingleLoad) + if (ISJ->Core.getUnits() == slotSingleLoad || + HexagonMCInstrInfo::getType(MCII, ID) == + HexagonII::TypeCVI_VM_VP_LDU) ++load0; - if (HexagonMCInstrInfo::getDesc(MCII, *ID).isReturn()) - ++jumps, ++jump1; // DEALLOC_RETURN is of type LD. + if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn()) { + ++deallocs, ++jumps, ++jump1; // DEALLOC_RETURN is of type LD. + foundBranches.push_back(ISJ); + } break; case HexagonII::TypeCVI_VM_STU: ++onlyNo1; @@ -241,27 +349,66 @@ bool HexagonShuffler::check() { case HexagonII::TypeST: ++stores; ++memory; - if (ISJ->Core.getUnits() == slotSingleStore) + if (ISJ->Core.getUnits() == slotSingleStore || + HexagonMCInstrInfo::getType(MCII, ID) == HexagonII::TypeCVI_VM_STU) ++store0; break; case HexagonII::TypeV4LDST: ++loads; ++stores; ++store1; + ++memops; ++memory; break; - case HexagonII::TypeNV: + case HexagonII::TypeNCJ: ++memory; // NV insns are memory-like. - if (HexagonMCInstrInfo::getDesc(MCII, *ID).isBranch()) + if (HexagonMCInstrInfo::getDesc(MCII, ID).isBranch()) { ++jumps, ++jump1; + foundBranches.push_back(ISJ); + } + break; + case HexagonII::TypeV2LDST: + if(HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { + ++loads; + ++memory; + if (ISJ->Core.getUnits() == slotSingleLoad || + HexagonMCInstrInfo::getType(MCII,ID) == + HexagonII::TypeCVI_VM_VP_LDU) + ++load0; + } + else { + assert(HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()); + ++memory; + ++stores; + } break; case HexagonII::TypeCR: // Legacy conditional branch predicated on a register. - case HexagonII::TypeSYSTEM: - if (HexagonMCInstrInfo::getDesc(MCII, *ID).mayLoad()) - ++loads; + case HexagonII::TypeCJ: + if (HexagonMCInstrInfo::getDesc(MCII, ID).isBranch()) { + ++jumps; + foundBranches.push_back(ISJ); + } + break; + case HexagonII::TypeDUPLEX: { + ++duplex; + MCInst const &Inst0 = *ID.getOperand(0).getInst(); + MCInst const &Inst1 = *ID.getOperand(1).getInst(); + if (HexagonMCInstrInfo::isCofMax1(MCII, Inst0)) + ++jump1; + if (HexagonMCInstrInfo::isCofMax1(MCII, Inst1)) + ++jump1; + if (HexagonMCInstrInfo::getDesc(MCII, Inst0).isBranch()) { + ++jumps; + foundBranches.push_back(ISJ); + } + if (HexagonMCInstrInfo::getDesc(MCII, Inst1).isBranch()) { + ++jumps; + foundBranches.push_back(ISJ); + } break; } + } } // Check if the packet is legal. @@ -277,12 +424,20 @@ bool HexagonShuffler::check() { Error = SHUFFLE_ERROR_BRANCHES; return false; } + if (memops && stores > 1) { + Error = SHUFFLE_ERROR_STORE_LOAD_CONFLICT; + return false; + } + if (deallocs && stores) { + Error = SHUFFLE_ERROR_STORE_LOAD_CONFLICT; + return false; + } // Modify packet accordingly. // TODO: need to reserve slots #0 and #1 for duplex insns. bool bOnlySlot3 = false; for (iterator ISJ = begin(); ISJ != end(); ++ISJ) { - MCInst const *ID = ISJ->getDesc(); + MCInst const &ID = ISJ->getDesc(); if (!ISJ->Core.getUnits()) { // Error if insn may not be executed in any slot. @@ -291,40 +446,26 @@ bool HexagonShuffler::check() { } // Exclude from slot #1 any insn but A2_nop. - if (HexagonMCInstrInfo::getDesc(MCII, *ID).getOpcode() != Hexagon::A2_nop) + if (HexagonMCInstrInfo::getDesc(MCII, ID).getOpcode() != Hexagon::A2_nop) if (onlyNo1) ISJ->Core.setUnits(ISJ->Core.getUnits() & ~slotOne); // Exclude from slot #1 any insn but A-type. - if (HexagonMCInstrInfo::getType(MCII, *ID) != HexagonII::TypeALU32) + if (HexagonMCInstrInfo::getType(MCII, ID) != HexagonII::TypeALU32_2op && + HexagonMCInstrInfo::getType(MCII, ID) != HexagonII::TypeALU32_3op && + HexagonMCInstrInfo::getType(MCII, ID) != HexagonII::TypeALU32_ADDI) if (onlyAin1) ISJ->Core.setUnits(ISJ->Core.getUnits() & ~slotOne); - // Branches must keep the original order. - if (HexagonMCInstrInfo::getDesc(MCII, *ID).isBranch() || - HexagonMCInstrInfo::getDesc(MCII, *ID).isCall()) - if (jumps > 1) { - if (slotJump < slotLastJump) { - // Error if indirect branch with another branch or - // no more slots available for branches. - Error = SHUFFLE_ERROR_BRANCHES; - return false; - } - // Pin the branch to the highest slot available to it. - ISJ->Core.setUnits(ISJ->Core.getUnits() & slotJump); - // Update next highest slot available to branches. - slotJump >>= 1; - } - // A single load must use slot #0. - if (HexagonMCInstrInfo::getDesc(MCII, *ID).mayLoad()) { - if (loads == 1 && loads == memory) + if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { + if (loads == 1 && loads == memory && memops == 0) // Pin the load to slot #0. ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleLoad); } // A single store must use slot #0. - if (HexagonMCInstrInfo::getDesc(MCII, *ID).mayStore()) { + if (HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()) { if (!store0) { if (stores == 1) ISJ->Core.setUnits(ISJ->Core.getUnits() & slotSingleStore); @@ -347,7 +488,7 @@ bool HexagonShuffler::check() { } } - // flag if an instruction can only be executed in slot 3 + // flag if an instruction requires to be in slot 3 if (ISJ->Core.getUnits() == slotThree) bOnlySlot3 = true; @@ -358,14 +499,61 @@ bool HexagonShuffler::check() { } } + // preserve branch order bool validateSlots = true; - if (bOnlySlot3 == false && pSlot3Cnt == 1 && slot3ISJ != end()) { + if (jumps > 1) { + if (foundBranches.size() > 2) { + Error = SHUFFLE_ERROR_BRANCHES; + return false; + } + + // try all possible choices + for (unsigned int i = 0 ; i < MAX_JUMP_SLOTS ; ++i) { + // validate first jump with this slot rule + if (!(jumpSlots[i].first & foundBranches[0]->Core.getUnits())) + continue; + + // validate second jump with this slot rule + if (!(jumpSlots[i].second & foundBranches[1]->Core.getUnits())) + continue; + + // both valid for this configuration, set new slot rules + PacketSave = Packet; + foundBranches[0]->Core.setUnits(jumpSlots[i].first); + foundBranches[1]->Core.setUnits(jumpSlots[i].second); + + HexagonUnitAuction AuctionCore(reservedSlots); + std::sort(begin(), end(), HexagonInstr::lessCore); + + // see if things ok with that instruction being pinned to slot "slotJump" + bool bFail = false; + for (iterator I = begin(); I != end() && bFail != true; ++I) + if (!AuctionCore.bid(I->Core.getUnits())) + bFail = true; + + // if yes, great, if not then restore original slot mask + if (!bFail) { + validateSlots = false; // all good, no need to re-do auction + break; + } + else + // restore original values + Packet = PacketSave; + } + if (validateSlots == true) { + Error = SHUFFLE_ERROR_NOSLOTS; + return false; + } + } + + if (jumps <= 1 && bOnlySlot3 == false && pSlot3Cnt == 1 && slot3ISJ != end()) { + validateSlots = true; // save off slot mask of instruction marked with A_PREFER_SLOT3 // and then pin it to slot #3 unsigned saveUnits = slot3ISJ->Core.getUnits(); slot3ISJ->Core.setUnits(saveUnits & slotThree); - HexagonUnitAuction AuctionCore; + HexagonUnitAuction AuctionCore(reservedSlots); std::sort(begin(), end(), HexagonInstr::lessCore); // see if things ok with that instruction being pinned to slot #3 @@ -379,16 +567,16 @@ bool HexagonShuffler::check() { validateSlots = false; // all good, no need to re-do auction else for (iterator ISJ = begin(); ISJ != end(); ++ISJ) { - MCInst const *ID = ISJ->getDesc(); - if (HexagonMCInstrInfo::prefersSlot3(MCII, *ID)) + MCInst const &ID = ISJ->getDesc(); + if (HexagonMCInstrInfo::prefersSlot3(MCII, ID)) ISJ->Core.setUnits(saveUnits); } } - // Check if any slot, core, is over-subscribed. + // Check if any slot, core or CVI, is over-subscribed. // Verify the core slot subscriptions. if (validateSlots) { - HexagonUnitAuction AuctionCore; + HexagonUnitAuction AuctionCore(reservedSlots); std::sort(begin(), end(), HexagonInstr::lessCore); @@ -399,17 +587,27 @@ bool HexagonShuffler::check() { } } // Verify the CVI slot subscriptions. - { - HexagonUnitAuction AuctionCVI; - - std::sort(begin(), end(), HexagonInstr::lessCVI); - - for (iterator I = begin(); I != end(); ++I) - for (unsigned i = 0; i < I->CVI.getLanes(); ++i) // TODO: I->CVI.isValid? - if (!AuctionCVI.bid(I->CVI.getUnits() << i)) { - Error = SHUFFLE_ERROR_SLOTS; - return false; - } + std::sort(begin(), end(), HexagonInstr::lessCVI); + // create vector of hvx instructions to check + HVXInstsT hvxInsts; + hvxInsts.clear(); + for (iterator I = begin(); I != end(); ++I) { + struct CVIUnits inst; + inst.Units = I->CVI.getUnits(); + inst.Lanes = I->CVI.getLanes(); + if (inst.Units == 0) + continue; // not an hvx inst or an hvx inst that doesn't uses any pipes + hvxInsts.push_back(inst); + } + // if there are any hvx instructions in this packet, check pipe usage + if (hvxInsts.size() > 0) { + unsigned startIdx, usedUnits; + startIdx = usedUnits = 0x0; + if (checkHVXPipes(hvxInsts, startIdx, usedUnits) == false) { + // too many pipes used to be valid + Error = SHUFFLE_ERROR_SLOTS; + return false; + } } Error = SHUFFLE_SUCCESS; @@ -452,10 +650,12 @@ bool HexagonShuffler::shuffle() { } for (iterator ISJ = begin(); ISJ != end(); ++ISJ) - DEBUG(dbgs().write_hex(ISJ->Core.getUnits()); - dbgs() << ':' - << HexagonMCInstrInfo::getDesc(MCII, *ISJ->getDesc()) - .getOpcode(); + DEBUG(dbgs().write_hex(ISJ->Core.getUnits()); if (ISJ->CVI.isValid()) { + dbgs() << '/'; + dbgs().write_hex(ISJ->CVI.getUnits()) << '|'; + dbgs() << ISJ->CVI.getLanes(); + } dbgs() << ':' + << HexagonMCInstrInfo::getDesc(MCII, ISJ->getDesc()).getOpcode(); dbgs() << '\n'); DEBUG(dbgs() << '\n'); diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h index a093f8545132..36e8fa19d467 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h @@ -35,7 +35,8 @@ public: HexagonResource(unsigned s) { setUnits(s); }; void setUnits(unsigned s) { - Slots = s & ~(~0U << HEXAGON_PACKET_SIZE); + Slots = s & ((1u << HEXAGON_PACKET_SIZE) - 1); + setWeight(s); }; unsigned setWeight(unsigned s); @@ -44,7 +45,8 @@ public: // Check if the resources are in ascending slot order. static bool lessUnits(const HexagonResource &A, const HexagonResource &B) { - return (countPopulation(A.getUnits()) < countPopulation(B.getUnits())); + return (countPopulation(A.getUnits()) < + countPopulation(B.getUnits())); }; // Check if the resources are in ascending weight order. static bool lessWeight(const HexagonResource &A, const HexagonResource &B) { @@ -86,10 +88,10 @@ public: unsigned s, MCInst const *id); static void SetupTUL(TypeUnitsAndLanes *TUL, StringRef CPU); - bool isValid() const { return (Valid); }; - unsigned getLanes() const { return (Lanes); }; - bool mayLoad() const { return (Load); }; - bool mayStore() const { return (Store); }; + bool isValid() const { return Valid; }; + unsigned getLanes() const { return Lanes; }; + bool mayLoad() const { return Load; }; + bool mayStore() const { return Store; }; }; // Handle to an insn used by the shuffling algorithm. @@ -100,21 +102,17 @@ class HexagonInstr { MCInst const *Extender; HexagonResource Core; HexagonCVIResource CVI; - bool SoloException; public: HexagonInstr(HexagonCVIResource::TypeUnitsAndLanes *T, MCInstrInfo const &MCII, MCInst const *id, - MCInst const *Extender, unsigned s, bool x = false) - : ID(id), Extender(Extender), Core(s), CVI(T, MCII, s, id), - SoloException(x) {}; + MCInst const *Extender, unsigned s) + : ID(id), Extender(Extender), Core(s), CVI(T, MCII, s, id) {} - MCInst const *getDesc() const { return (ID); }; + MCInst const &getDesc() const { return *ID; }; MCInst const *getExtender() const { return Extender; } - unsigned isSoloException() const { return (SoloException); }; - // Check if the handles are in ascending order for shuffling purposes. bool operator<(const HexagonInstr &B) const { return (HexagonResource::lessWeight(B.Core, Core)); @@ -136,6 +134,7 @@ class HexagonShuffler { // Insn handles in a bundle. HexagonPacket Packet; + HexagonPacket PacketSave; // Shuffling error code. unsigned Error; @@ -178,8 +177,7 @@ public: iterator end() { return (Packet.end()); }; // Add insn handle to the bundle . - void append(MCInst const *ID, MCInst const *Extender, unsigned S, - bool X = false); + void append(MCInst const &ID, MCInst const *Extender, unsigned S); // Return the error code for the last check or shuffling of the bundle. void setError(unsigned Err) { Error = Err; }; diff --git a/contrib/llvm/lib/Target/Hexagon/RDFCopy.cpp b/contrib/llvm/lib/Target/Hexagon/RDFCopy.cpp index 392871628d98..57ce9fabc5e3 100644 --- a/contrib/llvm/lib/Target/Hexagon/RDFCopy.cpp +++ b/contrib/llvm/lib/Target/Hexagon/RDFCopy.cpp @@ -11,6 +11,7 @@ #include "RDFCopy.h" #include "RDFGraph.h" +#include "RDFLiveness.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineInstr.h" @@ -53,47 +54,12 @@ bool CopyPropagation::interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) { void CopyPropagation::recordCopy(NodeAddr<StmtNode*> SA, EqualityMap &EM) { CopyMap.insert(std::make_pair(SA.Id, EM)); Copies.push_back(SA.Id); - - for (auto I : EM) { - auto FS = DefM.find(I.second.Reg); - if (FS == DefM.end() || FS->second.empty()) - continue; // Undefined source - RDefMap[I.second][SA.Id] = FS->second.top()->Id; - // Insert DstR into the map. - RDefMap[I.first]; - } -} - - -void CopyPropagation::updateMap(NodeAddr<InstrNode*> IA) { - RegisterSet RRs; - for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)) - RRs.insert(RA.Addr->getRegRef(DFG)); - bool Common = false; - for (auto &R : RDefMap) { - if (!RRs.count(R.first)) - continue; - Common = true; - break; - } - if (!Common) - return; - - for (auto &R : RDefMap) { - if (!RRs.count(R.first)) - continue; - auto F = DefM.find(R.first.Reg); - if (F == DefM.end() || F->second.empty()) - continue; - R.second[IA.Id] = F->second.top()->Id; - } } bool CopyPropagation::scanBlock(MachineBasicBlock *B) { bool Changed = false; auto BA = DFG.getFunc().Addr->findBlock(B, DFG); - DFG.markBlock(BA.Id, DefM); for (NodeAddr<InstrNode*> IA : BA.Addr->members(DFG)) { if (DFG.IsCode<NodeAttrs::Stmt>(IA)) { @@ -102,20 +68,30 @@ bool CopyPropagation::scanBlock(MachineBasicBlock *B) { if (interpretAsCopy(SA.Addr->getCode(), EM)) recordCopy(SA, EM); } - - updateMap(IA); - DFG.pushDefs(IA, DefM); } MachineDomTreeNode *N = MDT.getNode(B); for (auto I : *N) Changed |= scanBlock(I->getBlock()); - DFG.releaseBlock(BA.Id, DefM); return Changed; } +NodeId CopyPropagation::getLocalReachingDef(RegisterRef RefRR, + NodeAddr<InstrNode*> IA) { + NodeAddr<RefNode*> RA = L.getNearestAliasedRef(RefRR, IA); + if (RA.Id != 0) { + if (RA.Addr->getKind() == NodeAttrs::Def) + return RA.Id; + assert(RA.Addr->getKind() == NodeAttrs::Use); + if (NodeId RD = RA.Addr->getReachingDef()) + return RD; + } + return 0; +} + + bool CopyPropagation::run() { scanBlock(&DFG.getMF().front()); @@ -129,14 +105,6 @@ bool CopyPropagation::run() { << Print<RegisterRef>(J.second, DFG); dbgs() << " }\n"; } - dbgs() << "\nRDef map:\n"; - for (auto R : RDefMap) { - dbgs() << Print<RegisterRef>(R.first, DFG) << " -> {"; - for (auto &M : R.second) - dbgs() << ' ' << Print<NodeId>(M.first, DFG) << ':' - << Print<NodeId>(M.second, DFG); - dbgs() << " }\n"; - } } bool Changed = false; @@ -176,8 +144,7 @@ bool CopyPropagation::run() { if (DR == SR) continue; - auto &RDefSR = RDefMap[SR]; - NodeId RDefSR_SA = RDefSR[SA.Id]; + NodeId AtCopy = getLocalReachingDef(SR, SA); for (NodeId N = DA.Addr->getReachedUse(), NextN; N; N = NextN) { auto UA = DFG.addr<UseNode*>(N); @@ -190,7 +157,8 @@ bool CopyPropagation::run() { NodeAddr<InstrNode*> IA = UA.Addr->getOwner(DFG); assert(DFG.IsCode<NodeAttrs::Stmt>(IA)); - if (RDefSR[IA.Id] != RDefSR_SA) + NodeId AtUse = getLocalReachingDef(SR, IA); + if (AtCopy != AtUse) continue; MachineOperand &Op = UA.Addr->getOp(); @@ -206,8 +174,8 @@ bool CopyPropagation::run() { Op.setReg(NewReg); Op.setSubReg(0); DFG.unlinkUse(UA, false); - if (RDefSR_SA != 0) { - UA.Addr->linkToDef(UA.Id, DFG.addr<DefNode*>(RDefSR_SA)); + if (AtCopy != 0) { + UA.Addr->linkToDef(UA.Id, DFG.addr<DefNode*>(AtCopy)); } else { UA.Addr->setReachingDef(0); UA.Addr->setSibling(0); diff --git a/contrib/llvm/lib/Target/Hexagon/RDFCopy.h b/contrib/llvm/lib/Target/Hexagon/RDFCopy.h index 5ece11bd5ce4..bbd625c5f5f6 100644 --- a/contrib/llvm/lib/Target/Hexagon/RDFCopy.h +++ b/contrib/llvm/lib/Target/Hexagon/RDFCopy.h @@ -11,6 +11,9 @@ #define LLVM_LIB_TARGET_HEXAGON_RDFCOPY_H #include "RDFGraph.h" +#include "RDFLiveness.h" +#include "llvm/CodeGen/MachineFunction.h" + #include <map> #include <vector> @@ -24,7 +27,7 @@ namespace rdf { struct CopyPropagation { CopyPropagation(DataFlowGraph &dfg) : MDT(dfg.getDT()), DFG(dfg), - Trace(false) {} + L(dfg.getMF().getRegInfo(), dfg), Trace(false) {} virtual ~CopyPropagation() = default; @@ -39,18 +42,16 @@ namespace rdf { private: const MachineDominatorTree &MDT; DataFlowGraph &DFG; - DataFlowGraph::DefStackMap DefM; + Liveness L; bool Trace; - // map: register -> (map: stmt -> reaching def) - std::map<RegisterRef,std::map<NodeId,NodeId>> RDefMap; // map: statement -> (map: dst reg -> src reg) std::map<NodeId, EqualityMap> CopyMap; std::vector<NodeId> Copies; void recordCopy(NodeAddr<StmtNode*> SA, EqualityMap &EM); - void updateMap(NodeAddr<InstrNode*> IA); bool scanBlock(MachineBasicBlock *B); + NodeId getLocalReachingDef(RegisterRef RefRR, NodeAddr<InstrNode*> IA); }; } // end namespace rdf diff --git a/contrib/llvm/lib/Target/Hexagon/RDFDeadCode.cpp b/contrib/llvm/lib/Target/Hexagon/RDFDeadCode.cpp index 63177d51cada..9aa8ad68e07e 100644 --- a/contrib/llvm/lib/Target/Hexagon/RDFDeadCode.cpp +++ b/contrib/llvm/lib/Target/Hexagon/RDFDeadCode.cpp @@ -62,9 +62,19 @@ bool DeadCodeElimination::isLiveInstr(const MachineInstr *MI) const { return true; if (MI->isPHI()) return false; - for (auto &Op : MI->operands()) + for (auto &Op : MI->operands()) { if (Op.isReg() && MRI.isReserved(Op.getReg())) return true; + if (Op.isRegMask()) { + const uint32_t *BM = Op.getRegMask(); + for (unsigned R = 0, RN = DFG.getTRI().getNumRegs(); R != RN; ++R) { + if (BM[R/32] & (1u << (R%32))) + continue; + if (MRI.isReserved(R)) + return true; + } + } + } return false; } diff --git a/contrib/llvm/lib/Target/Hexagon/RDFGraph.cpp b/contrib/llvm/lib/Target/Hexagon/RDFGraph.cpp index fa272ea1a76a..7a2895aa4e8c 100644 --- a/contrib/llvm/lib/Target/Hexagon/RDFGraph.cpp +++ b/contrib/llvm/lib/Target/Hexagon/RDFGraph.cpp @@ -276,7 +276,7 @@ raw_ostream &operator<< (raw_ostream &OS, MachineBasicBlock *BB = P.Obj.Addr->getCode(); unsigned NP = BB->pred_size(); std::vector<int> Ns; - auto PrintBBs = [&OS,&P] (std::vector<int> Ns) -> void { + auto PrintBBs = [&OS] (std::vector<int> Ns) -> void { unsigned N = Ns.size(); for (int I : Ns) { OS << "BB#" << I; @@ -424,7 +424,7 @@ RegisterRef RefNode::getRegRef(const DataFlowGraph &G) const { if (NodeAttrs::flags(Attrs) & NodeAttrs::PhiRef) return G.unpack(Ref.PR); assert(Ref.Op != nullptr); - return G.makeRegRef(Ref.Op->getReg(), Ref.Op->getSubReg()); + return G.makeRegRef(*Ref.Op); } // Set the register reference in the reference node directly (for references @@ -617,8 +617,12 @@ bool TargetOperandInfo::isPreserving(const MachineInstr &In, unsigned OpNum) // Check if the definition of RR produces an unspecified value. bool TargetOperandInfo::isClobbering(const MachineInstr &In, unsigned OpNum) const { + const MachineOperand &Op = In.getOperand(OpNum); + if (Op.isRegMask()) + return true; + assert(Op.isReg()); if (In.isCall()) - if (In.getOperand(OpNum).isImplicit()) + if (Op.isDef() && Op.isDead()) return true; return false; } @@ -654,109 +658,6 @@ bool TargetOperandInfo::isFixedReg(const MachineInstr &In, unsigned OpNum) return false; } -RegisterRef RegisterAggr::normalize(RegisterRef RR) const { - RegisterId SuperReg = RR.Reg; - while (true) { - MCSuperRegIterator SR(SuperReg, &TRI, false); - if (!SR.isValid()) - break; - SuperReg = *SR; - } - - const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(RR.Reg); - LaneBitmask Common = RR.Mask & RC.LaneMask; - uint32_t Sub = TRI.getSubRegIndex(SuperReg, RR.Reg); - LaneBitmask SuperMask = TRI.composeSubRegIndexLaneMask(Sub, Common); - return RegisterRef(SuperReg, SuperMask); -} - -bool RegisterAggr::hasAliasOf(RegisterRef RR) const { - RegisterRef NR = normalize(RR); - auto F = Masks.find(NR.Reg); - if (F != Masks.end()) { - if ((F->second & NR.Mask).any()) - return true; - } - if (CheckUnits) { - for (MCRegUnitIterator U(RR.Reg, &TRI); U.isValid(); ++U) - if (ExpAliasUnits.test(*U)) - return true; - } - return false; -} - -bool RegisterAggr::hasCoverOf(RegisterRef RR) const { - // Always have a cover for empty lane mask. - RegisterRef NR = normalize(RR); - if (NR.Mask.none()) - return true; - auto F = Masks.find(NR.Reg); - if (F == Masks.end()) - return false; - return (NR.Mask & F->second) == NR.Mask; -} - -RegisterAggr &RegisterAggr::insert(RegisterRef RR) { - RegisterRef NR = normalize(RR); - auto F = Masks.find(NR.Reg); - if (F == Masks.end()) - Masks.insert({NR.Reg, NR.Mask}); - else - F->second |= NR.Mask; - - // Visit all register units to see if there are any that were created - // by explicit aliases. Add those that were to the bit vector. - for (MCRegUnitIterator U(RR.Reg, &TRI); U.isValid(); ++U) { - MCRegUnitRootIterator R(*U, &TRI); - ++R; - if (!R.isValid()) - continue; - ExpAliasUnits.set(*U); - CheckUnits = true; - } - return *this; -} - -RegisterAggr &RegisterAggr::insert(const RegisterAggr &RG) { - for (std::pair<RegisterId,LaneBitmask> P : RG.Masks) - insert(RegisterRef(P.first, P.second)); - return *this; -} - -RegisterAggr &RegisterAggr::clear(RegisterRef RR) { - RegisterRef NR = normalize(RR); - auto F = Masks.find(NR.Reg); - if (F == Masks.end()) - return *this; - LaneBitmask NewM = F->second & ~NR.Mask; - if (NewM.none()) - Masks.erase(F); - else - F->second = NewM; - return *this; -} - -RegisterAggr &RegisterAggr::clear(const RegisterAggr &RG) { - for (std::pair<RegisterId,LaneBitmask> P : RG.Masks) - clear(RegisterRef(P.first, P.second)); - return *this; -} - -RegisterRef RegisterAggr::clearIn(RegisterRef RR) const { - RegisterAggr T(TRI); - T.insert(RR).clear(*this); - if (T.empty()) - return RegisterRef(); - return RegisterRef(T.begin()->first, T.begin()->second); -} - -void RegisterAggr::print(raw_ostream &OS) const { - OS << '{'; - for (auto I : Masks) - OS << ' ' << PrintReg(I.first, &TRI) << PrintLaneMaskOpt(I.second); - OS << " }"; -} - // // The data flow graph construction. // @@ -764,7 +665,8 @@ void RegisterAggr::print(raw_ostream &OS) const { DataFlowGraph::DataFlowGraph(MachineFunction &mf, const TargetInstrInfo &tii, const TargetRegisterInfo &tri, const MachineDominatorTree &mdt, const MachineDominanceFrontier &mdf, const TargetOperandInfo &toi) - : MF(mf), TII(tii), TRI(tri), MDT(mdt), MDF(mdf), TOI(toi) { + : MF(mf), TII(tii), TRI(tri), PRI(tri, mf), MDT(mdt), MDF(mdf), TOI(toi), + LiveIns(PRI) { } // The implementation of the definition stack. @@ -857,17 +759,6 @@ unsigned DataFlowGraph::DefStack::nextDown(unsigned P) const { // Register information. -// Get the list of references aliased to RR. Lane masks are ignored. -RegisterSet DataFlowGraph::getAliasSet(RegisterId Reg) const { - // Do not include RR in the alias set. - RegisterSet AS; - assert(TargetRegisterInfo::isPhysicalRegister(Reg)); - - for (MCRegAliasIterator AI(Reg, &TRI, false); AI.isValid(); ++AI) - AS.insert(RegisterRef(*AI)); - return AS; -} - RegisterSet DataFlowGraph::getLandingPadLiveIns() const { RegisterSet LR; const Function &F = *MF.getFunction(); @@ -1010,11 +901,22 @@ void DataFlowGraph::build(unsigned Options) { BlockRefsMap RefM; buildBlockRefs(EA, RefM); - // Add function-entry phi nodes. + // Collect function live-ins and entry block live-ins. MachineRegisterInfo &MRI = MF.getRegInfo(); - for (auto I = MRI.livein_begin(), E = MRI.livein_end(); I != E; ++I) { + MachineBasicBlock &EntryB = *EA.Addr->getCode(); + assert(EntryB.pred_empty() && "Function entry block has predecessors"); + for (auto I = MRI.livein_begin(), E = MRI.livein_end(); I != E; ++I) + LiveIns.insert(RegisterRef(I->first)); + if (MRI.tracksLiveness()) { + for (auto I : EntryB.liveins()) + LiveIns.insert(RegisterRef(I.PhysReg, I.LaneMask)); + } + + // Add function-entry phi nodes for the live-in registers. + //for (std::pair<RegisterId,LaneBitmask> P : LiveIns) { + for (auto I = LiveIns.rr_begin(), E = LiveIns.rr_end(); I != E; ++I) { + RegisterRef RR = *I; NodeAddr<PhiNode*> PA = newPhi(EA); - RegisterRef RR = RegisterRef(I->first); uint16_t PhiFlags = NodeAttrs::PhiRef | NodeAttrs::Preserving; NodeAddr<DefNode*> DA = newDef(PA, RR, PhiFlags); PA.Addr->addMember(DA, *this); @@ -1071,27 +973,19 @@ void DataFlowGraph::build(unsigned Options) { } RegisterRef DataFlowGraph::makeRegRef(unsigned Reg, unsigned Sub) const { - assert(TargetRegisterInfo::isPhysicalRegister(Reg)); + assert(PhysicalRegisterInfo::isRegMaskId(Reg) || + TargetRegisterInfo::isPhysicalRegister(Reg)); + assert(Reg != 0); if (Sub != 0) Reg = TRI.getSubReg(Reg, Sub); return RegisterRef(Reg); } -RegisterRef DataFlowGraph::normalizeRef(RegisterRef RR) const { - // FIXME copied from RegisterAggr - RegisterId SuperReg = RR.Reg; - while (true) { - MCSuperRegIterator SR(SuperReg, &TRI, false); - if (!SR.isValid()) - break; - SuperReg = *SR; - } - - uint32_t Sub = TRI.getSubRegIndex(SuperReg, RR.Reg); - const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(RR.Reg); - LaneBitmask SuperMask = RR.Mask & - TRI.composeSubRegIndexLaneMask(Sub, RC.LaneMask); - return RegisterRef(SuperReg, SuperMask); +RegisterRef DataFlowGraph::makeRegRef(const MachineOperand &Op) const { + assert(Op.isReg() || Op.isRegMask()); + if (Op.isReg()) + return makeRegRef(Op.getReg(), Op.getSubReg()); + return RegisterRef(PRI.getRegMaskId(Op.getRegMask()), LaneBitmask::getAll()); } RegisterRef DataFlowGraph::restrictRef(RegisterRef AR, RegisterRef BR) const { @@ -1100,13 +994,13 @@ RegisterRef DataFlowGraph::restrictRef(RegisterRef AR, RegisterRef BR) const { return M.any() ? RegisterRef(AR.Reg, M) : RegisterRef(); } #ifndef NDEBUG - RegisterRef NAR = normalizeRef(AR); - RegisterRef NBR = normalizeRef(BR); - assert(NAR.Reg != NBR.Reg); +// RegisterRef NAR = PRI.normalize(AR); +// RegisterRef NBR = PRI.normalize(BR); +// assert(NAR.Reg != NBR.Reg); #endif // This isn't strictly correct, because the overlap may happen in the // part masked out. - if (TRI.regsOverlap(AR.Reg, BR.Reg)) + if (PRI.alias(AR, BR)) return AR; return RegisterRef(); } @@ -1137,11 +1031,61 @@ void DataFlowGraph::releaseBlock(NodeId B, DefStackMap &DefM) { // Push all definitions from the instruction node IA to an appropriate // stack in DefM. +void DataFlowGraph::pushAllDefs(NodeAddr<InstrNode*> IA, DefStackMap &DefM) { + pushClobbers(IA, DefM); + pushDefs(IA, DefM); +} + +// Push all definitions from the instruction node IA to an appropriate +// stack in DefM. +void DataFlowGraph::pushClobbers(NodeAddr<InstrNode*> IA, DefStackMap &DefM) { + NodeSet Visited; + std::set<RegisterId> Defined; + + // The important objectives of this function are: + // - to be able to handle instructions both while the graph is being + // constructed, and after the graph has been constructed, and + // - maintain proper ordering of definitions on the stack for each + // register reference: + // - if there are two or more related defs in IA (i.e. coming from + // the same machine operand), then only push one def on the stack, + // - if there are multiple unrelated defs of non-overlapping + // subregisters of S, then the stack for S will have both (in an + // unspecified order), but the order does not matter from the data- + // -flow perspective. + + for (NodeAddr<DefNode*> DA : IA.Addr->members_if(IsDef, *this)) { + if (Visited.count(DA.Id)) + continue; + if (!(DA.Addr->getFlags() & NodeAttrs::Clobbering)) + continue; + + NodeList Rel = getRelatedRefs(IA, DA); + NodeAddr<DefNode*> PDA = Rel.front(); + RegisterRef RR = PDA.Addr->getRegRef(*this); + + // Push the definition on the stack for the register and all aliases. + // The def stack traversal in linkNodeUp will check the exact aliasing. + DefM[RR.Reg].push(DA); + Defined.insert(RR.Reg); + for (RegisterId A : PRI.getAliasSet(RR.Reg)) { + // Check that we don't push the same def twice. + assert(A != RR.Reg); + if (!Defined.count(A)) + DefM[A].push(DA); + } + // Mark all the related defs as visited. + for (NodeAddr<NodeBase*> T : Rel) + Visited.insert(T.Id); + } +} + +// Push all definitions from the instruction node IA to an appropriate +// stack in DefM. void DataFlowGraph::pushDefs(NodeAddr<InstrNode*> IA, DefStackMap &DefM) { - NodeList Defs = IA.Addr->members_if(IsDef, *this); NodeSet Visited; #ifndef NDEBUG - RegisterSet Defined; + std::set<RegisterId> Defined; #endif // The important objectives of this function are: @@ -1156,9 +1100,11 @@ void DataFlowGraph::pushDefs(NodeAddr<InstrNode*> IA, DefStackMap &DefM) { // unspecified order), but the order does not matter from the data- // -flow perspective. - for (NodeAddr<DefNode*> DA : Defs) { + for (NodeAddr<DefNode*> DA : IA.Addr->members_if(IsDef, *this)) { if (Visited.count(DA.Id)) continue; + if (DA.Addr->getFlags() & NodeAttrs::Clobbering) + continue; NodeList Rel = getRelatedRefs(IA, DA); NodeAddr<DefNode*> PDA = Rel.front(); @@ -1166,7 +1112,7 @@ void DataFlowGraph::pushDefs(NodeAddr<InstrNode*> IA, DefStackMap &DefM) { #ifndef NDEBUG // Assert if the register is defined in two or more unrelated defs. // This could happen if there are two or more def operands defining it. - if (!Defined.insert(RR).second) { + if (!Defined.insert(RR.Reg).second) { MachineInstr *MI = NodeAddr<StmtNode*>(IA).Addr->getCode(); dbgs() << "Multiple definitions of register: " << Print<RegisterRef>(RR, *this) << " in\n " << *MI @@ -1177,10 +1123,10 @@ void DataFlowGraph::pushDefs(NodeAddr<InstrNode*> IA, DefStackMap &DefM) { // Push the definition on the stack for the register and all aliases. // The def stack traversal in linkNodeUp will check the exact aliasing. DefM[RR.Reg].push(DA); - for (RegisterRef A : getAliasSet(RR.Reg /*FIXME? use RegisterRef*/)) { + for (RegisterId A : PRI.getAliasSet(RR.Reg)) { // Check that we don't push the same def twice. - assert(A != RR); - DefM[A.Reg].push(DA); + assert(A != RR.Reg); + DefM[A].push(DA); } // Mark all the related defs as visited. for (NodeAddr<NodeBase*> T : Rel) @@ -1203,59 +1149,6 @@ NodeList DataFlowGraph::getRelatedRefs(NodeAddr<InstrNode*> IA, return Refs; } -// Return true if RA and RB overlap, false otherwise. -bool DataFlowGraph::alias(RegisterRef RA, RegisterRef RB) const { - assert(TargetRegisterInfo::isPhysicalRegister(RA.Reg)); - assert(TargetRegisterInfo::isPhysicalRegister(RB.Reg)); - - MCRegUnitMaskIterator UMA(RA.Reg, &TRI); - MCRegUnitMaskIterator UMB(RB.Reg, &TRI); - // Reg units are returned in the numerical order. - while (UMA.isValid() && UMB.isValid()) { - std::pair<uint32_t,LaneBitmask> PA = *UMA; - std::pair<uint32_t,LaneBitmask> PB = *UMB; - if (PA.first == PB.first) { - // Lane mask of 0 (given by the iterator) should be treated as "full". - // This can happen when the register has only one unit, or when the - // unit corresponds to explicit aliasing. In such cases, the lane mask - // from RegisterRef should be ignored. - if (PA.second.none() || PB.second.none()) - return true; - - // At this point the common unit corresponds to a subregister. The lane - // masks correspond to the lane mask of that unit within the original - // register, for example assuming register quadruple q0 = r3:0, and - // a register pair d1 = r3:2, the lane mask of r2 in q0 may be 0b0100, - // while the lane mask of r2 in d1 may be 0b0001. - LaneBitmask LA = PA.second & RA.Mask; - LaneBitmask LB = PB.second & RB.Mask; - if (LA.any() && LB.any()) { - unsigned Root = *MCRegUnitRootIterator(PA.first, &TRI); - // If register units were guaranteed to only have 1 bit in any lane - // mask, the code below would not be necessary. This is because LA - // and LB would have at most 1 bit set each, and that bit would be - // guaranteed to correspond to the given register unit. - uint32_t SubA = TRI.getSubRegIndex(RA.Reg, Root); - uint32_t SubB = TRI.getSubRegIndex(RB.Reg, Root); - const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(Root); - LaneBitmask MaskA = TRI.reverseComposeSubRegIndexLaneMask(SubA, LA); - LaneBitmask MaskB = TRI.reverseComposeSubRegIndexLaneMask(SubB, LB); - if ((MaskA & MaskB & RC.LaneMask).any()) - return true; - } - - ++UMA; - ++UMB; - continue; - } - if (PA.first < PB.first) - ++UMA; - else if (PB.first < PA.first) - ++UMB; - } - return false; -} - // Clear all information in the graph. void DataFlowGraph::reset() { Memory.clear(); @@ -1370,58 +1263,53 @@ void DataFlowGraph::buildStmt(NodeAddr<BlockNode*> BA, MachineInstr &In) { if (In.isCall()) return true; // Is tail call? - if (In.isBranch()) + if (In.isBranch()) { for (const MachineOperand &Op : In.operands()) if (Op.isGlobal() || Op.isSymbol()) return true; + // Assume indirect branches are calls. This is for the purpose of + // keeping implicit operands, and so it won't hurt on intra-function + // indirect branches. + if (In.isIndirectBranch()) + return true; + } return false; }; auto isDefUndef = [this] (const MachineInstr &In, RegisterRef DR) -> bool { // This instruction defines DR. Check if there is a use operand that // would make DR live on entry to the instruction. - for (const MachineOperand &UseOp : In.operands()) { - if (!UseOp.isReg() || !UseOp.isUse() || UseOp.isUndef()) + for (const MachineOperand &Op : In.operands()) { + if (!Op.isReg() || Op.getReg() == 0 || !Op.isUse() || Op.isUndef()) continue; - RegisterRef UR = makeRegRef(UseOp.getReg(), UseOp.getSubReg()); - if (alias(DR, UR)) + RegisterRef UR = makeRegRef(Op); + if (PRI.alias(DR, UR)) return false; } return true; }; - // Collect a set of registers that this instruction implicitly uses - // or defines. Implicit operands from an instruction will be ignored - // unless they are listed here. - RegisterSet ImpUses, ImpDefs; - if (const uint16_t *ImpD = In.getDesc().getImplicitDefs()) - while (uint16_t R = *ImpD++) - ImpDefs.insert(RegisterRef(R)); - if (const uint16_t *ImpU = In.getDesc().getImplicitUses()) - while (uint16_t R = *ImpU++) - ImpUses.insert(RegisterRef(R)); - bool IsCall = isCall(In); - bool NeedsImplicit = IsCall || In.isInlineAsm() || In.isReturn(); - bool IsPredicated = TII.isPredicated(In); unsigned NumOps = In.getNumOperands(); // Avoid duplicate implicit defs. This will not detect cases of implicit // defs that define registers that overlap, but it is not clear how to // interpret that in the absence of explicit defs. Overlapping explicit // defs are likely illegal already. - RegisterSet DoneDefs; + BitVector DoneDefs(TRI.getNumRegs()); // Process explicit defs first. for (unsigned OpN = 0; OpN < NumOps; ++OpN) { MachineOperand &Op = In.getOperand(OpN); if (!Op.isReg() || !Op.isDef() || Op.isImplicit()) continue; - RegisterRef RR = makeRegRef(Op.getReg(), Op.getSubReg()); + unsigned R = Op.getReg(); + if (!R || !TargetRegisterInfo::isPhysicalRegister(R)) + continue; uint16_t Flags = NodeAttrs::None; if (TOI.isPreserving(In, OpN)) { Flags |= NodeAttrs::Preserving; // If the def is preserving, check if it is also undefined. - if (isDefUndef(In, RR)) + if (isDefUndef(In, makeRegRef(Op))) Flags |= NodeAttrs::Undef; } if (TOI.isClobbering(In, OpN)) @@ -1432,7 +1320,25 @@ void DataFlowGraph::buildStmt(NodeAddr<BlockNode*> BA, MachineInstr &In) { Flags |= NodeAttrs::Dead; NodeAddr<DefNode*> DA = newDef(SA, Op, Flags); SA.Addr->addMember(DA, *this); - DoneDefs.insert(RR); + assert(!DoneDefs.test(R)); + DoneDefs.set(R); + } + + // Process reg-masks (as clobbers). + BitVector DoneClobbers(TRI.getNumRegs()); + for (unsigned OpN = 0; OpN < NumOps; ++OpN) { + MachineOperand &Op = In.getOperand(OpN); + if (!Op.isRegMask()) + continue; + uint16_t Flags = NodeAttrs::Clobbering | NodeAttrs::Fixed | + NodeAttrs::Dead; + NodeAddr<DefNode*> DA = newDef(SA, Op, Flags); + SA.Addr->addMember(DA, *this); + // Record all clobbered registers in DoneDefs. + const uint32_t *RM = Op.getRegMask(); + for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) + if (!(RM[i/32] & (1u << (i%32)))) + DoneClobbers.set(i); } // Process implicit defs, skipping those that have already been added @@ -1441,11 +1347,10 @@ void DataFlowGraph::buildStmt(NodeAddr<BlockNode*> BA, MachineInstr &In) { MachineOperand &Op = In.getOperand(OpN); if (!Op.isReg() || !Op.isDef() || !Op.isImplicit()) continue; - RegisterRef RR = makeRegRef(Op.getReg(), Op.getSubReg()); - if (!NeedsImplicit && !ImpDefs.count(RR)) - continue; - if (DoneDefs.count(RR)) + unsigned R = Op.getReg(); + if (!R || !TargetRegisterInfo::isPhysicalRegister(R) || DoneDefs.test(R)) continue; + RegisterRef RR = makeRegRef(Op); uint16_t Flags = NodeAttrs::None; if (TOI.isPreserving(In, OpN)) { Flags |= NodeAttrs::Preserving; @@ -1457,24 +1362,22 @@ void DataFlowGraph::buildStmt(NodeAddr<BlockNode*> BA, MachineInstr &In) { Flags |= NodeAttrs::Clobbering; if (TOI.isFixedReg(In, OpN)) Flags |= NodeAttrs::Fixed; - if (IsCall && Op.isDead()) + if (IsCall && Op.isDead()) { + if (DoneClobbers.test(R)) + continue; Flags |= NodeAttrs::Dead; + } NodeAddr<DefNode*> DA = newDef(SA, Op, Flags); SA.Addr->addMember(DA, *this); - DoneDefs.insert(RR); + DoneDefs.set(R); } for (unsigned OpN = 0; OpN < NumOps; ++OpN) { MachineOperand &Op = In.getOperand(OpN); if (!Op.isReg() || !Op.isUse()) continue; - RegisterRef RR = makeRegRef(Op.getReg(), Op.getSubReg()); - // Add implicit uses on return and call instructions, and on predicated - // instructions regardless of whether or not they appear in the instruction - // descriptor's list. - bool Implicit = Op.isImplicit(); - bool TakeImplicit = NeedsImplicit || IsPredicated; - if (Implicit && !TakeImplicit && !ImpUses.count(RR)) + unsigned R = Op.getReg(); + if (!R || !TargetRegisterInfo::isPhysicalRegister(R)) continue; uint16_t Flags = NodeAttrs::None; if (Op.isUndef()) @@ -1570,7 +1473,7 @@ void DataFlowGraph::buildPhis(BlockRefsMap &PhiM, BlockRefsMap &RefM, auto MaxCoverIn = [this] (RegisterRef RR, RegisterSet &RRs) -> RegisterRef { for (RegisterRef I : RRs) - if (I != RR && RegisterAggr::isCoverOf(I, RR, TRI)) + if (I != RR && RegisterAggr::isCoverOf(I, RR, PRI)) RR = I; return RR; }; @@ -1597,7 +1500,7 @@ void DataFlowGraph::buildPhis(BlockRefsMap &PhiM, BlockRefsMap &RefM, auto Aliased = [this,&MaxRefs](RegisterRef RR, std::vector<unsigned> &Closure) -> bool { for (unsigned I : Closure) - if (alias(RR, MaxRefs[I])) + if (PRI.alias(RR, MaxRefs[I])) return true; return false; }; @@ -1708,7 +1611,7 @@ void DataFlowGraph::linkRefUp(NodeAddr<InstrNode*> IA, NodeAddr<T> TA, NodeAddr<T> TAP; // References from the def stack that have been examined so far. - RegisterAggr Defs(TRI); + RegisterAggr Defs(PRI); for (auto I = DS.top(), E = DS.bottom(); I != E; I.down()) { RegisterRef QR = I->Addr->getRegRef(*this); @@ -1744,13 +1647,15 @@ void DataFlowGraph::linkRefUp(NodeAddr<InstrNode*> IA, NodeAddr<T> TA, } // Create data-flow links for all reference nodes in the statement node SA. -void DataFlowGraph::linkStmtRefs(DefStackMap &DefM, NodeAddr<StmtNode*> SA) { +template <typename Predicate> +void DataFlowGraph::linkStmtRefs(DefStackMap &DefM, NodeAddr<StmtNode*> SA, + Predicate P) { #ifndef NDEBUG RegisterSet Defs; #endif // Link all nodes (upwards in the data-flow) with their reaching defs. - for (NodeAddr<RefNode*> RA : SA.Addr->members(*this)) { + for (NodeAddr<RefNode*> RA : SA.Addr->members_if(P, *this)) { uint16_t Kind = RA.Addr->getKind(); assert(Kind == NodeAttrs::Def || Kind == NodeAttrs::Use); RegisterRef RR = RA.Addr->getRegRef(*this); @@ -1779,6 +1684,13 @@ void DataFlowGraph::linkBlockRefs(DefStackMap &DefM, NodeAddr<BlockNode*> BA) { // Push block delimiters. markBlock(BA.Id, DefM); + auto IsClobber = [] (NodeAddr<RefNode*> RA) -> bool { + return IsDef(RA) && (RA.Addr->getFlags() & NodeAttrs::Clobbering); + }; + auto IsNoClobber = [] (NodeAddr<RefNode*> RA) -> bool { + return IsDef(RA) && !(RA.Addr->getFlags() & NodeAttrs::Clobbering); + }; + assert(BA.Addr && "block node address is needed to create a data-flow link"); // For each non-phi instruction in the block, link all the defs and uses // to their reaching defs. For any member of the block (including phis), @@ -1786,10 +1698,17 @@ void DataFlowGraph::linkBlockRefs(DefStackMap &DefM, NodeAddr<BlockNode*> BA) { for (NodeAddr<InstrNode*> IA : BA.Addr->members(*this)) { // Ignore phi nodes here. They will be linked part by part from the // predecessors. - if (IA.Addr->getKind() == NodeAttrs::Stmt) - linkStmtRefs(DefM, IA); + if (IA.Addr->getKind() == NodeAttrs::Stmt) { + linkStmtRefs(DefM, IA, IsUse); + linkStmtRefs(DefM, IA, IsClobber); + } // Push the definitions on the stack. + pushClobbers(IA, DefM); + + if (IA.Addr->getKind() == NodeAttrs::Stmt) + linkStmtRefs(DefM, IA, IsNoClobber); + pushDefs(IA, DefM); } diff --git a/contrib/llvm/lib/Target/Hexagon/RDFGraph.h b/contrib/llvm/lib/Target/Hexagon/RDFGraph.h index 49d78a8b22b5..d5faca4cd6f4 100644 --- a/contrib/llvm/lib/Target/Hexagon/RDFGraph.h +++ b/contrib/llvm/lib/Target/Hexagon/RDFGraph.h @@ -225,6 +225,7 @@ #ifndef LLVM_LIB_TARGET_HEXAGON_RDFGRAPH_H #define LLVM_LIB_TARGET_HEXAGON_RDFGRAPH_H +#include "RDFRegisters.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include "llvm/MC/LaneBitmask.h" @@ -260,7 +261,6 @@ namespace llvm { namespace rdf { typedef uint32_t NodeId; - typedef uint32_t RegisterId; struct DataFlowGraph; @@ -412,25 +412,6 @@ namespace rdf { AllocatorTy MemPool; }; - struct RegisterRef { - RegisterId Reg; - LaneBitmask Mask; - - RegisterRef() : RegisterRef(0) {} - explicit RegisterRef(RegisterId R, LaneBitmask M = LaneBitmask::getAll()) - : Reg(R), Mask(R != 0 ? M : LaneBitmask::getNone()) {} - - operator bool() const { return Reg != 0 && Mask.any(); } - bool operator== (const RegisterRef &RR) const { - return Reg == RR.Reg && Mask == RR.Mask; - } - bool operator!= (const RegisterRef &RR) const { - return !operator==(RR); - } - bool operator< (const RegisterRef &RR) const { - return Reg < RR.Reg || (Reg == RR.Reg && Mask < RR.Mask); - } - }; typedef std::set<RegisterRef> RegisterSet; struct TargetOperandInfo { @@ -450,39 +431,6 @@ namespace rdf { uint32_t MaskId; }; - // Template class for a map translating uint32_t into arbitrary types. - // The map will act like an indexed set: upon insertion of a new object, - // it will automatically assign a new index to it. Index of 0 is treated - // as invalid and is never allocated. - template <typename T, unsigned N = 32> - struct IndexedSet { - IndexedSet() : Map() { Map.reserve(N); } - - T get(uint32_t Idx) const { - // Index Idx corresponds to Map[Idx-1]. - assert(Idx != 0 && !Map.empty() && Idx-1 < Map.size()); - return Map[Idx-1]; - } - - uint32_t insert(T Val) { - // Linear search. - auto F = llvm::find(Map, Val); - if (F != Map.end()) - return F - Map.begin() + 1; - Map.push_back(Val); - return Map.size(); // Return actual_index + 1. - } - - uint32_t find(T Val) const { - auto F = llvm::find(Map, Val); - assert(F != Map.end()); - return F - Map.begin(); - } - - private: - std::vector<T> Map; - }; - struct LaneMaskIndex : private IndexedSet<LaneBitmask> { LaneMaskIndex() = default; @@ -497,55 +445,6 @@ namespace rdf { assert(LM.any()); return LM.all() ? 0 : find(LM); } - - PackedRegisterRef pack(RegisterRef RR) { - return { RR.Reg, getIndexForLaneMask(RR.Mask) }; - } - PackedRegisterRef pack(RegisterRef RR) const { - return { RR.Reg, getIndexForLaneMask(RR.Mask) }; - } - - RegisterRef unpack(PackedRegisterRef PR) const { - return RegisterRef(PR.Reg, getLaneMaskForIndex(PR.MaskId)); - } - }; - - struct RegisterAggr { - RegisterAggr(const TargetRegisterInfo &tri) - : ExpAliasUnits(tri.getNumRegUnits()), CheckUnits(false), TRI(tri) {} - RegisterAggr(const RegisterAggr &RG) = default; - - bool empty() const { return Masks.empty(); } - bool hasAliasOf(RegisterRef RR) const; - bool hasCoverOf(RegisterRef RR) const; - static bool isCoverOf(RegisterRef RA, RegisterRef RB, - const TargetRegisterInfo &TRI) { - return RegisterAggr(TRI).insert(RA).hasCoverOf(RB); - } - - RegisterAggr &insert(RegisterRef RR); - RegisterAggr &insert(const RegisterAggr &RG); - RegisterAggr &clear(RegisterRef RR); - RegisterAggr &clear(const RegisterAggr &RG); - - RegisterRef clearIn(RegisterRef RR) const; - - void print(raw_ostream &OS) const; - - private: - typedef std::unordered_map<RegisterId, LaneBitmask> MapType; - - public: - typedef MapType::const_iterator iterator; - iterator begin() const { return Masks.begin(); } - iterator end() const { return Masks.end(); } - RegisterRef normalize(RegisterRef RR) const; - - private: - MapType Masks; - BitVector ExpAliasUnits; // Register units for explicit aliases. - bool CheckUnits; - const TargetRegisterInfo &TRI; }; struct NodeBase { @@ -761,8 +660,10 @@ namespace rdf { MachineFunction &getMF() const { return MF; } const TargetInstrInfo &getTII() const { return TII; } const TargetRegisterInfo &getTRI() const { return TRI; } + const PhysicalRegisterInfo &getPRI() const { return PRI; } const MachineDominatorTree &getDT() const { return MDT; } const MachineDominanceFrontier &getDF() const { return MDF; } + const RegisterAggr &getLiveIns() const { return LiveIns; } struct DefStack { DefStack() = default; @@ -828,15 +729,22 @@ namespace rdf { typedef std::unordered_map<RegisterId,DefStack> DefStackMap; void build(unsigned Options = BuildOptions::None); - void pushDefs(NodeAddr<InstrNode*> IA, DefStackMap &DM); + void pushAllDefs(NodeAddr<InstrNode*> IA, DefStackMap &DM); void markBlock(NodeId B, DefStackMap &DefM); void releaseBlock(NodeId B, DefStackMap &DefM); - PackedRegisterRef pack(RegisterRef RR) { return LMI.pack(RR); } - PackedRegisterRef pack(RegisterRef RR) const { return LMI.pack(RR); } - RegisterRef unpack(PackedRegisterRef PR) const { return LMI.unpack(PR); } + PackedRegisterRef pack(RegisterRef RR) { + return { RR.Reg, LMI.getIndexForLaneMask(RR.Mask) }; + } + PackedRegisterRef pack(RegisterRef RR) const { + return { RR.Reg, LMI.getIndexForLaneMask(RR.Mask) }; + } + RegisterRef unpack(PackedRegisterRef PR) const { + return RegisterRef(PR.Reg, LMI.getLaneMaskForIndex(PR.MaskId)); + } + RegisterRef makeRegRef(unsigned Reg, unsigned Sub) const; - RegisterRef normalizeRef(RegisterRef RR) const; + RegisterRef makeRegRef(const MachineOperand &Op) const; RegisterRef restrictRef(RegisterRef AR, RegisterRef BR) const; NodeAddr<RefNode*> getNextRelated(NodeAddr<InstrNode*> IA, @@ -853,6 +761,10 @@ namespace rdf { NodeList getRelatedRefs(NodeAddr<InstrNode*> IA, NodeAddr<RefNode*> RA) const; + NodeAddr<BlockNode*> findBlock(MachineBasicBlock *BB) const { + return BlockNodes.at(BB); + } + void unlinkUse(NodeAddr<UseNode*> UA, bool RemoveFromOwner) { unlinkUseDF(UA); if (RemoveFromOwner) @@ -898,13 +810,9 @@ namespace rdf { return (Flags & NodeAttrs::Preserving) && !(Flags & NodeAttrs::Undef); } - // Register aliasing. - bool alias(RegisterRef RA, RegisterRef RB) const; - private: void reset(); - RegisterSet getAliasSet(RegisterId Reg) const; RegisterSet getLandingPadLiveIns() const; NodeAddr<NodeBase*> newNode(uint16_t Attrs); @@ -940,9 +848,12 @@ namespace rdf { NodeAddr<BlockNode*> BA); void removeUnusedPhis(); + void pushClobbers(NodeAddr<InstrNode*> IA, DefStackMap &DM); + void pushDefs(NodeAddr<InstrNode*> IA, DefStackMap &DM); template <typename T> void linkRefUp(NodeAddr<InstrNode*> IA, NodeAddr<T> TA, DefStack &DS); - void linkStmtRefs(DefStackMap &DefM, NodeAddr<StmtNode*> SA); + template <typename Predicate> void linkStmtRefs(DefStackMap &DefM, + NodeAddr<StmtNode*> SA, Predicate P); void linkBlockRefs(DefStackMap &DefM, NodeAddr<BlockNode*> BA); void unlinkUseDF(NodeAddr<UseNode*> UA); @@ -953,23 +864,21 @@ namespace rdf { IA.Addr->removeMember(RA, *this); } - NodeAddr<BlockNode*> findBlock(MachineBasicBlock *BB) { - return BlockNodes[BB]; - } + MachineFunction &MF; + const TargetInstrInfo &TII; + const TargetRegisterInfo &TRI; + const PhysicalRegisterInfo PRI; + const MachineDominatorTree &MDT; + const MachineDominanceFrontier &MDF; + const TargetOperandInfo &TOI; + RegisterAggr LiveIns; NodeAddr<FuncNode*> Func; NodeAllocator Memory; // Local map: MachineBasicBlock -> NodeAddr<BlockNode*> std::map<MachineBasicBlock*,NodeAddr<BlockNode*>> BlockNodes; // Lane mask map. LaneMaskIndex LMI; - - MachineFunction &MF; - const TargetInstrInfo &TII; - const TargetRegisterInfo &TRI; - const MachineDominatorTree &MDT; - const MachineDominanceFrontier &MDF; - const TargetOperandInfo &TOI; }; // struct DataFlowGraph template <typename Predicate> @@ -1013,12 +922,6 @@ namespace rdf { return MM; } - // Optionally print the lane mask, if it is not ~0. - struct PrintLaneMaskOpt { - PrintLaneMaskOpt(LaneBitmask M) : Mask(M) {} - LaneBitmask Mask; - }; - raw_ostream &operator<< (raw_ostream &OS, const PrintLaneMaskOpt &P); template <typename T> struct Print; template <typename T> diff --git a/contrib/llvm/lib/Target/Hexagon/RDFLiveness.cpp b/contrib/llvm/lib/Target/Hexagon/RDFLiveness.cpp index e74c4bfc1645..b0532f933b16 100644 --- a/contrib/llvm/lib/Target/Hexagon/RDFLiveness.cpp +++ b/contrib/llvm/lib/Target/Hexagon/RDFLiveness.cpp @@ -31,11 +31,15 @@ #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Target/TargetRegisterInfo.h" using namespace llvm; using namespace rdf; +static cl::opt<unsigned> MaxRecNest("rdf-liveness-max-rec", cl::init(25), + cl::Hidden, cl::desc("Maximum recursion level")); + namespace llvm { namespace rdf { template<> @@ -85,7 +89,8 @@ namespace rdf { // the data-flow. NodeList Liveness::getAllReachingDefs(RegisterRef RefRR, - NodeAddr<RefNode*> RefA, bool FullChain, const RegisterAggr &DefRRs) { + NodeAddr<RefNode*> RefA, bool TopShadows, bool FullChain, + const RegisterAggr &DefRRs) { NodeList RDefs; // Return value. SetVector<NodeId> DefQ; SetVector<NodeId> Owners; @@ -105,6 +110,11 @@ NodeList Liveness::getAllReachingDefs(RegisterRef RefRR, auto SNA = DFG.addr<RefNode*>(Start); if (NodeId RD = SNA.Addr->getReachingDef()) DefQ.insert(RD); + if (TopShadows) { + for (auto S : DFG.getRelatedRefs(RefA.Addr->getOwner(DFG), RefA)) + if (NodeId RD = NodeAddr<RefNode*>(S).Addr->getReachingDef()) + DefQ.insert(RD); + } // Collect all the reaching defs, going up until a phi node is encountered, // or there are no more reaching defs. From this set, the actual set of @@ -119,7 +129,7 @@ NodeList Liveness::getAllReachingDefs(RegisterRef RefRR, // Stop at the covering/overwriting def of the initial register reference. RegisterRef RR = TA.Addr->getRegRef(DFG); if (!DFG.IsPreservingDef(TA)) - if (RegisterAggr::isCoverOf(RR, RefRR, TRI)) + if (RegisterAggr::isCoverOf(RR, RefRR, PRI)) continue; // Get the next level of reaching defs. This will include multiple // reaching defs for shadows. @@ -134,7 +144,7 @@ NodeList Liveness::getAllReachingDefs(RegisterRef RefRR, for (NodeId N : DefQ) { auto TA = DFG.addr<DefNode*>(N); bool IsPhi = TA.Addr->getFlags() & NodeAttrs::PhiRef; - if (!IsPhi && !DFG.alias(RefRR, TA.Addr->getRegRef(DFG))) + if (!IsPhi && !PRI.alias(RefRR, TA.Addr->getRegRef(DFG))) continue; Defs.insert(TA.Id); Owners.insert(TA.Addr->getOwner(DFG).Id); @@ -241,20 +251,30 @@ NodeList Liveness::getAllReachingDefs(RegisterRef RefRR, } -NodeSet Liveness::getAllReachingDefsRec(RegisterRef RefRR, - NodeAddr<RefNode*> RefA, NodeSet &Visited, const NodeSet &Defs) { +std::pair<NodeSet,bool> +Liveness::getAllReachingDefsRec(RegisterRef RefRR, NodeAddr<RefNode*> RefA, + NodeSet &Visited, const NodeSet &Defs) { + return getAllReachingDefsRecImpl(RefRR, RefA, Visited, Defs, 0, MaxRecNest); +} + + +std::pair<NodeSet,bool> +Liveness::getAllReachingDefsRecImpl(RegisterRef RefRR, NodeAddr<RefNode*> RefA, + NodeSet &Visited, const NodeSet &Defs, unsigned Nest, unsigned MaxNest) { + if (Nest > MaxNest) + return { NodeSet(), false }; // Collect all defined registers. Do not consider phis to be defining // anything, only collect "real" definitions. - RegisterAggr DefRRs(TRI); + RegisterAggr DefRRs(PRI); for (NodeId D : Defs) { const auto DA = DFG.addr<const DefNode*>(D); if (!(DA.Addr->getFlags() & NodeAttrs::PhiRef)) DefRRs.insert(DA.Addr->getRegRef(DFG)); } - NodeList RDs = getAllReachingDefs(RefRR, RefA, true, DefRRs); + NodeList RDs = getAllReachingDefs(RefRR, RefA, false, true, DefRRs); if (RDs.empty()) - return Defs; + return { Defs, true }; // Make a copy of the preexisting definitions and add the newly found ones. NodeSet TmpDefs = Defs; @@ -273,12 +293,74 @@ NodeSet Liveness::getAllReachingDefsRec(RegisterRef RefRR, Visited.insert(PA.Id); // Go over all phi uses and get the reaching defs for each use. for (auto U : PA.Addr->members_if(DFG.IsRef<NodeAttrs::Use>, DFG)) { - const auto &T = getAllReachingDefsRec(RefRR, U, Visited, TmpDefs); - Result.insert(T.begin(), T.end()); + const auto &T = getAllReachingDefsRecImpl(RefRR, U, Visited, TmpDefs, + Nest+1, MaxNest); + if (!T.second) + return { T.first, false }; + Result.insert(T.first.begin(), T.first.end()); } } - return Result; + return { Result, true }; +} + +/// Find the nearest ref node aliased to RefRR, going upwards in the data +/// flow, starting from the instruction immediately preceding Inst. +NodeAddr<RefNode*> Liveness::getNearestAliasedRef(RegisterRef RefRR, + NodeAddr<InstrNode*> IA) { + NodeAddr<BlockNode*> BA = IA.Addr->getOwner(DFG); + NodeList Ins = BA.Addr->members(DFG); + NodeId FindId = IA.Id; + auto E = Ins.rend(); + auto B = std::find_if(Ins.rbegin(), E, + [FindId] (const NodeAddr<InstrNode*> T) { + return T.Id == FindId; + }); + // Do not scan IA (which is what B would point to). + if (B != E) + ++B; + + do { + // Process the range of instructions from B to E. + for (NodeAddr<InstrNode*> I : make_range(B, E)) { + NodeList Refs = I.Addr->members(DFG); + NodeAddr<RefNode*> Clob, Use; + // Scan all the refs in I aliased to RefRR, and return the one that + // is the closest to the output of I, i.e. def > clobber > use. + for (NodeAddr<RefNode*> R : Refs) { + if (!PRI.alias(R.Addr->getRegRef(DFG), RefRR)) + continue; + if (DFG.IsDef(R)) { + // If it's a non-clobbering def, just return it. + if (!(R.Addr->getFlags() & NodeAttrs::Clobbering)) + return R; + Clob = R; + } else { + Use = R; + } + } + if (Clob.Id != 0) + return Clob; + if (Use.Id != 0) + return Use; + } + + // Go up to the immediate dominator, if any. + MachineBasicBlock *BB = BA.Addr->getCode(); + BA = NodeAddr<BlockNode*>(); + if (MachineDomTreeNode *N = MDT.getNode(BB)) { + if ((N = N->getIDom())) + BA = DFG.findBlock(N->getBlock()); + } + if (!BA.Id) + break; + + Ins = BA.Addr->members(DFG); + B = Ins.rbegin(); + E = Ins.rend(); + } while (true); + + return NodeAddr<RefNode*>(); } @@ -299,7 +381,7 @@ NodeSet Liveness::getAllReachedUses(RegisterRef RefRR, auto UA = DFG.addr<UseNode*>(U); if (!(UA.Addr->getFlags() & NodeAttrs::Undef)) { RegisterRef UR = UA.Addr->getRegRef(DFG); - if (DFG.alias(RefRR, UR) && !DefRRs.hasCoverOf(UR)) + if (PRI.alias(RefRR, UR) && !DefRRs.hasCoverOf(UR)) Uses.insert(U); } U = UA.Addr->getSibling(); @@ -312,7 +394,7 @@ NodeSet Liveness::getAllReachedUses(RegisterRef RefRR, RegisterRef DR = DA.Addr->getRegRef(DFG); // If this def is already covered, it cannot reach anything new. // Similarly, skip it if it is not aliased to the interesting register. - if (DefRRs.hasCoverOf(DR) || !DFG.alias(RefRR, DR)) + if (DefRRs.hasCoverOf(DR) || !PRI.alias(RefRR, DR)) continue; NodeSet T; if (DFG.IsPreservingDef(DA)) { @@ -343,6 +425,7 @@ void Liveness::computePhiInfo() { // phi use -> (map: reaching phi -> set of registers defined in between) std::map<NodeId,std::map<NodeId,RegisterAggr>> PhiUp; std::vector<NodeId> PhiUQ; // Work list of phis for upward propagation. + std::map<NodeId,RegisterAggr> PhiDRs; // Phi -> registers defined by it. // Go over all phis. for (NodeAddr<PhiNode*> PhiA : Phis) { @@ -355,12 +438,15 @@ void Liveness::computePhiInfo() { // For each def, add to the queue all reached (non-phi) defs. SetVector<NodeId> DefQ; NodeSet PhiDefs; + RegisterAggr DRs(PRI); for (NodeAddr<RefNode*> R : PhiRefs) { if (!DFG.IsRef<NodeAttrs::Def>(R)) continue; + DRs.insert(R.Addr->getRegRef(DFG)); DefQ.insert(R.Id); PhiDefs.insert(R.Id); } + PhiDRs.insert(std::make_pair(PhiA.Id, DRs)); // Collect the super-set of all possible reached uses. This set will // contain all uses reached from this phi, either directly from the @@ -377,9 +463,9 @@ void Liveness::computePhiInfo() { NodeAddr<UseNode*> A = DFG.addr<UseNode*>(UN); uint16_t F = A.Addr->getFlags(); if ((F & (NodeAttrs::Undef | NodeAttrs::PhiRef)) == 0) { - RegisterRef R = DFG.normalizeRef(getRestrictedRegRef(A)); + RegisterRef R = PRI.normalize(A.Addr->getRegRef(DFG)); RealUses[R.Reg].insert({A.Id,R.Mask}); - } + } UN = A.Addr->getSibling(); } // Visit all reached defs, and add them to the queue. These defs may @@ -424,17 +510,13 @@ void Liveness::computePhiInfo() { auto UA = DFG.addr<UseNode*>(I->first); // Undef flag is checked above. assert((UA.Addr->getFlags() & NodeAttrs::Undef) == 0); - RegisterRef R(UI->first, I->second); + RegisterRef R(UI->first, I->second); NodeList RDs = getAllReachingDefs(R, UA); - if (any_of(RDs, InPhiDefs)) - ++I; - else - I = Uses.erase(I); + // If none of the reaching defs of R are from this phi, remove this + // use of R. + I = any_of(RDs, InPhiDefs) ? std::next(I) : Uses.erase(I); } - if (Uses.empty()) - UI = RealUses.erase(UI); - else - ++UI; + UI = Uses.empty() ? RealUses.erase(UI) : std::next(UI); } // If this phi reaches some "real" uses, add it to the queue for upward @@ -452,32 +534,29 @@ void Liveness::computePhiInfo() { for (auto I : PhiRefs) { if (!DFG.IsRef<NodeAttrs::Use>(I) || SeenUses.count(I.Id)) continue; - NodeAddr<UseNode*> UA = I; - - // Given a phi use UA, traverse all related phi uses (including UA). - // The related phi uses may reach different phi nodes or may reach the - // same phi node. If multiple uses reach the same phi P, the intervening - // defs must be accumulated for all such uses. To group all such uses - // into one set, map their node ids to the first use id that reaches P. - std::map<NodeId,NodeId> FirstUse; // Phi reached up -> first phi use. - - for (NodeAddr<UseNode*> VA : DFG.getRelatedRefs(PhiA, UA)) { - SeenUses.insert(VA.Id); - RegisterAggr DefRRs(TRI); - for (NodeAddr<DefNode*> DA : getAllReachingDefs(VA)) { - if (DA.Addr->getFlags() & NodeAttrs::PhiRef) { - NodeId RP = DA.Addr->getOwner(DFG).Id; - NodeId FU = FirstUse.insert({RP,VA.Id}).first->second; - std::map<NodeId,RegisterAggr> &M = PhiUp[FU]; - auto F = M.find(RP); - if (F == M.end()) - M.insert(std::make_pair(RP, DefRRs)); - else - F->second.insert(DefRRs); - } - DefRRs.insert(DA.Addr->getRegRef(DFG)); + NodeAddr<PhiUseNode*> PUA = I; + if (PUA.Addr->getReachingDef() == 0) + continue; + + RegisterRef UR = PUA.Addr->getRegRef(DFG); + NodeList Ds = getAllReachingDefs(UR, PUA, true, false, NoRegs); + RegisterAggr DefRRs(PRI); + + for (NodeAddr<DefNode*> D : Ds) { + if (D.Addr->getFlags() & NodeAttrs::PhiRef) { + NodeId RP = D.Addr->getOwner(DFG).Id; + std::map<NodeId,RegisterAggr> &M = PhiUp[PUA.Id]; + auto F = M.find(RP); + if (F == M.end()) + M.insert(std::make_pair(RP, DefRRs)); + else + F->second.insert(DefRRs); } + DefRRs.insert(D.Addr->getRegRef(DFG)); } + + for (NodeAddr<PhiUseNode*> T : DFG.getRelatedRefs(PhiA, PUA)) + SeenUses.insert(T.Id); } } @@ -522,7 +601,7 @@ void Liveness::computePhiInfo() { for (NodeAddr<UseNode*> UA : PUs) { std::map<NodeId,RegisterAggr> &PUM = PhiUp[UA.Id]; - RegisterRef UR = DFG.normalizeRef(getRestrictedRegRef(UA)); + RegisterRef UR = PRI.normalize(UA.Addr->getRegRef(DFG)); for (const std::pair<NodeId,RegisterAggr> &P : PUM) { bool Changed = false; const RegisterAggr &MidDefs = P.second; @@ -540,14 +619,19 @@ void Liveness::computePhiInfo() { // then add (R-MidDefs,U) to RealUseMap[P] // for (const std::pair<RegisterId,NodeRefSet> &T : RUM) { - RegisterRef R = DFG.restrictRef(RegisterRef(T.first), UR); - if (!R) + RegisterRef R(T.first); + // The current phi (PA) could be a phi for a regmask. It could + // reach a whole variety of uses that are not related to the + // specific upward phi (P.first). + const RegisterAggr &DRs = PhiDRs.at(P.first); + if (!DRs.hasAliasOf(R)) continue; + R = DRs.intersectWith(R); for (std::pair<NodeId,LaneBitmask> V : T.second) { - RegisterRef S = DFG.restrictRef(RegisterRef(R.Reg, V.second), R); - if (!S) + LaneBitmask M = R.Mask & V.second; + if (M.none()) continue; - if (RegisterRef SS = MidDefs.clearIn(S)) { + if (RegisterRef SS = MidDefs.clearIn(RegisterRef(R.Reg, M))) { NodeRefSet &RS = RealUseMap[P.first][SS.Reg]; Changed |= RS.insert({V.first,SS.Mask}).second; } @@ -645,30 +729,43 @@ void Liveness::computeLiveIns() { if (RUs.empty()) continue; + NodeSet SeenUses; for (auto U : PA.Addr->members_if(DFG.IsRef<NodeAttrs::Use>, DFG)) { + if (!SeenUses.insert(U.Id).second) + continue; NodeAddr<PhiUseNode*> PUA = U; if (PUA.Addr->getReachingDef() == 0) continue; - // Mark all reached "real" uses of P as live on exit in the - // predecessor. - // Remap all the RUs so that they have a correct reaching def. + // Each phi has some set (possibly empty) of reached "real" uses, + // that is, uses that are part of the compiled program. Such a use + // may be located in some farther block, but following a chain of + // reaching defs will eventually lead to this phi. + // Any chain of reaching defs may fork at a phi node, but there + // will be a path upwards that will lead to this phi. Now, this + // chain will need to fork at this phi, since some of the reached + // uses may have definitions joining in from multiple predecessors. + // For each reached "real" use, identify the set of reaching defs + // coming from each predecessor P, and add them to PhiLOX[P]. + // auto PrA = DFG.addr<BlockNode*>(PUA.Addr->getPredecessor()); RefMap &LOX = PhiLOX[PrA.Addr->getCode()]; - RegisterRef UR = DFG.normalizeRef(getRestrictedRegRef(PUA)); - for (const std::pair<RegisterId,NodeRefSet> &T : RUs) { - // Check if T.first aliases UR? - LaneBitmask M; - for (std::pair<NodeId,LaneBitmask> P : T.second) - M |= P.second; - - RegisterRef S = DFG.restrictRef(RegisterRef(T.first, M), UR); - if (!S) - continue; - for (NodeAddr<DefNode*> D : getAllReachingDefs(S, PUA)) - LOX[S.Reg].insert({D.Id, S.Mask}); + for (const std::pair<RegisterId,NodeRefSet> &RS : RUs) { + // We need to visit each individual use. + for (std::pair<NodeId,LaneBitmask> P : RS.second) { + // Create a register ref corresponding to the use, and find + // all reaching defs starting from the phi use, and treating + // all related shadows as a single use cluster. + RegisterRef S(RS.first, P.second); + NodeList Ds = getAllReachingDefs(S, PUA, true, false, NoRegs); + for (NodeAddr<DefNode*> D : Ds) + LOX[S.Reg].insert({D.Id, S.Mask}); + } } + + for (NodeAddr<PhiUseNode*> T : DFG.getRelatedRefs(PA, PUA)) + SeenUses.insert(T.Id); } // for U : phi uses } // for P : Phis } // for B : Blocks @@ -684,9 +781,7 @@ void Liveness::computeLiveIns() { traverse(&MF.front(), LiveIn); // Add function live-ins to the live-in set of the function entry block. - auto &EntryIn = LiveMap[&MF.front()]; - for (auto I = MRI.livein_begin(), E = MRI.livein_end(); I != E; ++I) - EntryIn.insert(RegisterRef(I->first)); + LiveMap[&MF.front()].insert(DFG.getLiveIns()); if (Trace) { // Dump the liveness map @@ -702,19 +797,9 @@ void Liveness::computeLiveIns() { //dbgs() << "\tcomp = " << Print<RegisterAggr>(LiveMap[&B], DFG) << '\n'; LV.clear(); - for (std::pair<RegisterId,LaneBitmask> P : LiveMap[&B]) { - MCSubRegIndexIterator S(P.first, &TRI); - if (!S.isValid()) { - LV.push_back(RegisterRef(P.first)); - continue; - } - do { - LaneBitmask M = TRI.getSubRegIndexLaneMask(S.getSubRegIndex()); - if ((M & P.second).any()) - LV.push_back(RegisterRef(S.getSubReg())); - ++S; - } while (S.isValid()); - } + const RegisterAggr &LG = LiveMap[&B]; + for (auto I = LG.rr_begin(), E = LG.rr_end(); I != E; ++I) + LV.push_back(*I); std::sort(LV.begin(), LV.end()); dbgs() << "\tcomp = {"; for (auto I : LV) @@ -735,9 +820,10 @@ void Liveness::resetLiveIns() { for (auto I : T) B.removeLiveIn(I); // Add the newly computed live-ins. - auto &LiveIns = LiveMap[&B]; - for (auto I : LiveIns) { - B.addLiveIn({MCPhysReg(I.first), I.second}); + const RegisterAggr &LiveIns = LiveMap[&B]; + for (auto I = LiveIns.rr_begin(), E = LiveIns.rr_end(); I != E; ++I) { + RegisterRef R = *I; + B.addLiveIn({MCPhysReg(R.Reg), R.Mask}); } } } @@ -791,7 +877,7 @@ void Liveness::resetKills(MachineBasicBlock *B) { Live.reset(*SR); } for (auto &Op : MI->operands()) { - if (!Op.isReg() || !Op.isUse()) + if (!Op.isReg() || !Op.isUse() || Op.isUndef()) continue; unsigned R = Op.getReg(); if (!TargetRegisterInfo::isPhysicalRegister(R)) @@ -803,9 +889,8 @@ void Liveness::resetKills(MachineBasicBlock *B) { IsLive = true; break; } - if (IsLive) - continue; - Op.setIsKill(true); + if (!IsLive) + Op.setIsKill(true); for (MCSubRegIterator SR(R, &TRI, true); SR.isValid(); ++SR) Live.set(*SR); } @@ -813,17 +898,6 @@ void Liveness::resetKills(MachineBasicBlock *B) { } -RegisterRef Liveness::getRestrictedRegRef(NodeAddr<RefNode*> RA) const { - assert(DFG.IsRef<NodeAttrs::Use>(RA)); - if (RA.Addr->getFlags() & NodeAttrs::Shadow) { - NodeId RD = RA.Addr->getReachingDef(); - assert(RD); - RA = DFG.addr<DefNode*>(RD); - } - return RA.Addr->getRegRef(DFG); -} - - // Helper function to obtain the basic block containing the reaching def // of the given use. MachineBasicBlock *Liveness::getBlockWithRef(NodeId RN) const { @@ -921,7 +995,7 @@ void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) { // propagated upwards. This only applies to non-preserving defs, // and to the parts of the register actually covered by those defs. // (Note that phi defs should always be preserving.) - RegisterAggr RRs(TRI); + RegisterAggr RRs(PRI); LRef.Mask = OR.second; if (!DFG.IsPreservingDef(DA)) { @@ -949,10 +1023,9 @@ void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) { // registers are not covering LRef. The first def from the // upward chain will be live. // Subtract all accumulated defs (RRs) from LRef. - RegisterAggr L(TRI); - L.insert(LRef).clear(RRs); - assert(!L.empty()); - NewDefs.insert({TA.Id,L.begin()->second}); + RegisterRef T = RRs.clearIn(LRef); + assert(T); + NewDefs.insert({TA.Id,T.Mask}); break; } @@ -983,7 +1056,7 @@ void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) { for (NodeAddr<UseNode*> UA : IA.Addr->members_if(DFG.IsUse, DFG)) { if (UA.Addr->getFlags() & NodeAttrs::Undef) continue; - RegisterRef RR = DFG.normalizeRef(UA.Addr->getRegRef(DFG)); + RegisterRef RR = PRI.normalize(UA.Addr->getRegRef(DFG)); for (NodeAddr<DefNode*> D : getAllReachingDefs(UA)) if (getBlockWithRef(D.Id) != B) LiveIn[RR.Reg].insert({D.Id,RR.Mask}); diff --git a/contrib/llvm/lib/Target/Hexagon/RDFLiveness.h b/contrib/llvm/lib/Target/Hexagon/RDFLiveness.h index c88396f36bbb..6f2615b7c4f3 100644 --- a/contrib/llvm/lib/Target/Hexagon/RDFLiveness.h +++ b/contrib/llvm/lib/Target/Hexagon/RDFLiveness.h @@ -33,7 +33,7 @@ namespace rdf { // This is really a std::map, except that it provides a non-trivial // default constructor to the element accessed via []. struct LiveMapType { - LiveMapType(const TargetRegisterInfo &tri) : Empty(tri) {} + LiveMapType(const PhysicalRegisterInfo &pri) : Empty(pri) {} RegisterAggr &operator[] (MachineBasicBlock *B) { return Map.emplace(B, Empty).first->second; @@ -49,26 +49,31 @@ namespace rdf { typedef std::map<RegisterId,NodeRefSet> RefMap; Liveness(MachineRegisterInfo &mri, const DataFlowGraph &g) - : DFG(g), TRI(g.getTRI()), MDT(g.getDT()), MDF(g.getDF()), - MRI(mri), LiveMap(g.getTRI()), Empty(), NoRegs(g.getTRI()), - Trace(false) {} + : DFG(g), TRI(g.getTRI()), PRI(g.getPRI()), MDT(g.getDT()), + MDF(g.getDF()), LiveMap(g.getPRI()), Empty(), + NoRegs(g.getPRI()), Trace(false) {} NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr<RefNode*> RefA, - bool FullChain, const RegisterAggr &DefRRs); + bool TopShadows, bool FullChain, const RegisterAggr &DefRRs); NodeList getAllReachingDefs(NodeAddr<RefNode*> RefA) { - return getAllReachingDefs(RefA.Addr->getRegRef(DFG), RefA, false, NoRegs); + return getAllReachingDefs(RefA.Addr->getRegRef(DFG), RefA, false, + false, NoRegs); } NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr<RefNode*> RefA) { - return getAllReachingDefs(RefRR, RefA, false, NoRegs); + return getAllReachingDefs(RefRR, RefA, false, false, NoRegs); } - NodeSet getAllReachingDefsRec(RegisterRef RefRR, NodeAddr<RefNode*> RefA, - NodeSet &Visited, const NodeSet &Defs); NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr<DefNode*> DefA, const RegisterAggr &DefRRs); NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr<DefNode*> DefA) { return getAllReachedUses(RefRR, DefA, NoRegs); } + std::pair<NodeSet,bool> getAllReachingDefsRec(RegisterRef RefRR, + NodeAddr<RefNode*> RefA, NodeSet &Visited, const NodeSet &Defs); + + NodeAddr<RefNode*> getNearestAliasedRef(RegisterRef RefRR, + NodeAddr<InstrNode*> IA); + LiveMapType &getLiveMap() { return LiveMap; } const LiveMapType &getLiveMap() const { return LiveMap; } const RefMap &getRealUses(NodeId P) const { @@ -87,9 +92,9 @@ namespace rdf { private: const DataFlowGraph &DFG; const TargetRegisterInfo &TRI; + const PhysicalRegisterInfo &PRI; const MachineDominatorTree &MDT; const MachineDominanceFrontier &MDF; - MachineRegisterInfo &MRI; LiveMapType LiveMap; const RefMap Empty; const RegisterAggr NoRegs; @@ -121,12 +126,13 @@ namespace rdf { // the dominator tree), create a map: block -> set of uses live on exit. std::map<MachineBasicBlock*,RefMap> PhiLOX; - bool isRestrictedToRef(NodeAddr<InstrNode*> IA, NodeAddr<RefNode*> RA, - RegisterRef RR) const; - RegisterRef getRestrictedRegRef(NodeAddr<RefNode*> RA) const; MachineBasicBlock *getBlockWithRef(NodeId RN) const; void traverse(MachineBasicBlock *B, RefMap &LiveIn); void emptify(RefMap &M); + + std::pair<NodeSet,bool> getAllReachingDefsRecImpl(RegisterRef RefRR, + NodeAddr<RefNode*> RefA, NodeSet &Visited, const NodeSet &Defs, + unsigned Nest, unsigned MaxNest); }; } // namespace rdf } // namespace llvm diff --git a/contrib/llvm/lib/Target/Hexagon/RDFRegisters.cpp b/contrib/llvm/lib/Target/Hexagon/RDFRegisters.cpp new file mode 100644 index 000000000000..5c5496a548af --- /dev/null +++ b/contrib/llvm/lib/Target/Hexagon/RDFRegisters.cpp @@ -0,0 +1,368 @@ +//===--- RDFRegisters.cpp ---------------------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "RDFRegisters.h" +#include "llvm/ADT/BitVector.h" +#include "llvm/CodeGen/MachineFunction.h" + +using namespace llvm; +using namespace rdf; + +PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri, + const MachineFunction &mf) + : TRI(tri) { + RegInfos.resize(TRI.getNumRegs()); + + BitVector BadRC(TRI.getNumRegs()); + for (const TargetRegisterClass *RC : TRI.regclasses()) { + for (MCPhysReg R : *RC) { + RegInfo &RI = RegInfos[R]; + if (RI.RegClass != nullptr && !BadRC[R]) { + if (RC->LaneMask != RI.RegClass->LaneMask) { + BadRC.set(R); + RI.RegClass = nullptr; + } + } else + RI.RegClass = RC; + } + } + + UnitInfos.resize(TRI.getNumRegUnits()); + + for (uint32_t U = 0, NU = TRI.getNumRegUnits(); U != NU; ++U) { + if (UnitInfos[U].Reg != 0) + continue; + MCRegUnitRootIterator R(U, &TRI); + assert(R.isValid()); + RegisterId F = *R; + ++R; + if (R.isValid()) { + UnitInfos[U].Mask = LaneBitmask::getAll(); + UnitInfos[U].Reg = F; + } else { + for (MCRegUnitMaskIterator I(F, &TRI); I.isValid(); ++I) { + std::pair<uint32_t,LaneBitmask> P = *I; + UnitInfo &UI = UnitInfos[P.first]; + UI.Reg = F; + if (P.second.any()) { + UI.Mask = P.second; + } else { + if (const TargetRegisterClass *RC = RegInfos[F].RegClass) + UI.Mask = RC->LaneMask; + else + UI.Mask = LaneBitmask::getAll(); + } + } + } + } + + for (const uint32_t *RM : TRI.getRegMasks()) + RegMasks.insert(RM); + for (const MachineBasicBlock &B : mf) + for (const MachineInstr &In : B) + for (const MachineOperand &Op : In.operands()) + if (Op.isRegMask()) + RegMasks.insert(Op.getRegMask()); +} + +RegisterRef PhysicalRegisterInfo::normalize(RegisterRef RR) const { + return RR; +} + +std::set<RegisterId> PhysicalRegisterInfo::getAliasSet(RegisterId Reg) const { + // Do not include RR in the alias set. + std::set<RegisterId> AS; + assert(isRegMaskId(Reg) || TargetRegisterInfo::isPhysicalRegister(Reg)); + if (isRegMaskId(Reg)) { + // XXX SLOW + const uint32_t *MB = getRegMaskBits(Reg); + for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) { + if (MB[i/32] & (1u << (i%32))) + continue; + AS.insert(i); + } + for (const uint32_t *RM : RegMasks) { + RegisterId MI = getRegMaskId(RM); + if (MI != Reg && aliasMM(RegisterRef(Reg), RegisterRef(MI))) + AS.insert(MI); + } + return AS; + } + + for (MCRegAliasIterator AI(Reg, &TRI, false); AI.isValid(); ++AI) + AS.insert(*AI); + for (const uint32_t *RM : RegMasks) { + RegisterId MI = getRegMaskId(RM); + if (aliasRM(RegisterRef(Reg), RegisterRef(MI))) + AS.insert(MI); + } + return AS; +} + +bool PhysicalRegisterInfo::aliasRR(RegisterRef RA, RegisterRef RB) const { + assert(TargetRegisterInfo::isPhysicalRegister(RA.Reg)); + assert(TargetRegisterInfo::isPhysicalRegister(RB.Reg)); + + MCRegUnitMaskIterator UMA(RA.Reg, &TRI); + MCRegUnitMaskIterator UMB(RB.Reg, &TRI); + // Reg units are returned in the numerical order. + while (UMA.isValid() && UMB.isValid()) { + // Skip units that are masked off in RA. + std::pair<RegisterId,LaneBitmask> PA = *UMA; + if (PA.second.any() && (PA.second & RA.Mask).none()) { + ++UMA; + continue; + } + // Skip units that are masked off in RB. + std::pair<RegisterId,LaneBitmask> PB = *UMB; + if (PB.second.any() && (PB.second & RB.Mask).none()) { + ++UMB; + continue; + } + + if (PA.first == PB.first) + return true; + if (PA.first < PB.first) + ++UMA; + else if (PB.first < PA.first) + ++UMB; + } + return false; +} + +bool PhysicalRegisterInfo::aliasRM(RegisterRef RR, RegisterRef RM) const { + assert(TargetRegisterInfo::isPhysicalRegister(RR.Reg) && isRegMaskId(RM.Reg)); + const uint32_t *MB = getRegMaskBits(RM.Reg); + bool Preserved = MB[RR.Reg/32] & (1u << (RR.Reg%32)); + // If the lane mask information is "full", e.g. when the given lane mask + // is a superset of the lane mask from the register class, check the regmask + // bit directly. + if (RR.Mask == LaneBitmask::getAll()) + return !Preserved; + const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass; + if (RC != nullptr && (RR.Mask & RC->LaneMask) == RC->LaneMask) + return !Preserved; + + // Otherwise, check all subregisters whose lane mask overlaps the given + // mask. For each such register, if it is preserved by the regmask, then + // clear the corresponding bits in the given mask. If at the end, all + // bits have been cleared, the register does not alias the regmask (i.e. + // is it preserved by it). + LaneBitmask M = RR.Mask; + for (MCSubRegIndexIterator SI(RR.Reg, &TRI); SI.isValid(); ++SI) { + LaneBitmask SM = TRI.getSubRegIndexLaneMask(SI.getSubRegIndex()); + if ((SM & RR.Mask).none()) + continue; + unsigned SR = SI.getSubReg(); + if (!(MB[SR/32] & (1u << (SR%32)))) + continue; + // The subregister SR is preserved. + M &= ~SM; + if (M.none()) + return false; + } + + return true; +} + +bool PhysicalRegisterInfo::aliasMM(RegisterRef RM, RegisterRef RN) const { + assert(isRegMaskId(RM.Reg) && isRegMaskId(RN.Reg)); + unsigned NumRegs = TRI.getNumRegs(); + const uint32_t *BM = getRegMaskBits(RM.Reg); + const uint32_t *BN = getRegMaskBits(RN.Reg); + + for (unsigned w = 0, nw = NumRegs/32; w != nw; ++w) { + // Intersect the negations of both words. Disregard reg=0, + // i.e. 0th bit in the 0th word. + uint32_t C = ~BM[w] & ~BN[w]; + if (w == 0) + C &= ~1; + if (C) + return true; + } + + // Check the remaining registers in the last word. + unsigned TailRegs = NumRegs % 32; + if (TailRegs == 0) + return false; + unsigned TW = NumRegs / 32; + uint32_t TailMask = (1u << TailRegs) - 1; + if (~BM[TW] & ~BN[TW] & TailMask) + return true; + + return false; +} + + +bool RegisterAggr::hasAliasOf(RegisterRef RR) const { + if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) { + // XXX SLOW + const uint32_t *MB = PRI.getRegMaskBits(RR.Reg); + for (unsigned i = 1, e = PRI.getTRI().getNumRegs(); i != e; ++i) { + if (MB[i/32] & (1u << (i%32))) + continue; + if (hasAliasOf(RegisterRef(i, LaneBitmask::getAll()))) + return true; + } + return false; + } + + for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) { + std::pair<uint32_t,LaneBitmask> P = *U; + if (P.second.none() || (P.second & RR.Mask).any()) + if (Units.test(P.first)) + return true; + } + return false; +} + +bool RegisterAggr::hasCoverOf(RegisterRef RR) const { + if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) { + // XXX SLOW + const uint32_t *MB = PRI.getRegMaskBits(RR.Reg); + for (unsigned i = 1, e = PRI.getTRI().getNumRegs(); i != e; ++i) { + if (MB[i/32] & (1u << (i%32))) + continue; + if (!hasCoverOf(RegisterRef(i, LaneBitmask::getAll()))) + return false; + } + return true; + } + + for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) { + std::pair<uint32_t,LaneBitmask> P = *U; + if (P.second.none() || (P.second & RR.Mask).any()) + if (!Units.test(P.first)) + return false; + } + return true; +} + +RegisterAggr &RegisterAggr::insert(RegisterRef RR) { + if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) { + BitVector PU(PRI.getTRI().getNumRegUnits()); // Preserved units. + const uint32_t *MB = PRI.getRegMaskBits(RR.Reg); + for (unsigned i = 1, e = PRI.getTRI().getNumRegs(); i != e; ++i) { + if (!(MB[i/32] & (1u << (i%32)))) + continue; + for (MCRegUnitIterator U(i, &PRI.getTRI()); U.isValid(); ++U) + PU.set(*U); + } + Units |= PU.flip(); + return *this; + } + + for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) { + std::pair<uint32_t,LaneBitmask> P = *U; + if (P.second.none() || (P.second & RR.Mask).any()) + Units.set(P.first); + } + return *this; +} + +RegisterAggr &RegisterAggr::insert(const RegisterAggr &RG) { + Units |= RG.Units; + return *this; +} + +RegisterAggr &RegisterAggr::intersect(RegisterRef RR) { + return intersect(RegisterAggr(PRI).insert(RR)); +} + +RegisterAggr &RegisterAggr::intersect(const RegisterAggr &RG) { + Units &= RG.Units; + return *this; +} + +RegisterAggr &RegisterAggr::clear(RegisterRef RR) { + return clear(RegisterAggr(PRI).insert(RR)); +} + +RegisterAggr &RegisterAggr::clear(const RegisterAggr &RG) { + Units.reset(RG.Units); + return *this; +} + +RegisterRef RegisterAggr::intersectWith(RegisterRef RR) const { + RegisterAggr T(PRI); + T.insert(RR).intersect(*this); + if (T.empty()) + return RegisterRef(); + RegisterRef NR = T.makeRegRef(); + assert(NR); + return NR; +} + +RegisterRef RegisterAggr::clearIn(RegisterRef RR) const { + return RegisterAggr(PRI).insert(RR).clear(*this).makeRegRef(); +} + +RegisterRef RegisterAggr::makeRegRef() const { + int U = Units.find_first(); + if (U < 0) + return RegisterRef(); + + auto AliasedRegs = [this] (uint32_t Unit, BitVector &Regs) { + for (MCRegUnitRootIterator R(Unit, &PRI.getTRI()); R.isValid(); ++R) + for (MCSuperRegIterator S(*R, &PRI.getTRI(), true); S.isValid(); ++S) + Regs.set(*S); + }; + + // Find the set of all registers that are aliased to all the units + // in this aggregate. + + // Get all the registers aliased to the first unit in the bit vector. + BitVector Regs(PRI.getTRI().getNumRegs()); + AliasedRegs(U, Regs); + U = Units.find_next(U); + + // For each other unit, intersect it with the set of all registers + // aliased that unit. + while (U >= 0) { + BitVector AR(PRI.getTRI().getNumRegs()); + AliasedRegs(U, AR); + Regs &= AR; + U = Units.find_next(U); + } + + // If there is at least one register remaining, pick the first one, + // and consolidate the masks of all of its units contained in this + // aggregate. + + int F = Regs.find_first(); + if (F <= 0) + return RegisterRef(); + + LaneBitmask M; + for (MCRegUnitMaskIterator I(F, &PRI.getTRI()); I.isValid(); ++I) { + std::pair<uint32_t,LaneBitmask> P = *I; + if (Units.test(P.first)) + M |= P.second.none() ? LaneBitmask::getAll() : P.second; + } + return RegisterRef(F, M); +} + +void RegisterAggr::print(raw_ostream &OS) const { + OS << '{'; + for (int U = Units.find_first(); U >= 0; U = Units.find_next(U)) + OS << ' ' << PrintRegUnit(U, &PRI.getTRI()); + OS << " }"; +} + +RegisterAggr::rr_iterator::rr_iterator(const RegisterAggr &RG, + bool End) + : Owner(&RG) { + for (int U = RG.Units.find_first(); U >= 0; U = RG.Units.find_next(U)) { + RegisterRef R = RG.PRI.getRefForUnit(U); + Masks[R.Reg] |= R.Mask; + } + Pos = End ? Masks.end() : Masks.begin(); + Index = End ? Masks.size() : 0; +} + diff --git a/contrib/llvm/lib/Target/Hexagon/RDFRegisters.h b/contrib/llvm/lib/Target/Hexagon/RDFRegisters.h new file mode 100644 index 000000000000..4b35c85a6b62 --- /dev/null +++ b/contrib/llvm/lib/Target/Hexagon/RDFRegisters.h @@ -0,0 +1,209 @@ +//===--- RDFRegisters.h -----------------------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H +#define LLVM_LIB_TARGET_HEXAGON_RDFREGISTERS_H + +#include "llvm/ADT/BitVector.h" +#include "llvm/Target/TargetRegisterInfo.h" + +#include <set> +#include <unordered_map> +#include <vector> + +namespace llvm { +namespace rdf { + + typedef uint32_t RegisterId; + + // Template class for a map translating uint32_t into arbitrary types. + // The map will act like an indexed set: upon insertion of a new object, + // it will automatically assign a new index to it. Index of 0 is treated + // as invalid and is never allocated. + template <typename T, unsigned N = 32> + struct IndexedSet { + IndexedSet() : Map() { Map.reserve(N); } + + T get(uint32_t Idx) const { + // Index Idx corresponds to Map[Idx-1]. + assert(Idx != 0 && !Map.empty() && Idx-1 < Map.size()); + return Map[Idx-1]; + } + + uint32_t insert(T Val) { + // Linear search. + auto F = llvm::find(Map, Val); + if (F != Map.end()) + return F - Map.begin() + 1; + Map.push_back(Val); + return Map.size(); // Return actual_index + 1. + } + + uint32_t find(T Val) const { + auto F = llvm::find(Map, Val); + assert(F != Map.end()); + return F - Map.begin() + 1; + } + + typedef typename std::vector<T>::const_iterator const_iterator; + const_iterator begin() const { return Map.begin(); } + const_iterator end() const { return Map.end(); } + + private: + std::vector<T> Map; + }; + + struct RegisterRef { + RegisterId Reg = 0; + LaneBitmask Mask = LaneBitmask::getNone(); + + RegisterRef() = default; + explicit RegisterRef(RegisterId R, LaneBitmask M = LaneBitmask::getAll()) + : Reg(R), Mask(R != 0 ? M : LaneBitmask::getNone()) {} + + operator bool() const { + return Reg != 0 && Mask.any(); + } + bool operator== (const RegisterRef &RR) const { + return Reg == RR.Reg && Mask == RR.Mask; + } + bool operator!= (const RegisterRef &RR) const { + return !operator==(RR); + } + bool operator< (const RegisterRef &RR) const { + return Reg < RR.Reg || (Reg == RR.Reg && Mask < RR.Mask); + } + }; + + + struct PhysicalRegisterInfo { + PhysicalRegisterInfo(const TargetRegisterInfo &tri, + const MachineFunction &mf); + + static bool isRegMaskId(RegisterId R) { + return TargetRegisterInfo::isStackSlot(R); + } + RegisterId getRegMaskId(const uint32_t *RM) const { + return TargetRegisterInfo::index2StackSlot(RegMasks.find(RM)); + } + const uint32_t *getRegMaskBits(RegisterId R) const { + return RegMasks.get(TargetRegisterInfo::stackSlot2Index(R)); + } + RegisterRef normalize(RegisterRef RR) const; + + bool alias(RegisterRef RA, RegisterRef RB) const { + if (!isRegMaskId(RA.Reg)) + return !isRegMaskId(RB.Reg) ? aliasRR(RA, RB) : aliasRM(RA, RB); + return !isRegMaskId(RB.Reg) ? aliasRM(RB, RA) : aliasMM(RA, RB); + } + std::set<RegisterId> getAliasSet(RegisterId Reg) const; + + RegisterRef getRefForUnit(uint32_t U) const { + return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask); + } + + const TargetRegisterInfo &getTRI() const { return TRI; } + + private: + struct RegInfo { + const TargetRegisterClass *RegClass = nullptr; + }; + struct UnitInfo { + RegisterId Reg = 0; + LaneBitmask Mask; + }; + + const TargetRegisterInfo &TRI; + std::vector<RegInfo> RegInfos; + std::vector<UnitInfo> UnitInfos; + IndexedSet<const uint32_t*> RegMasks; + + bool aliasRR(RegisterRef RA, RegisterRef RB) const; + bool aliasRM(RegisterRef RR, RegisterRef RM) const; + bool aliasMM(RegisterRef RM, RegisterRef RN) const; + }; + + + struct RegisterAggr { + RegisterAggr(const PhysicalRegisterInfo &pri) + : Units(pri.getTRI().getNumRegUnits()), PRI(pri) {} + RegisterAggr(const RegisterAggr &RG) = default; + + bool empty() const { return Units.empty(); } + bool hasAliasOf(RegisterRef RR) const; + bool hasCoverOf(RegisterRef RR) const; + static bool isCoverOf(RegisterRef RA, RegisterRef RB, + const PhysicalRegisterInfo &PRI) { + return RegisterAggr(PRI).insert(RA).hasCoverOf(RB); + } + + RegisterAggr &insert(RegisterRef RR); + RegisterAggr &insert(const RegisterAggr &RG); + RegisterAggr &intersect(RegisterRef RR); + RegisterAggr &intersect(const RegisterAggr &RG); + RegisterAggr &clear(RegisterRef RR); + RegisterAggr &clear(const RegisterAggr &RG); + + RegisterRef intersectWith(RegisterRef RR) const; + RegisterRef clearIn(RegisterRef RR) const; + RegisterRef makeRegRef() const; + + void print(raw_ostream &OS) const; + + struct rr_iterator { + typedef std::map<RegisterId,LaneBitmask> MapType; + private: + MapType Masks; + MapType::iterator Pos; + unsigned Index; + const RegisterAggr *Owner; + public: + rr_iterator(const RegisterAggr &RG, bool End); + RegisterRef operator*() const { + return RegisterRef(Pos->first, Pos->second); + } + rr_iterator &operator++() { + ++Pos; + ++Index; + return *this; + } + bool operator==(const rr_iterator &I) const { + assert(Owner == I.Owner); + return Index == I.Index; + } + bool operator!=(const rr_iterator &I) const { + return !(*this == I); + } + }; + + rr_iterator rr_begin() const { + return rr_iterator(*this, false); + } + rr_iterator rr_end() const { + return rr_iterator(*this, true); + } + + private: + BitVector Units; + const PhysicalRegisterInfo &PRI; + }; + + + // Optionally print the lane mask, if it is not ~0. + struct PrintLaneMaskOpt { + PrintLaneMaskOpt(LaneBitmask M) : Mask(M) {} + LaneBitmask Mask; + }; + raw_ostream &operator<< (raw_ostream &OS, const PrintLaneMaskOpt &P); + +} // namespace rdf +} // namespace llvm + +#endif + |