diff options
Diffstat (limited to 'contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.td')
| -rw-r--r-- | contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 65 |
1 files changed, 42 insertions, 23 deletions
diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index 3b32c10ed5b0..5cfeba720d90 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/contrib/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -13,7 +13,7 @@ include "HexagonInstrFormats.td" include "HexagonOperands.td" - +include "HexagonInstrEnc.td" // Pattern fragment that combines the value type and the register class // into a single parameter. // The pat frags in the definitions below need to have a named register, @@ -1426,9 +1426,6 @@ def retflag : SDNode<"HexagonISD::RET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; def eh_return: SDNode<"HexagonISD::EH_RETURN", SDTNone, [SDNPHasChain]>; -def SDHexagonBR_JT: SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; -def HexagonBR_JT: SDNode<"HexagonISD::BR_JT", SDHexagonBR_JT, [SDNPHasChain]>; - class CondStr<string CReg, bit True, bit New> { string S = "if (" # !if(True,"","!") # CReg # !if(New,".new","") # ") "; } @@ -1606,8 +1603,6 @@ def EH_RETURN_JMPR : T_JMPr; def: Pat<(eh_return), (EH_RETURN_JMPR (i32 R31))>; -def: Pat<(HexagonBR_JT (i32 IntRegs:$dst)), - (J2_jumpr IntRegs:$dst)>; def: Pat<(brind (i32 IntRegs:$dst)), (J2_jumpr IntRegs:$dst)>; @@ -2825,7 +2820,7 @@ let CextOpcode = "ADD_acc" in { let isExtentSigned = 1 in def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8Ext, [(set (i32 IntRegs:$dst), - (add (add (i32 IntRegs:$src2), s16_16ImmPred:$src3), + (add (add (i32 IntRegs:$src2), s32ImmPred:$src3), (i32 IntRegs:$src1)))]>, ImmRegRel; def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0, @@ -2859,7 +2854,7 @@ class T_MType_acc_pat2 <InstHexagon MI, SDNode firstOp, SDNode secOp> def : T_MType_acc_pat2 <M2_xor_xacc, xor, xor>; def : T_MType_acc_pat1 <M2_macsin, mul, sub, u32ImmPred>; -def : T_MType_acc_pat1 <M2_naccii, add, sub, s16_16ImmPred>; +def : T_MType_acc_pat1 <M2_naccii, add, sub, s32ImmPred>; def : T_MType_acc_pat2 <M2_nacci, add, sub>; //===----------------------------------------------------------------------===// @@ -3303,7 +3298,8 @@ class T_store_pi <string mnemonic, RegisterClass RC, Operand ImmOp, !if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2}, !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, /* s4_0Imm */ offset{3-0}))); - let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1); + // Store upper-half and store doubleword cannot be NV. + let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, !if(isHalf,0,1)); let IClass = 0b1010; @@ -3322,7 +3318,7 @@ class T_store_pi <string mnemonic, RegisterClass RC, Operand ImmOp, //===----------------------------------------------------------------------===// let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in class T_pstore_pi <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<4> MajOp, bit isHalf, bit isPredNot, bit isPredNew > + bits<4> MajOp, bit isHalf, bit isPredNot, bit isPredNew> : STInst <(outs IntRegs:$_dst_), (ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3), !if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ", @@ -3341,7 +3337,8 @@ class T_pstore_pi <string mnemonic, RegisterClass RC, Operand ImmOp, !if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1}, /* s4_0Imm */ offset{3-0}))); - let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1); + // Store upper-half and store doubleword cannot be NV. + let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, !if(isHalf,0,1)); let isPredicatedNew = isPredNew; let isPredicatedFalse = isPredNot; @@ -3404,7 +3401,6 @@ def: Storepi_pat<post_store, I64, s4_3ImmPred, S2_storerd_pi>; //===----------------------------------------------------------------------===// // Template class for post increment stores with register offset. //===----------------------------------------------------------------------===// -let isNVStorable = 1 in class T_store_pr <string mnemonic, RegisterClass RC, bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0> : STInst <(outs IntRegs:$_dst_), @@ -3416,6 +3412,9 @@ class T_store_pr <string mnemonic, RegisterClass RC, bits<3> MajOp, bits<5> src3; let accessSize = AccessSz; + // Store upper-half and store doubleword cannot be NV. + let isNVStorable = !if(!eq(mnemonic,"memd"), 0, !if(isHalf,0,1)); + let IClass = 0b1010; let Inst{27-24} = 0b1101; @@ -3430,12 +3429,11 @@ def S2_storerb_pr : T_store_pr<"memb", IntRegs, 0b000, ByteAccess>; def S2_storerh_pr : T_store_pr<"memh", IntRegs, 0b010, HalfWordAccess>; def S2_storeri_pr : T_store_pr<"memw", IntRegs, 0b100, WordAccess>; def S2_storerd_pr : T_store_pr<"memd", DoubleRegs, 0b110, DoubleWordAccess>; - def S2_storerf_pr : T_store_pr<"memh", IntRegs, 0b011, HalfWordAccess, 1>; let opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in class T_store_io <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<3>MajOp, bit isH = 0> + bits<3> MajOp, bit isH = 0> : STInst <(outs), (ins IntRegs:$src1, ImmOp:$src2, RC:$src3), mnemonic#"($src1+#$src2) = $src3"#!if(isH,".h","")>, @@ -3455,6 +3453,8 @@ class T_store_io <string mnemonic, RegisterClass RC, Operand ImmOp, !if (!eq(ImmOpStr, "s11_2Ext"), src2{12-2}, !if (!eq(ImmOpStr, "s11_1Ext"), src2{11-1}, /* s11_0Ext */ src2{10-0}))); + // Store upper-half and store doubleword cannot be NV. + let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1)); let IClass = 0b1010; let Inst{27} = 0b0; @@ -3494,7 +3494,10 @@ class T_pstore_io <string mnemonic, RegisterClass RC, Operand ImmOp, !if (!eq(ImmOpStr, "u6_2Ext"), src3{7-2}, !if (!eq(ImmOpStr, "u6_1Ext"), src3{6-1}, /* u6_0Ext */ src3{5-0}))); - let IClass = 0b0100; + // Store upper-half and store doubleword cannot be NV. + let isNVStorable = !if (!eq(mnemonic, "memd"), 0, !if(isH,0,1)); + + let IClass = 0b0100; let Inst{27} = 0b0; let Inst{26} = PredNot; @@ -3508,7 +3511,7 @@ class T_pstore_io <string mnemonic, RegisterClass RC, Operand ImmOp, let Inst{1-0} = src1; } -let isExtendable = 1, isNVStorable = 1, hasSideEffects = 0 in +let isExtendable = 1, hasSideEffects = 0 in multiclass ST_Idxd<string mnemonic, string CextOp, RegisterClass RC, Operand ImmOp, Operand predImmOp, bits<3> MajOp, bit isH = 0> { let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed in { @@ -3665,7 +3668,7 @@ def S2_allocframe: ST0Inst < // S2_storer[bhwdf]_pci: Store byte/half/word/double. // S2_storer[bhwdf]_pci -> S2_storerbnew_pci -let Uses = [CS], isNVStorable = 1 in +let Uses = [CS] in class T_store_pci <string mnemonic, RegisterClass RC, Operand Imm, bits<4>MajOp, MemAccessSize AlignSize, string RegSrc = "Rt"> @@ -3679,6 +3682,8 @@ class T_store_pci <string mnemonic, RegisterClass RC, bits<1> Mu; bits<5> Rt; let accessSize = AlignSize; + let isNVStorable = !if(!eq(mnemonic,"memd"), 0, + !if(!eq(RegSrc,"Rt.h"), 0, 1)); let IClass = 0b1010; let Inst{27-25} = 0b100; @@ -3696,15 +3701,15 @@ class T_store_pci <string mnemonic, RegisterClass RC, } def S2_storerb_pci : T_store_pci<"memb", IntRegs, s4_0Imm, 0b1000, - ByteAccess>; + ByteAccess>; def S2_storerh_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1010, - HalfWordAccess>; + HalfWordAccess>; def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011, - HalfWordAccess, "Rt.h">; + HalfWordAccess, "Rt.h">; def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100, - WordAccess>; + WordAccess>; def S2_storerd_pci : T_store_pci<"memd", DoubleRegs, s4_3Imm, 0b1110, - DoubleWordAccess>; + DoubleWordAccess>; let Uses = [CS], isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 4 in class T_storenew_pci <string mnemonic, Operand Imm, @@ -3762,7 +3767,7 @@ def S2_storerd_pci_pseudo : T_store_pci_pseudo <"memd", DoubleRegs>; //===----------------------------------------------------------------------===// // Circular stores with auto-increment register //===----------------------------------------------------------------------===// -let Uses = [CS], isNVStorable = 1 in +let Uses = [CS] in class T_store_pcr <string mnemonic, RegisterClass RC, bits<4>MajOp, MemAccessSize AlignSize, string RegSrc = "Rt"> : STInst <(outs IntRegs:$_dst_), @@ -3775,6 +3780,8 @@ class T_store_pcr <string mnemonic, RegisterClass RC, bits<4>MajOp, bits<5> Rt; let accessSize = AlignSize; + let isNVStorable = !if(!eq(mnemonic,"memd"), 0, + !if(!eq(RegSrc,"Rt.h"), 0, 1)); let IClass = 0b1010; let Inst{27-25} = 0b100; @@ -5784,7 +5791,19 @@ include "HexagonInstrInfoV5.td" //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// +// V60 Instructions + +//===----------------------------------------------------------------------===// + +include "HexagonInstrInfoV60.td" + +//===----------------------------------------------------------------------===// +// V60 Instructions - +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// // ALU32/64/Vector + //===----------------------------------------------------------------------===/// include "HexagonInstrInfoVector.td" + +include "HexagonInstrAlias.td" |