diff options
Diffstat (limited to 'contrib/binutils/opcodes')
| -rw-r--r-- | contrib/binutils/opcodes/acconfig.h | 6 | ||||
| -rw-r--r-- | contrib/binutils/opcodes/arc-dis.c | 268 | ||||
| -rw-r--r-- | contrib/binutils/opcodes/arc-opc.c | 1131 | ||||
| -rw-r--r-- | contrib/binutils/opcodes/cgen-asm.c | 359 | ||||
| -rw-r--r-- | contrib/binutils/opcodes/cgen-dis.c | 226 | ||||
| -rw-r--r-- | contrib/binutils/opcodes/cgen-opc.c | 621 | ||||
| -rw-r--r-- | contrib/binutils/opcodes/sh-dis.c | 734 | ||||
| -rw-r--r-- | contrib/binutils/opcodes/sh-opc.h | 830 |
8 files changed, 0 insertions, 4175 deletions
diff --git a/contrib/binutils/opcodes/acconfig.h b/contrib/binutils/opcodes/acconfig.h deleted file mode 100644 index ef2f4966c1bd..000000000000 --- a/contrib/binutils/opcodes/acconfig.h +++ /dev/null @@ -1,6 +0,0 @@ - -/* Name of package. */ -#undef PACKAGE - -/* Version of package. */ -#undef VERSION diff --git a/contrib/binutils/opcodes/arc-dis.c b/contrib/binutils/opcodes/arc-dis.c deleted file mode 100644 index 03f13795275e..000000000000 --- a/contrib/binutils/opcodes/arc-dis.c +++ /dev/null @@ -1,268 +0,0 @@ -/* Instruction printing code for the ARC. - Copyright (C) 1994, 1995, 1997, 1998 Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include "dis-asm.h" -#include "opcode/arc.h" -#include "elf-bfd.h" -#include "elf/arc.h" -#include "opintl.h" - -static int print_insn_arc_base_little PARAMS ((bfd_vma, disassemble_info *)); -static int print_insn_arc_base_big PARAMS ((bfd_vma, disassemble_info *)); - -static int print_insn PARAMS ((bfd_vma, disassemble_info *, int, int)); - -/* Print one instruction from PC on INFO->STREAM. - Return the size of the instruction (4 or 8 for the ARC). */ - -static int -print_insn (pc, info, mach, big_p) - bfd_vma pc; - disassemble_info *info; - int mach; - int big_p; -{ - const struct arc_opcode *opcode; - bfd_byte buffer[4]; - void *stream = info->stream; - fprintf_ftype func = info->fprintf_func; - int status; - /* First element is insn, second element is limm (if present). */ - arc_insn insn[2]; - int got_limm_p = 0; - static int initialized = 0; - static int current_mach = 0; - - if (!initialized || mach != current_mach) - { - initialized = 1; - current_mach = arc_get_opcode_mach (mach, big_p); - arc_opcode_init_tables (current_mach); - } - - status = (*info->read_memory_func) (pc, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - if (big_p) - insn[0] = bfd_getb32 (buffer); - else - insn[0] = bfd_getl32 (buffer); - - (*func) (stream, "%08lx\t", insn[0]); - - /* The instructions are stored in lists hashed by the insn code - (though we needn't care how they're hashed). */ - - opcode = arc_opcode_lookup_dis (insn[0]); - for ( ; opcode != NULL; opcode = ARC_OPCODE_NEXT_DIS (opcode)) - { - char *syn; - int mods,invalid; - long value; - const struct arc_operand *operand; - const struct arc_operand_value *opval; - - /* Basic bit mask must be correct. */ - if ((insn[0] & opcode->mask) != opcode->value) - continue; - - /* Supported by this cpu? */ - if (! arc_opcode_supported (opcode)) - continue; - - /* Make two passes over the operands. First see if any of them - have extraction functions, and, if they do, make sure the - instruction is valid. */ - - arc_opcode_init_extract (); - invalid = 0; - - /* ??? Granted, this is slower than the `ppc' way. Maybe when this is - done it'll be clear what the right way to do this is. */ - /* Instructions like "add.f r0,r1,1" are tricky because the ".f" gets - printed first, but we don't know how to print it until we've processed - the regs. Since we're scanning all the args before printing the insn - anyways, it's actually quite easy. */ - - for (syn = opcode->syntax; *syn; ++syn) - { - int c; - - if (*syn != '%' || *++syn == '%') - continue; - mods = 0; - c = *syn; - while (ARC_MOD_P (arc_operands[arc_operand_map[c]].flags)) - { - mods |= arc_operands[arc_operand_map[c]].flags & ARC_MOD_BITS; - ++syn; - c = *syn; - } - operand = arc_operands + arc_operand_map[c]; - if (operand->extract) - (*operand->extract) (insn, operand, mods, - (const struct arc_operand_value **) NULL, - &invalid); - } - if (invalid) - continue; - - /* The instruction is valid. */ - - /* If we have an insn with a limm, fetch it now. Scanning the insns - twice lets us do this. */ - if (arc_opcode_limm_p (NULL)) - { - status = (*info->read_memory_func) (pc + 4, buffer, 4, info); - if (status != 0) - { - (*info->memory_error_func) (status, pc, info); - return -1; - } - if (big_p) - insn[1] = bfd_getb32 (buffer); - else - insn[1] = bfd_getl32 (buffer); - got_limm_p = 1; - } - - for (syn = opcode->syntax; *syn; ++syn) - { - int c; - - if (*syn != '%' || *++syn == '%') - { - (*func) (stream, "%c", *syn); - continue; - } - - /* We have an operand. Fetch any special modifiers. */ - mods = 0; - c = *syn; - while (ARC_MOD_P (arc_operands[arc_operand_map[c]].flags)) - { - mods |= arc_operands[arc_operand_map[c]].flags & ARC_MOD_BITS; - ++syn; - c = *syn; - } - operand = arc_operands + arc_operand_map[c]; - - /* Extract the value from the instruction. */ - opval = NULL; - if (operand->extract) - { - value = (*operand->extract) (insn, operand, mods, - &opval, (int *) NULL); - } - else - { - value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); - if ((operand->flags & ARC_OPERAND_SIGNED) - && (value & (1 << (operand->bits - 1)))) - value -= 1 << operand->bits; - - /* If this is a suffix operand, set `opval'. */ - if (operand->flags & ARC_OPERAND_SUFFIX) - opval = arc_opcode_lookup_suffix (operand, value); - } - - /* Print the operand as directed by the flags. */ - if (operand->flags & ARC_OPERAND_FAKE) - ; /* nothing to do (??? at least not yet) */ - else if (operand->flags & ARC_OPERAND_SUFFIX) - { - /* Default suffixes aren't printed. Fortunately, they all have - zero values. Also, zero values for boolean suffixes are - represented by the absence of text. */ - - if (value != 0) - { - /* ??? OPVAL should have a value. If it doesn't just cope - as we want disassembly to be reasonably robust. - Also remember that several condition code values (16-31) - aren't defined yet. For these cases just print the - number suitably decorated. */ - if (opval) - (*func) (stream, "%s%s", - mods & ARC_MOD_DOT ? "." : "", - opval->name); - else - (*func) (stream, "%s%c%d", - mods & ARC_MOD_DOT ? "." : "", - operand->fmt, value); - } - } - else if (operand->flags & ARC_OPERAND_RELATIVE_BRANCH) - (*info->print_address_func) (pc + 4 + value, info); - /* ??? Not all cases of this are currently caught. */ - else if (operand->flags & ARC_OPERAND_ABSOLUTE_BRANCH) - (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); - else if (operand->flags & ARC_OPERAND_ADDRESS) - (*info->print_address_func) ((bfd_vma) value & 0xffffffff, info); - else if (opval) - /* Note that this case catches both normal and auxiliary regs. */ - (*func) (stream, "%s", opval->name); - else - (*func) (stream, "%ld", value); - } - - /* We have found and printed an instruction; return. */ - return got_limm_p ? 8 : 4; - } - - (*func) (stream, _("*unknown*")); - return 4; -} - -/* Given MACH, one of bfd_mach_arc_xxx, return the print_insn function to use. - This does things a non-standard way (the "standard" way would be to copy - this code into disassemble.c). Since there are more than a couple of - variants, hiding all this crud here seems cleaner. */ - -disassembler_ftype -arc_get_disassembler (mach, big_p) - int mach; - int big_p; -{ - switch (mach) - { - case bfd_mach_arc_base: - return big_p ? print_insn_arc_base_big : print_insn_arc_base_little; - } - return print_insn_arc_base_little; -} - -static int -print_insn_arc_base_little (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - return print_insn (pc, info, bfd_mach_arc_base, 0); -} - -static int -print_insn_arc_base_big (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - return print_insn (pc, info, bfd_mach_arc_base, 1); -} diff --git a/contrib/binutils/opcodes/arc-opc.c b/contrib/binutils/opcodes/arc-opc.c deleted file mode 100644 index f17ffc086fe9..000000000000 --- a/contrib/binutils/opcodes/arc-opc.c +++ /dev/null @@ -1,1131 +0,0 @@ -/* Opcode table for the ARC. - Copyright (c) 1994, 1995, 1997, 1998 Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include <stdio.h> -#include "sysdep.h" -#include "opcode/arc.h" -#include "opintl.h" - -#ifndef NULL -#define NULL 0 -#endif - -#define INSERT_FN(fn) \ -static arc_insn fn PARAMS ((arc_insn, const struct arc_operand *, \ - int, const struct arc_operand_value *, long, \ - const char **)) -#define EXTRACT_FN(fn) \ -static long fn PARAMS ((arc_insn *, const struct arc_operand *, \ - int, const struct arc_operand_value **, int *)) - -INSERT_FN (insert_reg); -INSERT_FN (insert_shimmfinish); -INSERT_FN (insert_limmfinish); -INSERT_FN (insert_shimmoffset); -INSERT_FN (insert_shimmzero); -INSERT_FN (insert_flag); -INSERT_FN (insert_flagfinish); -INSERT_FN (insert_cond); -INSERT_FN (insert_forcelimm); -INSERT_FN (insert_reladdr); -INSERT_FN (insert_absaddr); -INSERT_FN (insert_unopmacro); - -EXTRACT_FN (extract_reg); -EXTRACT_FN (extract_flag); -EXTRACT_FN (extract_cond); -EXTRACT_FN (extract_reladdr); -EXTRACT_FN (extract_unopmacro); - -/* Various types of ARC operands, including insn suffixes. */ - -/* Insn format values: - - 'a' REGA register A field - 'b' REGB register B field - 'c' REGC register C field - 'S' SHIMMFINISH finish inserting a shimm value - 'L' LIMMFINISH finish inserting a limm value - 'd' SHIMMOFFSET shimm offset in ld,st insns - '0' SHIMMZERO 0 shimm value in ld,st insns - 'f' FLAG F flag - 'F' FLAGFINISH finish inserting the F flag - 'G' FLAGINSN insert F flag in "flag" insn - 'n' DELAY N field (nullify field) - 'q' COND condition code field - 'Q' FORCELIMM set `cond_p' to 1 to ensure a constant is a limm - 'B' BRANCH branch address (22 bit pc relative) - 'J' JUMP jump address (26 bit absolute) - 'z' SIZE1 size field in ld a,[b,c] - 'Z' SIZE10 size field in ld a,[b,shimm] - 'y' SIZE22 size field in st c,[b,shimm] - 'x' SIGN0 sign extend field ld a,[b,c] - 'X' SIGN9 sign extend field ld a,[b,shimm] - 'w' ADDRESS3 write-back field in ld a,[b,c] - 'W' ADDRESS12 write-back field in ld a,[b,shimm] - 'v' ADDRESS24 write-back field in st c,[b,shimm] - 'e' CACHEBYPASS5 cache bypass in ld a,[b,c] - 'E' CACHEBYPASS14 cache bypass in ld a,[b,shimm] - 'D' CACHEBYPASS26 cache bypass in st c,[b,shimm] - 'U' UNOPMACRO fake operand to copy REGB to REGC for unop macros - - The following modifiers may appear between the % and char (eg: %.f): - - '.' MODDOT '.' prefix must be present - 'r' REG generic register value, for register table - 'A' AUXREG auxiliary register in lr a,[b], sr c,[b] - - Fields are: - - CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN -*/ - -const struct arc_operand arc_operands[] = -{ -/* place holder (??? not sure if needed) */ -#define UNUSED 0 - { 0 }, - -/* register A or shimm/limm indicator */ -#define REGA (UNUSED + 1) - { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED, insert_reg, extract_reg }, - -/* register B or shimm/limm indicator */ -#define REGB (REGA + 1) - { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED, insert_reg, extract_reg }, - -/* register C or shimm/limm indicator */ -#define REGC (REGB + 1) - { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED, insert_reg, extract_reg }, - -/* fake operand used to insert shimm value into most instructions */ -#define SHIMMFINISH (REGC + 1) - { 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 }, - -/* fake operand used to insert limm value into most instructions. */ -#define LIMMFINISH (SHIMMFINISH + 1) - { 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 }, - -/* shimm operand when there is no reg indicator (ld,st) */ -#define SHIMMOFFSET (LIMMFINISH + 1) - { 'd', 9, 0, ARC_OPERAND_SIGNED, insert_shimmoffset, 0 }, - -/* 0 shimm operand for ld,st insns */ -#define SHIMMZERO (SHIMMOFFSET + 1) - { '0', 9, 0, ARC_OPERAND_FAKE, insert_shimmzero, 0 }, - -/* flag update bit (insertion is defered until we know how) */ -#define FLAG (SHIMMZERO + 1) - { 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag }, - -/* fake utility operand to finish 'f' suffix handling */ -#define FLAGFINISH (FLAG + 1) - { 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 }, - -/* fake utility operand to set the 'f' flag for the "flag" insn */ -#define FLAGINSN (FLAGFINISH + 1) - { 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 }, - -/* branch delay types */ -#define DELAY (FLAGINSN + 1) - { 'n', 2, 5, ARC_OPERAND_SUFFIX }, - -/* conditions */ -#define COND (DELAY + 1) - { 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond }, - -/* set `cond_p' to 1 to ensure a constant is treated as a limm */ -#define FORCELIMM (COND + 1) - { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm }, - -/* branch address; b, bl, and lp insns */ -#define BRANCH (FORCELIMM + 1) - { 'B', 20, 7, ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED, insert_reladdr, extract_reladdr }, - -/* jump address; j insn (this is basically the same as 'L' except that the - value is right shifted by 2) */ -#define JUMP (BRANCH + 1) - { 'J', 24, 32, ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_absaddr }, - -/* size field, stored in bit 1,2 */ -#define SIZE1 (JUMP + 1) - { 'z', 2, 1, ARC_OPERAND_SUFFIX }, - -/* size field, stored in bit 10,11 */ -#define SIZE10 (SIZE1 + 1) - { 'Z', 2, 10, ARC_OPERAND_SUFFIX, }, - -/* size field, stored in bit 22,23 */ -#define SIZE22 (SIZE10 + 1) - { 'y', 2, 22, ARC_OPERAND_SUFFIX, }, - -/* sign extend field, stored in bit 0 */ -#define SIGN0 (SIZE22 + 1) - { 'x', 1, 0, ARC_OPERAND_SUFFIX }, - -/* sign extend field, stored in bit 9 */ -#define SIGN9 (SIGN0 + 1) - { 'X', 1, 9, ARC_OPERAND_SUFFIX }, - -/* address write back, stored in bit 3 */ -#define ADDRESS3 (SIGN9 + 1) - { 'w', 1, 3, ARC_OPERAND_SUFFIX }, - -/* address write back, stored in bit 12 */ -#define ADDRESS12 (ADDRESS3 + 1) - { 'W', 1, 12, ARC_OPERAND_SUFFIX }, - -/* address write back, stored in bit 24 */ -#define ADDRESS24 (ADDRESS12 + 1) - { 'v', 1, 24, ARC_OPERAND_SUFFIX }, - -/* cache bypass, stored in bit 5 */ -#define CACHEBYPASS5 (ADDRESS24 + 1) - { 'e', 1, 5, ARC_OPERAND_SUFFIX }, - -/* cache bypass, stored in bit 14 */ -#define CACHEBYPASS14 (CACHEBYPASS5 + 1) - { 'E', 1, 14, ARC_OPERAND_SUFFIX }, - -/* cache bypass, stored in bit 26 */ -#define CACHEBYPASS26 (CACHEBYPASS14 + 1) - { 'D', 1, 26, ARC_OPERAND_SUFFIX }, - -/* unop macro, used to copy REGB to REGC */ -#define UNOPMACRO (CACHEBYPASS26 + 1) - { 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro }, - -/* '.' modifier ('.' required). */ -#define MODDOT (UNOPMACRO + 1) - { '.', 1, 0, ARC_MOD_DOT }, - -/* Dummy 'r' modifier for the register table. - It's called a "dummy" because there's no point in inserting an 'r' into all - the %a/%b/%c occurrences in the insn table. */ -#define REG (MODDOT + 1) - { 'r', 6, 0, ARC_MOD_REG }, - -/* Known auxiliary register modifier (stored in shimm field). */ -#define AUXREG (REG + 1) - { 'A', 9, 0, ARC_MOD_AUXREG }, - -/* end of list place holder */ - { 0 } -}; - -/* Given a format letter, yields the index into `arc_operands'. - eg: arc_operand_map['a'] = REGA. */ -unsigned char arc_operand_map[256]; - -#define I(x) (((x) & 31) << 27) -#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA) -#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB) -#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC) -#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */ - -/* ARC instructions. - - Longer versions of insns must appear before shorter ones (if gas sees - "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is - junk). This isn't necessary for `ld' because of the trailing ']'. - - Instructions that are really macros based on other insns must appear - before the real insn so they're chosen when disassembling. Eg: The `mov' - insn is really the `and' insn. - - This table is best viewed on a wide screen (161 columns). I'd prefer to - keep it this way. The rest of the file, however, should be viewable on an - 80 column terminal. */ - -/* ??? This table also includes macros: asl, lsl, and mov. The ppc port has - a more general facility for dealing with macros which could be used if - we need to. */ - -/* This table can't be `const' because members `next_asm' and `next_dis' are - computed at run-time. We could split this into two, but that doesn't seem - worth it. */ - -struct arc_opcode arc_opcodes[] = { - - /* Macros appear first. */ - /* "mov" is really an "and". */ - { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12) }, - /* "asl" is really an "add". */ - { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) }, - /* "lsl" is really an "add". */ - { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) }, - /* "nop" is really an "xor". */ - { "nop", 0xffffffff, 0x7fffffff }, - /* "rlc" is really an "adc". */ - { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9) }, - - /* The rest of these needn't be sorted, but it helps to find them if they are. */ - { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9) }, - { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8) }, - { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12) }, - { "asr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(1) }, - { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14) }, - { "b%q%.n %B", I(-1), I(4), ARC_OPCODE_COND_BRANCH }, - { "bl%q%.n %B", I(-1), I(5), ARC_OPCODE_COND_BRANCH }, - { "extb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(7) }, - { "extw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(8) }, - { "flag%.q %b%G%S%L", I(-1)+A(-1)+C(-1), I(3)+A(ARC_REG_SHIMM_UPDATE)+C(0) }, - /* %Q: force cond_p=1 --> no shimm values */ - /* ??? This insn allows an optional flags spec. */ - { "j%q%Q%.n%.f %b%J", I(-1)+A(-1)+C(-1)+R(-1,7,1), I(7)+A(0)+C(0)+R(0,7,1) }, - /* Put opcode 1 ld insns first so shimm gets prefered over limm. */ - /* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */ - { "ld%Z%.X%.W%.E %0%a,[%b]%L", I(-1)+R(-1,13,1)+R(-1,0,511), I(1)+R(0,13,1)+R(0,0,511) }, - { "ld%Z%.X%.W%.E %a,[%b,%d]%S%L", I(-1)+R(-1,13,1), I(1)+R(0,13,1) }, - { "ld%z%.x%.w%.e%Q %a,[%b,%c]%L", I(-1)+R(-1,4,1)+R(-1,6,7), I(0)+R(0,4,1)+R(0,6,7) }, - { "lp%q%.n %B", I(-1), I(6), }, - { "lr %a,[%Ab]%S%L", I(-1)+C(-1), I(1)+C(0x10) }, - { "lsr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(2) }, - { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13) }, - { "ror%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(3) }, - { "rrc%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(4) }, - { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11) }, - { "sexb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(5) }, - { "sexw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(6) }, - { "sr %c,[%Ab]%S%L", I(-1)+A(-1), I(2)+A(0x10) }, - /* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */ - { "st%y%.v%.D%Q %0%c,[%b]%L", I(-1)+R(-1,25,1)+R(-1,21,1)+R(-1,0,511), I(2)+R(0,25,1)+R(0,21,1)+R(0,0,511) }, - { "st%y%.v%.D %c,[%b,%d]%S%L", I(-1)+R(-1,25,1)+R(-1,21,1), I(2)+R(0,25,1)+R(0,21,1) }, - { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10) }, - { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15) } -}; -const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]); - -const struct arc_operand_value arc_reg_names[] = -{ - /* Sort this so that the first 61 entries are sequential. - IE: For each i (i<61), arc_reg_names[i].value == i. */ - - { "r0", 0, REG }, { "r1", 1, REG }, { "r2", 2, REG }, { "r3", 3, REG }, - { "r4", 4, REG }, { "r5", 5, REG }, { "r6", 6, REG }, { "r7", 7, REG }, - { "r8", 8, REG }, { "r9", 9, REG }, { "r10", 10, REG }, { "r11", 11, REG }, - { "r12", 12, REG }, { "r13", 13, REG }, { "r14", 14, REG }, { "r15", 15, REG }, - { "r16", 16, REG }, { "r17", 17, REG }, { "r18", 18, REG }, { "r19", 19, REG }, - { "r20", 20, REG }, { "r21", 21, REG }, { "r22", 22, REG }, { "r23", 23, REG }, - { "r24", 24, REG }, { "r25", 25, REG }, { "r26", 26, REG }, { "fp", 27, REG }, - { "sp", 28, REG }, { "ilink1", 29, REG }, { "ilink2", 30, REG }, { "blink", 31, REG }, - { "r32", 32, REG }, { "r33", 33, REG }, { "r34", 34, REG }, { "r35", 35, REG }, - { "r36", 36, REG }, { "r37", 37, REG }, { "r38", 38, REG }, { "r39", 39, REG }, - { "r40", 40, REG }, { "r41", 41, REG }, { "r42", 42, REG }, { "r43", 43, REG }, - { "r44", 44, REG }, { "r45", 45, REG }, { "r46", 46, REG }, { "r47", 47, REG }, - { "r48", 48, REG }, { "r49", 49, REG }, { "r50", 50, REG }, { "r51", 51, REG }, - { "r52", 52, REG }, { "r53", 53, REG }, { "r54", 54, REG }, { "r55", 55, REG }, - { "r56", 56, REG }, { "r57", 57, REG }, { "r58", 58, REG }, { "r59", 59, REG }, - { "lp_count", 60, REG }, - - /* I'd prefer to output these as "fp" and "sp" by default, but we still need - to recognize the canonical values. */ - { "r27", 27, REG }, { "r28", 28, REG }, - - /* Someone may wish to refer to these in this way, and it's probably a - good idea to reserve them as such anyway. */ - { "r29", 29, REG }, { "r30", 30, REG }, { "r31", 31, REG }, { "r60", 60, REG }, - - /* Standard auxiliary registers. */ - { "status", 0, AUXREG }, - { "semaphore", 1, AUXREG }, - { "lp_start", 2, AUXREG }, - { "lp_end", 3, AUXREG }, - { "identity", 4, AUXREG }, - { "debug", 5, AUXREG }, -}; -const int arc_reg_names_count = sizeof (arc_reg_names) / sizeof (arc_reg_names[0]); - -/* The suffix table. - Operands with the same name must be stored together. */ - -const struct arc_operand_value arc_suffixes[] = -{ - /* Entry 0 is special, default values aren't printed by the disassembler. */ - { "", 0, -1 }, - { "al", 0, COND }, - { "ra", 0, COND }, - { "eq", 1, COND }, - { "z", 1, COND }, - { "ne", 2, COND }, - { "nz", 2, COND }, - { "p", 3, COND }, - { "pl", 3, COND }, - { "n", 4, COND }, - { "mi", 4, COND }, - { "c", 5, COND }, - { "cs", 5, COND }, - { "lo", 5, COND }, - { "nc", 6, COND }, - { "cc", 6, COND }, - { "hs", 6, COND }, - { "v", 7, COND }, - { "vs", 7, COND }, - { "nv", 8, COND }, - { "vc", 8, COND }, - { "gt", 9, COND }, - { "ge", 10, COND }, - { "lt", 11, COND }, - { "le", 12, COND }, - { "hi", 13, COND }, - { "ls", 14, COND }, - { "pnz", 15, COND }, - { "f", 1, FLAG }, - { "nd", ARC_DELAY_NONE, DELAY }, - { "d", ARC_DELAY_NORMAL, DELAY }, - { "jd", ARC_DELAY_JUMP, DELAY }, -/*{ "b", 7, SIZEEXT },*/ -/*{ "b", 5, SIZESEX },*/ - { "b", 1, SIZE1 }, - { "b", 1, SIZE10 }, - { "b", 1, SIZE22 }, -/*{ "w", 8, SIZEEXT },*/ -/*{ "w", 6, SIZESEX },*/ - { "w", 2, SIZE1 }, - { "w", 2, SIZE10 }, - { "w", 2, SIZE22 }, - { "x", 1, SIGN0 }, - { "x", 1, SIGN9 }, - { "a", 1, ADDRESS3 }, - { "a", 1, ADDRESS12 }, - { "a", 1, ADDRESS24 }, - { "di", 1, CACHEBYPASS5 }, - { "di", 1, CACHEBYPASS14 }, - { "di", 1, CACHEBYPASS26 }, -}; -const int arc_suffixes_count = sizeof (arc_suffixes) / sizeof (arc_suffixes[0]); - -/* Indexed by first letter of opcode. Points to chain of opcodes with same - first letter. */ -static struct arc_opcode *opcode_map[26 + 1]; - -/* Indexed by insn code. Points to chain of opcodes with same insn code. */ -static struct arc_opcode *icode_map[32]; - -/* Configuration flags. */ - -/* Various ARC_HAVE_XXX bits. */ -static int cpu_type; - -/* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value. */ - -int -arc_get_opcode_mach (bfd_mach, big_p) - int bfd_mach, big_p; -{ - static int mach_type_map[] = - { - ARC_MACH_BASE - }; - - return mach_type_map[bfd_mach] | (big_p ? ARC_MACH_BIG : 0); -} - -/* Initialize any tables that need it. - Must be called once at start up (or when first needed). - - FLAGS is a set of bits that say what version of the cpu we have, - and in particular at least (one of) ARC_MACH_XXX. */ - -void -arc_opcode_init_tables (flags) - int flags; -{ - static int init_p = 0; - - cpu_type = flags; - - /* We may be intentionally called more than once (for example gdb will call - us each time the user switches cpu). These tables only need to be init'd - once though. */ - /* ??? We can remove the need for arc_opcode_supported by taking it into - account here, but I'm not sure I want to do that yet (if ever). */ - if (!init_p) - { - register int i,n; - - memset (arc_operand_map, 0, sizeof (arc_operand_map)); - n = sizeof (arc_operands) / sizeof (arc_operands[0]); - for (i = 0; i < n; ++i) - arc_operand_map[arc_operands[i].fmt] = i; - - memset (opcode_map, 0, sizeof (opcode_map)); - memset (icode_map, 0, sizeof (icode_map)); - /* Scan the table backwards so macros appear at the front. */ - for (i = arc_opcodes_count - 1; i >= 0; --i) - { - int opcode_hash = ARC_HASH_OPCODE (arc_opcodes[i].syntax); - int icode_hash = ARC_HASH_ICODE (arc_opcodes[i].value); - - arc_opcodes[i].next_asm = opcode_map[opcode_hash]; - opcode_map[opcode_hash] = &arc_opcodes[i]; - - arc_opcodes[i].next_dis = icode_map[icode_hash]; - icode_map[icode_hash] = &arc_opcodes[i]; - } - - init_p = 1; - } -} - -/* Return non-zero if OPCODE is supported on the specified cpu. - Cpu selection is made when calling `arc_opcode_init_tables'. */ - -int -arc_opcode_supported (opcode) - const struct arc_opcode *opcode; -{ - if (ARC_OPCODE_CPU (opcode->flags) == 0) - return 1; - if (ARC_OPCODE_CPU (opcode->flags) & ARC_HAVE_CPU (cpu_type)) - return 1; - return 0; -} - -/* Return non-zero if OPVAL is supported on the specified cpu. - Cpu selection is made when calling `arc_opcode_init_tables'. */ - -int -arc_opval_supported (opval) - const struct arc_operand_value *opval; -{ - if (ARC_OPVAL_CPU (opval->flags) == 0) - return 1; - if (ARC_OPVAL_CPU (opval->flags) & ARC_HAVE_CPU (cpu_type)) - return 1; - return 0; -} - -/* Return the first insn in the chain for assembling INSN. */ - -const struct arc_opcode * -arc_opcode_lookup_asm (insn) - const char *insn; -{ - return opcode_map[ARC_HASH_OPCODE (insn)]; -} - -/* Return the first insn in the chain for disassembling INSN. */ - -const struct arc_opcode * -arc_opcode_lookup_dis (insn) - unsigned int insn; -{ - return icode_map[ARC_HASH_ICODE (insn)]; -} - -/* Nonzero if we've seen an 'f' suffix (in certain insns). */ -static int flag_p; - -/* Nonzero if we've finished processing the 'f' suffix. */ -static int flagshimm_handled_p; - -/* Nonzero if we've seen a 'q' suffix (condition code). */ -static int cond_p; - -/* Nonzero if we've inserted a shimm. */ -static int shimm_p; - -/* The value of the shimm we inserted (each insn only gets one but it can - appear multiple times. */ -static int shimm; - -/* Nonzero if we've inserted a limm (during assembly) or seen a limm - (during disassembly). */ -static int limm_p; - -/* The value of the limm we inserted. Each insn only gets one but it can - appear multiple times. */ -static long limm; - -/* Insertion functions. */ - -/* Called by the assembler before parsing an instruction. */ - -void -arc_opcode_init_insert () -{ - flag_p = 0; - flagshimm_handled_p = 0; - cond_p = 0; - shimm_p = 0; - limm_p = 0; -} - -/* Called by the assembler to see if the insn has a limm operand. - Also called by the disassembler to see if the insn contains a limm. */ - -int -arc_opcode_limm_p (limmp) - long *limmp; -{ - if (limmp) - *limmp = limm; - return limm_p; -} - -/* Insert a value into a register field. - If REG is NULL, then this is actually a constant. - - We must also handle auxiliary registers for lr/sr insns. */ - -static arc_insn -insert_reg (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - static char buf[100]; - - if (reg == NULL) - { - /* We have a constant that also requires a value stored in a register - field. Handle these by updating the register field and saving the - value for later handling by either %S (shimm) or %L (limm). */ - - /* Try to use a shimm value before a limm one. */ - if (ARC_SHIMM_CONST_P (value) - /* If we've seen a conditional suffix we have to use a limm. */ - && !cond_p - /* If we already have a shimm value that is different than ours - we have to use a limm. */ - && (!shimm_p || shimm == value)) - { - int marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM; - flagshimm_handled_p = 1; - shimm_p = 1; - shimm = value; - insn |= marker << operand->shift; - /* insn |= value & 511; - done later */ - } - /* We have to use a limm. If we've already seen one they must match. */ - else if (!limm_p || limm == value) - { - limm_p = 1; - limm = value; - insn |= ARC_REG_LIMM << operand->shift; - /* The constant is stored later. */ - } - else - { - *errmsg = _("unable to fit different valued constants into instruction"); - } - } - else - { - /* We have to handle both normal and auxiliary registers. */ - - if (reg->type == AUXREG) - { - if (!(mods & ARC_MOD_AUXREG)) - *errmsg = _("auxiliary register not allowed here"); - else - { - insn |= ARC_REG_SHIMM << operand->shift; - insn |= reg->value << arc_operands[reg->type].shift; - } - } - else - { - /* We should never get an invalid register number here. */ - if ((unsigned int) reg->value > 60) - { - /* xgettext:c-format */ - sprintf (buf, _("invalid register number `%d'"), reg->value); - *errmsg = buf; - } - else - insn |= reg->value << operand->shift; - } - } - - return insn; -} - -/* Called when we see an 'f' flag. */ - -static arc_insn -insert_flag (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - /* We can't store anything in the insn until we've parsed the registers. - Just record the fact that we've got this flag. `insert_reg' will use it - to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */ - flag_p = 1; - - return insn; -} - -/* Called after completely building an insn to ensure the 'f' flag gets set - properly. This is needed because we don't know how to set this flag until - we've parsed the registers. */ - -static arc_insn -insert_flagfinish (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - if (flag_p && !flagshimm_handled_p) - { - if (shimm_p) - abort (); - flagshimm_handled_p = 1; - insn |= (1 << operand->shift); - } - return insn; -} - -/* Called when we see a conditional flag (eg: .eq). */ - -static arc_insn -insert_cond (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - cond_p = 1; - insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; - return insn; -} - -/* Used in the "j" instruction to prevent constants from being interpreted as - shimm values (which the jump insn doesn't accept). This can also be used - to force the use of limm values in other situations (eg: ld r0,[foo] uses - this). - ??? The mechanism is sound. Access to it is a bit klunky right now. */ - -static arc_insn -insert_forcelimm (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - cond_p = 1; - return insn; -} - -/* Used in ld/st insns to handle the shimm offset field. */ - -static arc_insn -insert_shimmoffset (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - long minval, maxval; - static char buf[100]; - - if (reg != NULL) - { - *errmsg = "register appears where shimm value expected"; - } - else - { - /* This is *way* more general than necessary, but maybe some day it'll - be useful. */ - if (operand->flags & ARC_OPERAND_SIGNED) - { - minval = -(1 << (operand->bits - 1)); - maxval = (1 << (operand->bits - 1)) - 1; - } - else - { - minval = 0; - maxval = (1 << operand->bits) - 1; - } - if (value < minval || value > maxval) - { - /* xgettext:c-format */ - sprintf (buf, _("value won't fit in range %ld - %ld"), - minval, maxval); - *errmsg = buf; - } - else - insn |= (value & ((1 << operand->bits) - 1)) << operand->shift; - } - return insn; -} - -/* Used in ld/st insns when the shimm offset is 0. */ - -static arc_insn -insert_shimmzero (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - shimm_p = 1; - shimm = 0; - return insn; -} - -/* Called at the end of processing normal insns (eg: add) to insert a shimm - value (if present) into the insn. */ - -static arc_insn -insert_shimmfinish (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - if (shimm_p) - insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift; - return insn; -} - -/* Called at the end of processing normal insns (eg: add) to insert a limm - value (if present) into the insn. - - Note that this function is only intended to handle instructions (with 4 byte - immediate operands). It is not intended to handle data. */ - -/* ??? Actually, there's nothing for us to do as we can't call frag_more, the - caller must do that. The extract fns take a pointer to two words. The - insert fns could be converted and then we could do something useful, but - then the reloc handlers would have to know to work on the second word of - a 2 word quantity. That's too much so we don't handle them. */ - -static arc_insn -insert_limmfinish (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - if (limm_p) - ; /* nothing to do, gas does it */ - return insn; -} - -/* Called at the end of unary operand macros to copy the B field to C. */ - -static arc_insn -insert_unopmacro (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift; - return insn; -} - -/* Insert a relative address for a branch insn (b, bl, or lp). */ - -static arc_insn -insert_reladdr (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - if (value & 3) - *errmsg = _("branch address not on 4 byte boundary"); - insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift; - return insn; -} - -/* Insert a limm value as a 26 bit address right shifted 2 into the insn. - - Note that this function is only intended to handle instructions (with 4 byte - immediate operands). It is not intended to handle data. */ - -/* ??? Actually, there's nothing for us to do as we can't call frag_more, the - caller must do that. The extract fns take a pointer to two words. The - insert fns could be converted and then we could do something useful, but - then the reloc handlers would have to know to work on the second word of - a 2 word quantity. That's too much so we don't handle them. */ - -static arc_insn -insert_absaddr (insn, operand, mods, reg, value, errmsg) - arc_insn insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value *reg; - long value; - const char **errmsg; -{ - if (limm_p) - ; /* nothing to do */ - return insn; -} - -/* Extraction functions. - - The suffix extraction functions' return value is redundant since it can be - obtained from (*OPVAL)->value. However, the boolean suffixes don't have - a suffix table entry for the "false" case, so values of zero must be - obtained from the return value (*OPVAL == NULL). */ - -static const struct arc_operand_value *lookup_register (int type, long regno); - -/* Called by the disassembler before printing an instruction. */ - -void -arc_opcode_init_extract () -{ - flag_p = 0; - flagshimm_handled_p = 0; - shimm_p = 0; - limm_p = 0; -} - -/* As we're extracting registers, keep an eye out for the 'f' indicator - (ARC_REG_SHIMM_UPDATE). If we find a register (not a constant marker, - like ARC_REG_SHIMM), set OPVAL so our caller will know this is a register. - - We must also handle auxiliary registers for lr/sr insns. They are just - constants with special names. */ - -static long -extract_reg (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; - int *invalid; -{ - int regno; - long value; - - /* Get the register number. */ - regno = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); - - /* Is it a constant marker? */ - if (regno == ARC_REG_SHIMM) - { - value = insn[0] & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) - && (value & 256)) - value -= 512; - flagshimm_handled_p = 1; - } - else if (regno == ARC_REG_SHIMM_UPDATE) - { - value = insn[0] & 511; - if ((operand->flags & ARC_OPERAND_SIGNED) - && (value & 256)) - value -= 512; - flag_p = 1; - flagshimm_handled_p = 1; - } - else if (regno == ARC_REG_LIMM) - { - value = insn[1]; - limm_p = 1; - } - /* It's a register, set OPVAL (that's the only way we distinguish registers - from constants here). */ - else - { - const struct arc_operand_value *reg = lookup_register (REG, regno); - - if (reg == NULL) - abort (); - if (opval != NULL) - *opval = reg; - value = regno; - } - - /* If this field takes an auxiliary register, see if it's a known one. */ - if ((mods & ARC_MOD_AUXREG) - && ARC_REG_CONSTANT_P (regno)) - { - const struct arc_operand_value *reg = lookup_register (AUXREG, value); - - /* This is really a constant, but tell the caller it has a special - name. */ - if (reg != NULL && opval != NULL) - *opval = reg; - } - - return value; -} - -/* Return the value of the "flag update" field for shimm insns. - This value is actually stored in the register field. */ - -static long -extract_flag (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; - int *invalid; -{ - int f; - const struct arc_operand_value *val; - - if (flagshimm_handled_p) - f = flag_p != 0; - else - f = (insn[0] & (1 << operand->shift)) != 0; - - /* There is no text for zero values. */ - if (f == 0) - return 0; - - val = arc_opcode_lookup_suffix (operand, 1); - if (opval != NULL && val != NULL) - *opval = val; - return val->value; -} - -/* Extract the condition code (if it exists). - If we've seen a shimm value in this insn (meaning that the insn can't have - a condition code field), then we don't store anything in OPVAL and return - zero. */ - -static long -extract_cond (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; - int *invalid; -{ - long cond; - const struct arc_operand_value *val; - - if (flagshimm_handled_p) - return 0; - - cond = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); - val = arc_opcode_lookup_suffix (operand, cond); - - /* Ignore NULL values of `val'. Several condition code values are - reserved for extensions. */ - if (opval != NULL && val != NULL) - *opval = val; - return cond; -} - -/* Extract a branch address. - We return the value as a real address (not right shifted by 2). */ - -static long -extract_reladdr (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; - int *invalid; -{ - long addr; - - addr = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1); - if ((operand->flags & ARC_OPERAND_SIGNED) - && (addr & (1 << (operand->bits - 1)))) - addr -= 1 << operand->bits; - - return addr << 2; -} - -/* The only thing this does is set the `invalid' flag if B != C. - This is needed because the "mov" macro appears before it's real insn "and" - and we don't want the disassembler to confuse them. */ - -static long -extract_unopmacro (insn, operand, mods, opval, invalid) - arc_insn *insn; - const struct arc_operand *operand; - int mods; - const struct arc_operand_value **opval; - int *invalid; -{ - /* This misses the case where B == ARC_REG_SHIMM_UPDATE && - C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get - printed as "and"s. */ - if (((insn[0] >> ARC_SHIFT_REGB) & ARC_MASK_REG) - != ((insn[0] >> ARC_SHIFT_REGC) & ARC_MASK_REG)) - if (invalid != NULL) - *invalid = 1; - - return 0; -} - -/* Utility for the extraction functions to return the index into - `arc_suffixes'. */ - -const struct arc_operand_value * -arc_opcode_lookup_suffix (type, value) - const struct arc_operand *type; - int value; -{ - register const struct arc_operand_value *v,*end; - - /* ??? This is a little slow and can be speeded up. */ - - for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v) - if (type == &arc_operands[v->type] - && value == v->value) - return v; - return 0; -} - -static const struct arc_operand_value * -lookup_register (type, regno) - int type; - long regno; -{ - register const struct arc_operand_value *r,*end; - - if (type == REG) - return &arc_reg_names[regno]; - - /* ??? This is a little slow and can be speeded up. */ - - for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count; - r < end; ++r) - if (type == r->type && regno == r->value) - return r; - return 0; -} diff --git a/contrib/binutils/opcodes/cgen-asm.c b/contrib/binutils/opcodes/cgen-asm.c deleted file mode 100644 index 4ed69363a9db..000000000000 --- a/contrib/binutils/opcodes/cgen-asm.c +++ /dev/null @@ -1,359 +0,0 @@ -/* CGEN generic assembler support code. - - Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. - - This file is part of the GNU Binutils and GDB, the GNU debugger. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <stdio.h> -#include <ctype.h> -#include "ansidecl.h" -#include "libiberty.h" -#include "bfd.h" -#include "symcat.h" -#include "opcode/cgen.h" -#include "opintl.h" - -/* Set the cgen_parse_operand_fn callback. */ - -void -cgen_set_parse_operand_fn (cd, fn) - CGEN_CPU_DESC cd; - cgen_parse_operand_fn fn; -{ - cd->parse_operand_fn = fn; -} - -/* Called whenever starting to parse an insn. */ - -void -cgen_init_parse_operand (cd) - CGEN_CPU_DESC cd; -{ - /* This tells the callback to re-initialize. */ - (void) (* cd->parse_operand_fn) - (cd, CGEN_PARSE_OPERAND_INIT, NULL, 0, 0, NULL, NULL); -} - -/* Subroutine of build_asm_hash_table to add INSNS to the hash table. - - COUNT is the number of elements in INSNS. - ENTSIZE is sizeof (CGEN_IBASE) for the target. - ??? No longer used but leave in for now. - HTABLE points to the hash table. - HENTBUF is a pointer to sufficiently large buffer of hash entries. - The result is a pointer to the next entry to use. - - The table is scanned backwards as additions are made to the front of the - list and we want earlier ones to be prefered. */ - -static CGEN_INSN_LIST * -hash_insn_array (cd, insns, count, entsize, htable, hentbuf) - CGEN_CPU_DESC cd; - const CGEN_INSN *insns; - int count; - int entsize; - CGEN_INSN_LIST **htable; - CGEN_INSN_LIST *hentbuf; -{ - int i; - - for (i = count - 1; i >= 0; --i, ++hentbuf) - { - unsigned int hash; - const CGEN_INSN *insn = &insns[i]; - - if (! (* cd->asm_hash_p) (insn)) - continue; - hash = (* cd->asm_hash) (CGEN_INSN_MNEMONIC (insn)); - hentbuf->next = htable[hash]; - hentbuf->insn = insn; - htable[hash] = hentbuf; - } - - return hentbuf; -} - -/* Subroutine of build_asm_hash_table to add INSNS to the hash table. - This function is identical to hash_insn_array except the insns are - in a list. */ - -static CGEN_INSN_LIST * -hash_insn_list (cd, insns, htable, hentbuf) - CGEN_CPU_DESC cd; - const CGEN_INSN_LIST *insns; - CGEN_INSN_LIST **htable; - CGEN_INSN_LIST *hentbuf; -{ - const CGEN_INSN_LIST *ilist; - - for (ilist = insns; ilist != NULL; ilist = ilist->next, ++ hentbuf) - { - unsigned int hash; - - if (! (* cd->asm_hash_p) (ilist->insn)) - continue; - hash = (* cd->asm_hash) (CGEN_INSN_MNEMONIC (ilist->insn)); - hentbuf->next = htable[hash]; - hentbuf->insn = ilist->insn; - htable[hash] = hentbuf; - } - - return hentbuf; -} - -/* Build the assembler instruction hash table. */ - -static void -build_asm_hash_table (cd) - CGEN_CPU_DESC cd; -{ - int count = cgen_insn_count (cd) + cgen_macro_insn_count (cd); - CGEN_INSN_TABLE *insn_table = &cd->insn_table; - CGEN_INSN_TABLE *macro_insn_table = &cd->macro_insn_table; - unsigned int hash_size = cd->asm_hash_size; - CGEN_INSN_LIST *hash_entry_buf; - CGEN_INSN_LIST **asm_hash_table; - CGEN_INSN_LIST *asm_hash_table_entries; - - /* The space allocated for the hash table consists of two parts: - the hash table and the hash lists. */ - - asm_hash_table = (CGEN_INSN_LIST **) - xmalloc (hash_size * sizeof (CGEN_INSN_LIST *)); - memset (asm_hash_table, 0, hash_size * sizeof (CGEN_INSN_LIST *)); - asm_hash_table_entries = hash_entry_buf = (CGEN_INSN_LIST *) - xmalloc (count * sizeof (CGEN_INSN_LIST)); - - /* Add compiled in insns. - Don't include the first one as it is a reserved entry. */ - /* ??? It was the end of all hash chains, and also the special - "invalid insn" marker. May be able to do it differently now. */ - - hash_entry_buf = hash_insn_array (cd, - insn_table->init_entries + 1, - insn_table->num_init_entries - 1, - insn_table->entry_size, - asm_hash_table, hash_entry_buf); - - /* Add compiled in macro-insns. */ - - hash_entry_buf = hash_insn_array (cd, macro_insn_table->init_entries, - macro_insn_table->num_init_entries, - macro_insn_table->entry_size, - asm_hash_table, hash_entry_buf); - - /* Add runtime added insns. - Later added insns will be prefered over earlier ones. */ - - hash_entry_buf = hash_insn_list (cd, insn_table->new_entries, - asm_hash_table, hash_entry_buf); - - /* Add runtime added macro-insns. */ - - hash_insn_list (cd, macro_insn_table->new_entries, - asm_hash_table, hash_entry_buf); - - cd->asm_hash_table = asm_hash_table; - cd->asm_hash_table_entries = asm_hash_table_entries; -} - -/* Return the first entry in the hash list for INSN. */ - -CGEN_INSN_LIST * -cgen_asm_lookup_insn (cd, insn) - CGEN_CPU_DESC cd; - const char *insn; -{ - unsigned int hash; - - if (cd->asm_hash_table == NULL) - build_asm_hash_table (cd); - - hash = (* cd->asm_hash) (insn); - return cd->asm_hash_table[hash]; -} - -/* Keyword parser. - The result is NULL upon success or an error message. - If successful, *STRP is updated to point passed the keyword. - - ??? At present we have a static notion of how to pick out a keyword. - Later we can allow a target to customize this if necessary [say by - recording something in the keyword table]. */ - -const char * -cgen_parse_keyword (cd, strp, keyword_table, valuep) - CGEN_CPU_DESC cd; - const char **strp; - CGEN_KEYWORD *keyword_table; - long *valuep; -{ - const CGEN_KEYWORD_ENTRY *ke; - char buf[256]; - const char *p,*start; - - p = start = *strp; - - /* Allow any first character. - Note that this allows recognizing ",a" for the annul flag in sparc - even though "," is subsequently not a valid keyword char. */ - if (*p) - ++p; - - /* Now allow letters, digits, and _. */ - while (((p - start) < (int) sizeof (buf)) - && (isalnum ((unsigned char) *p) || *p == '_')) - ++p; - - if (p - start >= (int) sizeof (buf)) - return _("unrecognized keyword/register name"); - - memcpy (buf, start, p - start); - buf[p - start] = 0; - - ke = cgen_keyword_lookup_name (keyword_table, buf); - - if (ke != NULL) - { - *valuep = ke->value; - /* Don't advance pointer if we recognized the null keyword. */ - if (ke->name[0] != 0) - *strp = p; - return NULL; - } - - return "unrecognized keyword/register name"; -} - -/* Parse a small signed integer parser. - ??? VALUEP is not a bfd_vma * on purpose, though this is confusing. - Note that if the caller expects a bfd_vma result, it should call - cgen_parse_address. */ - -const char * -cgen_parse_signed_integer (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - long *valuep; -{ - bfd_vma value; - enum cgen_parse_operand_result result; - const char *errmsg; - - errmsg = (* cd->parse_operand_fn) - (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE, - &result, &value); - /* FIXME: Examine `result'. */ - if (!errmsg) - *valuep = value; - return errmsg; -} - -/* Parse a small unsigned integer parser. - ??? VALUEP is not a bfd_vma * on purpose, though this is confusing. - Note that if the caller expects a bfd_vma result, it should call - cgen_parse_address. */ - -const char * -cgen_parse_unsigned_integer (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; -{ - bfd_vma value; - enum cgen_parse_operand_result result; - const char *errmsg; - - errmsg = (* cd->parse_operand_fn) - (cd, CGEN_PARSE_OPERAND_INTEGER, strp, opindex, BFD_RELOC_NONE, - &result, &value); - /* FIXME: Examine `result'. */ - if (!errmsg) - *valuep = value; - return errmsg; -} - -/* Address parser. */ - -const char * -cgen_parse_address (cd, strp, opindex, opinfo, resultp, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - int opinfo; - enum cgen_parse_operand_result *resultp; - bfd_vma *valuep; -{ - bfd_vma value; - enum cgen_parse_operand_result result_type; - const char *errmsg; - - errmsg = (* cd->parse_operand_fn) - (cd, CGEN_PARSE_OPERAND_ADDRESS, strp, opindex, opinfo, - &result_type, &value); - /* FIXME: Examine `result'. */ - if (!errmsg) - { - if (resultp != NULL) - *resultp = result_type; - *valuep = value; - } - return errmsg; -} - -/* Signed integer validation routine. */ - -const char * -cgen_validate_signed_integer (value, min, max) - long value, min, max; -{ - if (value < min || value > max) - { - static char buf[100]; - - /* xgettext:c-format */ - sprintf (buf, _("operand out of range (%ld not between %ld and %ld)"), - value, min, max); - return buf; - } - - return NULL; -} - -/* Unsigned integer validation routine. - Supplying `min' here may seem unnecessary, but we also want to handle - cases where min != 0 (and max > LONG_MAX). */ - -const char * -cgen_validate_unsigned_integer (value, min, max) - unsigned long value, min, max; -{ - if (value < min || value > max) - { - static char buf[100]; - - /* xgettext:c-format */ - sprintf (buf, _("operand out of range (%lu not between %lu and %lu)"), - value, min, max); - return buf; - } - - return NULL; -} diff --git a/contrib/binutils/opcodes/cgen-dis.c b/contrib/binutils/opcodes/cgen-dis.c deleted file mode 100644 index 78b1cd90ed91..000000000000 --- a/contrib/binutils/opcodes/cgen-dis.c +++ /dev/null @@ -1,226 +0,0 @@ -/* CGEN generic disassembler support code. - - Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc. - - This file is part of the GNU Binutils and GDB, the GNU debugger. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <stdio.h> -#include "ansidecl.h" -#include "libiberty.h" -#include "bfd.h" -#include "symcat.h" -#include "opcode/cgen.h" - -/* Subroutine of build_dis_hash_table to add INSNS to the hash table. - - COUNT is the number of elements in INSNS. - ENTSIZE is sizeof (CGEN_IBASE) for the target. - ??? No longer used but leave in for now. - HTABLE points to the hash table. - HENTBUF is a pointer to sufficiently large buffer of hash entries. - The result is a pointer to the next entry to use. - - The table is scanned backwards as additions are made to the front of the - list and we want earlier ones to be prefered. */ - -static CGEN_INSN_LIST * -hash_insn_array (cd, insns, count, entsize, htable, hentbuf) - CGEN_CPU_DESC cd; - const CGEN_INSN * insns; - int count; - int entsize; - CGEN_INSN_LIST ** htable; - CGEN_INSN_LIST * hentbuf; -{ - int big_p = CGEN_CPU_ENDIAN (cd) == CGEN_ENDIAN_BIG; - int i; - - for (i = count - 1; i >= 0; --i, ++hentbuf) - { - unsigned int hash; - char buf [4]; - unsigned long value; - const CGEN_INSN *insn = &insns[i]; - - if (! (* cd->dis_hash_p) (insn)) - continue; - - /* We don't know whether the target uses the buffer or the base insn - to hash on, so set both up. */ - - value = CGEN_INSN_BASE_VALUE (insn); - switch (CGEN_INSN_MASK_BITSIZE (insn)) - { - case 8: - buf[0] = value; - break; - case 16: - if (big_p) - bfd_putb16 ((bfd_vma) value, buf); - else - bfd_putl16 ((bfd_vma) value, buf); - break; - case 32: - if (big_p) - bfd_putb32 ((bfd_vma) value, buf); - else - bfd_putl32 ((bfd_vma) value, buf); - break; - default: - abort (); - } - - hash = (* cd->dis_hash) (buf, value); - hentbuf->next = htable[hash]; - hentbuf->insn = insn; - htable[hash] = hentbuf; - } - - return hentbuf; -} - -/* Subroutine of build_dis_hash_table to add INSNS to the hash table. - This function is identical to hash_insn_array except the insns are - in a list. */ - -static CGEN_INSN_LIST * -hash_insn_list (cd, insns, htable, hentbuf) - CGEN_CPU_DESC cd; - const CGEN_INSN_LIST *insns; - CGEN_INSN_LIST **htable; - CGEN_INSN_LIST *hentbuf; -{ - int big_p = CGEN_CPU_ENDIAN (cd) == CGEN_ENDIAN_BIG; - const CGEN_INSN_LIST *ilist; - - for (ilist = insns; ilist != NULL; ilist = ilist->next, ++ hentbuf) - { - unsigned int hash; - char buf[4]; - unsigned long value; - - if (! (* cd->dis_hash_p) (ilist->insn)) - continue; - - /* We don't know whether the target uses the buffer or the base insn - to hash on, so set both up. */ - - value = CGEN_INSN_BASE_VALUE (ilist->insn); - switch (CGEN_INSN_MASK_BITSIZE (ilist->insn)) - { - case 8: - buf[0] = value; - break; - case 16: - if (big_p) - bfd_putb16 ((bfd_vma) value, buf); - else - bfd_putl16 ((bfd_vma) value, buf); - break; - case 32: - if (big_p) - bfd_putb32 ((bfd_vma) value, buf); - else - bfd_putl32 ((bfd_vma) value, buf); - break; - default: - abort (); - } - - hash = (* cd->dis_hash) (buf, value); - hentbuf->next = htable [hash]; - hentbuf->insn = ilist->insn; - htable [hash] = hentbuf; - } - - return hentbuf; -} - -/* Build the disassembler instruction hash table. */ - -static void -build_dis_hash_table (cd) - CGEN_CPU_DESC cd; -{ - int count = cgen_insn_count (cd) + cgen_macro_insn_count (cd); - CGEN_INSN_TABLE *insn_table = & cd->insn_table; - CGEN_INSN_TABLE *macro_insn_table = & cd->macro_insn_table; - unsigned int hash_size = cd->dis_hash_size; - CGEN_INSN_LIST *hash_entry_buf; - CGEN_INSN_LIST **dis_hash_table; - CGEN_INSN_LIST *dis_hash_table_entries; - - /* The space allocated for the hash table consists of two parts: - the hash table and the hash lists. */ - - dis_hash_table = (CGEN_INSN_LIST **) - xmalloc (hash_size * sizeof (CGEN_INSN_LIST *)); - memset (dis_hash_table, 0, hash_size * sizeof (CGEN_INSN_LIST *)); - dis_hash_table_entries = hash_entry_buf = (CGEN_INSN_LIST *) - xmalloc (count * sizeof (CGEN_INSN_LIST)); - - /* Add compiled in insns. - Don't include the first one as it is a reserved entry. */ - /* ??? It was the end of all hash chains, and also the special - "invalid insn" marker. May be able to do it differently now. */ - - hash_entry_buf = hash_insn_array (cd, - insn_table->init_entries + 1, - insn_table->num_init_entries - 1, - insn_table->entry_size, - dis_hash_table, hash_entry_buf); - - /* Add compiled in macro-insns. */ - - hash_entry_buf = hash_insn_array (cd, macro_insn_table->init_entries, - macro_insn_table->num_init_entries, - macro_insn_table->entry_size, - dis_hash_table, hash_entry_buf); - - /* Add runtime added insns. - Later added insns will be prefered over earlier ones. */ - - hash_entry_buf = hash_insn_list (cd, insn_table->new_entries, - dis_hash_table, hash_entry_buf); - - /* Add runtime added macro-insns. */ - - hash_insn_list (cd, macro_insn_table->new_entries, - dis_hash_table, hash_entry_buf); - - cd->dis_hash_table = dis_hash_table; - cd->dis_hash_table_entries = dis_hash_table_entries; -} - -/* Return the first entry in the hash list for INSN. */ - -CGEN_INSN_LIST * -cgen_dis_lookup_insn (cd, buf, value) - CGEN_CPU_DESC cd; - const char * buf; - CGEN_INSN_INT value; -{ - unsigned int hash; - - if (cd->dis_hash_table == NULL) - build_dis_hash_table (cd); - - hash = (* cd->dis_hash) (buf, value); - - return cd->dis_hash_table[hash]; -} diff --git a/contrib/binutils/opcodes/cgen-opc.c b/contrib/binutils/opcodes/cgen-opc.c deleted file mode 100644 index ede3adde1153..000000000000 --- a/contrib/binutils/opcodes/cgen-opc.c +++ /dev/null @@ -1,621 +0,0 @@ -/* CGEN generic opcode support. - - Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. - - This file is part of the GNU Binutils and GDB, the GNU debugger. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License along - with this program; if not, write to the Free Software Foundation, Inc., - 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <ctype.h> -#include <stdio.h> -#include "ansidecl.h" -#include "libiberty.h" -#include "bfd.h" -#include "symcat.h" -#include "opcode/cgen.h" - -static unsigned int hash_keyword_name - PARAMS ((const CGEN_KEYWORD *, const char *, int)); -static unsigned int hash_keyword_value - PARAMS ((const CGEN_KEYWORD *, unsigned int)); -static void build_keyword_hash_tables - PARAMS ((CGEN_KEYWORD *)); - -/* Return number of hash table entries to use for N elements. */ -#define KEYWORD_HASH_SIZE(n) ((n) <= 31 ? 17 : 31) - -/* Look up *NAMEP in the keyword table KT. - The result is the keyword entry or NULL if not found. */ - -const CGEN_KEYWORD_ENTRY * -cgen_keyword_lookup_name (kt, name) - CGEN_KEYWORD *kt; - const char *name; -{ - const CGEN_KEYWORD_ENTRY *ke; - const char *p,*n; - - if (kt->name_hash_table == NULL) - build_keyword_hash_tables (kt); - - ke = kt->name_hash_table[hash_keyword_name (kt, name, 0)]; - - /* We do case insensitive comparisons. - If that ever becomes a problem, add an attribute that denotes - "do case sensitive comparisons". */ - - while (ke != NULL) - { - n = name; - p = ke->name; - - while (*p - && (*p == *n - || (isalpha ((unsigned char) *p) - && (tolower ((unsigned char) *p) - == tolower ((unsigned char) *n))))) - ++n, ++p; - - if (!*p && !*n) - return ke; - - ke = ke->next_name; - } - - if (kt->null_entry) - return kt->null_entry; - return NULL; -} - -/* Look up VALUE in the keyword table KT. - The result is the keyword entry or NULL if not found. */ - -const CGEN_KEYWORD_ENTRY * -cgen_keyword_lookup_value (kt, value) - CGEN_KEYWORD *kt; - int value; -{ - const CGEN_KEYWORD_ENTRY *ke; - - if (kt->name_hash_table == NULL) - build_keyword_hash_tables (kt); - - ke = kt->value_hash_table[hash_keyword_value (kt, value)]; - - while (ke != NULL) - { - if (value == ke->value) - return ke; - ke = ke->next_value; - } - - return NULL; -} - -/* Add an entry to a keyword table. */ - -void -cgen_keyword_add (kt, ke) - CGEN_KEYWORD *kt; - CGEN_KEYWORD_ENTRY *ke; -{ - unsigned int hash; - - if (kt->name_hash_table == NULL) - build_keyword_hash_tables (kt); - - hash = hash_keyword_name (kt, ke->name, 0); - ke->next_name = kt->name_hash_table[hash]; - kt->name_hash_table[hash] = ke; - - hash = hash_keyword_value (kt, ke->value); - ke->next_value = kt->value_hash_table[hash]; - kt->value_hash_table[hash] = ke; - - if (ke->name[0] == 0) - kt->null_entry = ke; -} - -/* FIXME: Need function to return count of keywords. */ - -/* Initialize a keyword table search. - SPEC is a specification of what to search for. - A value of NULL means to find every keyword. - Currently NULL is the only acceptable value [further specification - deferred]. - The result is an opaque data item used to record the search status. - It is passed to each call to cgen_keyword_search_next. */ - -CGEN_KEYWORD_SEARCH -cgen_keyword_search_init (kt, spec) - CGEN_KEYWORD *kt; - const char *spec; -{ - CGEN_KEYWORD_SEARCH search; - - /* FIXME: Need to specify format of PARAMS. */ - if (spec != NULL) - abort (); - - if (kt->name_hash_table == NULL) - build_keyword_hash_tables (kt); - - search.table = kt; - search.spec = spec; - search.current_hash = 0; - search.current_entry = NULL; - return search; -} - -/* Return the next keyword specified by SEARCH. - The result is the next entry or NULL if there are no more. */ - -const CGEN_KEYWORD_ENTRY * -cgen_keyword_search_next (search) - CGEN_KEYWORD_SEARCH *search; -{ - /* Has search finished? */ - if (search->current_hash == search->table->hash_table_size) - return NULL; - - /* Search in progress? */ - if (search->current_entry != NULL - /* Anything left on this hash chain? */ - && search->current_entry->next_name != NULL) - { - search->current_entry = search->current_entry->next_name; - return search->current_entry; - } - - /* Move to next hash chain [unless we haven't started yet]. */ - if (search->current_entry != NULL) - ++search->current_hash; - - while (search->current_hash < search->table->hash_table_size) - { - search->current_entry = search->table->name_hash_table[search->current_hash]; - if (search->current_entry != NULL) - return search->current_entry; - ++search->current_hash; - } - - return NULL; -} - -/* Return first entry in hash chain for NAME. - If CASE_SENSITIVE_P is non-zero, return a case sensitive hash. */ - -static unsigned int -hash_keyword_name (kt, name, case_sensitive_p) - const CGEN_KEYWORD *kt; - const char *name; - int case_sensitive_p; -{ - unsigned int hash; - - if (case_sensitive_p) - for (hash = 0; *name; ++name) - hash = (hash * 97) + (unsigned char) *name; - else - for (hash = 0; *name; ++name) - hash = (hash * 97) + (unsigned char) tolower (*name); - return hash % kt->hash_table_size; -} - -/* Return first entry in hash chain for VALUE. */ - -static unsigned int -hash_keyword_value (kt, value) - const CGEN_KEYWORD *kt; - unsigned int value; -{ - return value % kt->hash_table_size; -} - -/* Build a keyword table's hash tables. - We probably needn't build the value hash table for the assembler when - we're using the disassembler, but we keep things simple. */ - -static void -build_keyword_hash_tables (kt) - CGEN_KEYWORD *kt; -{ - int i; - /* Use the number of compiled in entries as an estimate for the - typical sized table [not too many added at runtime]. */ - unsigned int size = KEYWORD_HASH_SIZE (kt->num_init_entries); - - kt->hash_table_size = size; - kt->name_hash_table = (CGEN_KEYWORD_ENTRY **) - xmalloc (size * sizeof (CGEN_KEYWORD_ENTRY *)); - memset (kt->name_hash_table, 0, size * sizeof (CGEN_KEYWORD_ENTRY *)); - kt->value_hash_table = (CGEN_KEYWORD_ENTRY **) - xmalloc (size * sizeof (CGEN_KEYWORD_ENTRY *)); - memset (kt->value_hash_table, 0, size * sizeof (CGEN_KEYWORD_ENTRY *)); - - /* The table is scanned backwards as we want keywords appearing earlier to - be prefered over later ones. */ - for (i = kt->num_init_entries - 1; i >= 0; --i) - cgen_keyword_add (kt, &kt->init_entries[i]); -} - -/* Hardware support. */ - -/* Lookup a hardware element by its name. - Returns NULL if NAME is not supported by the currently selected - mach/isa. */ - -const CGEN_HW_ENTRY * -cgen_hw_lookup_by_name (cd, name) - CGEN_CPU_DESC cd; - const char *name; -{ - int i; - const CGEN_HW_ENTRY **hw = cd->hw_table.entries; - - for (i = 0; i < cd->hw_table.num_entries; ++i) - if (hw[i] && strcmp (name, hw[i]->name) == 0) - return hw[i]; - - return NULL; -} - -/* Lookup a hardware element by its number. - Hardware elements are enumerated, however it may be possible to add some - at runtime, thus HWNUM is not an enum type but rather an int. - Returns NULL if HWNUM is not supported by the currently selected mach. */ - -const CGEN_HW_ENTRY * -cgen_hw_lookup_by_num (cd, hwnum) - CGEN_CPU_DESC cd; - int hwnum; -{ - int i; - const CGEN_HW_ENTRY **hw = cd->hw_table.entries; - - /* ??? This can be speeded up. */ - for (i = 0; i < cd->hw_table.num_entries; ++i) - if (hw[i] && hwnum == hw[i]->type) - return hw[i]; - - return NULL; -} - -/* Operand support. */ - -/* Lookup an operand by its name. - Returns NULL if NAME is not supported by the currently selected - mach/isa. */ - -const CGEN_OPERAND * -cgen_operand_lookup_by_name (cd, name) - CGEN_CPU_DESC cd; - const char *name; -{ - int i; - const CGEN_OPERAND **op = cd->operand_table.entries; - - for (i = 0; i < cd->operand_table.num_entries; ++i) - if (op[i] && strcmp (name, op[i]->name) == 0) - return op[i]; - - return NULL; -} - -/* Lookup an operand by its number. - Operands are enumerated, however it may be possible to add some - at runtime, thus OPNUM is not an enum type but rather an int. - Returns NULL if OPNUM is not supported by the currently selected - mach/isa. */ - -const CGEN_OPERAND * -cgen_operand_lookup_by_num (cd, opnum) - CGEN_CPU_DESC cd; - int opnum; -{ - return cd->operand_table.entries[opnum]; -} - -/* Instruction support. */ - -/* Return number of instructions. This includes any added at runtime. */ - -int -cgen_insn_count (cd) - CGEN_CPU_DESC cd; -{ - int count = cd->insn_table.num_init_entries; - CGEN_INSN_LIST *rt_insns = cd->insn_table.new_entries; - - for ( ; rt_insns != NULL; rt_insns = rt_insns->next) - ++count; - - return count; -} - -/* Return number of macro-instructions. - This includes any added at runtime. */ - -int -cgen_macro_insn_count (cd) - CGEN_CPU_DESC cd; -{ - int count = cd->macro_insn_table.num_init_entries; - CGEN_INSN_LIST *rt_insns = cd->macro_insn_table.new_entries; - - for ( ; rt_insns != NULL; rt_insns = rt_insns->next) - ++count; - - return count; -} - -/* Cover function to read and properly byteswap an insn value. */ - -CGEN_INSN_INT -cgen_get_insn_value (cd, buf, length) - CGEN_CPU_DESC cd; - unsigned char *buf; - int length; -{ - CGEN_INSN_INT value; - - switch (length) - { - case 8: - value = *buf; - break; - case 16: - if (cd->insn_endian == CGEN_ENDIAN_BIG) - value = bfd_getb16 (buf); - else - value = bfd_getl16 (buf); - break; - case 32: - if (cd->insn_endian == CGEN_ENDIAN_BIG) - value = bfd_getb32 (buf); - else - value = bfd_getl32 (buf); - break; - default: - abort (); - } - - return value; -} - -/* Cover function to store an insn value properly byteswapped. */ - -void -cgen_put_insn_value (cd, buf, length, value) - CGEN_CPU_DESC cd; - unsigned char *buf; - int length; - CGEN_INSN_INT value; -{ - switch (length) - { - case 8: - buf[0] = value; - break; - case 16: - if (cd->insn_endian == CGEN_ENDIAN_BIG) - bfd_putb16 (value, buf); - else - bfd_putl16 (value, buf); - break; - case 32: - if (cd->insn_endian == CGEN_ENDIAN_BIG) - bfd_putb32 (value, buf); - else - bfd_putl32 (value, buf); - break; - default: - abort (); - } -} - -/* Look up instruction INSN_*_VALUE and extract its fields. - INSN_INT_VALUE is used if CGEN_INT_INSN_P. - Otherwise INSN_BYTES_VALUE is used. - INSN, if non-null, is the insn table entry. - Otherwise INSN_*_VALUE is examined to compute it. - LENGTH is the bit length of INSN_*_VALUE if known, otherwise 0. - 0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'. - If INSN != NULL, LENGTH must be valid. - ALIAS_P is non-zero if alias insns are to be included in the search. - - The result is a pointer to the insn table entry, or NULL if the instruction - wasn't recognized. */ - -/* ??? Will need to be revisited for VLIW architectures. */ - -const CGEN_INSN * -cgen_lookup_insn (cd, insn, insn_int_value, insn_bytes_value, length, fields, - alias_p) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - CGEN_INSN_INT insn_int_value; - /* ??? CGEN_INSN_BYTES would be a nice type name to use here. */ - unsigned char *insn_bytes_value; - int length; - CGEN_FIELDS *fields; - int alias_p; -{ - unsigned char *buf; - CGEN_INSN_INT base_insn; - CGEN_EXTRACT_INFO ex_info; - CGEN_EXTRACT_INFO *info; - - if (cd->int_insn_p) - { - info = NULL; - buf = (unsigned char *) alloca (cd->max_insn_bitsize / 8); - cgen_put_insn_value (cd, buf, length, insn_int_value); - base_insn = insn_int_value; - } - else - { - info = &ex_info; - ex_info.dis_info = NULL; - ex_info.insn_bytes = insn_bytes_value; - ex_info.valid = -1; - buf = insn_bytes_value; - base_insn = cgen_get_insn_value (cd, buf, length); - } - - if (!insn) - { - const CGEN_INSN_LIST *insn_list; - - /* The instructions are stored in hash lists. - Pick the first one and keep trying until we find the right one. */ - - insn_list = cgen_dis_lookup_insn (cd, buf, base_insn); - while (insn_list != NULL) - { - insn = insn_list->insn; - - if (alias_p - /* FIXME: Ensure ALIAS attribute always has same index. */ - || ! CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ALIAS)) - { - /* Basic bit mask must be correct. */ - /* ??? May wish to allow target to defer this check until the - extract handler. */ - if ((base_insn & CGEN_INSN_BASE_MASK (insn)) - == CGEN_INSN_BASE_VALUE (insn)) - { - /* ??? 0 is passed for `pc' */ - int elength = CGEN_EXTRACT_FN (cd, insn) - (cd, insn, info, base_insn, fields, (bfd_vma) 0); - if (elength > 0) - { - /* sanity check */ - if (length != 0 && length != elength) - abort (); - return insn; - } - } - } - - insn_list = insn_list->next; - } - } - else - { - /* Sanity check: can't pass an alias insn if ! alias_p. */ - if (! alias_p - && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ALIAS)) - abort (); - /* Sanity check: length must be correct. */ - if (length != CGEN_INSN_BITSIZE (insn)) - abort (); - - /* ??? 0 is passed for `pc' */ - length = CGEN_EXTRACT_FN (cd, insn) - (cd, insn, info, base_insn, fields, (bfd_vma) 0); - /* Sanity check: must succeed. - Could relax this later if it ever proves useful. */ - if (length == 0) - abort (); - return insn; - } - - return NULL; -} - -/* Fill in the operand instances used by INSN whose operands are FIELDS. - INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled - in. */ - -void -cgen_get_insn_operands (cd, insn, fields, indices) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - const CGEN_FIELDS *fields; - int *indices; -{ - const CGEN_OPINST *opinst; - int i; - - if (insn->opinst == NULL) - abort (); - for (i = 0, opinst = insn->opinst; opinst->type != CGEN_OPINST_END; ++i, ++opinst) - { - enum cgen_operand_type op_type = opinst->op_type; - if (op_type == CGEN_OPERAND_NIL) - indices[i] = opinst->index; - else - indices[i] = (*cd->get_int_operand) (cd, op_type, fields); - } -} - -/* Cover function to cgen_get_insn_operands when either INSN or FIELDS - isn't known. - The INSN, INSN_*_VALUE, and LENGTH arguments are passed to - cgen_lookup_insn unchanged. - INSN_INT_VALUE is used if CGEN_INT_INSN_P. - Otherwise INSN_BYTES_VALUE is used. - - The result is the insn table entry or NULL if the instruction wasn't - recognized. */ - -const CGEN_INSN * -cgen_lookup_get_insn_operands (cd, insn, insn_int_value, insn_bytes_value, - length, indices, fields) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - CGEN_INSN_INT insn_int_value; - /* ??? CGEN_INSN_BYTES would be a nice type name to use here. */ - unsigned char *insn_bytes_value; - int length; - int *indices; - CGEN_FIELDS *fields; -{ - /* Pass non-zero for ALIAS_P only if INSN != NULL. - If INSN == NULL, we want a real insn. */ - insn = cgen_lookup_insn (cd, insn, insn_int_value, insn_bytes_value, - length, fields, insn != NULL); - if (! insn) - return NULL; - - cgen_get_insn_operands (cd, insn, fields, indices); - return insn; -} - -/* Allow signed overflow of instruction fields. */ -void -cgen_set_signed_overflow_ok (cd) - CGEN_CPU_DESC cd; -{ - cd->signed_overflow_ok_p = 1; -} - -/* Generate an error message if a signed field in an instruction overflows. */ -void -cgen_clear_signed_overflow_ok (cd) - CGEN_CPU_DESC cd; -{ - cd->signed_overflow_ok_p = 0; -} - -/* Will an error message be generated if a signed field in an instruction overflows ? */ -unsigned int -cgen_signed_overflow_ok_p (cd) - CGEN_CPU_DESC cd; -{ - return cd->signed_overflow_ok_p; -} diff --git a/contrib/binutils/opcodes/sh-dis.c b/contrib/binutils/opcodes/sh-dis.c deleted file mode 100644 index c4e960c24e8b..000000000000 --- a/contrib/binutils/opcodes/sh-dis.c +++ /dev/null @@ -1,734 +0,0 @@ -/* Disassemble SH instructions. - Copyright (C) 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include <stdio.h> -#define STATIC_TABLE -#define DEFINE_TABLE - -#include "sh-opc.h" -#include "dis-asm.h" - -#define LITTLE_BIT 2 - -static void -print_movxy (op, rn, rm, fprintf_fn, stream) - sh_opcode_info *op; - int rn, rm; - fprintf_ftype fprintf_fn; - void *stream; -{ - int n; - - fprintf_fn (stream,"%s\t", op->name); - for (n = 0; n < 2; n++) - { - switch (op->arg[n]) - { - case A_IND_N: - fprintf_fn (stream, "@r%d", rn); - break; - case A_INC_N: - fprintf_fn (stream, "@r%d+", rn); - break; - case A_PMOD_N: - fprintf_fn (stream, "@r%d+r8", rn); - break; - case A_PMODY_N: - fprintf_fn (stream, "@r%d+r9", rn); - break; - case DSP_REG_M: - fprintf_fn (stream, "a%c", '0' + rm); - break; - case DSP_REG_X: - fprintf_fn (stream, "x%c", '0' + rm); - break; - case DSP_REG_Y: - fprintf_fn (stream, "y%c", '0' + rm); - break; - default: - abort (); - } - if (n == 0) - fprintf_fn (stream, ","); - } -} - -/* Print a double data transfer insn. INSN is just the lower three - nibbles of the insn, i.e. field a and the bit that indicates if - a parallel processing insn follows. - Return nonzero if a field b of a parallel processing insns follows. */ -static void -print_insn_ddt (insn, info) - int insn; - struct disassemble_info *info; -{ - fprintf_ftype fprintf_fn = info->fprintf_func; - void *stream = info->stream; - - /* If this is just a nop, make sure to emit something. */ - if (insn == 0x000) - fprintf_fn (stream, "nopx\tnopy"); - - /* If a parallel processing insn was printed before, - and we got a non-nop, emit a tab. */ - if ((insn & 0x800) && (insn & 0x3ff)) - fprintf_fn (stream, "\t"); - - /* Check if either the x or y part is invalid. */ - if (((insn & 0xc) == 0 && (insn & 0x2a0)) - || ((insn & 3) == 0 && (insn & 0x150))) - fprintf_fn (stream, ".word 0x%x", insn); - else - { - static sh_opcode_info *first_movx, *first_movy; - sh_opcode_info *opx, *opy; - int insn_x, insn_y; - - if (! first_movx) - { - for (first_movx = sh_table; first_movx->nibbles[1] != MOVX; ) - first_movx++; - for (first_movy = first_movx; first_movy->nibbles[1] != MOVY; ) - first_movy++; - } - insn_x = (insn >> 2) & 0xb; - if (insn_x) - { - for (opx = first_movx; opx->nibbles[2] != insn_x; ) opx++; - print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1, - fprintf_fn, stream); - } - insn_y = (insn & 3) | ((insn >> 1) & 8); - if (insn_y) - { - if (insn_x) - fprintf_fn (stream, "\t"); - for (opy = first_movy; opy->nibbles[2] != insn_y; ) opy++; - print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1, - fprintf_fn, stream); - } - } -} - -static void -print_dsp_reg (rm, fprintf_fn, stream) - int rm; - fprintf_ftype fprintf_fn; - void *stream; -{ - switch (rm) - { - case A_A1_NUM: - fprintf_fn (stream, "a1"); - break; - case A_A0_NUM: - fprintf_fn (stream, "a0"); - break; - case A_X0_NUM: - fprintf_fn (stream, "x0"); - break; - case A_X1_NUM: - fprintf_fn (stream, "x1"); - break; - case A_Y0_NUM: - fprintf_fn (stream, "y0"); - break; - case A_Y1_NUM: - fprintf_fn (stream, "y1"); - break; - case A_M0_NUM: - fprintf_fn (stream, "m0"); - break; - case A_A1G_NUM: - fprintf_fn (stream, "a1g"); - break; - case A_M1_NUM: - fprintf_fn (stream, "m1"); - break; - case A_A0G_NUM: - fprintf_fn (stream, "a0g"); - break; - default: - fprintf_fn (stream, "0x%x", rm); - break; - } -} - -static void -print_insn_ppi (field_b, info) - int field_b; - struct disassemble_info *info; -{ - static char *sx_tab[] = {"x0","x1","a0","a1"}; - static char *sy_tab[] = {"y0","y1","m0","m1"}; - fprintf_ftype fprintf_fn = info->fprintf_func; - void *stream = info->stream; - int nib1, nib2, nib3; - char *dc; - sh_opcode_info *op; - - if ((field_b & 0xe800) == 0) - { - fprintf_fn (stream, "psh%c\t#%d,", - field_b & 0x1000 ? 'a' : 'l', - (field_b >> 4) & 127); - print_dsp_reg (field_b & 0xf, fprintf_fn, stream); - return; - } - if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000) - { - static char *du_tab[] = {"x0","y0","a0","a1"}; - static char *se_tab[] = {"x0","x1","y0","a1"}; - static char *sf_tab[] = {"y0","y1","x0","a1"}; - static char *sg_tab[] = {"m0","m1","a0","a1"}; - - if (field_b & 0x2000) - { - fprintf_fn (stream, "p%s %s,%s,%s\t", - (field_b & 0x1000) ? "add" : "sub", - sx_tab[(field_b >> 6) & 3], - sy_tab[(field_b >> 4) & 3], - du_tab[(field_b >> 0) & 3]); - } - fprintf_fn (stream, "pmuls%c%s,%s,%s", - field_b & 0x2000 ? ' ' : '\t', - se_tab[(field_b >> 10) & 3], - sf_tab[(field_b >> 8) & 3], - sg_tab[(field_b >> 2) & 3]); - return; - } - - nib1 = PPIC; - nib2 = field_b >> 12 & 0xf; - nib3 = field_b >> 8 & 0xf; - switch (nib3 & 0x3) - { - case 0: - dc = ""; - nib1 = PPI3; - break; - case 1: - dc = ""; - break; - case 2: - dc = "dct "; - nib3 -= 1; - break; - case 3: - dc = "dcf "; - nib3 -= 2; - break; - } - for (op = sh_table; op->name; op++) - { - if (op->nibbles[1] == nib1 - && op->nibbles[2] == nib2 - && op->nibbles[3] == nib3) - { - int n; - - fprintf_fn (stream, "%s%s\t", dc, op->name); - for (n = 0; n < 3 && op->arg[n] != A_END; n++) - { - if (n && op->arg[1] != A_END) - fprintf_fn (stream, ","); - switch (op->arg[n]) - { - case DSP_REG_N: - print_dsp_reg (field_b & 0xf, fprintf_fn, stream); - break; - case DSP_REG_X: - fprintf_fn (stream, sx_tab[(field_b >> 6) & 3]); - break; - case DSP_REG_Y: - fprintf_fn (stream, sy_tab[(field_b >> 4) & 3]); - break; - case A_MACH: - fprintf_fn (stream, "mach"); - break; - case A_MACL: - fprintf_fn (stream ,"macl"); - break; - default: - abort (); - } - } - return; - } - } - /* Not found. */ - fprintf_fn (stream, ".word 0x%x", field_b); -} - -static int -print_insn_shx (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - fprintf_ftype fprintf_fn = info->fprintf_func; - void *stream = info->stream; - unsigned char insn[2]; - unsigned char nibs[4]; - int status; - bfd_vma relmask = ~ (bfd_vma) 0; - sh_opcode_info *op; - int target_arch; - - switch (info->mach) - { - case bfd_mach_sh: - target_arch = arch_sh1; - break; - case bfd_mach_sh2: - target_arch = arch_sh2; - break; - case bfd_mach_sh_dsp: - target_arch = arch_sh_dsp; - break; - case bfd_mach_sh3: - target_arch = arch_sh3; - break; - case bfd_mach_sh3_dsp: - target_arch = arch_sh3_dsp; - break; - case bfd_mach_sh3e: - target_arch = arch_sh3e; - break; - case bfd_mach_sh4: - target_arch = arch_sh4; - break; - default: - abort (); - } - - status = info->read_memory_func (memaddr, insn, 2, info); - - if (status != 0) - { - info->memory_error_func (status, memaddr, info); - return -1; - } - - if (info->flags & LITTLE_BIT) - { - nibs[0] = (insn[1] >> 4) & 0xf; - nibs[1] = insn[1] & 0xf; - - nibs[2] = (insn[0] >> 4) & 0xf; - nibs[3] = insn[0] & 0xf; - } - else - { - nibs[0] = (insn[0] >> 4) & 0xf; - nibs[1] = insn[0] & 0xf; - - nibs[2] = (insn[1] >> 4) & 0xf; - nibs[3] = insn[1] & 0xf; - } - - if (nibs[0] == 0xf && (nibs[1] & 4) == 0 && target_arch & arch_sh_dsp_up) - { - if (nibs[1] & 8) - { - int field_b; - - status = info->read_memory_func (memaddr + 2, insn, 2, info); - - if (status != 0) - { - info->memory_error_func (status, memaddr + 2, info); - return -1; - } - - if (info->flags & LITTLE_BIT) - field_b = insn[1] << 8 | insn[0]; - else - field_b = insn[0] << 8 | insn[1]; - - print_insn_ppi (field_b, info); - print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info); - return 4; - } - print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info); - return 2; - } - for (op = sh_table; op->name; op++) - { - int n; - int imm = 0; - int rn = 0; - int rm = 0; - int rb = 0; - int disp_pc; - bfd_vma disp_pc_addr = 0; - - if ((op->arch & target_arch) == 0) - goto fail; - for (n = 0; n < 4; n++) - { - int i = op->nibbles[n]; - - if (i < 16) - { - if (nibs[n] == i) - continue; - goto fail; - } - switch (i) - { - case BRANCH_8: - imm = (nibs[2] << 4) | (nibs[3]); - if (imm & 0x80) - imm |= ~0xff; - imm = ((char)imm) * 2 + 4 ; - goto ok; - case BRANCH_12: - imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]); - if (imm & 0x800) - imm |= ~0xfff; - imm = imm * 2 + 4; - goto ok; - case IMM_4: - imm = nibs[3]; - goto ok; - case IMM_4BY2: - imm = nibs[3] <<1; - goto ok; - case IMM_4BY4: - imm = nibs[3] <<2; - goto ok; - case IMM_8: - imm = (nibs[2] << 4) | nibs[3]; - goto ok; - case PCRELIMM_8BY2: - imm = ((nibs[2] << 4) | nibs[3]) <<1; - relmask = ~ (bfd_vma) 1; - goto ok; - case PCRELIMM_8BY4: - imm = ((nibs[2] << 4) | nibs[3]) <<2; - relmask = ~ (bfd_vma) 3; - goto ok; - case IMM_8BY2: - imm = ((nibs[2] << 4) | nibs[3]) <<1; - goto ok; - case IMM_8BY4: - imm = ((nibs[2] << 4) | nibs[3]) <<2; - goto ok; - case DISP_8: - imm = (nibs[2] << 4) | (nibs[3]); - goto ok; - case DISP_4: - imm = nibs[3]; - goto ok; - case REG_N: - rn = nibs[n]; - break; - case REG_M: - rm = nibs[n]; - break; - case REG_NM: - rn = (nibs[n] & 0xc) >> 2; - rm = (nibs[n] & 0x3); - break; - case REG_B: - rb = nibs[n] & 0x07; - break; - case SDT_REG_N: - /* sh-dsp: single data transfer. */ - rn = nibs[n]; - if ((rn & 0xc) != 4) - goto fail; - rn = rn & 0x3; - rn |= (rn & 2) << 1; - break; - case PPI: - goto fail; - default: - abort(); - } - } - - ok: - fprintf_fn (stream,"%s\t", op->name); - disp_pc = 0; - for (n = 0; n < 3 && op->arg[n] != A_END; n++) - { - if (n && op->arg[1] != A_END) - fprintf_fn (stream, ","); - switch (op->arg[n]) - { - case A_IMM: - fprintf_fn (stream, "#%d", (char)(imm)); - break; - case A_R0: - fprintf_fn (stream, "r0"); - break; - case A_REG_N: - fprintf_fn (stream, "r%d", rn); - break; - case A_INC_N: - fprintf_fn (stream, "@r%d+", rn); - break; - case A_DEC_N: - fprintf_fn (stream, "@-r%d", rn); - break; - case A_IND_N: - fprintf_fn (stream, "@r%d", rn); - break; - case A_DISP_REG_N: - fprintf_fn (stream, "@(%d,r%d)", imm, rn); - break; - case A_PMOD_N: - fprintf_fn (stream, "@r%d+r8", rn); - break; - case A_REG_M: - fprintf_fn (stream, "r%d", rm); - break; - case A_INC_M: - fprintf_fn (stream, "@r%d+", rm); - break; - case A_DEC_M: - fprintf_fn (stream, "@-r%d", rm); - break; - case A_IND_M: - fprintf_fn (stream, "@r%d", rm); - break; - case A_DISP_REG_M: - fprintf_fn (stream, "@(%d,r%d)", imm, rm); - break; - case A_REG_B: - fprintf_fn (stream, "r%d_bank", rb); - break; - case A_DISP_PC: - disp_pc = 1; - disp_pc_addr = imm + 4 + (memaddr & relmask); - (*info->print_address_func) (disp_pc_addr, info); - break; - case A_IND_R0_REG_N: - fprintf_fn (stream, "@(r0,r%d)", rn); - break; - case A_IND_R0_REG_M: - fprintf_fn (stream, "@(r0,r%d)", rm); - break; - case A_DISP_GBR: - fprintf_fn (stream, "@(%d,gbr)",imm); - break; - case A_R0_GBR: - fprintf_fn (stream, "@(r0,gbr)"); - break; - case A_BDISP12: - case A_BDISP8: - (*info->print_address_func) (imm + memaddr, info); - break; - case A_SR: - fprintf_fn (stream, "sr"); - break; - case A_GBR: - fprintf_fn (stream, "gbr"); - break; - case A_VBR: - fprintf_fn (stream, "vbr"); - break; - case A_DSR: - fprintf_fn (stream, "dsr"); - break; - case A_MOD: - fprintf_fn (stream, "mod"); - break; - case A_RE: - fprintf_fn (stream, "re"); - break; - case A_RS: - fprintf_fn (stream, "rs"); - break; - case A_A0: - fprintf_fn (stream, "a0"); - break; - case A_X0: - fprintf_fn (stream, "x0"); - break; - case A_X1: - fprintf_fn (stream, "x1"); - break; - case A_Y0: - fprintf_fn (stream, "y0"); - break; - case A_Y1: - fprintf_fn (stream, "y1"); - break; - case DSP_REG_M: - print_dsp_reg (rm, fprintf_fn, stream); - break; - case A_SSR: - fprintf_fn (stream, "ssr"); - break; - case A_SPC: - fprintf_fn (stream, "spc"); - break; - case A_MACH: - fprintf_fn (stream, "mach"); - break; - case A_MACL: - fprintf_fn (stream ,"macl"); - break; - case A_PR: - fprintf_fn (stream, "pr"); - break; - case A_SGR: - fprintf_fn (stream, "sgr"); - break; - case A_DBR: - fprintf_fn (stream, "dbr"); - break; - case F_REG_N: - fprintf_fn (stream, "fr%d", rn); - break; - case F_REG_M: - fprintf_fn (stream, "fr%d", rm); - break; - case DX_REG_N: - if (rn & 1) - { - fprintf_fn (stream, "xd%d", rn & ~1); - break; - } - d_reg_n: - case D_REG_N: - fprintf_fn (stream, "dr%d", rn); - break; - case DX_REG_M: - if (rm & 1) - { - fprintf_fn (stream, "xd%d", rm & ~1); - break; - } - case D_REG_M: - fprintf_fn (stream, "dr%d", rm); - break; - case FPSCR_M: - case FPSCR_N: - fprintf_fn (stream, "fpscr"); - break; - case FPUL_M: - case FPUL_N: - fprintf_fn (stream, "fpul"); - break; - case F_FR0: - fprintf_fn (stream, "fr0"); - break; - case V_REG_N: - fprintf_fn (stream, "fv%d", rn*4); - break; - case V_REG_M: - fprintf_fn (stream, "fv%d", rm*4); - break; - case XMTRX_M4: - fprintf_fn (stream, "xmtrx"); - break; - default: - abort(); - } - } - -#if 0 - /* This code prints instructions in delay slots on the same line - as the instruction which needs the delay slots. This can be - confusing, since other disassembler don't work this way, and - it means that the instructions are not all in a line. So I - disabled it. Ian. */ - if (!(info->flags & 1) - && (op->name[0] == 'j' - || (op->name[0] == 'b' - && (op->name[1] == 'r' - || op->name[1] == 's')) - || (op->name[0] == 'r' && op->name[1] == 't') - || (op->name[0] == 'b' && op->name[2] == '.'))) - { - info->flags |= 1; - fprintf_fn (stream, "\t(slot "); - print_insn_shx (memaddr + 2, info); - info->flags &= ~1; - fprintf_fn (stream, ")"); - return 4; - } -#endif - - if (disp_pc && strcmp (op->name, "mova") != 0) - { - int size; - bfd_byte bytes[4]; - - if (relmask == ~ (bfd_vma) 1) - size = 2; - else - size = 4; - status = info->read_memory_func (disp_pc_addr, bytes, size, info); - if (status == 0) - { - unsigned int val; - - if (size == 2) - { - if ((info->flags & LITTLE_BIT) != 0) - val = bfd_getl16 (bytes); - else - val = bfd_getb16 (bytes); - } - else - { - if ((info->flags & LITTLE_BIT) != 0) - val = bfd_getl32 (bytes); - else - val = bfd_getb32 (bytes); - } - fprintf_fn (stream, "\t! 0x%x", val); - } - } - - return 2; - fail: - ; - - } - fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]); - return 2; -} - -int -print_insn_shl (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - int r; - - info->flags = LITTLE_BIT; - r = print_insn_shx (memaddr, info); - return r; -} - -int -print_insn_sh (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; -{ - int r; - - info->flags = 0; - r = print_insn_shx (memaddr, info); - return r; -} diff --git a/contrib/binutils/opcodes/sh-opc.h b/contrib/binutils/opcodes/sh-opc.h deleted file mode 100644 index 38bfbcde4b62..000000000000 --- a/contrib/binutils/opcodes/sh-opc.h +++ /dev/null @@ -1,830 +0,0 @@ -/* Definitions for SH opcodes. - Copyright (C) 1993, 94, 95, 96, 1997 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -typedef enum { - HEX_0, - HEX_1, - HEX_2, - HEX_3, - HEX_4, - HEX_5, - HEX_6, - HEX_7, - HEX_8, - HEX_9, - HEX_A, - HEX_B, - HEX_C, - HEX_D, - HEX_E, - HEX_F, - REG_N, - REG_M, - SDT_REG_N, - REG_NM, - REG_B, - BRANCH_12, - BRANCH_8, - DISP_8, - DISP_4, - IMM_4, - IMM_4BY2, - IMM_4BY4, - PCRELIMM_8BY2, - PCRELIMM_8BY4, - IMM_8, - IMM_8BY2, - IMM_8BY4, - PPI, - NOPX, - NOPY, - MOVX, - MOVY, - PSH, - PMUL, - PPI3, - PDC, - PPIC -} sh_nibble_type; - -typedef enum { - A_END, - A_BDISP12, - A_BDISP8, - A_DEC_M, - A_DEC_N, - A_DISP_GBR, - A_DISP_PC, - A_DISP_REG_M, - A_DISP_REG_N, - A_GBR, - A_IMM, - A_INC_M, - A_INC_N, - A_IND_M, - A_IND_N, - A_PMOD_N, - A_PMODY_N, - A_IND_R0_REG_M, - A_IND_R0_REG_N, - A_MACH, - A_MACL, - A_PR, - A_R0, - A_R0_GBR, - A_REG_M, - A_REG_N, - A_REG_B, - A_SR, - A_VBR, - A_MOD, - A_RE, - A_RS, - A_DSR, - DSP_REG_M, - DSP_REG_N, - DSP_REG_X, - DSP_REG_Y, - DSP_REG_E, - DSP_REG_F, - DSP_REG_G, - A_A0, - A_X0, - A_X1, - A_Y0, - A_Y1, - A_SSR, - A_SPC, - A_SGR, - A_DBR, - F_REG_N, - F_REG_M, - D_REG_N, - D_REG_M, - X_REG_N, /* Only used for argument parsing */ - X_REG_M, /* Only used for argument parsing */ - DX_REG_N, - DX_REG_M, - V_REG_N, - V_REG_M, - XMTRX_M4, - F_FR0, - FPUL_N, - FPUL_M, - FPSCR_N, - FPSCR_M -} sh_arg_type; - -typedef enum { - A_A1_NUM = 5, - A_A0_NUM = 7, - A_X0_NUM, A_X1_NUM, A_Y0_NUM, A_Y1_NUM, - A_M0_NUM, A_A1G_NUM, A_M1_NUM, A_A0G_NUM -} sh_dsp_reg_nums; - -#define arch_sh1 0x0001 -#define arch_sh2 0x0002 -#define arch_sh3 0x0004 -#define arch_sh3e 0x0008 -#define arch_sh4 0x0010 -#define arch_sh_dsp 0x0100 -#define arch_sh3_dsp 0x0200 - -#define arch_sh1_up (arch_sh1 | arch_sh2_up) -#define arch_sh2_up (arch_sh2 | arch_sh3_up | arch_sh_dsp) -#define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp) -#define arch_sh3e_up (arch_sh3e | arch_sh4_up) -#define arch_sh4_up arch_sh4 - -#define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up) -#define arch_sh3_dsp_up arch_sh3_dsp - -typedef struct { - char *name; - sh_arg_type arg[4]; - sh_nibble_type nibbles[4]; - int arch; -} sh_opcode_info; - -#ifdef DEFINE_TABLE - -sh_opcode_info sh_table[] = { - -/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM_8}, arch_sh1_up}, - -/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh1_up}, - -/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh1_up}, - -/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh1_up}, - -/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM_8}, arch_sh1_up}, - -/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh1_up}, - -/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM_8}, arch_sh1_up}, - -/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh1_up}, - -/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh1_up}, - -/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh1_up}, - -/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh1_up}, - -/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}, - -/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}, - -/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}, - -/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}, - -/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh1_up}, - -/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh1_up}, - -/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh1_up}, - -/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM_8}, arch_sh1_up}, - -/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh1_up}, - -/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh1_up}, - -/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh1_up}, - -/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh1_up}, - -/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh1_up}, - -/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh1_up}, - -/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh1_up}, - -/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh1_up}, - -/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh1_up}, - -/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh1_up}, - -/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh1_up}, - -/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh1_up}, - -/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh1_up}, - -/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh1_up}, - -/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh1_up}, - -/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh1_up}, - -/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh1_up}, - -/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh1_up}, - -/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh1_up}, - -/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh1_up}, - -/* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}, - -/* 0100nnnn01111110 ldc <REG_N>,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}, - -/* 0100nnnn01101110 ldc <REG_N>,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}, - -/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_up}, - -/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_up}, - -/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_up}, - -/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_up}, - -/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh1_up}, - -/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh1_up}, - -/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh1_up}, - -/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}, - -/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}, - -/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up}, - -/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_up}, - -/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_up}, - -/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_up}, - -/* 0100nnnn1xxx0111 ldc.l <REG_N>,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_up}, - -/* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_BDISP8},{HEX_8,HEX_E,BRANCH_8}, arch_sh_dsp_up}, - -/* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_BDISP8},{HEX_8,HEX_C,BRANCH_8}, arch_sh_dsp_up}, - -/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh1_up}, - -/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh1_up}, - -/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh1_up}, - -/* 0100nnnn01101010 lds <REG_N>,DSR */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}, - -/* 0100nnnn01111010 lds <REG_N>,A0 */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}, - -/* 0100nnnn10001010 lds <REG_N>,X0 */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}, - -/* 0100nnnn10011010 lds <REG_N>,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}, - -/* 0100nnnn10101010 lds <REG_N>,Y0 */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}, - -/* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}, - -/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh3e_up}, - -/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh3e_up}, - -/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh1_up}, - -/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh1_up}, - -/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh1_up}, - -/* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up}, - -/* 0100nnnn01110110 lds.l @<REG_N>+,A0 */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up}, - -/* 0100nnnn10000110 lds.l @<REG_N>+,X0 */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up}, - -/* 0100nnnn10010110 lds.l @<REG_N>+,X1 */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up}, - -/* 0100nnnn10100110 lds.l @<REG_N>+,Y0 */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up}, - -/* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}, - -/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh3e_up}, - -/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh3e_up}, - -/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}, - -/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh1_up}, - -/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM_8}, arch_sh1_up}, - -/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh1_up}, - -/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh1_up}, - -/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh1_up}, - -/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh1_up}, - -/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM_4}, arch_sh1_up}, - -/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM_8}, arch_sh1_up}, - -/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh1_up}, - -/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh1_up}, - -/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh1_up}, - -/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM_4}, arch_sh1_up}, - -/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM_8}, arch_sh1_up}, - -/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM_4BY4}, arch_sh1_up}, - -/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh1_up}, - -/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh1_up}, - -/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh1_up}, - -/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM_4BY4}, arch_sh1_up}, - -/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM_8BY4}, arch_sh1_up}, - -/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh1_up}, - -/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh1_up}, - -/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh1_up}, - -/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh1_up}, - -/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM_8BY4}, arch_sh1_up}, - -/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh1_up}, - -/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh1_up}, - -/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh1_up}, - -/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM_4BY2}, arch_sh1_up}, - -/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM_8BY2}, arch_sh1_up}, - -/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh1_up}, - -/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh1_up}, - -/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh1_up}, - -/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh1_up}, - -/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM_4BY2}, arch_sh1_up}, - -/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM_8BY2}, arch_sh1_up}, - -/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up}, -/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_up}, - - -/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh1_up}, - -/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up}, -/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up}, - -/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}, - -/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up}, -/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up}, - -/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh1_up}, - -/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh1_up}, - -/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh1_up}, - -/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh1_up}, -/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_up}, - -/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_up}, - -/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_up}, - - -/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM_8}, arch_sh1_up}, - -/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh1_up}, - -/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM_8}, arch_sh1_up}, - -/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_up}, - -/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh1_up}, - -/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh1_up}, - -/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh1_up}, - -/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh1_up}, - -/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh1_up}, - -/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh1_up}, - -/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh1_up}, -/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh1_up}, - -/* 0100nnnn00010100 setrc <REG_N> */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}, - -/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM_8}, arch_sh_dsp_up}, - -/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh3_up}, - -/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh3_up}, - -/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh1_up}, - -/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh1_up}, - -/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh1_up}, - -/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh1_up}, - -/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh1_up}, - -/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh1_up}, - -/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh1_up}, - -/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh1_up}, - -/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh1_up}, - -/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh1_up}, - -/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh1_up}, - -/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh1_up}, - -/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh1_up}, - -/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh1_up}, - -/* 0000nnnn01010010 stc MOD,<REG_N> */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up}, - -/* 0000nnnn01110010 stc RE,<REG_N> */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}, - -/* 0000nnnn01100010 stc RS,<REG_N> */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}, - -/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_up}, - -/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_up}, - -/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_up}, - -/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_up}, - -/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_up}, - -/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh1_up}, - -/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh1_up}, - -/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up}, - -/* 0100nnnn01110011 stc.l RE,@-<REG_N> */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up}, - -/* 0100nnnn01100011 stc.l RS,@-<REG_N> */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up}, - -/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_up}, - -/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_up}, - -/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh4_up}, - -/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_up}, - -/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_up}, - -/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_up}, - -/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh1_up}, - -/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh1_up}, - -/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh1_up}, - -/* 0000nnnn01101010 sts DSR,<REG_N> */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}, - -/* 0000nnnn01111010 sts A0,<REG_N> */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}, - -/* 0000nnnn10001010 sts X0,<REG_N> */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}, - -/* 0000nnnn10011010 sts X1,<REG_N> */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}, - -/* 0000nnnn10101010 sts Y0,<REG_N> */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}, - -/* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}, - -/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh3e_up}, - -/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh3e_up}, - -/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh1_up}, - -/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh1_up}, - -/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh1_up}, - -/* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}, - -/* 0100nnnn01110110 sts.l A0,@-<REG_N> */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}, - -/* 0100nnnn10000110 sts.l X0,@-<REG_N> */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up}, - -/* 0100nnnn10010110 sts.l X1,@-<REG_N> */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up}, - -/* 0100nnnn10100110 sts.l Y0,@-<REG_N> */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up}, - -/* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}, - -/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh3e_up}, - -/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh3e_up}, - -/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh1_up}, - -/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh1_up}, - -/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh1_up}, - -/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh1_up}, - -/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh1_up}, - -/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh1_up}, - -/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM_8}, arch_sh1_up}, - -/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM_8}, arch_sh1_up}, - -/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh1_up}, - -/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM_8}, arch_sh1_up}, - -/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM_8}, arch_sh1_up}, - -/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh1_up}, - -/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM_8}, arch_sh1_up}, - -/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh1_up}, - -/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh1_up}, - -/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}, - -/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}, - -/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}, - -/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}, - -/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}, - -/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}, - -/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up}, - -/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up}, - -/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up}, - -/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{A_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up}, - -/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up}, - -/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */ {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up}, - -/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up}, - -/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,A_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up}, - -/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up}, - -/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up}, - -/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up}, - -/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{A_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up}, - -/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}, - -/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}, - -/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}, - -/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,A_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}, - -/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up}, -/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up}, -/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{A_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}, -/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{A_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}, -/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{A_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}, -/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_M,A_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}, -/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_M,A_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}, -/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_M,A_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}, -/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{A_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}, -/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{A_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}, -/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{A_PMODY_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}, -/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_M,A_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}, -/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_M,A_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}, -/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_M,A_PMODY_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}, - -/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up}, -/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up}, -/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up}, -/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */ -{"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up}, -/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up}, -/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up}, -/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */ -{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3,HEX_8,HEX_8}, arch_sh_dsp_up}, -/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */ -{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3,HEX_9,HEX_8}, arch_sh_dsp_up}, -/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ -{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_8}, arch_sh_dsp_up}, -/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ -{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_8}, arch_sh_dsp_up}, - -{"dct",{0},{PPI,PDC,HEX_1}, arch_sh_dsp_up}, -{"dcf",{0},{PPI,PDC,HEX_2}, arch_sh_dsp_up}, - -/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up}, -/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up}, -/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up}, -/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up}, -/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up}, -/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up}, -/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up}, -/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up}, -/* 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ -{"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up}, -/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */ -{"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up}, -/* 10011001xxyynnnn pinc <DSP_REG_X>,<DSP_REG_N> */ -{"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9}, arch_sh_dsp_up}, -/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */ -{"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up}, -/* 10111001xxyynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */ -{"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9}, arch_sh_dsp_up}, -/* 10001101xxyynnnn pclr <DSP_REG_N> */ -{"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up}, -/* 10011101xxyynnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */ -{"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D}, arch_sh_dsp_up}, -/* 10111101xxyynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */ -{"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D}, arch_sh_dsp_up}, -/* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */ -{"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up}, -/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */ -{"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up}, -/* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */ -{"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up}, -/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */ -{"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up}, -/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */ -{"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up}, -/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */ -{"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up}, -/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */ -{"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up}, -/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */ -{"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}, - -/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh3e_up}, -/* 1111nnnn01011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up}, - -/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh3e_up}, -/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh4_up}, - -/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh3e_up}, -/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh4_up}, - -/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh3e_up}, -/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh4_up}, - -/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_B,HEX_D}, arch_sh4_up}, - -/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_A,HEX_D}, arch_sh4_up}, - -/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh3e_up}, -/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh4_up}, - -/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}, - -/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh3e_up}, - -/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh3e_up}, - -/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh3e_up}, - -/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh3e_up}, -/* 1111nnnn00101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh4_up}, - -/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh3e_up}, - -/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh3e_up}, -/* 1111nnnnmmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh4_up}, - -/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh3e_up}, -/* 1111nnnnmmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up}, - -/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh3e_up}, -/* 1111nnnnmmmm1010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up}, - -/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh3e_up}, -/* 1111nnnnmmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up}, - -/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh3e_up}, -/* 1111nnnnmmmm1011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up}, - -/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh3e_up}, -/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up}, - -/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh3e_up}, -/* 1111nnnnmmmm0111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up}, - -/* 1111nnnnmmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up}, - -/* 1111nnnnmmmm1010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up}, - -/* 1111nnnnmmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up}, - -/* 1111nnnnmmmm1011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up}, - -/* 1111nnnnmmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up}, - -/* 1111nnnnmmmm0111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up}, - -/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh3e_up}, - -/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh3e_up}, - -/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh3e_up}, - -/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh3e_up}, - -/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh3e_up}, - -/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh3e_up}, - -/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh3e_up}, -/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh4_up}, - -/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh3e_up}, -/* 1111nnnn01001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up}, - -/* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up}, - -/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh4_up}, - -/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up}, -/* 1111nnnn01101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up}, - -/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh3e_up}, - -/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh3e_up}, -/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh4_up}, - -/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh3e_up}, -/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh4_up}, - -/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_NM,HEX_F,HEX_D}, arch_sh4_up}, - -{ 0 } -}; - -#endif |