diff options
| -rw-r--r-- | sys/dev/sfxge/common/ef10_nic.c | 10 | ||||
| -rw-r--r-- | sys/dev/sfxge/common/hunt_nic.c | 10 | ||||
| -rw-r--r-- | sys/dev/sfxge/common/medford2_nic.c | 10 | ||||
| -rw-r--r-- | sys/dev/sfxge/common/medford_nic.c | 10 |
4 files changed, 10 insertions, 30 deletions
diff --git a/sys/dev/sfxge/common/ef10_nic.c b/sys/dev/sfxge/common/ef10_nic.c index b669ddd1ad00..15f213f14ea7 100644 --- a/sys/dev/sfxge/common/ef10_nic.c +++ b/sys/dev/sfxge/common/ef10_nic.c @@ -1672,6 +1672,16 @@ ef10_nic_board_cfg( */ encp->enc_rx_scale_max_exclusive_contexts = 64 - 6; + encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT); + /* No boundary crossing limits */ + encp->enc_tx_dma_desc_boundary = 0; + + /* + * Maximum number of bytes into the frame the TCP header can start for + * firmware assisted TSO to work. + */ + encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; + /* Get remaining controller-specific board config */ if ((rc = enop->eno_board_cfg(enp)) != 0) diff --git a/sys/dev/sfxge/common/hunt_nic.c b/sys/dev/sfxge/common/hunt_nic.c index 7d9cb053d69e..c11423b30e03 100644 --- a/sys/dev/sfxge/common/hunt_nic.c +++ b/sys/dev/sfxge/common/hunt_nic.c @@ -232,10 +232,6 @@ hunt_board_cfg( encp->enc_rx_buf_align_start = 1; encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */ - encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT); - /* No boundary crossing limits */ - encp->enc_tx_dma_desc_boundary = 0; - /* * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available @@ -281,12 +277,6 @@ hunt_board_cfg( encp->enc_intr_vec_base = base; encp->enc_intr_limit = nvec; - /* - * Maximum number of bytes into the frame the TCP header can start for - * firmware assisted TSO to work. - */ - encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; - if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0) goto fail7; encp->enc_required_pcie_bandwidth_mbps = bandwidth; diff --git a/sys/dev/sfxge/common/medford2_nic.c b/sys/dev/sfxge/common/medford2_nic.c index a5c556629fb3..25dfc76a2358 100644 --- a/sys/dev/sfxge/common/medford2_nic.c +++ b/sys/dev/sfxge/common/medford2_nic.c @@ -166,10 +166,6 @@ medford2_board_cfg( } encp->enc_rx_buf_align_end = end_padding; - encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT); - /* No boundary crossing limits */ - encp->enc_tx_dma_desc_boundary = 0; - /* * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available @@ -217,12 +213,6 @@ medford2_board_cfg( encp->enc_intr_limit = nvec; /* - * Maximum number of bytes into the frame the TCP header can start for - * firmware assisted TSO to work. - */ - encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; - - /* * Medford2 stores a single global copy of VPD, not per-PF as on * Huntington. */ diff --git a/sys/dev/sfxge/common/medford_nic.c b/sys/dev/sfxge/common/medford_nic.c index ef5a89c70df2..06c73fe5ecb2 100644 --- a/sys/dev/sfxge/common/medford_nic.c +++ b/sys/dev/sfxge/common/medford_nic.c @@ -163,10 +163,6 @@ medford_board_cfg( } encp->enc_rx_buf_align_end = end_padding; - encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT); - /* No boundary crossing limits */ - encp->enc_tx_dma_desc_boundary = 0; - /* * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available @@ -214,12 +210,6 @@ medford_board_cfg( encp->enc_intr_limit = nvec; /* - * Maximum number of bytes into the frame the TCP header can start for - * firmware assisted TSO to work. - */ - encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT; - - /* * Medford stores a single global copy of VPD, not per-PF as on * Huntington. */ |