diff options
| -rw-r--r-- | sys/dev/alc/if_alc.c | 16 | ||||
| -rw-r--r-- | sys/dev/bge/if_bge.c | 16 | ||||
| -rw-r--r-- | sys/dev/cxgb/cxgb_main.c | 4 | ||||
| -rw-r--r-- | sys/dev/cxgb/cxgb_osdep.h | 10 | ||||
| -rw-r--r-- | sys/dev/cxgbe/osdep.h | 14 | ||||
| -rw-r--r-- | sys/dev/cxgbe/t4_main.c | 6 | ||||
| -rw-r--r-- | sys/dev/e1000/if_em.c | 6 | ||||
| -rw-r--r-- | sys/dev/et/if_et.c | 6 | ||||
| -rw-r--r-- | sys/dev/jme/if_jme.c | 2 | ||||
| -rw-r--r-- | sys/dev/pci/pci.c | 80 | ||||
| -rw-r--r-- | sys/dev/pci/pcireg.h | 282 | ||||
| -rw-r--r-- | sys/dev/re/if_re.c | 8 | ||||
| -rw-r--r-- | sys/ofed/include/linux/pci.h | 4 | ||||
| -rw-r--r-- | sys/powerpc/mpc85xx/pci_fdt.c | 12 | ||||
| -rw-r--r-- | usr.sbin/pciconf/cap.c | 50 | ||||
| -rw-r--r-- | usr.sbin/pciconf/err.c | 18 |
16 files changed, 267 insertions, 267 deletions
diff --git a/sys/dev/alc/if_alc.c b/sys/dev/alc/if_alc.c index c73075c6a8fc..2a0ddb2f509b 100644 --- a/sys/dev/alc/if_alc.c +++ b/sys/dev/alc/if_alc.c @@ -683,7 +683,7 @@ alc_aspm(struct alc_softc *sc, int media) if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == (ALC_FLAG_APS | ALC_FLAG_PCIE)) linkcfg = CSR_READ_2(sc, sc->alc_expcap + - PCIR_EXPRESS_LINK_CTL); + PCIER_LINK_CTL); else linkcfg = 0; pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; @@ -698,7 +698,7 @@ alc_aspm(struct alc_softc *sc, int media) if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && sc->alc_rev == ATHEROS_AR8152_B_V10) linkcfg |= 0x80; - CSR_WRITE_2(sc, sc->alc_expcap + PCIR_EXPRESS_LINK_CTL, + CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, linkcfg); pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | PM_CFG_HOTRST); @@ -798,10 +798,10 @@ alc_attach(device_t dev) if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { sc->alc_flags |= ALC_FLAG_PCIE; sc->alc_expcap = base; - burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL); + burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); sc->alc_dma_rd_burst = - (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12; - sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5; + (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; + sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; if (bootverbose) { device_printf(dev, "Read request size : %u bytes.\n", alc_dma_burst[sc->alc_dma_rd_burst]); @@ -831,9 +831,9 @@ alc_attach(device_t dev) CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); } /* Disable ASPM L0S and L1. */ - cap = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CAP); - if ((cap & PCIM_LINK_CAP_ASPM) != 0) { - ctl = CSR_READ_2(sc, base + PCIR_EXPRESS_LINK_CTL); + cap = CSR_READ_2(sc, base + PCIER_LINK_CAP); + if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { + ctl = CSR_READ_2(sc, base + PCIER_LINK_CTL); if ((ctl & 0x08) != 0) sc->alc_rcb = DMA_CFG_RCB_128; if (bootverbose) diff --git a/sys/dev/bge/if_bge.c b/sys/dev/bge/if_bge.c index 16cfe27a2202..4ddcd8c7e2da 100644 --- a/sys/dev/bge/if_bge.c +++ b/sys/dev/bge/if_bge.c @@ -3625,17 +3625,17 @@ bge_reset(struct bge_softc *sc) pci_write_config(dev, 0xC4, val | (1 << 15), 4); } devctl = pci_read_config(dev, - sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); + sc->bge_expcap + PCIER_DEVICE_CTL, 2); /* Clear enable no snoop and disable relaxed ordering. */ - devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE | - PCIM_EXP_CTL_NOSNOOP_ENABLE); - pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, + devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE | + PCIEM_CTL_NOSNOOP_ENABLE); + pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL, devctl, 2); /* Clear error status. */ - pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA, - PCIM_EXP_STA_CORRECTABLE_ERROR | - PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR | - PCIM_EXP_STA_UNSUPPORTED_REQ, 2); + pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA, + PCIEM_STA_CORRECTABLE_ERROR | + PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | + PCIEM_STA_UNSUPPORTED_REQ, 2); } /* Reset some of the PCI state that got zapped by reset. */ diff --git a/sys/dev/cxgb/cxgb_main.c b/sys/dev/cxgb/cxgb_main.c index 62ad05152dbf..b0987167f8c6 100644 --- a/sys/dev/cxgb/cxgb_main.c +++ b/sys/dev/cxgb/cxgb_main.c @@ -476,8 +476,8 @@ cxgb_controller_attach(device_t dev) if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { uint16_t lnk; - lnk = pci_read_config(dev, reg + PCIR_EXPRESS_LINK_STA, 2); - sc->link_width = (lnk & PCIM_LINK_STA_WIDTH) >> 4; + lnk = pci_read_config(dev, reg + PCIER_LINK_STA, 2); + sc->link_width = (lnk & PCIEM_LINK_STA_WIDTH) >> 4; if (sc->link_width < 8 && (ai->caps & SUPPORTED_10000baseT_Full)) { device_printf(sc->dev, diff --git a/sys/dev/cxgb/cxgb_osdep.h b/sys/dev/cxgb/cxgb_osdep.h index 37171d94f5ac..71572d5ad883 100644 --- a/sys/dev/cxgb/cxgb_osdep.h +++ b/sys/dev/cxgb/cxgb_osdep.h @@ -215,11 +215,11 @@ static const int debug_flags = DBG_RX; #define PCI_VPD_DATA PCIR_VPD_DATA #define PCI_CAP_ID_EXP PCIY_EXPRESS -#define PCI_EXP_DEVCTL PCIR_EXPRESS_DEVICE_CTL -#define PCI_EXP_DEVCTL_PAYLOAD PCIM_EXP_CTL_MAX_PAYLOAD -#define PCI_EXP_DEVCTL_READRQ PCIM_EXP_CTL_MAX_READ_REQUEST -#define PCI_EXP_LNKCTL PCIR_EXPRESS_LINK_CTL -#define PCI_EXP_LNKSTA PCIR_EXPRESS_LINK_STA +#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL +#define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD +#define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST +#define PCI_EXP_LNKCTL PCIER_LINK_CTL +#define PCI_EXP_LNKSTA PCIER_LINK_STA /* * Linux compatibility macros diff --git a/sys/dev/cxgbe/osdep.h b/sys/dev/cxgbe/osdep.h index f2a75cf3c29e..a8c68c21fcc7 100644 --- a/sys/dev/cxgbe/osdep.h +++ b/sys/dev/cxgbe/osdep.h @@ -118,13 +118,13 @@ typedef boolean_t bool; #define PCI_VPD_DATA PCIR_VPD_DATA #define PCI_CAP_ID_EXP PCIY_EXPRESS -#define PCI_EXP_DEVCTL PCIR_EXPRESS_DEVICE_CTL -#define PCI_EXP_DEVCTL_PAYLOAD PCIM_EXP_CTL_MAX_PAYLOAD -#define PCI_EXP_DEVCTL_READRQ PCIM_EXP_CTL_MAX_READ_REQUEST -#define PCI_EXP_LNKCTL PCIR_EXPRESS_LINK_CTL -#define PCI_EXP_LNKSTA PCIR_EXPRESS_LINK_STA -#define PCI_EXP_LNKSTA_CLS PCIM_LINK_STA_SPEED -#define PCI_EXP_LNKSTA_NLW PCIM_LINK_STA_WIDTH +#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL +#define PCI_EXP_DEVCTL_PAYLOAD PCIEM_CTL_MAX_PAYLOAD +#define PCI_EXP_DEVCTL_READRQ PCIEM_CTL_MAX_READ_REQUEST +#define PCI_EXP_LNKCTL PCIER_LINK_CTL +#define PCI_EXP_LNKSTA PCIER_LINK_STA +#define PCI_EXP_LNKSTA_CLS PCIEM_LINK_STA_SPEED +#define PCI_EXP_LNKSTA_NLW PCIEM_LINK_STA_WIDTH #define PCI_EXP_DEVCTL2 0x28 static inline int diff --git a/sys/dev/cxgbe/t4_main.c b/sys/dev/cxgbe/t4_main.c index 5b46e142519c..50a8725ff03e 100644 --- a/sys/dev/cxgbe/t4_main.c +++ b/sys/dev/cxgbe/t4_main.c @@ -429,9 +429,9 @@ t4_attach(device_t dev) uint32_t v; pci_set_max_read_req(dev, 4096); - v = pci_read_config(dev, i + PCIR_EXPRESS_DEVICE_CTL, 2); - v |= PCIM_EXP_CTL_RELAXED_ORD_ENABLE; - pci_write_config(dev, i + PCIR_EXPRESS_DEVICE_CTL, v, 2); + v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); + v |= PCIEM_CTL_RELAXED_ORD_ENABLE; + pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2); } snprintf(sc->lockname, sizeof(sc->lockname), "%s", diff --git a/sys/dev/e1000/if_em.c b/sys/dev/e1000/if_em.c index c57293b26435..a4f43e7840e0 100644 --- a/sys/dev/e1000/if_em.c +++ b/sys/dev/e1000/if_em.c @@ -5113,11 +5113,11 @@ em_disable_aspm(struct adapter *adapter) } if (pci_find_cap(dev, PCIY_EXPRESS, &base) != 0) return; - reg = base + PCIR_EXPRESS_LINK_CAP; + reg = base + PCIER_LINK_CAP; link_cap = pci_read_config(dev, reg, 2); - if ((link_cap & PCIM_LINK_CAP_ASPM) == 0) + if ((link_cap & PCIEM_LINK_CAP_ASPM) == 0) return; - reg = base + PCIR_EXPRESS_LINK_CTL; + reg = base + PCIER_LINK_CTL; link_ctrl = pci_read_config(dev, reg, 2); link_ctrl &= 0xFFFC; /* turn off bit 1 and 2 */ pci_write_config(dev, reg, link_ctrl, 2); diff --git a/sys/dev/et/if_et.c b/sys/dev/et/if_et.c index bde680e5981d..dfdcde73438b 100644 --- a/sys/dev/et/if_et.c +++ b/sys/dev/et/if_et.c @@ -700,8 +700,8 @@ et_bus_config(struct et_softc *sc) * max playload size */ val = pci_read_config(sc->dev, - sc->sc_expcap + PCIR_EXPRESS_DEVICE_CAP, 4); - max_plsz = val & PCIM_EXP_CAP_MAX_PAYLOAD; + sc->sc_expcap + PCIER_DEVICE_CAP, 4); + max_plsz = val & PCIEM_CAP_MAX_PAYLOAD; switch (max_plsz) { case ET_PCIV_DEVICE_CAPS_PLSZ_128: @@ -732,7 +732,7 @@ et_bus_config(struct et_softc *sc) * Set L0s and L1 latency timer to 2us */ val = pci_read_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, 4); - val &= ~(PCIM_LINK_CAP_L0S_EXIT | PCIM_LINK_CAP_L1_EXIT); + val &= ~(PCIEM_LINK_CAP_L0S_EXIT | PCIEM_LINK_CAP_L1_EXIT); /* L0s exit latency : 2us */ val |= 0x00005000; /* L1 exit latency : 2us */ diff --git a/sys/dev/jme/if_jme.c b/sys/dev/jme/if_jme.c index 7f0f9174f8af..13270b78d40c 100644 --- a/sys/dev/jme/if_jme.c +++ b/sys/dev/jme/if_jme.c @@ -778,7 +778,7 @@ jme_attach(device_t dev) /* Set max allowable DMA size. */ if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { sc->jme_flags |= JME_FLAG_PCIE; - burst = pci_read_config(dev, i + PCIR_EXPRESS_DEVICE_CTL, 2); + burst = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); if (bootverbose) { device_printf(dev, "Read request size : %d bytes.\n", 128 << ((burst >> 12) & 0x07)); diff --git a/sys/dev/pci/pci.c b/sys/dev/pci/pci.c index 650342101cda..3de932ab8740 100644 --- a/sys/dev/pci/pci.c +++ b/sys/dev/pci/pci.c @@ -743,8 +743,8 @@ pci_read_cap(device_t pcib, pcicfgregs *cfg) */ pcie_chipset = 1; cfg->pcie.pcie_location = ptr; - val = REG(ptr + PCIR_EXPRESS_FLAGS, 2); - cfg->pcie.pcie_type = val & PCIM_EXP_FLAGS_TYPE; + val = REG(ptr + PCIER_FLAGS, 2); + cfg->pcie.pcie_type = val & PCIEM_FLAGS_TYPE; break; default: break; @@ -1791,8 +1791,8 @@ pci_get_max_read_req(device_t dev) cap = dinfo->cfg.pcie.pcie_location; if (cap == 0) return (0); - val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2); - val &= PCIM_EXP_CTL_MAX_READ_REQUEST; + val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); + val &= PCIEM_CTL_MAX_READ_REQUEST; val >>= 12; return (1 << (val + 7)); } @@ -1812,10 +1812,10 @@ pci_set_max_read_req(device_t dev, int size) if (size > 4096) size = 4096; size = (1 << (fls(size) - 1)); - val = pci_read_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, 2); - val &= ~PCIM_EXP_CTL_MAX_READ_REQUEST; + val = pci_read_config(dev, cap + PCIER_DEVICE_CTL, 2); + val &= ~PCIEM_CTL_MAX_READ_REQUEST; val |= (fls(size) - 8) << 12; - pci_write_config(dev, cap + PCIR_EXPRESS_DEVICE_CTL, val, 2); + pci_write_config(dev, cap + PCIER_DEVICE_CTL, val, 2); return (size); } @@ -4469,28 +4469,28 @@ pci_cfg_restore_pcie(device_t dev, struct pci_devinfo *dinfo) cfg = &dinfo->cfg.pcie; pos = cfg->pcie_location; - version = cfg->pcie_flags & PCIM_EXP_FLAGS_VERSION; + version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; - WREG(PCIR_EXPRESS_DEVICE_CTL, cfg->pcie_device_ctl); + WREG(PCIER_DEVICE_CTL, cfg->pcie_device_ctl); - if (version > 1 || cfg->pcie_type == PCIM_EXP_TYPE_ROOT_PORT || - cfg->pcie_type == PCIM_EXP_TYPE_ENDPOINT || - cfg->pcie_type == PCIM_EXP_TYPE_LEGACY_ENDPOINT) - WREG(PCIR_EXPRESS_LINK_CTL, cfg->pcie_link_ctl); + if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || + cfg->pcie_type == PCIEM_TYPE_ENDPOINT || + cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) + WREG(PCIER_LINK_CTL, cfg->pcie_link_ctl); - if (version > 1 || (cfg->pcie_type == PCIM_EXP_TYPE_ROOT_PORT || - (cfg->pcie_type == PCIM_EXP_TYPE_DOWNSTREAM_PORT && - (cfg->pcie_flags & PCIM_EXP_FLAGS_SLOT)))) - WREG(PCIR_EXPRESS_SLOT_CTL, cfg->pcie_slot_ctl); + if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || + (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && + (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) + WREG(PCIER_SLOT_CTL, cfg->pcie_slot_ctl); - if (version > 1 || cfg->pcie_type == PCIM_EXP_TYPE_ROOT_PORT || - cfg->pcie_type == PCIM_EXP_TYPE_ROOT_EC) - WREG(PCIR_EXPRESS_ROOT_CTL, cfg->pcie_root_ctl); + if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || + cfg->pcie_type == PCIEM_TYPE_ROOT_EC) + WREG(PCIER_ROOT_CTL, cfg->pcie_root_ctl); if (version > 1) { - WREG(PCIR_EXPRESS_DEVICE_CTL2, cfg->pcie_device_ctl2); - WREG(PCIR_EXPRESS_LINK_CTL2, cfg->pcie_link_ctl2); - WREG(PCIR_EXPRESS_SLOT_CTL2, cfg->pcie_slot_ctl2); + WREG(PCIER_DEVICE_CTL2, cfg->pcie_device_ctl2); + WREG(PCIER_LINK_CTL2, cfg->pcie_link_ctl2); + WREG(PCIER_SLOT_CTL2, cfg->pcie_slot_ctl2); } #undef WREG } @@ -4562,30 +4562,30 @@ pci_cfg_save_pcie(device_t dev, struct pci_devinfo *dinfo) cfg = &dinfo->cfg.pcie; pos = cfg->pcie_location; - cfg->pcie_flags = RREG(PCIR_EXPRESS_FLAGS); + cfg->pcie_flags = RREG(PCIER_FLAGS); - version = cfg->pcie_flags & PCIM_EXP_FLAGS_VERSION; + version = cfg->pcie_flags & PCIEM_FLAGS_VERSION; - cfg->pcie_device_ctl = RREG(PCIR_EXPRESS_DEVICE_CTL); + cfg->pcie_device_ctl = RREG(PCIER_DEVICE_CTL); - if (version > 1 || cfg->pcie_type == PCIM_EXP_TYPE_ROOT_PORT || - cfg->pcie_type == PCIM_EXP_TYPE_ENDPOINT || - cfg->pcie_type == PCIM_EXP_TYPE_LEGACY_ENDPOINT) - cfg->pcie_link_ctl = RREG(PCIR_EXPRESS_LINK_CTL); + if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || + cfg->pcie_type == PCIEM_TYPE_ENDPOINT || + cfg->pcie_type == PCIEM_TYPE_LEGACY_ENDPOINT) + cfg->pcie_link_ctl = RREG(PCIER_LINK_CTL); - if (version > 1 || (cfg->pcie_type == PCIM_EXP_TYPE_ROOT_PORT || - (cfg->pcie_type == PCIM_EXP_TYPE_DOWNSTREAM_PORT && - (cfg->pcie_flags & PCIM_EXP_FLAGS_SLOT)))) - cfg->pcie_slot_ctl = RREG(PCIR_EXPRESS_SLOT_CTL); + if (version > 1 || (cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || + (cfg->pcie_type == PCIEM_TYPE_DOWNSTREAM_PORT && + (cfg->pcie_flags & PCIEM_FLAGS_SLOT)))) + cfg->pcie_slot_ctl = RREG(PCIER_SLOT_CTL); - if (version > 1 || cfg->pcie_type == PCIM_EXP_TYPE_ROOT_PORT || - cfg->pcie_type == PCIM_EXP_TYPE_ROOT_EC) - cfg->pcie_root_ctl = RREG(PCIR_EXPRESS_ROOT_CTL); + if (version > 1 || cfg->pcie_type == PCIEM_TYPE_ROOT_PORT || + cfg->pcie_type == PCIEM_TYPE_ROOT_EC) + cfg->pcie_root_ctl = RREG(PCIER_ROOT_CTL); if (version > 1) { - cfg->pcie_device_ctl2 = RREG(PCIR_EXPRESS_DEVICE_CTL2); - cfg->pcie_link_ctl2 = RREG(PCIR_EXPRESS_LINK_CTL2); - cfg->pcie_slot_ctl2 = RREG(PCIR_EXPRESS_SLOT_CTL2); + cfg->pcie_device_ctl2 = RREG(PCIER_DEVICE_CTL2); + cfg->pcie_link_ctl2 = RREG(PCIER_LINK_CTL2); + cfg->pcie_slot_ctl2 = RREG(PCIER_SLOT_CTL2); } #undef RREG } diff --git a/sys/dev/pci/pcireg.h b/sys/dev/pci/pcireg.h index 1913ca2e1c22..735d5f654d89 100644 --- a/sys/dev/pci/pcireg.h +++ b/sys/dev/pci/pcireg.h @@ -629,147 +629,147 @@ #define PCIR_SUBVENDCAP_ID 0x4 /* PCI Express definitions */ -#define PCIR_EXPRESS_FLAGS 0x2 -#define PCIM_EXP_FLAGS_VERSION 0x000F -#define PCIM_EXP_FLAGS_TYPE 0x00F0 -#define PCIM_EXP_TYPE_ENDPOINT 0x0000 -#define PCIM_EXP_TYPE_LEGACY_ENDPOINT 0x0010 -#define PCIM_EXP_TYPE_ROOT_PORT 0x0040 -#define PCIM_EXP_TYPE_UPSTREAM_PORT 0x0050 -#define PCIM_EXP_TYPE_DOWNSTREAM_PORT 0x0060 -#define PCIM_EXP_TYPE_PCI_BRIDGE 0x0070 -#define PCIM_EXP_TYPE_PCIE_BRIDGE 0x0080 -#define PCIM_EXP_TYPE_ROOT_INT_EP 0x0090 -#define PCIM_EXP_TYPE_ROOT_EC 0x00a0 -#define PCIM_EXP_FLAGS_SLOT 0x0100 -#define PCIM_EXP_FLAGS_IRQ 0x3e00 -#define PCIR_EXPRESS_DEVICE_CAP 0x4 -#define PCIM_EXP_CAP_MAX_PAYLOAD 0x00000007 -#define PCIM_EXP_CAP_PHANTHOM_FUNCS 0x00000018 -#define PCIM_EXP_CAP_EXT_TAG_FIELD 0x00000020 -#define PCIM_EXP_CAP_L0S_LATENCY 0x000001c0 -#define PCIM_EXP_CAP_L1_LATENCY 0x00000e00 -#define PCIM_EXP_CAP_ROLE_ERR_RPT 0x00008000 -#define PCIM_EXP_CAP_SLOT_PWR_LIM_VAL 0x03fc0000 -#define PCIM_EXP_CAP_SLOT_PWR_LIM_SCALE 0x0c000000 -#define PCIM_EXP_CAP_FLR 0x10000000 -#define PCIR_EXPRESS_DEVICE_CTL 0x8 -#define PCIM_EXP_CTL_COR_ENABLE 0x0001 -#define PCIM_EXP_CTL_NFER_ENABLE 0x0002 -#define PCIM_EXP_CTL_FER_ENABLE 0x0004 -#define PCIM_EXP_CTL_URR_ENABLE 0x0008 -#define PCIM_EXP_CTL_RELAXED_ORD_ENABLE 0x0010 -#define PCIM_EXP_CTL_MAX_PAYLOAD 0x00e0 -#define PCIM_EXP_CTL_EXT_TAG_FIELD 0x0100 -#define PCIM_EXP_CTL_PHANTHOM_FUNCS 0x0200 -#define PCIM_EXP_CTL_AUX_POWER_PM 0x0400 -#define PCIM_EXP_CTL_NOSNOOP_ENABLE 0x0800 -#define PCIM_EXP_CTL_MAX_READ_REQUEST 0x7000 -#define PCIM_EXP_CTL_BRDG_CFG_RETRY 0x8000 /* PCI-E - PCI/PCI-X bridges */ -#define PCIM_EXP_CTL_INITIATE_FLR 0x8000 /* FLR capable endpoints */ -#define PCIR_EXPRESS_DEVICE_STA 0xa -#define PCIM_EXP_STA_CORRECTABLE_ERROR 0x0001 -#define PCIM_EXP_STA_NON_FATAL_ERROR 0x0002 -#define PCIM_EXP_STA_FATAL_ERROR 0x0004 -#define PCIM_EXP_STA_UNSUPPORTED_REQ 0x0008 -#define PCIM_EXP_STA_AUX_POWER 0x0010 -#define PCIM_EXP_STA_TRANSACTION_PND 0x0020 -#define PCIR_EXPRESS_LINK_CAP 0xc -#define PCIM_LINK_CAP_MAX_SPEED 0x0000000f -#define PCIM_LINK_CAP_MAX_WIDTH 0x000003f0 -#define PCIM_LINK_CAP_ASPM 0x00000c00 -#define PCIM_LINK_CAP_L0S_EXIT 0x00007000 -#define PCIM_LINK_CAP_L1_EXIT 0x00038000 -#define PCIM_LINK_CAP_CLOCK_PM 0x00040000 -#define PCIM_LINK_CAP_SURPRISE_DOWN 0x00080000 -#define PCIM_LINK_CAP_DL_ACTIVE 0x00100000 -#define PCIM_LINK_CAP_LINK_BW_NOTIFY 0x00200000 -#define PCIM_LINK_CAP_ASPM_COMPLIANCE 0x00400000 -#define PCIM_LINK_CAP_PORT 0xff000000 -#define PCIR_EXPRESS_LINK_CTL 0x10 -#define PCIM_EXP_LINK_CTL_ASPMC_DIS 0x0000 -#define PCIM_EXP_LINK_CTL_ASPMC_L0S 0x0001 -#define PCIM_EXP_LINK_CTL_ASPMC_L1 0x0002 -#define PCIM_EXP_LINK_CTL_ASPMC 0x0003 -#define PCIM_EXP_LINK_CTL_RCB 0x0008 -#define PCIM_EXP_LINK_CTL_LINK_DIS 0x0010 -#define PCIM_EXP_LINK_CTL_RETRAIN_LINK 0x0020 -#define PCIM_EXP_LINK_CTL_COMMON_CLOCK 0x0040 -#define PCIM_EXP_LINK_CTL_EXTENDED_SYNC 0x0080 -#define PCIM_EXP_LINK_CTL_ECPM 0x0100 -#define PCIM_EXP_LINK_CTL_HAWD 0x0200 -#define PCIM_EXP_LINK_CTL_LBMIE 0x0400 -#define PCIM_EXP_LINK_CTL_LABIE 0x0800 -#define PCIR_EXPRESS_LINK_STA 0x12 -#define PCIM_LINK_STA_SPEED 0x000f -#define PCIM_LINK_STA_WIDTH 0x03f0 -#define PCIM_LINK_STA_TRAINING_ERROR 0x0400 -#define PCIM_LINK_STA_TRAINING 0x0800 -#define PCIM_LINK_STA_SLOT_CLOCK 0x1000 -#define PCIM_LINK_STA_DL_ACTIVE 0x2000 -#define PCIM_LINK_STA_LINK_BW_MGMT 0x4000 -#define PCIM_LINK_STA_LINK_AUTO_BW 0x8000 -#define PCIR_EXPRESS_SLOT_CAP 0x14 -#define PCIM_EXP_SLOT_CAP_APB 0x00000001 -#define PCIM_EXP_SLOT_CAP_PCP 0x00000002 -#define PCIM_EXP_SLOT_CAP_MRLSP 0x00000004 -#define PCIM_EXP_SLOT_CAP_AIP 0x00000008 -#define PCIM_EXP_SLOT_CAP_PIP 0x00000010 -#define PCIM_EXP_SLOT_CAP_HPS 0x00000020 -#define PCIM_EXP_SLOT_CAP_HPC 0x00000040 -#define PCIM_EXP_SLOT_CAP_SPLV 0x00007f80 -#define PCIM_EXP_SLOT_CAP_SPLS 0x00018000 -#define PCIM_EXP_SLOT_CAP_EIP 0x00020000 -#define PCIM_EXP_SLOT_CAP_NCCS 0x00040000 -#define PCIM_EXP_SLOT_CAP_PSN 0xfff80000 -#define PCIR_EXPRESS_SLOT_CTL 0x18 -#define PCIM_EXP_SLOT_CTL_ABPE 0x0001 -#define PCIM_EXP_SLOT_CTL_PFDE 0x0002 -#define PCIM_EXP_SLOT_CTL_MRLSCE 0x0004 -#define PCIM_EXP_SLOT_CTL_PDCE 0x0008 -#define PCIM_EXP_SLOT_CTL_CCIE 0x0010 -#define PCIM_EXP_SLOT_CTL_HPIE 0x0020 -#define PCIM_EXP_SLOT_CTL_AIC 0x00c0 -#define PCIM_EXP_SLOT_CTL_PIC 0x0300 -#define PCIM_EXP_SLOT_CTL_PCC 0x0400 -#define PCIM_EXP_SLOT_CTL_EIC 0x0800 -#define PCIM_EXP_SLOT_CTL_DLLSCE 0x1000 -#define PCIR_EXPRESS_SLOT_STA 0x1a -#define PCIM_EXP_SLOT_STA_ABP 0x0001 -#define PCIM_EXP_SLOT_STA_PFD 0x0002 -#define PCIM_EXP_SLOT_STA_MRLSC 0x0004 -#define PCIM_EXP_SLOT_STA_PDC 0x0008 -#define PCIM_EXP_SLOT_STA_CC 0x0010 -#define PCIM_EXP_SLOT_STA_MRLSS 0x0020 -#define PCIM_EXP_SLOT_STA_PDS 0x0040 -#define PCIM_EXP_SLOT_STA_EIS 0x0080 -#define PCIM_EXP_SLOT_STA_DLLSC 0x0100 -#define PCIR_EXPRESS_ROOT_CTL 0x1c -#define PCIR_EXPRESS_ROOT_CAP 0x1e -#define PCIR_EXPRESS_ROOT_STA 0x20 -#define PCIR_EXPRESS_DEVICE_CAP2 0x24 -#define PCIR_EXPRESS_DEVICE_CTL2 0x28 -#define PCIM_EXP_CTL2_COMP_TIMEOUT_VAL 0x000f -#define PCIM_EXP_CTL2_COMP_TIMEOUT_DIS 0x0010 -#define PCIM_EXP_CTL2_ARI 0x0020 -#define PCIM_EXP_CTL2_ATOMIC_REQ_ENABLE 0x0040 -#define PCIM_EXP_CTL2_ATOMIC_EGR_BLOCK 0x0080 -#define PCIM_EXP_CTL2_ID_ORDERED_REQ_EN 0x0100 -#define PCIM_EXP_CTL2_ID_ORDERED_CMP_EN 0x0200 -#define PCIM_EXP_CTL2_LTR_ENABLE 0x0400 -#define PCIM_EXP_CTL2_OBFF 0x6000 -#define PCIM_EXP_OBFF_DISABLE 0x0000 -#define PCIM_EXP_OBFF_MSGA_ENABLE 0x2000 -#define PCIM_EXP_OBFF_MSGB_ENABLE 0x4000 -#define PCIM_EXP_OBFF_WAKE_ENABLE 0x6000 -#define PCIM_EXP_CTL2_END2END_TLP 0x8000 -#define PCIR_EXPRESS_DEVICE_STA2 0x2a -#define PCIR_EXPRESS_LINK_CAP2 0x2c -#define PCIR_EXPRESS_LINK_CTL2 0x30 -#define PCIR_EXPRESS_LINK_STA2 0x32 -#define PCIR_EXPRESS_SLOT_CAP2 0x34 -#define PCIR_EXPRESS_SLOT_CTL2 0x38 -#define PCIR_EXPRESS_SLOT_STA2 0x3a +#define PCIER_FLAGS 0x2 +#define PCIEM_FLAGS_VERSION 0x000F +#define PCIEM_FLAGS_TYPE 0x00F0 +#define PCIEM_TYPE_ENDPOINT 0x0000 +#define PCIEM_TYPE_LEGACY_ENDPOINT 0x0010 +#define PCIEM_TYPE_ROOT_PORT 0x0040 +#define PCIEM_TYPE_UPSTREAM_PORT 0x0050 +#define PCIEM_TYPE_DOWNSTREAM_PORT 0x0060 +#define PCIEM_TYPE_PCI_BRIDGE 0x0070 +#define PCIEM_TYPE_PCIE_BRIDGE 0x0080 +#define PCIEM_TYPE_ROOT_INT_EP 0x0090 +#define PCIEM_TYPE_ROOT_EC 0x00a0 +#define PCIEM_FLAGS_SLOT 0x0100 +#define PCIEM_FLAGS_IRQ 0x3e00 +#define PCIER_DEVICE_CAP 0x4 +#define PCIEM_CAP_MAX_PAYLOAD 0x00000007 +#define PCIEM_CAP_PHANTHOM_FUNCS 0x00000018 +#define PCIEM_CAP_EXT_TAG_FIELD 0x00000020 +#define PCIEM_CAP_L0S_LATENCY 0x000001c0 +#define PCIEM_CAP_L1_LATENCY 0x00000e00 +#define PCIEM_CAP_ROLE_ERR_RPT 0x00008000 +#define PCIEM_CAP_SLOT_PWR_LIM_VAL 0x03fc0000 +#define PCIEM_CAP_SLOT_PWR_LIM_SCALE 0x0c000000 +#define PCIEM_CAP_FLR 0x10000000 +#define PCIER_DEVICE_CTL 0x8 +#define PCIEM_CTL_COR_ENABLE 0x0001 +#define PCIEM_CTL_NFER_ENABLE 0x0002 +#define PCIEM_CTL_FER_ENABLE 0x0004 +#define PCIEM_CTL_URR_ENABLE 0x0008 +#define PCIEM_CTL_RELAXED_ORD_ENABLE 0x0010 +#define PCIEM_CTL_MAX_PAYLOAD 0x00e0 +#define PCIEM_CTL_EXT_TAG_FIELD 0x0100 +#define PCIEM_CTL_PHANTHOM_FUNCS 0x0200 +#define PCIEM_CTL_AUX_POWER_PM 0x0400 +#define PCIEM_CTL_NOSNOOP_ENABLE 0x0800 +#define PCIEM_CTL_MAX_READ_REQUEST 0x7000 +#define PCIEM_CTL_BRDG_CFG_RETRY 0x8000 /* PCI-E - PCI/PCI-X bridges */ +#define PCIEM_CTL_INITIATE_FLR 0x8000 /* FLR capable endpoints */ +#define PCIER_DEVICE_STA 0xa +#define PCIEM_STA_CORRECTABLE_ERROR 0x0001 +#define PCIEM_STA_NON_FATAL_ERROR 0x0002 +#define PCIEM_STA_FATAL_ERROR 0x0004 +#define PCIEM_STA_UNSUPPORTED_REQ 0x0008 +#define PCIEM_STA_AUX_POWER 0x0010 +#define PCIEM_STA_TRANSACTION_PND 0x0020 +#define PCIER_LINK_CAP 0xc +#define PCIEM_LINK_CAP_MAX_SPEED 0x0000000f +#define PCIEM_LINK_CAP_MAX_WIDTH 0x000003f0 +#define PCIEM_LINK_CAP_ASPM 0x00000c00 +#define PCIEM_LINK_CAP_L0S_EXIT 0x00007000 +#define PCIEM_LINK_CAP_L1_EXIT 0x00038000 +#define PCIEM_LINK_CAP_CLOCK_PM 0x00040000 +#define PCIEM_LINK_CAP_SURPRISE_DOWN 0x00080000 +#define PCIEM_LINK_CAP_DL_ACTIVE 0x00100000 +#define PCIEM_LINK_CAP_LINK_BW_NOTIFY 0x00200000 +#define PCIEM_LINK_CAP_ASPM_COMPLIANCE 0x00400000 +#define PCIEM_LINK_CAP_PORT 0xff000000 +#define PCIER_LINK_CTL 0x10 +#define PCIEM_LINK_CTL_ASPMC_DIS 0x0000 +#define PCIEM_LINK_CTL_ASPMC_L0S 0x0001 +#define PCIEM_LINK_CTL_ASPMC_L1 0x0002 +#define PCIEM_LINK_CTL_ASPMC 0x0003 +#define PCIEM_LINK_CTL_RCB 0x0008 +#define PCIEM_LINK_CTL_LINK_DIS 0x0010 +#define PCIEM_LINK_CTL_RETRAIN_LINK 0x0020 +#define PCIEM_LINK_CTL_COMMON_CLOCK 0x0040 +#define PCIEM_LINK_CTL_EXTENDED_SYNC 0x0080 +#define PCIEM_LINK_CTL_ECPM 0x0100 +#define PCIEM_LINK_CTL_HAWD 0x0200 +#define PCIEM_LINK_CTL_LBMIE 0x0400 +#define PCIEM_LINK_CTL_LABIE 0x0800 +#define PCIER_LINK_STA 0x12 +#define PCIEM_LINK_STA_SPEED 0x000f +#define PCIEM_LINK_STA_WIDTH 0x03f0 +#define PCIEM_LINK_STA_TRAINING_ERROR 0x0400 +#define PCIEM_LINK_STA_TRAINING 0x0800 +#define PCIEM_LINK_STA_SLOT_CLOCK 0x1000 +#define PCIEM_LINK_STA_DL_ACTIVE 0x2000 +#define PCIEM_LINK_STA_LINK_BW_MGMT 0x4000 +#define PCIEM_LINK_STA_LINK_AUTO_BW 0x8000 +#define PCIER_SLOT_CAP 0x14 +#define PCIEM_SLOT_CAP_APB 0x00000001 +#define PCIEM_SLOT_CAP_PCP 0x00000002 +#define PCIEM_SLOT_CAP_MRLSP 0x00000004 +#define PCIEM_SLOT_CAP_AIP 0x00000008 +#define PCIEM_SLOT_CAP_PIP 0x00000010 +#define PCIEM_SLOT_CAP_HPS 0x00000020 +#define PCIEM_SLOT_CAP_HPC 0x00000040 +#define PCIEM_SLOT_CAP_SPLV 0x00007f80 +#define PCIEM_SLOT_CAP_SPLS 0x00018000 +#define PCIEM_SLOT_CAP_EIP 0x00020000 +#define PCIEM_SLOT_CAP_NCCS 0x00040000 +#define PCIEM_SLOT_CAP_PSN 0xfff80000 +#define PCIER_SLOT_CTL 0x18 +#define PCIEM_SLOT_CTL_ABPE 0x0001 +#define PCIEM_SLOT_CTL_PFDE 0x0002 +#define PCIEM_SLOT_CTL_MRLSCE 0x0004 +#define PCIEM_SLOT_CTL_PDCE 0x0008 +#define PCIEM_SLOT_CTL_CCIE 0x0010 +#define PCIEM_SLOT_CTL_HPIE 0x0020 +#define PCIEM_SLOT_CTL_AIC 0x00c0 +#define PCIEM_SLOT_CTL_PIC 0x0300 +#define PCIEM_SLOT_CTL_PCC 0x0400 +#define PCIEM_SLOT_CTL_EIC 0x0800 +#define PCIEM_SLOT_CTL_DLLSCE 0x1000 +#define PCIER_SLOT_STA 0x1a +#define PCIEM_SLOT_STA_ABP 0x0001 +#define PCIEM_SLOT_STA_PFD 0x0002 +#define PCIEM_SLOT_STA_MRLSC 0x0004 +#define PCIEM_SLOT_STA_PDC 0x0008 +#define PCIEM_SLOT_STA_CC 0x0010 +#define PCIEM_SLOT_STA_MRLSS 0x0020 +#define PCIEM_SLOT_STA_PDS 0x0040 +#define PCIEM_SLOT_STA_EIS 0x0080 +#define PCIEM_SLOT_STA_DLLSC 0x0100 +#define PCIER_ROOT_CTL 0x1c +#define PCIER_ROOT_CAP 0x1e +#define PCIER_ROOT_STA 0x20 +#define PCIER_DEVICE_CAP2 0x24 +#define PCIER_DEVICE_CTL2 0x28 +#define PCIEM_CTL2_COMP_TIMEOUT_VAL 0x000f +#define PCIEM_CTL2_COMP_TIMEOUT_DIS 0x0010 +#define PCIEM_CTL2_ARI 0x0020 +#define PCIEM_CTL2_ATOMIC_REQ_ENABLE 0x0040 +#define PCIEM_CTL2_ATOMIC_EGR_BLOCK 0x0080 +#define PCIEM_CTL2_ID_ORDERED_REQ_EN 0x0100 +#define PCIEM_CTL2_ID_ORDERED_CMP_EN 0x0200 +#define PCIEM_CTL2_LTR_ENABLE 0x0400 +#define PCIEM_CTL2_OBFF 0x6000 +#define PCIEM_OBFF_DISABLE 0x0000 +#define PCIEM_OBFF_MSGA_ENABLE 0x2000 +#define PCIEM_OBFF_MSGB_ENABLE 0x4000 +#define PCIEM_OBFF_WAKE_ENABLE 0x6000 +#define PCIEM_CTL2_END2END_TLP 0x8000 +#define PCIER_DEVICE_STA2 0x2a +#define PCIER_LINK_CAP2 0x2c +#define PCIER_LINK_CTL2 0x30 +#define PCIER_LINK_STA2 0x32 +#define PCIER_SLOT_CAP2 0x34 +#define PCIER_SLOT_CTL2 0x38 +#define PCIER_SLOT_STA2 0x3a /* MSI-X definitions */ #define PCIR_MSIX_CTRL 0x2 diff --git a/sys/dev/re/if_re.c b/sys/dev/re/if_re.c index 493bfaa4909e..006731080f27 100644 --- a/sys/dev/re/if_re.c +++ b/sys/dev/re/if_re.c @@ -1343,14 +1343,14 @@ re_attach(device_t dev) /* Disable ASPM L0S/L1. */ if (sc->rl_expcap != 0) { cap = pci_read_config(dev, sc->rl_expcap + - PCIR_EXPRESS_LINK_CAP, 2); - if ((cap & PCIM_LINK_CAP_ASPM) != 0) { + PCIER_LINK_CAP, 2); + if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { ctl = pci_read_config(dev, sc->rl_expcap + - PCIR_EXPRESS_LINK_CTL, 2); + PCIER_LINK_CTL, 2); if ((ctl & 0x0003) != 0) { ctl &= ~0x0003; pci_write_config(dev, sc->rl_expcap + - PCIR_EXPRESS_LINK_CTL, ctl, 2); + PCIER_LINK_CTL, ctl, 2); device_printf(dev, "ASPM disabled\n"); } } else diff --git a/sys/ofed/include/linux/pci.h b/sys/ofed/include/linux/pci.h index f9828ef3a282..b05f6f27c512 100644 --- a/sys/ofed/include/linux/pci.h +++ b/sys/ofed/include/linux/pci.h @@ -82,8 +82,8 @@ struct pci_device_id { #define PCI_VENDOR_ID PCIR_DEVVENDOR #define PCI_COMMAND PCIR_COMMAND -#define PCI_EXP_DEVCTL PCIR_EXPRESS_DEVICE_CTL -#define PCI_EXP_LNKCTL PCIR_EXPRESS_LINK_CTL +#define PCI_EXP_DEVCTL PCIER_DEVICE_CTL +#define PCI_EXP_LNKCTL PCIER_LINK_CTL #define IORESOURCE_MEM SYS_RES_MEMORY #define IORESOURCE_IO SYS_RES_IOPORT diff --git a/sys/powerpc/mpc85xx/pci_fdt.c b/sys/powerpc/mpc85xx/pci_fdt.c index c431d66d0a5a..724384d5707f 100644 --- a/sys/powerpc/mpc85xx/pci_fdt.c +++ b/sys/powerpc/mpc85xx/pci_fdt.c @@ -848,10 +848,10 @@ fsl_pcib_err_init(device_t dev) 0xffffffff); dsr = fsl_pcib_cfgread(sc, 0, 0, 0, - sc->sc_pcie_capreg + PCIR_EXPRESS_DEVICE_STA, 2); + sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2); if (dsr) fsl_pcib_cfgwrite(sc, 0, 0, 0, - sc->sc_pcie_capreg + PCIR_EXPRESS_DEVICE_STA, + sc->sc_pcie_capreg + PCIER_DEVICE_STA, 0xffff, 2); /* Enable all errors reporting */ @@ -861,11 +861,11 @@ fsl_pcib_err_init(device_t dev) /* Enable error reporting: URR, FER, NFER */ dcr = fsl_pcib_cfgread(sc, 0, 0, 0, - sc->sc_pcie_capreg + PCIR_EXPRESS_DEVICE_CTL, 4); - dcr |= PCIM_EXP_CTL_URR_ENABLE | PCIM_EXP_CTL_FER_ENABLE | - PCIM_EXP_CTL_NFER_ENABLE; + sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4); + dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE | + PCIEM_CTL_NFER_ENABLE; fsl_pcib_cfgwrite(sc, 0, 0, 0, - sc->sc_pcie_capreg + PCIR_EXPRESS_DEVICE_CTL, dcr, 4); + sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4); } } diff --git a/usr.sbin/pciconf/cap.c b/usr.sbin/pciconf/cap.c index 77f116caedfd..0dff0b234271 100644 --- a/usr.sbin/pciconf/cap.c +++ b/usr.sbin/pciconf/cap.c @@ -369,55 +369,55 @@ cap_express(int fd, struct pci_conf *p, uint8_t ptr) uint32_t val; uint16_t flags; - flags = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_FLAGS, 2); - printf("PCI-Express %d ", flags & PCIM_EXP_FLAGS_VERSION); - switch (flags & PCIM_EXP_FLAGS_TYPE) { - case PCIM_EXP_TYPE_ENDPOINT: + flags = read_config(fd, &p->pc_sel, ptr + PCIER_FLAGS, 2); + printf("PCI-Express %d ", flags & PCIEM_FLAGS_VERSION); + switch (flags & PCIEM_FLAGS_TYPE) { + case PCIEM_TYPE_ENDPOINT: printf("endpoint"); break; - case PCIM_EXP_TYPE_LEGACY_ENDPOINT: + case PCIEM_TYPE_LEGACY_ENDPOINT: printf("legacy endpoint"); break; - case PCIM_EXP_TYPE_ROOT_PORT: + case PCIEM_TYPE_ROOT_PORT: printf("root port"); break; - case PCIM_EXP_TYPE_UPSTREAM_PORT: + case PCIEM_TYPE_UPSTREAM_PORT: printf("upstream port"); break; - case PCIM_EXP_TYPE_DOWNSTREAM_PORT: + case PCIEM_TYPE_DOWNSTREAM_PORT: printf("downstream port"); break; - case PCIM_EXP_TYPE_PCI_BRIDGE: + case PCIEM_TYPE_PCI_BRIDGE: printf("PCI bridge"); break; - case PCIM_EXP_TYPE_PCIE_BRIDGE: + case PCIEM_TYPE_PCIE_BRIDGE: printf("PCI to PCIe bridge"); break; - case PCIM_EXP_TYPE_ROOT_INT_EP: + case PCIEM_TYPE_ROOT_INT_EP: printf("root endpoint"); break; - case PCIM_EXP_TYPE_ROOT_EC: + case PCIEM_TYPE_ROOT_EC: printf("event collector"); break; default: - printf("type %d", (flags & PCIM_EXP_FLAGS_TYPE) >> 4); + printf("type %d", (flags & PCIEM_FLAGS_TYPE) >> 4); break; } - if (flags & PCIM_EXP_FLAGS_SLOT) + if (flags & PCIEM_FLAGS_SLOT) printf(" slot"); - if (flags & PCIM_EXP_FLAGS_IRQ) - printf(" IRQ %d", (flags & PCIM_EXP_FLAGS_IRQ) >> 9); - val = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_DEVICE_CAP, 4); - flags = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_DEVICE_CTL, 2); + if (flags & PCIEM_FLAGS_IRQ) + printf(" IRQ %d", (flags & PCIEM_FLAGS_IRQ) >> 9); + val = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP, 4); + flags = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CTL, 2); printf(" max data %d(%d)", - MAX_PAYLOAD((flags & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5), - MAX_PAYLOAD(val & PCIM_EXP_CAP_MAX_PAYLOAD)); - if (val & PCIM_EXP_CAP_FLR) + MAX_PAYLOAD((flags & PCIEM_CTL_MAX_PAYLOAD) >> 5), + MAX_PAYLOAD(val & PCIEM_CAP_MAX_PAYLOAD)); + if (val & PCIEM_CAP_FLR) printf(" FLR"); - val = read_config(fd, &p->pc_sel, ptr + PCIR_EXPRESS_LINK_CAP, 4); - flags = read_config(fd, &p->pc_sel, ptr+ PCIR_EXPRESS_LINK_STA, 2); - printf(" link x%d(x%d)", (flags & PCIM_LINK_STA_WIDTH) >> 4, - (val & PCIM_LINK_CAP_MAX_WIDTH) >> 4); + val = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CAP, 4); + flags = read_config(fd, &p->pc_sel, ptr+ PCIER_LINK_STA, 2); + printf(" link x%d(x%d)", (flags & PCIEM_LINK_STA_WIDTH) >> 4, + (val & PCIEM_LINK_CAP_MAX_WIDTH) >> 4); } static void diff --git a/usr.sbin/pciconf/err.c b/usr.sbin/pciconf/err.c index 6b364f6c51db..b67d1f55e81b 100644 --- a/usr.sbin/pciconf/err.c +++ b/usr.sbin/pciconf/err.c @@ -63,18 +63,18 @@ static struct bit_table pci_status[] = { /* Error indicators in the PCI-Express device status register. */ static struct bit_table pcie_device_status[] = { - { PCIM_EXP_STA_CORRECTABLE_ERROR, "Correctable Error Detected" }, - { PCIM_EXP_STA_NON_FATAL_ERROR, "Non-Fatal Error Detected" }, - { PCIM_EXP_STA_FATAL_ERROR, "Fatal Error Detected" }, - { PCIM_EXP_STA_UNSUPPORTED_REQ, "Unsupported Request Detected" }, + { PCIEM_STA_CORRECTABLE_ERROR, "Correctable Error Detected" }, + { PCIEM_STA_NON_FATAL_ERROR, "Non-Fatal Error Detected" }, + { PCIEM_STA_FATAL_ERROR, "Fatal Error Detected" }, + { PCIEM_STA_UNSUPPORTED_REQ, "Unsupported Request Detected" }, { 0, NULL }, }; /* Valid error indicator bits in the PCI-Express device status register. */ -#define PCIE_ERRORS (PCIM_EXP_STA_CORRECTABLE_ERROR | \ - PCIM_EXP_STA_NON_FATAL_ERROR | \ - PCIM_EXP_STA_FATAL_ERROR | \ - PCIM_EXP_STA_UNSUPPORTED_REQ) +#define PCIE_ERRORS (PCIEM_STA_CORRECTABLE_ERROR | \ + PCIEM_STA_NON_FATAL_ERROR | \ + PCIEM_STA_FATAL_ERROR | \ + PCIEM_STA_UNSUPPORTED_REQ) /* AER Uncorrected errors. */ static struct bit_table aer_uc[] = { @@ -153,7 +153,7 @@ list_errors(int fd, struct pci_conf *p) return; /* Check for PCI-e errors. */ - sta = read_config(fd, &p->pc_sel, pcie + PCIR_EXPRESS_DEVICE_STA, 2); + sta = read_config(fd, &p->pc_sel, pcie + PCIER_DEVICE_STA, 2); print_bits("PCI-e errors", pcie_device_status, sta & PCIE_ERRORS); /* See if this device supports AER. */ |