diff options
44 files changed, 535 insertions, 2660 deletions
diff --git a/contrib/compiler-rt/lib/builtins/arm/aeabi_dcmp.S b/contrib/compiler-rt/lib/builtins/arm/aeabi_dcmp.S index 51539c0ac813..9fa78b461248 100644 --- a/contrib/compiler-rt/lib/builtins/arm/aeabi_dcmp.S +++ b/contrib/compiler-rt/lib/builtins/arm/aeabi_dcmp.S @@ -18,11 +18,20 @@ // } // } +#if defined(COMPILER_RT_ARMHF_TARGET) +# define CONVERT_DCMP_ARGS_TO_DF2_ARGS \ + vmov d0, r0, r1 SEPARATOR \ + vmov d1, r2, r3 +#else +# define CONVERT_DCMP_ARGS_TO_DF2_ARGS +#endif + #define DEFINE_AEABI_DCMP(cond) \ .syntax unified SEPARATOR \ .p2align 2 SEPARATOR \ DEFINE_COMPILERRT_FUNCTION(__aeabi_dcmp ## cond) \ push { r4, lr } SEPARATOR \ + CONVERT_DCMP_ARGS_TO_DF2_ARGS SEPARATOR \ bl SYMBOL_NAME(__ ## cond ## df2) SEPARATOR \ cmp r0, #0 SEPARATOR \ b ## cond 1f SEPARATOR \ diff --git a/contrib/compiler-rt/lib/builtins/arm/aeabi_fcmp.S b/contrib/compiler-rt/lib/builtins/arm/aeabi_fcmp.S index 8e7774b58974..ea5b96c21d57 100644 --- a/contrib/compiler-rt/lib/builtins/arm/aeabi_fcmp.S +++ b/contrib/compiler-rt/lib/builtins/arm/aeabi_fcmp.S @@ -18,11 +18,20 @@ // } // } +#if defined(COMPILER_RT_ARMHF_TARGET) +# define CONVERT_FCMP_ARGS_TO_SF2_ARGS \ + vmov s0, r0 SEPARATOR \ + vmov s1, r1 +#else +# define CONVERT_FCMP_ARGS_TO_SF2_ARGS +#endif + #define DEFINE_AEABI_FCMP(cond) \ .syntax unified SEPARATOR \ .p2align 2 SEPARATOR \ DEFINE_COMPILERRT_FUNCTION(__aeabi_fcmp ## cond) \ push { r4, lr } SEPARATOR \ + CONVERT_FCMP_ARGS_TO_SF2_ARGS SEPARATOR \ bl SYMBOL_NAME(__ ## cond ## sf2) SEPARATOR \ cmp r0, #0 SEPARATOR \ b ## cond 1f SEPARATOR \ diff --git a/contrib/compiler-rt/lib/esan/esan_sideline_linux.cpp b/contrib/compiler-rt/lib/esan/esan_sideline_linux.cpp index d04f5909d6a2..bc272dfe49f8 100644 --- a/contrib/compiler-rt/lib/esan/esan_sideline_linux.cpp +++ b/contrib/compiler-rt/lib/esan/esan_sideline_linux.cpp @@ -70,7 +70,7 @@ int SidelineThread::runSideline(void *Arg) { // Set up a signal handler on an alternate stack for safety. InternalScopedBuffer<char> StackMap(SigAltStackSize); - struct sigaltstack SigAltStack; + stack_t SigAltStack; SigAltStack.ss_sp = StackMap.data(); SigAltStack.ss_size = SigAltStackSize; SigAltStack.ss_flags = 0; diff --git a/contrib/compiler-rt/lib/profile/InstrProfilingNameVar.c b/contrib/compiler-rt/lib/profile/InstrProfilingNameVar.c index a0c448c679b5..264568fbc912 100644 --- a/contrib/compiler-rt/lib/profile/InstrProfilingNameVar.c +++ b/contrib/compiler-rt/lib/profile/InstrProfilingNameVar.c @@ -1,11 +1,11 @@ -//===- InstrProfilingNameVar.c - profile name variable setup --------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// +/*===- InstrProfilingNameVar.c - profile name variable setup -------------===*\ +|* +|* The LLVM Compiler Infrastructure +|* +|* This file is distributed under the University of Illinois Open Source +|* License. See LICENSE.TXT for details. +|* +\*===----------------------------------------------------------------------===*/ #include "InstrProfiling.h" diff --git a/contrib/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/contrib/llvm/include/llvm/CodeGen/SelectionDAGNodes.h index db42fb6c170c..051c93601d3f 100644 --- a/contrib/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/contrib/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -85,7 +85,10 @@ namespace ISD { /// If N is a BUILD_VECTOR node whose elements are all the same constant or /// undefined, return true and return the constant value in \p SplatValue. - bool isConstantSplatVector(const SDNode *N, APInt &SplatValue); + /// This sets \p SplatValue to the smallest possible splat unless AllowShrink + /// is set to false. + bool isConstantSplatVector(const SDNode *N, APInt &SplatValue, + bool AllowShrink = true); /// Return true if the specified node is a BUILD_VECTOR where all of the /// elements are ~0 or undef. diff --git a/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h index e102df5e913d..c46d1b04804c 100644 --- a/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -627,6 +627,7 @@ private: SDValue ScalarizeVecOp_CONCAT_VECTORS(SDNode *N); SDValue ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N); SDValue ScalarizeVecOp_VSELECT(SDNode *N); + SDValue ScalarizeVecOp_VSETCC(SDNode *N); SDValue ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo); SDValue ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo); diff --git a/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index ecb54e1e4b41..6aa3270883f0 100644 --- a/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/contrib/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -484,6 +484,9 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) { case ISD::VSELECT: Res = ScalarizeVecOp_VSELECT(N); break; + case ISD::SETCC: + Res = ScalarizeVecOp_VSETCC(N); + break; case ISD::STORE: Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); break; @@ -560,6 +563,36 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) { N->getOperand(2)); } +/// If the operand is a vector that needs to be scalarized then the +/// result must be v1i1, so just convert to a scalar SETCC and wrap +/// with a scalar_to_vector since the res type is legal if we got here +SDValue DAGTypeLegalizer::ScalarizeVecOp_VSETCC(SDNode *N) { + assert(N->getValueType(0).isVector() && + N->getOperand(0).getValueType().isVector() && + "Operand types must be vectors"); + assert(N->getValueType(0) == MVT::v1i1 && "Expected v1i1 type"); + + EVT VT = N->getValueType(0); + SDValue LHS = GetScalarizedVector(N->getOperand(0)); + SDValue RHS = GetScalarizedVector(N->getOperand(1)); + + EVT OpVT = N->getOperand(0).getValueType(); + EVT NVT = VT.getVectorElementType(); + SDLoc DL(N); + // Turn it into a scalar SETCC. + SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, + N->getOperand(2)); + + // Vectors may have a different boolean contents to scalars. Promote the + // value appropriately. + ISD::NodeType ExtendCode = + TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT)); + + Res = DAG.getNode(ExtendCode, DL, NVT, Res); + + return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Res); +} + /// If the value to store is a vector that needs to be scalarized, it must be /// <1 x ty>. Just store the element. SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){ diff --git a/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 0ff154784f68..16f425dc7969 100644 --- a/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/contrib/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -116,7 +116,8 @@ bool ConstantFPSDNode::isValueValidForType(EVT VT, // ISD Namespace //===----------------------------------------------------------------------===// -bool ISD::isConstantSplatVector(const SDNode *N, APInt &SplatVal) { +bool ISD::isConstantSplatVector(const SDNode *N, APInt &SplatVal, + bool AllowShrink) { auto *BV = dyn_cast<BuildVectorSDNode>(N); if (!BV) return false; @@ -124,9 +125,11 @@ bool ISD::isConstantSplatVector(const SDNode *N, APInt &SplatVal) { APInt SplatUndef; unsigned SplatBitSize; bool HasUndefs; - EVT EltVT = N->getValueType(0).getVectorElementType(); - return BV->isConstantSplat(SplatVal, SplatUndef, SplatBitSize, HasUndefs) && - EltVT.getSizeInBits() >= SplatBitSize; + unsigned EltSize = N->getValueType(0).getVectorElementType().getSizeInBits(); + unsigned MinSplatBits = AllowShrink ? 0 : EltSize; + return BV->isConstantSplat(SplatVal, SplatUndef, SplatBitSize, HasUndefs, + MinSplatBits) && + EltSize >= SplatBitSize; } // FIXME: AllOnes and AllZeros duplicate a lot of code. Could these be diff --git a/contrib/llvm/lib/IR/AutoUpgrade.cpp b/contrib/llvm/lib/IR/AutoUpgrade.cpp index 6a4b8032ffd5..a501799b4799 100644 --- a/contrib/llvm/lib/IR/AutoUpgrade.cpp +++ b/contrib/llvm/lib/IR/AutoUpgrade.cpp @@ -2239,14 +2239,14 @@ bool llvm::UpgradeDebugInfo(Module &M) { } bool llvm::UpgradeModuleFlags(Module &M) { - const NamedMDNode *ModFlags = M.getModuleFlagsMetadata(); + NamedMDNode *ModFlags = M.getModuleFlagsMetadata(); if (!ModFlags) return false; - bool HasObjCFlag = false, HasClassProperties = false; + bool HasObjCFlag = false, HasClassProperties = false, Changed = false; for (unsigned I = 0, E = ModFlags->getNumOperands(); I != E; ++I) { MDNode *Op = ModFlags->getOperand(I); - if (Op->getNumOperands() < 2) + if (Op->getNumOperands() != 3) continue; MDString *ID = dyn_cast_or_null<MDString>(Op->getOperand(1)); if (!ID) @@ -2255,7 +2255,24 @@ bool llvm::UpgradeModuleFlags(Module &M) { HasObjCFlag = true; if (ID->getString() == "Objective-C Class Properties") HasClassProperties = true; + // Upgrade PIC/PIE Module Flags. The module flag behavior for these two + // field was Error and now they are Max. + if (ID->getString() == "PIC Level" || ID->getString() == "PIE Level") { + if (auto *Behavior = + mdconst::dyn_extract_or_null<ConstantInt>(Op->getOperand(0))) { + if (Behavior->getLimitedValue() == Module::Error) { + Type *Int32Ty = Type::getInt32Ty(M.getContext()); + Metadata *Ops[3] = { + ConstantAsMetadata::get(ConstantInt::get(Int32Ty, Module::Max)), + MDString::get(M.getContext(), ID->getString()), + Op->getOperand(2)}; + ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops)); + Changed = true; + } + } + } } + // "Objective-C Class Properties" is recently added for Objective-C. We // upgrade ObjC bitcodes to contain a "Objective-C Class Properties" module // flag of value 0, so we can correclty downgrade this flag when trying to @@ -2264,9 +2281,10 @@ bool llvm::UpgradeModuleFlags(Module &M) { if (HasObjCFlag && !HasClassProperties) { M.addModuleFlag(llvm::Module::Override, "Objective-C Class Properties", (uint32_t)0); - return true; + Changed = true; } - return false; + + return Changed; } static bool isOldLoopArgument(Metadata *MD) { diff --git a/contrib/llvm/lib/Object/COFFModuleDefinition.cpp b/contrib/llvm/lib/Object/COFFModuleDefinition.cpp index ed9140d1fe08..510eac8b239b 100644 --- a/contrib/llvm/lib/Object/COFFModuleDefinition.cpp +++ b/contrib/llvm/lib/Object/COFFModuleDefinition.cpp @@ -232,7 +232,13 @@ private: for (;;) { read(); if (Tok.K == Identifier && Tok.Value[0] == '@') { - Tok.Value.drop_front().getAsInteger(10, E.Ordinal); + if (Tok.Value.drop_front().getAsInteger(10, E.Ordinal)) { + // Not an ordinal modifier at all, but the next export (fastcall + // decorated) - complete the current one. + unget(); + Info.Exports.push_back(E); + return Error::success(); + } read(); if (Tok.K == KwNoname) { E.Noname = true; diff --git a/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp b/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp index 6ba7593543a9..27dda93387b6 100644 --- a/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/contrib/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -5901,7 +5901,10 @@ static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { return false; for (unsigned i = 0; i < M.size(); i += NumElts) { - WhichResult = M[i] == 0 ? 0 : 1; + if (M.size() == NumElts * 2) + WhichResult = i / NumElts; + else + WhichResult = M[i] == 0 ? 0 : 1; for (unsigned j = 0; j < NumElts; ++j) { if (M[i+j] >= 0 && (unsigned) M[i+j] != 2 * j + WhichResult) return false; @@ -5932,7 +5935,10 @@ static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){ unsigned Half = NumElts / 2; for (unsigned i = 0; i < M.size(); i += NumElts) { - WhichResult = M[i] == 0 ? 0 : 1; + if (M.size() == NumElts * 2) + WhichResult = i / NumElts; + else + WhichResult = M[i] == 0 ? 0 : 1; for (unsigned j = 0; j < NumElts; j += Half) { unsigned Idx = WhichResult; for (unsigned k = 0; k < Half; ++k) { @@ -5972,7 +5978,10 @@ static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { return false; for (unsigned i = 0; i < M.size(); i += NumElts) { - WhichResult = M[i] == 0 ? 0 : 1; + if (M.size() == NumElts * 2) + WhichResult = i / NumElts; + else + WhichResult = M[i] == 0 ? 0 : 1; unsigned Idx = WhichResult * NumElts / 2; for (unsigned j = 0; j < NumElts; j += 2) { if ((M[i+j] >= 0 && (unsigned) M[i+j] != Idx) || @@ -6005,7 +6014,10 @@ static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){ return false; for (unsigned i = 0; i < M.size(); i += NumElts) { - WhichResult = M[i] == 0 ? 0 : 1; + if (M.size() == NumElts * 2) + WhichResult = i / NumElts; + else + WhichResult = M[i] == 0 ? 0 : 1; unsigned Idx = WhichResult * NumElts / 2; for (unsigned j = 0; j < NumElts; j += 2) { if ((M[i+j] >= 0 && (unsigned) M[i+j] != Idx) || @@ -8793,6 +8805,8 @@ ARMTargetLowering::EmitLowered__chkstk(MachineInstr &MI, .addReg(ARM::R4, RegState::Implicit | RegState::Kill) .addReg(ARM::R4, RegState::Implicit | RegState::Define) .addReg(ARM::R12, + RegState::Implicit | RegState::Define | RegState::Dead) + .addReg(ARM::CPSR, RegState::Implicit | RegState::Define | RegState::Dead); break; case CodeModel::Large: @@ -8808,6 +8822,8 @@ ARMTargetLowering::EmitLowered__chkstk(MachineInstr &MI, .addReg(ARM::R4, RegState::Implicit | RegState::Kill) .addReg(ARM::R4, RegState::Implicit | RegState::Define) .addReg(ARM::R12, + RegState::Implicit | RegState::Define | RegState::Dead) + .addReg(ARM::CPSR, RegState::Implicit | RegState::Define | RegState::Dead); break; } diff --git a/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp b/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp index 1e73122cdc38..193ee8de6192 100644 --- a/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/contrib/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -29540,8 +29540,9 @@ static bool detectZextAbsDiff(const SDValue &Select, SDValue &Op0, // In SetLT case, The second operand of the comparison can be either 1 or 0. APInt SplatVal; if ((CC == ISD::SETLT) && - !((ISD::isConstantSplatVector(SetCC.getOperand(1).getNode(), SplatVal) && - SplatVal == 1) || + !((ISD::isConstantSplatVector(SetCC.getOperand(1).getNode(), SplatVal, + /*AllowShrink*/false) && + SplatVal.isOneValue()) || (ISD::isBuildVectorAllZeros(SetCC.getOperand(1).getNode())))) return false; @@ -30628,6 +30629,9 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG, // Byte blends are only available in AVX2 if (VT == MVT::v32i8 && !Subtarget.hasAVX2()) return SDValue(); + // There are no 512-bit blend instructions that use sign bits. + if (VT.is512BitVector()) + return SDValue(); assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size"); APInt DemandedMask(APInt::getSignMask(BitWidth)); @@ -32058,7 +32062,8 @@ static SDValue combineAndMaskToShift(SDNode *N, SelectionDAG &DAG, return SDValue(); APInt SplatVal; - if (!ISD::isConstantSplatVector(Op1.getNode(), SplatVal) || + if (!ISD::isConstantSplatVector(Op1.getNode(), SplatVal, + /*AllowShrink*/false) || !SplatVal.isMask()) return SDValue(); @@ -32642,7 +32647,8 @@ static SDValue detectUSatPattern(SDValue In, EVT VT) { "Unexpected types for truncate operation"); APInt C; - if (ISD::isConstantSplatVector(In.getOperand(1).getNode(), C)) { + if (ISD::isConstantSplatVector(In.getOperand(1).getNode(), C, + /*AllowShrink*/false)) { // C should be equal to UINT32_MAX / UINT16_MAX / UINT8_MAX according // the element size of the destination type. return C.isMask(VT.getScalarSizeInBits()) ? In.getOperand(0) : @@ -35346,7 +35352,8 @@ static SDValue combineIncDecVector(SDNode *N, SelectionDAG &DAG) { SDNode *N1 = N->getOperand(1).getNode(); APInt SplatVal; - if (!ISD::isConstantSplatVector(N1, SplatVal) || !SplatVal.isOneValue()) + if (!ISD::isConstantSplatVector(N1, SplatVal, /*AllowShrink*/false) || + !SplatVal.isOneValue()) return SDValue(); SDValue AllOnesVec = getOnesVector(VT, DAG, SDLoc(N)); diff --git a/contrib/llvm/lib/Target/X86/X86InstrAVX512.td b/contrib/llvm/lib/Target/X86/X86InstrAVX512.td index 0e654a380e7c..0ae960e7d566 100644 --- a/contrib/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/contrib/llvm/lib/Target/X86/X86InstrAVX512.td @@ -3619,8 +3619,8 @@ let Predicates = [HasVLX] in { def : Pat<(alignedstore256 (v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))), addr:$dst), (VMOVAPDZ256mr addr:$dst, (v4f64 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>; - def : Pat<(alignedstore (v8f32 (extract_subvector - (v16f32 VR512:$src), (iPTR 0))), addr:$dst), + def : Pat<(alignedstore256 (v8f32 (extract_subvector + (v16f32 VR512:$src), (iPTR 0))), addr:$dst), (VMOVAPSZ256mr addr:$dst, (v8f32 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>; def : Pat<(alignedstore256 (v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))), addr:$dst), diff --git a/contrib/llvm/lib/Target/X86/X86SchedSandyBridge.td b/contrib/llvm/lib/Target/X86/X86SchedSandyBridge.td index 6d85ca6cad64..b8ec5883152c 100644 --- a/contrib/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/contrib/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -24,8 +24,8 @@ def SandyBridgeModel : SchedMachineModel { // Based on the LSD (loop-stream detector) queue size. let LoopMicroOpBufferSize = 28; - // This flag is set to allow the scheduler to assign - // a default model to unrecognized opcodes. + // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow + // the scheduler to assign a default model to unrecognized opcodes. let CompleteModel = 0; } @@ -48,7 +48,6 @@ def SBPort23 : ProcResource<2>; def SBPort4 : ProcResource<1>; // Many micro-ops are capable of issuing on multiple ports. -def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>; def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>; def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; @@ -116,10 +115,10 @@ def : WriteRes<WriteIDivLd, [SBPort23, SBPort0, SBDivider]> { // Scalar and vector floating point. defm : SBWriteResPair<WriteFAdd, SBPort1, 3>; defm : SBWriteResPair<WriteFMul, SBPort0, 5>; -defm : SBWriteResPair<WriteFDiv, SBPort0, 24>; +defm : SBWriteResPair<WriteFDiv, SBPort0, 12>; // 10-14 cycles. defm : SBWriteResPair<WriteFRcp, SBPort0, 5>; defm : SBWriteResPair<WriteFRsqrt, SBPort0, 5>; -defm : SBWriteResPair<WriteFSqrt, SBPort0, 14>; +defm : SBWriteResPair<WriteFSqrt, SBPort0, 15>; defm : SBWriteResPair<WriteCvtF2I, SBPort1, 3>; defm : SBWriteResPair<WriteCvtI2F, SBPort1, 4>; defm : SBWriteResPair<WriteCvtF2F, SBPort1, 3>; @@ -135,11 +134,11 @@ def : WriteRes<WriteFVarBlendLd, [SBPort0, SBPort5, SBPort23]> { } // Vector integer operations. -defm : SBWriteResPair<WriteVecShift, SBPort5, 1>; -defm : SBWriteResPair<WriteVecLogic, SBPort5, 1>; -defm : SBWriteResPair<WriteVecALU, SBPort1, 3>; +defm : SBWriteResPair<WriteVecShift, SBPort05, 1>; +defm : SBWriteResPair<WriteVecLogic, SBPort015, 1>; +defm : SBWriteResPair<WriteVecALU, SBPort15, 1>; defm : SBWriteResPair<WriteVecIMul, SBPort0, 5>; -defm : SBWriteResPair<WriteShuffle, SBPort5, 1>; +defm : SBWriteResPair<WriteShuffle, SBPort15, 1>; defm : SBWriteResPair<WriteBlend, SBPort15, 1>; def : WriteRes<WriteVarBlend, [SBPort1, SBPort5]> { let Latency = 2; @@ -149,15 +148,13 @@ def : WriteRes<WriteVarBlendLd, [SBPort1, SBPort5, SBPort23]> { let Latency = 6; let ResourceCycles = [1, 1, 1]; } -def : WriteRes<WriteMPSAD, [SBPort0,SBPort15]> { - let Latency = 5; - let NumMicroOps = 3; - let ResourceCycles = [1,2]; +def : WriteRes<WriteMPSAD, [SBPort0, SBPort1, SBPort5]> { + let Latency = 6; + let ResourceCycles = [1, 1, 1]; } -def : WriteRes<WriteMPSADLd, [SBPort0,SBPort23,SBPort15]> { - let Latency = 11; - let NumMicroOps = 4; - let ResourceCycles = [1,1,2]; +def : WriteRes<WriteMPSADLd, [SBPort0, SBPort1, SBPort5, SBPort23]> { + let Latency = 6; + let ResourceCycles = [1, 1, 1, 1]; } //////////////////////////////////////////////////////////////////////////////// @@ -207,15 +204,13 @@ def : WriteRes<WritePCmpEStrMLd, [SBPort015, SBPort23]> { } // Packed Compare Implicit Length Strings, Return Index -def : WriteRes<WritePCmpIStrI, [SBPort0]> { - let Latency = 11; - let NumMicroOps = 3; +def : WriteRes<WritePCmpIStrI, [SBPort015]> { + let Latency = 3; let ResourceCycles = [3]; } -def : WriteRes<WritePCmpIStrILd, [SBPort0,SBPort23]> { - let Latency = 17; - let NumMicroOps = 4; - let ResourceCycles = [3,1]; +def : WriteRes<WritePCmpIStrILd, [SBPort015, SBPort23]> { + let Latency = 3; + let ResourceCycles = [3, 1]; } // Packed Compare Explicit Length Strings, Return Index @@ -229,26 +224,22 @@ def : WriteRes<WritePCmpEStrILd, [SBPort015, SBPort23]> { } // AES Instructions. -def : WriteRes<WriteAESDecEnc, [SBPort5,SBPort015]> { - let Latency = 7; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; +def : WriteRes<WriteAESDecEnc, [SBPort015]> { + let Latency = 8; + let ResourceCycles = [2]; } -def : WriteRes<WriteAESDecEncLd, [SBPort5,SBPort23,SBPort015]> { - let Latency = 13; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; +def : WriteRes<WriteAESDecEncLd, [SBPort015, SBPort23]> { + let Latency = 8; + let ResourceCycles = [2, 1]; } -def : WriteRes<WriteAESIMC, [SBPort5]> { - let Latency = 12; - let NumMicroOps = 2; +def : WriteRes<WriteAESIMC, [SBPort015]> { + let Latency = 8; let ResourceCycles = [2]; } -def : WriteRes<WriteAESIMCLd, [SBPort5,SBPort23]> { - let Latency = 18; - let NumMicroOps = 3; - let ResourceCycles = [2,1]; +def : WriteRes<WriteAESIMCLd, [SBPort015, SBPort23]> { + let Latency = 8; + let ResourceCycles = [2, 1]; } def : WriteRes<WriteAESKeyGen, [SBPort015]> { @@ -281,2407 +272,4 @@ def : WriteRes<WriteNop, []>; defm : SBWriteResPair<WriteFShuffle256, SBPort0, 1>; defm : SBWriteResPair<WriteShuffle256, SBPort0, 1>; defm : SBWriteResPair<WriteVarVecShift, SBPort0, 1>; - -// Remaining SNB instrs. - -def SBWriteResGroup0 : SchedWriteRes<[SBPort0]> { - let Latency = 1; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup0], (instregex "CVTSS2SDrr")>; -def: InstRW<[SBWriteResGroup0], (instregex "PSLLDri")>; -def: InstRW<[SBWriteResGroup0], (instregex "PSLLQri")>; -def: InstRW<[SBWriteResGroup0], (instregex "PSLLWri")>; -def: InstRW<[SBWriteResGroup0], (instregex "PSRADri")>; -def: InstRW<[SBWriteResGroup0], (instregex "PSRAWri")>; -def: InstRW<[SBWriteResGroup0], (instregex "PSRLDri")>; -def: InstRW<[SBWriteResGroup0], (instregex "PSRLQri")>; -def: InstRW<[SBWriteResGroup0], (instregex "PSRLWri")>; -def: InstRW<[SBWriteResGroup0], (instregex "VCVTSS2SDrr")>; -def: InstRW<[SBWriteResGroup0], (instregex "VPMOVMSKBrr")>; -def: InstRW<[SBWriteResGroup0], (instregex "VPSLLDri")>; -def: InstRW<[SBWriteResGroup0], (instregex "VPSLLQri")>; -def: InstRW<[SBWriteResGroup0], (instregex "VPSLLWri")>; -def: InstRW<[SBWriteResGroup0], (instregex "VPSRADri")>; -def: InstRW<[SBWriteResGroup0], (instregex "VPSRAWri")>; -def: InstRW<[SBWriteResGroup0], (instregex "VPSRLDri")>; -def: InstRW<[SBWriteResGroup0], (instregex "VPSRLQri")>; -def: InstRW<[SBWriteResGroup0], (instregex "VPSRLWri")>; -def: InstRW<[SBWriteResGroup0], (instregex "VTESTPDYrr")>; -def: InstRW<[SBWriteResGroup0], (instregex "VTESTPDrr")>; -def: InstRW<[SBWriteResGroup0], (instregex "VTESTPSYrr")>; -def: InstRW<[SBWriteResGroup0], (instregex "VTESTPSrr")>; - -def SBWriteResGroup1 : SchedWriteRes<[SBPort1]> { - let Latency = 1; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup1], (instregex "COMP_FST0r")>; -def: InstRW<[SBWriteResGroup1], (instregex "COM_FST0r")>; -def: InstRW<[SBWriteResGroup1], (instregex "UCOM_FPr")>; -def: InstRW<[SBWriteResGroup1], (instregex "UCOM_Fr")>; - -def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> { - let Latency = 1; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup2], (instregex "ANDNPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "ANDNPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "ANDPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "ANDPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "FDECSTP")>; -def: InstRW<[SBWriteResGroup2], (instregex "FFREE")>; -def: InstRW<[SBWriteResGroup2], (instregex "FINCSTP")>; -def: InstRW<[SBWriteResGroup2], (instregex "FNOP")>; -def: InstRW<[SBWriteResGroup2], (instregex "INSERTPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "JMP64r")>; -def: InstRW<[SBWriteResGroup2], (instregex "LD_Frr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOV64toPQIrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVAPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVAPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVDDUPrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVDI2PDIrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVHLPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVLHPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVSDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVSHDUPrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVSLDUPrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVSSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVUPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "MOVUPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "ORPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "ORPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "RETQ")>; -def: InstRW<[SBWriteResGroup2], (instregex "SHUFPDrri")>; -def: InstRW<[SBWriteResGroup2], (instregex "SHUFPSrri")>; -def: InstRW<[SBWriteResGroup2], (instregex "ST_FPrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "ST_Frr")>; -def: InstRW<[SBWriteResGroup2], (instregex "UNPCKHPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "UNPCKHPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "UNPCKLPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "UNPCKLPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VANDNPDYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VANDNPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VANDNPSYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VANDNPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VANDPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VANDPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VANDPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VEXTRACTF128rr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VINSERTF128rr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VINSERTPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOV64toPQIrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOV64toPQIrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVAPDYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVAPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVAPSYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVAPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVDDUPYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVDDUPrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVHLPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVHLPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVSDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVSHDUPYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVSHDUPrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVSLDUPYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVSLDUPrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVSSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVUPDYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVUPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVUPSYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VMOVUPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VORPDYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VORPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VORPSYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VORPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPDri")>; -def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPDrm")>; -def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPSri")>; -def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPSrm")>; -def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VPERMILPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VSHUFPDYrri")>; -def: InstRW<[SBWriteResGroup2], (instregex "VSHUFPDrri")>; -def: InstRW<[SBWriteResGroup2], (instregex "VSHUFPSYrri")>; -def: InstRW<[SBWriteResGroup2], (instregex "VSHUFPSrri")>; -def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKHPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKHPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKLPDYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKLPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKLPSYrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VUNPCKLPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VXORPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "VXORPSrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "XORPDrr")>; -def: InstRW<[SBWriteResGroup2], (instregex "XORPSrr")>; - -def SBWriteResGroup3 : SchedWriteRes<[SBPort01]> { - let Latency = 1; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup3], (instregex "LEA64_32r")>; - -def SBWriteResGroup4 : SchedWriteRes<[SBPort0]> { - let Latency = 1; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup4], (instregex "BLENDPDrri")>; -def: InstRW<[SBWriteResGroup4], (instregex "BLENDPSrri")>; -def: InstRW<[SBWriteResGroup4], (instregex "BT32ri8")>; -def: InstRW<[SBWriteResGroup4], (instregex "BT32rr")>; -def: InstRW<[SBWriteResGroup4], (instregex "BTC32ri8")>; -def: InstRW<[SBWriteResGroup4], (instregex "BTC32rr")>; -def: InstRW<[SBWriteResGroup4], (instregex "BTR32ri8")>; -def: InstRW<[SBWriteResGroup4], (instregex "BTR32rr")>; -def: InstRW<[SBWriteResGroup4], (instregex "BTS32ri8")>; -def: InstRW<[SBWriteResGroup4], (instregex "BTS32rr")>; -def: InstRW<[SBWriteResGroup4], (instregex "CDQ")>; -def: InstRW<[SBWriteResGroup4], (instregex "CQO")>; -def: InstRW<[SBWriteResGroup4], (instregex "LAHF")>; -def: InstRW<[SBWriteResGroup4], (instregex "SAHF")>; -def: InstRW<[SBWriteResGroup4], (instregex "SAR32ri")>; -def: InstRW<[SBWriteResGroup4], (instregex "SAR8ri")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETAEr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETBr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETEr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETGEr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETGr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETLEr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETLr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETNEr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETNOr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETNPr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETNSr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETOr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETPr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SETSr")>; -def: InstRW<[SBWriteResGroup4], (instregex "SHL32ri")>; -def: InstRW<[SBWriteResGroup4], (instregex "SHL64r1")>; -def: InstRW<[SBWriteResGroup4], (instregex "SHL8r1")>; -def: InstRW<[SBWriteResGroup4], (instregex "SHL8ri")>; -def: InstRW<[SBWriteResGroup4], (instregex "SHR32ri")>; -def: InstRW<[SBWriteResGroup4], (instregex "SHR8ri")>; -def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPDYrri")>; -def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPDrri")>; -def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPSYrri")>; -def: InstRW<[SBWriteResGroup4], (instregex "VBLENDPSrri")>; -def: InstRW<[SBWriteResGroup4], (instregex "VMOVDQAYrr")>; -def: InstRW<[SBWriteResGroup4], (instregex "VMOVDQArr")>; -def: InstRW<[SBWriteResGroup4], (instregex "VMOVDQUYrr")>; -def: InstRW<[SBWriteResGroup4], (instregex "VMOVDQUrr")>; - -def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> { - let Latency = 1; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup5], (instregex "KORTESTBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSBrr64")>; -def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSDrr64")>; -def: InstRW<[SBWriteResGroup5], (instregex "MMX_PABSWrr64")>; -def: InstRW<[SBWriteResGroup5], (instregex "MMX_PADDQirr")>; -def: InstRW<[SBWriteResGroup5], (instregex "MMX_PALIGNR64irr")>; -def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSHUFBrr64")>; -def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNBrr64")>; -def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNDrr64")>; -def: InstRW<[SBWriteResGroup5], (instregex "MMX_PSIGNWrr64")>; -def: InstRW<[SBWriteResGroup5], (instregex "PABSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PABSDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PABSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PACKSSDWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PACKSSWBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PACKUSDWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PACKUSWBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PADDBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PADDDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PADDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PADDSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PADDSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PADDUSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PADDUSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PADDWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PALIGNRrri")>; -def: InstRW<[SBWriteResGroup5], (instregex "PAVGBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PAVGWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PBLENDWrri")>; -def: InstRW<[SBWriteResGroup5], (instregex "PCMPEQBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PCMPEQDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PCMPEQQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PCMPEQWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PCMPGTBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PCMPGTDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PCMPGTWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMAXSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMAXSDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMAXSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMAXUBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMAXUDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMAXUWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMINSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMINSDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMINSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMINUBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMINUDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMINUWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXBDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXBQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXBWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXWDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVSXWQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXBDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXBQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXBWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXWDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PMOVZXWQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSHUFBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSHUFDri")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSHUFHWri")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSHUFLWri")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSIGNBrr128")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSIGNDrr128")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSIGNWrr128")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSLLDQri")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSRLDQri")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSUBBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSUBDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSUBQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSUBSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSUBSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSUBUSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSUBUSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PSUBWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKHBWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKHDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKHQDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKHWDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKLBWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKLDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKLQDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "PUNPCKLWDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VMASKMOVPSYrm")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPABSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPABSDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPABSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPACKSSDWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPACKSSWBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPACKUSDWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPACKUSWBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPADDBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPADDDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPADDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPADDUSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPADDUSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPALIGNRrri")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPAVGBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPAVGWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPBLENDWrri")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPCMPEQBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPCMPEQDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPCMPEQWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPCMPGTBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPCMPGTDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPCMPGTWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMAXSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMAXSDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMAXSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMAXUBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMAXUDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMAXUWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMINSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMINSDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMINSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMINUBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMINUDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMINUWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXBDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXBQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXBWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXWDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVSXWQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXBDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXBQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXBWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXWDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPMOVZXWQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSHUFBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSHUFDri")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSHUFLWri")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNBrr128")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNDrr128")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSIGNWrr128")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSLLDQri")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSRLDQri")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSUBBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSUBDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSUBQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSUBSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSUBSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSUBUSBrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSUBUSWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPSUBWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKHBWrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKHDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKHWDrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKLDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKLQDQrr")>; -def: InstRW<[SBWriteResGroup5], (instregex "VPUNPCKLWDrr")>; - -def SBWriteResGroup6 : SchedWriteRes<[SBPort015]> { - let Latency = 1; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup6], (instregex "ADD32ri8")>; -def: InstRW<[SBWriteResGroup6], (instregex "ADD32rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "ADD8ri")>; -def: InstRW<[SBWriteResGroup6], (instregex "ADD8rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "AND32ri")>; -def: InstRW<[SBWriteResGroup6], (instregex "AND64ri8")>; -def: InstRW<[SBWriteResGroup6], (instregex "AND64rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "AND8ri")>; -def: InstRW<[SBWriteResGroup6], (instregex "AND8rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "CBW")>; -def: InstRW<[SBWriteResGroup6], (instregex "CMC")>; -def: InstRW<[SBWriteResGroup6], (instregex "CMP16ri8")>; -def: InstRW<[SBWriteResGroup6], (instregex "CMP32i32")>; -def: InstRW<[SBWriteResGroup6], (instregex "CMP64rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "CMP8ri")>; -def: InstRW<[SBWriteResGroup6], (instregex "CMP8rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "CWDE")>; -def: InstRW<[SBWriteResGroup6], (instregex "DEC64r")>; -def: InstRW<[SBWriteResGroup6], (instregex "DEC8r")>; -def: InstRW<[SBWriteResGroup6], (instregex "INC64r")>; -def: InstRW<[SBWriteResGroup6], (instregex "INC8r")>; -def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVD64from64rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVQ2DQrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "MOV32rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "MOV8ri")>; -def: InstRW<[SBWriteResGroup6], (instregex "MOV8rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "MOVDQArr")>; -def: InstRW<[SBWriteResGroup6], (instregex "MOVDQUrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "MOVPQI2QIrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "MOVSX32rr16")>; -def: InstRW<[SBWriteResGroup6], (instregex "MOVSX32rr8")>; -def: InstRW<[SBWriteResGroup6], (instregex "MOVZX32rr16")>; -def: InstRW<[SBWriteResGroup6], (instregex "MOVZX32rr8")>; -def: InstRW<[SBWriteResGroup6], (instregex "NEG64r")>; -def: InstRW<[SBWriteResGroup6], (instregex "NEG8r")>; -def: InstRW<[SBWriteResGroup6], (instregex "NOT64r")>; -def: InstRW<[SBWriteResGroup6], (instregex "NOT8r")>; -def: InstRW<[SBWriteResGroup6], (instregex "OR64ri8")>; -def: InstRW<[SBWriteResGroup6], (instregex "OR64rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "OR8ri")>; -def: InstRW<[SBWriteResGroup6], (instregex "OR8rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "PANDNrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "PANDrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "PORrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "PXORrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "STC")>; -def: InstRW<[SBWriteResGroup6], (instregex "SUB64ri8")>; -def: InstRW<[SBWriteResGroup6], (instregex "SUB64rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "SUB8ri")>; -def: InstRW<[SBWriteResGroup6], (instregex "SUB8rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "TEST64rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "TEST8ri")>; -def: InstRW<[SBWriteResGroup6], (instregex "TEST8rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "VMOVPQI2QIrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "VMOVZPQILo2PQIrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "VPANDNrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "VPANDrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "VPORrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "VPXORrr")>; -def: InstRW<[SBWriteResGroup6], (instregex "XOR32rr")>; -def: InstRW<[SBWriteResGroup6], (instregex "XOR64ri8")>; -def: InstRW<[SBWriteResGroup6], (instregex "XOR8ri")>; -def: InstRW<[SBWriteResGroup6], (instregex "XOR8rr")>; - -def SBWriteResGroup7 : SchedWriteRes<[SBPort0]> { - let Latency = 2; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup7], (instregex "MOVMSKPDrr")>; -def: InstRW<[SBWriteResGroup7], (instregex "MOVMSKPSrr")>; -def: InstRW<[SBWriteResGroup7], (instregex "MOVPDI2DIrr")>; -def: InstRW<[SBWriteResGroup7], (instregex "MOVPQIto64rr")>; -def: InstRW<[SBWriteResGroup7], (instregex "PMOVMSKBrr")>; -def: InstRW<[SBWriteResGroup7], (instregex "VMOVMSKPDYrr")>; -def: InstRW<[SBWriteResGroup7], (instregex "VMOVMSKPDrr")>; -def: InstRW<[SBWriteResGroup7], (instregex "VMOVMSKPSrr")>; -def: InstRW<[SBWriteResGroup7], (instregex "VMOVPDI2DIrr")>; -def: InstRW<[SBWriteResGroup7], (instregex "VMOVPQIto64rr")>; - -def SBWriteResGroup9 : SchedWriteRes<[SBPort0]> { - let Latency = 2; - let NumMicroOps = 2; - let ResourceCycles = [2]; -} -def: InstRW<[SBWriteResGroup9], (instregex "BLENDVPDrr0")>; -def: InstRW<[SBWriteResGroup9], (instregex "BLENDVPSrr0")>; -def: InstRW<[SBWriteResGroup9], (instregex "ROL32ri")>; -def: InstRW<[SBWriteResGroup9], (instregex "ROL8ri")>; -def: InstRW<[SBWriteResGroup9], (instregex "ROR32ri")>; -def: InstRW<[SBWriteResGroup9], (instregex "ROR8ri")>; -def: InstRW<[SBWriteResGroup9], (instregex "SETAr")>; -def: InstRW<[SBWriteResGroup9], (instregex "SETBEr")>; -def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPDYrr")>; -def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPDrr")>; -def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPSYrr")>; -def: InstRW<[SBWriteResGroup9], (instregex "VBLENDVPSrr")>; - -def SBWriteResGroup10 : SchedWriteRes<[SBPort15]> { - let Latency = 2; - let NumMicroOps = 2; - let ResourceCycles = [2]; -} -def: InstRW<[SBWriteResGroup10], (instregex "VPBLENDVBrr")>; - -def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> { - let Latency = 2; - let NumMicroOps = 2; - let ResourceCycles = [2]; -} -def: InstRW<[SBWriteResGroup11], (instregex "SCASB")>; -def: InstRW<[SBWriteResGroup11], (instregex "SCASL")>; -def: InstRW<[SBWriteResGroup11], (instregex "SCASQ")>; -def: InstRW<[SBWriteResGroup11], (instregex "SCASW")>; - -def SBWriteResGroup12 : SchedWriteRes<[SBPort0,SBPort1]> { - let Latency = 2; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup12], (instregex "COMISDrr")>; -def: InstRW<[SBWriteResGroup12], (instregex "COMISSrr")>; -def: InstRW<[SBWriteResGroup12], (instregex "UCOMISDrr")>; -def: InstRW<[SBWriteResGroup12], (instregex "UCOMISSrr")>; -def: InstRW<[SBWriteResGroup12], (instregex "VCOMISDrr")>; -def: InstRW<[SBWriteResGroup12], (instregex "VCOMISSrr")>; -def: InstRW<[SBWriteResGroup12], (instregex "VUCOMISDrr")>; -def: InstRW<[SBWriteResGroup12], (instregex "VUCOMISSrr")>; - -def SBWriteResGroup13 : SchedWriteRes<[SBPort0,SBPort5]> { - let Latency = 2; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup13], (instregex "CVTPS2PDrr")>; -def: InstRW<[SBWriteResGroup13], (instregex "PTESTrr")>; -def: InstRW<[SBWriteResGroup13], (instregex "VCVTPS2PDYrr")>; -def: InstRW<[SBWriteResGroup13], (instregex "VCVTPS2PDrr")>; -def: InstRW<[SBWriteResGroup13], (instregex "VPTESTYrr")>; -def: InstRW<[SBWriteResGroup13], (instregex "VPTESTrr")>; - -def SBWriteResGroup14 : SchedWriteRes<[SBPort0,SBPort15]> { - let Latency = 2; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup14], (instregex "PSLLDrr")>; -def: InstRW<[SBWriteResGroup14], (instregex "PSLLQrr")>; -def: InstRW<[SBWriteResGroup14], (instregex "PSLLWrr")>; -def: InstRW<[SBWriteResGroup14], (instregex "PSRADrr")>; -def: InstRW<[SBWriteResGroup14], (instregex "PSRAWrr")>; -def: InstRW<[SBWriteResGroup14], (instregex "PSRLDrr")>; -def: InstRW<[SBWriteResGroup14], (instregex "PSRLQrr")>; -def: InstRW<[SBWriteResGroup14], (instregex "PSRLWrr")>; -def: InstRW<[SBWriteResGroup14], (instregex "VPSRADrr")>; -def: InstRW<[SBWriteResGroup14], (instregex "VPSRAWrr")>; -def: InstRW<[SBWriteResGroup14], (instregex "VPSRLDrr")>; -def: InstRW<[SBWriteResGroup14], (instregex "VPSRLQrr")>; -def: InstRW<[SBWriteResGroup14], (instregex "VPSRLWrr")>; - -def SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> { - let Latency = 2; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup15], (instregex "FNSTSW16r")>; - -def SBWriteResGroup16 : SchedWriteRes<[SBPort1,SBPort0]> { - let Latency = 2; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup16], (instregex "BSWAP32r")>; - -def SBWriteResGroup17 : SchedWriteRes<[SBPort5,SBPort15]> { - let Latency = 2; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup17], (instregex "PINSRBrr")>; -def: InstRW<[SBWriteResGroup17], (instregex "PINSRDrr")>; -def: InstRW<[SBWriteResGroup17], (instregex "PINSRQrr")>; -def: InstRW<[SBWriteResGroup17], (instregex "PINSRWrri")>; -def: InstRW<[SBWriteResGroup17], (instregex "VPINSRBrr")>; -def: InstRW<[SBWriteResGroup17], (instregex "VPINSRDrr")>; -def: InstRW<[SBWriteResGroup17], (instregex "VPINSRQrr")>; -def: InstRW<[SBWriteResGroup17], (instregex "VPINSRWrri")>; - -def SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> { - let Latency = 2; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup18], (instregex "MMX_MOVDQ2Qrr")>; - -def SBWriteResGroup19 : SchedWriteRes<[SBPort0,SBPort015]> { - let Latency = 2; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup19], (instregex "ADC64ri8")>; -def: InstRW<[SBWriteResGroup19], (instregex "ADC64rr")>; -def: InstRW<[SBWriteResGroup19], (instregex "ADC8ri")>; -def: InstRW<[SBWriteResGroup19], (instregex "ADC8rr")>; -def: InstRW<[SBWriteResGroup19], (instregex "CMOVAE32rr")>; -def: InstRW<[SBWriteResGroup19], (instregex "CMOVB32rr")>; -def: InstRW<[SBWriteResGroup19], (instregex "CMOVE32rr")>; -def: InstRW<[SBWriteResGroup19], (instregex "CMOVG32rr")>; -def: InstRW<[SBWriteResGroup19], (instregex "CMOVGE32rr")>; -def: InstRW<[SBWriteResGroup19], (instregex "CMOVL32rr")>; -def: InstRW<[SBWriteResGroup19], (instregex "CMOVLE32rr")>; -def: InstRW<[SBWriteResGroup19], (instregex "CMOVNE32rr")>; -def: InstRW<[SBWriteResGroup19], (instregex "CMOVNO32rr")>; -def: InstRW<[SBWriteResGroup19], (instregex "CMOVNP32rr")>; -def: InstRW<[SBWriteResGroup19], (instregex "CMOVNS32rr")>; -def: InstRW<[SBWriteResGroup19], (instregex "CMOVO32rr")>; -def: InstRW<[SBWriteResGroup19], (instregex "CMOVP32rr")>; -def: InstRW<[SBWriteResGroup19], (instregex "CMOVS32rr")>; -def: InstRW<[SBWriteResGroup19], (instregex "SBB32rr")>; -def: InstRW<[SBWriteResGroup19], (instregex "SBB64ri8")>; -def: InstRW<[SBWriteResGroup19], (instregex "SBB8ri")>; -def: InstRW<[SBWriteResGroup19], (instregex "SBB8rr")>; -def: InstRW<[SBWriteResGroup19], (instregex "SHLD32rri8")>; -def: InstRW<[SBWriteResGroup19], (instregex "SHRD32rri8")>; - -def SBWriteResGroup20 : SchedWriteRes<[SBPort0]> { - let Latency = 3; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMADDUBSWrr64")>; -def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMULHRSWrr64")>; -def: InstRW<[SBWriteResGroup20], (instregex "MMX_PMULUDQirr")>; -def: InstRW<[SBWriteResGroup20], (instregex "PMADDUBSWrr")>; -def: InstRW<[SBWriteResGroup20], (instregex "PMADDWDrr")>; -def: InstRW<[SBWriteResGroup20], (instregex "PMULDQrr")>; -def: InstRW<[SBWriteResGroup20], (instregex "PMULHRSWrr")>; -def: InstRW<[SBWriteResGroup20], (instregex "PMULHUWrr")>; -def: InstRW<[SBWriteResGroup20], (instregex "PMULHWrr")>; -def: InstRW<[SBWriteResGroup20], (instregex "PMULLDrr")>; -def: InstRW<[SBWriteResGroup20], (instregex "PMULLWrr")>; -def: InstRW<[SBWriteResGroup20], (instregex "PMULUDQrr")>; -def: InstRW<[SBWriteResGroup20], (instregex "PSADBWrr")>; -def: InstRW<[SBWriteResGroup20], (instregex "VMOVMSKPSYrr")>; -def: InstRW<[SBWriteResGroup20], (instregex "VPMADDUBSWrr")>; -def: InstRW<[SBWriteResGroup20], (instregex "VPMADDWDrr")>; -def: InstRW<[SBWriteResGroup20], (instregex "VPMULDQrr")>; -def: InstRW<[SBWriteResGroup20], (instregex "VPMULHRSWrr")>; -def: InstRW<[SBWriteResGroup20], (instregex "VPMULHWrr")>; -def: InstRW<[SBWriteResGroup20], (instregex "VPMULLDrr")>; -def: InstRW<[SBWriteResGroup20], (instregex "VPMULLWrr")>; -def: InstRW<[SBWriteResGroup20], (instregex "VPSADBWrr")>; - -def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> { - let Latency = 3; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup21], (instregex "ADDPDrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "ADDPSrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "ADDSDrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "ADDSSrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "ADDSUBPDrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "ADDSUBPSrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "ADD_FPrST0")>; -def: InstRW<[SBWriteResGroup21], (instregex "ADD_FST0r")>; -def: InstRW<[SBWriteResGroup21], (instregex "ADD_FrST0")>; -def: InstRW<[SBWriteResGroup21], (instregex "BSF32rr")>; -def: InstRW<[SBWriteResGroup21], (instregex "BSR32rr")>; -def: InstRW<[SBWriteResGroup21], (instregex "CMPPDrri")>; -def: InstRW<[SBWriteResGroup21], (instregex "CMPPSrri")>; -def: InstRW<[SBWriteResGroup21], (instregex "CMPSDrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "CMPSSrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "CRC32r32r32")>; -def: InstRW<[SBWriteResGroup21], (instregex "CRC32r32r8")>; -def: InstRW<[SBWriteResGroup21], (instregex "CVTDQ2PSrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "CVTPS2DQrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "CVTTPS2DQrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "MAXPDrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "MAXPSrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "MAXSDrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "MAXSSrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "MINPDrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "MINPSrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "MINSDrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "MINSSrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "MMX_CVTPI2PSirr")>; -def: InstRW<[SBWriteResGroup21], (instregex "MMX_CVTPS2PIirr")>; -def: InstRW<[SBWriteResGroup21], (instregex "MMX_CVTTPS2PIirr")>; -def: InstRW<[SBWriteResGroup21], (instregex "MUL8r")>; -def: InstRW<[SBWriteResGroup21], (instregex "POPCNT32rr")>; -def: InstRW<[SBWriteResGroup21], (instregex "ROUNDPDr")>; -def: InstRW<[SBWriteResGroup21], (instregex "ROUNDPSr")>; -def: InstRW<[SBWriteResGroup21], (instregex "ROUNDSDr")>; -def: InstRW<[SBWriteResGroup21], (instregex "ROUNDSSr")>; -def: InstRW<[SBWriteResGroup21], (instregex "SUBPDrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "SUBPSrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "SUBR_FPrST0")>; -def: InstRW<[SBWriteResGroup21], (instregex "SUBR_FST0r")>; -def: InstRW<[SBWriteResGroup21], (instregex "SUBR_FrST0")>; -def: InstRW<[SBWriteResGroup21], (instregex "SUBSDrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "SUBSSrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "SUB_FPrST0")>; -def: InstRW<[SBWriteResGroup21], (instregex "SUB_FST0r")>; -def: InstRW<[SBWriteResGroup21], (instregex "SUB_FrST0")>; -def: InstRW<[SBWriteResGroup21], (instregex "VADDPDYrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VADDPDrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VADDPSYrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VADDPSrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VADDSDrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VADDSSrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VADDSUBPDYrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VADDSUBPDrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VADDSUBPSYrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VADDSUBPSrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VBROADCASTF128")>; -def: InstRW<[SBWriteResGroup21], (instregex "VCMPPDYrri")>; -def: InstRW<[SBWriteResGroup21], (instregex "VCMPPDrri")>; -def: InstRW<[SBWriteResGroup21], (instregex "VCMPPSYrri")>; -def: InstRW<[SBWriteResGroup21], (instregex "VCMPPSrri")>; -def: InstRW<[SBWriteResGroup21], (instregex "VCMPSDrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VCMPSSrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VCVTDQ2PSYrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VCVTDQ2PSrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VCVTPS2DQYrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VCVTPS2DQrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VCVTTPS2DQrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VMAXPDYrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VMAXPDrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VMAXPSYrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VMAXPSrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VMAXSDrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VMAXSSrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VMINPDrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VMINPSrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VMINSDrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VMINSSrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VROUNDPDr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VROUNDPSr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VROUNDSDr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VSUBPDYrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VSUBPDrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VSUBPSYrr")>; -def: InstRW<[SBWriteResGroup21], (instregex "VSUBPSrr")>; - -def SBWriteResGroup22 : SchedWriteRes<[SBPort0,SBPort5]> { - let Latency = 3; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup22], (instregex "EXTRACTPSrr")>; -def: InstRW<[SBWriteResGroup22], (instregex "VEXTRACTPSrr")>; - -def SBWriteResGroup23 : SchedWriteRes<[SBPort0,SBPort15]> { - let Latency = 3; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup23], (instregex "PEXTRBrr")>; -def: InstRW<[SBWriteResGroup23], (instregex "PEXTRDrr")>; -def: InstRW<[SBWriteResGroup23], (instregex "PEXTRQrr")>; -def: InstRW<[SBWriteResGroup23], (instregex "PEXTRWri")>; -def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRBrr")>; -def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRDrr")>; -def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRQrr")>; -def: InstRW<[SBWriteResGroup23], (instregex "VPEXTRWri")>; -def: InstRW<[SBWriteResGroup23], (instregex "SHL64rCL")>; -def: InstRW<[SBWriteResGroup23], (instregex "SHL8rCL")>; - -def SBWriteResGroup24 : SchedWriteRes<[SBPort15]> { - let Latency = 3; - let NumMicroOps = 3; - let ResourceCycles = [3]; -} -def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDSWrr64")>; -def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDWrr64")>; -def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDrr64")>; -def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBDrr64")>; -def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBSWrr64")>; -def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBWrr64")>; -def: InstRW<[SBWriteResGroup24], (instregex "PHADDDrr")>; -def: InstRW<[SBWriteResGroup24], (instregex "PHADDSWrr128")>; -def: InstRW<[SBWriteResGroup24], (instregex "PHADDWrr")>; -def: InstRW<[SBWriteResGroup24], (instregex "PHSUBDrr")>; -def: InstRW<[SBWriteResGroup24], (instregex "PHSUBSWrr128")>; -def: InstRW<[SBWriteResGroup24], (instregex "PHSUBWrr")>; -def: InstRW<[SBWriteResGroup24], (instregex "VPHADDDrr")>; -def: InstRW<[SBWriteResGroup24], (instregex "VPHADDSWrr128")>; -def: InstRW<[SBWriteResGroup24], (instregex "VPHADDWrr")>; -def: InstRW<[SBWriteResGroup24], (instregex "VPHSUBDrr")>; -def: InstRW<[SBWriteResGroup24], (instregex "VPHSUBSWrr128")>; -def: InstRW<[SBWriteResGroup24], (instregex "VPHSUBWrr")>; - -def SBWriteResGroup25 : SchedWriteRes<[SBPort015]> { - let Latency = 3; - let NumMicroOps = 3; - let ResourceCycles = [3]; -} -def: InstRW<[SBWriteResGroup25], (instregex "LEAVE64")>; -def: InstRW<[SBWriteResGroup25], (instregex "XADD32rr")>; -def: InstRW<[SBWriteResGroup25], (instregex "XADD8rr")>; - -def SBWriteResGroup26 : SchedWriteRes<[SBPort0,SBPort015]> { - let Latency = 3; - let NumMicroOps = 3; - let ResourceCycles = [2,1]; -} -def: InstRW<[SBWriteResGroup26], (instregex "CMOVA32rr")>; -def: InstRW<[SBWriteResGroup26], (instregex "CMOVBE32rr")>; - -def SBWriteResGroup27 : SchedWriteRes<[SBPort0,SBPort1]> { - let Latency = 4; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup27], (instregex "MUL64r")>; - -def SBWriteResGroup28 : SchedWriteRes<[SBPort1,SBPort5]> { - let Latency = 4; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup28], (instregex "CVTDQ2PDrr")>; -def: InstRW<[SBWriteResGroup28], (instregex "CVTPD2DQrr")>; -def: InstRW<[SBWriteResGroup28], (instregex "CVTPD2PSrr")>; -def: InstRW<[SBWriteResGroup28], (instregex "CVTSD2SSrr")>; -def: InstRW<[SBWriteResGroup28], (instregex "CVTSI2SD64rr")>; -def: InstRW<[SBWriteResGroup28], (instregex "CVTSI2SDrr")>; -def: InstRW<[SBWriteResGroup28], (instregex "CVTTPD2DQrr")>; -def: InstRW<[SBWriteResGroup28], (instregex "MMX_CVTPD2PIirr")>; -def: InstRW<[SBWriteResGroup28], (instregex "MMX_CVTPI2PDirr")>; -def: InstRW<[SBWriteResGroup28], (instregex "MMX_CVTTPD2PIirr")>; -def: InstRW<[SBWriteResGroup28], (instregex "VCVTDQ2PDYrr")>; -def: InstRW<[SBWriteResGroup28], (instregex "VCVTDQ2PDrr")>; -def: InstRW<[SBWriteResGroup28], (instregex "VCVTPD2DQYrr")>; -def: InstRW<[SBWriteResGroup28], (instregex "VCVTPD2DQrr")>; -def: InstRW<[SBWriteResGroup28], (instregex "VCVTPD2PSYrr")>; -def: InstRW<[SBWriteResGroup28], (instregex "VCVTPD2PSrr")>; -def: InstRW<[SBWriteResGroup28], (instregex "VCVTSI2SD64rr")>; -def: InstRW<[SBWriteResGroup28], (instregex "VCVTSI2SDrr")>; -def: InstRW<[SBWriteResGroup28], (instregex "VCVTTPD2DQYrr")>; -def: InstRW<[SBWriteResGroup28], (instregex "VCVTTPD2DQrr")>; - -def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> { - let Latency = 4; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup29], (instregex "MOV64sr")>; -def: InstRW<[SBWriteResGroup29], (instregex "PAUSE")>; - -def SBWriteResGroup30 : SchedWriteRes<[SBPort0]> { - let Latency = 5; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup30], (instregex "MULPDrr")>; -def: InstRW<[SBWriteResGroup30], (instregex "MULPSrr")>; -def: InstRW<[SBWriteResGroup30], (instregex "MULSDrr")>; -def: InstRW<[SBWriteResGroup30], (instregex "MULSSrr")>; -def: InstRW<[SBWriteResGroup30], (instregex "MUL_FPrST0")>; -def: InstRW<[SBWriteResGroup30], (instregex "MUL_FST0r")>; -def: InstRW<[SBWriteResGroup30], (instregex "MUL_FrST0")>; -def: InstRW<[SBWriteResGroup30], (instregex "PCMPGTQrr")>; -def: InstRW<[SBWriteResGroup30], (instregex "PHMINPOSUWrr128")>; -def: InstRW<[SBWriteResGroup30], (instregex "RCPPSr")>; -def: InstRW<[SBWriteResGroup30], (instregex "RCPSSr")>; -def: InstRW<[SBWriteResGroup30], (instregex "RSQRTPSr")>; -def: InstRW<[SBWriteResGroup30], (instregex "RSQRTSSr")>; -def: InstRW<[SBWriteResGroup30], (instregex "VMULPDYrr")>; -def: InstRW<[SBWriteResGroup30], (instregex "VMULPDrr")>; -def: InstRW<[SBWriteResGroup30], (instregex "VMULPSYrr")>; -def: InstRW<[SBWriteResGroup30], (instregex "VMULPSrr")>; -def: InstRW<[SBWriteResGroup30], (instregex "VMULSDrr")>; -def: InstRW<[SBWriteResGroup30], (instregex "VMULSSrr")>; -def: InstRW<[SBWriteResGroup30], (instregex "VPCMPGTQrr")>; -def: InstRW<[SBWriteResGroup30], (instregex "VPHMINPOSUWrr128")>; -def: InstRW<[SBWriteResGroup30], (instregex "VRSQRTPSr")>; -def: InstRW<[SBWriteResGroup30], (instregex "VRSQRTSSr")>; - -def SBWriteResGroup31 : SchedWriteRes<[SBPort23]> { - let Latency = 5; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup31], (instregex "MOV32rm")>; -def: InstRW<[SBWriteResGroup31], (instregex "MOV8rm")>; -def: InstRW<[SBWriteResGroup31], (instregex "MOVSX32rm16")>; -def: InstRW<[SBWriteResGroup31], (instregex "MOVSX32rm8")>; -def: InstRW<[SBWriteResGroup31], (instregex "MOVZX32rm16")>; -def: InstRW<[SBWriteResGroup31], (instregex "MOVZX32rm8")>; -def: InstRW<[SBWriteResGroup31], (instregex "PREFETCH")>; - -def SBWriteResGroup32 : SchedWriteRes<[SBPort0,SBPort1]> { - let Latency = 5; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup32], (instregex "CVTSD2SI64rr")>; -def: InstRW<[SBWriteResGroup32], (instregex "CVTSD2SIrr")>; -def: InstRW<[SBWriteResGroup32], (instregex "CVTSS2SI64rr")>; -def: InstRW<[SBWriteResGroup32], (instregex "CVTSS2SIrr")>; -def: InstRW<[SBWriteResGroup32], (instregex "CVTTSD2SI64rr")>; -def: InstRW<[SBWriteResGroup32], (instregex "CVTTSD2SIrr")>; -def: InstRW<[SBWriteResGroup32], (instregex "CVTTSS2SI64rr")>; -def: InstRW<[SBWriteResGroup32], (instregex "CVTTSS2SIrr")>; -def: InstRW<[SBWriteResGroup32], (instregex "VCVTSD2SI64rr")>; -def: InstRW<[SBWriteResGroup32], (instregex "VCVTSS2SI64rr")>; -def: InstRW<[SBWriteResGroup32], (instregex "VCVTSS2SIrr")>; -def: InstRW<[SBWriteResGroup32], (instregex "VCVTTSD2SI64rr")>; -def: InstRW<[SBWriteResGroup32], (instregex "VCVTTSD2SIrr")>; -def: InstRW<[SBWriteResGroup32], (instregex "VCVTTSS2SI64rr")>; -def: InstRW<[SBWriteResGroup32], (instregex "VCVTTSS2SIrr")>; - -def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> { - let Latency = 5; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup33], (instregex "MOV64mr")>; -def: InstRW<[SBWriteResGroup33], (instregex "MOV8mr")>; -def: InstRW<[SBWriteResGroup33], (instregex "MOVAPDmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "MOVAPSmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "MOVDQAmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "MOVDQUmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "MOVHPDmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "MOVHPSmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "MOVLPDmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "MOVLPSmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "MOVNTDQmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "MOVNTI_64mr")>; -def: InstRW<[SBWriteResGroup33], (instregex "MOVNTImr")>; -def: InstRW<[SBWriteResGroup33], (instregex "MOVNTPDmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "MOVNTPSmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "MOVPDI2DImr")>; -def: InstRW<[SBWriteResGroup33], (instregex "MOVPQI2QImr")>; -def: InstRW<[SBWriteResGroup33], (instregex "MOVPQIto64mr")>; -def: InstRW<[SBWriteResGroup33], (instregex "MOVSSmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "MOVUPDmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "MOVUPSmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "PUSH64i8")>; -def: InstRW<[SBWriteResGroup33], (instregex "PUSH64r")>; -def: InstRW<[SBWriteResGroup33], (instregex "VEXTRACTF128mr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVAPDYmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVAPDmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVAPSYmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVAPSmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVDQAYmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVDQAmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVDQUYmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVDQUmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVHPDmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVHPSmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVLPDmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVLPSmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTDQYmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTDQmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTPDYmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTPDmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTPSYmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVNTPSmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVPDI2DImr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVPQI2QImr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVPQIto64mr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVSDmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVSSmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVUPDYmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVUPDmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVUPSYmr")>; -def: InstRW<[SBWriteResGroup33], (instregex "VMOVUPSmr")>; - -def SBWriteResGroup34 : SchedWriteRes<[SBPort0,SBPort15]> { - let Latency = 5; - let NumMicroOps = 3; - let ResourceCycles = [1,2]; -} -def: InstRW<[SBWriteResGroup34], (instregex "MPSADBWrri")>; -def: InstRW<[SBWriteResGroup34], (instregex "VMPSADBWrri")>; - -def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> { - let Latency = 5; - let NumMicroOps = 3; - let ResourceCycles = [1,2]; -} -def: InstRW<[SBWriteResGroup35], (instregex "CLI")>; -def: InstRW<[SBWriteResGroup35], (instregex "CVTSI2SS64rr")>; -def: InstRW<[SBWriteResGroup35], (instregex "CVTSI2SSrr")>; -def: InstRW<[SBWriteResGroup35], (instregex "HADDPDrr")>; -def: InstRW<[SBWriteResGroup35], (instregex "HADDPSrr")>; -def: InstRW<[SBWriteResGroup35], (instregex "HSUBPDrr")>; -def: InstRW<[SBWriteResGroup35], (instregex "HSUBPSrr")>; -def: InstRW<[SBWriteResGroup35], (instregex "VCVTSI2SS64rr")>; -def: InstRW<[SBWriteResGroup35], (instregex "VCVTSI2SSrr")>; -def: InstRW<[SBWriteResGroup35], (instregex "VHADDPDrr")>; -def: InstRW<[SBWriteResGroup35], (instregex "VHADDPSYrr")>; -def: InstRW<[SBWriteResGroup35], (instregex "VHADDPSrr")>; -def: InstRW<[SBWriteResGroup35], (instregex "VHSUBPDYrr")>; -def: InstRW<[SBWriteResGroup35], (instregex "VHSUBPDrr")>; -def: InstRW<[SBWriteResGroup35], (instregex "VHSUBPSYrr")>; -def: InstRW<[SBWriteResGroup35], (instregex "VHSUBPSrr")>; - -def SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { - let Latency = 5; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup36], (instregex "CALL64r")>; -def: InstRW<[SBWriteResGroup36], (instregex "EXTRACTPSmr")>; -def: InstRW<[SBWriteResGroup36], (instregex "VEXTRACTPSmr")>; - -def SBWriteResGroup37 : SchedWriteRes<[SBPort4,SBPort01,SBPort23]> { - let Latency = 5; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup37], (instregex "VMASKMOVPDYrm")>; -def: InstRW<[SBWriteResGroup37], (instregex "VMASKMOVPDmr")>; -def: InstRW<[SBWriteResGroup37], (instregex "VMASKMOVPSmr")>; - -def SBWriteResGroup38 : SchedWriteRes<[SBPort4,SBPort23,SBPort0]> { - let Latency = 5; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup38], (instregex "SETAEm")>; -def: InstRW<[SBWriteResGroup38], (instregex "SETBm")>; -def: InstRW<[SBWriteResGroup38], (instregex "SETEm")>; -def: InstRW<[SBWriteResGroup38], (instregex "SETGEm")>; -def: InstRW<[SBWriteResGroup38], (instregex "SETGm")>; -def: InstRW<[SBWriteResGroup38], (instregex "SETLEm")>; -def: InstRW<[SBWriteResGroup38], (instregex "SETLm")>; -def: InstRW<[SBWriteResGroup38], (instregex "SETNEm")>; -def: InstRW<[SBWriteResGroup38], (instregex "SETNOm")>; -def: InstRW<[SBWriteResGroup38], (instregex "SETNPm")>; -def: InstRW<[SBWriteResGroup38], (instregex "SETNSm")>; -def: InstRW<[SBWriteResGroup38], (instregex "SETOm")>; -def: InstRW<[SBWriteResGroup38], (instregex "SETPm")>; -def: InstRW<[SBWriteResGroup38], (instregex "SETSm")>; - -def SBWriteResGroup39 : SchedWriteRes<[SBPort4,SBPort23,SBPort15]> { - let Latency = 5; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup39], (instregex "PEXTRBmr")>; -def: InstRW<[SBWriteResGroup39], (instregex "VPEXTRBmr")>; -def: InstRW<[SBWriteResGroup39], (instregex "VPEXTRDmr")>; -def: InstRW<[SBWriteResGroup39], (instregex "VPEXTRWmr")>; - -def SBWriteResGroup40 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { - let Latency = 5; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup40], (instregex "MOV8mi")>; -def: InstRW<[SBWriteResGroup40], (instregex "STOSB")>; -def: InstRW<[SBWriteResGroup40], (instregex "STOSL")>; -def: InstRW<[SBWriteResGroup40], (instregex "STOSQ")>; -def: InstRW<[SBWriteResGroup40], (instregex "STOSW")>; - -def SBWriteResGroup41 : SchedWriteRes<[SBPort5,SBPort015]> { - let Latency = 5; - let NumMicroOps = 4; - let ResourceCycles = [1,3]; -} -def: InstRW<[SBWriteResGroup41], (instregex "FNINIT")>; - -def SBWriteResGroup42 : SchedWriteRes<[SBPort0,SBPort015]> { - let Latency = 5; - let NumMicroOps = 4; - let ResourceCycles = [1,3]; -} -def: InstRW<[SBWriteResGroup42], (instregex "CMPXCHG32rr")>; -def: InstRW<[SBWriteResGroup42], (instregex "CMPXCHG8rr")>; - -def SBWriteResGroup43 : SchedWriteRes<[SBPort4,SBPort23,SBPort0]> { - let Latency = 5; - let NumMicroOps = 4; - let ResourceCycles = [1,1,2]; -} -def: InstRW<[SBWriteResGroup43], (instregex "SETAm")>; -def: InstRW<[SBWriteResGroup43], (instregex "SETBEm")>; - -def SBWriteResGroup44 : SchedWriteRes<[SBPort0,SBPort4,SBPort5,SBPort23]> { - let Latency = 5; - let NumMicroOps = 4; - let ResourceCycles = [1,1,1,1]; -} -def: InstRW<[SBWriteResGroup44], (instregex "LDMXCSR")>; -def: InstRW<[SBWriteResGroup44], (instregex "STMXCSR")>; -def: InstRW<[SBWriteResGroup44], (instregex "VLDMXCSR")>; -def: InstRW<[SBWriteResGroup44], (instregex "VSTMXCSR")>; - -def SBWriteResGroup45 : SchedWriteRes<[SBPort0,SBPort4,SBPort23,SBPort15]> { - let Latency = 5; - let NumMicroOps = 4; - let ResourceCycles = [1,1,1,1]; -} -def: InstRW<[SBWriteResGroup45], (instregex "PEXTRDmr")>; -def: InstRW<[SBWriteResGroup45], (instregex "PEXTRQmr")>; -def: InstRW<[SBWriteResGroup45], (instregex "VPEXTRQmr")>; -def: InstRW<[SBWriteResGroup45], (instregex "PUSHF16")>; -def: InstRW<[SBWriteResGroup45], (instregex "PUSHF64")>; - -def SBWriteResGroup46 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { - let Latency = 5; - let NumMicroOps = 4; - let ResourceCycles = [1,1,1,1]; -} -def: InstRW<[SBWriteResGroup46], (instregex "CLFLUSH")>; - -def SBWriteResGroup47 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { - let Latency = 5; - let NumMicroOps = 5; - let ResourceCycles = [1,2,1,1]; -} -def: InstRW<[SBWriteResGroup47], (instregex "FXRSTOR")>; - -def SBWriteResGroup48 : SchedWriteRes<[SBPort23]> { - let Latency = 6; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup48], (instregex "LDDQUrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "MMX_MOVD64from64rm")>; -def: InstRW<[SBWriteResGroup48], (instregex "MOV64toPQIrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "MOVAPDrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "MOVAPSrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "MOVDDUPrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "MOVDI2PDIrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "MOVDQArm")>; -def: InstRW<[SBWriteResGroup48], (instregex "MOVDQUrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "MOVNTDQArm")>; -def: InstRW<[SBWriteResGroup48], (instregex "MOVSHDUPrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "MOVSLDUPrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "MOVSSrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "MOVUPDrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "MOVUPSrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "POP64r")>; -def: InstRW<[SBWriteResGroup48], (instregex "VBROADCASTSSrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "VLDDQUYrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "VLDDQUrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "VMOV64toPQIrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "VMOVAPDrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "VMOVAPSrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "VMOVDDUPrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "VMOVDI2PDIrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "VMOVDQArm")>; -def: InstRW<[SBWriteResGroup48], (instregex "VMOVDQUrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "VMOVNTDQArm")>; -def: InstRW<[SBWriteResGroup48], (instregex "VMOVQI2PQIrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "VMOVSDrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "VMOVSHDUPrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "VMOVSLDUPrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "VMOVSSrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "VMOVUPDrm")>; -def: InstRW<[SBWriteResGroup48], (instregex "VMOVUPSrm")>; - -def SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> { - let Latency = 6; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup49], (instregex "JMP64m")>; -def: InstRW<[SBWriteResGroup49], (instregex "MOV64sm")>; - -def SBWriteResGroup50 : SchedWriteRes<[SBPort23,SBPort0]> { - let Latency = 6; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup50], (instregex "BT64mi8")>; - -def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> { - let Latency = 6; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABSBrm64")>; -def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABSDrm64")>; -def: InstRW<[SBWriteResGroup51], (instregex "MMX_PABSWrm64")>; -def: InstRW<[SBWriteResGroup51], (instregex "MMX_PALIGNR64irm")>; -def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSHUFBrm64")>; -def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSIGNBrm64")>; -def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSIGNDrm64")>; -def: InstRW<[SBWriteResGroup51], (instregex "MMX_PSIGNWrm64")>; - -def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> { - let Latency = 6; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup52], (instregex "ADD64rm")>; -def: InstRW<[SBWriteResGroup52], (instregex "ADD8rm")>; -def: InstRW<[SBWriteResGroup52], (instregex "AND64rm")>; -def: InstRW<[SBWriteResGroup52], (instregex "AND8rm")>; -def: InstRW<[SBWriteResGroup52], (instregex "CMP64mi8")>; -def: InstRW<[SBWriteResGroup52], (instregex "CMP64mr")>; -def: InstRW<[SBWriteResGroup52], (instregex "CMP64rm")>; -def: InstRW<[SBWriteResGroup52], (instregex "CMP8mi")>; -def: InstRW<[SBWriteResGroup52], (instregex "CMP8mr")>; -def: InstRW<[SBWriteResGroup52], (instregex "CMP8rm")>; -def: InstRW<[SBWriteResGroup52], (instregex "LODSL")>; -def: InstRW<[SBWriteResGroup52], (instregex "LODSQ")>; -def: InstRW<[SBWriteResGroup52], (instregex "OR64rm")>; -def: InstRW<[SBWriteResGroup52], (instregex "OR8rm")>; -def: InstRW<[SBWriteResGroup52], (instregex "SUB64rm")>; -def: InstRW<[SBWriteResGroup52], (instregex "SUB8rm")>; -def: InstRW<[SBWriteResGroup52], (instregex "XOR64rm")>; -def: InstRW<[SBWriteResGroup52], (instregex "XOR8rm")>; - -def SBWriteResGroup53 : SchedWriteRes<[SBPort4,SBPort23]> { - let Latency = 6; - let NumMicroOps = 3; - let ResourceCycles = [1,2]; -} -def: InstRW<[SBWriteResGroup53], (instregex "POP64rmm")>; -def: InstRW<[SBWriteResGroup53], (instregex "PUSH64rmm")>; -def: InstRW<[SBWriteResGroup53], (instregex "ST_F32m")>; -def: InstRW<[SBWriteResGroup53], (instregex "ST_F64m")>; -def: InstRW<[SBWriteResGroup53], (instregex "ST_FP32m")>; -def: InstRW<[SBWriteResGroup53], (instregex "ST_FP64m")>; -def: InstRW<[SBWriteResGroup53], (instregex "ST_FP80m")>; - -def SBWriteResGroup54 : SchedWriteRes<[SBPort23]> { - let Latency = 7; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup54], (instregex "VBROADCASTSDYrm")>; -def: InstRW<[SBWriteResGroup54], (instregex "VBROADCASTSSrm")>; -def: InstRW<[SBWriteResGroup54], (instregex "VMOVAPDYrm")>; -def: InstRW<[SBWriteResGroup54], (instregex "VMOVAPSYrm")>; -def: InstRW<[SBWriteResGroup54], (instregex "VMOVDDUPYrm")>; -def: InstRW<[SBWriteResGroup54], (instregex "VMOVDQAYrm")>; -def: InstRW<[SBWriteResGroup54], (instregex "VMOVDQUYrm")>; -def: InstRW<[SBWriteResGroup54], (instregex "VMOVSHDUPYrm")>; -def: InstRW<[SBWriteResGroup54], (instregex "VMOVSLDUPYrm")>; -def: InstRW<[SBWriteResGroup54], (instregex "VMOVUPDYrm")>; -def: InstRW<[SBWriteResGroup54], (instregex "VMOVUPSYrm")>; - -def SBWriteResGroup55 : SchedWriteRes<[SBPort0,SBPort23]> { - let Latency = 7; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup55], (instregex "CVTPS2PDrm")>; -def: InstRW<[SBWriteResGroup55], (instregex "CVTSS2SDrm")>; -def: InstRW<[SBWriteResGroup55], (instregex "VCVTPS2PDYrm")>; -def: InstRW<[SBWriteResGroup55], (instregex "VCVTPS2PDrm")>; -def: InstRW<[SBWriteResGroup55], (instregex "VCVTSS2SDrm")>; -def: InstRW<[SBWriteResGroup55], (instregex "VTESTPDrm")>; -def: InstRW<[SBWriteResGroup55], (instregex "VTESTPSrm")>; - -def SBWriteResGroup56 : SchedWriteRes<[SBPort5,SBPort23]> { - let Latency = 7; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup56], (instregex "ANDNPDrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "ANDNPSrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "ANDPDrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "ANDPSrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "INSERTPSrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "MOVHPDrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "MOVHPSrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "MOVLPDrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "MOVLPSrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "ORPDrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "ORPSrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "SHUFPDrmi")>; -def: InstRW<[SBWriteResGroup56], (instregex "SHUFPSrmi")>; -def: InstRW<[SBWriteResGroup56], (instregex "UNPCKHPDrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "UNPCKHPSrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "UNPCKLPDrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "UNPCKLPSrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "VANDNPDrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "VANDNPSrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "VANDPDrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "VANDPSrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "VBROADCASTF128")>; -def: InstRW<[SBWriteResGroup56], (instregex "VINSERTPSrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "VMOVHPDrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "VMOVHPSrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "VMOVLPDrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "VMOVLPSrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "VORPDrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "VORPSrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "VPERMILPDmi")>; -def: InstRW<[SBWriteResGroup56], (instregex "VPERMILPDri")>; -def: InstRW<[SBWriteResGroup56], (instregex "VPERMILPSmi")>; -def: InstRW<[SBWriteResGroup56], (instregex "VPERMILPSri")>; -def: InstRW<[SBWriteResGroup56], (instregex "VSHUFPDrmi")>; -def: InstRW<[SBWriteResGroup56], (instregex "VSHUFPSrmi")>; -def: InstRW<[SBWriteResGroup56], (instregex "VUNPCKHPDrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "VUNPCKHPSrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "VUNPCKLPDrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "VUNPCKLPSrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "VXORPDrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "VXORPSrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "XORPDrm")>; -def: InstRW<[SBWriteResGroup56], (instregex "XORPSrm")>; - -def SBWriteResGroup57 : SchedWriteRes<[SBPort5,SBPort015]> { - let Latency = 7; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup57], (instregex "AESDECLASTrr")>; -def: InstRW<[SBWriteResGroup57], (instregex "AESDECrr")>; -def: InstRW<[SBWriteResGroup57], (instregex "AESENCLASTrr")>; -def: InstRW<[SBWriteResGroup57], (instregex "AESENCrr")>; -def: InstRW<[SBWriteResGroup57], (instregex "KANDQrr")>; -def: InstRW<[SBWriteResGroup57], (instregex "VAESDECLASTrr")>; -def: InstRW<[SBWriteResGroup57], (instregex "VAESDECrr")>; -def: InstRW<[SBWriteResGroup57], (instregex "VAESENCrr")>; - -def SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort0]> { - let Latency = 7; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup58], (instregex "BLENDPDrmi")>; -def: InstRW<[SBWriteResGroup58], (instregex "BLENDPSrmi")>; -def: InstRW<[SBWriteResGroup58], (instregex "VBLENDPDrmi")>; -def: InstRW<[SBWriteResGroup58], (instregex "VBLENDPSrmi")>; -def: InstRW<[SBWriteResGroup58], (instregex "VINSERTF128rm")>; - -def SBWriteResGroup59 : SchedWriteRes<[SBPort23,SBPort15]> { - let Latency = 7; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup59], (instregex "MMX_PADDQirm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PABSBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PABSDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PABSWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PACKSSDWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PACKSSWBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PACKUSDWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PACKUSWBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PADDBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PADDDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PADDQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PADDSBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PADDSWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PADDUSBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PADDUSWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PADDWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PALIGNRrmi")>; -def: InstRW<[SBWriteResGroup59], (instregex "PAVGBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PAVGWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PBLENDWrmi")>; -def: InstRW<[SBWriteResGroup59], (instregex "PCMPEQBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PCMPEQDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PCMPEQQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PCMPEQWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PCMPGTBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PCMPGTDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PCMPGTWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PINSRBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PINSRDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PINSRQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PINSRWrmi")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMAXSBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMAXSDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMAXSWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMAXUBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMAXUDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMAXUWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMINSBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMINSDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMINSWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMINUBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMINUDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMINUWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXBDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXBQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXBWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXDQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXWDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMOVSXWQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXBDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXBQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXBWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXDQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXWDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PMOVZXWQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PSHUFBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PSHUFDmi")>; -def: InstRW<[SBWriteResGroup59], (instregex "PSHUFHWmi")>; -def: InstRW<[SBWriteResGroup59], (instregex "PSHUFLWmi")>; -def: InstRW<[SBWriteResGroup59], (instregex "PSIGNBrm128")>; -def: InstRW<[SBWriteResGroup59], (instregex "PSIGNDrm128")>; -def: InstRW<[SBWriteResGroup59], (instregex "PSIGNWrm128")>; -def: InstRW<[SBWriteResGroup59], (instregex "PSUBBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PSUBDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PSUBQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PSUBSBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PSUBSWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PSUBUSBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PSUBUSWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PSUBWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKHBWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKHDQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKHQDQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKHWDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKLBWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKLDQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKLQDQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "PUNPCKLWDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPABSBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPABSDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPABSWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPACKSSDWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPACKSSWBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPACKUSDWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPACKUSWBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPADDBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPADDDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPADDQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPADDSBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPADDSWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPADDUSBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPADDUSWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPADDWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPALIGNRrmi")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPAVGBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPAVGWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPBLENDWrmi")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPCMPEQBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPCMPEQDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPCMPEQQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPCMPEQWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPCMPGTBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPCMPGTDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPCMPGTWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPINSRBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPINSRDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPINSRQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPINSRWrmi")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMAXSBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMAXSDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMAXSWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMAXUBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMAXUDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMAXUWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMINSBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMINSDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMINSWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMINUBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMINUDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMINUWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXBDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXBQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXBWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXDQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXWDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMOVSXWQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXBDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXBQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXBWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXDQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXWDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPMOVZXWQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPSHUFBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPSHUFDmi")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPSHUFHWmi")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPSHUFLWmi")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPSIGNBrm128")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPSIGNDrm128")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPSIGNWrm128")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPSUBBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPSUBDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPSUBQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPSUBSBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPSUBSWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPSUBUSBrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPSUBUSWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPSUBWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKHBWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKHDQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKHQDQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKHWDrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKLBWrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKLDQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKLQDQrm")>; -def: InstRW<[SBWriteResGroup59], (instregex "VPUNPCKLWDrm")>; - -def SBWriteResGroup60 : SchedWriteRes<[SBPort23,SBPort015]> { - let Latency = 7; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup60], (instregex "PANDNrm")>; -def: InstRW<[SBWriteResGroup60], (instregex "PANDrm")>; -def: InstRW<[SBWriteResGroup60], (instregex "PORrm")>; -def: InstRW<[SBWriteResGroup60], (instregex "PXORrm")>; -def: InstRW<[SBWriteResGroup60], (instregex "VPANDNrm")>; -def: InstRW<[SBWriteResGroup60], (instregex "VPANDrm")>; -def: InstRW<[SBWriteResGroup60], (instregex "VPORrm")>; -def: InstRW<[SBWriteResGroup60], (instregex "VPXORrm")>; - -def SBWriteResGroup61 : SchedWriteRes<[SBPort0,SBPort0]> { - let Latency = 7; - let NumMicroOps = 3; - let ResourceCycles = [2,1]; -} -def: InstRW<[SBWriteResGroup61], (instregex "VRCPPSr")>; -def: InstRW<[SBWriteResGroup61], (instregex "VRSQRTPSYr")>; - -def SBWriteResGroup62 : SchedWriteRes<[SBPort5,SBPort23]> { - let Latency = 7; - let NumMicroOps = 3; - let ResourceCycles = [2,1]; -} -def: InstRW<[SBWriteResGroup62], (instregex "VERRm")>; -def: InstRW<[SBWriteResGroup62], (instregex "VERWm")>; - -def SBWriteResGroup63 : SchedWriteRes<[SBPort23,SBPort015]> { - let Latency = 7; - let NumMicroOps = 3; - let ResourceCycles = [1,2]; -} -def: InstRW<[SBWriteResGroup63], (instregex "LODSB")>; -def: InstRW<[SBWriteResGroup63], (instregex "LODSW")>; - -def SBWriteResGroup64 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> { - let Latency = 7; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup64], (instregex "FARJMP64")>; - -def SBWriteResGroup65 : SchedWriteRes<[SBPort23,SBPort0,SBPort015]> { - let Latency = 7; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup65], (instregex "ADC64rm")>; -def: InstRW<[SBWriteResGroup65], (instregex "ADC8rm")>; -def: InstRW<[SBWriteResGroup65], (instregex "CMOVAE64rm")>; -def: InstRW<[SBWriteResGroup65], (instregex "CMOVB64rm")>; -def: InstRW<[SBWriteResGroup65], (instregex "CMOVE64rm")>; -def: InstRW<[SBWriteResGroup65], (instregex "CMOVG64rm")>; -def: InstRW<[SBWriteResGroup65], (instregex "CMOVGE64rm")>; -def: InstRW<[SBWriteResGroup65], (instregex "CMOVL64rm")>; -def: InstRW<[SBWriteResGroup65], (instregex "CMOVLE64rm")>; -def: InstRW<[SBWriteResGroup65], (instregex "CMOVNE64rm")>; -def: InstRW<[SBWriteResGroup65], (instregex "CMOVNO64rm")>; -def: InstRW<[SBWriteResGroup65], (instregex "CMOVNP64rm")>; -def: InstRW<[SBWriteResGroup65], (instregex "CMOVNS64rm")>; -def: InstRW<[SBWriteResGroup65], (instregex "CMOVO64rm")>; -def: InstRW<[SBWriteResGroup65], (instregex "CMOVP64rm")>; -def: InstRW<[SBWriteResGroup65], (instregex "CMOVS64rm")>; -def: InstRW<[SBWriteResGroup65], (instregex "SBB64rm")>; -def: InstRW<[SBWriteResGroup65], (instregex "SBB8rm")>; - -def SBWriteResGroup66 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> { - let Latency = 7; - let NumMicroOps = 4; - let ResourceCycles = [1,1,2]; -} -def: InstRW<[SBWriteResGroup66], (instregex "FNSTSWm")>; - -def SBWriteResGroup67 : SchedWriteRes<[SBPort1,SBPort5,SBPort015]> { - let Latency = 7; - let NumMicroOps = 4; - let ResourceCycles = [1,2,1]; -} -def: InstRW<[SBWriteResGroup67], (instregex "SLDT32r")>; -def: InstRW<[SBWriteResGroup67], (instregex "STR32r")>; - -def SBWriteResGroup68 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { - let Latency = 7; - let NumMicroOps = 4; - let ResourceCycles = [1,1,2]; -} -def: InstRW<[SBWriteResGroup68], (instregex "CALL64m")>; -def: InstRW<[SBWriteResGroup68], (instregex "FNSTCW16m")>; - -def SBWriteResGroup69 : SchedWriteRes<[SBPort4,SBPort23,SBPort0]> { - let Latency = 7; - let NumMicroOps = 4; - let ResourceCycles = [1,2,1]; -} -def: InstRW<[SBWriteResGroup69], (instregex "BTC64mi8")>; -def: InstRW<[SBWriteResGroup69], (instregex "BTR64mi8")>; -def: InstRW<[SBWriteResGroup69], (instregex "BTS64mi8")>; -def: InstRW<[SBWriteResGroup69], (instregex "SAR64mi")>; -def: InstRW<[SBWriteResGroup69], (instregex "SAR8mi")>; -def: InstRW<[SBWriteResGroup69], (instregex "SHL64m1")>; -def: InstRW<[SBWriteResGroup69], (instregex "SHL64mi")>; -def: InstRW<[SBWriteResGroup69], (instregex "SHL8m1")>; -def: InstRW<[SBWriteResGroup69], (instregex "SHL8mi")>; -def: InstRW<[SBWriteResGroup69], (instregex "SHR64mi")>; -def: InstRW<[SBWriteResGroup69], (instregex "SHR8mi")>; - -def SBWriteResGroup70 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { - let Latency = 7; - let NumMicroOps = 4; - let ResourceCycles = [1,2,1]; -} -def: InstRW<[SBWriteResGroup70], (instregex "ADD64mi8")>; -def: InstRW<[SBWriteResGroup70], (instregex "ADD64mr")>; -def: InstRW<[SBWriteResGroup70], (instregex "ADD8mi")>; -def: InstRW<[SBWriteResGroup70], (instregex "ADD8mr")>; -def: InstRW<[SBWriteResGroup70], (instregex "AND64mi8")>; -def: InstRW<[SBWriteResGroup70], (instregex "AND64mr")>; -def: InstRW<[SBWriteResGroup70], (instregex "AND8mi")>; -def: InstRW<[SBWriteResGroup70], (instregex "AND8mr")>; -def: InstRW<[SBWriteResGroup70], (instregex "DEC64m")>; -def: InstRW<[SBWriteResGroup70], (instregex "DEC8m")>; -def: InstRW<[SBWriteResGroup70], (instregex "INC64m")>; -def: InstRW<[SBWriteResGroup70], (instregex "INC8m")>; -def: InstRW<[SBWriteResGroup70], (instregex "NEG64m")>; -def: InstRW<[SBWriteResGroup70], (instregex "NEG8m")>; -def: InstRW<[SBWriteResGroup70], (instregex "NOT64m")>; -def: InstRW<[SBWriteResGroup70], (instregex "NOT8m")>; -def: InstRW<[SBWriteResGroup70], (instregex "OR64mi8")>; -def: InstRW<[SBWriteResGroup70], (instregex "OR64mr")>; -def: InstRW<[SBWriteResGroup70], (instregex "OR8mi")>; -def: InstRW<[SBWriteResGroup70], (instregex "OR8mr")>; -def: InstRW<[SBWriteResGroup70], (instregex "SUB64mi8")>; -def: InstRW<[SBWriteResGroup70], (instregex "SUB64mr")>; -def: InstRW<[SBWriteResGroup70], (instregex "SUB8mi")>; -def: InstRW<[SBWriteResGroup70], (instregex "SUB8mr")>; -def: InstRW<[SBWriteResGroup70], (instregex "TEST64rm")>; -def: InstRW<[SBWriteResGroup70], (instregex "TEST8mi")>; -def: InstRW<[SBWriteResGroup70], (instregex "TEST8rm")>; -def: InstRW<[SBWriteResGroup70], (instregex "XOR64mi8")>; -def: InstRW<[SBWriteResGroup70], (instregex "XOR64mr")>; -def: InstRW<[SBWriteResGroup70], (instregex "XOR8mi")>; -def: InstRW<[SBWriteResGroup70], (instregex "XOR8mr")>; - -def SBWriteResGroup71 : SchedWriteRes<[SBPort0,SBPort23]> { - let Latency = 8; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup71], (instregex "MMX_PMADDUBSWrm64")>; -def: InstRW<[SBWriteResGroup71], (instregex "MMX_PMULHRSWrm64")>; -def: InstRW<[SBWriteResGroup71], (instregex "VTESTPDYrm")>; -def: InstRW<[SBWriteResGroup71], (instregex "VTESTPSYrm")>; - -def SBWriteResGroup72 : SchedWriteRes<[SBPort1,SBPort23]> { - let Latency = 8; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup72], (instregex "BSF64rm")>; -def: InstRW<[SBWriteResGroup72], (instregex "BSR64rm")>; -def: InstRW<[SBWriteResGroup72], (instregex "CRC32r32m16")>; -def: InstRW<[SBWriteResGroup72], (instregex "CRC32r32m8")>; -def: InstRW<[SBWriteResGroup72], (instregex "FCOM32m")>; -def: InstRW<[SBWriteResGroup72], (instregex "FCOM64m")>; -def: InstRW<[SBWriteResGroup72], (instregex "FCOMP32m")>; -def: InstRW<[SBWriteResGroup72], (instregex "FCOMP64m")>; -def: InstRW<[SBWriteResGroup72], (instregex "MUL8m")>; - -def SBWriteResGroup73 : SchedWriteRes<[SBPort5,SBPort23]> { - let Latency = 8; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup73], (instregex "VANDNPDYrm")>; -def: InstRW<[SBWriteResGroup73], (instregex "VANDNPSYrm")>; -def: InstRW<[SBWriteResGroup73], (instregex "VANDPDrm")>; -def: InstRW<[SBWriteResGroup73], (instregex "VANDPSrm")>; -def: InstRW<[SBWriteResGroup73], (instregex "VORPDYrm")>; -def: InstRW<[SBWriteResGroup73], (instregex "VORPSYrm")>; -def: InstRW<[SBWriteResGroup73], (instregex "VPERM2F128rm")>; -def: InstRW<[SBWriteResGroup73], (instregex "VPERMILPDYri")>; -def: InstRW<[SBWriteResGroup73], (instregex "VPERMILPDmi")>; -def: InstRW<[SBWriteResGroup73], (instregex "VPERMILPSYri")>; -def: InstRW<[SBWriteResGroup73], (instregex "VPERMILPSmi")>; -def: InstRW<[SBWriteResGroup73], (instregex "VSHUFPDYrmi")>; -def: InstRW<[SBWriteResGroup73], (instregex "VSHUFPSYrmi")>; -def: InstRW<[SBWriteResGroup73], (instregex "VUNPCKHPDrm")>; -def: InstRW<[SBWriteResGroup73], (instregex "VUNPCKHPSrm")>; -def: InstRW<[SBWriteResGroup73], (instregex "VUNPCKLPDYrm")>; -def: InstRW<[SBWriteResGroup73], (instregex "VUNPCKLPSYrm")>; -def: InstRW<[SBWriteResGroup73], (instregex "VXORPDrm")>; -def: InstRW<[SBWriteResGroup73], (instregex "VXORPSrm")>; - -def SBWriteResGroup74 : SchedWriteRes<[SBPort23,SBPort0]> { - let Latency = 8; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup74], (instregex "VBLENDPDYrmi")>; -def: InstRW<[SBWriteResGroup74], (instregex "VBLENDPSYrmi")>; - -def SBWriteResGroup75 : SchedWriteRes<[SBPort23,SBPort0]> { - let Latency = 8; - let NumMicroOps = 3; - let ResourceCycles = [1,2]; -} -def: InstRW<[SBWriteResGroup75], (instregex "BLENDVPDrm0")>; -def: InstRW<[SBWriteResGroup75], (instregex "BLENDVPSrm0")>; -def: InstRW<[SBWriteResGroup75], (instregex "VBLENDVPDrm")>; -def: InstRW<[SBWriteResGroup75], (instregex "VBLENDVPSrm")>; -def: InstRW<[SBWriteResGroup75], (instregex "VMASKMOVPDrm")>; -def: InstRW<[SBWriteResGroup75], (instregex "VMASKMOVPSrm")>; - -def SBWriteResGroup76 : SchedWriteRes<[SBPort23,SBPort15]> { - let Latency = 8; - let NumMicroOps = 3; - let ResourceCycles = [1,2]; -} -def: InstRW<[SBWriteResGroup76], (instregex "PBLENDVBrr0")>; -def: InstRW<[SBWriteResGroup76], (instregex "VPBLENDVBrm")>; - -def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { - let Latency = 8; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup77], (instregex "COMISDrm")>; -def: InstRW<[SBWriteResGroup77], (instregex "COMISSrm")>; -def: InstRW<[SBWriteResGroup77], (instregex "UCOMISDrm")>; -def: InstRW<[SBWriteResGroup77], (instregex "UCOMISSrm")>; -def: InstRW<[SBWriteResGroup77], (instregex "VCOMISDrm")>; -def: InstRW<[SBWriteResGroup77], (instregex "VCOMISSrm")>; -def: InstRW<[SBWriteResGroup77], (instregex "VUCOMISDrm")>; -def: InstRW<[SBWriteResGroup77], (instregex "VUCOMISSrm")>; - -def SBWriteResGroup78 : SchedWriteRes<[SBPort0,SBPort5,SBPort23]> { - let Latency = 8; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup78], (instregex "PTESTrm")>; -def: InstRW<[SBWriteResGroup78], (instregex "VPTESTrm")>; - -def SBWriteResGroup79 : SchedWriteRes<[SBPort0,SBPort23,SBPort15]> { - let Latency = 8; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup79], (instregex "PSLLDrm")>; -def: InstRW<[SBWriteResGroup79], (instregex "PSLLQrm")>; -def: InstRW<[SBWriteResGroup79], (instregex "PSLLWrm")>; -def: InstRW<[SBWriteResGroup79], (instregex "PSRADrm")>; -def: InstRW<[SBWriteResGroup79], (instregex "PSRAWrm")>; -def: InstRW<[SBWriteResGroup79], (instregex "PSRLDrm")>; -def: InstRW<[SBWriteResGroup79], (instregex "PSRLQrm")>; -def: InstRW<[SBWriteResGroup79], (instregex "PSRLWrm")>; -def: InstRW<[SBWriteResGroup79], (instregex "VPSLLDri")>; -def: InstRW<[SBWriteResGroup79], (instregex "VPSLLQri")>; -def: InstRW<[SBWriteResGroup79], (instregex "VPSLLWri")>; -def: InstRW<[SBWriteResGroup79], (instregex "VPSRADrm")>; -def: InstRW<[SBWriteResGroup79], (instregex "VPSRAWrm")>; -def: InstRW<[SBWriteResGroup79], (instregex "VPSRLDrm")>; -def: InstRW<[SBWriteResGroup79], (instregex "VPSRLQrm")>; -def: InstRW<[SBWriteResGroup79], (instregex "VPSRLWrm")>; - -def SBWriteResGroup80 : SchedWriteRes<[SBPort23,SBPort15]> { - let Latency = 8; - let NumMicroOps = 4; - let ResourceCycles = [1,3]; -} -def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDSWrm64")>; -def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDWrm64")>; -def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDrm64")>; -def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBDrm64")>; -def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBSWrm64")>; -def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBWrm64")>; - -def SBWriteResGroup81 : SchedWriteRes<[SBPort23,SBPort015]> { - let Latency = 8; - let NumMicroOps = 4; - let ResourceCycles = [1,3]; -} -def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG64rm")>; -def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG8rm")>; - -def SBWriteResGroup82 : SchedWriteRes<[SBPort23,SBPort0,SBPort015]> { - let Latency = 8; - let NumMicroOps = 4; - let ResourceCycles = [1,2,1]; -} -def: InstRW<[SBWriteResGroup82], (instregex "CMOVA64rm")>; -def: InstRW<[SBWriteResGroup82], (instregex "CMOVBE64rm")>; - -def SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> { - let Latency = 8; - let NumMicroOps = 5; - let ResourceCycles = [2,3]; -} -def: InstRW<[SBWriteResGroup83], (instregex "CMPSB")>; -def: InstRW<[SBWriteResGroup83], (instregex "CMPSL")>; -def: InstRW<[SBWriteResGroup83], (instregex "CMPSQ")>; -def: InstRW<[SBWriteResGroup83], (instregex "CMPSW")>; - -def SBWriteResGroup84 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { - let Latency = 8; - let NumMicroOps = 5; - let ResourceCycles = [1,2,2]; -} -def: InstRW<[SBWriteResGroup84], (instregex "FLDCW16m")>; - -def SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort0]> { - let Latency = 8; - let NumMicroOps = 5; - let ResourceCycles = [1,2,2]; -} -def: InstRW<[SBWriteResGroup85], (instregex "ROL64mi")>; -def: InstRW<[SBWriteResGroup85], (instregex "ROL8mi")>; -def: InstRW<[SBWriteResGroup85], (instregex "ROR64mi")>; -def: InstRW<[SBWriteResGroup85], (instregex "ROR8mi")>; - -def SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { - let Latency = 8; - let NumMicroOps = 5; - let ResourceCycles = [1,2,2]; -} -def: InstRW<[SBWriteResGroup86], (instregex "MOVSB")>; -def: InstRW<[SBWriteResGroup86], (instregex "MOVSL")>; -def: InstRW<[SBWriteResGroup86], (instregex "MOVSQ")>; -def: InstRW<[SBWriteResGroup86], (instregex "MOVSW")>; -def: InstRW<[SBWriteResGroup86], (instregex "XADD64rm")>; -def: InstRW<[SBWriteResGroup86], (instregex "XADD8rm")>; - -def SBWriteResGroup87 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { - let Latency = 8; - let NumMicroOps = 5; - let ResourceCycles = [1,1,1,2]; -} -def: InstRW<[SBWriteResGroup87], (instregex "FARCALL64")>; - -def SBWriteResGroup88 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> { - let Latency = 8; - let NumMicroOps = 5; - let ResourceCycles = [1,2,1,1]; -} -def: InstRW<[SBWriteResGroup88], (instregex "SHLD64mri8")>; -def: InstRW<[SBWriteResGroup88], (instregex "SHRD64mri8")>; - -def SBWriteResGroup89 : SchedWriteRes<[SBPort0,SBPort23]> { - let Latency = 9; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup89], (instregex "MMX_PMULUDQirm")>; -def: InstRW<[SBWriteResGroup89], (instregex "PMADDUBSWrm")>; -def: InstRW<[SBWriteResGroup89], (instregex "PMADDWDrm")>; -def: InstRW<[SBWriteResGroup89], (instregex "PMULDQrm")>; -def: InstRW<[SBWriteResGroup89], (instregex "PMULHRSWrm")>; -def: InstRW<[SBWriteResGroup89], (instregex "PMULHUWrm")>; -def: InstRW<[SBWriteResGroup89], (instregex "PMULHWrm")>; -def: InstRW<[SBWriteResGroup89], (instregex "PMULLDrm")>; -def: InstRW<[SBWriteResGroup89], (instregex "PMULLWrm")>; -def: InstRW<[SBWriteResGroup89], (instregex "PMULUDQrm")>; -def: InstRW<[SBWriteResGroup89], (instregex "PSADBWrm")>; -def: InstRW<[SBWriteResGroup89], (instregex "VPMADDUBSWrm")>; -def: InstRW<[SBWriteResGroup89], (instregex "VPMADDWDrm")>; -def: InstRW<[SBWriteResGroup89], (instregex "VPMULDQrm")>; -def: InstRW<[SBWriteResGroup89], (instregex "VPMULHRSWrm")>; -def: InstRW<[SBWriteResGroup89], (instregex "VPMULHUWrm")>; -def: InstRW<[SBWriteResGroup89], (instregex "VPMULHWrm")>; -def: InstRW<[SBWriteResGroup89], (instregex "VPMULLDrm")>; -def: InstRW<[SBWriteResGroup89], (instregex "VPMULLWrm")>; -def: InstRW<[SBWriteResGroup89], (instregex "VPMULUDQrm")>; -def: InstRW<[SBWriteResGroup89], (instregex "VPSADBWrm")>; - -def SBWriteResGroup90 : SchedWriteRes<[SBPort1,SBPort23]> { - let Latency = 9; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup90], (instregex "ADDPDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "ADDPSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "ADDSDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "ADDSSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "ADDSUBPDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "ADDSUBPSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "CMPPDrmi")>; -def: InstRW<[SBWriteResGroup90], (instregex "CMPPSrmi")>; -def: InstRW<[SBWriteResGroup90], (instregex "CMPSSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "CVTDQ2PSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "CVTPS2DQrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "CVTSI2SD64rm")>; -def: InstRW<[SBWriteResGroup90], (instregex "CVTSI2SDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "CVTTPS2DQrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "MAXPDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "MAXPSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "MAXSDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "MAXSSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "MINPDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "MINPSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "MINSDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "MINSSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "MMX_CVTPI2PSirm")>; -def: InstRW<[SBWriteResGroup90], (instregex "MMX_CVTPS2PIirm")>; -def: InstRW<[SBWriteResGroup90], (instregex "MMX_CVTTPS2PIirm")>; -def: InstRW<[SBWriteResGroup90], (instregex "POPCNT64rm")>; -def: InstRW<[SBWriteResGroup90], (instregex "ROUNDPDm")>; -def: InstRW<[SBWriteResGroup90], (instregex "ROUNDPSm")>; -def: InstRW<[SBWriteResGroup90], (instregex "ROUNDSDm")>; -def: InstRW<[SBWriteResGroup90], (instregex "ROUNDSSm")>; -def: InstRW<[SBWriteResGroup90], (instregex "SUBPDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "SUBPSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "SUBSDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "SUBSSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VADDPDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VADDPSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VADDSDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VADDSSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VADDSUBPDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VADDSUBPSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VCMPPDrmi")>; -def: InstRW<[SBWriteResGroup90], (instregex "VCMPPSrmi")>; -def: InstRW<[SBWriteResGroup90], (instregex "VCMPSDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VCMPSSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VCVTDQ2PSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VCVTPS2DQrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VCVTSI2SD64rm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VCVTSI2SDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VCVTTPS2DQrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VMAXPDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VMAXPSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VMAXSDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VMAXSSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VMINPDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VMINPSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VMINSDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VMINSSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VROUNDPDm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VROUNDPSm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VROUNDSDm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VROUNDSSm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VSUBPDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VSUBPSrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VSUBSDrm")>; -def: InstRW<[SBWriteResGroup90], (instregex "VSUBSSrm")>; - -def SBWriteResGroup91 : SchedWriteRes<[SBPort23,SBPort0]> { - let Latency = 9; - let NumMicroOps = 3; - let ResourceCycles = [1,2]; -} -def: InstRW<[SBWriteResGroup91], (instregex "VBLENDVPDYrm")>; -def: InstRW<[SBWriteResGroup91], (instregex "VBLENDVPSYrm")>; -def: InstRW<[SBWriteResGroup91], (instregex "VMASKMOVPDrm")>; -def: InstRW<[SBWriteResGroup91], (instregex "VMASKMOVPSrm")>; - -def SBWriteResGroup92 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> { - let Latency = 9; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup92], (instregex "DPPDrri")>; -def: InstRW<[SBWriteResGroup92], (instregex "VDPPDrri")>; - -def SBWriteResGroup93 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { - let Latency = 9; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup93], (instregex "CVTSD2SI64rm")>; -def: InstRW<[SBWriteResGroup93], (instregex "CVTSD2SIrm")>; -def: InstRW<[SBWriteResGroup93], (instregex "CVTSS2SI64rm")>; -def: InstRW<[SBWriteResGroup93], (instregex "CVTSS2SIrm")>; -def: InstRW<[SBWriteResGroup93], (instregex "CVTTSD2SI64rm")>; -def: InstRW<[SBWriteResGroup93], (instregex "CVTTSD2SIrm")>; -def: InstRW<[SBWriteResGroup93], (instregex "CVTTSS2SI64rm")>; -def: InstRW<[SBWriteResGroup93], (instregex "CVTTSS2SIrm")>; -def: InstRW<[SBWriteResGroup93], (instregex "MUL64m")>; - -def SBWriteResGroup94 : SchedWriteRes<[SBPort0,SBPort5,SBPort23]> { - let Latency = 9; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup94], (instregex "VPTESTYrm")>; - -def SBWriteResGroup95 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> { - let Latency = 9; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup95], (instregex "LD_F32m")>; -def: InstRW<[SBWriteResGroup95], (instregex "LD_F64m")>; -def: InstRW<[SBWriteResGroup95], (instregex "LD_F80m")>; - -def SBWriteResGroup96 : SchedWriteRes<[SBPort23,SBPort15]> { - let Latency = 9; - let NumMicroOps = 4; - let ResourceCycles = [1,3]; -} -def: InstRW<[SBWriteResGroup96], (instregex "PHADDDrm")>; -def: InstRW<[SBWriteResGroup96], (instregex "PHADDSWrm128")>; -def: InstRW<[SBWriteResGroup96], (instregex "PHADDWrm")>; -def: InstRW<[SBWriteResGroup96], (instregex "PHSUBDrm")>; -def: InstRW<[SBWriteResGroup96], (instregex "PHSUBSWrm128")>; -def: InstRW<[SBWriteResGroup96], (instregex "PHSUBWrm")>; -def: InstRW<[SBWriteResGroup96], (instregex "VPHADDDrm")>; -def: InstRW<[SBWriteResGroup96], (instregex "VPHADDSWrm128")>; -def: InstRW<[SBWriteResGroup96], (instregex "VPHADDWrm")>; -def: InstRW<[SBWriteResGroup96], (instregex "VPHSUBDrm")>; -def: InstRW<[SBWriteResGroup96], (instregex "VPHSUBSWrm128")>; -def: InstRW<[SBWriteResGroup96], (instregex "VPHSUBWrm")>; - -def SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> { - let Latency = 9; - let NumMicroOps = 4; - let ResourceCycles = [1,1,2]; -} -def: InstRW<[SBWriteResGroup97], (instregex "IST_F16m")>; -def: InstRW<[SBWriteResGroup97], (instregex "IST_F32m")>; -def: InstRW<[SBWriteResGroup97], (instregex "IST_FP16m")>; -def: InstRW<[SBWriteResGroup97], (instregex "IST_FP32m")>; -def: InstRW<[SBWriteResGroup97], (instregex "IST_FP64m")>; -def: InstRW<[SBWriteResGroup97], (instregex "SHL64mCL")>; -def: InstRW<[SBWriteResGroup97], (instregex "SHL8mCL")>; - -def SBWriteResGroup98 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { - let Latency = 9; - let NumMicroOps = 6; - let ResourceCycles = [1,2,3]; -} -def: InstRW<[SBWriteResGroup98], (instregex "ADC64mi8")>; -def: InstRW<[SBWriteResGroup98], (instregex "ADC8mi")>; -def: InstRW<[SBWriteResGroup98], (instregex "SBB64mi8")>; -def: InstRW<[SBWriteResGroup98], (instregex "SBB8mi")>; - -def SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> { - let Latency = 9; - let NumMicroOps = 6; - let ResourceCycles = [1,2,2,1]; -} -def: InstRW<[SBWriteResGroup99], (instregex "ADC64mr")>; -def: InstRW<[SBWriteResGroup99], (instregex "ADC8mr")>; -def: InstRW<[SBWriteResGroup99], (instregex "SBB64mr")>; -def: InstRW<[SBWriteResGroup99], (instregex "SBB8mr")>; - -def SBWriteResGroup100 : SchedWriteRes<[SBPort4,SBPort5,SBPort23,SBPort0,SBPort015]> { - let Latency = 9; - let NumMicroOps = 6; - let ResourceCycles = [1,1,2,1,1]; -} -def: InstRW<[SBWriteResGroup100], (instregex "BT64mr")>; -def: InstRW<[SBWriteResGroup100], (instregex "BTC64mr")>; -def: InstRW<[SBWriteResGroup100], (instregex "BTR64mr")>; -def: InstRW<[SBWriteResGroup100], (instregex "BTS64mr")>; - -def SBWriteResGroup101 : SchedWriteRes<[SBPort1,SBPort23]> { - let Latency = 10; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup101], (instregex "ADD_F32m")>; -def: InstRW<[SBWriteResGroup101], (instregex "ADD_F64m")>; -def: InstRW<[SBWriteResGroup101], (instregex "ILD_F16m")>; -def: InstRW<[SBWriteResGroup101], (instregex "ILD_F32m")>; -def: InstRW<[SBWriteResGroup101], (instregex "ILD_F64m")>; -def: InstRW<[SBWriteResGroup101], (instregex "SUBR_F32m")>; -def: InstRW<[SBWriteResGroup101], (instregex "SUBR_F64m")>; -def: InstRW<[SBWriteResGroup101], (instregex "SUB_F32m")>; -def: InstRW<[SBWriteResGroup101], (instregex "SUB_F64m")>; -def: InstRW<[SBWriteResGroup101], (instregex "VADDPDYrm")>; -def: InstRW<[SBWriteResGroup101], (instregex "VADDPSYrm")>; -def: InstRW<[SBWriteResGroup101], (instregex "VADDSUBPDYrm")>; -def: InstRW<[SBWriteResGroup101], (instregex "VADDSUBPSYrm")>; -def: InstRW<[SBWriteResGroup101], (instregex "VCMPPDYrmi")>; -def: InstRW<[SBWriteResGroup101], (instregex "VCMPPSYrmi")>; -def: InstRW<[SBWriteResGroup101], (instregex "VCVTDQ2PSYrm")>; -def: InstRW<[SBWriteResGroup101], (instregex "VCVTPS2DQYrm")>; -def: InstRW<[SBWriteResGroup101], (instregex "VCVTTPS2DQrm")>; -def: InstRW<[SBWriteResGroup101], (instregex "VMAXPDYrm")>; -def: InstRW<[SBWriteResGroup101], (instregex "VMAXPSYrm")>; -def: InstRW<[SBWriteResGroup101], (instregex "VMINPDrm")>; -def: InstRW<[SBWriteResGroup101], (instregex "VMINPSrm")>; -def: InstRW<[SBWriteResGroup101], (instregex "VROUNDPDm")>; -def: InstRW<[SBWriteResGroup101], (instregex "VROUNDPSm")>; -def: InstRW<[SBWriteResGroup101], (instregex "VSUBPDYrm")>; -def: InstRW<[SBWriteResGroup101], (instregex "VSUBPSYrm")>; - -def SBWriteResGroup102 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { - let Latency = 10; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup102], (instregex "VCVTSD2SI64rm")>; -def: InstRW<[SBWriteResGroup102], (instregex "VCVTSD2SI64rr")>; -def: InstRW<[SBWriteResGroup102], (instregex "VCVTSS2SI64rm")>; -def: InstRW<[SBWriteResGroup102], (instregex "VCVTSS2SIrm")>; -def: InstRW<[SBWriteResGroup102], (instregex "VCVTTSD2SI64rm")>; -def: InstRW<[SBWriteResGroup102], (instregex "VCVTTSD2SI64rr")>; -def: InstRW<[SBWriteResGroup102], (instregex "VCVTTSS2SI64rm")>; -def: InstRW<[SBWriteResGroup102], (instregex "VCVTTSS2SIrm")>; - -def SBWriteResGroup103 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> { - let Latency = 10; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup103], (instregex "CVTDQ2PDrm")>; -def: InstRW<[SBWriteResGroup103], (instregex "CVTPD2DQrm")>; -def: InstRW<[SBWriteResGroup103], (instregex "CVTPD2PSrm")>; -def: InstRW<[SBWriteResGroup103], (instregex "CVTSD2SSrm")>; -def: InstRW<[SBWriteResGroup103], (instregex "CVTSI2SS64rm")>; -def: InstRW<[SBWriteResGroup103], (instregex "CVTSI2SSrm")>; -def: InstRW<[SBWriteResGroup103], (instregex "CVTTPD2DQrm")>; -def: InstRW<[SBWriteResGroup103], (instregex "MMX_CVTPD2PIirm")>; -def: InstRW<[SBWriteResGroup103], (instregex "MMX_CVTPI2PDirm")>; -def: InstRW<[SBWriteResGroup103], (instregex "MMX_CVTTPD2PIirm")>; -def: InstRW<[SBWriteResGroup103], (instregex "VCVTDQ2PDYrm")>; -def: InstRW<[SBWriteResGroup103], (instregex "VCVTDQ2PDrm")>; -def: InstRW<[SBWriteResGroup103], (instregex "VCVTPD2DQrm")>; -def: InstRW<[SBWriteResGroup103], (instregex "VCVTPD2PSrm")>; -def: InstRW<[SBWriteResGroup103], (instregex "VCVTSD2SSrm")>; -def: InstRW<[SBWriteResGroup103], (instregex "VCVTSI2SS64rm")>; -def: InstRW<[SBWriteResGroup103], (instregex "VCVTSI2SSrm")>; -def: InstRW<[SBWriteResGroup103], (instregex "VCVTTPD2DQrm")>; - -def SBWriteResGroup104 : SchedWriteRes<[SBPort0,SBPort23]> { - let Latency = 11; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup104], (instregex "MULPDrm")>; -def: InstRW<[SBWriteResGroup104], (instregex "MULPSrm")>; -def: InstRW<[SBWriteResGroup104], (instregex "MULSDrm")>; -def: InstRW<[SBWriteResGroup104], (instregex "MULSSrm")>; -def: InstRW<[SBWriteResGroup104], (instregex "PCMPGTQrm")>; -def: InstRW<[SBWriteResGroup104], (instregex "PHMINPOSUWrm128")>; -def: InstRW<[SBWriteResGroup104], (instregex "RCPPSm")>; -def: InstRW<[SBWriteResGroup104], (instregex "RCPSSm")>; -def: InstRW<[SBWriteResGroup104], (instregex "RSQRTPSm")>; -def: InstRW<[SBWriteResGroup104], (instregex "RSQRTSSm")>; -def: InstRW<[SBWriteResGroup104], (instregex "VMULPDrm")>; -def: InstRW<[SBWriteResGroup104], (instregex "VMULPSrm")>; -def: InstRW<[SBWriteResGroup104], (instregex "VMULSDrm")>; -def: InstRW<[SBWriteResGroup104], (instregex "VMULSSrm")>; -def: InstRW<[SBWriteResGroup104], (instregex "VPCMPGTQrm")>; -def: InstRW<[SBWriteResGroup104], (instregex "VPHMINPOSUWrm128")>; -def: InstRW<[SBWriteResGroup104], (instregex "VRCPPSm")>; -def: InstRW<[SBWriteResGroup104], (instregex "VRCPSSm")>; -def: InstRW<[SBWriteResGroup104], (instregex "VRSQRTPSm")>; -def: InstRW<[SBWriteResGroup104], (instregex "VRSQRTSSm")>; - -def SBWriteResGroup105 : SchedWriteRes<[SBPort0]> { - let Latency = 11; - let NumMicroOps = 3; - let ResourceCycles = [3]; -} -def: InstRW<[SBWriteResGroup105], (instregex "PCMPISTRIrr")>; -def: InstRW<[SBWriteResGroup105], (instregex "PCMPISTRM128rr")>; -def: InstRW<[SBWriteResGroup105], (instregex "VPCMPISTRIrr")>; -def: InstRW<[SBWriteResGroup105], (instregex "VPCMPISTRM128rr")>; - -def SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> { - let Latency = 11; - let NumMicroOps = 3; - let ResourceCycles = [2,1]; -} -def: InstRW<[SBWriteResGroup106], (instregex "FICOM16m")>; -def: InstRW<[SBWriteResGroup106], (instregex "FICOM32m")>; -def: InstRW<[SBWriteResGroup106], (instregex "FICOMP16m")>; -def: InstRW<[SBWriteResGroup106], (instregex "FICOMP32m")>; - -def SBWriteResGroup107 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> { - let Latency = 11; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup107], (instregex "VCVTPD2DQYrm")>; -def: InstRW<[SBWriteResGroup107], (instregex "VCVTPD2PSYrm")>; -def: InstRW<[SBWriteResGroup107], (instregex "VCVTTPD2DQYrm")>; - -def SBWriteResGroup108 : SchedWriteRes<[SBPort0,SBPort23,SBPort15]> { - let Latency = 11; - let NumMicroOps = 4; - let ResourceCycles = [1,1,2]; -} -def: InstRW<[SBWriteResGroup108], (instregex "MPSADBWrmi")>; -def: InstRW<[SBWriteResGroup108], (instregex "VMPSADBWrmi")>; - -def SBWriteResGroup109 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> { - let Latency = 11; - let NumMicroOps = 4; - let ResourceCycles = [1,2,1]; -} -def: InstRW<[SBWriteResGroup109], (instregex "HADDPDrm")>; -def: InstRW<[SBWriteResGroup109], (instregex "HADDPSrm")>; -def: InstRW<[SBWriteResGroup109], (instregex "HSUBPDrm")>; -def: InstRW<[SBWriteResGroup109], (instregex "HSUBPSrm")>; -def: InstRW<[SBWriteResGroup109], (instregex "VHADDPDrm")>; -def: InstRW<[SBWriteResGroup109], (instregex "VHADDPSrm")>; -def: InstRW<[SBWriteResGroup109], (instregex "VHSUBPDrm")>; -def: InstRW<[SBWriteResGroup109], (instregex "VHSUBPSrm")>; - -def SBWriteResGroup110 : SchedWriteRes<[SBPort5]> { - let Latency = 12; - let NumMicroOps = 2; - let ResourceCycles = [2]; -} -def: InstRW<[SBWriteResGroup110], (instregex "AESIMCrr")>; -def: InstRW<[SBWriteResGroup110], (instregex "VAESIMCrr")>; - -def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> { - let Latency = 12; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup111], (instregex "MUL_F32m")>; -def: InstRW<[SBWriteResGroup111], (instregex "MUL_F64m")>; -def: InstRW<[SBWriteResGroup111], (instregex "VMULPDYrm")>; -def: InstRW<[SBWriteResGroup111], (instregex "VMULPSYrm")>; - -def SBWriteResGroup112 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> { - let Latency = 12; - let NumMicroOps = 4; - let ResourceCycles = [1,2,1]; -} -def: InstRW<[SBWriteResGroup112], (instregex "DPPSrri")>; -def: InstRW<[SBWriteResGroup112], (instregex "VDPPSYrri")>; -def: InstRW<[SBWriteResGroup112], (instregex "VDPPSrri")>; - -def SBWriteResGroup113 : SchedWriteRes<[SBPort1,SBPort5,SBPort23]> { - let Latency = 12; - let NumMicroOps = 4; - let ResourceCycles = [1,2,1]; -} -def: InstRW<[SBWriteResGroup113], (instregex "VHADDPDrm")>; -def: InstRW<[SBWriteResGroup113], (instregex "VHADDPSYrm")>; -def: InstRW<[SBWriteResGroup113], (instregex "VHSUBPDYrm")>; -def: InstRW<[SBWriteResGroup113], (instregex "VHSUBPSYrm")>; - -def SBWriteResGroup114 : SchedWriteRes<[SBPort1,SBPort23]> { - let Latency = 13; - let NumMicroOps = 3; - let ResourceCycles = [2,1]; -} -def: InstRW<[SBWriteResGroup114], (instregex "ADD_FI16m")>; -def: InstRW<[SBWriteResGroup114], (instregex "ADD_FI32m")>; -def: InstRW<[SBWriteResGroup114], (instregex "SUBR_FI16m")>; -def: InstRW<[SBWriteResGroup114], (instregex "SUBR_FI32m")>; -def: InstRW<[SBWriteResGroup114], (instregex "SUB_FI16m")>; -def: InstRW<[SBWriteResGroup114], (instregex "SUB_FI32m")>; - -def SBWriteResGroup115 : SchedWriteRes<[SBPort5,SBPort23,SBPort015]> { - let Latency = 13; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup115], (instregex "AESDECLASTrm")>; -def: InstRW<[SBWriteResGroup115], (instregex "AESDECrm")>; -def: InstRW<[SBWriteResGroup115], (instregex "AESENCLASTrm")>; -def: InstRW<[SBWriteResGroup115], (instregex "AESENCrm")>; -def: InstRW<[SBWriteResGroup115], (instregex "VAESDECLASTrm")>; -def: InstRW<[SBWriteResGroup115], (instregex "VAESDECrm")>; -def: InstRW<[SBWriteResGroup115], (instregex "VAESENCLASTrm")>; -def: InstRW<[SBWriteResGroup115], (instregex "VAESENCrm")>; - -def SBWriteResGroup116 : SchedWriteRes<[SBPort0]> { - let Latency = 14; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup116], (instregex "DIVPSrr")>; -def: InstRW<[SBWriteResGroup116], (instregex "DIVSSrr")>; -def: InstRW<[SBWriteResGroup116], (instregex "SQRTPSr")>; -def: InstRW<[SBWriteResGroup116], (instregex "SQRTSSr")>; -def: InstRW<[SBWriteResGroup116], (instregex "VDIVPSrr")>; -def: InstRW<[SBWriteResGroup116], (instregex "VDIVSSrr")>; -def: InstRW<[SBWriteResGroup116], (instregex "VSQRTPSr")>; - -def SBWriteResGroup117 : SchedWriteRes<[SBPort0,SBPort23]> { - let Latency = 14; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup117], (instregex "VSQRTSSm")>; - -def SBWriteResGroup118 : SchedWriteRes<[SBPort0,SBPort23,SBPort0]> { - let Latency = 14; - let NumMicroOps = 4; - let ResourceCycles = [2,1,1]; -} -def: InstRW<[SBWriteResGroup118], (instregex "VRCPPSm")>; -def: InstRW<[SBWriteResGroup118], (instregex "VRSQRTPSYm")>; - -def SBWriteResGroup119 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { - let Latency = 15; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI16m")>; -def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI32m")>; - -def SBWriteResGroup120 : SchedWriteRes<[SBPort0,SBPort1,SBPort5,SBPort23]> { - let Latency = 15; - let NumMicroOps = 4; - let ResourceCycles = [1,1,1,1]; -} -def: InstRW<[SBWriteResGroup120], (instregex "DPPDrmi")>; -def: InstRW<[SBWriteResGroup120], (instregex "VDPPDrmi")>; - -def SBWriteResGroup121 : SchedWriteRes<[SBPort0,SBPort23]> { - let Latency = 17; - let NumMicroOps = 4; - let ResourceCycles = [3,1]; -} -def: InstRW<[SBWriteResGroup121], (instregex "PCMPISTRIrm")>; -def: InstRW<[SBWriteResGroup121], (instregex "PCMPISTRM128rm")>; -def: InstRW<[SBWriteResGroup121], (instregex "VPCMPISTRIrm")>; -def: InstRW<[SBWriteResGroup121], (instregex "VPCMPISTRM128rm")>; - -def SBWriteResGroup122 : SchedWriteRes<[SBPort5,SBPort23]> { - let Latency = 18; - let NumMicroOps = 3; - let ResourceCycles = [2,1]; -} -def: InstRW<[SBWriteResGroup122], (instregex "AESIMCrm")>; -def: InstRW<[SBWriteResGroup122], (instregex "VAESIMCrm")>; - -def SBWriteResGroup123 : SchedWriteRes<[SBPort0,SBPort23]> { - let Latency = 20; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup123], (instregex "DIVPSrm")>; -def: InstRW<[SBWriteResGroup123], (instregex "DIVSSrm")>; -def: InstRW<[SBWriteResGroup123], (instregex "SQRTPSm")>; -def: InstRW<[SBWriteResGroup123], (instregex "SQRTSSm")>; -def: InstRW<[SBWriteResGroup123], (instregex "VDIVPSrm")>; -def: InstRW<[SBWriteResGroup123], (instregex "VDIVSSrm")>; -def: InstRW<[SBWriteResGroup123], (instregex "VSQRTPSm")>; - -def SBWriteResGroup124 : SchedWriteRes<[SBPort0]> { - let Latency = 21; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup124], (instregex "VSQRTSDr")>; - -def SBWriteResGroup125 : SchedWriteRes<[SBPort0,SBPort23]> { - let Latency = 21; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup125], (instregex "VSQRTSDm")>; - -def SBWriteResGroup126 : SchedWriteRes<[SBPort0]> { - let Latency = 22; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup126], (instregex "DIVPDrr")>; -def: InstRW<[SBWriteResGroup126], (instregex "DIVSDrr")>; -def: InstRW<[SBWriteResGroup126], (instregex "SQRTPDr")>; -def: InstRW<[SBWriteResGroup126], (instregex "SQRTSDr")>; -def: InstRW<[SBWriteResGroup126], (instregex "VDIVPDrr")>; -def: InstRW<[SBWriteResGroup126], (instregex "VDIVSDrr")>; -def: InstRW<[SBWriteResGroup126], (instregex "VSQRTPDr")>; - -def SBWriteResGroup127 : SchedWriteRes<[SBPort0]> { - let Latency = 24; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup127], (instregex "DIVR_FPrST0")>; -def: InstRW<[SBWriteResGroup127], (instregex "DIVR_FST0r")>; -def: InstRW<[SBWriteResGroup127], (instregex "DIVR_FrST0")>; -def: InstRW<[SBWriteResGroup127], (instregex "DIV_FPrST0")>; -def: InstRW<[SBWriteResGroup127], (instregex "DIV_FST0r")>; -def: InstRW<[SBWriteResGroup127], (instregex "DIV_FrST0")>; - -def SBWriteResGroup128 : SchedWriteRes<[SBPort0,SBPort23]> { - let Latency = 28; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup128], (instregex "DIVPDrm")>; -def: InstRW<[SBWriteResGroup128], (instregex "DIVSDrm")>; -def: InstRW<[SBWriteResGroup128], (instregex "SQRTPDm")>; -def: InstRW<[SBWriteResGroup128], (instregex "SQRTSDm")>; -def: InstRW<[SBWriteResGroup128], (instregex "VDIVPDrm")>; -def: InstRW<[SBWriteResGroup128], (instregex "VDIVSDrm")>; -def: InstRW<[SBWriteResGroup128], (instregex "VSQRTPDm")>; - -def SBWriteResGroup129 : SchedWriteRes<[SBPort0,SBPort0]> { - let Latency = 29; - let NumMicroOps = 3; - let ResourceCycles = [2,1]; -} -def: InstRW<[SBWriteResGroup129], (instregex "VDIVPSYrr")>; -def: InstRW<[SBWriteResGroup129], (instregex "VSQRTPSYr")>; - -def SBWriteResGroup130 : SchedWriteRes<[SBPort0,SBPort23]> { - let Latency = 31; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SBWriteResGroup130], (instregex "DIVR_F32m")>; -def: InstRW<[SBWriteResGroup130], (instregex "DIVR_F64m")>; -def: InstRW<[SBWriteResGroup130], (instregex "DIV_F32m")>; -def: InstRW<[SBWriteResGroup130], (instregex "DIV_F64m")>; - -def SBWriteResGroup131 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { - let Latency = 34; - let NumMicroOps = 3; - let ResourceCycles = [1,1,1]; -} -def: InstRW<[SBWriteResGroup131], (instregex "DIVR_FI16m")>; -def: InstRW<[SBWriteResGroup131], (instregex "DIVR_FI32m")>; -def: InstRW<[SBWriteResGroup131], (instregex "DIV_FI16m")>; -def: InstRW<[SBWriteResGroup131], (instregex "DIV_FI32m")>; - -def SBWriteResGroup132 : SchedWriteRes<[SBPort0,SBPort23,SBPort0]> { - let Latency = 36; - let NumMicroOps = 4; - let ResourceCycles = [2,1,1]; -} -def: InstRW<[SBWriteResGroup132], (instregex "VDIVPSYrm")>; -def: InstRW<[SBWriteResGroup132], (instregex "VSQRTPSYm")>; - -def SBWriteResGroup133 : SchedWriteRes<[SBPort0,SBPort0]> { - let Latency = 45; - let NumMicroOps = 3; - let ResourceCycles = [2,1]; -} -def: InstRW<[SBWriteResGroup133], (instregex "VDIVPDYrr")>; -def: InstRW<[SBWriteResGroup133], (instregex "VSQRTPDYr")>; - -def SBWriteResGroup134 : SchedWriteRes<[SBPort0,SBPort23,SBPort0]> { - let Latency = 52; - let NumMicroOps = 4; - let ResourceCycles = [2,1,1]; -} -def: InstRW<[SBWriteResGroup134], (instregex "VDIVPDYrm")>; -def: InstRW<[SBWriteResGroup134], (instregex "VSQRTPDYm")>; - -def SBWriteResGroup135 : SchedWriteRes<[SBPort0]> { - let Latency = 114; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup135], (instregex "VSQRTSSr")>; - } // SchedModel diff --git a/contrib/llvm/lib/ToolDrivers/llvm-dlltool/DlltoolDriver.cpp b/contrib/llvm/lib/ToolDrivers/llvm-dlltool/DlltoolDriver.cpp index fc15dc1e6032..4820b9f7de58 100644 --- a/contrib/llvm/lib/ToolDrivers/llvm-dlltool/DlltoolDriver.cpp +++ b/contrib/llvm/lib/ToolDrivers/llvm-dlltool/DlltoolDriver.cpp @@ -161,6 +161,22 @@ int llvm::dlltoolDriverMain(llvm::ArrayRef<const char *> ArgsArr) { if (Path.empty()) Path = getImplibPath(Def->OutputFile); + if (Machine == IMAGE_FILE_MACHINE_I386 && Args.getLastArg(OPT_k)) { + for (COFFShortExport& E : Def->Exports) { + if (E.isWeak() || (!E.Name.empty() && E.Name[0] == '?')) + continue; + E.SymbolName = E.Name; + // Trim off the trailing decoration. Symbols will always have a + // starting prefix here (either _ for cdecl/stdcall, @ for fastcall + // or ? for C++ functions). (Vectorcall functions also will end up having + // a prefix here, even if they shouldn't.) + E.Name = E.Name.substr(0, E.Name.find('@', 1)); + // By making sure E.SymbolName != E.Name for decorated symbols, + // writeImportLibrary writes these symbols with the type + // IMPORT_NAME_UNDECORATE. + } + } + if (writeImportLibrary(Def->OutputFile, Path, Def->Exports, Machine, true)) return 1; return 0; diff --git a/contrib/llvm/lib/ToolDrivers/llvm-dlltool/Options.td b/contrib/llvm/lib/ToolDrivers/llvm-dlltool/Options.td index 213c6a4d7674..e78182ab8130 100644 --- a/contrib/llvm/lib/ToolDrivers/llvm-dlltool/Options.td +++ b/contrib/llvm/lib/ToolDrivers/llvm-dlltool/Options.td @@ -12,13 +12,13 @@ def D_long : JoinedOrSeparate<["--"], "dllname">, Alias<D>; def d: JoinedOrSeparate<["-"], "d">, HelpText<"Input .def File">; def d_long : JoinedOrSeparate<["--"], "input-def">, Alias<d>; +def k: Flag<["-"], "k">, HelpText<"Kill @n Symbol from export">; +def k_alias: Flag<["--"], "kill-at">, Alias<k>; + //============================================================================== // The flags below do nothing. They are defined only for dlltool compatibility. //============================================================================== -def k: Flag<["-"], "k">, HelpText<"Kill @n Symbol from export">; -def k_alias: Flag<["--"], "kill-at">, Alias<k>; - def S: JoinedOrSeparate<["-"], "S">, HelpText<"Assembler">; def S_alias: JoinedOrSeparate<["--"], "as">, Alias<S>; diff --git a/contrib/llvm/lib/Transforms/Scalar/LowerAtomic.cpp b/contrib/llvm/lib/Transforms/Scalar/LowerAtomic.cpp index 08e60b16bedf..6f77c5bd0d07 100644 --- a/contrib/llvm/lib/Transforms/Scalar/LowerAtomic.cpp +++ b/contrib/llvm/lib/Transforms/Scalar/LowerAtomic.cpp @@ -155,8 +155,7 @@ public: } bool runOnFunction(Function &F) override { - if (skipFunction(F)) - return false; + // Don't skip optnone functions; atomics still need to be lowered. FunctionAnalysisManager DummyFAM; auto PA = Impl.run(F, DummyFAM); return !PA.areAllPreserved(); diff --git a/contrib/llvm/lib/Transforms/Scalar/Reassociate.cpp b/contrib/llvm/lib/Transforms/Scalar/Reassociate.cpp index 29d1ba406ae4..e235e5eb1a06 100644 --- a/contrib/llvm/lib/Transforms/Scalar/Reassociate.cpp +++ b/contrib/llvm/lib/Transforms/Scalar/Reassociate.cpp @@ -1941,6 +1941,12 @@ Instruction *ReassociatePass::canonicalizeNegConstExpr(Instruction *I) { if (!User->isCommutative() && User->getOperand(1) != I) return nullptr; + // Don't canonicalize x + (-Constant * y) -> x - (Constant * y), if the + // resulting subtract will be broken up later. This can get us into an + // infinite loop during reassociation. + if (UserOpcode == Instruction::FAdd && ShouldBreakUpSubtract(User)) + return nullptr; + // Change the sign of the constant. APFloat Val = CF->getValueAPF(); Val.changeSign(); diff --git a/contrib/llvm/lib/Transforms/Utils/CloneFunction.cpp b/contrib/llvm/lib/Transforms/Utils/CloneFunction.cpp index 7e75e8847785..9c4e13903ed7 100644 --- a/contrib/llvm/lib/Transforms/Utils/CloneFunction.cpp +++ b/contrib/llvm/lib/Transforms/Utils/CloneFunction.cpp @@ -341,8 +341,9 @@ void PruningFunctionCloner::CloneBlock(const BasicBlock *BB, SimplifyInstruction(NewInst, BB->getModule()->getDataLayout())) { // On the off-chance that this simplifies to an instruction in the old // function, map it back into the new function. - if (Value *MappedV = VMap.lookup(V)) - V = MappedV; + if (NewFunc != OldFunc) + if (Value *MappedV = VMap.lookup(V)) + V = MappedV; if (!NewInst->mayHaveSideEffects()) { VMap[&*II] = V; diff --git a/contrib/llvm/tools/clang/include/clang/AST/DeclCXX.h b/contrib/llvm/tools/clang/include/clang/AST/DeclCXX.h index 9d64f0244ec3..c39eaee9b124 100644 --- a/contrib/llvm/tools/clang/include/clang/AST/DeclCXX.h +++ b/contrib/llvm/tools/clang/include/clang/AST/DeclCXX.h @@ -375,6 +375,7 @@ class CXXRecordDecl : public RecordDecl { /// \brief These flags are \c true if a defaulted corresponding special /// member can't be fully analyzed without performing overload resolution. /// @{ + unsigned NeedOverloadResolutionForCopyConstructor : 1; unsigned NeedOverloadResolutionForMoveConstructor : 1; unsigned NeedOverloadResolutionForMoveAssignment : 1; unsigned NeedOverloadResolutionForDestructor : 1; @@ -383,6 +384,7 @@ class CXXRecordDecl : public RecordDecl { /// \brief These flags are \c true if an implicit defaulted corresponding /// special member would be defined as deleted. /// @{ + unsigned DefaultedCopyConstructorIsDeleted : 1; unsigned DefaultedMoveConstructorIsDeleted : 1; unsigned DefaultedMoveAssignmentIsDeleted : 1; unsigned DefaultedDestructorIsDeleted : 1; @@ -415,6 +417,12 @@ class CXXRecordDecl : public RecordDecl { /// constructor. unsigned HasDefaultedDefaultConstructor : 1; + /// \brief True if this class can be passed in a non-address-preserving + /// fashion (such as in registers) according to the C++ language rules. + /// This does not imply anything about how the ABI in use will actually + /// pass an object of this class. + unsigned CanPassInRegisters : 1; + /// \brief True if a defaulted default constructor for this class would /// be constexpr. unsigned DefaultedDefaultConstructorIsConstexpr : 1; @@ -811,18 +819,50 @@ public: return data().FirstFriend.isValid(); } + /// \brief \c true if a defaulted copy constructor for this class would be + /// deleted. + bool defaultedCopyConstructorIsDeleted() const { + assert((!needsOverloadResolutionForCopyConstructor() || + (data().DeclaredSpecialMembers & SMF_CopyConstructor)) && + "this property has not yet been computed by Sema"); + return data().DefaultedCopyConstructorIsDeleted; + } + + /// \brief \c true if a defaulted move constructor for this class would be + /// deleted. + bool defaultedMoveConstructorIsDeleted() const { + assert((!needsOverloadResolutionForMoveConstructor() || + (data().DeclaredSpecialMembers & SMF_MoveConstructor)) && + "this property has not yet been computed by Sema"); + return data().DefaultedMoveConstructorIsDeleted; + } + + /// \brief \c true if a defaulted destructor for this class would be deleted. + bool defaultedDestructorIsDeleted() const { + return !data().DefaultedDestructorIsDeleted; + } + + /// \brief \c true if we know for sure that this class has a single, + /// accessible, unambiguous copy constructor that is not deleted. + bool hasSimpleCopyConstructor() const { + return !hasUserDeclaredCopyConstructor() && + !data().DefaultedCopyConstructorIsDeleted; + } + /// \brief \c true if we know for sure that this class has a single, /// accessible, unambiguous move constructor that is not deleted. bool hasSimpleMoveConstructor() const { return !hasUserDeclaredMoveConstructor() && hasMoveConstructor() && !data().DefaultedMoveConstructorIsDeleted; } + /// \brief \c true if we know for sure that this class has a single, /// accessible, unambiguous move assignment operator that is not deleted. bool hasSimpleMoveAssignment() const { return !hasUserDeclaredMoveAssignment() && hasMoveAssignment() && !data().DefaultedMoveAssignmentIsDeleted; } + /// \brief \c true if we know for sure that this class has an accessible /// destructor that is not deleted. bool hasSimpleDestructor() const { @@ -878,7 +918,16 @@ public: /// \brief Determine whether we need to eagerly declare a defaulted copy /// constructor for this class. bool needsOverloadResolutionForCopyConstructor() const { - return data().HasMutableFields; + // C++17 [class.copy.ctor]p6: + // If the class definition declares a move constructor or move assignment + // operator, the implicitly declared copy constructor is defined as + // deleted. + // In MSVC mode, sometimes a declared move assignment does not delete an + // implicit copy constructor, so defer this choice to Sema. + if (data().UserDeclaredSpecialMembers & + (SMF_MoveConstructor | SMF_MoveAssignment)) + return true; + return data().NeedOverloadResolutionForCopyConstructor; } /// \brief Determine whether an implicit copy constructor for this type @@ -919,7 +968,16 @@ public: needsImplicitMoveConstructor(); } - /// \brief Set that we attempted to declare an implicitly move + /// \brief Set that we attempted to declare an implicit copy + /// constructor, but overload resolution failed so we deleted it. + void setImplicitCopyConstructorIsDeleted() { + assert((data().DefaultedCopyConstructorIsDeleted || + needsOverloadResolutionForCopyConstructor()) && + "Copy constructor should not be deleted"); + data().DefaultedCopyConstructorIsDeleted = true; + } + + /// \brief Set that we attempted to declare an implicit move /// constructor, but overload resolution failed so we deleted it. void setImplicitMoveConstructorIsDeleted() { assert((data().DefaultedMoveConstructorIsDeleted || @@ -1316,6 +1374,18 @@ public: return data().HasIrrelevantDestructor; } + /// \brief Determine whether this class has at least one trivial, non-deleted + /// copy or move constructor. + bool canPassInRegisters() const { + return data().CanPassInRegisters; + } + + /// \brief Set that we can pass this RecordDecl in registers. + // FIXME: This should be set as part of completeDefinition. + void setCanPassInRegisters(bool CanPass) { + data().CanPassInRegisters = CanPass; + } + /// \brief Determine whether this class has a non-literal or/ volatile type /// non-static data member or base class. bool hasNonLiteralTypeFieldsOrBases() const { diff --git a/contrib/llvm/tools/clang/include/clang/Lex/Preprocessor.h b/contrib/llvm/tools/clang/include/clang/Lex/Preprocessor.h index a058fbfbb4cf..dba4b80f6071 100644 --- a/contrib/llvm/tools/clang/include/clang/Lex/Preprocessor.h +++ b/contrib/llvm/tools/clang/include/clang/Lex/Preprocessor.h @@ -1048,10 +1048,6 @@ public: /// which implicitly adds the builtin defines etc. void EnterMainSourceFile(); - /// \brief After parser warm-up, initialize the conditional stack from - /// the preamble. - void replayPreambleConditionalStack(); - /// \brief Inform the preprocessor callbacks that processing is complete. void EndSourceFile(); @@ -2025,6 +2021,10 @@ public: } private: + /// \brief After processing predefined file, initialize the conditional stack from + /// the preamble. + void replayPreambleConditionalStack(); + // Macro handling. void HandleDefineDirective(Token &Tok, bool ImmediatelyAfterTopLevelIfndef); void HandleUndefDirective(); diff --git a/contrib/llvm/tools/clang/lib/AST/ASTImporter.cpp b/contrib/llvm/tools/clang/lib/AST/ASTImporter.cpp index 6e33b98d2f18..2c0bb11cc4bc 100644 --- a/contrib/llvm/tools/clang/lib/AST/ASTImporter.cpp +++ b/contrib/llvm/tools/clang/lib/AST/ASTImporter.cpp @@ -956,12 +956,16 @@ bool ASTNodeImporter::ImportDefinition(RecordDecl *From, RecordDecl *To, ToData.HasUninitializedFields = FromData.HasUninitializedFields; ToData.HasInheritedConstructor = FromData.HasInheritedConstructor; ToData.HasInheritedAssignment = FromData.HasInheritedAssignment; + ToData.NeedOverloadResolutionForCopyConstructor + = FromData.NeedOverloadResolutionForCopyConstructor; ToData.NeedOverloadResolutionForMoveConstructor = FromData.NeedOverloadResolutionForMoveConstructor; ToData.NeedOverloadResolutionForMoveAssignment = FromData.NeedOverloadResolutionForMoveAssignment; ToData.NeedOverloadResolutionForDestructor = FromData.NeedOverloadResolutionForDestructor; + ToData.DefaultedCopyConstructorIsDeleted + = FromData.DefaultedCopyConstructorIsDeleted; ToData.DefaultedMoveConstructorIsDeleted = FromData.DefaultedMoveConstructorIsDeleted; ToData.DefaultedMoveAssignmentIsDeleted @@ -973,6 +977,7 @@ bool ASTNodeImporter::ImportDefinition(RecordDecl *From, RecordDecl *To, = FromData.HasConstexprNonCopyMoveConstructor; ToData.HasDefaultedDefaultConstructor = FromData.HasDefaultedDefaultConstructor; + ToData.CanPassInRegisters = FromData.CanPassInRegisters; ToData.DefaultedDefaultConstructorIsConstexpr = FromData.DefaultedDefaultConstructorIsConstexpr; ToData.HasConstexprDefaultConstructor diff --git a/contrib/llvm/tools/clang/lib/AST/DeclCXX.cpp b/contrib/llvm/tools/clang/lib/AST/DeclCXX.cpp index 1caceab85eea..5782b7b56c96 100644 --- a/contrib/llvm/tools/clang/lib/AST/DeclCXX.cpp +++ b/contrib/llvm/tools/clang/lib/AST/DeclCXX.cpp @@ -55,15 +55,18 @@ CXXRecordDecl::DefinitionData::DefinitionData(CXXRecordDecl *D) HasOnlyCMembers(true), HasInClassInitializer(false), HasUninitializedReferenceMember(false), HasUninitializedFields(false), HasInheritedConstructor(false), HasInheritedAssignment(false), + NeedOverloadResolutionForCopyConstructor(false), NeedOverloadResolutionForMoveConstructor(false), NeedOverloadResolutionForMoveAssignment(false), NeedOverloadResolutionForDestructor(false), + DefaultedCopyConstructorIsDeleted(false), DefaultedMoveConstructorIsDeleted(false), DefaultedMoveAssignmentIsDeleted(false), DefaultedDestructorIsDeleted(false), HasTrivialSpecialMembers(SMF_All), DeclaredNonTrivialSpecialMembers(0), HasIrrelevantDestructor(true), HasConstexprNonCopyMoveConstructor(false), HasDefaultedDefaultConstructor(false), + CanPassInRegisters(true), DefaultedDefaultConstructorIsConstexpr(true), HasConstexprDefaultConstructor(false), HasNonLiteralTypeFieldsOrBases(false), ComputedVisibleConversions(false), @@ -352,8 +355,10 @@ CXXRecordDecl::setBases(CXXBaseSpecifier const * const *Bases, setHasVolatileMember(true); // Keep track of the presence of mutable fields. - if (BaseClassDecl->hasMutableFields()) + if (BaseClassDecl->hasMutableFields()) { data().HasMutableFields = true; + data().NeedOverloadResolutionForCopyConstructor = true; + } if (BaseClassDecl->hasUninitializedReferenceMember()) data().HasUninitializedReferenceMember = true; @@ -406,6 +411,8 @@ void CXXRecordDecl::addedClassSubobject(CXXRecordDecl *Subobj) { // -- a direct or virtual base class B that cannot be copied/moved [...] // -- a non-static data member of class type M (or array thereof) // that cannot be copied or moved [...] + if (!Subobj->hasSimpleCopyConstructor()) + data().NeedOverloadResolutionForCopyConstructor = true; if (!Subobj->hasSimpleMoveConstructor()) data().NeedOverloadResolutionForMoveConstructor = true; @@ -426,6 +433,7 @@ void CXXRecordDecl::addedClassSubobject(CXXRecordDecl *Subobj) { // -- any non-static data member has a type with a destructor // that is deleted or inaccessible from the defaulted [ctor or dtor]. if (!Subobj->hasSimpleDestructor()) { + data().NeedOverloadResolutionForCopyConstructor = true; data().NeedOverloadResolutionForMoveConstructor = true; data().NeedOverloadResolutionForDestructor = true; } @@ -711,8 +719,10 @@ void CXXRecordDecl::addedMember(Decl *D) { data().IsStandardLayout = false; // Keep track of the presence of mutable fields. - if (Field->isMutable()) + if (Field->isMutable()) { data().HasMutableFields = true; + data().NeedOverloadResolutionForCopyConstructor = true; + } // C++11 [class.union]p8, DR1460: // If X is a union, a non-static data member of X that is not an anonymous @@ -756,6 +766,12 @@ void CXXRecordDecl::addedMember(Decl *D) { // A standard-layout class is a class that: // -- has no non-static data members of type [...] reference, data().IsStandardLayout = false; + + // C++1z [class.copy.ctor]p10: + // A defaulted copy constructor for a class X is defined as deleted if X has: + // -- a non-static data member of rvalue reference type + if (T->isRValueReferenceType()) + data().DefaultedCopyConstructorIsDeleted = true; } if (!Field->hasInClassInitializer() && !Field->isMutable()) { @@ -809,6 +825,10 @@ void CXXRecordDecl::addedMember(Decl *D) { // We may need to perform overload resolution to determine whether a // field can be moved if it's const or volatile qualified. if (T.getCVRQualifiers() & (Qualifiers::Const | Qualifiers::Volatile)) { + // We need to care about 'const' for the copy constructor because an + // implicit copy constructor might be declared with a non-const + // parameter. + data().NeedOverloadResolutionForCopyConstructor = true; data().NeedOverloadResolutionForMoveConstructor = true; data().NeedOverloadResolutionForMoveAssignment = true; } @@ -819,6 +839,8 @@ void CXXRecordDecl::addedMember(Decl *D) { // -- X is a union-like class that has a variant member with a // non-trivial [corresponding special member] if (isUnion()) { + if (FieldRec->hasNonTrivialCopyConstructor()) + data().DefaultedCopyConstructorIsDeleted = true; if (FieldRec->hasNonTrivialMoveConstructor()) data().DefaultedMoveConstructorIsDeleted = true; if (FieldRec->hasNonTrivialMoveAssignment()) @@ -830,6 +852,8 @@ void CXXRecordDecl::addedMember(Decl *D) { // For an anonymous union member, our overload resolution will perform // overload resolution for its members. if (Field->isAnonymousStructOrUnion()) { + data().NeedOverloadResolutionForCopyConstructor |= + FieldRec->data().NeedOverloadResolutionForCopyConstructor; data().NeedOverloadResolutionForMoveConstructor |= FieldRec->data().NeedOverloadResolutionForMoveConstructor; data().NeedOverloadResolutionForMoveAssignment |= @@ -915,8 +939,10 @@ void CXXRecordDecl::addedMember(Decl *D) { } // Keep track of the presence of mutable fields. - if (FieldRec->hasMutableFields()) + if (FieldRec->hasMutableFields()) { data().HasMutableFields = true; + data().NeedOverloadResolutionForCopyConstructor = true; + } // C++11 [class.copy]p13: // If the implicitly-defined constructor would satisfy the @@ -1450,7 +1476,7 @@ void CXXRecordDecl::completeDefinition() { void CXXRecordDecl::completeDefinition(CXXFinalOverriderMap *FinalOverriders) { RecordDecl::completeDefinition(); - + // If the class may be abstract (but hasn't been marked as such), check for // any pure final overriders. if (mayBeAbstract()) { diff --git a/contrib/llvm/tools/clang/lib/CodeGen/CGCXXABI.cpp b/contrib/llvm/tools/clang/lib/CodeGen/CGCXXABI.cpp index e29e525edd24..033258643ddf 100644 --- a/contrib/llvm/tools/clang/lib/CodeGen/CGCXXABI.cpp +++ b/contrib/llvm/tools/clang/lib/CodeGen/CGCXXABI.cpp @@ -30,38 +30,9 @@ void CGCXXABI::ErrorUnsupportedABI(CodeGenFunction &CGF, StringRef S) { } bool CGCXXABI::canCopyArgument(const CXXRecordDecl *RD) const { - // If RD has a non-trivial move or copy constructor, we cannot copy the - // argument. - if (RD->hasNonTrivialCopyConstructor() || RD->hasNonTrivialMoveConstructor()) - return false; - - // If RD has a non-trivial destructor, we cannot copy the argument. - if (RD->hasNonTrivialDestructor()) - return false; - // We can only copy the argument if there exists at least one trivial, // non-deleted copy or move constructor. - // FIXME: This assumes that all lazily declared copy and move constructors are - // not deleted. This assumption might not be true in some corner cases. - bool CopyDeleted = false; - bool MoveDeleted = false; - for (const CXXConstructorDecl *CD : RD->ctors()) { - if (CD->isCopyConstructor() || CD->isMoveConstructor()) { - assert(CD->isTrivial()); - // We had at least one undeleted trivial copy or move ctor. Return - // directly. - if (!CD->isDeleted()) - return true; - if (CD->isCopyConstructor()) - CopyDeleted = true; - else - MoveDeleted = true; - } - } - - // If all trivial copy and move constructors are deleted, we cannot copy the - // argument. - return !(CopyDeleted && MoveDeleted); + return RD->canPassInRegisters(); } llvm::Constant *CGCXXABI::GetBogusMemberPointer(QualType T) { diff --git a/contrib/llvm/tools/clang/lib/CodeGen/ItaniumCXXABI.cpp b/contrib/llvm/tools/clang/lib/CodeGen/ItaniumCXXABI.cpp index c82b9677eacf..e7963674fc29 100644 --- a/contrib/llvm/tools/clang/lib/CodeGen/ItaniumCXXABI.cpp +++ b/contrib/llvm/tools/clang/lib/CodeGen/ItaniumCXXABI.cpp @@ -63,11 +63,8 @@ public: bool classifyReturnType(CGFunctionInfo &FI) const override; RecordArgABI getRecordArgABI(const CXXRecordDecl *RD) const override { - // Structures with either a non-trivial destructor or a non-trivial - // copy constructor are always indirect. - // FIXME: Use canCopyArgument() when it is fixed to handle lazily declared - // special members. - if (RD->hasNonTrivialDestructor() || RD->hasNonTrivialCopyConstructor()) + // If C++ prohibits us from making a copy, pass by address. + if (!canCopyArgument(RD)) return RAA_Indirect; return RAA_Default; } @@ -998,10 +995,8 @@ bool ItaniumCXXABI::classifyReturnType(CGFunctionInfo &FI) const { if (!RD) return false; - // Return indirectly if we have a non-trivial copy ctor or non-trivial dtor. - // FIXME: Use canCopyArgument() when it is fixed to handle lazily declared - // special members. - if (RD->hasNonTrivialDestructor() || RD->hasNonTrivialCopyConstructor()) { + // If C++ prohibits us from making a copy, return by address. + if (!canCopyArgument(RD)) { auto Align = CGM.getContext().getTypeAlignInChars(FI.getReturnType()); FI.getReturnInfo() = ABIArgInfo::getIndirect(Align, /*ByVal=*/false); return true; diff --git a/contrib/llvm/tools/clang/lib/CodeGen/MicrosoftCXXABI.cpp b/contrib/llvm/tools/clang/lib/CodeGen/MicrosoftCXXABI.cpp index 78b510bb4665..1bd2937e4747 100644 --- a/contrib/llvm/tools/clang/lib/CodeGen/MicrosoftCXXABI.cpp +++ b/contrib/llvm/tools/clang/lib/CodeGen/MicrosoftCXXABI.cpp @@ -819,46 +819,44 @@ MicrosoftCXXABI::getRecordArgABI(const CXXRecordDecl *RD) const { return RAA_Default; case llvm::Triple::x86_64: - // Win64 passes objects with non-trivial copy ctors indirectly. - if (RD->hasNonTrivialCopyConstructor()) - return RAA_Indirect; - - // If an object has a destructor, we'd really like to pass it indirectly + // If a class has a destructor, we'd really like to pass it indirectly // because it allows us to elide copies. Unfortunately, MSVC makes that // impossible for small types, which it will pass in a single register or // stack slot. Most objects with dtors are large-ish, so handle that early. // We can't call out all large objects as being indirect because there are // multiple x64 calling conventions and the C++ ABI code shouldn't dictate // how we pass large POD types. + // + // Note: This permits small classes with nontrivial destructors to be + // passed in registers, which is non-conforming. if (RD->hasNonTrivialDestructor() && getContext().getTypeSize(RD->getTypeForDecl()) > 64) return RAA_Indirect; - // If this is true, the implicit copy constructor that Sema would have - // created would not be deleted. FIXME: We should provide a more direct way - // for CodeGen to ask whether the constructor was deleted. - if (!RD->hasUserDeclaredCopyConstructor() && - !RD->hasUserDeclaredMoveConstructor() && - !RD->needsOverloadResolutionForMoveConstructor() && - !RD->hasUserDeclaredMoveAssignment() && - !RD->needsOverloadResolutionForMoveAssignment()) - return RAA_Default; - - // Otherwise, Sema should have created an implicit copy constructor if - // needed. - assert(!RD->needsImplicitCopyConstructor()); - - // We have to make sure the trivial copy constructor isn't deleted. - for (const CXXConstructorDecl *CD : RD->ctors()) { - if (CD->isCopyConstructor()) { - assert(CD->isTrivial()); - // We had at least one undeleted trivial copy ctor. Return directly. - if (!CD->isDeleted()) - return RAA_Default; + // If a class has at least one non-deleted, trivial copy constructor, it + // is passed according to the C ABI. Otherwise, it is passed indirectly. + // + // Note: This permits classes with non-trivial copy or move ctors to be + // passed in registers, so long as they *also* have a trivial copy ctor, + // which is non-conforming. + if (RD->needsImplicitCopyConstructor()) { + // If the copy ctor has not yet been declared, we can read its triviality + // off the AST. + if (!RD->defaultedCopyConstructorIsDeleted() && + RD->hasTrivialCopyConstructor()) + return RAA_Default; + } else { + // Otherwise, we need to find the copy constructor(s) and ask. + for (const CXXConstructorDecl *CD : RD->ctors()) { + if (CD->isCopyConstructor()) { + // We had at least one nondeleted trivial copy ctor. Return directly. + if (!CD->isDeleted() && CD->isTrivial()) + return RAA_Default; + } } } - // The trivial copy constructor was deleted. Return indirectly. + // We have no trivial, non-deleted copy constructor. return RAA_Indirect; } diff --git a/contrib/llvm/tools/clang/lib/Driver/ToolChains/Darwin.cpp b/contrib/llvm/tools/clang/lib/Driver/ToolChains/Darwin.cpp index 6b7f0c71dfb7..32103a6120d4 100644 --- a/contrib/llvm/tools/clang/lib/Driver/ToolChains/Darwin.cpp +++ b/contrib/llvm/tools/clang/lib/Driver/ToolChains/Darwin.cpp @@ -1837,7 +1837,12 @@ Darwin::TranslateArgs(const DerivedArgList &Args, StringRef BoundArch, } bool MachO::IsUnwindTablesDefault(const ArgList &Args) const { - return !UseSjLjExceptions(Args); + // Unwind tables are not emitted if -fno-exceptions is supplied (except when + // targeting x86_64). + return getArch() == llvm::Triple::x86_64 || + (!UseSjLjExceptions(Args) && + Args.hasFlag(options::OPT_fexceptions, options::OPT_fno_exceptions, + true)); } bool MachO::UseDwarfDebugFlags() const { diff --git a/contrib/llvm/tools/clang/lib/Driver/ToolChains/MSVC.cpp b/contrib/llvm/tools/clang/lib/Driver/ToolChains/MSVC.cpp index b871c856d2a0..7978a6941cb8 100644 --- a/contrib/llvm/tools/clang/lib/Driver/ToolChains/MSVC.cpp +++ b/contrib/llvm/tools/clang/lib/Driver/ToolChains/MSVC.cpp @@ -76,7 +76,7 @@ static bool getSystemRegistryString(const char *keyPath, const char *valueName, // Check various environment variables to try and find a toolchain. static bool findVCToolChainViaEnvironment(std::string &Path, - bool &IsVS2017OrNewer) { + MSVCToolChain::ToolsetLayout &VSLayout) { // These variables are typically set by vcvarsall.bat // when launching a developer command prompt. if (llvm::Optional<std::string> VCToolsInstallDir = @@ -84,7 +84,7 @@ static bool findVCToolChainViaEnvironment(std::string &Path, // This is only set by newer Visual Studios, and it leads straight to // the toolchain directory. Path = std::move(*VCToolsInstallDir); - IsVS2017OrNewer = true; + VSLayout = MSVCToolChain::ToolsetLayout::VS2017OrNewer; return true; } if (llvm::Optional<std::string> VCInstallDir = @@ -94,7 +94,7 @@ static bool findVCToolChainViaEnvironment(std::string &Path, // so this check has to appear second. // In older Visual Studios, the VC directory is the toolchain. Path = std::move(*VCInstallDir); - IsVS2017OrNewer = false; + VSLayout = MSVCToolChain::ToolsetLayout::OlderVS; return true; } @@ -134,9 +134,16 @@ static bool findVCToolChainViaEnvironment(std::string &Path, } if (IsBin) { llvm::StringRef ParentPath = llvm::sys::path::parent_path(TestPath); - if (llvm::sys::path::filename(ParentPath) == "VC") { + llvm::StringRef ParentFilename = llvm::sys::path::filename(ParentPath); + if (ParentFilename == "VC") { Path = ParentPath; - IsVS2017OrNewer = false; + VSLayout = MSVCToolChain::ToolsetLayout::OlderVS; + return true; + } + if (ParentFilename == "x86ret" || ParentFilename == "x86chk" + || ParentFilename == "amd64ret" || ParentFilename == "amd64chk") { + Path = ParentPath; + VSLayout = MSVCToolChain::ToolsetLayout::DevDivInternal; return true; } @@ -165,7 +172,7 @@ static bool findVCToolChainViaEnvironment(std::string &Path, ToolChainPath = llvm::sys::path::parent_path(ToolChainPath); Path = ToolChainPath; - IsVS2017OrNewer = true; + VSLayout = MSVCToolChain::ToolsetLayout::VS2017OrNewer; return true; } @@ -181,7 +188,7 @@ static bool findVCToolChainViaEnvironment(std::string &Path, // This is the preferred way to discover new Visual Studios, as they're no // longer listed in the registry. static bool findVCToolChainViaSetupConfig(std::string &Path, - bool &IsVS2017OrNewer) { + MSVCToolChain::ToolsetLayout &VSLayout) { #if !defined(USE_MSVC_SETUP_API) return false; #else @@ -263,7 +270,7 @@ static bool findVCToolChainViaSetupConfig(std::string &Path, return false; Path = ToolchainPath.str(); - IsVS2017OrNewer = true; + VSLayout = MSVCToolChain::ToolsetLayout::VS2017OrNewer; return true; #endif } @@ -272,7 +279,7 @@ static bool findVCToolChainViaSetupConfig(std::string &Path, // a toolchain path. VS2017 and newer don't get added to the registry. // So if we find something here, we know that it's an older version. static bool findVCToolChainViaRegistry(std::string &Path, - bool &IsVS2017OrNewer) { + MSVCToolChain::ToolsetLayout &VSLayout) { std::string VSInstallPath; if (getSystemRegistryString(R"(SOFTWARE\Microsoft\VisualStudio\$VERSION)", "InstallDir", VSInstallPath, nullptr) || @@ -284,7 +291,7 @@ static bool findVCToolChainViaRegistry(std::string &Path, llvm::sys::path::append(VCPath, "VC"); Path = VCPath.str(); - IsVS2017OrNewer = false; + VSLayout = MSVCToolChain::ToolsetLayout::OlderVS; return true; } } @@ -475,6 +482,7 @@ void visualstudio::Linker::ConstructJob(Compilation &C, const JobAction &JA, // native target bin directory. // e.g. when compiling for x86 on an x64 host, PATH should start with: // /bin/HostX64/x86;/bin/HostX64/x64 + // This doesn't attempt to handle ToolsetLayout::DevDivInternal. if (TC.getIsVS2017OrNewer() && llvm::Triple(llvm::sys::getProcessTriple()).getArch() != TC.getArch()) { auto HostArch = llvm::Triple(llvm::sys::getProcessTriple()).getArch(); @@ -677,9 +685,9 @@ MSVCToolChain::MSVCToolChain(const Driver &D, const llvm::Triple &Triple, // what they want to use. // Failing that, just try to find the newest Visual Studio version we can // and use its default VC toolchain. - findVCToolChainViaEnvironment(VCToolChainPath, IsVS2017OrNewer) || - findVCToolChainViaSetupConfig(VCToolChainPath, IsVS2017OrNewer) || - findVCToolChainViaRegistry(VCToolChainPath, IsVS2017OrNewer); + findVCToolChainViaEnvironment(VCToolChainPath, VSLayout) || + findVCToolChainViaSetupConfig(VCToolChainPath, VSLayout) || + findVCToolChainViaRegistry(VCToolChainPath, VSLayout); } Tool *MSVCToolChain::buildLinker() const { @@ -766,6 +774,21 @@ static const char *llvmArchToLegacyVCArch(llvm::Triple::ArchType Arch) { } } +// Similar to the above function, but for DevDiv internal builds. +static const char *llvmArchToDevDivInternalArch(llvm::Triple::ArchType Arch) { + using ArchType = llvm::Triple::ArchType; + switch (Arch) { + case ArchType::x86: + return "i386"; + case ArchType::x86_64: + return "amd64"; + case ArchType::arm: + return "arm"; + default: + return ""; + } +} + // Get the path to a specific subdirectory in the current toolchain for // a given target architecture. // VS2017 changed the VC toolchain layout, so this should be used instead @@ -773,26 +796,40 @@ static const char *llvmArchToLegacyVCArch(llvm::Triple::ArchType Arch) { std::string MSVCToolChain::getSubDirectoryPath(SubDirectoryType Type, llvm::Triple::ArchType TargetArch) const { + const char *SubdirName; + const char *IncludeName; + switch (VSLayout) { + case ToolsetLayout::OlderVS: + SubdirName = llvmArchToLegacyVCArch(TargetArch); + IncludeName = "include"; + break; + case ToolsetLayout::VS2017OrNewer: + SubdirName = llvmArchToWindowsSDKArch(TargetArch); + IncludeName = "include"; + break; + case ToolsetLayout::DevDivInternal: + SubdirName = llvmArchToDevDivInternalArch(TargetArch); + IncludeName = "inc"; + break; + } + llvm::SmallString<256> Path(VCToolChainPath); switch (Type) { case SubDirectoryType::Bin: - if (IsVS2017OrNewer) { - bool HostIsX64 = + if (VSLayout == ToolsetLayout::VS2017OrNewer) { + const bool HostIsX64 = llvm::Triple(llvm::sys::getProcessTriple()).isArch64Bit(); - llvm::sys::path::append(Path, "bin", (HostIsX64 ? "HostX64" : "HostX86"), - llvmArchToWindowsSDKArch(TargetArch)); - - } else { - llvm::sys::path::append(Path, "bin", llvmArchToLegacyVCArch(TargetArch)); + const char *const HostName = HostIsX64 ? "HostX64" : "HostX86"; + llvm::sys::path::append(Path, "bin", HostName, SubdirName); + } else { // OlderVS or DevDivInternal + llvm::sys::path::append(Path, "bin", SubdirName); } break; case SubDirectoryType::Include: - llvm::sys::path::append(Path, "include"); + llvm::sys::path::append(Path, IncludeName); break; case SubDirectoryType::Lib: - llvm::sys::path::append( - Path, "lib", IsVS2017OrNewer ? llvmArchToWindowsSDKArch(TargetArch) - : llvmArchToLegacyVCArch(TargetArch)); + llvm::sys::path::append(Path, "lib", SubdirName); break; } return Path.str(); diff --git a/contrib/llvm/tools/clang/lib/Driver/ToolChains/MSVC.h b/contrib/llvm/tools/clang/lib/Driver/ToolChains/MSVC.h index d153691a5c90..854f88a36fd2 100644 --- a/contrib/llvm/tools/clang/lib/Driver/ToolChains/MSVC.h +++ b/contrib/llvm/tools/clang/lib/Driver/ToolChains/MSVC.h @@ -92,7 +92,12 @@ public: return getSubDirectoryPath(Type, getArch()); } - bool getIsVS2017OrNewer() const { return IsVS2017OrNewer; } + enum class ToolsetLayout { + OlderVS, + VS2017OrNewer, + DevDivInternal, + }; + bool getIsVS2017OrNewer() const { return VSLayout == ToolsetLayout::VS2017OrNewer; } void AddClangSystemIncludeArgs(const llvm::opt::ArgList &DriverArgs, @@ -130,7 +135,7 @@ protected: Tool *buildAssembler() const override; private: std::string VCToolChainPath; - bool IsVS2017OrNewer = false; + ToolsetLayout VSLayout = ToolsetLayout::OlderVS; CudaInstallationDetector CudaInstallation; }; diff --git a/contrib/llvm/tools/clang/lib/Format/WhitespaceManager.cpp b/contrib/llvm/tools/clang/lib/Format/WhitespaceManager.cpp index 4b4fd13145fb..b1a5f1eab552 100644 --- a/contrib/llvm/tools/clang/lib/Format/WhitespaceManager.cpp +++ b/contrib/llvm/tools/clang/lib/Format/WhitespaceManager.cpp @@ -472,9 +472,14 @@ void WhitespaceManager::alignTrailingComments() { continue; unsigned ChangeMinColumn = Changes[i].StartOfTokenColumn; - unsigned ChangeMaxColumn = Style.ColumnLimit >= Changes[i].TokenLength - ? Style.ColumnLimit - Changes[i].TokenLength - : ChangeMinColumn; + unsigned ChangeMaxColumn; + + if (Style.ColumnLimit == 0) + ChangeMaxColumn = UINT_MAX; + else if (Style.ColumnLimit >= Changes[i].TokenLength) + ChangeMaxColumn = Style.ColumnLimit - Changes[i].TokenLength; + else + ChangeMaxColumn = ChangeMinColumn; // If we don't create a replacement for this change, we have to consider // it to be immovable. diff --git a/contrib/llvm/tools/clang/lib/Headers/unwind.h b/contrib/llvm/tools/clang/lib/Headers/unwind.h index e94b00b57c26..4f74a3478740 100644 --- a/contrib/llvm/tools/clang/lib/Headers/unwind.h +++ b/contrib/llvm/tools/clang/lib/Headers/unwind.h @@ -76,13 +76,7 @@ typedef intptr_t _sleb128_t; typedef uintptr_t _uleb128_t; struct _Unwind_Context; -#if defined(__arm__) && !(defined(__USING_SJLJ_EXCEPTIONS__) || defined(__ARM_DWARF_EH___)) -struct _Unwind_Control_Block; -typedef struct _Unwind_Control_Block _Unwind_Exception; /* Alias */ -#else struct _Unwind_Exception; -typedef struct _Unwind_Exception _Unwind_Exception; -#endif typedef enum { _URC_NO_REASON = 0, #if defined(__arm__) && !defined(__USING_SJLJ_EXCEPTIONS__) && \ @@ -115,42 +109,8 @@ typedef enum { } _Unwind_Action; typedef void (*_Unwind_Exception_Cleanup_Fn)(_Unwind_Reason_Code, - _Unwind_Exception *); - -#if defined(__arm__) && !(defined(__USING_SJLJ_EXCEPTIONS__) || defined(__ARM_DWARF_EH___)) -typedef struct _Unwind_Control_Block _Unwind_Control_Block; -typedef uint32_t _Unwind_EHT_Header; - -struct _Unwind_Control_Block { - uint64_t exception_class; - void (*exception_cleanup)(_Unwind_Reason_Code, _Unwind_Control_Block *); - /* unwinder cache (private fields for the unwinder's use) */ - struct { - uint32_t reserved1; /* forced unwind stop function, 0 if not forced */ - uint32_t reserved2; /* personality routine */ - uint32_t reserved3; /* callsite */ - uint32_t reserved4; /* forced unwind stop argument */ - uint32_t reserved5; - } unwinder_cache; - /* propagation barrier cache (valid after phase 1) */ - struct { - uint32_t sp; - uint32_t bitpattern[5]; - } barrier_cache; - /* cleanup cache (preserved over cleanup) */ - struct { - uint32_t bitpattern[4]; - } cleanup_cache; - /* personality cache (for personality's benefit) */ - struct { - uint32_t fnstart; /* function start address */ - _Unwind_EHT_Header *ehtp; /* pointer to EHT entry header word */ - uint32_t additional; /* additional data */ - uint32_t reserved1; - } pr_cache; - long long int : 0; /* force alignment of next item to 8-byte boundary */ -}; -#else + struct _Unwind_Exception *); + struct _Unwind_Exception { _Unwind_Exception_Class exception_class; _Unwind_Exception_Cleanup_Fn exception_cleanup; @@ -160,24 +120,23 @@ struct _Unwind_Exception { * aligned". GCC has interpreted this to mean "use the maximum useful * alignment for the target"; so do we. */ } __attribute__((__aligned__)); -#endif typedef _Unwind_Reason_Code (*_Unwind_Stop_Fn)(int, _Unwind_Action, _Unwind_Exception_Class, - _Unwind_Exception *, + struct _Unwind_Exception *, struct _Unwind_Context *, void *); -typedef _Unwind_Reason_Code (*_Unwind_Personality_Fn)(int, _Unwind_Action, - _Unwind_Exception_Class, - _Unwind_Exception *, - struct _Unwind_Context *); +typedef _Unwind_Reason_Code (*_Unwind_Personality_Fn)( + int, _Unwind_Action, _Unwind_Exception_Class, struct _Unwind_Exception *, + struct _Unwind_Context *); typedef _Unwind_Personality_Fn __personality_routine; typedef _Unwind_Reason_Code (*_Unwind_Trace_Fn)(struct _Unwind_Context *, void *); -#if defined(__arm__) && !(defined(__USING_SJLJ_EXCEPTIONS__) || defined(__ARM_DWARF_EH___)) +#if defined(__arm__) && !defined(__APPLE__) + typedef enum { _UVRSC_CORE = 0, /* integer register */ _UVRSC_VFP = 1, /* vfp */ @@ -199,12 +158,14 @@ typedef enum { _UVRSR_FAILED = 2 } _Unwind_VRS_Result; +#if !defined(__USING_SJLJ_EXCEPTIONS__) && !defined(__ARM_DWARF_EH__) typedef uint32_t _Unwind_State; #define _US_VIRTUAL_UNWIND_FRAME ((_Unwind_State)0) #define _US_UNWIND_FRAME_STARTING ((_Unwind_State)1) #define _US_UNWIND_FRAME_RESUME ((_Unwind_State)2) #define _US_ACTION_MASK ((_Unwind_State)3) #define _US_FORCE_UNWIND ((_Unwind_State)8) +#endif _Unwind_VRS_Result _Unwind_VRS_Get(struct _Unwind_Context *__context, _Unwind_VRS_RegClass __regclass, @@ -263,12 +224,13 @@ _Unwind_Ptr _Unwind_GetRegionStart(struct _Unwind_Context *); /* DWARF EH functions; currently not available on Darwin/ARM */ #if !defined(__APPLE__) || !defined(__arm__) -_Unwind_Reason_Code _Unwind_RaiseException(_Unwind_Exception *); -_Unwind_Reason_Code _Unwind_ForcedUnwind(_Unwind_Exception *, _Unwind_Stop_Fn, - void *); -void _Unwind_DeleteException(_Unwind_Exception *); -void _Unwind_Resume(_Unwind_Exception *); -_Unwind_Reason_Code _Unwind_Resume_or_Rethrow(_Unwind_Exception *); + +_Unwind_Reason_Code _Unwind_RaiseException(struct _Unwind_Exception *); +_Unwind_Reason_Code _Unwind_ForcedUnwind(struct _Unwind_Exception *, + _Unwind_Stop_Fn, void *); +void _Unwind_DeleteException(struct _Unwind_Exception *); +void _Unwind_Resume(struct _Unwind_Exception *); +_Unwind_Reason_Code _Unwind_Resume_or_Rethrow(struct _Unwind_Exception *); #endif @@ -279,11 +241,11 @@ typedef struct SjLj_Function_Context *_Unwind_FunctionContext_t; void _Unwind_SjLj_Register(_Unwind_FunctionContext_t); void _Unwind_SjLj_Unregister(_Unwind_FunctionContext_t); -_Unwind_Reason_Code _Unwind_SjLj_RaiseException(_Unwind_Exception *); -_Unwind_Reason_Code _Unwind_SjLj_ForcedUnwind(_Unwind_Exception *, +_Unwind_Reason_Code _Unwind_SjLj_RaiseException(struct _Unwind_Exception *); +_Unwind_Reason_Code _Unwind_SjLj_ForcedUnwind(struct _Unwind_Exception *, _Unwind_Stop_Fn, void *); -void _Unwind_SjLj_Resume(_Unwind_Exception *); -_Unwind_Reason_Code _Unwind_SjLj_Resume_or_Rethrow(_Unwind_Exception *); +void _Unwind_SjLj_Resume(struct _Unwind_Exception *); +_Unwind_Reason_Code _Unwind_SjLj_Resume_or_Rethrow(struct _Unwind_Exception *); void *_Unwind_FindEnclosingFunction(void *); diff --git a/contrib/llvm/tools/clang/lib/Lex/PPLexerChange.cpp b/contrib/llvm/tools/clang/lib/Lex/PPLexerChange.cpp index 5a589d6a17b3..36d7028da688 100644 --- a/contrib/llvm/tools/clang/lib/Lex/PPLexerChange.cpp +++ b/contrib/llvm/tools/clang/lib/Lex/PPLexerChange.cpp @@ -458,10 +458,16 @@ bool Preprocessor::HandleEndOfFile(Token &Result, bool isEndOfMacro) { SourceMgr.setNumCreatedFIDsForFileID(CurPPLexer->getFileID(), NumFIDs); } + bool ExitedFromPredefinesFile = false; FileID ExitedFID; - if (Callbacks && !isEndOfMacro && CurPPLexer) + if (!isEndOfMacro && CurPPLexer) { ExitedFID = CurPPLexer->getFileID(); + assert(PredefinesFileID.isValid() && + "HandleEndOfFile is called before PredefinesFileId is set"); + ExitedFromPredefinesFile = (PredefinesFileID == ExitedFID); + } + if (LeavingSubmodule) { // We're done with this submodule. Module *M = LeaveSubmodule(/*ForPragma*/false); @@ -489,6 +495,11 @@ bool Preprocessor::HandleEndOfFile(Token &Result, bool isEndOfMacro) { PPCallbacks::ExitFile, FileType, ExitedFID); } + // Restore conditional stack from the preamble right after exiting from the + // predefines file. + if (ExitedFromPredefinesFile) + replayPreambleConditionalStack(); + // Client should lex another token unless we generated an EOM. return LeavingSubmodule; } diff --git a/contrib/llvm/tools/clang/lib/Lex/Preprocessor.cpp b/contrib/llvm/tools/clang/lib/Lex/Preprocessor.cpp index d1dc8e1c0010..7979be773aa1 100644 --- a/contrib/llvm/tools/clang/lib/Lex/Preprocessor.cpp +++ b/contrib/llvm/tools/clang/lib/Lex/Preprocessor.cpp @@ -540,6 +540,8 @@ void Preprocessor::EnterMainSourceFile() { void Preprocessor::replayPreambleConditionalStack() { // Restore the conditional stack from the preamble, if there is one. if (PreambleConditionalStack.isReplaying()) { + assert(CurPPLexer && + "CurPPLexer is null when calling replayPreambleConditionalStack."); CurPPLexer->setConditionalLevels(PreambleConditionalStack.getStack()); PreambleConditionalStack.doneReplaying(); } diff --git a/contrib/llvm/tools/clang/lib/Parse/Parser.cpp b/contrib/llvm/tools/clang/lib/Parse/Parser.cpp index 4aa9a5971929..1ed7ef966358 100644 --- a/contrib/llvm/tools/clang/lib/Parse/Parser.cpp +++ b/contrib/llvm/tools/clang/lib/Parse/Parser.cpp @@ -516,8 +516,6 @@ void Parser::Initialize() { // Prime the lexer look-ahead. ConsumeToken(); - - PP.replayPreambleConditionalStack(); } void Parser::LateTemplateParserCleanupCallback(void *P) { diff --git a/contrib/llvm/tools/clang/lib/Sema/SemaDeclCXX.cpp b/contrib/llvm/tools/clang/lib/Sema/SemaDeclCXX.cpp index e9070881afe4..c05e5f020708 100644 --- a/contrib/llvm/tools/clang/lib/Sema/SemaDeclCXX.cpp +++ b/contrib/llvm/tools/clang/lib/Sema/SemaDeclCXX.cpp @@ -5726,6 +5726,53 @@ static void DefineImplicitSpecialMember(Sema &S, CXXMethodDecl *MD, } } +/// Determine whether a type is permitted to be passed or returned in +/// registers, per C++ [class.temporary]p3. +static bool computeCanPassInRegisters(Sema &S, CXXRecordDecl *D) { + if (D->isDependentType() || D->isInvalidDecl()) + return false; + + // Per C++ [class.temporary]p3, the relevant condition is: + // each copy constructor, move constructor, and destructor of X is + // either trivial or deleted, and X has at least one non-deleted copy + // or move constructor + bool HasNonDeletedCopyOrMove = false; + + if (D->needsImplicitCopyConstructor() && + !D->defaultedCopyConstructorIsDeleted()) { + if (!D->hasTrivialCopyConstructor()) + return false; + HasNonDeletedCopyOrMove = true; + } + + if (S.getLangOpts().CPlusPlus11 && D->needsImplicitMoveConstructor() && + !D->defaultedMoveConstructorIsDeleted()) { + if (!D->hasTrivialMoveConstructor()) + return false; + HasNonDeletedCopyOrMove = true; + } + + if (D->needsImplicitDestructor() && !D->defaultedDestructorIsDeleted() && + !D->hasTrivialDestructor()) + return false; + + for (const CXXMethodDecl *MD : D->methods()) { + if (MD->isDeleted()) + continue; + + auto *CD = dyn_cast<CXXConstructorDecl>(MD); + if (CD && CD->isCopyOrMoveConstructor()) + HasNonDeletedCopyOrMove = true; + else if (!isa<CXXDestructorDecl>(MD)) + continue; + + if (!MD->isTrivial()) + return false; + } + + return HasNonDeletedCopyOrMove; +} + /// \brief Perform semantic checks on a class definition that has been /// completing, introducing implicitly-declared members, checking for /// abstract types, etc. @@ -5870,6 +5917,8 @@ void Sema::CheckCompletedCXXClass(CXXRecordDecl *Record) { } checkClassLevelDLLAttribute(Record); + + Record->setCanPassInRegisters(computeCanPassInRegisters(*this, Record)); } /// Look up the special member function that would be called by a special @@ -7496,8 +7545,7 @@ void Sema::ActOnFinishCXXMemberSpecification(Scope* S, SourceLocation RLoc, reinterpret_cast<Decl**>(FieldCollector->getCurFields()), FieldCollector->getCurNumFields()), LBrac, RBrac, AttrList); - CheckCompletedCXXClass( - dyn_cast_or_null<CXXRecordDecl>(TagDecl)); + CheckCompletedCXXClass(dyn_cast_or_null<CXXRecordDecl>(TagDecl)); } /// AddImplicitlyDeclaredMembersToClass - Adds any implicitly-declared @@ -11929,8 +11977,10 @@ CXXConstructorDecl *Sema::DeclareImplicitCopyConstructor( Scope *S = getScopeForContext(ClassDecl); CheckImplicitSpecialMemberDeclaration(S, CopyConstructor); - if (ShouldDeleteSpecialMember(CopyConstructor, CXXCopyConstructor)) + if (ShouldDeleteSpecialMember(CopyConstructor, CXXCopyConstructor)) { + ClassDecl->setImplicitCopyConstructorIsDeleted(); SetDeclDeleted(CopyConstructor, ClassLoc); + } if (S) PushOnScopeChains(CopyConstructor, S, false); diff --git a/contrib/llvm/tools/clang/lib/Sema/SemaObjCProperty.cpp b/contrib/llvm/tools/clang/lib/Sema/SemaObjCProperty.cpp index e1e85dfd5e55..bfb0071a54f9 100644 --- a/contrib/llvm/tools/clang/lib/Sema/SemaObjCProperty.cpp +++ b/contrib/llvm/tools/clang/lib/Sema/SemaObjCProperty.cpp @@ -872,7 +872,7 @@ SelectPropertyForSynthesisFromProtocols(Sema &S, SourceLocation AtLoc, } QualType RHSType = S.Context.getCanonicalType(Property->getType()); - unsigned OriginalAttributes = Property->getPropertyAttributes(); + unsigned OriginalAttributes = Property->getPropertyAttributesAsWritten(); enum MismatchKind { IncompatibleType = 0, HasNoExpectedAttribute, @@ -890,7 +890,7 @@ SelectPropertyForSynthesisFromProtocols(Sema &S, SourceLocation AtLoc, SmallVector<MismatchingProperty, 4> Mismatches; for (ObjCPropertyDecl *Prop : Properties) { // Verify the property attributes. - unsigned Attr = Prop->getPropertyAttributes(); + unsigned Attr = Prop->getPropertyAttributesAsWritten(); if (Attr != OriginalAttributes) { auto Diag = [&](bool OriginalHasAttribute, StringRef AttributeName) { MismatchKind Kind = OriginalHasAttribute ? HasNoExpectedAttribute diff --git a/contrib/llvm/tools/clang/lib/Serialization/ASTReaderDecl.cpp b/contrib/llvm/tools/clang/lib/Serialization/ASTReaderDecl.cpp index abed2586561a..085341571ced 100644 --- a/contrib/llvm/tools/clang/lib/Serialization/ASTReaderDecl.cpp +++ b/contrib/llvm/tools/clang/lib/Serialization/ASTReaderDecl.cpp @@ -1559,9 +1559,11 @@ void ASTDeclReader::ReadCXXDefinitionData( Data.HasUninitializedFields = Record.readInt(); Data.HasInheritedConstructor = Record.readInt(); Data.HasInheritedAssignment = Record.readInt(); + Data.NeedOverloadResolutionForCopyConstructor = Record.readInt(); Data.NeedOverloadResolutionForMoveConstructor = Record.readInt(); Data.NeedOverloadResolutionForMoveAssignment = Record.readInt(); Data.NeedOverloadResolutionForDestructor = Record.readInt(); + Data.DefaultedCopyConstructorIsDeleted = Record.readInt(); Data.DefaultedMoveConstructorIsDeleted = Record.readInt(); Data.DefaultedMoveAssignmentIsDeleted = Record.readInt(); Data.DefaultedDestructorIsDeleted = Record.readInt(); @@ -1570,6 +1572,7 @@ void ASTDeclReader::ReadCXXDefinitionData( Data.HasIrrelevantDestructor = Record.readInt(); Data.HasConstexprNonCopyMoveConstructor = Record.readInt(); Data.HasDefaultedDefaultConstructor = Record.readInt(); + Data.CanPassInRegisters = Record.readInt(); Data.DefaultedDefaultConstructorIsConstexpr = Record.readInt(); Data.HasConstexprDefaultConstructor = Record.readInt(); Data.HasNonLiteralTypeFieldsOrBases = Record.readInt(); @@ -1697,9 +1700,11 @@ void ASTDeclReader::MergeDefinitionData( MATCH_FIELD(HasUninitializedFields) MATCH_FIELD(HasInheritedConstructor) MATCH_FIELD(HasInheritedAssignment) + MATCH_FIELD(NeedOverloadResolutionForCopyConstructor) MATCH_FIELD(NeedOverloadResolutionForMoveConstructor) MATCH_FIELD(NeedOverloadResolutionForMoveAssignment) MATCH_FIELD(NeedOverloadResolutionForDestructor) + MATCH_FIELD(DefaultedCopyConstructorIsDeleted) MATCH_FIELD(DefaultedMoveConstructorIsDeleted) MATCH_FIELD(DefaultedMoveAssignmentIsDeleted) MATCH_FIELD(DefaultedDestructorIsDeleted) @@ -1708,6 +1713,7 @@ void ASTDeclReader::MergeDefinitionData( MATCH_FIELD(HasIrrelevantDestructor) OR_FIELD(HasConstexprNonCopyMoveConstructor) OR_FIELD(HasDefaultedDefaultConstructor) + MATCH_FIELD(CanPassInRegisters) MATCH_FIELD(DefaultedDefaultConstructorIsConstexpr) OR_FIELD(HasConstexprDefaultConstructor) MATCH_FIELD(HasNonLiteralTypeFieldsOrBases) diff --git a/contrib/llvm/tools/clang/lib/Serialization/ASTWriter.cpp b/contrib/llvm/tools/clang/lib/Serialization/ASTWriter.cpp index a875e627bdfb..128e53b91b1d 100644 --- a/contrib/llvm/tools/clang/lib/Serialization/ASTWriter.cpp +++ b/contrib/llvm/tools/clang/lib/Serialization/ASTWriter.cpp @@ -5874,9 +5874,11 @@ void ASTRecordWriter::AddCXXDefinitionData(const CXXRecordDecl *D) { Record->push_back(Data.HasUninitializedFields); Record->push_back(Data.HasInheritedConstructor); Record->push_back(Data.HasInheritedAssignment); + Record->push_back(Data.NeedOverloadResolutionForCopyConstructor); Record->push_back(Data.NeedOverloadResolutionForMoveConstructor); Record->push_back(Data.NeedOverloadResolutionForMoveAssignment); Record->push_back(Data.NeedOverloadResolutionForDestructor); + Record->push_back(Data.DefaultedCopyConstructorIsDeleted); Record->push_back(Data.DefaultedMoveConstructorIsDeleted); Record->push_back(Data.DefaultedMoveAssignmentIsDeleted); Record->push_back(Data.DefaultedDestructorIsDeleted); @@ -5885,6 +5887,7 @@ void ASTRecordWriter::AddCXXDefinitionData(const CXXRecordDecl *D) { Record->push_back(Data.HasIrrelevantDestructor); Record->push_back(Data.HasConstexprNonCopyMoveConstructor); Record->push_back(Data.HasDefaultedDefaultConstructor); + Record->push_back(Data.CanPassInRegisters); Record->push_back(Data.DefaultedDefaultConstructorIsConstexpr); Record->push_back(Data.HasConstexprDefaultConstructor); Record->push_back(Data.HasNonLiteralTypeFieldsOrBases); diff --git a/contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/RegionStore.cpp b/contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/RegionStore.cpp index 28f78fa3ff5e..11902f66df91 100644 --- a/contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/RegionStore.cpp +++ b/contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/RegionStore.cpp @@ -409,6 +409,19 @@ public: // Part of public interface to class. // BindDefault is only used to initialize a region with a default value. StoreRef BindDefault(Store store, const MemRegion *R, SVal V) override { + // FIXME: The offsets of empty bases can be tricky because of + // of the so called "empty base class optimization". + // If a base class has been optimized out + // we should not try to create a binding, otherwise we should. + // Unfortunately, at the moment ASTRecordLayout doesn't expose + // the actual sizes of the empty bases + // and trying to infer them from offsets/alignments + // seems to be error-prone and non-trivial because of the trailing padding. + // As a temporary mitigation we don't create bindings for empty bases. + if (R->getKind() == MemRegion::CXXBaseObjectRegionKind && + cast<CXXBaseObjectRegion>(R)->getDecl()->isEmpty()) + return StoreRef(store, *this); + RegionBindingsRef B = getRegionBindings(store); assert(!B.lookup(R, BindingKey::Direct)); diff --git a/contrib/llvm/tools/lldb/source/Plugins/Process/Utility/RegisterContextLinux_i386.cpp b/contrib/llvm/tools/lldb/source/Plugins/Process/Utility/RegisterContextLinux_i386.cpp index 6563796db12c..2cb17cb182e2 100644 --- a/contrib/llvm/tools/lldb/source/Plugins/Process/Utility/RegisterContextLinux_i386.cpp +++ b/contrib/llvm/tools/lldb/source/Plugins/Process/Utility/RegisterContextLinux_i386.cpp @@ -36,8 +36,7 @@ struct GPR { struct FPR_i386 { uint16_t fctrl; // FPU Control Word (fcw) uint16_t fstat; // FPU Status Word (fsw) - uint8_t ftag; // FPU Tag Word (ftw) - uint8_t reserved_1; // Reserved + uint16_t ftag; // FPU Tag Word (ftw) uint16_t fop; // Last Instruction Opcode (fop) union { struct { diff --git a/contrib/llvm/tools/lldb/source/Plugins/Process/Utility/RegisterContext_x86.h b/contrib/llvm/tools/lldb/source/Plugins/Process/Utility/RegisterContext_x86.h index ab2ca2bb6c2c..5f6fc295a15c 100644 --- a/contrib/llvm/tools/lldb/source/Plugins/Process/Utility/RegisterContext_x86.h +++ b/contrib/llvm/tools/lldb/source/Plugins/Process/Utility/RegisterContext_x86.h @@ -257,8 +257,7 @@ struct XMMReg { struct FXSAVE { uint16_t fctrl; // FPU Control Word (fcw) uint16_t fstat; // FPU Status Word (fsw) - uint8_t ftag; // FPU Tag Word (ftw) - uint8_t reserved_1; // Reserved + uint16_t ftag; // FPU Tag Word (ftw) uint16_t fop; // Last Instruction Opcode (fop) union { struct { diff --git a/lib/clang/include/clang/Basic/Version.inc b/lib/clang/include/clang/Basic/Version.inc index 7a9a4f7cc287..41440c4d9efa 100644 --- a/lib/clang/include/clang/Basic/Version.inc +++ b/lib/clang/include/clang/Basic/Version.inc @@ -8,4 +8,4 @@ #define CLANG_VENDOR "FreeBSD " -#define SVN_REVISION "311219" +#define SVN_REVISION "311606" diff --git a/lib/clang/include/lld/Config/Version.inc b/lib/clang/include/lld/Config/Version.inc index c506bdf0fc83..0e0d14e6eb13 100644 --- a/lib/clang/include/lld/Config/Version.inc +++ b/lib/clang/include/lld/Config/Version.inc @@ -4,5 +4,5 @@ #define LLD_VERSION_STRING "5.0.0" #define LLD_VERSION_MAJOR 5 #define LLD_VERSION_MINOR 0 -#define LLD_REVISION_STRING "311219" +#define LLD_REVISION_STRING "311606" #define LLD_REPOSITORY_STRING "FreeBSD" diff --git a/lib/clang/include/llvm/Support/VCSRevision.h b/lib/clang/include/llvm/Support/VCSRevision.h index 8060bd4818f8..11e6679b7b96 100644 --- a/lib/clang/include/llvm/Support/VCSRevision.h +++ b/lib/clang/include/llvm/Support/VCSRevision.h @@ -1,2 +1,2 @@ /* $FreeBSD$ */ -#define LLVM_REVISION "svn-r311219" +#define LLVM_REVISION "svn-r311606" |