Vendor import of llvm release_31 branch r155985:vendor/llvm/llvm-release_31-r155985

http://llvm.org/svn/llvm-project/llvm/branches/release_31@155985

88 files changed, 3810 insertions, 239 deletions

diff --git a/test/Analysis/ScalarEvolution/nsw-offset.ll b/test/Analysis/ScalarEvolution/nsw-offset.ll
index a919319bdcd5..8969a5ad4ceb 100644
--- a/test/Analysis/ScalarEvolution/nsw-offset.ll
+++ b/test/Analysis/ScalarEvolution/nsw-offset.ll
@@ -23,7 +23,7 @@ bb:                                               ; preds = %bb.nph, %bb1
   %1 = sext i32 %i.01 to i64                      ; <i64> [#uses=1]
 
 ; CHECK: %2 = getelementptr inbounds double* %d, i64 %1
-; CHECK: -->  {%d,+,16}<nuw><%bb>
+; CHECK: -->  {%d,+,16}<nsw><%bb>
   %2 = getelementptr inbounds double* %d, i64 %1  ; <double*> [#uses=1]
 
   %3 = load double* %2, align 8                   ; <double> [#uses=1]
@@ -37,7 +37,7 @@ bb:                                               ; preds = %bb.nph, %bb1
   %8 = sext i32 %7 to i64                         ; <i64> [#uses=1]
 
 ; CHECK: %9 = getelementptr inbounds double* %q, i64 %8
-; CHECK: {(8 + %q),+,16}<nuw><%bb>
+; CHECK: {(8 + %q),+,16}<nsw><%bb>
   %9 = getelementptr inbounds double* %q, i64 %8  ; <double*> [#uses=1]
 
 ; Artificially repeat the above three instructions, this time using
@@ -49,7 +49,7 @@ bb:                                               ; preds = %bb.nph, %bb1
   %t8 = sext i32 %t7 to i64                         ; <i64> [#uses=1]
 
 ; CHECK: %t9 = getelementptr inbounds double* %q, i64 %t8
-; CHECK: {(8 + %q),+,16}<nuw><%bb>
+; CHECK: {(8 + %q),+,16}<nsw><%bb>
   %t9 = getelementptr inbounds double* %q, i64 %t8  ; <double*> [#uses=1]
 
   %10 = load double* %9, align 8                  ; <double> [#uses=1]
diff --git a/test/Analysis/ScalarEvolution/nsw.ll b/test/Analysis/ScalarEvolution/nsw.ll
index 288b6facd94d..659cf4f8da97 100644
--- a/test/Analysis/ScalarEvolution/nsw.ll
+++ b/test/Analysis/ScalarEvolution/nsw.ll
@@ -92,10 +92,10 @@ for.body.i.i:                                     ; preds = %entry, %for.body.i.
 ; CHECK: {1,+,1}<nuw><nsw><%for.body.i.i>
   %ptrincdec.i.i = getelementptr inbounds i32* %begin, i64 %tmp
 ; CHECK: %ptrincdec.i.i =
-; CHECK: {(4 + %begin),+,4}<nuw><%for.body.i.i>
+; CHECK: {(4 + %begin),+,4}<nsw><%for.body.i.i>
   %__first.addr.08.i.i = getelementptr inbounds i32* %begin, i64 %indvar.i.i
 ; CHECK: %__first.addr.08.i.i
-; CHECK: {%begin,+,4}<nuw><%for.body.i.i>
+; CHECK: {%begin,+,4}<nsw><%for.body.i.i>
   store i32 0, i32* %__first.addr.08.i.i, align 4
   %cmp.i.i = icmp eq i32* %ptrincdec.i.i, %end
   br i1 %cmp.i.i, label %_ZSt4fillIPiiEvT_S1_RKT0_.exit, label %for.body.i.i
diff --git a/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll b/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll
index 7c9af6f5e590..0fe88bd0ed7e 100644
--- a/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll
+++ b/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll
@@ -26,7 +26,7 @@ bb2:                                              ; preds = %bb1, %entry
 ; CHECK: bb2
 ; CHECK: subs [[REG:r[0-9]+]], #1
 ; CHECK: cmp [[REG]], #0
-; CHECK: bgt
+; CHECK: ble
   %indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %entry ]
   %tries.0 = sub i32 2147483647, %indvar
   %tmp1 = icmp sgt i32 %tries.0, 0
diff --git a/test/CodeGen/ARM/fusedMAC.ll b/test/CodeGen/ARM/fusedMAC.ll
index a8b3999d2bf5..802d1b8b3932 100644
--- a/test/CodeGen/ARM/fusedMAC.ll
+++ b/test/CodeGen/ARM/fusedMAC.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mattr=+neon,+vfp4 | FileCheck %s
+; RUN: llc < %s -mtriple=armv7-eabi -mattr=+neon,+vfp4 | FileCheck %s
 ; Check generated fused MAC and MLS.
 
 define double @fusedMACTest1(double %d1, double %d2, double %d3) {
diff --git a/test/CodeGen/ARM/ldr_post.ll b/test/CodeGen/ARM/ldr_post.ll
index 97a48e1377e5..8ddf025dbf1b 100644
--- a/test/CodeGen/ARM/ldr_post.ll
+++ b/test/CodeGen/ARM/ldr_post.ll
@@ -1,7 +1,9 @@
-; RUN: llc < %s -march=arm | \
-; RUN:   grep {ldr.*\\\[.*\],} | count 1
+; RUN: llc < %s -march=arm | FileCheck %s
 
-define i32 @test(i32 %a, i32 %b, i32 %c) {
+; CHECK: test1:
+; CHECK: ldr {{.*, \[.*]}}, -r2
+; CHECK-NOT: ldr
+define i32 @test1(i32 %a, i32 %b, i32 %c) {
         %tmp1 = mul i32 %a, %b          ; <i32> [#uses=2]
         %tmp2 = inttoptr i32 %tmp1 to i32*              ; <i32*> [#uses=1]
         %tmp3 = load i32* %tmp2         ; <i32> [#uses=1]
@@ -10,3 +12,14 @@ define i32 @test(i32 %a, i32 %b, i32 %c) {
         ret i32 %tmp5
 }
 
+; CHECK: test2:
+; CHECK: ldr {{.*, \[.*\]}}, #-16
+; CHECK-NOT: ldr
+define i32 @test2(i32 %a, i32 %b) {
+        %tmp1 = mul i32 %a, %b          ; <i32> [#uses=2]
+        %tmp2 = inttoptr i32 %tmp1 to i32*              ; <i32*> [#uses=1]
+        %tmp3 = load i32* %tmp2         ; <i32> [#uses=1]
+        %tmp4 = sub i32 %tmp1, 16               ; <i32> [#uses=1]
+        %tmp5 = mul i32 %tmp4, %tmp3            ; <i32> [#uses=1]
+        ret i32 %tmp5
+}
diff --git a/test/CodeGen/ARM/ldr_pre.ll b/test/CodeGen/ARM/ldr_pre.ll
index 7c442845682e..e904e5fd2cdb 100644
--- a/test/CodeGen/ARM/ldr_pre.ll
+++ b/test/CodeGen/ARM/ldr_pre.ll
@@ -1,6 +1,8 @@
-; RUN: llc < %s -march=arm | \
-; RUN:   grep {ldr.*\\!} | count 2
+; RUN: llc < %s -march=arm | FileCheck %s
 
+; CHECK: test1:
+; CHECK: ldr {{.*!}}
+; CHECK-NOT: ldr
 define i32* @test1(i32* %X, i32* %dest) {
         %Y = getelementptr i32* %X, i32 4               ; <i32*> [#uses=2]
         %A = load i32* %Y               ; <i32> [#uses=1]
@@ -8,6 +10,9 @@ define i32* @test1(i32* %X, i32* %dest) {
         ret i32* %Y
 }
 
+; CHECK: test2:
+; CHECK: ldr {{.*!}}
+; CHECK-NOT: ldr
 define i32 @test2(i32 %a, i32 %b, i32 %c) {
         %tmp1 = sub i32 %a, %b          ; <i32> [#uses=2]
         %tmp2 = inttoptr i32 %tmp1 to i32*              ; <i32*> [#uses=1]
@@ -16,4 +21,3 @@ define i32 @test2(i32 %a, i32 %b, i32 %c) {
         %tmp5 = add i32 %tmp4, %tmp3            ; <i32> [#uses=1]
         ret i32 %tmp5
 }
-
diff --git a/test/CodeGen/ARM/tail-opts.ll b/test/CodeGen/ARM/tail-opts.ll
index 3dc77e2a8086..220b0f173739 100644
--- a/test/CodeGen/ARM/tail-opts.ll
+++ b/test/CodeGen/ARM/tail-opts.ll
@@ -16,11 +16,11 @@ declare i8* @choose(i8*, i8*)
 
 ; CHECK: tail_duplicate_me:
 ; CHECK:      qux
-; CHECK:      qux
 ; CHECK:      movw r{{[0-9]+}}, :lower16:_GHJK
 ; CHECK:      movt r{{[0-9]+}}, :upper16:_GHJK
 ; CHECK:      str r
 ; CHECK-NEXT: bx r
+; CHECK:      qux
 ; CHECK:      movw r{{[0-9]+}}, :lower16:_GHJK
 ; CHECK:      movt r{{[0-9]+}}, :upper16:_GHJK
 ; CHECK:      str r
diff --git a/test/CodeGen/ARM/vector-extend-narrow.ll b/test/CodeGen/ARM/vector-extend-narrow.ll
index 5e9239f25632..1ec36da38f77 100644
--- a/test/CodeGen/ARM/vector-extend-narrow.ll
+++ b/test/CodeGen/ARM/vector-extend-narrow.ll
@@ -44,3 +44,17 @@ define <4 x i8> @h(<4 x float> %v) {
   %1 = fptoui <4 x float> %v to <4 x i8>
   ret <4 x i8> %1
 }
+
+; CHECK: i:
+define <4 x i8> @i(<4 x i8>* %x) {
+  ; CHECK: vldr
+  ; CHECK: vmovl.s8
+  ; CHECK: vmovl.s16
+  ; CHECK: vrecpe
+  ; CHECK: vrecps
+  ; CHECK: vmul
+  ; CHECK: vmovn
+  %1 = load <4 x i8>* %x, align 4
+  %2 = sdiv <4 x i8> zeroinitializer, %1
+  ret <4 x i8> %2
+}
diff --git a/test/CodeGen/ARM/widen-vmovs.ll b/test/CodeGen/ARM/widen-vmovs.ll
index 2cffda317902..679e3f434733 100644
--- a/test/CodeGen/ARM/widen-vmovs.ll
+++ b/test/CodeGen/ARM/widen-vmovs.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -widen-vmovs -mcpu=cortex-a8 -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -widen-vmovs -mcpu=cortex-a8 -verify-machineinstrs -disable-code-place | FileCheck %s
 target triple = "thumbv7-apple-ios"
 
 ; The 1.0e+10 constant is loaded from the constant pool and kept in a register.
@@ -10,6 +10,7 @@ target triple = "thumbv7-apple-ios"
 ; CHECK: , [[DN]]
 ; CHECK: %for.body.i
 ; CHECK: vadd.f32 [[DL]], [[DL]], [[DN]]
+; CHECK: %rInnerproduct.exit
 ;
 ; This test is verifying:
 ; - The VMOVS widening is happening.
diff --git a/test/CodeGen/CellSPU/2009-01-01-BrCond.ll b/test/CodeGen/CellSPU/2009-01-01-BrCond.ll
index 58e3190454f8..35422311c574 100644
--- a/test/CodeGen/CellSPU/2009-01-01-BrCond.ll
+++ b/test/CodeGen/CellSPU/2009-01-01-BrCond.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=cellspu -o - | grep brnz
+; RUN: llc < %s -march=cellspu -o - | grep brz
 ; PR3274
 
 target datalayout = "E-p:32:32:128-i1:8:128-i8:8:128-i16:16:128-i32:32:128-i64:32:128-f32:32:128-f64:64:128-v64:64:64-v128:128:128-a0:0:128-s0:128:128"
diff --git a/test/CodeGen/Mips/analyzebranch.ll b/test/CodeGen/Mips/analyzebranch.ll
index 8f0bdf286c52..bc5bcc391ba3 100644
--- a/test/CodeGen/Mips/analyzebranch.ll
+++ b/test/CodeGen/Mips/analyzebranch.ll
@@ -26,9 +26,9 @@ return:                                           ; preds = %if.else, %if.end6
 
 define void @f1(float %f) nounwind {
 entry:
-; CHECK: bc1t $BB1_2
+; CHECK: bc1f $BB1_1
 ; CHECK: nop
-; CHECK: # BB#1:      
+; CHECK: # BB#2:
   %cmp = fcmp une float %f, 0.000000e+00
   br i1 %cmp, label %if.then, label %if.end
 
diff --git a/test/CodeGen/Mips/eh.ll b/test/CodeGen/Mips/eh.ll
index c3facdbc5556..2e2f9a451ed1 100644
--- a/test/CodeGen/Mips/eh.ll
+++ b/test/CodeGen/Mips/eh.ll
@@ -26,7 +26,7 @@ entry:
 lpad:                                             ; preds = %entry
 ; CHECK-EL:  # %lpad
 ; CHECK-EL:  lw  $gp
-; CHECK-EL:  beq $5
+; CHECK-EL:  bne $5
 
   %exn.val = landingpad { i8*, i32 } personality i32 (...)* @__gxx_personality_v0
            catch i8* bitcast (i8** @_ZTId to i8*)
diff --git a/test/CodeGen/Mips/fpbr.ll b/test/CodeGen/Mips/fpbr.ll
index 0a6478b0f8f0..a136557cc4a3 100644
--- a/test/CodeGen/Mips/fpbr.ll
+++ b/test/CodeGen/Mips/fpbr.ll
@@ -45,7 +45,7 @@ if.end:                                           ; preds = %if.else, %if.then
 define void @func2(float %f2, float %f3) nounwind {
 entry:
 ; CHECK: c.ole.s
-; CHECK: bc1f
+; CHECK: bc1t
   %cmp = fcmp ugt float %f2, %f3
   br i1 %cmp, label %if.else, label %if.then
 
@@ -102,7 +102,7 @@ if.end:                                           ; preds = %if.else, %if.then
 define void @func5(double %f2, double %f3) nounwind {
 entry:
 ; CHECK: c.ole.d
-; CHECK: bc1f
+; CHECK: bc1t
   %cmp = fcmp ugt double %f2, %f3
   br i1 %cmp, label %if.else, label %if.then
 
diff --git a/test/CodeGen/PowerPC/ppc-vaarg-agg.ll b/test/CodeGen/PowerPC/ppc-vaarg-agg.ll
new file mode 100644
index 000000000000..d5ea044599ee
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppc-vaarg-agg.ll
@@ -0,0 +1,46 @@
+target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"
+target triple = "powerpc-montavista-linux-gnuspe"
+; RUN: llc < %s -march=ppc32 | FileCheck %s
+
+%struct.__va_list_tag.0.9.18.23.32.41.48.55.62.67.72.77.82.87.90.93.96.101.105 = type { i8, i8, i16, i8*, i8* }
+
+define fastcc void @test1(%struct.__va_list_tag.0.9.18.23.32.41.48.55.62.67.72.77.82.87.90.93.96.101.105* %args) {
+entry:
+  br i1 undef, label %repeat, label %maxlen_reached
+
+repeat:                                           ; preds = %entry
+  switch i32 undef, label %sw.bb323 [
+    i32 77, label %sw.bb72
+    i32 111, label %sw.bb309
+    i32 80, label %sw.bb313
+    i32 117, label %sw.bb326
+    i32 88, label %sw.bb321
+  ]
+
+sw.bb72:                                          ; preds = %repeat
+  unreachable
+
+sw.bb309:                                         ; preds = %repeat
+  unreachable
+
+sw.bb313:                                         ; preds = %repeat
+  unreachable
+
+sw.bb321:                                         ; preds = %repeat
+  unreachable
+
+sw.bb323:                                         ; preds = %repeat
+  %0 = va_arg %struct.__va_list_tag.0.9.18.23.32.41.48.55.62.67.72.77.82.87.90.93.96.101.105* %args, i32
+  unreachable
+
+sw.bb326:                                         ; preds = %repeat
+  unreachable
+
+maxlen_reached:                                   ; preds = %entry
+  ret void
+}
+
+; If the SD nodes are not cleaup up correctly, then this can fail to compile
+; with an error like:  Cannot select: ch = setlt [ID=6]
+; CHECK: @test1
+
diff --git a/test/CodeGen/Thumb2/thumb2-branch.ll b/test/CodeGen/Thumb2/thumb2-branch.ll
index 27d8e8fb4086..f1c097c1892d 100644
--- a/test/CodeGen/Thumb2/thumb2-branch.ll
+++ b/test/CodeGen/Thumb2/thumb2-branch.ll
@@ -58,8 +58,8 @@ define i32 @f4(i32 %a, i32 %b, i32* %v) {
 entry:
 ; CHECK: f4:
 ; CHECK: blo LBB
-        %tmp = icmp ult i32 %a, %b              ; <i1> [#uses=1]
-        br i1 %tmp, label %return, label %cond_true
+        %tmp = icmp uge i32 %a, %b              ; <i1> [#uses=1]
+        br i1 %tmp, label %cond_true, label %return
 
 cond_true:              ; preds = %entry
         fence seq_cst
diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt2.ll b/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
index f577f79d6917..5aa9a735f250 100644
--- a/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
+++ b/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
@@ -29,13 +29,13 @@ declare i32 @bar(...)
 define fastcc i32 @CountTree(%struct.quad_struct* %tree) {
 entry:
 ; CHECK: CountTree:
-; CHECK: it eq
-; CHECK: cmpeq
-; CHECK: bne
-; CHECK: cmp
 ; CHECK: itt eq
 ; CHECK: moveq
 ; CHECK: popeq
+; CHECK: bne
+; CHECK: cmp
+; CHECK: it eq
+; CHECK: cmpeq
 	br label %tailrecurse
 
 tailrecurse:		; preds = %bb, %entry
@@ -83,7 +83,7 @@ define fastcc void @t2() nounwind {
 entry:
 ; CHECK: t2:
 ; CHECK: cmp r0, #0
-; CHECK: beq
+; CHECK: %growMapping.exit
 	br i1 undef, label %bb.i.i3, label %growMapping.exit
 
 bb.i.i3:		; preds = %entry
diff --git a/test/CodeGen/Thumb2/thumb2-jtb.ll b/test/CodeGen/Thumb2/thumb2-jtb.ll
index f5a56e5ace08..7e1655f6c252 100644
--- a/test/CodeGen/Thumb2/thumb2-jtb.ll
+++ b/test/CodeGen/Thumb2/thumb2-jtb.ll
@@ -3,11 +3,19 @@
 ; Do not use tbb / tbh if any destination is before the jumptable.
 ; rdar://7102917
 
-define i16 @main__getopt_internal_2E_exit_2E_ce(i32) nounwind {
+define i16 @main__getopt_internal_2E_exit_2E_ce(i32, i1 %b) nounwind {
+entry:
+  br i1 %b, label %codeRepl127.exitStub, label %newFuncRoot
+
 newFuncRoot:
 	br label %_getopt_internal.exit.ce
 
 codeRepl127.exitStub:		; preds = %_getopt_internal.exit.ce
+  ; Add an explicit edge back to before the jump table to ensure this block
+  ; is placed first.
+  br i1 %b, label %newFuncRoot, label %codeRepl127.exitStub.exit
+
+codeRepl127.exitStub.exit:
 	ret i16 0
 
 parse_options.exit.loopexit.exitStub:		; preds = %_getopt_internal.exit.ce
diff --git a/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll b/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll
index 88e8b4a4fd92..d583e5964dc2 100644
--- a/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll
+++ b/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll
@@ -6,8 +6,8 @@
 define i32 @test(i32 %argc, i8** %argv) nounwind {
 entry:
 ; CHECK: cmpl	$2
-; CHECK-NEXT: je
-; CHECK-NEXT: %entry
+; CHECK-NEXT: jne
+; CHECK-NEXT: %bb2
 
 	switch i32 %argc, label %UnifiedReturnBlock [
 		 i32 1, label %bb
diff --git a/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll b/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll
index a708224dd0d9..4160b203e36b 100644
--- a/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll
+++ b/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -enable-unsafe-fp-math -march=x86 | grep jnp
+; RUN: llc < %s -enable-unsafe-fp-math -march=x86 | grep jp
 ; rdar://5902801
 
 declare void @test2()
diff --git a/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll b/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll
index 1919d2ef34ae..12a8274fb56f 100644
--- a/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll
+++ b/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll
@@ -17,7 +17,7 @@ entry:
 
 ; CHECK: andl	$150
 ; CHECK-NEXT: testb
-; CHECK-NEXT: jg
+; CHECK-NEXT: jle
 
 entry.if.end_crit_edge:                           ; preds = %entry
   %tmp4.pre = load i32* @g_38                     ; <i32> [#uses=1]
diff --git a/test/CodeGen/X86/2010-11-18-SelectOfExtload.ll b/test/CodeGen/X86/2010-11-18-SelectOfExtload.ll
index a1074b6b8f3c..6d54c7e2982b 100644
--- a/test/CodeGen/X86/2010-11-18-SelectOfExtload.ll
+++ b/test/CodeGen/X86/2010-11-18-SelectOfExtload.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 | FileCheck %s
+; RUN: llc < %s -march=x86 -mattr=+cmov | FileCheck %s
 ; Both values were being zero extended.
 @u = external global i8
 @s = external global i8
diff --git a/test/CodeGen/X86/2011-09-14-valcoalesce.ll b/test/CodeGen/X86/2011-09-14-valcoalesce.ll
index 1068d1b704b0..a5ec614a943b 100644
--- a/test/CodeGen/X86/2011-09-14-valcoalesce.ll
+++ b/test/CodeGen/X86/2011-09-14-valcoalesce.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 | FileCheck %s
+; RUN: llc < %s -march=x86 -disable-code-place | FileCheck %s
 ;
 ; Test RegistersDefinedFromSameValue. We have multiple copies of the same vreg:
 ; while.body85.i:
diff --git a/test/CodeGen/X86/2012-04-26-sdglue.ll b/test/CodeGen/X86/2012-04-26-sdglue.ll
new file mode 100644
index 000000000000..9543587747a6
--- /dev/null
+++ b/test/CodeGen/X86/2012-04-26-sdglue.ll
@@ -0,0 +1,46 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx | FileCheck %s
+; rdar://11314175: SD Scheduler, BuildSchedUnits assert:
+;                  N->getNodeId() == -1 && "Node already inserted!
+
+; It's hard to test for the ISEL condition because CodeGen optimizes
+; away the bugpointed code. Just ensure the basics are still there.
+;CHECK: func:
+;CHECK: vmovups
+;CHECK: vpshufd
+;CHECK: vpshufd
+;CHECK: vmulps
+;CHECK: vmulps
+;CHECK: ret
+
+define void @func() nounwind ssp {
+  %tmp = load <4 x float>* null, align 1
+  %tmp14 = getelementptr <4 x float>* null, i32 2
+  %tmp15 = load <4 x float>* %tmp14, align 1
+  %tmp16 = shufflevector <4 x float> %tmp, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>
+  %tmp17 = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %tmp16, <4 x float> undef, i8 1)
+  %tmp18 = bitcast <4 x float> %tmp to <16 x i8>
+  %tmp19 = shufflevector <16 x i8> %tmp18, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
+  %tmp20 = bitcast <16 x i8> %tmp19 to <4 x float>
+  %tmp21 = bitcast <4 x float> %tmp15 to <16 x i8>
+  %tmp22 = shufflevector <16 x i8> undef, <16 x i8> %tmp21, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
+  %tmp23 = bitcast <16 x i8> %tmp22 to <4 x float>
+  %tmp24 = shufflevector <4 x float> %tmp20, <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 4, i32 4>
+  %tmp25 = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> %tmp24, <4 x float> %tmp23, i8 1)
+  %tmp26 = fmul <8 x float> %tmp17, undef
+  %tmp27 = fmul <8 x float> %tmp25, undef
+  %tmp28 = fadd <8 x float> %tmp26, %tmp27
+  %tmp29 = fadd <8 x float> %tmp28, undef
+  %tmp30 = shufflevector <8 x float> %tmp29, <8 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %tmp31 = fmul <4 x float> undef, %tmp30
+  %tmp32 = call <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float> zeroinitializer, <4 x float> %tmp31, i8 1)
+  %tmp33 = fadd <8 x float> undef, %tmp32
+  %tmp34 = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %tmp33, <8 x float> undef) nounwind
+  %tmp35 = fsub <8 x float> %tmp34, undef
+  %tmp36 = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> zeroinitializer, <8 x float> %tmp35) nounwind
+  store <8 x float> %tmp36, <8 x float>* undef, align 32
+  ret void
+}
+
+declare <8 x float> @llvm.x86.avx.vinsertf128.ps.256(<8 x float>, <4 x float>, i8) nounwind readnone
+
+declare <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float>, <8 x float>) nounwind readnone
diff --git a/test/CodeGen/X86/GC/cg-O0.ll b/test/CodeGen/X86/GC/cg-O0.ll
new file mode 100644
index 000000000000..b4929425e94a
--- /dev/null
+++ b/test/CodeGen/X86/GC/cg-O0.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -O0
+
+define i32 @main() {
+entry:
+  call void @f()
+  ret i32 0
+}
+
+define void @f() gc "ocaml" {
+entry:
+  %ptr.stackref = alloca i8*
+  %gcroot = bitcast i8** %ptr.stackref to i8**
+  call void @llvm.gcroot(i8** %gcroot, i8* null)
+  ret void
+}
+
+declare void @llvm.gcroot(i8**, i8*) nounwind
diff --git a/test/CodeGen/X86/atom-sched.ll b/test/CodeGen/X86/atom-sched.ll
index 2301dfc020ad..4dd9a9e3481d 100644
--- a/test/CodeGen/X86/atom-sched.ll
+++ b/test/CodeGen/X86/atom-sched.ll
@@ -1,5 +1,9 @@
+; XFAIL: *
 ; RUN: llc <%s -O2 -mcpu=atom -march=x86 -relocation-model=static | FileCheck -check-prefix=atom %s
 ; RUN: llc <%s -O2 -mcpu=core2 -march=x86 -relocation-model=static | FileCheck %s
+;
+; FIXME: Atom's scheduler is temporarily disabled.
+; XFAIL: *
 
 @a = common global i32 0, align 4
 @b = common global i32 0, align 4
diff --git a/test/CodeGen/X86/atomic_op.ll b/test/CodeGen/X86/atomic_op.ll
index 972dab292ae1..7c5abe2095cc 100644
--- a/test/CodeGen/X86/atomic_op.ll
+++ b/test/CodeGen/X86/atomic_op.ll
@@ -13,6 +13,7 @@ entry:
 	%xort = alloca i32		; <i32*> [#uses=2]
 	%old = alloca i32		; <i32*> [#uses=18]
 	%temp = alloca i32		; <i32*> [#uses=2]
+	%temp64 = alloca i64
 	store i32 %argc, i32* %argc.addr
 	store i8** %argv, i8*** %argv.addr
 	store i32 0, i32* %val1
@@ -106,6 +107,25 @@ entry:
         ; CHECK: cmpxchgl
   %17 = cmpxchg i32* %val2, i32 1976, i32 1 monotonic
 	store i32 %17, i32* %old
+        ; CHECK: movl	$1401, %[[R17mask:[a-z]*]]
+        ; CHECK: movl	[[R17atomic:.*]], %eax
+        ; CHECK: movl	%eax, %[[R17newval:[a-z]*]]
+        ; CHECK: andl	%[[R17mask]], %[[R17newval]]
+        ; CHECK: notl	%[[R17newval]]
+        ; CHECK: lock
+        ; CHECK: cmpxchgl	%[[R17newval]], [[R17atomic]]
+        ; CHECK: jne
+        ; CHECK: movl	%eax,
+  %18 = atomicrmw nand i32* %val2, i32 1401 monotonic
+  store i32 %18, i32* %old
+        ; CHECK: andl
+        ; CHECK: andl
+        ; CHECK: notl
+        ; CHECK: notl
+        ; CHECK: lock
+        ; CHECK: cmpxchg8b
+  %19 = atomicrmw nand i64* %temp64, i64 17361641481138401520 monotonic
+  store i64 %19, i64* %temp64
 	ret void
 }
 
diff --git a/test/CodeGen/X86/avx2-intrinsics-x86.ll b/test/CodeGen/X86/avx2-intrinsics-x86.ll
index 1fb41c02b9e9..3f27a0291b4f 100644
--- a/test/CodeGen/X86/avx2-intrinsics-x86.ll
+++ b/test/CodeGen/X86/avx2-intrinsics-x86.ll
@@ -800,22 +800,6 @@ define <8 x float> @test_x86_avx2_permps(<8 x float> %a0, <8 x float> %a1) {
 declare <8 x float> @llvm.x86.avx2.permps(<8 x float>, <8 x float>) nounwind readonly
 
 
-define <4 x i64> @test_x86_avx2_permq(<4 x i64> %a0) {
-  ; CHECK: vpermq
-  %res = call <4 x i64> @llvm.x86.avx2.permq(<4 x i64> %a0, i8 7) ; <<4 x i64>> [#uses=1]
-  ret <4 x i64> %res
-}
-declare <4 x i64> @llvm.x86.avx2.permq(<4 x i64>, i8) nounwind readonly
-
-
-define <4 x double> @test_x86_avx2_permpd(<4 x double> %a0) {
-  ; CHECK: vpermpd
-  %res = call <4 x double> @llvm.x86.avx2.permpd(<4 x double> %a0, i8 7) ; <<4 x double>> [#uses=1]
-  ret <4 x double> %res
-}
-declare <4 x double> @llvm.x86.avx2.permpd(<4 x double>, i8) nounwind readonly
-
-
 define <4 x i64> @test_x86_avx2_vperm2i128(<4 x i64> %a0, <4 x i64> %a1) {
   ; CHECK: vperm2i128
   %res = call <4 x i64> @llvm.x86.avx2.vperm2i128(<4 x i64> %a0, <4 x i64> %a1, i8 1) ; <<4 x i64>> [#uses=1]
diff --git a/test/CodeGen/X86/avx2-vperm.ll b/test/CodeGen/X86/avx2-vperm.ll
new file mode 100755
index 000000000000..d576d0e3741e
--- /dev/null
+++ b/test/CodeGen/X86/avx2-vperm.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
+
+define <8 x i32> @perm_cl_int_8x32(<8 x i32> %A) nounwind readnone {
+entry:
+; CHECK: perm_cl_int_8x32
+; CHECK: vpermd
+  %B = shufflevector <8 x i32> %A, <8 x i32> undef, <8 x i32> <i32 0, i32 7, i32 2, i32 1, i32 2, i32 7, i32 6, i32 0>
+  ret <8 x i32> %B
+}
+
+
+define <8 x float> @perm_cl_fp_8x32(<8 x float> %A) nounwind readnone {
+entry:
+; CHECK: perm_cl_fp_8x32
+; CHECK: vpermps
+  %B = shufflevector <8 x float> %A, <8 x float> undef, <8 x i32> <i32 undef, i32 7, i32 2, i32 undef, i32 4, i32 undef, i32 1, i32 6>
+  ret <8 x float> %B
+}
+
+define <4 x i64> @perm_cl_int_4x64(<4 x i64> %A) nounwind readnone {
+entry:
+; CHECK: perm_cl_int_4x64
+; CHECK: vpermq
+  %B = shufflevector <4 x i64> %A, <4 x i64> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 1>
+  ret <4 x i64> %B
+}
+
+define <4 x double> @perm_cl_fp_4x64(<4 x double> %A) nounwind readnone {
+entry:
+; CHECK: perm_cl_fp_4x64
+; CHECK: vpermpd
+  %B = shufflevector <4 x double> %A, <4 x double> undef, <4 x i32> <i32 0, i32 3, i32 2, i32 1>
+  ret <4 x double> %B
+}
diff --git a/test/CodeGen/X86/block-placement.ll b/test/CodeGen/X86/block-placement.ll
index 167d522d47d8..fc7b6383b8b0 100644
--- a/test/CodeGen/X86/block-placement.ll
+++ b/test/CodeGen/X86/block-placement.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=i686-linux -enable-block-placement < %s | FileCheck %s
+; RUN: llc -mtriple=i686-linux < %s | FileCheck %s
 
 declare void @error(i32 %i, i32 %a, i32 %b)
 
@@ -76,11 +76,11 @@ define i32 @test_loop_cold_blocks(i32 %i, i32* %a) {
 ; Check that we sink cold loop blocks after the hot loop body.
 ; CHECK: test_loop_cold_blocks:
 ; CHECK: %entry
+; CHECK: %unlikely1
+; CHECK: %unlikely2
 ; CHECK: %body1
 ; CHECK: %body2
 ; CHECK: %body3
-; CHECK: %unlikely1
-; CHECK: %unlikely2
 ; CHECK: %exit
 
 entry:
@@ -122,14 +122,14 @@ define i32 @test_loop_early_exits(i32 %i, i32* %a) {
 ; Check that we sink early exit blocks out of loop bodies.
 ; CHECK: test_loop_early_exits:
 ; CHECK: %entry
+; CHECK: %body1
 ; CHECK: %body2
 ; CHECK: %body3
 ; CHECK: %body4
-; CHECK: %body1
+; CHECK: %exit
 ; CHECK: %bail1
 ; CHECK: %bail2
 ; CHECK: %bail3
-; CHECK: %exit
 
 entry:
   br label %body1
@@ -199,6 +199,36 @@ exit:
   ret i32 %base
 }
 
+define i32 @test_no_loop_rotate(i32 %i, i32* %a) {
+; Check that we don't try to rotate a loop which is already laid out with
+; fallthrough opportunities into the top and out of the bottom.
+; CHECK: test_no_loop_rotate:
+; CHECK: %entry
+; CHECK: %body0
+; CHECK: %body1
+; CHECK: %exit
+
+entry:
+  br label %body0
+
+body0:
+  %iv = phi i32 [ 0, %entry ], [ %next, %body1 ]
+  %base = phi i32 [ 0, %entry ], [ %sum, %body1 ]
+  %arrayidx = getelementptr inbounds i32* %a, i32 %iv
+  %0 = load i32* %arrayidx
+  %sum = add nsw i32 %0, %base
+  %bailcond1 = icmp eq i32 %sum, 42
+  br i1 %bailcond1, label %exit, label %body1
+
+body1:
+  %next = add i32 %iv, 1
+  %exitcond = icmp eq i32 %next, %i
+  br i1 %exitcond, label %exit, label %body0
+
+exit:
+  ret i32 %base
+}
+
 define void @test_loop_rotate_reversed_blocks() {
 ; This test case (greatly reduced from an Olden bencmark) ensures that the loop
 ; rotate implementation doesn't assume that loops are laid out in a particular
@@ -348,7 +378,6 @@ define void @unnatural_cfg2() {
 ; CHECK: %entry
 ; CHECK: %loop.body1
 ; CHECK: %loop.body2
-; CHECK: %loop.header
 ; CHECK: %loop.body3
 ; CHECK: %loop.inner1.begin
 ; The end block is folded with %loop.body3...
@@ -356,6 +385,7 @@ define void @unnatural_cfg2() {
 ; CHECK: %loop.body4
 ; CHECK: %loop.inner2.begin
 ; The loop.inner2.end block is folded
+; CHECK: %loop.header
 ; CHECK: %bail
 
 entry:
@@ -928,3 +958,126 @@ entry:
 exit:
   ret void
 }
+
+define void @benchmark_heapsort(i32 %n, double* nocapture %ra) {
+; This test case comes from the heapsort benchmark, and exemplifies several
+; important aspects to block placement in the presence of loops:
+; 1) Loop rotation needs to *ensure* that the desired exiting edge can be
+;    a fallthrough.
+; 2) The exiting edge from the loop which is rotated to be laid out at the
+;    bottom of the loop needs to be exiting into the nearest enclosing loop (to
+;    which there is an exit). Otherwise, we force that enclosing loop into
+;    strange layouts that are siginificantly less efficient, often times maing
+;    it discontiguous.
+;
+; CHECK: @benchmark_heapsort
+; CHECK: %entry
+; First rotated loop top.
+; CHECK: .align
+; CHECK: %while.end
+; CHECK: %for.cond
+; CHECK: %if.then
+; CHECK: %if.else
+; CHECK: %if.end10
+; Second rotated loop top
+; CHECK: .align
+; CHECK: %if.then24
+; CHECK: %while.cond.outer
+; Third rotated loop top
+; CHECK: .align
+; CHECK: %while.cond
+; CHECK: %while.body
+; CHECK: %land.lhs.true
+; CHECK: %if.then19
+; CHECK: %if.then19
+; CHECK: %if.then8
+; CHECK: ret
+
+entry:
+  %shr = ashr i32 %n, 1
+  %add = add nsw i32 %shr, 1
+  %arrayidx3 = getelementptr inbounds double* %ra, i64 1
+  br label %for.cond
+
+for.cond:
+  %ir.0 = phi i32 [ %n, %entry ], [ %ir.1, %while.end ]
+  %l.0 = phi i32 [ %add, %entry ], [ %l.1, %while.end ]
+  %cmp = icmp sgt i32 %l.0, 1
+  br i1 %cmp, label %if.then, label %if.else
+
+if.then:
+  %dec = add nsw i32 %l.0, -1
+  %idxprom = sext i32 %dec to i64
+  %arrayidx = getelementptr inbounds double* %ra, i64 %idxprom
+  %0 = load double* %arrayidx, align 8
+  br label %if.end10
+
+if.else:
+  %idxprom1 = sext i32 %ir.0 to i64
+  %arrayidx2 = getelementptr inbounds double* %ra, i64 %idxprom1
+  %1 = load double* %arrayidx2, align 8
+  %2 = load double* %arrayidx3, align 8
+  store double %2, double* %arrayidx2, align 8
+  %dec6 = add nsw i32 %ir.0, -1
+  %cmp7 = icmp eq i32 %dec6, 1
+  br i1 %cmp7, label %if.then8, label %if.end10
+
+if.then8:
+  store double %1, double* %arrayidx3, align 8
+  ret void
+
+if.end10:
+  %ir.1 = phi i32 [ %ir.0, %if.then ], [ %dec6, %if.else ]
+  %l.1 = phi i32 [ %dec, %if.then ], [ %l.0, %if.else ]
+  %rra.0 = phi double [ %0, %if.then ], [ %1, %if.else ]
+  %add31 = add nsw i32 %ir.1, 1
+  br label %while.cond.outer
+
+while.cond.outer:
+  %j.0.ph.in = phi i32 [ %l.1, %if.end10 ], [ %j.1, %if.then24 ]
+  %j.0.ph = shl i32 %j.0.ph.in, 1
+  br label %while.cond
+
+while.cond:
+  %j.0 = phi i32 [ %add31, %if.end20 ], [ %j.0.ph, %while.cond.outer ]
+  %cmp11 = icmp sgt i32 %j.0, %ir.1
+  br i1 %cmp11, label %while.end, label %while.body
+
+while.body:
+  %cmp12 = icmp slt i32 %j.0, %ir.1
+  br i1 %cmp12, label %land.lhs.true, label %if.end20
+
+land.lhs.true:
+  %idxprom13 = sext i32 %j.0 to i64
+  %arrayidx14 = getelementptr inbounds double* %ra, i64 %idxprom13
+  %3 = load double* %arrayidx14, align 8
+  %add15 = add nsw i32 %j.0, 1
+  %idxprom16 = sext i32 %add15 to i64
+  %arrayidx17 = getelementptr inbounds double* %ra, i64 %idxprom16
+  %4 = load double* %arrayidx17, align 8
+  %cmp18 = fcmp olt double %3, %4
+  br i1 %cmp18, label %if.then19, label %if.end20
+
+if.then19:
+  br label %if.end20
+
+if.end20:
+  %j.1 = phi i32 [ %add15, %if.then19 ], [ %j.0, %land.lhs.true ], [ %j.0, %while.body ]
+  %idxprom21 = sext i32 %j.1 to i64
+  %arrayidx22 = getelementptr inbounds double* %ra, i64 %idxprom21
+  %5 = load double* %arrayidx22, align 8
+  %cmp23 = fcmp olt double %rra.0, %5
+  br i1 %cmp23, label %if.then24, label %while.cond
+
+if.then24:
+  %idxprom27 = sext i32 %j.0.ph.in to i64
+  %arrayidx28 = getelementptr inbounds double* %ra, i64 %idxprom27
+  store double %5, double* %arrayidx28, align 8
+  br label %while.cond.outer
+
+while.end:
+  %idxprom33 = sext i32 %j.0.ph.in to i64
+  %arrayidx34 = getelementptr inbounds double* %ra, i64 %idxprom33
+  store double %rra.0, double* %arrayidx34, align 8
+  br label %for.cond
+}
diff --git a/test/CodeGen/X86/br-fold.ll b/test/CodeGen/X86/br-fold.ll
index 8af3bd1bc229..2c3719493801 100644
--- a/test/CodeGen/X86/br-fold.ll
+++ b/test/CodeGen/X86/br-fold.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -march=x86-64 < %s | FileCheck %s
 
 ; CHECK: orq
-; CHECK-NEXT: jne
+; CHECK-NEXT: LBB0_1
 
 @_ZN11xercesc_2_513SchemaSymbols21fgURI_SCHEMAFORSCHEMAE = external constant [33 x i16], align 32 ; <[33 x i16]*> [#uses=1]
 @_ZN11xercesc_2_56XMLUni16fgNotationStringE = external constant [9 x i16], align 16 ; <[9 x i16]*> [#uses=1]
diff --git a/test/CodeGen/X86/call-push.ll b/test/CodeGen/X86/call-push.ll
index 8cca10c83073..e69f8c1ebf79 100644
--- a/test/CodeGen/X86/call-push.ll
+++ b/test/CodeGen/X86/call-push.ll
@@ -7,8 +7,8 @@ define i32 @decode_byte(%struct.decode_t* %decode) nounwind {
 ; CHECK: decode_byte:
 ; CHECK: pushl
 ; CHECK: popl
-; CHECK: popl
 ; CHECK: jmp
+; CHECK: popl
 entry:
         %tmp2 = getelementptr %struct.decode_t* %decode, i32 0, i32 4           ; <i16*> [#uses=1]
         %tmp23 = bitcast i16* %tmp2 to i32*             ; <i32*> [#uses=1]
diff --git a/test/CodeGen/Generic/dbg-declare.ll b/test/CodeGen/X86/dbg-declare.ll
index 01f7d6d47916..5d4cedc5c4e3 100644
--- a/test/CodeGen/Generic/dbg-declare.ll
+++ b/test/CodeGen/X86/dbg-declare.ll
@@ -1,7 +1,5 @@
-; RUN: llc < %s -O0
+; RUN: llc < %s -O0 -mtriple x86_64-apple-darwin
 ; <rdar://problem/11134152>
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
-target triple = "x86_64-apple-macosx10.8.0"
 
 define i32 @foo(i32* %x) nounwind uwtable ssp {
 entry:
diff --git a/test/CodeGen/X86/licm-dominance.ll b/test/CodeGen/X86/licm-dominance.ll
index 8a0958db0ef5..019f8a32b6c0 100644
--- a/test/CodeGen/X86/licm-dominance.ll
+++ b/test/CodeGen/X86/licm-dominance.ll
@@ -1,7 +1,7 @@
-; RUN: llc -asm-verbose=false < %s | FileCheck %s
+; RUN: llc -asm-verbose=true < %s | FileCheck %s
 
 ; MachineLICM should check dominance before hoisting instructions.
-; CHECK:	jne	LBB0_3
+; CHECK: ## in Loop:
 ; CHECK-NEXT:	xorb	%al, %al
 ; CHECK-NEXT:	testb	%al, %al
 
diff --git a/test/CodeGen/X86/loop-blocks.ll b/test/CodeGen/X86/loop-blocks.ll
index faba63007127..d14102fe245b 100644
--- a/test/CodeGen/X86/loop-blocks.ll
+++ b/test/CodeGen/X86/loop-blocks.ll
@@ -41,6 +41,7 @@ done:
 ; CHECK-NEXT:   align
 ; CHECK-NEXT: .LBB1_4:
 ; CHECK-NEXT:   callq bar99
+; CHECK-NEXT:   align
 ; CHECK-NEXT: .LBB1_1:
 ; CHECK-NEXT:   callq body
 
@@ -75,19 +76,21 @@ exit:
 ; CHECK: yet_more_involved:
 ;      CHECK:   jmp .LBB2_1
 ; CHECK-NEXT:   align
-; CHECK-NEXT: .LBB2_4:
-; CHECK-NEXT:   callq bar99
+; CHECK-NEXT: .LBB2_5:
+; CHECK-NEXT:   callq block_a_true_func
+; CHECK-NEXT:   callq block_a_merge_func
+; CHECK-NEXT:   align
+; CHECK-NEXT: .LBB2_1:
+; CHECK-NEXT:   callq body
+;
+; LBB2_4
+;      CHECK:   callq bar99
 ; CHECK-NEXT:   callq get
 ; CHECK-NEXT:   cmpl $2999, %eax
 ; CHECK-NEXT:   jle .LBB2_5
 ; CHECK-NEXT:   callq block_a_false_func
 ; CHECK-NEXT:   callq block_a_merge_func
 ; CHECK-NEXT:   jmp .LBB2_1
-; CHECK-NEXT: .LBB2_5:
-; CHECK-NEXT:   callq block_a_true_func
-; CHECK-NEXT:   callq block_a_merge_func
-; CHECK-NEXT: .LBB2_1:
-; CHECK-NEXT:   callq body
 
 define void @yet_more_involved() nounwind {
 entry:
@@ -136,17 +139,22 @@ exit:
 ; CHECK-NEXT:   align
 ; CHECK-NEXT: .LBB3_7:
 ; CHECK-NEXT:   callq   bar100
-; CHECK-NEXT:   jmp     .LBB3_1
-; CHECK-NEXT: .LBB3_8:
+; CHECK-NEXT:   align
+; CHECK-NEXT: .LBB3_1:
+; CHECK-NEXT:   callq   loop_header
+;      CHECK:   jl .LBB3_7
+;      CHECK:   jge .LBB3_3
 ; CHECK-NEXT:   callq   bar101
 ; CHECK-NEXT:   jmp     .LBB3_1
-; CHECK-NEXT: .LBB3_9:
+; CHECK-NEXT: .LBB3_3:
+;      CHECK:   jge .LBB3_4
 ; CHECK-NEXT:   callq   bar102
 ; CHECK-NEXT:   jmp     .LBB3_1
-; CHECK-NEXT: .LBB3_5:
+; CHECK-NEXT: .LBB3_4:
+;      CHECK:   jl .LBB3_6
 ; CHECK-NEXT:   callq   loop_latch
-; CHECK-NEXT: .LBB3_1:
-; CHECK-NEXT:   callq   loop_header
+; CHECK-NEXT:   jmp     .LBB3_1
+; CHECK-NEXT: .LBB3_6:
 
 define void @cfg_islands() nounwind {
 entry:
diff --git a/test/CodeGen/X86/machine-cp.ll b/test/CodeGen/X86/machine-cp.ll
index 54fa01c38fde..8e97b991d076 100644
--- a/test/CodeGen/X86/machine-cp.ll
+++ b/test/CodeGen/X86/machine-cp.ll
@@ -5,11 +5,11 @@
 define i32 @t1(i32 %a, i32 %b) nounwind  {
 entry:
 ; CHECK: t1:
-; CHECK: jne
+; CHECK: je [[LABEL:.*BB.*]]
   %cmp1 = icmp eq i32 %b, 0
   br i1 %cmp1, label %while.end, label %while.body
 
-; CHECK: BB
+; CHECK: [[LABEL]]:
 ; CHECK-NOT: mov
 ; CHECK: ret
 
diff --git a/test/CodeGen/X86/postra-licm.ll b/test/CodeGen/X86/postra-licm.ll
index 48c48aebe5be..01d6cbef1ee5 100644
--- a/test/CodeGen/X86/postra-licm.ll
+++ b/test/CodeGen/X86/postra-licm.ll
@@ -70,8 +70,8 @@ bb26.preheader:                                   ; preds = %imix_test.exit
 bb23:                                             ; preds = %imix_test.exit
   unreachable
 ; Verify that there are no loads inside the loop.
-; X86-32: %bb26.preheader
 ; X86-32: .align 4
+; X86-32: %bb28
 ; X86-32-NOT: (%esp),
 ; X86-32-NOT: (%ebp),
 ; X86-32: jmp
diff --git a/test/CodeGen/X86/pr2659.ll b/test/CodeGen/X86/pr2659.ll
index 5dab5c9f5b8c..8003588a2e84 100644
--- a/test/CodeGen/X86/pr2659.ll
+++ b/test/CodeGen/X86/pr2659.ll
@@ -18,11 +18,12 @@ forcond.preheader:              ; preds = %entry
 ; CHECK-NOT: xorl
 ; CHECK-NOT: movl
 ; CHECK-NOT: LBB
-; CHECK: jne
+; CHECK: je
 
 ; There should be no moves required in the for loop body.
 ; CHECK: %forbody
 ; CHECK-NOT: mov
+; CHECK: jbe
 
 ifthen:         ; preds = %entry
   ret i32 0
diff --git a/test/CodeGen/X86/select.ll b/test/CodeGen/X86/select.ll
index ce04e07854a4..f465a4ffc584 100644
--- a/test/CodeGen/X86/select.ll
+++ b/test/CodeGen/X86/select.ll
@@ -75,9 +75,9 @@ define void @test6(i32 %C, <4 x float>* %A, <4 x float>* %B) nounwind {
 ; Verify that the fmul gets sunk into the one part of the diamond where it is
 ; needed.
 ; CHECK: test6:
-; CHECK: jne
-; CHECK: mulps
+; CHECK: je
 ; CHECK: ret
+; CHECK: mulps
 ; CHECK: ret
 }
 
diff --git a/test/CodeGen/X86/sibcall.ll b/test/CodeGen/X86/sibcall.ll
index a9a5420cbcd8..2af355905dc3 100644
--- a/test/CodeGen/X86/sibcall.ll
+++ b/test/CodeGen/X86/sibcall.ll
@@ -147,7 +147,7 @@ define i32 @t11(i32 %x, i32 %y, i32 %z.0, i32 %z.1, i32 %z.2) nounwind ssp {
 
 ; 32: t11:
 ; 32-NOT: subl ${{[0-9]+}}, %esp
-; 32: jne
+; 32: je
 ; 32-NOT: movl
 ; 32-NOT: addl ${{[0-9]+}}, %esp
 ; 32: jmp {{_?}}foo5
diff --git a/test/CodeGen/X86/sink-hoist.ll b/test/CodeGen/X86/sink-hoist.ll
index e13a81719ea7..7957eb849673 100644
--- a/test/CodeGen/X86/sink-hoist.ll
+++ b/test/CodeGen/X86/sink-hoist.ll
@@ -7,8 +7,9 @@
 
 ; CHECK: foo:
 ; CHECK-NEXT: testb $1, %dil
-; CHECK-NEXT: je
+; CHECK-NEXT: jne
 ; CHECK-NEXT: divsd
+; CHECK-NEXT: movaps
 ; CHECK-NEXT: ret
 ; CHECK:      divsd
 
@@ -25,10 +26,10 @@ define double @foo(double %x, double %y, i1 %c) nounwind {
 
 ; CHECK: split:
 ; CHECK-NEXT: testb $1, %dil
-; CHECK-NEXT: je
-; CHECK-NEXT: divsd
+; CHECK-NEXT: jne
+; CHECK-NEXT: movaps
 ; CHECK-NEXT: ret
-; CHECK:      movaps
+; CHECK:      divsd
 ; CHECK-NEXT: ret
 define double @split(double %x, double %y, i1 %c) nounwind {
   %a = fdiv double %x, 3.2
diff --git a/test/CodeGen/X86/smul-with-overflow.ll b/test/CodeGen/X86/smul-with-overflow.ll
index 7c2e247c8740..7ac3840482a2 100644
--- a/test/CodeGen/X86/smul-with-overflow.ll
+++ b/test/CodeGen/X86/smul-with-overflow.ll
@@ -19,7 +19,7 @@ overflow:
   ret i1 false
 ; CHECK: test1:
 ; CHECK: imull
-; CHECK-NEXT: jo
+; CHECK-NEXT: jno
 }
 
 define i1 @test2(i32 %v1, i32 %v2) nounwind {
diff --git a/test/CodeGen/X86/sse41-blend.ll b/test/CodeGen/X86/sse41-blend.ll
index 78604a0e9634..1a1017d2c176 100644
--- a/test/CodeGen/X86/sse41-blend.ll
+++ b/test/CodeGen/X86/sse41-blend.ll
@@ -80,3 +80,11 @@ define <2 x double> @B(<2 x double> %x, <2 x double> %y) {
   ret <2 x double> %min
 }
 
+; CHECK: float_crash
+define void @float_crash() nounwind {
+entry:
+  %merge205vector_func.i = select <4 x i1> undef, <4 x double> undef, <4 x double> undef
+  %extract214vector_func.i = extractelement <4 x double> %merge205vector_func.i, i32 0
+  store double %extract214vector_func.i, double addrspace(1)* undef, align 8
+  ret void
+}
diff --git a/test/CodeGen/X86/sub-with-overflow.ll b/test/CodeGen/X86/sub-with-overflow.ll
index 749b5db480f5..db8313cecdce 100644
--- a/test/CodeGen/X86/sub-with-overflow.ll
+++ b/test/CodeGen/X86/sub-with-overflow.ll
@@ -20,7 +20,7 @@ overflow:
 
 ; CHECK: func1:
 ; CHECK: subl 20(%esp)
-; CHECK-NEXT: jo
+; CHECK-NEXT: jno
 }
 
 define i1 @func2(i32 %v1, i32 %v2) nounwind {
@@ -40,7 +40,7 @@ carry:
 
 ; CHECK: func2:
 ; CHECK: subl 20(%esp)
-; CHECK-NEXT: jb
+; CHECK-NEXT: jae
 }
 
 declare i32 @printf(i8*, ...) nounwind
diff --git a/test/CodeGen/X86/switch-bt.ll b/test/CodeGen/X86/switch-bt.ll
index 8e3934221435..58a5c0338547 100644
--- a/test/CodeGen/X86/switch-bt.ll
+++ b/test/CodeGen/X86/switch-bt.ll
@@ -5,11 +5,11 @@
 
 ;      CHECK: movabsq $2305843009482129440, %r
 ; CHECK-NEXT: btq %rax, %r
-; CHECK-NEXT: jb
-; CHECK-NEXT: movl  $671088640, %e
+; CHECK-NEXT: jae
+;     CHECK: movl  $671088640, %e
 ; CHECK-NEXT: btq %rax, %r
-; CHECK-NEXT: jb
-; CHECK-NEXT: testq %rax, %r
+; CHECK-NEXT: jae
+;      CHECK: testq %rax, %r
 ; CHECK-NEXT: j
 
 define void @test(i8* %l) nounwind {
@@ -60,7 +60,7 @@ define void @test2(i32 %x) nounwind ssp {
 ; CHECK-NEXT: movl $91
 ; CHECK-NOT: movl
 ; CHECK-NEXT: btl
-; CHECK-NEXT: jb
+; CHECK-NEXT: jae
 entry:
   switch i32 %x, label %if.end [
     i32 6, label %if.then
@@ -85,7 +85,7 @@ define void @test3(i32 %x) nounwind {
 ; CHECK: cmpl $5
 ; CHECK: ja
 ; CHECK: cmpl $4
-; CHECK: jne
+; CHECK: je
   switch i32 %x, label %if.end [
     i32 0, label %if.then
     i32 1, label %if.then
diff --git a/test/CodeGen/X86/tail-opts.ll b/test/CodeGen/X86/tail-opts.ll
index f1b9f20082f5..6e20af5866e4 100644
--- a/test/CodeGen/X86/tail-opts.ll
+++ b/test/CodeGen/X86/tail-opts.ll
@@ -113,15 +113,16 @@ altret:
 ; CHECK-NEXT:   jbe .LBB2_3
 ; CHECK-NEXT:   ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}}
 ; CHECK-NEXT:   ja .LBB2_4
-; CHECK-NEXT: .LBB2_2:
-; CHECK-NEXT:   movb $1, %al
-; CHECK-NEXT:   ret
+; CHECK-NEXT:   jmp .LBB2_2
 ; CHECK-NEXT: .LBB2_3:
 ; CHECK-NEXT:   ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}}
 ; CHECK-NEXT:   jbe .LBB2_2
 ; CHECK-NEXT: .LBB2_4:
 ; CHECK-NEXT:   xorb %al, %al
 ; CHECK-NEXT:   ret
+; CHECK-NEXT: .LBB2_2:
+; CHECK-NEXT:   movb $1, %al
+; CHECK-NEXT:   ret
 
 define i1 @dont_merge_oddly(float* %result) nounwind {
 entry:
@@ -336,10 +337,10 @@ return:
 
 ; CHECK: two:
 ; CHECK-NOT: XYZ
+; CHECK: ret
 ; CHECK: movl $0, XYZ(%rip)
 ; CHECK: movl $1, XYZ(%rip)
 ; CHECK-NOT: XYZ
-; CHECK: ret
 
 define void @two() nounwind optsize {
 entry:
diff --git a/test/CodeGen/X86/uint64-to-float.ll b/test/CodeGen/X86/uint64-to-float.ll
index e853e7717f12..ca764e7568f3 100644
--- a/test/CodeGen/X86/uint64-to-float.ll
+++ b/test/CodeGen/X86/uint64-to-float.ll
@@ -7,13 +7,14 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "x86_64-apple-darwin10.0.0"
 
 ; CHECK: testq %rdi, %rdi
-; CHECK-NEXT: jns LBB0_2
+; CHECK-NEXT: js LBB0_1
+; CHECK: cvtsi2ss
+; CHECK-NEXT: ret
+; CHECK: LBB0_1
 ; CHECK: shrq
 ; CHECK-NEXT: andq
 ; CHECK-NEXT: orq
 ; CHECK-NEXT: cvtsi2ss
-; CHECK: LBB0_2
-; CHECK-NEXT: cvtsi2ss
 define float @test(i64 %a) {
 entry:
   %b = uitofp i64 %a to float
diff --git a/test/CodeGen/X86/vec_shuffle-20.ll b/test/CodeGen/X86/vec_shuffle-20.ll
index b6b8ba6f846a..976cd1835b40 100644
--- a/test/CodeGen/X86/vec_shuffle-20.ll
+++ b/test/CodeGen/X86/vec_shuffle-20.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -o /dev/null -march=x86 -mcpu=corei7 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 2
+; RUN: llc < %s -o /dev/null -march=x86 -mcpu=corei7 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 3
 
 define <4 x float> @func(<4 x float> %fp0, <4 x float> %fp1) nounwind  {
 entry:
diff --git a/test/CodeGen/X86/xor-icmp.ll b/test/CodeGen/X86/xor-icmp.ll
index 34875ed89957..fd1b0064046a 100644
--- a/test/CodeGen/X86/xor-icmp.ll
+++ b/test/CodeGen/X86/xor-icmp.ll
@@ -9,13 +9,13 @@ entry:
 ; X32-NOT: andb
 ; X32-NOT: shrb
 ; X32:     testb $64
-; X32:     jne
+; X32:     je
 
 ; X64:     t:
 ; X64-NOT: setne
 ; X64:     xorl
 ; X64:     testb $64
-; X64:     jne
+; X64:     je
   %0 = and i32 %a, 16384
   %1 = icmp ne i32 %0, 0
   %2 = and i32 %b, 16384
@@ -43,7 +43,7 @@ define i32 @t2(i32 %x, i32 %y) nounwind ssp {
 ; X32: cmpl
 ; X32: sete
 ; X32-NOT: xor
-; X32: jne
+; X32: je
 
 ; X64: t2:
 ; X64: testl
@@ -51,7 +51,7 @@ define i32 @t2(i32 %x, i32 %y) nounwind ssp {
 ; X64: testl
 ; X64: sete
 ; X64-NOT: xor
-; X64: jne
+; X64: je
 entry:
   %0 = icmp eq i32 %x, 0                          ; <i1> [#uses=1]
   %1 = icmp eq i32 %y, 0                          ; <i1> [#uses=1]
diff --git a/test/CodeGen/XCore/ashr.ll b/test/CodeGen/XCore/ashr.ll
index 4514fdb8bf3b..03b6b1f16950 100644
--- a/test/CodeGen/XCore/ashr.ll
+++ b/test/CodeGen/XCore/ashr.ll
@@ -30,7 +30,7 @@ not_less:
 }
 ; CHECK: f1:
 ; CHECK-NEXT: ashr r0, r0, 32
-; CHECK-NEXT: bf r0
+; CHECK-NEXT: bt r0
 
 define i32 @f2(i32 %a) {
         %1 = icmp sge i32 %a, 0
@@ -51,9 +51,9 @@ define i32 @f3(i32 %a) {
 }
 ; CHECK: f3:
 ; CHECK-NEXT: ashr r0, r0, 32
-; CHECK-NEXT: bf r0
-; CHECK-NEXT: ldc r0, 10
-; CHECK: ldc r0, 17
+; CHECK-NEXT: bt r0
+; CHECK-NEXT: ldc r0, 17
+; CHECK: ldc r0, 10
 
 define i32 @f4(i32 %a) {
         %1 = icmp sge i32 %a, 0
@@ -62,9 +62,9 @@ define i32 @f4(i32 %a) {
 }
 ; CHECK: f4:
 ; CHECK-NEXT: ashr r0, r0, 32
-; CHECK-NEXT: bf r0
-; CHECK-NEXT: ldc r0, 17
-; CHECK: ldc r0, 10
+; CHECK-NEXT: bt r0
+; CHECK-NEXT: ldc r0, 10
+; CHECK: ldc r0, 17
 
 define i32 @f5(i32 %a) {
         %1 = icmp sge i32 %a, 0
diff --git a/test/MC/ARM/neon-add-encoding.s b/test/MC/ARM/neon-add-encoding.s
index 1fdfa4c13dfb..50c8f85449ff 100644
--- a/test/MC/ARM/neon-add-encoding.s
+++ b/test/MC/ARM/neon-add-encoding.s
@@ -64,31 +64,86 @@
 	vhadd.u16	q8, q8, q9
 @ CHECK: vhadd.u32	q8, q8, q9      @ encoding: [0xe2,0x00,0x60,0xf3]
 	vhadd.u32	q8, q8, q9
-	
-@ CHECK: vrhadd.s8	d16, d16, d17   @ encoding: [0xa1,0x01,0x40,0xf2]
+
+
+	vhadd.s8	d11, d24
+	vhadd.s16	d12, d23
+	vhadd.s32	d13, d22
+	vhadd.u8	d14, d21
+	vhadd.u16	d15, d20
+	vhadd.u32	d16, d19
+	vhadd.s8	q1, q12
+	vhadd.s16	q2, q11
+	vhadd.s32	q3, q10
+	vhadd.u8	q4, q9
+	vhadd.u16	q5, q8
+	vhadd.u32	q6, q7
+
+@ CHECK: vhadd.s8	d11, d11, d24   @ encoding: [0x28,0xb0,0x0b,0xf2]
+@ CHECK: vhadd.s16	d12, d12, d23   @ encoding: [0x27,0xc0,0x1c,0xf2]
+@ CHECK: vhadd.s32	d13, d13, d22   @ encoding: [0x26,0xd0,0x2d,0xf2]
+@ CHECK: vhadd.u8	d14, d14, d21   @ encoding: [0x25,0xe0,0x0e,0xf3]
+@ CHECK: vhadd.u16	d15, d15, d20   @ encoding: [0x24,0xf0,0x1f,0xf3]
+@ CHECK: vhadd.u32	d16, d16, d19   @ encoding: [0xa3,0x00,0x60,0xf3]
+@ CHECK: vhadd.s8	q1, q1, q12     @ encoding: [0x68,0x20,0x02,0xf2]
+@ CHECK: vhadd.s16	q2, q2, q11     @ encoding: [0x66,0x40,0x14,0xf2]
+@ CHECK: vhadd.s32	q3, q3, q10     @ encoding: [0x64,0x60,0x26,0xf2]
+@ CHECK: vhadd.u8	q4, q4, q9      @ encoding: [0x62,0x80,0x08,0xf3]
+@ CHECK: vhadd.u16	q5, q5, q8      @ encoding: [0x60,0xa0,0x1a,0xf3]
+@ CHECK: vhadd.u32	q6, q6, q7      @ encoding: [0x4e,0xc0,0x2c,0xf3]
+
 	vrhadd.s8	d16, d16, d17
-@ CHECK: vrhadd.s16	d16, d16, d17   @ encoding: [0xa1,0x01,0x50,0xf2]
 	vrhadd.s16	d16, d16, d17
-@ CHECK: vrhadd.s32	d16, d16, d17   @ encoding: [0xa1,0x01,0x60,0xf2]
 	vrhadd.s32	d16, d16, d17
-@ CHECK: vrhadd.u8	d16, d16, d17   @ encoding: [0xa1,0x01,0x40,0xf3]
 	vrhadd.u8	d16, d16, d17
-@ CHECK: vrhadd.u16	d16, d16, d17   @ encoding: [0xa1,0x01,0x50,0xf3]
 	vrhadd.u16	d16, d16, d17
-@ CHECK: vrhadd.u32	d16, d16, d17   @ encoding: [0xa1,0x01,0x60,0xf3]
 	vrhadd.u32	d16, d16, d17
-@ CHECK: vrhadd.s8	q8, q8, q9      @ encoding: [0xe2,0x01,0x40,0xf2]
 	vrhadd.s8	q8, q8, q9
-@ CHECK: vrhadd.s16	q8, q8, q9      @ encoding: [0xe2,0x01,0x50,0xf2]
 	vrhadd.s16	q8, q8, q9
-@ CHECK: vrhadd.s32	q8, q8, q9      @ encoding: [0xe2,0x01,0x60,0xf2]
 	vrhadd.s32	q8, q8, q9
-@ CHECK: vrhadd.u8	q8, q8, q9      @ encoding: [0xe2,0x01,0x40,0xf3]
 	vrhadd.u8	q8, q8, q9
-@ CHECK: vrhadd.u16	q8, q8, q9      @ encoding: [0xe2,0x01,0x50,0xf3]
 	vrhadd.u16	q8, q8, q9
-@ CHECK: vrhadd.u32	q8, q8, q9      @ encoding: [0xe2,0x01,0x60,0xf3]
 	vrhadd.u32	q8, q8, q9
+        @ Two-operand forms.
+	vrhadd.s8	d16, d17
+	vrhadd.s16	d16, d17
+	vrhadd.s32	d16, d17
+	vrhadd.u8	d16, d17
+	vrhadd.u16	d16, d17
+	vrhadd.u32	d16, d17
+	vrhadd.s8	q8, q9
+	vrhadd.s16	q8, q9
+	vrhadd.s32	q8, q9
+	vrhadd.u8	q8, q9
+	vrhadd.u16	q8, q9
+	vrhadd.u32	q8, q9
+
+@ CHECK: vrhadd.s8	d16, d16, d17   @ encoding: [0xa1,0x01,0x40,0xf2]
+@ CHECK: vrhadd.s16	d16, d16, d17   @ encoding: [0xa1,0x01,0x50,0xf2]
+@ CHECK: vrhadd.s32	d16, d16, d17   @ encoding: [0xa1,0x01,0x60,0xf2]
+@ CHECK: vrhadd.u8	d16, d16, d17   @ encoding: [0xa1,0x01,0x40,0xf3]
+@ CHECK: vrhadd.u16	d16, d16, d17   @ encoding: [0xa1,0x01,0x50,0xf3]
+@ CHECK: vrhadd.u32	d16, d16, d17   @ encoding: [0xa1,0x01,0x60,0xf3]
+@ CHECK: vrhadd.s8	q8, q8, q9      @ encoding: [0xe2,0x01,0x40,0xf2]
+@ CHECK: vrhadd.s16	q8, q8, q9      @ encoding: [0xe2,0x01,0x50,0xf2]
+@ CHECK: vrhadd.s32	q8, q8, q9      @ encoding: [0xe2,0x01,0x60,0xf2]
+@ CHECK: vrhadd.u8	q8, q8, q9      @ encoding: [0xe2,0x01,0x40,0xf3]
+@ CHECK: vrhadd.u16	q8, q8, q9      @ encoding: [0xe2,0x01,0x50,0xf3]
+@ CHECK: vrhadd.u32	q8, q8, q9      @ encoding: [0xe2,0x01,0x60,0xf3]
+
+@ CHECK: vrhadd.s8	d16, d16, d17   @ encoding: [0xa1,0x01,0x40,0xf2]
+@ CHECK: vrhadd.s16	d16, d16, d17   @ encoding: [0xa1,0x01,0x50,0xf2]
+@ CHECK: vrhadd.s32	d16, d16, d17   @ encoding: [0xa1,0x01,0x60,0xf2]
+@ CHECK: vrhadd.u8	d16, d16, d17   @ encoding: [0xa1,0x01,0x40,0xf3]
+@ CHECK: vrhadd.u16	d16, d16, d17   @ encoding: [0xa1,0x01,0x50,0xf3]
+@ CHECK: vrhadd.u32	d16, d16, d17   @ encoding: [0xa1,0x01,0x60,0xf3]
+@ CHECK: vrhadd.s8	q8, q8, q9      @ encoding: [0xe2,0x01,0x40,0xf2]
+@ CHECK: vrhadd.s16	q8, q8, q9      @ encoding: [0xe2,0x01,0x50,0xf2]
+@ CHECK: vrhadd.s32	q8, q8, q9      @ encoding: [0xe2,0x01,0x60,0xf2]
+@ CHECK: vrhadd.u8	q8, q8, q9      @ encoding: [0xe2,0x01,0x40,0xf3]
+@ CHECK: vrhadd.u16	q8, q8, q9      @ encoding: [0xe2,0x01,0x50,0xf3]
+@ CHECK: vrhadd.u32	q8, q8, q9      @ encoding: [0xe2,0x01,0x60,0xf3]
+
 
 	vqadd.s8	d16, d16, d17
 	vqadd.s16	d16, d16, d17
diff --git a/test/MC/ARM/neon-shift-encoding.s b/test/MC/ARM/neon-shift-encoding.s
index 54ed173c92ee..3c97f8b61fb3 100644
--- a/test/MC/ARM/neon-shift-encoding.s
+++ b/test/MC/ARM/neon-shift-encoding.s
@@ -250,113 +250,124 @@ _foo:
 @ CHECK: vsli.64 q7, q7, #63            @ encoding: [0xde,0xe5,0xbf,0xf3]
 
 
-@ CHECK: vshll.s8	q8, d16, #7  @ encoding: [0x30,0x0a,0xcf,0xf2]
 	vshll.s8	q8, d16, #7
-@ CHECK: vshll.s16	q8, d16, #15  @ encoding: [0x30,0x0a,0xdf,0xf2]
 	vshll.s16	q8, d16, #15
-@ CHECK: vshll.s32	q8, d16, #31  @ encoding: [0x30,0x0a,0xff,0xf2]
 	vshll.s32	q8, d16, #31
-@ CHECK: vshll.u8	q8, d16, #7  @ encoding: [0x30,0x0a,0xcf,0xf3]
 	vshll.u8	q8, d16, #7
-@ CHECK: vshll.u16	q8, d16, #15  @ encoding: [0x30,0x0a,0xdf,0xf3]
 	vshll.u16	q8, d16, #15
-@ CHECK: vshll.u32	q8, d16, #31  @ encoding: [0x30,0x0a,0xff,0xf3]
 	vshll.u32	q8, d16, #31
-@ CHECK: vshll.i8	q8, d16, #8  @ encoding: [0x20,0x03,0xf2,0xf3]
 	vshll.i8	q8, d16, #8
-@ CHECK: vshll.i16	q8, d16, #16  @ encoding: [0x20,0x03,0xf6,0xf3]
 	vshll.i16	q8, d16, #16
-@ CHECK: vshll.i32	q8, d16, #32  @ encoding: [0x20,0x03,0xfa,0xf3]
 	vshll.i32	q8, d16, #32
-@ CHECK: vshrn.i16	d16, q8, #8  @ encoding: [0x30,0x08,0xc8,0xf2]
+
+@ CHECK: vshll.s8	q8, d16, #7  @ encoding: [0x30,0x0a,0xcf,0xf2]
+@ CHECK: vshll.s16	q8, d16, #15  @ encoding: [0x30,0x0a,0xdf,0xf2]
+@ CHECK: vshll.s32	q8, d16, #31  @ encoding: [0x30,0x0a,0xff,0xf2]
+@ CHECK: vshll.u8	q8, d16, #7  @ encoding: [0x30,0x0a,0xcf,0xf3]
+@ CHECK: vshll.u16	q8, d16, #15  @ encoding: [0x30,0x0a,0xdf,0xf3]
+@ CHECK: vshll.u32	q8, d16, #31  @ encoding: [0x30,0x0a,0xff,0xf3]
+@ CHECK: vshll.i8	q8, d16, #8  @ encoding: [0x20,0x03,0xf2,0xf3]
+@ CHECK: vshll.i16	q8, d16, #16  @ encoding: [0x20,0x03,0xf6,0xf3]
+@ CHECK: vshll.i32	q8, d16, #32  @ encoding: [0x20,0x03,0xfa,0xf3]
+
 	vshrn.i16	d16, q8, #8
-@ CHECK: vshrn.i32	d16, q8, #16  @ encoding: [0x30,0x08,0xd0,0xf2]
 	vshrn.i32	d16, q8, #16
-@ CHECK: vshrn.i64	d16, q8, #32  @ encoding: [0x30,0x08,0xe0,0xf2]
 	vshrn.i64	d16, q8, #32
-@ CHECK: vrshl.s8	d16, d17, d16  @ encoding: [0xa1,0x05,0x40,0xf2]
+
+@ CHECK: vshrn.i16	d16, q8, #8  @ encoding: [0x30,0x08,0xc8,0xf2]
+@ CHECK: vshrn.i32	d16, q8, #16  @ encoding: [0x30,0x08,0xd0,0xf2]
+@ CHECK: vshrn.i64	d16, q8, #32  @ encoding: [0x30,0x08,0xe0,0xf2]
+
 	vrshl.s8	d16, d17, d16
-@ CHECK: vrshl.s16	d16, d17, d16  @ encoding: [0xa1,0x05,0x50,0xf2]
 	vrshl.s16	d16, d17, d16
-@ CHECK: vrshl.s32	d16, d17, d16  @ encoding: [0xa1,0x05,0x60,0xf2]
 	vrshl.s32	d16, d17, d16
-@ CHECK: vrshl.s64	d16, d17, d16  @ encoding: [0xa1,0x05,0x70,0xf2]
 	vrshl.s64	d16, d17, d16
-@ CHECK: vrshl.u8	d16, d17, d16  @ encoding: [0xa1,0x05,0x40,0xf3]
 	vrshl.u8	d16, d17, d16
-@ CHECK: vrshl.u16	d16, d17, d16  @ encoding: [0xa1,0x05,0x50,0xf3]
 	vrshl.u16	d16, d17, d16
-@ CHECK: vrshl.u32	d16, d17, d16  @ encoding: [0xa1,0x05,0x60,0xf3]
 	vrshl.u32	d16, d17, d16
-@ CHECK: vrshl.u64	d16, d17, d16  @ encoding: [0xa1,0x05,0x70,0xf3]
 	vrshl.u64	d16, d17, d16
-@ CHECK: vrshl.s8	q8, q9, q8  @ encoding: [0xe2,0x05,0x40,0xf2]
 	vrshl.s8	q8, q9, q8
-@ CHECK: vrshl.s16	q8, q9, q8  @ encoding: [0xe2,0x05,0x50,0xf2]
 	vrshl.s16	q8, q9, q8
-@ CHECK: vrshl.s32	q8, q9, q8  @ encoding: [0xe2,0x05,0x60,0xf2]
 	vrshl.s32	q8, q9, q8
-@ CHECK: vrshl.s64	q8, q9, q8  @ encoding: [0xe2,0x05,0x70,0xf2]
 	vrshl.s64	q8, q9, q8
-@ CHECK: vrshl.u8	q8, q9, q8  @ encoding: [0xe2,0x05,0x40,0xf3]
 	vrshl.u8	q8, q9, q8
-@ CHECK: vrshl.u16	q8, q9, q8  @ encoding: [0xe2,0x05,0x50,0xf3]
 	vrshl.u16	q8, q9, q8
-@ CHECK: vrshl.u32	q8, q9, q8  @ encoding: [0xe2,0x05,0x60,0xf3]
 	vrshl.u32	q8, q9, q8
-@ CHECK: vrshl.u64	q8, q9, q8  @ encoding: [0xe2,0x05,0x70,0xf3]
 	vrshl.u64	q8, q9, q8
-@ CHECK: vrshr.s8	d16, d16, #8  @ encoding: [0x30,0x02,0xc8,0xf2]
+
+@ CHECK: vrshl.s8	d16, d17, d16  @ encoding: [0xa1,0x05,0x40,0xf2]
+@ CHECK: vrshl.s16	d16, d17, d16  @ encoding: [0xa1,0x05,0x50,0xf2]
+@ CHECK: vrshl.s32	d16, d17, d16  @ encoding: [0xa1,0x05,0x60,0xf2]
+@ CHECK: vrshl.s64	d16, d17, d16  @ encoding: [0xa1,0x05,0x70,0xf2]
+@ CHECK: vrshl.u8	d16, d17, d16  @ encoding: [0xa1,0x05,0x40,0xf3]
+@ CHECK: vrshl.u16	d16, d17, d16  @ encoding: [0xa1,0x05,0x50,0xf3]
+@ CHECK: vrshl.u32	d16, d17, d16  @ encoding: [0xa1,0x05,0x60,0xf3]
+@ CHECK: vrshl.u64	d16, d17, d16  @ encoding: [0xa1,0x05,0x70,0xf3]
+@ CHECK: vrshl.s8	q8, q9, q8  @ encoding: [0xe2,0x05,0x40,0xf2]
+@ CHECK: vrshl.s16	q8, q9, q8  @ encoding: [0xe2,0x05,0x50,0xf2]
+@ CHECK: vrshl.s32	q8, q9, q8  @ encoding: [0xe2,0x05,0x60,0xf2]
+@ CHECK: vrshl.s64	q8, q9, q8  @ encoding: [0xe2,0x05,0x70,0xf2]
+@ CHECK: vrshl.u8	q8, q9, q8  @ encoding: [0xe2,0x05,0x40,0xf3]
+@ CHECK: vrshl.u16	q8, q9, q8  @ encoding: [0xe2,0x05,0x50,0xf3]
+@ CHECK: vrshl.u32	q8, q9, q8  @ encoding: [0xe2,0x05,0x60,0xf3]
+@ CHECK: vrshl.u64	q8, q9, q8  @ encoding: [0xe2,0x05,0x70,0xf3]
+
 	vrshr.s8	d16, d16, #8
-@ CHECK: vrshr.s16	d16, d16, #16  @ encoding: [0x30,0x02,0xd0,0xf2]
 	vrshr.s16	d16, d16, #16
-@ CHECK: vrshr.s32	d16, d16, #32  @ encoding: [0x30,0x02,0xe0,0xf2]
 	vrshr.s32	d16, d16, #32
-@ CHECK: vrshr.s64	d16, d16, #64  @ encoding: [0xb0,0x02,0xc0,0xf2]
 	vrshr.s64	d16, d16, #64
-@ CHECK: vrshr.u8	d16, d16, #8  @ encoding: [0x30,0x02,0xc8,0xf3]
 	vrshr.u8	d16, d16, #8
-@ CHECK: vrshr.u16	d16, d16, #16  @ encoding: [0x30,0x02,0xd0,0xf3]
 	vrshr.u16	d16, d16, #16
-@ CHECK: vrshr.u32	d16, d16, #32  @ encoding: [0x30,0x02,0xe0,0xf3]
 	vrshr.u32	d16, d16, #32
-@ CHECK: vrshr.u64	d16, d16, #64  @ encoding: [0xb0,0x02,0xc0,0xf3]
 	vrshr.u64	d16, d16, #64
-@ CHECK: vrshr.s8	q8, q8, #8  @ encoding: [0x70,0x02,0xc8,0xf2]
 	vrshr.s8	q8, q8, #8
-@ CHECK: vrshr.s16	q8, q8, #16  @ encoding: [0x70,0x02,0xd0,0xf2]
 	vrshr.s16	q8, q8, #16
-@ CHECK: vrshr.s32	q8, q8, #32  @ encoding: [0x70,0x02,0xe0,0xf2]
 	vrshr.s32	q8, q8, #32
-@ CHECK: vrshr.s64	q8, q8, #64  @ encoding: [0xf0,0x02,0xc0,0xf2]
 	vrshr.s64	q8, q8, #64
-@ CHECK: vrshr.u8	q8, q8, #8  @ encoding: [0x70,0x02,0xc8,0xf3]
 	vrshr.u8	q8, q8, #8
-@ CHECK: vrshr.u16	q8, q8, #16  @ encoding: [0x70,0x02,0xd0,0xf3]
 	vrshr.u16	q8, q8, #16
-@ CHECK: vrshr.u32	q8, q8, #32  @ encoding: [0x70,0x02,0xe0,0xf3]
 	vrshr.u32	q8, q8, #32
-@ CHECK: vrshr.u64	q8, q8, #64  @ encoding: [0xf0,0x02,0xc0,0xf3]
 	vrshr.u64	q8, q8, #64
-@ CHECK: vrshrn.i16	d16, q8, #8  @ encoding: [0x70,0x08,0xc8,0xf2]
+
+@ CHECK: vrshr.s8	d16, d16, #8  @ encoding: [0x30,0x02,0xc8,0xf2]
+@ CHECK: vrshr.s16	d16, d16, #16  @ encoding: [0x30,0x02,0xd0,0xf2]
+@ CHECK: vrshr.s32	d16, d16, #32  @ encoding: [0x30,0x02,0xe0,0xf2]
+@ CHECK: vrshr.s64	d16, d16, #64  @ encoding: [0xb0,0x02,0xc0,0xf2]
+@ CHECK: vrshr.u8	d16, d16, #8  @ encoding: [0x30,0x02,0xc8,0xf3]
+@ CHECK: vrshr.u16	d16, d16, #16  @ encoding: [0x30,0x02,0xd0,0xf3]
+@ CHECK: vrshr.u32	d16, d16, #32  @ encoding: [0x30,0x02,0xe0,0xf3]
+@ CHECK: vrshr.u64	d16, d16, #64  @ encoding: [0xb0,0x02,0xc0,0xf3]
+@ CHECK: vrshr.s8	q8, q8, #8  @ encoding: [0x70,0x02,0xc8,0xf2]
+@ CHECK: vrshr.s16	q8, q8, #16  @ encoding: [0x70,0x02,0xd0,0xf2]
+@ CHECK: vrshr.s32	q8, q8, #32  @ encoding: [0x70,0x02,0xe0,0xf2]
+@ CHECK: vrshr.s64	q8, q8, #64  @ encoding: [0xf0,0x02,0xc0,0xf2]
+@ CHECK: vrshr.u8	q8, q8, #8  @ encoding: [0x70,0x02,0xc8,0xf3]
+@ CHECK: vrshr.u16	q8, q8, #16  @ encoding: [0x70,0x02,0xd0,0xf3]
+@ CHECK: vrshr.u32	q8, q8, #32  @ encoding: [0x70,0x02,0xe0,0xf3]
+@ CHECK: vrshr.u64	q8, q8, #64  @ encoding: [0xf0,0x02,0xc0,0xf3]
+
+
 	vrshrn.i16	d16, q8, #8
-@ CHECK: vrshrn.i32	d16, q8, #16  @ encoding: [0x70,0x08,0xd0,0xf2]
 	vrshrn.i32	d16, q8, #16
-@ CHECK: vrshrn.i64	d16, q8, #32  @ encoding: [0x70,0x08,0xe0,0xf2]
 	vrshrn.i64	d16, q8, #32
-@ CHECK: vqrshrn.s16	d16, q8, #4  @ encoding: [0x70,0x09,0xcc,0xf2]
 	vqrshrn.s16	d16, q8, #4
-@ CHECK: vqrshrn.s32	d16, q8, #13  @ encoding: [0x70,0x09,0xd3,0xf2]
 	vqrshrn.s32	d16, q8, #13
-@ CHECK: vqrshrn.s64	d16, q8, #13  @ encoding: [0x70,0x09,0xf3,0xf2]
 	vqrshrn.s64	d16, q8, #13
-@ CHECK: vqrshrn.u16	d16, q8, #4  @ encoding: [0x70,0x09,0xcc,0xf3]
 	vqrshrn.u16	d16, q8, #4
-@ CHECK: vqrshrn.u32	d16, q8, #13  @ encoding: [0x70,0x09,0xd3,0xf3]
 	vqrshrn.u32	d16, q8, #13
-@ CHECK: vqrshrn.u64	d16, q8, #13  @ encoding: [0x70,0x09,0xf3,0xf3]
 	vqrshrn.u64	d16, q8, #13
 
+@ CHECK: vrshrn.i16	d16, q8, #8  @ encoding: [0x70,0x08,0xc8,0xf2]
+@ CHECK: vrshrn.i32	d16, q8, #16  @ encoding: [0x70,0x08,0xd0,0xf2]
+@ CHECK: vrshrn.i64	d16, q8, #32  @ encoding: [0x70,0x08,0xe0,0xf2]
+@ CHECK: vqrshrn.s16	d16, q8, #4  @ encoding: [0x70,0x09,0xcc,0xf2]
+@ CHECK: vqrshrn.s32	d16, q8, #13  @ encoding: [0x70,0x09,0xd3,0xf2]
+@ CHECK: vqrshrn.s64	d16, q8, #13  @ encoding: [0x70,0x09,0xf3,0xf2]
+@ CHECK: vqrshrn.u16	d16, q8, #4  @ encoding: [0x70,0x09,0xcc,0xf3]
+@ CHECK: vqrshrn.u32	d16, q8, #13  @ encoding: [0x70,0x09,0xd3,0xf3]
+@ CHECK: vqrshrn.u64	d16, q8, #13  @ encoding: [0x70,0x09,0xf3,0xf3]
+
+
 @ Optional destination operand variants.
         vshl.s8 q4, q5
         vshl.s16 q4, q5
@@ -418,6 +429,41 @@ _foo:
 @ CHECK: vshl.i32	d4, d4, #17     @ encoding: [0x14,0x45,0xb1,0xf2]
 @ CHECK: vshl.i64	d4, d4, #43     @ encoding: [0x94,0x45,0xab,0xf2]
 
+        @ Two-operand VRSHL forms.
+	vrshl.s8	d11, d4
+	vrshl.s16	d12, d5
+	vrshl.s32	d13, d6
+	vrshl.s64	d14, d7
+	vrshl.u8	d15, d8
+	vrshl.u16	d16, d9
+	vrshl.u32	d17, d10
+	vrshl.u64	d18, d11
+	vrshl.s8	q1, q8
+	vrshl.s16	q2, q15
+	vrshl.s32	q3, q14
+	vrshl.s64	q4, q13
+	vrshl.u8	q5, q12
+	vrshl.u16	q6, q11
+	vrshl.u32	q7, q10
+	vrshl.u64	q8, q9
+
+@ CHECK: vrshl.s8	d11, d11, d4    @ encoding: [0x0b,0xb5,0x04,0xf2]
+@ CHECK: vrshl.s16	d12, d12, d5    @ encoding: [0x0c,0xc5,0x15,0xf2]
+@ CHECK: vrshl.s32	d13, d13, d6    @ encoding: [0x0d,0xd5,0x26,0xf2]
+@ CHECK: vrshl.s64	d14, d14, d7    @ encoding: [0x0e,0xe5,0x37,0xf2]
+@ CHECK: vrshl.u8	d15, d15, d8    @ encoding: [0x0f,0xf5,0x08,0xf3]
+@ CHECK: vrshl.u16	d16, d16, d9    @ encoding: [0x20,0x05,0x59,0xf3]
+@ CHECK: vrshl.u32	d17, d17, d10   @ encoding: [0x21,0x15,0x6a,0xf3]
+@ CHECK: vrshl.u64	d18, d18, d11   @ encoding: [0x22,0x25,0x7b,0xf3]
+@ CHECK: vrshl.s8	q1, q1, q8      @ encoding: [0xc2,0x25,0x00,0xf2]
+@ CHECK: vrshl.s16	q2, q2, q15     @ encoding: [0xc4,0x45,0x1e,0xf2]
+@ CHECK: vrshl.s32	q3, q3, q14     @ encoding: [0xc6,0x65,0x2c,0xf2]
+@ CHECK: vrshl.s64	q4, q4, q13     @ encoding: [0xc8,0x85,0x3a,0xf2]
+@ CHECK: vrshl.u8	q5, q5, q12     @ encoding: [0xca,0xa5,0x08,0xf3]
+@ CHECK: vrshl.u16	q6, q6, q11     @ encoding: [0xcc,0xc5,0x16,0xf3]
+@ CHECK: vrshl.u32	q7, q7, q10     @ encoding: [0xce,0xe5,0x24,0xf3]
+@ CHECK: vrshl.u64	q8, q8, q9      @ encoding: [0xe0,0x05,0x72,0xf3]
+
 
 @ Two-operand forms.
 	vshr.s8	d15, #8
diff --git a/test/MC/ARM/neon-sub-encoding.s b/test/MC/ARM/neon-sub-encoding.s
index 0622e192bc62..8eb38a5f7118 100644
--- a/test/MC/ARM/neon-sub-encoding.s
+++ b/test/MC/ARM/neon-sub-encoding.s
@@ -132,3 +132,29 @@
 	vrsubhn.i32	d16, q8, q9
 @ CHECK: vrsubhn.i64	d16, q8, q9     @ encoding: [0xa2,0x06,0xe0,0xf3]
 	vrsubhn.i64	d16, q8, q9
+
+	vhsub.s8	d11, d24
+	vhsub.s16	d12, d23
+	vhsub.s32	d13, d22
+	vhsub.u8	d14, d21
+	vhsub.u16	d15, d20
+	vhsub.u32	d16, d19
+	vhsub.s8	q1, q12
+	vhsub.s16	q2, q11
+	vhsub.s32	q3, q10
+	vhsub.u8	q4, q9
+	vhsub.u16	q5, q8
+	vhsub.u32	q6, q7
+
+@ CHECK: vhsub.s8	d11, d11, d24   @ encoding: [0x28,0xb2,0x0b,0xf2]
+@ CHECK: vhsub.s16	d12, d12, d23   @ encoding: [0x27,0xc2,0x1c,0xf2]
+@ CHECK: vhsub.s32	d13, d13, d22   @ encoding: [0x26,0xd2,0x2d,0xf2]
+@ CHECK: vhsub.u8	d14, d14, d21   @ encoding: [0x25,0xe2,0x0e,0xf3]
+@ CHECK: vhsub.u16	d15, d15, d20   @ encoding: [0x24,0xf2,0x1f,0xf3]
+@ CHECK: vhsub.u32	d16, d16, d19   @ encoding: [0xa3,0x02,0x60,0xf3]
+@ CHECK: vhsub.s8	q1, q1, q12     @ encoding: [0x68,0x22,0x02,0xf2]
+@ CHECK: vhsub.s16	q2, q2, q11     @ encoding: [0x66,0x42,0x14,0xf2]
+@ CHECK: vhsub.s32	q3, q3, q10     @ encoding: [0x64,0x62,0x26,0xf2]
+@ CHECK: vhsub.u8	q4, q4, q9      @ encoding: [0x62,0x82,0x08,0xf3]
+@ CHECK: vhsub.u16	q5, q5, q8      @ encoding: [0x60,0xa2,0x1a,0xf3]
+@ CHECK: vhsub.u32	q6, q6, q7      @ encoding: [0x4e,0xc2,0x2c,0xf3]
diff --git a/test/MC/AsmParser/macro-args.s b/test/MC/AsmParser/macro-args.s
index 4b878999e424..13b197a55a81 100644
--- a/test/MC/AsmParser/macro-args.s
+++ b/test/MC/AsmParser/macro-args.s
@@ -18,3 +18,27 @@ bar
 
 // CHECK: .long 3
 // CHECK: .long 0
+
+
+.macro top
+    middle _$0, $1
+.endm
+.macro middle
+     $0:
+    .if $n > 1
+        bottom $1
+    .endif
+.endm
+.macro bottom
+    .set fred, $0
+.endm
+
+.text
+
+top foo
+top bar, 42
+
+// CHECK: _foo:
+// CHECK-NOT: fred
+// CHECK: _bar
+// CHECK-NEXT: fred = 42
diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt
index ce1446b02b10..471076a19bd7 100644
--- a/test/MC/Disassembler/ARM/arm-tests.txt
+++ b/test/MC/Disassembler/ARM/arm-tests.txt
@@ -321,3 +321,6 @@
 # CHECK: ldmgt	sp!, {r9}
 0x00 0x02 0xbd 0xc8
 
+# CHECK: cdp2	p10, #0, c6, c12, c0, #7
+0xe0 0x6a 0x0c 0xfe
+
diff --git a/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt b/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt
new file mode 100644
index 000000000000..aaae6ce2e40a
--- /dev/null
+++ b/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt
@@ -0,0 +1,4 @@
+# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
+
+# CHECK: invalid instruction encoding
+0x00 0x1a 0x50 0xfc
diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt
index 58fe20eaa275..c5dbee3aa893 100644
--- a/test/MC/Disassembler/ARM/neon.txt
+++ b/test/MC/Disassembler/ARM/neon.txt
@@ -2243,3 +2243,40 @@
 # CHECK: vld4.16	{d8, d10, d12, d14}, [r4] 
 0x8f 0x81 0x24 0xf4
 # CHECK: vld4.32	{d8, d10, d12, d14}, [r4] 
+
+# rdar://11256967
+0x0f 0x0d 0xa2 0xf4
+# CHECK: vld2.8	{d0[], d1[]}, [r2]      
+0x4f 0x0d 0xa2 0xf4
+# CHECK: vld2.16	{d0[], d1[]}, [r2]      
+0x8f 0x0d 0xa2 0xf4
+# CHECK: vld2.32	{d0[], d1[]}, [r2]      
+0x0d 0x0d 0xa2 0xf4
+# CHECK: vld2.8	{d0[], d1[]}, [r2]!     
+0x4d 0x0d 0xa2 0xf4
+# CHECK: vld2.16	{d0[], d1[]}, [r2]!     
+0x8d 0x0d 0xa2 0xf4
+# CHECK: vld2.32	{d0[], d1[]}, [r2]!     
+0x03 0x0d 0xa2 0xf4
+# CHECK: vld2.8	{d0[], d1[]}, [r2], r3  
+0x43 0x0d 0xa2 0xf4
+# CHECK: vld2.16	{d0[], d1[]}, [r2], r3  
+0x83 0x0d 0xa2 0xf4
+# CHECK: vld2.32	{d0[], d1[]}, [r2], r3  
+0x2f 0x0d 0xa3 0xf4
+# CHECK: vld2.8	{d0[], d2[]}, [r3]      
+0x6f 0x0d 0xa3 0xf4
+# CHECK: vld2.16	{d0[], d2[]}, [r3]      
+0xaf 0x0d 0xa3 0xf4
+# CHECK: vld2.32	{d0[], d2[]}, [r3]      
+0x2d 0x0d 0xa3 0xf4
+# CHECK: vld2.8	{d0[], d2[]}, [r3]!     
+0x6d 0x0d 0xa3 0xf4
+# CHECK: vld2.16	{d0[], d2[]}, [r3]!     
+0xad 0x0d 0xa3 0xf4
+# CHECK: vld2.32	{d0[], d2[]}, [r3]!     
+0x24 0x0d 0xa3 0xf4
+# CHECK: vld2.8	{d0[], d2[]}, [r3], r4  
+0x64 0x0d 0xa3 0xf4
+0xa4 0x0d 0xa3 0xf4
+# CHECK: vld2.32	{d0[], d2[]}, [r3], r4  
diff --git a/test/MC/Disassembler/ARM/neont2.txt b/test/MC/Disassembler/ARM/neont2.txt
index efe7e60ddaed..65cd2304149d 100644
--- a/test/MC/Disassembler/ARM/neont2.txt
+++ b/test/MC/Disassembler/ARM/neont2.txt
@@ -1960,3 +1960,41 @@
 # CHECK: vld4.16	{d8, d10, d12, d14}, [r4] 
 0x24 0xf9 0x8f 0x81
 # CHECK: vld4.32	{d8, d10, d12, d14}, [r4] 
+
+# rdar://11256967
+0xa2 0xf9 0x0f 0x0d
+# CHECK: vld2.8	{d0[], d1[]}, [r2]      
+0xa2 0xf9 0x4f 0x0d
+# CHECK: vld2.16	{d0[], d1[]}, [r2]      
+0xa2 0xf9 0x8f 0x0d
+# CHECK: vld2.32	{d0[], d1[]}, [r2]      
+0xa2 0xf9 0x0d 0x0d
+# CHECK: vld2.8	{d0[], d1[]}, [r2]!     
+0xa2 0xf9 0x4d 0x0d
+# CHECK: vld2.16	{d0[], d1[]}, [r2]!     
+0xa2 0xf9 0x8d 0x0d
+# CHECK: vld2.32	{d0[], d1[]}, [r2]!     
+0xa2 0xf9 0x03 0x0d
+# CHECK: vld2.8	{d0[], d1[]}, [r2], r3  
+0xa2 0xf9 0x43 0x0d
+# CHECK: vld2.16	{d0[], d1[]}, [r2], r3  
+0xa2 0xf9 0x83 0x0d
+# CHECK: vld2.32	{d0[], d1[]}, [r2], r3  
+0xa3 0xf9 0x2f 0x0d
+# CHECK: vld2.8	{d0[], d2[]}, [r3]      
+0xa3 0xf9 0x6f 0x0d
+# CHECK: vld2.16	{d0[], d2[]}, [r3]      
+0xa3 0xf9 0xaf 0x0d
+# CHECK: vld2.32	{d0[], d2[]}, [r3]      
+0xa3 0xf9 0x2d 0x0d
+# CHECK: vld2.8	{d0[], d2[]}, [r3]!     
+0xa3 0xf9 0x6d 0x0d
+# CHECK: vld2.16	{d0[], d2[]}, [r3]!     
+0xa3 0xf9 0xad 0x0d
+# CHECK: vld2.32	{d0[], d2[]}, [r3]!     
+0xa3 0xf9 0x24 0x0d
+# CHECK: vld2.8	{d0[], d2[]}, [r3], r4  
+0xa3 0xf9 0x64 0x0d
+# CHECK: vld2.16	{d0[], d2[]}, [r3], r4  
+0xa3 0xf9 0xa4 0x0d
+# CHECK: vld2.32	{d0[], d2[]}, [r3], r4  
diff --git a/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt b/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt
new file mode 100644
index 000000000000..dac4390cde8c
--- /dev/null
+++ b/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt
@@ -0,0 +1,30 @@
+# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
+
+# CHECK: potentially undefined
+# CHECK: 0x01 0x10 0x50 0x03
+0x01 0x10 0x50 0x03
+
+# CHECK: potentially undefined
+# CHECK: 0x82 0x10  0x50 0x01
+0x82 0x10 0x50 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x02 0x10 0x50 0x01
+0x02 0x10 0x50 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x1f 0x01 0x52 0x01
+0x1f 0x01 0x52 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x10 0x11 0x52 0x01
+0x10 0x11 0x52 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x10 0x0f 0x51 0x01
+0x10 0x0f 0x51 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x10 0x01 0x5f 0x01
+0x10 0x01 0x5f 0x01
+
diff --git a/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt
new file mode 100644
index 000000000000..26b286dbf4ea
--- /dev/null
+++ b/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt
@@ -0,0 +1,13 @@
+# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
+
+# CHECK: potentially undefined
+# CHECK: 0x00 0x10 0x51 0xfc
+0x00 0x10 0x51 0xfc
+
+# CHECK: potentially undefined
+# CHECK: 0x00 0xf0 0x41 0x0c
+0x00 0xf0 0x41 0x0c
+
+# CHECK: potentially undefined
+# CHECK: 0x00 0x00 0x4f 0x0c
+0x00 0x00 0x4f 0x0c
diff --git a/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt b/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt
new file mode 100644
index 000000000000..3e472cdbfb14
--- /dev/null
+++ b/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt
@@ -0,0 +1,18 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
+
+# CHECK: warning: potentially undefined
+# CHECK: 0x00 0xf0 0x0f 0x01
+0x00 0xf0 0x0f 0x01
+
+# CHECK: warning: potentially undefined
+# CHECK: 0x00 0xf0 0x4f 0x01
+0x00 0xf0 0x4f 0x01
+
+# CHECK: warning: potentially undefined
+# CHECK: 0x0f 0x0d 0x01 0x01
+0x0f 0x0d 0x01 0x01
+
+# CHECK: warning: potentially undefined
+# CHECK: 0x0f 0x0d 0x40 0x01
+0x0f 0x0d 0x40 0x01
+
diff --git a/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt b/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt
new file mode 100644
index 000000000000..64bb171bf813
--- /dev/null
+++ b/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt
@@ -0,0 +1,26 @@
+# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
+
+# CHECK: potentially undefined
+# CHECK: 0x9f 0x10 0x03 0x01
+0x9f 0x10 0x03 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x90 0xf0 0x03 0x01
+0x90 0xf0 0x03 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x90 0x1f 0x03 0x01
+0x90 0x1f 0x03 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x90 0x10 0x0f 0x01
+0x90 0x10 0x0f 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x90 0x10 0x01 0x01
+0x90 0x10 0x01 0x01
+
+# CHECK: potentially undefined
+# CHECK: 0x90 0x10 0x00 0x01
+0x90 0x10 0x00 0x01
+
diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt
new file mode 100644
index 000000000000..591d8c444af4
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips32.txt
@@ -0,0 +1,421 @@
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux
+
+# CHECK: abs.d $f12,$f14
+0x46 0x20 0x39 0x85
+
+# CHECK: abs.s $f6,$f7
+0x46 0x00 0x39 0x85
+
+# CHECK: add t1,a2,a3
+0x00 0xc7 0x48 0x20
+
+# CHECK: add.d $f18,$f12,$f14
+0x46 0x27 0x32 0x40
+
+# CHECK: add.s $f9,$f6,$f7
+0x46 0x07 0x32 0x40
+
+# CHECK: addi t1,a2,17767
+0x20 0xc9 0x45 0x67
+
+# CHECK: addiu t1,a2,-15001
+0x24 0xc9 0xc5 0x67
+
+# CHECK: addu t1,a2,a3
+0x00 0xc7 0x48 0x21
+
+# CHECK: and t1,a2,a3
+0x00 0xc7 0x48 0x24
+
+# CHECK: andi t1,a2,0x4567
+0x30 0xc9 0x45 0x67
+
+# CHECK: b 00000534
+0x10 0x00 0x01 0x4c
+
+# CHECK: bal 00000534
+0x04 0x11 0x01 0x4c
+
+# CHECK: bc1f 00000534
+0x45 0x00 0x01 0x4c
+
+# CHECK: bc1t 00000534
+0x45 0x01 0x01 0x4c
+
+# CHECK: beq t1,a2,00000534
+0x11 0x26 0x01 0x4c
+
+# CHECK: bgez a2,00000534
+0x04 0xc1 0x01 0x4c
+
+# CHECK: bgezal a2,00000534
+0x04 0xd1 0x01 0x4c
+
+# CHECK: bgtz a2,00000534
+0x1c 0xc0 0x01 0x4c
+
+# CHECK: blez a2,00000534
+0x18 0xc0 0x01 0x4c
+
+# CHECK: bne t1,a2,00000534
+0x15 0x26 0x01 0x4c
+
+# CHECK: c.eq.d $f12,$f14
+0x46 0x27 0x30 0x32
+
+# CHECK: c.eq.s $f6,$f7
+0x46 0x07 0x30 0x32
+
+# CHECK: c.f.d $f12,$f14
+0x46 0x27 0x30 0x30
+
+# CHECK: c.f.s $f6,$f7
+0x46 0x07 0x30 0x30
+
+# CHECK: c.le.d $f12,$f14
+0x46 0x27 0x30 0x3e
+
+# CHECK: c.le.s $f6,$f7
+0x46 0x07 0x30 0x3e
+
+# CHECK: c.lt.d $f12,$f14
+0x46 0x27 0x30 0x3c
+
+# CHECK: c.lt.s $f6,$f7
+0x46 0x07 0x30 0x3c
+
+# CHECK: c.nge.d $f12,$f14
+0x46 0x27 0x30 0x3d
+
+# CHECK: c.nge.s $f6,$f7
+0x46 0x07 0x30 0x3d
+
+# CHECK: c.ngl.d $f12,$f14
+0x46 0x27 0x30 0x3b
+
+# CHECK: c.ngl.s $f6,$f7
+0x46 0x07 0x30 0x3b
+
+# CHECK: c.ngle.d $f12,$f14
+0x46 0x27 0x30 0x39
+
+# CHECK: c.ngle.s $f6,$f7
+0x46 0x07 0x30 0x39
+
+# CHECK: c.ngt.d $f12,$f14
+0x46 0x27 0x30 0x3f
+
+# CHECK: c.ngt.s $f6,$f7
+0x46 0x07 0x30 0x3f
+
+# CHECK: c.ole.d $f12,$f14
+0x46 0x27 0x30 0x36
+
+# CHECK: c.ole.s $f6,$f7
+0x46 0x07 0x30 0x36
+
+# CHECK: c.olt.d $f12,$f14
+0x46 0x27 0x30 0x34
+
+# CHECK: c.olt.s $f6,$f7
+0x46 0x07 0x30 0x34
+
+# CHECK: c.seq.d $f12,$f14
+0x46 0x27 0x30 0x3a
+
+# CHECK: c.seq.s $f6,$f7
+0x46 0x07 0x30 0x3a
+
+# CHECK: c.sf.d $f12,$f14
+0x46 0x27 0x30 0x38
+
+# CHECK: c.sf.s $f6,$f7
+0x46 0x07 0x30 0x38
+
+# CHECK: c.ueq.d $f12,$f14
+0x46 0x27 0x30 0x33
+
+# CHECK: c.ueq.s $f28,$f18
+0x46 0x12 0xe0 0x33
+
+# CHECK: c.ule.d $f12,$f14
+0x46 0x27 0x30 0x37
+
+# CHECK: c.ule.s $f6,$f7
+0x46 0x07 0x30 0x37
+
+# CHECK: c.ult.d $f12,$f14
+0x46 0x27 0x30 0x35
+
+# CHECK: c.ult.s $f6,$f7
+0x46 0x07 0x30 0x35
+
+# CHECK: c.un.d $f12,$f14
+0x46 0x27 0x30 0x31
+
+# CHECK: c.un.s $f6,$f7
+0x46 0x07 0x30 0x31
+
+# CHECK: ceil.w.d $f12,$f14
+0x46 0x20 0x39 0x8e
+
+# CHECK: ceil.w.s $f6,$f7
+0x46 0x00 0x39 0x8e
+
+# CHECK: cfc1 a2,$7
+0x44 0x46 0x38 0x00
+
+# CHECK: clo a2,a3
+0x70 0xe6 0x30 0x21
+
+# CHECK: clz a2,a3
+0x70 0xe6 0x30 0x20
+
+# CHECK: ctc1 a2,$7
+0x44 0xc6 0x38 0x00
+
+# CHECK: cvt.d.s $f6,$f7
+0x46 0x00 0x38 0xa1
+
+# CHECK: cvt.d.w $f12,$f14
+0x46 0x80 0x38 0xa1
+
+# CHECK: cvt.l.d $f12,$f14
+0x46 0x20 0x39 0xa5
+
+# CHECK: cvt.l.s $f6,$f7
+0x46 0x00 0x39 0xa5
+
+# CHECK: cvt.s.d $f12,$f14
+0x46 0x20 0x39 0xa0
+
+# CHECK: cvt.s.w $f6,$f7
+0x46 0x80 0x39 0xa0
+
+# CHECK: cvt.w.d $f12,$f14
+0x46 0x20 0x39 0xa4
+
+# CHECK: cvt.w.s $f6,$f7
+0x46 0x00 0x39 0xa4
+
+# CHECK: floor.w.d $f12,$f14
+0x46 0x20 0x39 0x8f
+
+# CHECK: floor.w.s $f6,$f7
+0x46 0x00 0x39 0x8f
+
+# CHECK: j 00000530
+0x08 0x00 0x01 0x4c
+
+# CHECK: jal 00000530
+0x0c 0x00 0x01 0x4c
+
+# CHECK: jalr a2,a3
+0x00 0xe0 0xf8 0x09
+
+# CHECK: jr a3
+0x00 0xe0 0x00 0x08
+
+# CHECK: lb  a0,9158(a1)
+0x80 0xa4 0x23 0xc6
+
+# CHECK: lbu a0,6(a1)
+0x90 0xa4 0x00 0x06
+
+# CHECK: ldc1  $f9,9158(a3)
+0xd4 0xe9 0x23 0xc6
+
+# CHECK: lh  a0,12(a1)
+0x84 0xa4 0x00 0x0c
+
+# CHECK: lh  a0,12(a1)
+0x84 0xa4 0x00 0x0c
+
+# CHECK: li  v1,17767
+0x24 0x03 0x45 0x67
+
+# CHECK: ll  t1,9158(a3)
+0xc0 0xe9 0x23 0xc6
+
+# CHECK: lui a2,0x4567
+0x3c 0x06 0x45 0x67
+
+# CHECK: lw  a0,24(a1)
+0x8c 0xa4 0x00 0x18
+
+# CHECK: lwc1  $f9,9158(a3)
+0xc4 0xe9 0x23 0xc6
+
+# CHECK: madd  a2,a3
+0x70 0xc7 0x00 0x00
+
+# CHECK: maddu a2,a3
+0x70 0xc7 0x00 0x01
+
+# CHECK: mfc1  a2,$f7
+0x44 0x06 0x38 0x00
+
+# CHECK: mfhi  a1
+0x00 0x00 0x28 0x10
+
+# CHECK: mflo  a1
+0x00 0x00 0x28 0x12
+
+# CHECK: mov.d $f6,$f7
+0x46 0x20 0x39 0x86
+
+# CHECK: mov.s $f6,$f7
+0x46 0x00 0x39 0x86
+
+# CHECK: move  a2,a1
+0x00 0xa0 0x30 0x21
+
+# CHECK: msub  a2,a3
+0x70 0xc7 0x00 0x04
+
+# CHECK: msubu a2,a3
+0x70 0xc7 0x00 0x05
+
+# CHECK: mtc1  a2,$f7
+0x44 0x86 0x38 0x00
+
+# CHECK: mthi  a3
+0x00 0xe0 0x00 0x11
+
+# CHECK: mtlo  a3
+0x00 0xe0 0x00 0x13
+
+# CHECK: mul.d $f9,$f12,$f14
+0x46 0x27 0x32 0x42
+
+# CHECK: mul.s $f9,$f6,$f7
+0x46 0x07 0x32 0x42
+
+# CHECK: mul t1,a2,a3
+0x70 0xc7 0x48 0x02
+
+# CHECK: mult  v1,a1
+0x00 0x65 0x00 0x18
+
+# CHECK: multu v1,a1
+0x00 0x65 0x00 0x19
+
+# CHECK: neg.d $f12,$f14
+0x46 0x20 0x39 0x87
+
+# CHECK: neg.s $f6,$f7
+0x46 0x00 0x39 0x87
+
+# CHECK: neg v1,a1
+0x00 0x05 0x18 0x22
+
+# CHECK: nop
+0x00 0x00 0x00 0x00
+
+# CHECK: nor t1,a2,a3
+0x00 0xc7 0x48 0x27
+
+# CHECK: not v1,a1
+0x00 0xa0 0x18 0x27
+
+# CHECK: or  v1,v1,a1
+0x00 0x65 0x18 0x25
+
+# CHECK: ori t1,a2,0x4567
+0x34 0xc9 0x45 0x67
+
+# CHECK: rdhwr a2,$29
+0x7c 0x06 0xe8 0x3b
+
+# CHECK: round.w.d $f12,$f14
+0x46 0x20 0x39 0x8c
+
+# CHECK: round.w.s $f6,$f7
+0x46 0x00 0x39 0x8c
+
+# CHECK: sb  a0,9158(a1)
+0xa0 0xa4 0x23 0xc6
+
+# CHECK: sb  a0,6(a1)
+0xa0 0xa4 0x00 0x06
+
+# CHECK: sc  t1,9158(a3)
+0xe0 0xe9 0x23 0xc6
+
+# CHECK: sdc1  $f9,9158(a3)
+0xf4 0xe9 0x23 0xc6
+
+# CHECK: sh  a0,9158(a1)
+0xa4 0xa4 0x23 0xc6
+
+# CHECK: sll a0,v1,0x7
+0x00 0x03 0x21 0xc0
+
+# CHECK: sllv  v0,v1,a1
+0x00 0xa3 0x10 0x04
+
+# CHECK: slt v1,v1,a1
+0x00 0x65 0x18 0x2a
+
+# CHECK: slti  v1,v1,103
+0x28 0x63 0x00 0x67
+
+# CHECK: sltiu v1,v1,103
+0x2c 0x63 0x00 0x67
+
+# CHECK: sltu  v1,v1,a1
+0x00 0x65 0x18 0x2b
+
+# CHECK: sqrt.d  $f12,$f14
+0x46 0x20 0x39 0x84
+
+# CHECK: sqrt.s  $f6,$f7
+0x46 0x00 0x39 0x84
+
+# CHECK: sra a0,v1,0x7
+0x00 0x03 0x21 0xc3
+
+# CHECK: sra a0,v1,0x7
+0x00 0x03 0x21 0xc3
+
+# CHECK: srav  v0,v1,a1
+0x00 0xa3 0x10 0x07
+
+# CHECK: srl a0,v1,0x7
+0x00 0x03 0x21 0xc2
+
+# CHECK: srlv  v0,v1,a1
+0x00 0xa3 0x10 0x06
+
+# CHECK: sub.d $f9,$f12,$f14
+0x46 0x27 0x32 0x41
+
+# CHECK: sub.s $f9,$f6,$f7
+0x46 0x07 0x32 0x41
+
+# CHECK: sub t1,a2,a3
+0x00 0xc7 0x48 0x22
+
+# CHECK: subu  a0,v1,a1
+0x00 0x65 0x20 0x23
+
+# CHECK: sw  a0,24(a1)
+0xac 0xa4 0x00 0x18
+
+# CHECK: swc1  $f9,9158(a3)
+0xe4 0xe9 0x23 0xc6
+
+# CHECK: sync  0x7
+0x00 0x00 0x01 0xcf
+
+# CHECK: trunc.w.d $f12,$f14
+0x46 0x20 0x39 0x8d
+
+# CHECK: trunc.w.s $f6,$f7
+0x46 0x00 0x39 0x8d
+
+# CHECK: xor v1,v1,a1
+0x00 0x65 0x18 0x26
+
+# CHECK: xori  t1,a2,0x4567
+0x38 0xc9 0x45 0x67
diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt
new file mode 100644
index 000000000000..a5a3cfd095df
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips32_le.txt
@@ -0,0 +1,424 @@
+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux
+
+# CHECK: abs.d $f12,$f14
+0x85 0x39 0x20 0x46
+
+# CHECK: abs.s $f6,$f7
+0x85 0x39 0x00 0x46
+
+# CHECK: add t1,a2,a3
+0x20 0x48 0xc7 0x00
+
+# CHECK: add.d $f18,$f12,$f14
+0x40 0x32 0x27 0x46
+
+# CHECK: add.s $f9,$f6,$f7
+0x40 0x32 0x07 0x46
+
+# CHECK: addi t1,a2,17767
+0x67 0x45 0xc9 0x20
+
+# CHECK: addiu t1,a2,-15001
+0x67 0xc5 0xc9 0x24
+
+# CHECK: addu t1,a2,a3
+0x21 0x48 0xc7 0x00
+
+# CHECK: and t1,a2,a3
+0x24 0x48 0xc7 0x00
+
+# CHECK: andi t1,a2,0x4567
+0x67 0x45 0xc9 0x30
+
+# CHECK: b 00000534
+0x4c 0x01 0x00 0x10
+
+# CHECK: bal 00000534
+0x4c 0x01 0x11 0x04
+
+# CHECK: bc1f 00000534
+0x4c 0x01 0x00 0x45
+
+# CHECK: bc1t 00000534
+0x4c 0x01 0x01 0x45
+
+# CHECK: beq t1,a2,00000534
+0x4c 0x01 0x26 0x11
+
+# CHECK: bgez a2,00000534
+0x4c 0x01 0xc1 0x04
+
+# CHECK: bgezal a2,00000534
+0x4c 0x01 0xd1 0x04
+
+# CHECK: bgtz a2,00000534
+0x4c 0x01 0xc0 0x1c
+
+# CHECK: blez a2,00000534
+0x4c 0x01 0xc0 0x18
+
+# CHECK: bne t1,a2,00000534
+0x4c 0x01 0x26 0x15
+
+# CHECK: c.eq.d $f12,$f14
+0x32 0x30 0x27 0x46
+
+# CHECK: c.eq.s $f6,$f7
+0x32 0x30 0x07 0x46
+
+# CHECK: c.f.d $f12,$f14
+0x30 0x30 0x27 0x46
+
+# CHECK: c.f.s $f6,$f7
+0x30 0x30 0x07 0x46
+
+# CHECK: c.le.d $f12,$f14
+0x3e 0x30 0x27 0x46
+
+# CHECK: c.le.s $f6,$f7
+0x3e 0x30 0x07 0x46
+
+# CHECK: c.lt.d $f12,$f14
+0x3c 0x30 0x27 0x46
+
+# CHECK: c.lt.s $f6,$f7
+0x3c 0x30 0x07 0x46
+
+# CHECK: c.nge.d $f12,$f14
+0x3d 0x30 0x27 0x46
+
+# CHECK: c.nge.s $f6,$f7
+0x3d 0x30 0x07 0x46
+
+# CHECK: c.ngl.d $f12,$f14
+0x3b 0x30 0x27 0x46
+
+# CHECK: c.ngl.s $f6,$f7
+0x3b 0x30 0x07 0x46
+
+# CHECK: c.ngle.d $f12,$f14
+0x39 0x30 0x27 0x46
+
+# CHECK: c.ngle.s $f6,$f7
+0x39 0x30 0x07 0x46
+
+# CHECK: c.ngt.d $f12,$f14
+0x3f 0x30 0x27 0x46
+
+# CHECK: c.ngt.s $f6,$f7
+0x3f 0x30 0x07 0x46
+
+# CHECK: c.ole.d $f12,$f14
+0x36 0x30 0x27 0x46
+
+# CHECK: c.ole.s $f6,$f7
+0x36 0x30 0x07 0x46
+
+# CHECK: c.olt.d $f12,$f14
+0x34 0x30 0x27 0x46
+
+# CHECK: c.olt.s $f6,$f7
+0x34 0x30 0x07 0x46
+
+# CHECK: c.seq.d $f12,$f14
+0x3a 0x30 0x27 0x46
+
+# CHECK: c.seq.s $f6,$f7
+0x3a 0x30 0x07 0x46
+
+# CHECK: c.sf.d $f12,$f14
+0x38 0x30 0x27 0x46
+
+# CHECK: c.sf.s $f6,$f7
+0x38 0x30 0x07 0x46
+
+# CHECK: c.ueq.d $f12,$f14
+0x33 0x30 0x27 0x46
+
+# CHECK: c.ueq.s $f28,$f18
+0x33 0xe0 0x12 0x46
+
+# CHECK: c.ule.d $f12,$f14
+0x37 0x30 0x27 0x46
+
+# CHECK: c.ule.s $f6,$f7
+0x37 0x30 0x07 0x46
+
+# CHECK: c.ult.d $f12,$f14
+0x35 0x30 0x27 0x46
+
+# CHECK: c.ult.s $f6,$f7
+0x35 0x30 0x07 0x46
+
+# CHECK: c.un.d $f12,$f14
+0x31 0x30 0x27 0x46
+
+# CHECK: c.un.s $f6,$f7
+0x31 0x30 0x07 0x46
+
+# CHECK: ceil.w.d $f12,$f14
+0x8e 0x38 0x20 0x46
+
+# CHECK: ceil.w.s $f6,$f7
+0x8e 0x38 0x00 0x46
+
+# CHECK: cfc1 a2,$7
+0x00 0x38 0x46 0x44
+
+# CHECK: clo a2,a3
+0x21 0x30 0xe6 0x70
+
+# CHECK: clz a2,a3
+0x20 0x30 0xe6 0x70
+
+# CHECK: ctc1 a2,$7
+0x00 0x38 0xc6 0x44
+
+# CHECK: cvt.d.s $f6,$f7
+0xa1 0x39 0x00 0x46
+
+# CHECK: cvt.d.w $f12,$f14
+0xa1 0x39 0x80 0x46
+
+# CHECK: cvt.l.d $f12,$f14
+0xa5 0x39 0x20 0x46
+
+# CHECK: cvt.l.s $f6,$f7
+0xa5 0x39 0x00 0x46
+
+# CHECK: cvt.s.d $f12,$f14
+0xa0 0x39 0x20 0x46
+
+# CHECK: cvt.s.w $f6,$f7
+0xa0 0x39 0x80 0x46
+
+# CHECK: cvt.w.d $f12,$f14
+0xa4 0x39 0x20 0x46
+
+# CHECK: cvt.w.s $f6,$f7
+0xa4 0x39 0x00 0x46
+
+# CHECK: floor.w.d $f12,$f14
+0x8f 0x39 0x20 0x46
+
+# CHECK: floor.w.s $f6,$f7
+0x8f 0x39 0x00 0x46
+
+# CHECK: j 00000530
+0x4c 0x01 0x00 0x08
+
+# CHECK: jal 00000530
+0x4c 0x01 0x00 0x0c
+
+# CHECK: jalr a2,a3
+0x09 0xf8 0xe0 0x00
+
+# CHECK: jr a3
+0x08 0x00 0xe0 0x00
+
+# CHECK: lb  a0,9158(a1)
+0xc6 0x23 0xa4 0x80
+
+# CHECK: lbu a0,6(a1)
+0x06 0x00 0xa4 0x90
+
+# CHECK: ldc1  $f9,9158(a3)
+0xc6 0x23 0xe9 0xd4
+
+# CHECK: lh  a0,12(a1)
+0x0c 0x00 0xa4 0x84
+
+# CHECK: lh  a0,12(a1)
+0x0c 0x00 0xa4 0x84
+
+# CHECK: li  v1,17767
+0x67 0x45 0x03 0x24
+
+# CHECK: ll  t1,9158(a3)
+0xc6 0x23 0xe9 0xc0
+
+# CHECK: lui a2,0x4567
+0x67 0x45 0x06 0x3c
+
+# CHECK: lw  a0,24(a1)
+0x18 0x00 0xa4 0x8c
+
+# CHECK lw at,-18316(v0)
+0x74 0xb8 0x41 0x8c
+
+# CHECK: lwc1  $f9,9158(a3)
+0xc6 0x23 0xe9 0xc4
+
+# CHECK: madd  a2,a3
+0x00 0x00 0xc7 0x70
+
+# CHECK: maddu a2,a3
+0x01 0x00 0xc7 0x70
+
+# CHECK: mfc1  a2,$f7
+0x00 0x38 0x06 0x44
+
+# CHECK: mfhi  a1
+0x10 0x28 0x00 0x00
+
+# CHECK: mflo  a1
+0x12 0x28 0x00 0x00
+
+# CHECK: mov.d $f12,$f14
+0x86 0x39 0x20 0x46
+
+# CHECK: mov.s $f6,$f7
+0x86 0x39 0x00 0x46
+
+# CHECK: move  a2,a1
+0x21 0x30 0xa0 0x00
+
+# CHECK: msub  a2,a3
+0x04 0x00 0xc7 0x70
+
+# CHECK: msubu a2,a3
+0x05 0x00 0xc7 0x70
+
+# CHECK: mtc1  a2,$f7
+0x00 0x38 0x86 0x44
+
+# CHECK: mthi  a3
+0x11 0x00 0xe0 0x00
+
+# CHECK: mtlo  a3
+0x13 0x00 0xe0 0x00
+
+# CHECK: mul.d $f9,$f12,$f14
+0x42 0x32 0x27 0x46
+
+# CHECK: mul.s $f9,$f6,$f7
+0x42 0x32 0x07 0x46
+
+# CHECK: mul t1,a2,a3
+0x02 0x48 0xc7 0x70
+
+# CHECK: mult  v1,a1
+0x18 0x00 0x65 0x00
+
+# CHECK: multu v1,a1
+0x19 0x00 0x65 0x00
+
+# CHECK: neg.d $f12,$f14
+0x87 0x39 0x20 0x46
+
+# CHECK: neg.s $f6,$f7
+0x87 0x39 0x00 0x46
+
+# CHECK: neg v1,a1
+0x22 0x18 0x05 0x00
+
+# CHECK: nop
+0x00 0x00 0x00 0x00
+
+# CHECK: nor t1,a2,a3
+0x27 0x48 0xc7 0x00
+
+# CHECK: not v1,a1
+0x27 0x18 0xa0 0x00
+
+# CHECK: or  v1,v1,a1
+0x25 0x18 0x65 0x00
+
+# CHECK: ori t1,a2,0x4567
+0x67 0x45 0xc9 0x34
+
+# CHECK: rdhwr a2,$29
+0x3b 0xe8 0x06 0x7c
+
+# CHECK: round.w.d $f12,$f14
+0x8c 0x39 0x20 0x46
+
+# CHECK: round.w.s $f6,$f7
+0x8c 0x39 0x00 0x46
+
+# CHECK: sb  a0,9158(a1)
+0xc6 0x23 0xa4 0xa0
+
+# CHECK: sb  a0,6(a1)
+0x06 0x00 0xa4 0xa0
+
+# CHECK: sc  t1,9158(a3)
+0xc6 0x23 0xe9 0xe0
+
+# CHECK: sdc1  $f9,9158(a3)
+0xc6 0x23 0xe9 0xf4
+
+# CHECK: sh  a0,9158(a1)
+0xc6 0x23 0xa4 0xa4
+
+# CHECK: sll a0,v1,0x7
+0xc0 0x21 0x03 0x00
+
+# CHECK: sllv  v0,v1,a1
+0x04 0x10 0xa3 0x00
+
+# CHECK: slt v1,v1,a1
+0x2a 0x18 0x65 0x00
+
+# CHECK: slti  v1,v1,103
+0x67 0x00 0x63 0x28
+
+# CHECK: sltiu v1,v1,103
+0x67 0x00 0x63 0x2c
+
+# CHECK: sltu  v1,v1,a1
+0x2b 0x18 0x65 0x00
+
+# CHECK: sqrt.d  $f12,$f14
+0x84 0x39 0x20 0x46
+
+# CHECK: sqrt.s  $f6,$f7
+0x84 0x39 0x00 0x46
+
+# CHECK: sra a0,v1,0x7
+0xc3 0x21 0x03 0x00
+
+# CHECK: sra a0,v1,0x7
+0xc3 0x21 0x03 0x00
+
+# CHECK: srav  v0,v1,a1
+0x07 0x10 0xa3 0x00
+
+# CHECK: srl a0,v1,0x7
+0xc2 0x21 0x03 0x00
+
+# CHECK: srlv  v0,v1,a1
+0x06 0x10 0xa3 0x00
+
+# CHECK: sub.d $f9,$f12,$f14
+0x41 0x32 0x27 0x46
+
+# CHECK: sub.s $f9,$f6,$f7
+0x41 0x32 0x07 0x46
+
+# CHECK: sub t1,a2,a3
+0x22 0x48 0xc7 0x00
+
+# CHECK: subu  a0,v1,a1
+0x23 0x20 0x65 0x00
+
+# CHECK: sw  a0,24(a1)
+0x18 0x00 0xa4 0xac
+
+# CHECK: swc1  $f9,9158(a3)
+0xc6 0x23 0xe9 0xe4
+
+# CHECK: sync  0x7
+0xcf 0x01 0x00 0x00
+
+# CHECK: trunc.w.d $f12,$f14
+0x8d 0x39 0x20 0x46
+
+# CHECK: trunc.w.s $f6,$f7
+0x8d 0x39 0x00 0x46
+
+# CHECK: xor v1,v1,a1
+0x26 0x18 0x65 0x00
+
+# CHECK: xori  t1,a2,0x4567
+0x67 0x45 0xc9 0x38
diff --git a/test/MC/Disassembler/Mips/mips32r2.txt b/test/MC/Disassembler/Mips/mips32r2.txt
new file mode 100644
index 000000000000..295ffd038959
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips32r2.txt
@@ -0,0 +1,439 @@
+# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2
+
+# CHECK: abs.d $f12,$f14
+0x46 0x20 0x39 0x85
+
+# CHECK: abs.s $f6,$f7
+0x46 0x00 0x39 0x85
+
+# CHECK: add t1,a2,a3
+0x00 0xc7 0x48 0x20
+
+# CHECK: add.d $f18,$f12,$f14
+0x46 0x27 0x32 0x40
+
+# CHECK: add.s $f9,$f6,$f7
+0x46 0x07 0x32 0x40
+
+# CHECK: addi t1,a2,17767
+0x20 0xc9 0x45 0x67
+
+# CHECK: addiu t1,a2,-15001
+0x24 0xc9 0xc5 0x67
+
+# CHECK: addu t1,a2,a3
+0x00 0xc7 0x48 0x21
+
+# CHECK: and t1,a2,a3
+0x00 0xc7 0x48 0x24
+
+# CHECK: andi t1,a2,0x4567
+0x30 0xc9 0x45 0x67
+
+# CHECK: b 00000534
+0x10 0x00 0x01 0x4c
+
+# CHECK: bal 00000534
+0x04 0x11 0x01 0x4c
+
+# CHECK: bc1f 00000534
+0x45 0x00 0x01 0x4c
+
+# CHECK: bc1t 00000534
+0x45 0x01 0x01 0x4c
+
+# CHECK: beq t1,a2,00000534
+0x11 0x26 0x01 0x4c
+
+# CHECK: bgez a2,00000534
+0x04 0xc1 0x01 0x4c
+
+# CHECK: bgezal a2,00000534
+0x04 0xd1 0x01 0x4c
+
+# CHECK: bgtz a2,00000534
+0x1c 0xc0 0x01 0x4c
+
+# CHECK: blez a2,00000534
+0x18 0xc0 0x01 0x4c
+
+# CHECK: bne t1,a2,00000534
+0x15 0x26 0x01 0x4c
+
+# CHECK: c.eq.d $f12,$f14
+0x46 0x27 0x30 0x32
+
+# CHECK: c.eq.s $f6,$f7
+0x46 0x07 0x30 0x32
+
+# CHECK: c.f.d $f12,$f14
+0x46 0x27 0x30 0x30
+
+# CHECK: c.f.s $f6,$f7
+0x46 0x07 0x30 0x30
+
+# CHECK: c.le.d $f12,$f14
+0x46 0x27 0x30 0x3e
+
+# CHECK: c.le.s $f6,$f7
+0x46 0x07 0x30 0x3e
+
+# CHECK: c.lt.d $f12,$f14
+0x46 0x27 0x30 0x3c
+
+# CHECK: c.lt.s $f6,$f7
+0x46 0x07 0x30 0x3c
+
+# CHECK: c.nge.d $f12,$f14
+0x46 0x27 0x30 0x3d
+
+# CHECK: c.nge.s $f6,$f7
+0x46 0x07 0x30 0x3d
+
+# CHECK: c.ngl.d $f12,$f14
+0x46 0x27 0x30 0x3b
+
+# CHECK: c.ngl.s $f6,$f7
+0x46 0x07 0x30 0x3b
+
+# CHECK: c.ngle.d $f12,$f14
+0x46 0x27 0x30 0x39
+
+# CHECK: c.ngle.s $f6,$f7
+0x46 0x07 0x30 0x39
+
+# CHECK: c.ngt.d $f12,$f14
+0x46 0x27 0x30 0x3f
+
+# CHECK: c.ngt.s $f6,$f7
+0x46 0x07 0x30 0x3f
+
+# CHECK: c.ole.d $f12,$f14
+0x46 0x27 0x30 0x36
+
+# CHECK: c.ole.s $f6,$f7
+0x46 0x07 0x30 0x36
+
+# CHECK: c.olt.d $f12,$f14
+0x46 0x27 0x30 0x34
+
+# CHECK: c.olt.s $f6,$f7
+0x46 0x07 0x30 0x34
+
+# CHECK: c.seq.d $f12,$f14
+0x46 0x27 0x30 0x3a
+
+# CHECK: c.seq.s $f6,$f7
+0x46 0x07 0x30 0x3a
+
+# CHECK: c.sf.d $f12,$f14
+0x46 0x27 0x30 0x38
+
+# CHECK: c.sf.s $f6,$f7
+0x46 0x07 0x30 0x38
+
+# CHECK: c.ueq.d $f12,$f14
+0x46 0x27 0x30 0x33
+
+# CHECK: c.ueq.s $f28,$f18
+0x46 0x12 0xe0 0x33
+
+# CHECK: c.ule.d $f12,$f14
+0x46 0x27 0x30 0x37
+
+# CHECK: c.ule.s $f6,$f7
+0x46 0x07 0x30 0x37
+
+# CHECK: c.ult.d $f12,$f14
+0x46 0x27 0x30 0x35
+
+# CHECK: c.ult.s $f6,$f7
+0x46 0x07 0x30 0x35
+
+# CHECK: c.un.d $f12,$f14
+0x46 0x27 0x30 0x31
+
+# CHECK: c.un.s $f6,$f7
+0x46 0x07 0x30 0x31
+
+# CHECK: ceil.w.d $f12,$f14
+0x46 0x20 0x39 0x8e
+
+# CHECK: ceil.w.s $f6,$f7
+0x46 0x00 0x39 0x8e
+
+# CHECK: cfc1 a2,$7
+0x44 0x46 0x38 0x00
+
+# CHECK: clo a2,a3
+0x70 0xe6 0x30 0x21
+
+# CHECK: clz a2,a3
+0x70 0xe6 0x30 0x20
+
+# CHECK: ctc1 a2,$7
+0x44 0xc6 0x38 0x00
+
+# CHECK: cvt.d.s $f6,$f7
+0x46 0x00 0x38 0xa1
+
+# CHECK: cvt.d.w $f12,$f14
+0x46 0x80 0x38 0xa1
+
+# CHECK: cvt.l.d $f12,$f14
+0x46 0x20 0x39 0xa5
+
+# CHECK: cvt.l.s $f6,$f7
+0x46 0x00 0x39 0xa5
+
+# CHECK: cvt.s.d $f12,$f14
+0x46 0x20 0x39 0xa0
+
+# CHECK: cvt.s.w $f6,$f7
+0x46 0x80 0x39 0xa0
+
+# CHECK: cvt.w.d $f12,$f14
+0x46 0x20 0x39 0xa4
+
+# CHECK: cvt.w.s $f6,$f7
+0x46 0x00 0x39 0xa4
+
+# CHECK: floor.w.d $f12,$f14
+0x46 0x20 0x39 0x8f
+
+# CHECK: floor.w.s $f6,$f7
+0x46 0x00 0x39 0x8f
+
+# CHECK: ins s3,t1,0x6,0x7
+0x7d 0x33 0x61 0x84
+
+# CHECK: j 00000530
+0x08 0x00 0x01 0x4c
+
+# CHECK: jal 00000530
+0x0c 0x00 0x01 0x4c
+
+# CHECK: jalr a2,a3
+0x00 0xe0 0xf8 0x09
+
+# CHECK: jr a3
+0x00 0xe0 0x00 0x08
+
+# CHECK: lb  a0,9158(a1)
+0x80 0xa4 0x23 0xc6
+
+# CHECK: lbu a0,6(a1)
+0x90 0xa4 0x00 0x06
+
+# CHECK: ldc1  $f9,9158(a3)
+0xd4 0xe9 0x23 0xc6
+
+# CHECK: lh  a0,12(a1)
+0x84 0xa4 0x00 0x0c
+
+# CHECK: lh  a0,12(a1)
+0x84 0xa4 0x00 0x0c
+
+# CHECK: li  v1,17767
+0x24 0x03 0x45 0x67
+
+# CHECK: ll  t1,9158(a3)
+0xc0 0xe9 0x23 0xc6
+
+# CHECK: lui a2,0x4567
+0x3c 0x06 0x45 0x67
+
+# CHECK: lw  a0,24(a1)
+0x8c 0xa4 0x00 0x18
+
+# CHECK: lwc1  $f9,9158(a3)
+0xc4 0xe9 0x23 0xc6
+
+# CHECK: madd  a2,a3
+0x70 0xc7 0x00 0x00
+
+# CHECK: maddu a2,a3
+0x70 0xc7 0x00 0x01
+
+# CHECK: mfc1  a2,$f7
+0x44 0x06 0x38 0x00
+
+# CHECK: mfhi  a1
+0x00 0x00 0x28 0x10
+
+# CHECK: mflo  a1
+0x00 0x00 0x28 0x12
+
+# CHECK: mov.d $f6,$f7
+0x46 0x20 0x39 0x86
+
+# CHECK: mov.s $f6,$f7
+0x46 0x00 0x39 0x86
+
+# CHECK: move  a2,a1
+0x00 0xa0 0x30 0x21
+
+# CHECK: msub  a2,a3
+0x70 0xc7 0x00 0x04
+
+# CHECK: msubu a2,a3
+0x70 0xc7 0x00 0x05
+
+# CHECK: mtc1  a2,$f7
+0x44 0x86 0x38 0x00
+
+# CHECK: mthi  a3
+0x00 0xe0 0x00 0x11
+
+# CHECK: mtlo  a3
+0x00 0xe0 0x00 0x13
+
+# CHECK: mul.d $f9,$f12,$f14
+0x46 0x27 0x32 0x42
+
+# CHECK: mul.s $f9,$f6,$f7
+0x46 0x07 0x32 0x42
+
+# CHECK: mul t1,a2,a3
+0x70 0xc7 0x48 0x02
+
+# CHECK: mult  v1,a1
+0x00 0x65 0x00 0x18
+
+# CHECK: multu v1,a1
+0x00 0x65 0x00 0x19
+
+# CHECK: neg.d $f12,$f14
+0x46 0x20 0x39 0x87
+
+# CHECK: neg.s $f6,$f7
+0x46 0x00 0x39 0x87
+
+# CHECK: neg v1,a1
+0x00 0x05 0x18 0x22
+
+# CHECK: nop
+0x00 0x00 0x00 0x00
+
+# CHECK: nor t1,a2,a3
+0x00 0xc7 0x48 0x27
+
+# CHECK: not v1,a1
+0x00 0xa0 0x18 0x27
+
+# CHECK: or  v1,v1,a1
+0x00 0x65 0x18 0x25
+
+# CHECK: ori t1,a2,0x4567
+0x34 0xc9 0x45 0x67
+
+# CHECK: rdhwr a2,$29
+0x7c 0x06 0xe8 0x3b
+
+# CHECK: ror t1,a2,0x7
+0x00 0x26 0x49 0xc2
+
+# CHECK: rorv  t1,a2,a3
+0x00 0xe6 0x48 0x46
+
+# CHECK: round.w.d $f12,$f14
+0x46 0x20 0x39 0x8c
+
+# CHECK: round.w.s $f6,$f7
+0x46 0x00 0x39 0x8c
+
+# CHECK: sb  a0,9158(a1)
+0xa0 0xa4 0x23 0xc6
+
+# CHECK: sb  a0,6(a1)
+0xa0 0xa4 0x00 0x06
+
+# CHECK: sc  t1,9158(a3)
+0xe0 0xe9 0x23 0xc6
+
+# CHECK: sdc1  $f9,9158(a3)
+0xf4 0xe9 0x23 0xc6
+
+# CHECK: seb a2,a3
+0x7c 0x07 0x34 0x20
+
+# CHECK: seh a2,a3
+0x7c 0x07 0x36 0x20
+
+# CHECK: sh  a0,9158(a1)
+0xa4 0xa4 0x23 0xc6
+
+# CHECK: sll a0,v1,0x7
+0x00 0x03 0x21 0xc0
+
+# CHECK: sllv  v0,v1,a1
+0x00 0xa3 0x10 0x04
+
+# CHECK: slt v1,v1,a1
+0x00 0x65 0x18 0x2a
+
+# CHECK: slti  v1,v1,103
+0x28 0x63 0x00 0x67
+
+# CHECK: sltiu v1,v1,103
+0x2c 0x63 0x00 0x67
+
+# CHECK: sltu  v1,v1,a1
+0x00 0x65 0x18 0x2b
+
+# CHECK: sqrt.d  $f12,$f14
+0x46 0x20 0x39 0x84
+
+# CHECK: sqrt.s  $f6,$f7
+0x46 0x00 0x39 0x84
+
+# CHECK: sra a0,v1,0x7
+0x00 0x03 0x21 0xc3
+
+# CHECK: sra a0,v1,0x7
+0x00 0x03 0x21 0xc3
+
+# CHECK: srav  v0,v1,a1
+0x00 0xa3 0x10 0x07
+
+# CHECK: srl a0,v1,0x7
+0x00 0x03 0x21 0xc2
+
+# CHECK: srlv  v0,v1,a1
+0x00 0xa3 0x10 0x06
+
+# CHECK: sub.d $f9,$f12,$f14
+0x46 0x27 0x32 0x41
+
+# CHECK: sub.s $f9,$f6,$f7
+0x46 0x07 0x32 0x41
+
+# CHECK: sub t1,a2,a3
+0x00 0xc7 0x48 0x22
+
+# CHECK: subu  a0,v1,a1
+0x00 0x65 0x20 0x23
+
+# CHECK: sw  a0,24(a1)
+0xac 0xa4 0x00 0x18
+
+# CHECK: swc1  $f9,9158(a3)
+0xe4 0xe9 0x23 0xc6
+
+# CHECK: sync  0x7
+0x00 0x00 0x01 0xcf
+
+# CHECK: trunc.w.d $f12,$f14
+0x46 0x20 0x39 0x8d
+
+# CHECK: trunc.w.s $f6,$f7
+0x46 0x00 0x39 0x8d
+
+# CHECK: wsbh  a2,a3
+0x7c 0x07 0x30 0xa0
+
+# CHECK: xor v1,v1,a1
+0x00 0x65 0x18 0x26
+
+# CHECK: xori  t1,a2,0x4567
+0x38 0xc9 0x45 0x67
diff --git a/test/MC/Disassembler/Mips/mips32r2_le.txt b/test/MC/Disassembler/Mips/mips32r2_le.txt
new file mode 100644
index 000000000000..6d8be790f148
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips32r2_le.txt
@@ -0,0 +1,442 @@
+# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2
+
+# CHECK: abs.d $f12,$f14
+0x85 0x39 0x20 0x46
+
+# CHECK: abs.s $f6,$f7
+0x85 0x39 0x00 0x46
+
+# CHECK: add t1,a2,a3
+0x20 0x48 0xc7 0x00
+
+# CHECK: add.d $f18,$f12,$f14
+0x40 0x32 0x27 0x46
+
+# CHECK: add.s $f9,$f6,$f7
+0x40 0x32 0x07 0x46
+
+# CHECK: addi t1,a2,17767
+0x67 0x45 0xc9 0x20
+
+# CHECK: addiu t1,a2,-15001
+0x67 0xc5 0xc9 0x24
+
+# CHECK: addu t1,a2,a3
+0x21 0x48 0xc7 0x00
+
+# CHECK: and t1,a2,a3
+0x24 0x48 0xc7 0x00
+
+# CHECK: andi t1,a2,0x4567
+0x67 0x45 0xc9 0x30
+
+# CHECK: b 00000534
+0x4c 0x01 0x00 0x10
+
+# CHECK: bal 00000534
+0x4c 0x01 0x11 0x04
+
+# CHECK: bc1f 00000534
+0x4c 0x01 0x00 0x45
+
+# CHECK: bc1t 00000534
+0x4c 0x01 0x01 0x45
+
+# CHECK: beq t1,a2,00000534
+0x4c 0x01 0x26 0x11
+
+# CHECK: bgez a2,00000534
+0x4c 0x01 0xc1 0x04
+
+# CHECK: bgezal a2,00000534
+0x4c 0x01 0xd1 0x04
+
+# CHECK: bgtz a2,00000534
+0x4c 0x01 0xc0 0x1c
+
+# CHECK: blez a2,00000534
+0x4c 0x01 0xc0 0x18
+
+# CHECK: bne t1,a2,00000534
+0x4c 0x01 0x26 0x15
+
+# CHECK: c.eq.d $f12,$f14
+0x32 0x30 0x27 0x46
+
+# CHECK: c.eq.s $f6,$f7
+0x32 0x30 0x07 0x46
+
+# CHECK: c.f.d $f12,$f14
+0x30 0x30 0x27 0x46
+
+# CHECK: c.f.s $f6,$f7
+0x30 0x30 0x07 0x46
+
+# CHECK: c.le.d $f12,$f14
+0x3e 0x30 0x27 0x46
+
+# CHECK: c.le.s $f6,$f7
+0x3e 0x30 0x07 0x46
+
+# CHECK: c.lt.d $f12,$f14
+0x3c 0x30 0x27 0x46
+
+# CHECK: c.lt.s $f6,$f7
+0x3c 0x30 0x07 0x46
+
+# CHECK: c.nge.d $f12,$f14
+0x3d 0x30 0x27 0x46
+
+# CHECK: c.nge.s $f6,$f7
+0x3d 0x30 0x07 0x46
+
+# CHECK: c.ngl.d $f12,$f14
+0x3b 0x30 0x27 0x46
+
+# CHECK: c.ngl.s $f6,$f7
+0x3b 0x30 0x07 0x46
+
+# CHECK: c.ngle.d $f12,$f14
+0x39 0x30 0x27 0x46
+
+# CHECK: c.ngle.s $f6,$f7
+0x39 0x30 0x07 0x46
+
+# CHECK: c.ngt.d $f12,$f14
+0x3f 0x30 0x27 0x46
+
+# CHECK: c.ngt.s $f6,$f7
+0x3f 0x30 0x07 0x46
+
+# CHECK: c.ole.d $f12,$f14
+0x36 0x30 0x27 0x46
+
+# CHECK: c.ole.s $f6,$f7
+0x36 0x30 0x07 0x46
+
+# CHECK: c.olt.d $f12,$f14
+0x34 0x30 0x27 0x46
+
+# CHECK: c.olt.s $f6,$f7
+0x34 0x30 0x07 0x46
+
+# CHECK: c.seq.d $f12,$f14
+0x3a 0x30 0x27 0x46
+
+# CHECK: c.seq.s $f6,$f7
+0x3a 0x30 0x07 0x46
+
+# CHECK: c.sf.d $f12,$f14
+0x38 0x30 0x27 0x46
+
+# CHECK: c.sf.s $f6,$f7
+0x38 0x30 0x07 0x46
+
+# CHECK: c.ueq.d $f12,$f14
+0x33 0x30 0x27 0x46
+
+# CHECK: c.ueq.s $f28,$f18
+0x33 0xe0 0x12 0x46
+
+# CHECK: c.ule.d $f12,$f14
+0x37 0x30 0x27 0x46
+
+# CHECK: c.ule.s $f6,$f7
+0x37 0x30 0x07 0x46
+
+# CHECK: c.ult.d $f12,$f14
+0x35 0x30 0x27 0x46
+
+# CHECK: c.ult.s $f6,$f7
+0x35 0x30 0x07 0x46
+
+# CHECK: c.un.d $f12,$f14
+0x31 0x30 0x27 0x46
+
+# CHECK: c.un.s $f6,$f7
+0x31 0x30 0x07 0x46
+
+# CHECK: ceil.w.d $f12,$f14
+0x8e 0x38 0x20 0x46
+
+# CHECK: ceil.w.s $f6,$f7
+0x8e 0x38 0x00 0x46
+
+# CHECK: cfc1 a2,$7
+0x00 0x38 0x46 0x44
+
+# CHECK: clo a2,a3
+0x21 0x30 0xe6 0x70
+
+# CHECK: clz a2,a3
+0x20 0x30 0xe6 0x70
+
+# CHECK: ctc1 a2,$7
+0x00 0x38 0xc6 0x44
+
+# CHECK: cvt.d.s $f6,$f7
+0xa1 0x39 0x00 0x46
+
+# CHECK: cvt.d.w $f12,$f14
+0xa1 0x39 0x80 0x46
+
+# CHECK: cvt.l.d $f12,$f14
+0xa5 0x39 0x20 0x46
+
+# CHECK: cvt.l.s $f6,$f7
+0xa5 0x39 0x00 0x46
+
+# CHECK: cvt.s.d $f12,$f14
+0xa0 0x39 0x20 0x46
+
+# CHECK: cvt.s.w $f6,$f7
+0xa0 0x39 0x80 0x46
+
+# CHECK: cvt.w.d $f12,$f14
+0xa4 0x39 0x20 0x46
+
+# CHECK: cvt.w.s $f6,$f7
+0xa4 0x39 0x00 0x46
+
+# CHECK: floor.w.d $f12,$f14
+0x8f 0x39 0x20 0x46
+
+# CHECK: floor.w.s $f6,$f7
+0x8f 0x39 0x00 0x46
+
+# CHECK: ins s3,t1,0x6,0x7
+0x84 0x61 0x33 0x7d
+
+# CHECK: j 00000530
+0x4c 0x01 0x00 0x08
+
+# CHECK: jal 00000530
+0x4c 0x01 0x00 0x0c
+
+# CHECK: jalr a2,a3
+0x09 0xf8 0xe0 0x00
+
+# CHECK: jr a3
+0x08 0x00 0xe0 0x00
+
+# CHECK: lb  a0,9158(a1)
+0xc6 0x23 0xa4 0x80
+
+# CHECK: lbu a0,6(a1)
+0x06 0x00 0xa4 0x90
+
+# CHECK: ldc1  $f9,9158(a3)
+0xc6 0x23 0xe9 0xd4
+
+# CHECK: lh  a0,12(a1)
+0x0c 0x00 0xa4 0x84
+
+# CHECK: lh  a0,12(a1)
+0x0c 0x00 0xa4 0x84
+
+# CHECK: li  v1,17767
+0x67 0x45 0x03 0x24
+
+# CHECK: ll  t1,9158(a3)
+0xc6 0x23 0xe9 0xc0
+
+# CHECK: lui a2,0x4567
+0x67 0x45 0x06 0x3c
+
+# CHECK: lw  a0,24(a1)
+0x18 0x00 0xa4 0x8c
+
+# CHECK lw at,-18316(v0)
+0x74 0xb8 0x41 0x8c
+
+# CHECK: lwc1  $f9,9158(a3)
+0xc6 0x23 0xe9 0xc4
+
+# CHECK: madd  a2,a3
+0x00 0x00 0xc7 0x70
+
+# CHECK: maddu a2,a3
+0x01 0x00 0xc7 0x70
+
+# CHECK: mfc1  a2,$f7
+0x00 0x38 0x06 0x44
+
+# CHECK: mfhi  a1
+0x10 0x28 0x00 0x00
+
+# CHECK: mflo  a1
+0x12 0x28 0x00 0x00
+
+# CHECK: mov.d $f12,$f14
+0x86 0x39 0x20 0x46
+
+# CHECK: mov.s $f6,$f7
+0x86 0x39 0x00 0x46
+
+# CHECK: move  a2,a1
+0x21 0x30 0xa0 0x00
+
+# CHECK: msub  a2,a3
+0x04 0x00 0xc7 0x70
+
+# CHECK: msubu a2,a3
+0x05 0x00 0xc7 0x70
+
+# CHECK: mtc1  a2,$f7
+0x00 0x38 0x86 0x44
+
+# CHECK: mthi  a3
+0x11 0x00 0xe0 0x00
+
+# CHECK: mtlo  a3
+0x13 0x00 0xe0 0x00
+
+# CHECK: mul.d $f9,$f12,$f14
+0x42 0x32 0x27 0x46
+
+# CHECK: mul.s $f9,$f6,$f7
+0x42 0x32 0x07 0x46
+
+# CHECK: mul t1,a2,a3
+0x02 0x48 0xc7 0x70
+
+# CHECK: mult  v1,a1
+0x18 0x00 0x65 0x00
+
+# CHECK: multu v1,a1
+0x19 0x00 0x65 0x00
+
+# CHECK: neg.d $f12,$f14
+0x87 0x39 0x20 0x46
+
+# CHECK: neg.s $f6,$f7
+0x87 0x39 0x00 0x46
+
+# CHECK: neg v1,a1
+0x22 0x18 0x05 0x00
+
+# CHECK: nop
+0x00 0x00 0x00 0x00
+
+# CHECK: nor t1,a2,a3
+0x27 0x48 0xc7 0x00
+
+# CHECK: not v1,a1
+0x27 0x18 0xa0 0x00
+
+# CHECK: or  v1,v1,a1
+0x25 0x18 0x65 0x00
+
+# CHECK: ori t1,a2,0x4567
+0x67 0x45 0xc9 0x34
+
+# CHECK: rdhwr a2,$29
+0x3b 0xe8 0x06 0x7c
+
+# CHECK: ror t1,a2,0x7
+0xc2 0x49 0x26 0x00
+
+# CHECK: rorv  t1,a2,a3
+0x46 0x48 0xe6 0x00
+
+# CHECK: round.w.d $f12,$f14
+0x8c 0x39 0x20 0x46
+
+# CHECK: round.w.s $f6,$f7
+0x8c 0x39 0x00 0x46
+
+# CHECK: sb  a0,9158(a1)
+0xc6 0x23 0xa4 0xa0
+
+# CHECK: sb  a0,6(a1)
+0x06 0x00 0xa4 0xa0
+
+# CHECK: sc  t1,9158(a3)
+0xc6 0x23 0xe9 0xe0
+
+# CHECK: sdc1  $f9,9158(a3)
+0xc6 0x23 0xe9 0xf4
+
+# CHECK: seb a2,a3
+0x20 0x34 0x07 0x7c
+
+# CHECK: seh a2,a3
+0x20 0x36 0x07 0x7c
+
+# CHECK: sh  a0,9158(a1)
+0xc6 0x23 0xa4 0xa4
+
+# CHECK: sll a0,v1,0x7
+0xc0 0x21 0x03 0x00
+
+# CHECK: sllv  v0,v1,a1
+0x04 0x10 0xa3 0x00
+
+# CHECK: slt v1,v1,a1
+0x2a 0x18 0x65 0x00
+
+# CHECK: slti  v1,v1,103
+0x67 0x00 0x63 0x28
+
+# CHECK: sltiu v1,v1,103
+0x67 0x00 0x63 0x2c
+
+# CHECK: sltu  v1,v1,a1
+0x2b 0x18 0x65 0x00
+
+# CHECK: sqrt.d  $f12,$f14
+0x84 0x39 0x20 0x46
+
+# CHECK: sqrt.s  $f6,$f7
+0x84 0x39 0x00 0x46
+
+# CHECK: sra a0,v1,0x7
+0xc3 0x21 0x03 0x00
+
+# CHECK: sra a0,v1,0x7
+0xc3 0x21 0x03 0x00
+
+# CHECK: srav  v0,v1,a1
+0x07 0x10 0xa3 0x00
+
+# CHECK: srl a0,v1,0x7
+0xc2 0x21 0x03 0x00
+
+# CHECK: srlv  v0,v1,a1
+0x06 0x10 0xa3 0x00
+
+# CHECK: sub.d $f9,$f12,$f14
+0x41 0x32 0x27 0x46
+
+# CHECK: sub.s $f9,$f6,$f7
+0x41 0x32 0x07 0x46
+
+# CHECK: sub t1,a2,a3
+0x22 0x48 0xc7 0x00
+
+# CHECK: subu  a0,v1,a1
+0x23 0x20 0x65 0x00
+
+# CHECK: sw  a0,24(a1)
+0x18 0x00 0xa4 0xac
+
+# CHECK: swc1  $f9,9158(a3)
+0xc6 0x23 0xe9 0xe4
+
+# CHECK: sync  0x7
+0xcf 0x01 0x00 0x00
+
+# CHECK: trunc.w.d $f12,$f14
+0x8d 0x39 0x20 0x46
+
+# CHECK: trunc.w.s $f6,$f7
+0x8d 0x39 0x00 0x46
+
+# CHECK: wsbh  a2,a3
+0xa0 0x30 0x07 0x7c
+
+# CHECK: xor v1,v1,a1
+0x26 0x18 0x65 0x00
+
+# CHECK: xori  t1,a2,0x4567
+0x67 0x45 0xc9 0x38
diff --git a/test/MC/Disassembler/Mips/mips64.txt b/test/MC/Disassembler/Mips/mips64.txt
new file mode 100644
index 000000000000..1c7447a815fc
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips64.txt
@@ -0,0 +1,67 @@
+# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux

+

+# CHECK: daddiu t3,k0,31949

+0x67 0x4b 0x7c 0xcd

+

+# CHECK: daddu k0,at,t3

+0x00 0x2b 0xd0 0x2d

+

+# CHECK: ddiv zero,k0,s6

+0x03 0x56 0x00 0x1e

+

+# CHECK: ddivu zero,t1,t8

+0x01 0x38 0x00 0x1f

+

+# CHECK: dmfc1 v0,$f14

+0x44 0x22 0x70 0x00

+

+# CHECK: dmtc1 s7,$f5

+0x44 0xb7 0x28 0x00

+

+# CHECK: dmult t3,k0

+0x01 0x7a 0x00 0x1c

+

+# CHECK: dmultu s7,t5

+0x02 0xed 0x00 0x1d

+

+# CHECK: dsll v1,t8,0x11

+0x00 0x18 0x1c 0x78

+

+# CHECK: dsllv gp,k1,t8

+0x03 0x1b 0xe0 0x14

+

+# CHECK: dsra at,at,0x1e

+0x00 0x01 0x0f 0xbb

+

+# CHECK: dsrav at,at,s8

+0x03 0xc1 0x08 0x17

+

+# CHECK: dsrl t2,gp,0x18

+0x00 0x1c 0x56 0x3a

+

+# CHECK: dsrlv gp,t2,s7

+0x02 0xea 0xe0 0x16

+

+# CHECK: dsubu gp,k1,t8

+0x03 0x78 0xe0 0x2f

+

+# CHECK: lw k1,-15155(at)

+0x8c 0x3b 0xc4 0xcd

+

+# CHECK: lui at,0x1

+0x3c 0x01 0x00 0x01

+

+# CHECK: lwu v1,-1746(v1)

+0x9c 0x63 0xf9 0x2e

+

+# CHECK: lui ra,0x1

+0x3c 0x1f 0x00 0x01

+

+# CHECK: sw k0,-15159(at)

+0xac 0x3a 0xc4 0xc9

+

+# CHECK: ld k0,3958(zero)

+0xdc 0x1a 0x0f 0x76

+

+# CHECK: sd a2,17767(zero)

+0xfc 0x06 0x45 0x67

diff --git a/test/MC/Disassembler/Mips/mips64_le.txt b/test/MC/Disassembler/Mips/mips64_le.txt
new file mode 100644
index 000000000000..dd87522b083f
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips64_le.txt
@@ -0,0 +1,67 @@
+# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux

+

+# CHECK: daddiu t3,k0,31949

+0xcd 0x7c 0x4b 0x67

+

+# CHECK: daddu k0,at,t3

+0x2d 0xd0 0x2b 0x00

+

+# CHECK: ddiv zero,k0,s6

+0x1e 0x00 0x56 0x03

+

+# CHECK: ddivu zero,t1,t8

+0x1f 0x00 0x38 0x01

+

+# CHECK: dmfc1 v0,$f14

+0x00 0x70 0x22 0x44

+

+# CHECK: dmtc1 s7,$f5

+0x00 0x28 0xb7 0x44

+

+# CHECK: dmult t3,k0

+0x1c 0x00 0x7a 0x01

+

+# CHECK: dmultu s7,t5

+0x1d 0x00 0xed 0x02

+

+# CHECK: dsll v1,t8,0x11

+0x78 0x1c 0x18 0x00

+

+# CHECK: dsllv gp,k1,t8

+0x14 0xe0 0x1b 0x03

+

+# CHECK: dsra at,at,0x1e

+0xbb 0x0f 0x01 0x00

+

+# CHECK: dsrav at,at,s8

+0x17 0x08 0xc1 0x03

+

+# CHECK: dsrl t2,gp,0x18

+0x3a 0x56 0x1c 0x00

+

+# CHECK: dsrlv gp,t2,s7

+0x16 0xe0 0xea 0x02

+

+# CHECK: dsubu gp,k1,t8

+0x2f 0xe0 0x78 0x03

+

+# CHECK: lw k1,-15155(at)

+0xcd 0xc4 0x3b 0x8c

+

+# CHECK: lui at,0x1

+0x01 0x00 0x01 0x3c

+

+# CHECK: lwu v1,-1746(v1)

+0x2e 0xf9 0x63 0x9c

+

+# CHECK: lui ra,0x1

+0x01 0x00 0x1f 0x3c

+

+# CHECK: sw k0,-15159(at)

+0xc9 0xc4 0x3a 0xac

+

+# CHECK: ld k0,3958(zero)

+0x76 0x0f 0x1a 0xdc

+

+# CHECK: sd a2,17767(zero)

+0x67 0x45 0x06 0xfc

diff --git a/test/MC/Disassembler/Mips/mips64r2.txt b/test/MC/Disassembler/Mips/mips64r2.txt
new file mode 100644
index 000000000000..26bc94d65b55
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips64r2.txt
@@ -0,0 +1,91 @@
+# RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mattr +mips64r2

+

+# CHECK: daddiu t3,k0,31949

+0x67 0x4b 0x7c 0xcd

+

+# CHECK: daddu k0,at,t3

+0x00 0x2b 0xd0 0x2d

+

+# CHECK: ddiv zero,k0,s6

+0x03 0x56 0x00 0x1e

+

+# CHECK: ddivu zero,t1,t8

+0x01 0x38 0x00 0x1f

+

+# CHECK: dmfc1 v0,$f14

+0x44 0x22 0x70 0x00

+

+# CHECK: dmtc1 s7,$f5

+0x44 0xb7 0x28 0x00

+

+# CHECK: dmult t3,k0

+0x01 0x7a 0x00 0x1c

+

+# CHECK: dmultu s7,t5

+0x02 0xed 0x00 0x1d

+

+# CHECK: dsll v1,t8,0x11

+0x00 0x18 0x1c 0x78

+

+# CHECK: dsllv gp,k1,t8

+0x03 0x1b 0xe0 0x14

+

+# CHECK: dsra at,at,0x1e

+0x00 0x01 0x0f 0xbb

+

+# CHECK: dsrav at,at,s8

+0x03 0xc1 0x08 0x17

+

+# CHECK: dsrl t2,gp,0x18

+0x00 0x1c 0x56 0x3a

+

+# CHECK: dsrlv gp,t2,s7

+0x02 0xea 0xe0 0x16

+

+# CHECK: dsubu gp,k1,t8

+0x03 0x78 0xe0 0x2f

+

+# CHECK: lw k1,-15155(at)

+0x8c 0x3b 0xc4 0xcd

+

+# CHECK: lui at,0x1

+0x3c 0x01 0x00 0x01

+

+# CHECK: lwu v1,-1746(v1)

+0x9c 0x63 0xf9 0x2e

+

+# CHECK: lui ra,0x1

+0x3c 0x1f 0x00 0x01

+

+# CHECK: sw k0,-15159(at)

+0xac 0x3a 0xc4 0xc9

+

+# CHECK: ld k0,3958(zero)

+0xdc 0x1a 0x0f 0x76

+

+# CHECK: sd a2,17767(zero)

+0xfc 0x06 0x45 0x67

+

+# CHECK: dclo t1,t8

+0x73 0x09 0x48 0x25

+

+# CHECK: dclz k0,t1

+0x71 0x3a 0xd0 0x24

+

+# CHECK: dext a3,gp,0x1d,0x1f

+0x7f 0x87 0xf7 0x43

+

+# CHECK: dins s4,gp,0xf,0x1

+0x7f 0x94 0x7b 0xc7

+

+# CHECK: dsbh a3,gp

+0x7c 0x1c 0x38 0xa4

+

+# CHECK: dshd v1,t6

+0x7c 0x0e 0x19 0x64

+

+# CHECK: drotr s4,k1,0x6

+0x00 0x3b 0xa1 0xba

+

+# CHECK: drotrv t8,s7,a1

+0x00 0xb7 0xc0 0x56

diff --git a/test/MC/Disassembler/Mips/mips64r2_le.txt b/test/MC/Disassembler/Mips/mips64r2_le.txt
new file mode 100644
index 000000000000..81a7c66d1a21
--- /dev/null
+++ b/test/MC/Disassembler/Mips/mips64r2_le.txt
@@ -0,0 +1,91 @@
+# RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mattr +mips64r2

+

+# CHECK: daddiu t3,k0,31949

+0xcd 0x7c 0x4b 0x67

+

+# CHECK: daddu k0,at,t3

+0x2d 0xd0 0x2b 0x00

+

+# CHECK: ddiv zero,k0,s6

+0x1e 0x00 0x56 0x03

+

+# CHECK: ddivu zero,t1,t8

+0x1f 0x00 0x38 0x01

+

+# CHECK: dmfc1 v0,$f14

+0x00 0x70 0x22 0x44

+

+# CHECK: dmtc1 s7,$f5

+0x00 0x28 0xb7 0x44

+

+# CHECK: dmult t3,k0

+0x1c 0x00 0x7a 0x01

+

+# CHECK: dmultu s7,t5

+0x1d 0x00 0xed 0x02

+

+# CHECK: dsll v1,t8,0x11

+0x78 0x1c 0x18 0x00

+

+# CHECK: dsllv gp,k1,t8

+0x14 0xe0 0x1b 0x03

+

+# CHECK: dsra at,at,0x1e

+0xbb 0x0f 0x01 0x00

+

+# CHECK: dsrav at,at,s8

+0x17 0x08 0xc1 0x03

+

+# CHECK: dsrl t2,gp,0x18

+0x3a 0x56 0x1c 0x00

+

+# CHECK: dsrlv gp,t2,s7

+0x16 0xe0 0xea 0x02

+

+# CHECK: dsubu gp,k1,t8

+0x2f 0xe0 0x78 0x03

+

+# CHECK: lw k1,-15155(at)

+0xcd 0xc4 0x3b 0x8c

+

+# CHECK: lui at,0x1

+0x01 0x00 0x01 0x3c

+

+# CHECK: lwu v1,-1746(v1)

+0x2e 0xf9 0x63 0x9c

+

+# CHECK: lui ra,0x1

+0x01 0x00 0x1f 0x3c

+

+# CHECK: sw k0,-15159(at)

+0xc9 0xc4 0x3a 0xac

+

+# CHECK: ld k0,3958(zero)

+0x76 0x0f 0x1a 0xdc

+

+# CHECK: sd a2,17767(zero)

+0x67 0x45 0x06 0xfc

+

+# CHECK: dclo t1,t8

+0x25 0x48 0x09 0x73

+

+# CHECK: dclz k0,t1

+0x24 0xd0 0x3a 0x71

+

+# CHECK: dext a3,gp,0x1d,0x1f

+0x43 0xf7 0x87 0x7f

+

+# CHECK: dins s4,gp,0xf,0x1

+0xc7 0x7b 0x94 0x7f

+

+# CHECK: dsbh a3,gp

+0xa4 0x38 0x1c 0x7c

+

+# CHECK: dshd v1,t6

+0x64 0x19 0x0e 0x7c

+

+# CHECK: drotr s4,k1,0x6

+0xba 0xa1 0x3b 0x00

+

+# CHECK: drotrv t8,s7,a1

+0x56 0xc0 0xb7 0x00

diff --git a/test/MC/Disassembler/X86/intel-syntax.txt b/test/MC/Disassembler/X86/intel-syntax.txt
index 3391e45cc000..a5dbcf29b964 100644
--- a/test/MC/Disassembler/X86/intel-syntax.txt
+++ b/test/MC/Disassembler/X86/intel-syntax.txt
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 -x86-asm-syntax=intel | FileCheck %s
+# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 --output-asm-variant=1 | FileCheck %s
 
 # CHECK: movsb
 0xa4
diff --git a/test/MC/Mips/elf-bigendian.ll b/test/MC/Mips/elf-bigendian.ll
index 875ba3ba965e..71c69bb7afa7 100644
--- a/test/MC/Mips/elf-bigendian.ll
+++ b/test/MC/Mips/elf-bigendian.ll
@@ -5,18 +5,18 @@
 
 ; Make sure that a section table (text) entry is correct.
 ; CHECK:   (('sh_name', 0x{{[0]*}}5) # '.text'
-; CHECKNEXT:   ('sh_type', 0x{{[0]*}}1)
-; CHECKNEXT:   ('sh_flags', 0x{{[0]*}}6)
-; CHECKNEXT:   ('sh_addr', 0x{{{[0-9,a-f]+}})
-; CHECKNEXT:   ('sh_offset', 0x{{{[0-9,a-f]+}})
-; CHECKNEXT:   ('sh_size', 0x{{{[0-9,a-f]+}})
-; CHECKNEXT:   ('sh_link', 0x{{[0]+}})
-; CHECKNEXT:   ('sh_info', 0x{{[0]+}})
-; CHECKNEXT:   ('sh_addralign', 0x{{[0]*}}4)
-; CHECKNEXT:   ('sh_entsize', 0x{{[0]+}})
+; CHECK-NEXT:   ('sh_type', 0x{{[0]*}}1)
+; CHECK-NEXT:   ('sh_flags', 0x{{[0]*}}6)
+; CHECK-NEXT:   ('sh_addr', 0x{{[0-9,a-f]+}})
+; CHECK-NEXT:   ('sh_offset', 0x{{[0-9,a-f]+}})
+; CHECK-NEXT:   ('sh_size', 0x{{[0-9,a-f]+}})
+; CHECK-NEXT:   ('sh_link', 0x{{[0]+}})
+; CHECK-NEXT:   ('sh_info', 0x{{[0]+}})
+; CHECK-NEXT:   ('sh_addralign', 0x{{[0]*}}4)
+; CHECK-NEXT:   ('sh_entsize', 0x{{[0]+}})
 
 ; See that at least first 3 instructions are correct: GP prologue
-; CHECKNEXT:   ('_section_data', '3c1c0000 279c0000 0399e021 {{[0-9,a-f]*}}')
+; CHECK-NEXT:   ('_section_data', '3c1c0000 279c0000 0399e021 {{[0-9,a-f, ]*}}')
 
 ; ModuleID = '../br1.c'
 target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32"
diff --git a/test/MC/Mips/sym-offset.ll b/test/MC/Mips/sym-offset.ll
new file mode 100644
index 000000000000..59399358394b
--- /dev/null
+++ b/test/MC/Mips/sym-offset.ll
@@ -0,0 +1,22 @@
+; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux %s -o - | elf-dump --dump-section-data  | FileCheck %s
+
+; FIXME: use assembler instead of llc when it becomes available.
+
+@string1 = internal global [11 x i8] c"aaaaaaaaaa\00", align 1
+@string2 = internal global [10 x i8] c"aaaa\00bbbb\00", align 1
+
+define i32 @foo1(i32 %n) nounwind readonly {
+entry:
+; check that the immediate fields of lwl and lwr are three apart.
+; 8841000e        lwl     at,14(v0)
+; 9841000b        lwr     at,11(v0)
+
+; CHECK: ('_section_data', '00001c3c 00009c27 21e09903 0000828f 0e004188 0b004198
+
+  %call = tail call i32 @memcmp(i8* getelementptr inbounds ([11 x i8]* @string1, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @string2, i32 0, i32 0), i32 4) nounwind readonly
+  %cmp = icmp eq i32 %call, 0
+  %conv = zext i1 %cmp to i32
+  ret i32 %conv
+}
+
+declare i32 @memcmp(i8* nocapture, i8* nocapture, i32) nounwind readonly
diff --git a/test/Transforms/BBVectorize/no-ldstr-conn.ll b/test/Transforms/BBVectorize/no-ldstr-conn.ll
new file mode 100644
index 000000000000..ada2a71e36ec
--- /dev/null
+++ b/test/Transforms/BBVectorize/no-ldstr-conn.ll
@@ -0,0 +1,23 @@
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+; RUN: opt < %s -bb-vectorize -bb-vectorize-req-chain-depth=2 -instcombine -gvn -S | FileCheck %s
+
+; Make sure that things (specifically getelementptr) are not connected to loads
+; and stores via the address operand (which would be bad because the address
+; is really a scalar even after vectorization)
+define i64 @test2(i64 %a) nounwind uwtable readonly {
+entry:
+  %a1 = inttoptr i64 %a to i64*
+  %a2 = getelementptr i64* %a1, i64 1
+  %a3 = getelementptr i64* %a1, i64 2
+  %v2 = load i64* %a2, align 8
+  %v3 = load i64* %a3, align 8
+  %v2a = add i64 %v2, 5
+  %v3a = add i64 %v3, 7
+  store i64 %v2a, i64* %a2, align 8
+  store i64 %v3a, i64* %a3, align 8
+  %r = add i64 %v2, %v3
+  ret i64 %r
+; CHECK: @test2
+; CHECK-NOT: getelementptr <2 x i64*>
+}
+
diff --git a/test/Transforms/BBVectorize/simple-ldstr-ptrs.ll b/test/Transforms/BBVectorize/simple-ldstr-ptrs.ll
new file mode 100644
index 000000000000..f992d4154779
--- /dev/null
+++ b/test/Transforms/BBVectorize/simple-ldstr-ptrs.ll
@@ -0,0 +1,81 @@
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+; RUN: opt < %s -bb-vectorize -bb-vectorize-req-chain-depth=3 -instcombine -gvn -S | FileCheck %s
+; RUN: opt < %s -bb-vectorize -bb-vectorize-req-chain-depth=3 -bb-vectorize-aligned-only -instcombine -gvn -S | FileCheck %s -check-prefix=CHECK-AO
+
+; Simple 3-pair chain also with loads and stores (using ptrs and gep)
+define double @test1(i64* %a, i64* %b, i64* %c) nounwind uwtable readonly {
+entry:
+  %i0 = load i64* %a, align 8
+  %i1 = load i64* %b, align 8
+  %mul = mul i64 %i0, %i1
+  %arrayidx3 = getelementptr inbounds i64* %a, i64 1
+  %i3 = load i64* %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds i64* %b, i64 1
+  %i4 = load i64* %arrayidx4, align 8
+  %mul5 = mul i64 %i3, %i4
+  %ptr = inttoptr i64 %mul to double*
+  %ptr5 = inttoptr i64 %mul5 to double*
+  %aptr = getelementptr inbounds double* %ptr, i64 2
+  %aptr5 = getelementptr inbounds double* %ptr5, i64 3
+  %av = load double* %aptr, align 16
+  %av5 = load double* %aptr5, align 16
+  %r = fmul double %av, %av5
+  store i64 %mul, i64* %c, align 8
+  %arrayidx5 = getelementptr inbounds i64* %c, i64 1
+  store i64 %mul5, i64* %arrayidx5, align 8
+  ret double %r
+; CHECK: @test1
+; CHECK: %i0.v.i0 = bitcast i64* %a to <2 x i64>*
+; CHECK: %i1.v.i0 = bitcast i64* %b to <2 x i64>*
+; CHECK: %i0 = load <2 x i64>* %i0.v.i0, align 8
+; CHECK: %i1 = load <2 x i64>* %i1.v.i0, align 8
+; CHECK: %mul = mul <2 x i64> %i0, %i1
+; CHECK: %ptr = inttoptr <2 x i64> %mul to <2 x double*>
+; CHECK: %aptr = getelementptr inbounds <2 x double*> %ptr, <2 x i64> <i64 2, i64 3>
+; CHECK: %aptr.v.r1 = extractelement <2 x double*> %aptr, i32 0
+; CHECK: %aptr.v.r2 = extractelement <2 x double*> %aptr, i32 1
+; CHECK: %av = load double* %aptr.v.r1, align 16
+; CHECK: %av5 = load double* %aptr.v.r2, align 16
+; CHECK: %r = fmul double %av, %av5
+; CHECK: %0 = bitcast i64* %c to <2 x i64>*
+; CHECK: store <2 x i64> %mul, <2 x i64>* %0, align 8
+; CHECK: ret double %r
+; CHECK-AO: @test1
+; CHECK-AO-NOT: load <2 x
+}
+
+; Simple 3-pair chain with loads and stores (using ptrs and gep)
+define void @test2(i64** %a, i64** %b, i64** %c) nounwind uwtable readonly {
+entry:
+  %i0 = load i64** %a, align 8
+  %i1 = load i64** %b, align 8
+  %arrayidx3 = getelementptr inbounds i64** %a, i64 1
+  %i3 = load i64** %arrayidx3, align 8
+  %arrayidx4 = getelementptr inbounds i64** %b, i64 1
+  %i4 = load i64** %arrayidx4, align 8
+  %o1 = load i64* %i1, align 8
+  %o4 = load i64* %i4, align 8
+  %ptr0 = getelementptr inbounds i64* %i0, i64 %o1
+  %ptr3 = getelementptr inbounds i64* %i3, i64 %o4
+  store i64* %ptr0, i64** %c, align 8
+  %arrayidx5 = getelementptr inbounds i64** %c, i64 1
+  store i64* %ptr3, i64** %arrayidx5, align 8
+  ret void
+; CHECK: @test2
+; CHECK: %i0.v.i0 = bitcast i64** %a to <2 x i64*>*
+; CHECK: %i1 = load i64** %b, align 8
+; CHECK: %i0 = load <2 x i64*>* %i0.v.i0, align 8
+; CHECK: %arrayidx4 = getelementptr inbounds i64** %b, i64 1
+; CHECK: %i4 = load i64** %arrayidx4, align 8
+; CHECK: %o1 = load i64* %i1, align 8
+; CHECK: %o4 = load i64* %i4, align 8
+; CHECK: %ptr0.v.i1.1 = insertelement <2 x i64> undef, i64 %o1, i32 0
+; CHECK: %ptr0.v.i1.2 = insertelement <2 x i64> %ptr0.v.i1.1, i64 %o4, i32 1
+; CHECK: %ptr0 = getelementptr inbounds <2 x i64*> %i0, <2 x i64> %ptr0.v.i1.2
+; CHECK: %0 = bitcast i64** %c to <2 x i64*>*
+; CHECK: store <2 x i64*> %ptr0, <2 x i64*>* %0, align 8
+; CHECK: ret void
+; CHECK-AO: @test2
+; CHECK-AO-NOT: <2 x
+}
+
diff --git a/test/Transforms/BBVectorize/simple-sel.ll b/test/Transforms/BBVectorize/simple-sel.ll
new file mode 100644
index 000000000000..4daa5714fbd3
--- /dev/null
+++ b/test/Transforms/BBVectorize/simple-sel.ll
@@ -0,0 +1,30 @@
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+; RUN: opt < %s -bb-vectorize -bb-vectorize-req-chain-depth=3 -instcombine -gvn -S | FileCheck %s
+
+; Basic depth-3 chain with select
+define double @test1(double %A1, double %A2, double %B1, double %B2, i1 %C1, i1 %C2) {
+; CHECK: @test1
+; CHECK: %X1.v.i1.1 = insertelement <2 x double> undef, double %B1, i32 0
+; CHECK: %X1.v.i0.1 = insertelement <2 x double> undef, double %A1, i32 0
+; CHECK: %X1.v.i1.2 = insertelement <2 x double> %X1.v.i1.1, double %B2, i32 1
+; CHECK: %X1.v.i0.2 = insertelement <2 x double> %X1.v.i0.1, double %A2, i32 1
+	%X1 = fsub double %A1, %B1
+	%X2 = fsub double %A2, %B2
+; CHECK: %X1 = fsub <2 x double> %X1.v.i0.2, %X1.v.i1.2
+	%Y1 = fmul double %X1, %A1
+	%Y2 = fmul double %X2, %A2
+; CHECK: %Y1 = fmul <2 x double> %X1, %X1.v.i0.2
+        %Z1 = select i1 %C1, double %Y1, double %B1
+        %Z2 = select i1 %C2, double %Y2, double %B2
+; CHECK: %Z1.v.i0.1 = insertelement <2 x i1> undef, i1 %C1, i32 0
+; CHECK: %Z1.v.i0.2 = insertelement <2 x i1> %Z1.v.i0.1, i1 %C2, i32 1
+; CHECK: %Z1 = select <2 x i1> %Z1.v.i0.2, <2 x double> %Y1, <2 x double> %X1.v.i1.2
+	%R  = fmul double %Z1, %Z2
+; CHECK: %Z1.v.r1 = extractelement <2 x double> %Z1, i32 0
+; CHECK: %Z1.v.r2 = extractelement <2 x double> %Z1, i32 1
+; CHECK: %R = fmul double %Z1.v.r1, %Z1.v.r2
+	ret double %R
+; CHECK: ret double %R
+}
+
+
diff --git a/test/Transforms/GlobalOpt/constantfold-initializers.ll b/test/Transforms/GlobalOpt/constantfold-initializers.ll
index af8fa324db8c..ce6e2c46d627 100644
--- a/test/Transforms/GlobalOpt/constantfold-initializers.ll
+++ b/test/Transforms/GlobalOpt/constantfold-initializers.ll
@@ -12,6 +12,11 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 @xs = global [2 x i32] zeroinitializer, align 4
 ; CHECK: @xs = global [2 x i32] [i32 1, i32 1]
 
+; PR12642
+%PR12642.struct = type { i8 }
+@PR12642.s = global <{}> zeroinitializer, align 1
+@PR12642.p = constant %PR12642.struct* bitcast (i8* getelementptr (i8* bitcast (<{}>* @PR12642.s to i8*), i64 1) to %PR12642.struct*), align 8
+
 define internal void @test1() {
 entry:
   store i32 1, i32* getelementptr inbounds ([2 x i32]* @xs, i64 0, i64 0)
diff --git a/test/Transforms/InstCombine/2012-04-30-SRem.ll b/test/Transforms/InstCombine/2012-04-30-SRem.ll
new file mode 100644
index 000000000000..a285d5aea5e5
--- /dev/null
+++ b/test/Transforms/InstCombine/2012-04-30-SRem.ll
@@ -0,0 +1,12 @@
+; RUN: opt -instcombine -S < %s | FileCheck %s
+; PR12541
+
+define i32 @foo(i32 %x) {
+  %y = xor i32 %x, 3
+  %z = srem i32 1656690544, %y
+  %sext = shl i32 %z, 24
+  %s = ashr exact i32 %sext, 24
+  ret i32 %s
+; CHECK-NOT: and
+; The shifts were wrongly being turned into an and with 112
+}
diff --git a/test/Transforms/InstCombine/apint-shift.ll b/test/Transforms/InstCombine/apint-shift.ll
index 55243a649183..0ea73a058c05 100644
--- a/test/Transforms/InstCombine/apint-shift.ll
+++ b/test/Transforms/InstCombine/apint-shift.ll
@@ -1,70 +1,93 @@
-; This test makes sure that shit instructions are properly eliminated
+; This test makes sure that shift instructions are properly eliminated
 ; even with arbitrary precision integers.
-; RUN: opt < %s -instcombine -S | not grep sh
-; END.
+; RUN: opt < %s -instcombine -S | FileCheck %s
 
+; CHECK: @test1
+; CHECK-NOT: sh
 define i47 @test1(i47 %A) {
 	%B = shl i47 %A, 0		; <i47> [#uses=1]
 	ret i47 %B
 }
 
+; CHECK: @test2
+; CHECK-NOT: sh
 define i41 @test2(i7 %X) {
 	%A = zext i7 %X to i41		; <i41> [#uses=1]
 	%B = shl i41 0, %A		; <i41> [#uses=1]
 	ret i41 %B
 }
 
+; CHECK: @test3
+; CHECK-NOT: sh
 define i41 @test3(i41 %A) {
 	%B = ashr i41 %A, 0		; <i41> [#uses=1]
 	ret i41 %B
 }
 
+; CHECK: @test4
+; CHECK-NOT: sh
 define i39 @test4(i7 %X) {
 	%A = zext i7 %X to i39		; <i39> [#uses=1]
 	%B = ashr i39 0, %A		; <i39> [#uses=1]
 	ret i39 %B
 }
 
+; CHECK: @test5
+; CHECK-NOT: sh
 define i55 @test5(i55 %A) {
 	%B = lshr i55 %A, 55		; <i55> [#uses=1]
 	ret i55 %B
 }
 
+; CHECK: @test5a
+; CHECK-NOT: sh
 define i32 @test5a(i32 %A) {
 	%B = shl i32 %A, 32		; <i32> [#uses=1]
 	ret i32 %B
 }
 
+; CHECK: @test6
+; CHECK-NOT: sh
 define i55 @test6(i55 %A) {
 	%B = shl i55 %A, 1		; <i55> [#uses=1]
 	%C = mul i55 %B, 3		; <i55> [#uses=1]
 	ret i55 %C
 }
 
+; CHECK: @test7
+; CHECK-NOT: sh
 define i29 @test7(i8 %X) {
 	%A = zext i8 %X to i29		; <i29> [#uses=1]
 	%B = ashr i29 -1, %A		; <i29> [#uses=1]
 	ret i29 %B
 }
 
+; CHECK: @test8
+; CHECK-NOT: sh
 define i7 @test8(i7 %A) {
 	%B = shl i7 %A, 4		; <i7> [#uses=1]
 	%C = shl i7 %B, 3		; <i7> [#uses=1]
 	ret i7 %C
 }
 
+; CHECK: @test9
+; CHECK-NOT: sh
 define i17 @test9(i17 %A) {
 	%B = shl i17 %A, 16		; <i17> [#uses=1]
 	%C = lshr i17 %B, 16		; <i17> [#uses=1]
 	ret i17 %C
 }
 
+; CHECK: @test10
+; CHECK-NOT: sh
 define i19 @test10(i19 %A) {
 	%B = lshr i19 %A, 18		; <i19> [#uses=1]
 	%C = shl i19 %B, 18		; <i19> [#uses=1]
 	ret i19 %C
 }
 
+; CHECK: @test11
+; CHECK-NOT: sh
 define i23 @test11(i23 %A) {
 	%a = mul i23 %A, 3		; <i23> [#uses=1]
 	%B = lshr i23 %a, 11		; <i23> [#uses=1]
@@ -72,12 +95,16 @@ define i23 @test11(i23 %A) {
 	ret i23 %C
 }
 
+; CHECK: @test12
+; CHECK-NOT: sh
 define i47 @test12(i47 %A) {
 	%B = ashr i47 %A, 8		; <i47> [#uses=1]
 	%C = shl i47 %B, 8		; <i47> [#uses=1]
 	ret i47 %C
 }
 
+; CHECK: @test13
+; CHECK-NOT: sh
 define i18 @test13(i18 %A) {
 	%a = mul i18 %A, 3		; <i18> [#uses=1]
 	%B = ashr i18 %a, 8		; <i18> [#uses=1]
@@ -85,6 +112,8 @@ define i18 @test13(i18 %A) {
 	ret i18 %C
 }
 
+; CHECK: @test14
+; CHECK-NOT: sh
 define i35 @test14(i35 %A) {
 	%B = lshr i35 %A, 4		; <i35> [#uses=1]
 	%C = or i35 %B, 1234		; <i35> [#uses=1]
@@ -92,6 +121,8 @@ define i35 @test14(i35 %A) {
 	ret i35 %D
 }
 
+; CHECK: @test14a
+; CHECK-NOT: sh
 define i79 @test14a(i79 %A) {
 	%B = shl i79 %A, 4		; <i79> [#uses=1]
 	%C = and i79 %B, 1234		; <i79> [#uses=1]
@@ -99,12 +130,16 @@ define i79 @test14a(i79 %A) {
 	ret i79 %D
 }
 
+; CHECK: @test15
+; CHECK-NOT: sh
 define i45 @test15(i1 %C) {
 	%A = select i1 %C, i45 3, i45 1	; <i45> [#uses=1]
 	%V = shl i45 %A, 2		; <i45> [#uses=1]
 	ret i45 %V
 }
 
+; CHECK: @test15a
+; CHECK-NOT: sh
 define i53 @test15a(i1 %X) {
 	%A = select i1 %X, i8 3, i8 1	; <i8> [#uses=1]
 	%B = zext i8 %A to i53		; <i53> [#uses=1]
@@ -112,6 +147,8 @@ define i53 @test15a(i1 %X) {
 	ret i53 %V
 }
 
+; CHECK: @test16
+; CHECK-NOT: sh
 define i1 @test16(i84 %X) {
 	%tmp.3 = ashr i84 %X, 4		; <i84> [#uses=1]
 	%tmp.6 = and i84 %tmp.3, 1	; <i84> [#uses=1]
@@ -119,48 +156,64 @@ define i1 @test16(i84 %X) {
 	ret i1 %tmp.7
 }
 
+; CHECK: @test17
+; CHECK-NOT: sh
 define i1 @test17(i106 %A) {
 	%B = lshr i106 %A, 3		; <i106> [#uses=1]
 	%C = icmp eq i106 %B, 1234	; <i1> [#uses=1]
 	ret i1 %C
 }
 
+; CHECK: @test18
+; CHECK-NOT: sh
 define i1 @test18(i11 %A) {
 	%B = lshr i11 %A, 10		; <i11> [#uses=1]
 	%C = icmp eq i11 %B, 123	; <i1> [#uses=1]
 	ret i1 %C
 }
 
+; CHECK: @test19
+; CHECK-NOT: sh
 define i1 @test19(i37 %A) {
 	%B = ashr i37 %A, 2		; <i37> [#uses=1]
 	%C = icmp eq i37 %B, 0		; <i1> [#uses=1]
 	ret i1 %C
 }
 
+; CHECK: @test19a
+; CHECK-NOT: sh
 define i1 @test19a(i39 %A) {
 	%B = ashr i39 %A, 2		; <i39> [#uses=1]
 	%C = icmp eq i39 %B, -1		; <i1> [#uses=1]
 	ret i1 %C
 }
 
+; CHECK: @test20
+; CHECK-NOT: sh
 define i1 @test20(i13 %A) {
 	%B = ashr i13 %A, 12		; <i13> [#uses=1]
 	%C = icmp eq i13 %B, 123	; <i1> [#uses=1]
 	ret i1 %C
 }
 
+; CHECK: @test21
+; CHECK-NOT: sh
 define i1 @test21(i12 %A) {
 	%B = shl i12 %A, 6		; <i12> [#uses=1]
 	%C = icmp eq i12 %B, -128		; <i1> [#uses=1]
 	ret i1 %C
 }
 
+; CHECK: @test22
+; CHECK-NOT: sh
 define i1 @test22(i14 %A) {
 	%B = shl i14 %A, 7		; <i14> [#uses=1]
 	%C = icmp eq i14 %B, 0		; <i1> [#uses=1]
 	ret i1 %C
 }
 
+; CHECK: @test23
+; CHECK-NOT: sh
 define i11 @test23(i44 %A) {
 	%B = shl i44 %A, 33		; <i44> [#uses=1]
 	%C = ashr i44 %B, 33		; <i44> [#uses=1]
@@ -168,6 +221,8 @@ define i11 @test23(i44 %A) {
 	ret i11 %D
 }
 
+; CHECK: @test25
+; CHECK-NOT: sh
 define i37 @test25(i37 %tmp.2, i37 %AA) {
 	%x = lshr i37 %AA, 17		; <i37> [#uses=1]
 	%tmp.3 = lshr i37 %tmp.2, 17		; <i37> [#uses=1]
@@ -176,6 +231,8 @@ define i37 @test25(i37 %tmp.2, i37 %AA) {
 	ret i37 %tmp.6
 }
 
+; CHECK: @test26
+; CHECK-NOT: sh
 define i40 @test26(i40 %A) {
 	%B = lshr i40 %A, 1		; <i40> [#uses=1]
 	%C = bitcast i40 %B to i40		; <i40> [#uses=1]
diff --git a/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll b/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll
index 2dcaab82a1a5..ed32ca8659c8 100644
--- a/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll
+++ b/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll
@@ -61,7 +61,7 @@ exit:                                 ; preds = %cond.true29.i, %cond.true.i
 ; CHECK: @test2
 ; CHECK: %entry
 ; CHECK-NOT: mov
-; CHECK: jne
+; CHECK: je
 define void @test2(i32 %n) nounwind uwtable {
 entry:
   br i1 undef, label %while.end, label %for.cond468
diff --git a/test/Transforms/LoopStrengthReduce/pr12691.ll b/test/Transforms/LoopStrengthReduce/pr12691.ll
new file mode 100644
index 000000000000..8399434343eb
--- /dev/null
+++ b/test/Transforms/LoopStrengthReduce/pr12691.ll
@@ -0,0 +1,34 @@
+; RUN: opt < %s -loop-reduce -S | FileCheck %s
+
+@d = common global i32 0, align 4
+
+define void @fn2(i32 %x) nounwind uwtable {
+entry:
+  br label %for.cond
+
+for.cond:
+  %g.0 = phi i32 [ 0, %entry ], [ %dec, %for.cond ]
+  %tobool = icmp eq i32 %x, 0
+  %dec = add nsw i32 %g.0, -1
+  br i1 %tobool, label %for.cond, label %for.end
+
+for.end:
+; CHECK:  %tmp1 = load i32* @d, align 4
+; CHECK-NEXT:  %tmp2 = load i32* @d, align 4
+; CHECK-NEXT:  %0 = sub i32 %tmp1, %tmp2
+
+  %tmp1 = load i32* @d, align 4
+  %add = add nsw i32 %tmp1, %g.0
+  %tmp2 = load i32* @d, align 4
+  %tobool26 = icmp eq i32 %x, 0
+  br i1 %tobool26, label %for.end5, label %for.body.lr.ph
+
+for.body.lr.ph:
+  %tobool3 = icmp ne i32 %tmp2, %add
+  br label %for.end5
+
+for.end5:
+  ret void
+}
+
+
diff --git a/test/Transforms/LoopUnswitch/2012-04-30-LoopUnswitch-LPad-Crash.ll b/test/Transforms/LoopUnswitch/2012-04-30-LoopUnswitch-LPad-Crash.ll
new file mode 100644
index 000000000000..261876df2aa0
--- /dev/null
+++ b/test/Transforms/LoopUnswitch/2012-04-30-LoopUnswitch-LPad-Crash.ll
@@ -0,0 +1,101 @@
+; RUN: opt < %s -basicaa -instcombine -inline -functionattrs -licm -loop-unswitch -gvn -verify
+; PR12573
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.7.0"
+
+%class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379 = type { %class.C.23.43.67.103.139.159.179.199.239.243.247.251.263.295.303.339.347.376*, %class.B.21.41.65.101.137.157.177.197.237.241.245.249.261.293.301.337.345.378 }
+%class.C.23.43.67.103.139.159.179.199.239.243.247.251.263.295.303.339.347.376 = type { %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379* }
+%class.B.21.41.65.101.137.157.177.197.237.241.245.249.261.293.301.337.345.378 = type { %class.A.20.40.64.100.136.156.176.196.236.240.244.248.260.292.300.336.344.377* }
+%class.A.20.40.64.100.136.156.176.196.236.240.244.248.260.292.300.336.344.377 = type { i8 }
+
+define void @_Z23get_reconstruction_pathv() uwtable ssp {
+entry:
+  %c = alloca %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379, align 8
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.end, %entry
+  invoke void @_ZN1DptEv(%class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379* %c)
+          to label %invoke.cont unwind label %lpad
+
+invoke.cont:                                      ; preds = %for.cond
+  invoke void @_ZN1C3endEv()
+          to label %for.cond3 unwind label %lpad
+
+for.cond3:                                        ; preds = %invoke.cont6, %invoke.cont
+  invoke void @_ZN1DptEv(%class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379* %c)
+          to label %invoke.cont4 unwind label %lpad
+
+invoke.cont4:                                     ; preds = %for.cond3
+  invoke void @_ZN1C3endEv()
+          to label %invoke.cont6 unwind label %lpad
+
+invoke.cont6:                                     ; preds = %invoke.cont4
+  br i1 undef, label %for.cond3, label %for.end
+
+lpad:                                             ; preds = %for.end, %invoke.cont4, %for.cond3, %invoke.cont, %for.cond
+  %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
+          cleanup
+  resume { i8*, i32 } undef
+
+for.end:                                          ; preds = %invoke.cont6
+  invoke void @_ZN1C13_M_insert_auxER1D()
+          to label %for.cond unwind label %lpad
+}
+
+define void @_ZN1DptEv(%class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379* %this) uwtable ssp align 2 {
+entry:
+  %this.addr = alloca %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379*, align 8
+  store %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379* %this, %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379** %this.addr, align 8, !tbaa !0
+  %this1 = load %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379** %this.addr
+  %px = getelementptr inbounds %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379* %this1, i32 0, i32 0
+  %0 = load %class.C.23.43.67.103.139.159.179.199.239.243.247.251.263.295.303.339.347.376** %px, align 8, !tbaa !0
+  %tobool = icmp ne %class.C.23.43.67.103.139.159.179.199.239.243.247.251.263.295.303.339.347.376* %0, null
+  br i1 %tobool, label %cond.end, label %cond.false
+
+cond.false:                                       ; preds = %entry
+  call void @_Z10__assert13v() noreturn
+  unreachable
+
+cond.end:                                         ; preds = %entry
+  ret void
+}
+
+declare i32 @__gxx_personality_v0(...)
+
+declare void @_ZN1C3endEv()
+
+define void @_ZN1C13_M_insert_auxER1D() uwtable ssp align 2 {
+entry:
+  ret void
+}
+
+define void @_ZN1DD1Ev() unnamed_addr uwtable inlinehint ssp align 2 {
+entry:
+  ret void
+}
+
+define void @_ZN1DD2Ev() unnamed_addr uwtable inlinehint ssp align 2 {
+entry:
+  ret void
+}
+
+define void @_ZN1BD1Ev() unnamed_addr uwtable ssp align 2 {
+entry:
+  ret void
+}
+
+define void @_ZN1BD2Ev() unnamed_addr uwtable ssp align 2 {
+entry:
+  ret void
+}
+
+define void @_ZN1BaSERS_() uwtable ssp align 2 {
+entry:
+  unreachable
+}
+
+declare void @_Z10__assert13v() noreturn
+
+!0 = metadata !{metadata !"any pointer", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
diff --git a/test/Transforms/ObjCARC/escape.ll b/test/Transforms/ObjCARC/escape.ll
new file mode 100644
index 000000000000..3f694cf1d5a4
--- /dev/null
+++ b/test/Transforms/ObjCARC/escape.ll
@@ -0,0 +1,131 @@
+; RUN: opt -objc-arc -S < %s | FileCheck %s
+; rdar://11229925
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+
+%struct.__block_byref_weakLogNTimes = type { i8*, %struct.__block_byref_weakLogNTimes*, i32, i32, i8*, i8*, void (...)* }
+%struct.__block_descriptor = type { i64, i64 }
+
+; Don't optimize away the retainBlock, because the object's address "escapes"
+; with the objc_storeWeak call.
+
+; CHECK: define void @test0(
+; CHECK: %tmp7 = call i8* @objc_retainBlock(i8* %tmp6) nounwind, !clang.arc.copy_on_escape !0
+; CHECK: call void @objc_release(i8* %tmp7) nounwind, !clang.imprecise_release !0
+; CHECK: }
+define void @test0() nounwind {
+entry:
+  %weakLogNTimes = alloca %struct.__block_byref_weakLogNTimes, align 8
+  %block = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>, align 8
+  %byref.isa = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 0
+  store i8* null, i8** %byref.isa, align 8
+  %byref.forwarding = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 1
+  store %struct.__block_byref_weakLogNTimes* %weakLogNTimes, %struct.__block_byref_weakLogNTimes** %byref.forwarding, align 8
+  %byref.flags = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 2
+  store i32 33554432, i32* %byref.flags, align 8
+  %byref.size = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 3
+  store i32 48, i32* %byref.size, align 4
+  %tmp1 = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 4
+  store i8* bitcast (void (i8*, i8*)* @__Block_byref_object_copy_ to i8*), i8** %tmp1, align 8
+  %tmp2 = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 5
+  store i8* bitcast (void (i8*)* @__Block_byref_object_dispose_ to i8*), i8** %tmp2, align 8
+  %weakLogNTimes1 = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 6
+  %tmp3 = bitcast void (...)** %weakLogNTimes1 to i8**
+  %tmp4 = call i8* @objc_initWeak(i8** %tmp3, i8* null) nounwind
+  %block.isa = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 0
+  store i8* null, i8** %block.isa, align 8
+  %block.flags = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 1
+  store i32 1107296256, i32* %block.flags, align 8
+  %block.reserved = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 2
+  store i32 0, i32* %block.reserved, align 4
+  %block.invoke = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 3
+  store i8* bitcast (void (i8*, i32)* @__main_block_invoke_0 to i8*), i8** %block.invoke, align 8
+  %block.descriptor = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 4
+  store %struct.__block_descriptor* null, %struct.__block_descriptor** %block.descriptor, align 8
+  %block.captured = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 5
+  %tmp5 = bitcast %struct.__block_byref_weakLogNTimes* %weakLogNTimes to i8*
+  store i8* %tmp5, i8** %block.captured, align 8
+  %tmp6 = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block to i8*
+  %tmp7 = call i8* @objc_retainBlock(i8* %tmp6) nounwind, !clang.arc.copy_on_escape !0
+  %tmp8 = load %struct.__block_byref_weakLogNTimes** %byref.forwarding, align 8
+  %weakLogNTimes3 = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %tmp8, i64 0, i32 6
+  %tmp9 = bitcast void (...)** %weakLogNTimes3 to i8**
+  %tmp10 = call i8* @objc_storeWeak(i8** %tmp9, i8* %tmp7) nounwind
+  %tmp11 = getelementptr inbounds i8* %tmp7, i64 16
+  %tmp12 = bitcast i8* %tmp11 to i8**
+  %tmp13 = load i8** %tmp12, align 8
+  %tmp14 = bitcast i8* %tmp13 to void (i8*, i32)*
+  call void %tmp14(i8* %tmp7, i32 10) nounwind, !clang.arc.no_objc_arc_exceptions !0
+  call void @objc_release(i8* %tmp7) nounwind, !clang.imprecise_release !0
+  call void @_Block_object_dispose(i8* %tmp5, i32 8) nounwind
+  call void @objc_destroyWeak(i8** %tmp3) nounwind
+  ret void
+}
+
+; Like test0, but it makes a regular call instead of a storeWeak call,
+; so the optimization is valid.
+
+; CHECK: define void @test1(
+; CHECK-NOT: @objc_retainBlock
+; CHECK: }
+define void @test1() nounwind {
+entry:
+  %weakLogNTimes = alloca %struct.__block_byref_weakLogNTimes, align 8
+  %block = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>, align 8
+  %byref.isa = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 0
+  store i8* null, i8** %byref.isa, align 8
+  %byref.forwarding = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 1
+  store %struct.__block_byref_weakLogNTimes* %weakLogNTimes, %struct.__block_byref_weakLogNTimes** %byref.forwarding, align 8
+  %byref.flags = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 2
+  store i32 33554432, i32* %byref.flags, align 8
+  %byref.size = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 3
+  store i32 48, i32* %byref.size, align 4
+  %tmp1 = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 4
+  store i8* bitcast (void (i8*, i8*)* @__Block_byref_object_copy_ to i8*), i8** %tmp1, align 8
+  %tmp2 = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 5
+  store i8* bitcast (void (i8*)* @__Block_byref_object_dispose_ to i8*), i8** %tmp2, align 8
+  %weakLogNTimes1 = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %weakLogNTimes, i64 0, i32 6
+  %tmp3 = bitcast void (...)** %weakLogNTimes1 to i8**
+  %tmp4 = call i8* @objc_initWeak(i8** %tmp3, i8* null) nounwind
+  %block.isa = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 0
+  store i8* null, i8** %block.isa, align 8
+  %block.flags = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 1
+  store i32 1107296256, i32* %block.flags, align 8
+  %block.reserved = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 2
+  store i32 0, i32* %block.reserved, align 4
+  %block.invoke = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 3
+  store i8* bitcast (void (i8*, i32)* @__main_block_invoke_0 to i8*), i8** %block.invoke, align 8
+  %block.descriptor = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 4
+  store %struct.__block_descriptor* null, %struct.__block_descriptor** %block.descriptor, align 8
+  %block.captured = getelementptr inbounds <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block, i64 0, i32 5
+  %tmp5 = bitcast %struct.__block_byref_weakLogNTimes* %weakLogNTimes to i8*
+  store i8* %tmp5, i8** %block.captured, align 8
+  %tmp6 = bitcast <{ i8*, i32, i32, i8*, %struct.__block_descriptor*, i8* }>* %block to i8*
+  %tmp7 = call i8* @objc_retainBlock(i8* %tmp6) nounwind, !clang.arc.copy_on_escape !0
+  %tmp8 = load %struct.__block_byref_weakLogNTimes** %byref.forwarding, align 8
+  %weakLogNTimes3 = getelementptr inbounds %struct.__block_byref_weakLogNTimes* %tmp8, i64 0, i32 6
+  %tmp9 = bitcast void (...)** %weakLogNTimes3 to i8**
+  %tmp10 = call i8* @not_really_objc_storeWeak(i8** %tmp9, i8* %tmp7) nounwind
+  %tmp11 = getelementptr inbounds i8* %tmp7, i64 16
+  %tmp12 = bitcast i8* %tmp11 to i8**
+  %tmp13 = load i8** %tmp12, align 8
+  %tmp14 = bitcast i8* %tmp13 to void (i8*, i32)*
+  call void %tmp14(i8* %tmp7, i32 10) nounwind, !clang.arc.no_objc_arc_exceptions !0
+  call void @objc_release(i8* %tmp7) nounwind, !clang.imprecise_release !0
+  call void @_Block_object_dispose(i8* %tmp5, i32 8) nounwind
+  call void @objc_destroyWeak(i8** %tmp3) nounwind
+  ret void
+}
+
+declare void @__Block_byref_object_copy_(i8*, i8*) nounwind
+declare void @__Block_byref_object_dispose_(i8*) nounwind
+declare void @objc_destroyWeak(i8**)
+declare i8* @objc_initWeak(i8**, i8*)
+declare void @__main_block_invoke_0(i8* nocapture, i32) nounwind ssp
+declare void @_Block_object_dispose(i8*, i32)
+declare i8* @objc_retainBlock(i8*)
+declare i8* @objc_storeWeak(i8**, i8*)
+declare i8* @not_really_objc_storeWeak(i8**, i8*)
+declare void @objc_release(i8*)
+
+!0 = metadata !{}
diff --git a/test/Transforms/Reassociate/pr12245.ll b/test/Transforms/Reassociate/pr12245.ll
new file mode 100644
index 000000000000..84098bdb006b
--- /dev/null
+++ b/test/Transforms/Reassociate/pr12245.ll
@@ -0,0 +1,50 @@
+; RUN: opt < %s -basicaa -inline -instcombine -reassociate -dse -disable-output
+; PR12245
+
+@a = common global i32 0, align 4
+@d = common global i32 0, align 4
+
+define i32 @fn2() nounwind uwtable ssp {
+entry:
+  %0 = load i32* @a, align 4, !tbaa !0
+  %dec = add nsw i32 %0, -1
+  store i32 %dec, i32* @a, align 4, !tbaa !0
+  %1 = load i32* @d, align 4, !tbaa !0
+  %sub = sub nsw i32 %dec, %1
+  store i32 %sub, i32* @d, align 4, !tbaa !0
+  %2 = load i32* @a, align 4, !tbaa !0
+  %dec1 = add nsw i32 %2, -1
+  store i32 %dec1, i32* @a, align 4, !tbaa !0
+  %3 = load i32* @d, align 4, !tbaa !0
+  %sub2 = sub nsw i32 %dec1, %3
+  store i32 %sub2, i32* @d, align 4, !tbaa !0
+  %4 = load i32* @a, align 4, !tbaa !0
+  %dec3 = add nsw i32 %4, -1
+  store i32 %dec3, i32* @a, align 4, !tbaa !0
+  %5 = load i32* @d, align 4, !tbaa !0
+  %sub4 = sub nsw i32 %dec3, %5
+  store i32 %sub4, i32* @d, align 4, !tbaa !0
+  %6 = load i32* @a, align 4, !tbaa !0
+  %dec5 = add nsw i32 %6, -1
+  store i32 %dec5, i32* @a, align 4, !tbaa !0
+  %7 = load i32* @d, align 4, !tbaa !0
+  %sub6 = sub nsw i32 %dec5, %7
+  store i32 %sub6, i32* @d, align 4, !tbaa !0
+  %8 = load i32* @a, align 4, !tbaa !0
+  %dec7 = add nsw i32 %8, -1
+  store i32 %dec7, i32* @a, align 4, !tbaa !0
+  %9 = load i32* @d, align 4, !tbaa !0
+  %sub8 = sub nsw i32 %dec7, %9
+  store i32 %sub8, i32* @d, align 4, !tbaa !0
+  ret i32 0
+}
+
+define i32 @fn1() nounwind uwtable ssp {
+entry:
+  %call = call i32 @fn2()
+  ret i32 %call
+}
+
+!0 = metadata !{metadata !"int", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA"}
diff --git a/test/Transforms/SimplifyLibCalls/floor.ll b/test/Transforms/SimplifyLibCalls/floor.ll
index 8780e32e0a0c..03dcdf585f9a 100644
--- a/test/Transforms/SimplifyLibCalls/floor.ll
+++ b/test/Transforms/SimplifyLibCalls/floor.ll
@@ -1,16 +1,31 @@
-; RUN: opt < %s -simplify-libcalls -S > %t
-; RUN: not grep {call.*floor(} %t
-; RUN: grep {call.*floorf(} %t
-; RUN: not grep {call.*ceil(} %t
-; RUN: grep {call.*ceilf(} %t
-; RUN: not grep {call.*nearbyint(} %t
-; RUN: grep {call.*nearbyintf(} %t
-; XFAIL: sparc
+; RUN: opt < %s -simplify-libcalls -S -mtriple "i386-pc-linux" | FileCheck -check-prefix=DO-SIMPLIFY %s
+; RUN: opt < %s -simplify-libcalls -S -mtriple "i386-pc-win32" | FileCheck -check-prefix=DONT-SIMPLIFY %s
+; RUN: opt < %s -simplify-libcalls -S -mtriple "x86_64-pc-win32" | FileCheck -check-prefix=C89-SIMPLIFY %s
+; RUN: opt < %s -simplify-libcalls -S -mtriple "i386-pc-mingw32" | FileCheck -check-prefix=DO-SIMPLIFY %s
+; RUN: opt < %s -simplify-libcalls -S -mtriple "x86_64-pc-mingw32" | FileCheck -check-prefix=DO-SIMPLIFY %s
+; RUN: opt < %s -simplify-libcalls -S -mtriple "sparc-sun-solaris" | FileCheck -check-prefix=DO-SIMPLIFY %s
+
+; DO-SIMPLIFY: call float @floorf(
+; DO-SIMPLIFY: call float @ceilf(
+; DO-SIMPLIFY: call float @roundf(
+; DO-SIMPLIFY: call float @nearbyintf(
+
+; C89-SIMPLIFY: call float @floorf(
+; C89-SIMPLIFY: call float @ceilf(
+; C89-SIMPLIFY: call double @round(
+; C89-SIMPLIFY: call double @nearbyint(
+
+; DONT-SIMPLIFY: call double @floor(
+; DONT-SIMPLIFY: call double @ceil(
+; DONT-SIMPLIFY: call double @round(
+; DONT-SIMPLIFY: call double @nearbyint(
 
 declare double @floor(double)
 
 declare double @ceil(double)
 
+declare double @round(double)
+
 declare double @nearbyint(double)
 
 define float @test_floor(float %C) {
@@ -29,8 +44,14 @@ define float @test_ceil(float %C) {
 	ret float %F
 }
 
-; PR8466
-; XFAIL: win32
+define float @test_round(float %C) {
+	%D = fpext float %C to double		; <double> [#uses=1]
+	; --> roundf
+        %E = call double @round( double %D )		; <double> [#uses=1]
+	%F = fptrunc double %E to float		; <float> [#uses=1]
+	ret float %F
+}
+
 define float @test_nearbyint(float %C) {
 	%D = fpext float %C to double		; <double> [#uses=1]
 	; --> nearbyintf
diff --git a/test/Transforms/SimplifyLibCalls/win-math.ll b/test/Transforms/SimplifyLibCalls/win-math.ll
new file mode 100644
index 000000000000..367e5b80721c
--- /dev/null
+++ b/test/Transforms/SimplifyLibCalls/win-math.ll
@@ -0,0 +1,275 @@
+; RUN: opt -O2 -S -mtriple=i386-pc-win32 < %s | FileCheck %s -check-prefix=WIN32
+; RUN: opt -O2 -S -mtriple=x86_64-pc-win32 < %s | FileCheck %s -check-prefix=WIN64
+; RUN: opt -O2 -S -mtriple=i386-pc-mingw32 < %s | FileCheck %s -check-prefix=MINGW32
+; RUN: opt -O2 -S -mtriple=x86_64-pc-mingw32 < %s | FileCheck %s -check-prefix=MINGW64
+
+; x86 win32 msvcrt does not provide entry points for single-precision libm.
+; x86-64 win32 msvcrt does (except for fabsf)
+; msvcrt does not provide C99 math, but mingw32 does.
+
+declare double @acos(double %x)
+define float @float_acos(float %x) nounwind readnone {
+; WIN32: @float_acos
+; WIN32-NOT: float @acosf
+; WIN32: double @acos
+    %1 = fpext float %x to double
+    %2 = call double @acos(double %1)
+    %3 = fptrunc double %2 to float
+    ret float %3
+}
+
+declare double @asin(double %x)
+define float @float_asin(float %x) nounwind readnone {
+; WIN32: @float_asin
+; WIN32-NOT: float @asinf
+; WIN32: double @asin
+    %1 = fpext float %x to double
+    %2 = call double @asin(double %1)
+    %3 = fptrunc double %2 to float
+    ret float %3
+}
+
+declare double @atan(double %x)
+define float @float_atan(float %x) nounwind readnone {
+; WIN32: @float_atan
+; WIN32-NOT: float @atanf
+; WIN32: double @atan
+    %1 = fpext float %x to double
+    %2 = call double @atan(double %1)
+    %3 = fptrunc double %2 to float
+    ret float %3
+}
+
+declare double @atan2(double %x, double %y)
+define float @float_atan2(float %x, float %y) nounwind readnone {
+; WIN32: @float_atan2
+; WIN32-NOT: float @atan2f
+; WIN32: double @atan2
+    %1 = fpext float %x to double
+    %2 = fpext float %y to double
+    %3 = call double @atan2(double %1, double %2)
+    %4 = fptrunc double %3 to float
+    ret float %4
+}
+
+declare double @ceil(double %x)
+define float @float_ceil(float %x) nounwind readnone {
+; WIN32: @float_ceil
+; WIN32-NOT: float @ceilf
+; WIN32: double @ceil
+; WIN64: @float_ceil
+; WIN64: float @ceilf
+; WIN64-NOT: double @ceil
+; MINGW32: @float_ceil
+; MINGW32: float @ceilf
+; MINGW32-NOT: double @ceil
+; MINGW64: @float_ceil
+; MINGW64: float @ceilf
+; MINGW64-NOT: double @ceil
+    %1 = fpext float %x to double
+    %2 = call double @ceil(double %1)
+    %3 = fptrunc double %2 to float
+    ret float %3
+}
+
+declare double @_copysign(double %x)
+define float @float_copysign(float %x) nounwind readnone {
+; WIN32: @float_copysign
+; WIN32-NOT: float @copysignf
+; WIN32-NOT: float @_copysignf
+; WIN32: double @_copysign
+    %1 = fpext float %x to double
+    %2 = call double @_copysign(double %1)
+    %3 = fptrunc double %2 to float
+    ret float %3
+}
+
+declare double @cos(double %x)
+define float @float_cos(float %x) nounwind readnone {
+; WIN32: @float_cos
+; WIN32-NOT: float @cosf
+; WIN32: double @cos
+    %1 = fpext float %x to double
+    %2 = call double @cos(double %1)
+    %3 = fptrunc double %2 to float
+    ret float %3
+}
+
+declare double @cosh(double %x)
+define float @float_cosh(float %x) nounwind readnone {
+; WIN32: @float_cosh
+; WIN32-NOT: float @coshf
+; WIN32: double @cosh
+    %1 = fpext float %x to double
+    %2 = call double @cosh(double %1)
+    %3 = fptrunc double %2 to float
+    ret float %3
+}
+
+declare double @exp(double %x, double %y)
+define float @float_exp(float %x, float %y) nounwind readnone {
+; WIN32: @float_exp
+; WIN32-NOT: float @expf
+; WIN32: double @exp
+    %1 = fpext float %x to double
+    %2 = fpext float %y to double
+    %3 = call double @exp(double %1, double %2)
+    %4 = fptrunc double %3 to float
+    ret float %4
+}
+
+declare double @fabs(double %x, double %y)
+define float @float_fabs(float %x, float %y) nounwind readnone {
+; WIN32: @float_fabs
+; WIN32-NOT: float @fabsf
+; WIN32: double @fabs
+; WIN64: @float_fabs
+; WIN64-NOT: float @fabsf
+; WIN64: double @fabs
+    %1 = fpext float %x to double
+    %2 = fpext float %y to double
+    %3 = call double @fabs(double %1, double %2)
+    %4 = fptrunc double %3 to float
+    ret float %4
+}
+
+declare double @floor(double %x)
+define float @float_floor(float %x) nounwind readnone {
+; WIN32: @float_floor
+; WIN32-NOT: float @floorf
+; WIN32: double @floor
+; WIN64: @float_floor
+; WIN64: float @floorf
+; WIN64-NOT: double @floor
+; MINGW32: @float_floor
+; MINGW32: float @floorf
+; MINGW32-NOT: double @floor
+; MINGW64: @float_floor
+; MINGW64: float @floorf
+; MINGW64-NOT: double @floor
+    %1 = fpext float %x to double
+    %2 = call double @floor(double %1)
+    %3 = fptrunc double %2 to float
+    ret float %3
+}
+
+declare double @fmod(double %x, double %y)
+define float @float_fmod(float %x, float %y) nounwind readnone {
+; WIN32: @float_fmod
+; WIN32-NOT: float @fmodf
+; WIN32: double @fmod
+    %1 = fpext float %x to double
+    %2 = fpext float %y to double
+    %3 = call double @fmod(double %1, double %2)
+    %4 = fptrunc double %3 to float
+    ret float %4
+}
+
+declare double @log(double %x)
+define float @float_log(float %x) nounwind readnone {
+; WIN32: @float_log
+; WIN32-NOT: float @logf
+; WIN32: double @log
+    %1 = fpext float %x to double
+    %2 = call double @log(double %1)
+    %3 = fptrunc double %2 to float
+    ret float %3
+}
+
+declare double @pow(double %x, double %y)
+define float @float_pow(float %x, float %y) nounwind readnone {
+; WIN32: @float_pow
+; WIN32-NOT: float @powf
+; WIN32: double @pow
+    %1 = fpext float %x to double
+    %2 = fpext float %y to double
+    %3 = call double @pow(double %1, double %2)
+    %4 = fptrunc double %3 to float
+    ret float %4
+}
+
+declare double @sin(double %x)
+define float @float_sin(float %x) nounwind readnone {
+; WIN32: @float_sin
+; WIN32-NOT: float @sinf
+; WIN32: double @sin
+    %1 = fpext float %x to double
+    %2 = call double @sin(double %1)
+    %3 = fptrunc double %2 to float
+    ret float %3
+}
+
+declare double @sinh(double %x)
+define float @float_sinh(float %x) nounwind readnone {
+; WIN32: @float_sinh
+; WIN32-NOT: float @sinhf
+; WIN32: double @sinh
+    %1 = fpext float %x to double
+    %2 = call double @sinh(double %1)
+    %3 = fptrunc double %2 to float
+    ret float %3
+}
+
+declare double @sqrt(double %x)
+define float @float_sqrt(float %x) nounwind readnone {
+; WIN32: @float_sqrt
+; WIN32-NOT: float @sqrtf
+; WIN32: double @sqrt
+; WIN64: @float_sqrt
+; WIN64: float @sqrtf
+; WIN64-NOT: double @sqrt
+; MINGW32: @float_sqrt
+; MINGW32: float @sqrtf
+; MINGW32-NOT: double @sqrt
+; MINGW64: @float_sqrt
+; MINGW64: float @sqrtf
+; MINGW64-NOT: double @sqrt
+    %1 = fpext float %x to double
+    %2 = call double @sqrt(double %1)
+    %3 = fptrunc double %2 to float
+    ret float %3
+}
+
+declare double @tan(double %x)
+define float @float_tan(float %x) nounwind readnone {
+; WIN32: @float_tan
+; WIN32-NOT: float @tanf
+; WIN32: double @tan
+    %1 = fpext float %x to double
+    %2 = call double @tan(double %1)
+    %3 = fptrunc double %2 to float
+    ret float %3
+}
+
+declare double @tanh(double %x)
+define float @float_tanh(float %x) nounwind readnone {
+; WIN32: @float_tanh
+; WIN32-NOT: float @tanhf
+; WIN32: double @tanh
+    %1 = fpext float %x to double
+    %2 = call double @tanh(double %1)
+    %3 = fptrunc double %2 to float
+    ret float %3
+}
+
+; win32 does not have round; mingw32 does
+declare double @round(double %x)
+define float @float_round(float %x) nounwind readnone {
+; WIN32: @float_round
+; WIN32-NOT: float @roundf
+; WIN32: double @round
+; WIN64: @float_round
+; WIN64-NOT: float @roundf
+; WIN64: double @round
+; MINGW32: @float_round
+; MINGW32: float @roundf
+; MINGW32-NOT: double @round
+; MINGW64: @float_round
+; MINGW64: float @roundf
+; MINGW64-NOT: double @round
+    %1 = fpext float %x to double
+    %2 = call double @round(double %1)
+    %3 = fptrunc double %2 to float
+    ret float %3
+}
+
diff --git a/test/Verifier/fpaccuracy.ll b/test/Verifier/fpaccuracy.ll
deleted file mode 100644
index 2fefde09f188..000000000000
--- a/test/Verifier/fpaccuracy.ll
+++ /dev/null
@@ -1,31 +0,0 @@
-; RUN: not llvm-as < %s |& FileCheck %s
-
-define void @foo(i32 %i, float %f, <2 x float> %g) {
-  %s = add i32 %i, %i, !fpaccuracy !0
-; CHECK: fpaccuracy requires a floating point result!
-  %t = fadd float %f, %f, !fpaccuracy !1
-; CHECK: fpaccuracy takes one operand!
-  %u = fadd float %f, %f, !fpaccuracy !2
-; CHECK: fpaccuracy takes one operand!
-  %v = fadd float %f, %f, !fpaccuracy !3
-; CHECK: fpaccuracy ULPs not a floating point number!
-  %w = fadd float %f, %f, !fpaccuracy !0
-; Above line is correct.
-  %w2 = fadd <2 x float> %g, %g, !fpaccuracy !0
-; Above line is correct.
-  %x = fadd float %f, %f, !fpaccuracy !4
-; CHECK: fpaccuracy ULPs is negative!
-  %y = fadd float %f, %f, !fpaccuracy !5
-; CHECK: fpaccuracy ULPs is negative!
-  %z = fadd float %f, %f, !fpaccuracy !6
-; CHECK: fpaccuracy ULPs not a normal number!
-  ret void
-}
-
-!0 = metadata !{ float 1.0 }
-!1 = metadata !{ }
-!2 = metadata !{ float 1.0, float 1.0 }
-!3 = metadata !{ i32 1 }
-!4 = metadata !{ float -1.0 }
-!5 = metadata !{ float -0.0 }
-!6 = metadata !{ float 0x7FFFFFFF00000000 }
diff --git a/test/Verifier/fpmath.ll b/test/Verifier/fpmath.ll
new file mode 100644
index 000000000000..b764a63f0a4a
--- /dev/null
+++ b/test/Verifier/fpmath.ll
@@ -0,0 +1,31 @@
+; RUN: not llvm-as < %s |& FileCheck %s
+
+define void @fpmath1(i32 %i, float %f, <2 x float> %g) {
+  %s = add i32 %i, %i, !fpmath !0
+; CHECK: fpmath requires a floating point result!
+  %t = fadd float %f, %f, !fpmath !1
+; CHECK: fpmath takes one operand!
+  %u = fadd float %f, %f, !fpmath !2
+; CHECK: fpmath takes one operand!
+  %v = fadd float %f, %f, !fpmath !3
+; CHECK: invalid fpmath accuracy!
+  %w = fadd float %f, %f, !fpmath !0
+; Above line is correct.
+  %w2 = fadd <2 x float> %g, %g, !fpmath !0
+; Above line is correct.
+  %x = fadd float %f, %f, !fpmath !4
+; CHECK: fpmath accuracy not a positive number!
+  %y = fadd float %f, %f, !fpmath !5
+; CHECK: fpmath accuracy not a positive number!
+  %z = fadd float %f, %f, !fpmath !6
+; CHECK: fpmath accuracy not a positive number!
+  ret void
+}
+
+!0 = metadata !{ float 1.0 }
+!1 = metadata !{ }
+!2 = metadata !{ float 1.0, float 1.0 }
+!3 = metadata !{ i32 1 }
+!4 = metadata !{ float -1.0 }
+!5 = metadata !{ float 0.0 }
+!6 = metadata !{ float 0x7FFFFFFF00000000 }
diff --git a/test/lit.cfg b/test/lit.cfg
index c58935956a4f..d74bc7bcb58f 100644
--- a/test/lit.cfg
+++ b/test/lit.cfg
@@ -236,8 +236,13 @@ if loadable_module:
 
 # llc knows whether he is compiled with -DNDEBUG.
 import subprocess
-llc_cmd = subprocess.Popen([os.path.join(llvm_tools_dir, 'llc'), '-version'],
+try:
+    llc_cmd = subprocess.Popen([os.path.join(llvm_tools_dir, 'llc'), '-version'],
                            stdout = subprocess.PIPE)
+except OSError, why:
+    print "Could not find llc in " + llvm_tools_dir
+    exit(42)
+
 if re.search(r'with assertions', llc_cmd.stdout.read()):
     config.available_features.add('asserts')
 llc_cmd.wait()