diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2017-06-16 21:03:24 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-06-16 21:03:24 +0000 |
| commit | 7c7aba6e5fef47a01a136be655b0a92cfd7090f6 (patch) | |
| tree | 99ec531924f6078534b100ab9d7696abce848099 /test | |
| parent | 7ab83427af0f77b59941ceba41d509d7d097b065 (diff) | |
| download | src-7c7aba6e5fef47a01a136be655b0a92cfd7090f6.tar.gz src-7c7aba6e5fef47a01a136be655b0a92cfd7090f6.zip | |
Vendor import of llvm trunk r305575:vendor/llvm/llvm-trunk-r305575
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=320013
svn path=/vendor/llvm/llvm-trunk-r305575/; revision=320014; tag=vendor/llvm/llvm-trunk-r305575
Diffstat (limited to 'test')
213 files changed, 7865 insertions, 5620 deletions
diff --git a/test/Analysis/ScalarEvolution/limit-depth.ll b/test/Analysis/ScalarEvolution/limit-depth.ll new file mode 100644 index 000000000000..5a35bfefd20a --- /dev/null +++ b/test/Analysis/ScalarEvolution/limit-depth.ll @@ -0,0 +1,44 @@ +; RUN: opt -scalar-evolution-max-arith-depth=0 -analyze -scalar-evolution < %s | FileCheck %s + +; Check that depth set to 0 prevents getAddExpr and getMulExpr from making +; transformations in SCEV. We expect the result to be very straightforward. + +define void @test_add(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f) { +; CHECK-LABEL: @test_add +; CHECK: %s2 = add i32 %s1, %p3 +; CHECK-NEXT: --> (%a + %a + %b + %b + %c + %c + %d + %d + %e + %e + %f + %f) + %tmp0 = add i32 %a, %b + %tmp1 = add i32 %b, %c + %tmp2 = add i32 %c, %d + %tmp3 = add i32 %d, %e + %tmp4 = add i32 %e, %f + %tmp5 = add i32 %f, %a + + %p1 = add i32 %tmp0, %tmp3 + %p2 = add i32 %tmp1, %tmp4 + %p3 = add i32 %tmp2, %tmp5 + + %s1 = add i32 %p1, %p2 + %s2 = add i32 %s1, %p3 + ret void +} + +define void @test_mul(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f) { +; CHECK-LABEL: @test_mul +; CHECK: %s2 = mul i32 %s1, %p3 +; CHECK-NEXT: --> (2 * 3 * 4 * 5 * 6 * 7 * %a * %b * %c * %d * %e * %f) + %tmp0 = mul i32 %a, 2 + %tmp1 = mul i32 %b, 3 + %tmp2 = mul i32 %c, 4 + %tmp3 = mul i32 %d, 5 + %tmp4 = mul i32 %e, 6 + %tmp5 = mul i32 %f, 7 + + %p1 = mul i32 %tmp0, %tmp3 + %p2 = mul i32 %tmp1, %tmp4 + %p3 = mul i32 %tmp2, %tmp5 + + %s1 = mul i32 %p1, %p2 + %s2 = mul i32 %s1, %p3 + ret void +} diff --git a/test/Assembler/diexpression.ll b/test/Assembler/diexpression.ll index c2fa3ee14c23..39f4be70145a 100644 --- a/test/Assembler/diexpression.ll +++ b/test/Assembler/diexpression.ll @@ -1,18 +1,20 @@ ; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s ; RUN: verify-uselistorder %s -; CHECK: !named = !{!0, !1, !2, !3, !4, !5} -!named = !{!0, !1, !2, !3, !4, !5} +; CHECK: !named = !{!0, !1, !2, !3, !4, !5, !6} +!named = !{!0, !1, !2, !3, !4, !5, !6} ; CHECK: !0 = !DIExpression() ; CHECK-NEXT: !1 = !DIExpression(DW_OP_deref) -; CHECK-NEXT: !2 = !DIExpression(DW_OP_plus, 3) +; CHECK-NEXT: !2 = !DIExpression(DW_OP_constu, 3, DW_OP_plus) ; CHECK-NEXT: !3 = !DIExpression(DW_OP_LLVM_fragment, 3, 7) -; CHECK-NEXT: !4 = !DIExpression(DW_OP_deref, DW_OP_plus, 3, DW_OP_LLVM_fragment, 3, 7) +; CHECK-NEXT: !4 = !DIExpression(DW_OP_deref, DW_OP_plus_uconst, 3, DW_OP_LLVM_fragment, 3, 7) ; CHECK-NEXT: !5 = !DIExpression(DW_OP_constu, 2, DW_OP_swap, DW_OP_xderef) +; CHECK-NEXT: !6 = !DIExpression(DW_OP_plus_uconst, 3) !0 = !DIExpression() !1 = !DIExpression(DW_OP_deref) -!2 = !DIExpression(DW_OP_plus, 3) +!2 = !DIExpression(DW_OP_constu, 3, DW_OP_plus) !3 = !DIExpression(DW_OP_LLVM_fragment, 3, 7) -!4 = !DIExpression(DW_OP_deref, DW_OP_plus, 3, DW_OP_LLVM_fragment, 3, 7) +!4 = !DIExpression(DW_OP_deref, DW_OP_plus_uconst, 3, DW_OP_LLVM_fragment, 3, 7) !5 = !DIExpression(DW_OP_constu, 2, DW_OP_swap, DW_OP_xderef) +!6 = !DIExpression(DW_OP_plus_uconst, 3) diff --git a/test/Bitcode/DIExpression-deref.ll b/test/Bitcode/DIExpression-deref.ll index 3a161b8ee4d2..a03d6016523e 100644 --- a/test/Bitcode/DIExpression-deref.ll +++ b/test/Bitcode/DIExpression-deref.ll @@ -11,11 +11,11 @@ !5 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) ; DW_OP_deref should be moved to the back of the expression. ; -; CHECK: !DIExpression(DW_OP_plus, 0, DW_OP_deref, DW_OP_LLVM_fragment, 8, 32) +; CHECK: !DIExpression(DW_OP_plus_uconst, 0, DW_OP_deref, DW_OP_LLVM_fragment, 8, 32) !6 = !DIExpression(DW_OP_deref, DW_OP_plus, 0, DW_OP_LLVM_fragment, 8, 32) -; CHECK: !DIExpression(DW_OP_plus, 0, DW_OP_deref) +; CHECK: !DIExpression(DW_OP_plus_uconst, 0, DW_OP_deref) !7 = !DIExpression(DW_OP_deref, DW_OP_plus, 0) -; CHECK: !DIExpression(DW_OP_plus, 1, DW_OP_deref) +; CHECK: !DIExpression(DW_OP_plus_uconst, 1, DW_OP_deref) !8 = !DIExpression(DW_OP_plus, 1, DW_OP_deref) ; CHECK: !DIExpression(DW_OP_deref) !9 = !DIExpression(DW_OP_deref) diff --git a/test/Bitcode/DIExpression-minus-upgrade.ll b/test/Bitcode/DIExpression-minus-upgrade.ll new file mode 100644 index 000000000000..1f26eba6f98c --- /dev/null +++ b/test/Bitcode/DIExpression-minus-upgrade.ll @@ -0,0 +1,16 @@ +; RUN: llvm-dis -o - %s.bc | FileCheck %s + +!llvm.dbg.cu = !{!1} +!llvm.module.flags = !{!8, !9} + +!0 = distinct !DIGlobalVariable(name: "g", scope: !1, file: !2, line: 1, type: !5, isLocal: false, isDefinition: true) +!1 = distinct !DICompileUnit(language: DW_LANG_C99, file: !2, producer: "clang (llvm/trunk 304286)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !3, globals: !4) +!2 = !DIFile(filename: "a.c", directory: "/") +!3 = !{} +!4 = !{!7} +!5 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +; CHECK: !DIExpression(DW_OP_constu, 42, DW_OP_minus) +!6 = !DIExpression(DW_OP_minus, 42) +!7 = !DIGlobalVariableExpression(var: !0, expr: !6) +!8 = !{i32 2, !"Dwarf Version", i32 4} +!9 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/test/Bitcode/DIExpression-minus-upgrade.ll.bc b/test/Bitcode/DIExpression-minus-upgrade.ll.bc Binary files differnew file mode 100644 index 000000000000..354ba6454c3f --- /dev/null +++ b/test/Bitcode/DIExpression-minus-upgrade.ll.bc diff --git a/test/Bitcode/DIGlobalVariableExpression.ll b/test/Bitcode/DIGlobalVariableExpression.ll index f6796bbdb7a0..31c3fda1b00a 100644 --- a/test/Bitcode/DIGlobalVariableExpression.ll +++ b/test/Bitcode/DIGlobalVariableExpression.ll @@ -14,7 +14,7 @@ ; CHECK: ![[HVAR:[0-9]+]] = distinct !DIGlobalVariable(name: "h", ; CHECK: ![[IMPORTS]] = !{![[CIMPORT:[0-9]+]]} ; CHECK: ![[CIMPORT]] = !DIImportedEntity({{.*}}entity: ![[HVAR]] -; CHECK: ![[GEXPR]] = !DIExpression(DW_OP_plus, 1) +; CHECK: ![[GEXPR]] = !DIExpression(DW_OP_plus_uconst, 1) ; CHECK: ![[H]] = {{.*}}!DIGlobalVariableExpression(var: ![[HVAR]]) @g = common global i32 0, align 4, !dbg !0 diff --git a/test/Bitcode/upgrade-linker-options.ll b/test/Bitcode/upgrade-linker-options.ll new file mode 100644 index 000000000000..6c874fa81e64 --- /dev/null +++ b/test/Bitcode/upgrade-linker-options.ll @@ -0,0 +1,15 @@ +; RUN: llvm-as -disable-verify < %s | llvm-dis | FileCheck %s +; RUN: not llvm-as < %s 2>&1 | FileCheck --check-prefix=ERROR %s + +; CHECK: !llvm.linker.options = !{!2, !3} +; CHECK: !2 = !{!"/DEFAULTLIB:libcmtd.lib"} +; CHECK: !3 = !{!"/DEFAULTLIB:oldnames.lib"} + +; ERROR: 'Linker Options' named metadata no longer supported + +!0 = !{i32 6, !"Linker Options", !1} +!1 = !{!2, !3} +!2 = !{!"/DEFAULTLIB:libcmtd.lib"} +!3 = !{!"/DEFAULTLIB:oldnames.lib"} + +!llvm.module.flags = !{!0} diff --git a/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir b/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir index c806b4a7060d..ce913d211ae2 100644 --- a/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir +++ b/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir @@ -53,9 +53,7 @@ body: | ; CHECK: %7(<2 x s32>) = G_LOAD %0(p0) :: (load 8 from %ir.addr) %7(<2 x s32>) = G_LOAD %0(p0) :: (load 8 from %ir.addr) - ; CHECK: [[OFFSET0:%[0-9]+]](s64) = G_CONSTANT i64 0 - ; CHECK: [[GEP0:%[0-9]+]](p0) = G_GEP %0, [[OFFSET0]](s64) - ; CHECK: [[LOAD0:%[0-9]+]](s64) = G_LOAD [[GEP0]](p0) :: (load 16 from %ir.addr) + ; CHECK: [[LOAD0:%[0-9]+]](s64) = G_LOAD %0(p0) :: (load 16 from %ir.addr) ; CHECK: [[OFFSET1:%[0-9]+]](s64) = G_CONSTANT i64 8 ; CHECK: [[GEP1:%[0-9]+]](p0) = G_GEP %0, [[OFFSET1]](s64) ; CHECK: [[LOAD1:%[0-9]+]](s64) = G_LOAD [[GEP1]](p0) :: (load 16 from %ir.addr) @@ -105,9 +103,7 @@ body: | ; CHECK: G_STORE %0(p0), %0(p0) :: (store 8 into %ir.addr) G_STORE %0(p0), %0(p0) :: (store 8 into %ir.addr) - ; CHECK: [[OFFSET0:%[0-9]+]](s64) = G_CONSTANT i64 0 - ; CHECK: [[GEP0:%[0-9]+]](p0) = G_GEP %0, [[OFFSET0]](s64) - ; CHECK: G_STORE %5(s64), [[GEP0]](p0) :: (store 16 into %ir.addr) + ; CHECK: G_STORE %5(s64), %0(p0) :: (store 16 into %ir.addr) ; CHECK: [[OFFSET1:%[0-9]+]](s64) = G_CONSTANT i64 8 ; CHECK: [[GEP1:%[0-9]+]](p0) = G_GEP %0, [[OFFSET1]](s64) ; CHECK: G_STORE %6(s64), [[GEP1]](p0) :: (store 16 into %ir.addr) diff --git a/test/CodeGen/AArch64/arm64-sincos.ll b/test/CodeGen/AArch64/arm64-sincos.ll index 06157b2580c4..98876dbe87b0 100644 --- a/test/CodeGen/AArch64/arm64-sincos.ll +++ b/test/CodeGen/AArch64/arm64-sincos.ll @@ -1,7 +1,9 @@ ; RUN: llc < %s -mtriple=arm64-apple-ios7 | FileCheck %s --check-prefix CHECK-IOS ; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s --check-prefix CHECK-LINUX -; Combine sin / cos into a single call. +; Combine sin / cos into a single call unless they may write errno (as +; captured by readnone attrbiute, controlled by clang -fmath-errno +; setting). ; rdar://12856873 define float @test1(float %x) nounwind { @@ -11,11 +13,26 @@ entry: ; CHECK-IOS: fadd s0, s0, s1 ; CHECK-LINUX-LABEL: test1: +; CHECK-LINUX: bl sincosf + + %call = tail call float @sinf(float %x) readnone + %call1 = tail call float @cosf(float %x) readnone + %add = fadd float %call, %call1 + ret float %add +} + +define float @test1_errno(float %x) nounwind { +entry: +; CHECK-IOS-LABEL: test1_errno: +; CHECK-IOS: bl _sinf +; CHECK-IOS: bl _cosf + +; CHECK-LINUX-LABEL: test1_errno: ; CHECK-LINUX: bl sinf ; CHECK-LINUX: bl cosf - %call = tail call float @sinf(float %x) nounwind readnone - %call1 = tail call float @cosf(float %x) nounwind readnone + %call = tail call float @sinf(float %x) + %call1 = tail call float @cosf(float %x) %add = fadd float %call, %call1 ret float %add } @@ -27,16 +44,31 @@ entry: ; CHECK-IOS: fadd d0, d0, d1 ; CHECK-LINUX-LABEL: test2: +; CHECK-LINUX: bl sincos + + %call = tail call double @sin(double %x) readnone + %call1 = tail call double @cos(double %x) readnone + %add = fadd double %call, %call1 + ret double %add +} + +define double @test2_errno(double %x) nounwind { +entry: +; CHECK-IOS-LABEL: test2_errno: +; CHECK-IOS: bl _sin +; CHECK-IOS: bl _cos + +; CHECK-LINUX-LABEL: test2_errno: ; CHECK-LINUX: bl sin ; CHECK-LINUX: bl cos - %call = tail call double @sin(double %x) nounwind readnone - %call1 = tail call double @cos(double %x) nounwind readnone + %call = tail call double @sin(double %x) + %call1 = tail call double @cos(double %x) %add = fadd double %call, %call1 ret double %add } -declare float @sinf(float) readonly -declare double @sin(double) readonly -declare float @cosf(float) readonly -declare double @cos(double) readonly +declare float @sinf(float) +declare double @sin(double) +declare float @cosf(float) +declare double @cos(double) diff --git a/test/CodeGen/AArch64/fast-isel-sp-adjust.ll b/test/CodeGen/AArch64/fast-isel-sp-adjust.ll new file mode 100644 index 000000000000..9201d1be6a9c --- /dev/null +++ b/test/CodeGen/AArch64/fast-isel-sp-adjust.ll @@ -0,0 +1,288 @@ +; RUN: llc -O0 -mtriple=aarch64-apple-ios -o - %s | FileCheck %s +; RUN: not llc -O0 -mtriple=aarch64-apple-ios -o /dev/null -fast-isel-abort=3 %s 2> %t +; RUN: FileCheck %s --check-prefix=CHECK-ERRORS < %t + +; The issue here is that FastISel cannot emit an ADDrr where one of the inputs +; is SP. This only ever crops up with function calls, and then only if the +; argument is at an offset > 2^12 * size from SP. + +; If FastISel ever starts coping with this and emits an "add xD, sp, xM" it's +; critical to check the encoding as well as the textual assembly. An ADDXrs with +; SP as an operand will still print with SP, but will actually mean XZR. + +; CHECK-ERRORS: LLVM ERROR: FastISel missed call + +; CHECK-LABEL: foo: +; CHECK-DAG: mov x[[SP:[0-9]+]], sp +; CHECK-DAG: mov [[TMP:w[0-9]+]], #4104 +; CHECK: mov w[[OFFSET:[0-9]+]], [[TMP]] +; CHECK: strb w0, [x[[SP]], x[[OFFSET]]] + +define void @foo(i8 %in) { + call void @bar(i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, ; All regs gone. + i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 32 + i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 64 + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 128 + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 256 + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 512 + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 1024 + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 2048 + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, + i64 undef, i64 undef, i64 undef, i64 undef, ; sp + 4096 + i64 undef, ; sp + 4104 (i.e. not uimm12 or uimm12 << 12). + i8 %in) + ret void +} + +declare void @bar(i64, i64, i64, i64, + i64, i64, i64, i64, ; All regs gone. + i64, i64, i64, i64, ; sp + 32 + i64, i64, i64, i64, ; sp + 64 + i64, i64, i64, i64, + i64, i64, i64, i64, ; sp + 128 + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, ; sp + 256 + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, ; sp + 512 + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, ; sp + 1024 + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, ; sp + 2048 + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, + i64, i64, i64, i64, ; sp + 4096 + i64, + i8) diff --git a/test/CodeGen/AArch64/misched-fusion-aes.ll b/test/CodeGen/AArch64/misched-fusion-aes.ll index bd7c69c910c0..8ee4dbcee52b 100644 --- a/test/CodeGen/AArch64/misched-fusion-aes.ll +++ b/test/CodeGen/AArch64/misched-fusion-aes.ll @@ -1,7 +1,9 @@ -; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a53 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKCORTEX -; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKCORTEX -; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKCORTEX -; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a73 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKCORTEX +; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=+fuse-aes,+crypto | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEALLPAIRS +; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=generic -mattr=+crypto | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEALLPAIRS +; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a53 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEALLPAIRS +; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEALLPAIRS +; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEALLPAIRS +; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a73 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSEALLPAIRS ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKM1 declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %d, <16 x i8> %k) @@ -74,22 +76,23 @@ define void @aesea(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d, ret void ; CHECK-LABEL: aesea: -; CHECKCORTEX: aese [[VA:v[0-7].16b]], {{v[0-7].16b}} -; CHECKCORTEX-NEXT: aesmc {{v[0-7].16b}}, [[VA]] -; CHECKCORTEX: aese [[VB:v[0-7].16b]], {{v[0-7].16b}} -; CHECKCORTEX-NEXT: aesmc {{v[0-7].16b}}, [[VB]] -; CHECKCORTEX: aese [[VC:v[0-7].16b]], {{v[0-7].16b}} -; CHECKCORTEX-NEXT: aesmc {{v[0-7].16b}}, [[VC]] -; CHECKCORTEX: aese [[VD:v[0-7].16b]], {{v[0-7].16b}} -; CHECKCORTEX-NEXT: aesmc {{v[0-7].16b}}, [[VD]] -; CHECKCORTEX: aese [[VE:v[0-7].16b]], {{v[0-7].16b}} -; CHECKCORTEX-NEXT: aesmc {{v[0-7].16b}}, [[VE]] -; CHECKCORTEX: aese [[VF:v[0-7].16b]], {{v[0-7].16b}} -; CHECKCORTEX-NEXT: aesmc {{v[0-7].16b}}, [[VF]] -; CHECKCORTEX: aese [[VG:v[0-7].16b]], {{v[0-7].16b}} -; CHECKCORTEX-NEXT: aesmc {{v[0-7].16b}}, [[VG]] -; CHECKCORTEX: aese [[VH:v[0-7].16b]], {{v[0-7].16b}} -; CHECKCORTEX-NEXT: aesmc {{v[0-7].16b}}, [[VH]] +; CHECKFUSEALLPAIRS: aese [[VA:v[0-7].16b]], {{v[0-7].16b}} +; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VA]] +; CHECKFUSEALLPAIRS: aese [[VB:v[0-7].16b]], {{v[0-7].16b}} +; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VB]] +; CHECKFUSEALLPAIRS: aese [[VC:v[0-7].16b]], {{v[0-7].16b}} +; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VC]] +; CHECKFUSEALLPAIRS: aese [[VD:v[0-7].16b]], {{v[0-7].16b}} +; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VD]] +; CHECKFUSEALLPAIRS: aese [[VE:v[0-7].16b]], {{v[0-7].16b}} +; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VE]] +; CHECKFUSEALLPAIRS: aese [[VF:v[0-7].16b]], {{v[0-7].16b}} +; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VF]] +; CHECKFUSEALLPAIRS: aese [[VG:v[0-7].16b]], {{v[0-7].16b}} +; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VG]] +; CHECKFUSEALLPAIRS: aese [[VH:v[0-7].16b]], {{v[0-7].16b}} +; CHECKFUSEALLPAIRS-NEXT: aesmc {{v[0-7].16b}}, [[VH]] +; CHECKFUSEALLPAIRS-NOT: aesmc ; CHECKM1: aese [[VA:v[0-7].16b]], {{v[0-7].16b}} ; CHECKM1-NEXT: aesmc {{v[0-7].16b}}, [[VA]] @@ -175,22 +178,23 @@ define void @aesda(<16 x i8>* %a0, <16 x i8>* %b0, <16 x i8>* %c0, <16 x i8> %d, ret void ; CHECK-LABEL: aesda: -; CHECKCORTEX: aesd [[VA:v[0-7].16b]], {{v[0-7].16b}} -; CHECKCORTEX-NEXT: aesimc {{v[0-7].16b}}, [[VA]] -; CHECKCORTEX: aesd [[VB:v[0-7].16b]], {{v[0-7].16b}} -; CHECKCORTEX-NEXT: aesimc {{v[0-7].16b}}, [[VB]] -; CHECKCORTEX: aesd [[VC:v[0-7].16b]], {{v[0-7].16b}} -; CHECKCORTEX-NEXT: aesimc {{v[0-7].16b}}, [[VC]] -; CHECKCORTEX: aesd [[VD:v[0-7].16b]], {{v[0-7].16b}} -; CHECKCORTEX-NEXT: aesimc {{v[0-7].16b}}, [[VD]] -; CHECKCORTEX: aesd [[VE:v[0-7].16b]], {{v[0-7].16b}} -; CHECKCORTEX-NEXT: aesimc {{v[0-7].16b}}, [[VE]] -; CHECKCORTEX: aesd [[VF:v[0-7].16b]], {{v[0-7].16b}} -; CHECKCORTEX-NEXT: aesimc {{v[0-7].16b}}, [[VF]] -; CHECKCORTEX: aesd [[VG:v[0-7].16b]], {{v[0-7].16b}} -; CHECKCORTEX-NEXT: aesimc {{v[0-7].16b}}, [[VG]] -; CHECKCORTEX: aesd [[VH:v[0-7].16b]], {{v[0-7].16b}} -; CHECKCORTEX-NEXT: aesimc {{v[0-7].16b}}, [[VH]] +; CHECKFUSEALLPAIRS: aesd [[VA:v[0-7].16b]], {{v[0-7].16b}} +; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VA]] +; CHECKFUSEALLPAIRS: aesd [[VB:v[0-7].16b]], {{v[0-7].16b}} +; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VB]] +; CHECKFUSEALLPAIRS: aesd [[VC:v[0-7].16b]], {{v[0-7].16b}} +; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VC]] +; CHECKFUSEALLPAIRS: aesd [[VD:v[0-7].16b]], {{v[0-7].16b}} +; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VD]] +; CHECKFUSEALLPAIRS: aesd [[VE:v[0-7].16b]], {{v[0-7].16b}} +; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VE]] +; CHECKFUSEALLPAIRS: aesd [[VF:v[0-7].16b]], {{v[0-7].16b}} +; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VF]] +; CHECKFUSEALLPAIRS: aesd [[VG:v[0-7].16b]], {{v[0-7].16b}} +; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VG]] +; CHECKFUSEALLPAIRS: aesd [[VH:v[0-7].16b]], {{v[0-7].16b}} +; CHECKFUSEALLPAIRS-NEXT: aesimc {{v[0-7].16b}}, [[VH]] +; CHECKFUSEALLPAIRS-NOT: aesimc ; CHECKM1: aesd [[VA:v[0-7].16b]], {{v[0-7].16b}} ; CHECKM1-NEXT: aesimc {{v[0-7].16b}}, [[VA]] @@ -236,4 +240,5 @@ entry: ; CHECK-NEXT: aesmc {{v[0-7].16b}}, [[VA]] ; CHECK: aese [[VB:v[0-7].16b]], {{v[0-7].16b}} ; CHECK-NEXT: aesmc {{v[0-7].16b}}, [[VB]] +; CHECK-NOT: aesmc } diff --git a/test/CodeGen/AArch64/sincos-expansion.ll b/test/CodeGen/AArch64/sincos-expansion.ll index c3a172dfb427..41ee40378b4f 100644 --- a/test/CodeGen/AArch64/sincos-expansion.ll +++ b/test/CodeGen/AArch64/sincos-expansion.ll @@ -1,8 +1,18 @@ ; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs -o - %s | FileCheck %s define float @test_sincos_f32(float %f) { +; CHECK-LABEL: test_sincos_f32: %sin = call float @sinf(float %f) readnone %cos = call float @cosf(float %f) readnone +; CHECK: bl sincosf + %val = fadd float %sin, %cos + ret float %val +} + +define float @test_sincos_f32_errno(float %f) { +; CHECK-LABEL: test_sincos_f32_errno: + %sin = call float @sinf(float %f) + %cos = call float @cosf(float %f) ; CHECK: bl sinf ; CHECK: bl cosf %val = fadd float %sin, %cos @@ -10,26 +20,46 @@ define float @test_sincos_f32(float %f) { } define double @test_sincos_f64(double %f) { +; CHECK-LABEL: test_sincos_f64: %sin = call double @sin(double %f) readnone %cos = call double @cos(double %f) readnone %val = fadd double %sin, %cos +; CHECK: bl sincos + ret double %val +} + +define double @test_sincos_f64_errno(double %f) { +; CHECK-LABEL: test_sincos_f64_errno: + %sin = call double @sin(double %f) + %cos = call double @cos(double %f) + %val = fadd double %sin, %cos ; CHECK: bl sin ; CHECK: bl cos ret double %val } define fp128 @test_sincos_f128(fp128 %f) { +; CHECK-LABEL: test_sincos_f128: %sin = call fp128 @sinl(fp128 %f) readnone %cos = call fp128 @cosl(fp128 %f) readnone %val = fadd fp128 %sin, %cos +; CHECK: bl sincosl + ret fp128 %val +} + +define fp128 @test_sincos_f128_errno(fp128 %f) { +; CHECK-LABEL: test_sincos_f128_errno: + %sin = call fp128 @sinl(fp128 %f) + %cos = call fp128 @cosl(fp128 %f) + %val = fadd fp128 %sin, %cos ; CHECK: bl sinl ; CHECK: bl cosl ret fp128 %val } -declare float @sinf(float) readonly -declare double @sin(double) readonly -declare fp128 @sinl(fp128) readonly -declare float @cosf(float) readonly -declare double @cos(double) readonly -declare fp128 @cosl(fp128) readonly +declare float @sinf(float) +declare double @sin(double) +declare fp128 @sinl(fp128) +declare float @cosf(float) +declare double @cos(double) +declare fp128 @cosl(fp128) diff --git a/test/CodeGen/AArch64/swifterror.ll b/test/CodeGen/AArch64/swifterror.ll index 69bf3510cc5a..bc28f477c810 100644 --- a/test/CodeGen/AArch64/swifterror.ll +++ b/test/CodeGen/AArch64/swifterror.ll @@ -597,3 +597,30 @@ entry: tail call void @acallee(i8* null) ret void } + +declare swiftcc void @foo2(%swift_error** swifterror) + +; Make sure we properly assign registers during fast-isel. +; CHECK-O0-LABEL: testAssign +; CHECK-O0: mov [[TMP:x.*]], xzr +; CHECK-O0: mov x21, [[TMP]] +; CHECK-O0: bl _foo2 +; CHECK-O0: str x21, [s[[STK:.*]]] +; CHECK-O0: ldr x0, [s[[STK]]] + +; CHECK-APPLE-LABEL: testAssign +; CHECK-APPLE: mov x21, xzr +; CHECK-APPLE: bl _foo2 +; CHECK-APPLE: mov x0, x21 + +define swiftcc %swift_error* @testAssign(i8* %error_ref) { +entry: + %error_ptr = alloca swifterror %swift_error* + store %swift_error* null, %swift_error** %error_ptr + call swiftcc void @foo2(%swift_error** swifterror %error_ptr) + br label %a + +a: + %error = load %swift_error*, %swift_error** %error_ptr + ret %swift_error* %error +} diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir index 2a3d3887ed69..56a9e7022db9 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir @@ -14,7 +14,7 @@ regBankSelected: true # GCN: global_addrspace # GCN: [[PTR:%[0-9]+]] = COPY %vgpr0_vgpr1 -# GCN: FLAT_LOAD_DWORD [[PTR]], 0, 0 +# GCN: FLAT_LOAD_DWORD [[PTR]], 0, 0, 0 body: | bb.0: diff --git a/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir b/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir index 89be3bde94a8..ea435725bf25 100644 --- a/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir +++ b/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir @@ -15,7 +15,7 @@ regBankSelected: true # GCN: global_addrspace # GCN: [[PTR:%[0-9]+]] = COPY %vgpr0_vgpr1 # GCN: [[VAL:%[0-9]+]] = COPY %vgpr2 -# GCN: FLAT_STORE_DWORD [[PTR]], [[VAL]], 0, 0 +# GCN: FLAT_STORE_DWORD [[PTR]], [[VAL]], 0, 0, 0 body: | bb.0: diff --git a/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir b/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir new file mode 100644 index 000000000000..f10c896a7af6 --- /dev/null +++ b/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir @@ -0,0 +1,22 @@ +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s + +--- | + define void @test_add() { ret void } +... + +--- +name: test_add +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %vgpr0, %vgpr1 + ; CHECK-LABEL: name: test_add + ; CHECK: %2(s32) = G_ADD %0, %1 + + %0(s32) = COPY %vgpr0 + %1(s32) = COPY %vgpr1 + %2(s32) = G_ADD %0, %1 +... diff --git a/test/CodeGen/AMDGPU/always-uniform.ll b/test/CodeGen/AMDGPU/always-uniform.ll new file mode 100644 index 000000000000..4ba57fba81bc --- /dev/null +++ b/test/CodeGen/AMDGPU/always-uniform.ll @@ -0,0 +1,21 @@ +; RUN: llc -mtriple amdgcn-amdhsa -mcpu=fiji -amdgpu-scalarize-global-loads -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +declare i32 @llvm.amdgcn.workitem.id.x() +declare i32 @llvm.amdgcn.readfirstlane(i32) + +; GCN-LABEL: readfirstlane_uniform +; GCN: s_load_dwordx2 s{{\[}}[[IN_ADDR:[0-9]+]]:1{{\]}}, s[4:5], 0x0 +; GCN: v_readfirstlane_b32 s[[SCALAR:[0-9]+]], v0 +; GCN: s_add_u32 s[[LOAD_ADDR:[0-9]+]], s[[IN_ADDR]], s[[SCALAR]] +; GCN: s_load_dword s{{[0-9]+}}, s{{\[}}[[LOAD_ADDR]] + +define amdgpu_kernel void @readfirstlane_uniform(float addrspace(1)* noalias nocapture readonly, float addrspace(1)* noalias nocapture readonly) { + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() + %scalar = tail call i32 @llvm.amdgcn.readfirstlane(i32 %tid) + %idx = zext i32 %scalar to i64 + %gep0 = getelementptr inbounds float, float addrspace(1)* %0, i64 %idx + %val = load float, float addrspace(1)* %gep0, align 4 + %gep1 = getelementptr inbounds float, float addrspace(1)* %1, i64 10 + store float %val, float addrspace(1)* %gep1, align 4 + ret void +} diff --git a/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll b/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll index cbdcf6aeaf42..5dec3e35ab3d 100644 --- a/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll +++ b/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll @@ -1,12 +1,19 @@ -; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=bonaire < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-CI %s -; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-VI %s -; RUN: llc -march=amdgcn -mcpu=bonaire -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s +; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=bonaire < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-CI -check-prefix=OPT-CIVI %s +; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-VI -check-prefix=OPT-CIVI %s +; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-GFX9 %s +; RUN: llc -march=amdgcn -mcpu=bonaire -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=CIVI %s +; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=CIVI %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; OPT-LABEL: @test_no_sink_flat_small_offset_i32( -; OPT: getelementptr i32, i32 addrspace(4)* %in -; OPT: br i1 -; OPT-NOT: ptrtoint +; OPT-CIVI: getelementptr i32, i32 addrspace(4)* %in +; OPT-CIVI: br i1 +; OPT-CIVI-NOT: ptrtoint + +; OPT-GFX9: br +; OPT-GFX9: %sunkaddr = getelementptr i8, i8 addrspace(4)* %0, i64 28 +; OPT-GFX9: %1 = bitcast i8 addrspace(4)* %sunkaddr to i32 addrspace(4)* +; OPT-GFX9: load i32, i32 addrspace(4)* %1 ; GCN-LABEL: {{^}}test_no_sink_flat_small_offset_i32: ; GCN: flat_load_dword @@ -96,3 +103,105 @@ endif: done: ret void } + +; OPT-LABEL: @test_sink_flat_small_max_flat_offset( +; OPT-CIVI: %in.gep = getelementptr i8, i8 addrspace(4)* %in, i64 4095 +; OPT-CIVI: br +; OPT-CIVI-NOT: getelementptr +; OPT-CIVI: load i8, i8 addrspace(4)* %in.gep + +; OPT-GFX9: br +; OPT-GFX9: %sunkaddr = getelementptr i8, i8 addrspace(4)* %in, i64 4095 +; OPT-GFX9: load i8, i8 addrspace(4)* %sunkaddr + +; GCN-LABEL: {{^}}test_sink_flat_small_max_flat_offset: +; GFX9: flat_load_sbyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} offset:4095{{$}} +; CIVI: flat_load_sbyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]$}} +define amdgpu_kernel void @test_sink_flat_small_max_flat_offset(i32 addrspace(4)* %out, i8 addrspace(4)* %in) #1 { +entry: + %out.gep = getelementptr i32, i32 addrspace(4)* %out, i32 1024 + %in.gep = getelementptr i8, i8 addrspace(4)* %in, i64 4095 + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %tmp0 = icmp eq i32 %tid, 0 + br i1 %tmp0, label %endif, label %if + +if: + %tmp1 = load i8, i8 addrspace(4)* %in.gep + %tmp2 = sext i8 %tmp1 to i32 + br label %endif + +endif: + %x = phi i32 [ %tmp2, %if ], [ 0, %entry ] + store i32 %x, i32 addrspace(4)* %out.gep + br label %done + +done: + ret void +} + +; OPT-LABEL: @test_sink_flat_small_max_plus_1_flat_offset( +; OPT: %in.gep = getelementptr i8, i8 addrspace(4)* %in, i64 4096 +; OPT: br +; OPT-NOT: getelementptr +; OPT: load i8, i8 addrspace(4)* %in.gep + +; GCN-LABEL: {{^}}test_sink_flat_small_max_plus_1_flat_offset: +; GCN: flat_load_sbyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]$}} +define amdgpu_kernel void @test_sink_flat_small_max_plus_1_flat_offset(i32 addrspace(4)* %out, i8 addrspace(4)* %in) #1 { +entry: + %out.gep = getelementptr i32, i32 addrspace(4)* %out, i64 99999 + %in.gep = getelementptr i8, i8 addrspace(4)* %in, i64 4096 + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %tmp0 = icmp eq i32 %tid, 0 + br i1 %tmp0, label %endif, label %if + +if: + %tmp1 = load i8, i8 addrspace(4)* %in.gep + %tmp2 = sext i8 %tmp1 to i32 + br label %endif + +endif: + %x = phi i32 [ %tmp2, %if ], [ 0, %entry ] + store i32 %x, i32 addrspace(4)* %out.gep + br label %done + +done: + ret void +} + +; OPT-LABEL: @test_no_sink_flat_reg_offset( +; OPT: %in.gep = getelementptr i8, i8 addrspace(4)* %in, i64 %reg +; OPT: br + +; OPT-NOT: getelementptr +; OPT: load i8, i8 addrspace(4)* %in.gep + +; GCN-LABEL: {{^}}test_no_sink_flat_reg_offset: +; GCN: flat_load_sbyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]$}} +define amdgpu_kernel void @test_no_sink_flat_reg_offset(i32 addrspace(4)* %out, i8 addrspace(4)* %in, i64 %reg) #1 { +entry: + %out.gep = getelementptr i32, i32 addrspace(4)* %out, i32 1024 + %in.gep = getelementptr i8, i8 addrspace(4)* %in, i64 %reg + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %tmp0 = icmp eq i32 %tid, 0 + br i1 %tmp0, label %endif, label %if + +if: + %tmp1 = load i8, i8 addrspace(4)* %in.gep + %tmp2 = sext i8 %tmp1 to i32 + br label %endif + +endif: + %x = phi i32 [ %tmp2, %if ], [ 0, %entry ] + store i32 %x, i32 addrspace(4)* %out.gep + br label %done + +done: + ret void +} + +declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0 + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } +attributes #2 = { nounwind argmemonly } diff --git a/test/CodeGen/AMDGPU/code-object-metadata-kernel-debug-props.ll b/test/CodeGen/AMDGPU/code-object-metadata-kernel-debug-props.ll index 801029be8cb9..0796c24b3317 100644 --- a/test/CodeGen/AMDGPU/code-object-metadata-kernel-debug-props.ll +++ b/test/CodeGen/AMDGPU/code-object-metadata-kernel-debug-props.ll @@ -12,7 +12,9 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) ; CHECK: DebugProps: ; CHECK: DebuggerABIVersion: [ 1, 0 ] ; CHECK: ReservedNumVGPRs: 4 -; CHECK: ReservedFirstVGPR: 11 +; GFX700: ReservedFirstVGPR: 11 +; GFX800: ReservedFirstVGPR: 11 +; GFX9: ReservedFirstVGPR: 14 ; CHECK: PrivateSegmentBufferSGPR: 0 ; CHECK: WavefrontPrivateSegmentOffsetSGPR: 11 define amdgpu_kernel void @test(i32 addrspace(1)* %A) #0 !dbg !7 !kernel_arg_addr_space !12 !kernel_arg_access_qual !13 !kernel_arg_type !14 !kernel_arg_base_type !14 !kernel_arg_type_qual !15 { diff --git a/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir b/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir index bc992ed77ffd..62b47beb1251 100644 --- a/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir +++ b/test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir @@ -219,19 +219,19 @@ body: | %34 = V_MOV_B32_e32 63, implicit %exec %27 = V_AND_B32_e64 %26, %24, implicit %exec - FLAT_STORE_DWORD %37, %27, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %37, %27, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %28 = V_AND_B32_e64 %24, %26, implicit %exec - FLAT_STORE_DWORD %37, %28, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %37, %28, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %29 = V_AND_B32_e32 %26, %24, implicit %exec - FLAT_STORE_DWORD %37, %29, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %37, %29, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %30 = V_AND_B32_e64 %26, %26, implicit %exec - FLAT_STORE_DWORD %37, %30, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %37, %30, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %31 = V_AND_B32_e64 %34, %34, implicit %exec - FLAT_STORE_DWORD %37, %31, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %37, %31, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) S_ENDPGM @@ -407,34 +407,34 @@ body: | %27 = S_MOV_B32 -4 %11 = V_LSHLREV_B32_e64 12, %10, implicit %exec - FLAT_STORE_DWORD %20, %11, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %11, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %12 = V_LSHLREV_B32_e64 %7, 12, implicit %exec - FLAT_STORE_DWORD %20, %12, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %12, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %13 = V_LSHL_B32_e64 %7, 12, implicit %exec - FLAT_STORE_DWORD %20, %13, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %13, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %14 = V_LSHL_B32_e64 12, %7, implicit %exec - FLAT_STORE_DWORD %20, %14, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %14, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %15 = V_LSHL_B32_e64 12, %24, implicit %exec - FLAT_STORE_DWORD %20, %15, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %15, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %22 = V_LSHL_B32_e64 %6, 12, implicit %exec - FLAT_STORE_DWORD %20, %22, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %22, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %23 = V_LSHL_B32_e64 %6, 32, implicit %exec - FLAT_STORE_DWORD %20, %23, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %23, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %25 = V_LSHL_B32_e32 %6, %6, implicit %exec - FLAT_STORE_DWORD %20, %25, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %25, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %26 = V_LSHLREV_B32_e32 11, %24, implicit %exec - FLAT_STORE_DWORD %20, %26, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %26, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %28 = V_LSHL_B32_e32 %27, %6, implicit %exec - FLAT_STORE_DWORD %20, %28, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %28, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) S_ENDPGM @@ -615,34 +615,34 @@ body: | %35 = V_MOV_B32_e32 2, implicit %exec %11 = V_ASHRREV_I32_e64 8, %10, implicit %exec - FLAT_STORE_DWORD %20, %11, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %11, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %12 = V_ASHRREV_I32_e64 %8, %10, implicit %exec - FLAT_STORE_DWORD %20, %12, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %12, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %13 = V_ASHR_I32_e64 %7, 3, implicit %exec - FLAT_STORE_DWORD %20, %13, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %13, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %14 = V_ASHR_I32_e64 7, %32, implicit %exec - FLAT_STORE_DWORD %20, %14, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %14, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %15 = V_ASHR_I32_e64 %27, %24, implicit %exec - FLAT_STORE_DWORD %20, %15, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %15, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %22 = V_ASHR_I32_e64 %6, 4, implicit %exec - FLAT_STORE_DWORD %20, %22, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %22, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %23 = V_ASHR_I32_e64 %6, %33, implicit %exec - FLAT_STORE_DWORD %20, %23, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %23, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %25 = V_ASHR_I32_e32 %34, %34, implicit %exec - FLAT_STORE_DWORD %20, %25, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %25, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %26 = V_ASHRREV_I32_e32 11, %10, implicit %exec - FLAT_STORE_DWORD %20, %26, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %26, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %28 = V_ASHR_I32_e32 %27, %35, implicit %exec - FLAT_STORE_DWORD %20, %28, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %28, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) S_ENDPGM @@ -824,34 +824,34 @@ body: | %35 = V_MOV_B32_e32 2, implicit %exec %11 = V_LSHRREV_B32_e64 8, %10, implicit %exec - FLAT_STORE_DWORD %20, %11, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %11, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %12 = V_LSHRREV_B32_e64 %8, %10, implicit %exec - FLAT_STORE_DWORD %20, %12, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %12, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %13 = V_LSHR_B32_e64 %7, 3, implicit %exec - FLAT_STORE_DWORD %20, %13, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %13, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %14 = V_LSHR_B32_e64 7, %32, implicit %exec - FLAT_STORE_DWORD %20, %14, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %14, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %15 = V_LSHR_B32_e64 %27, %24, implicit %exec - FLAT_STORE_DWORD %20, %15, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %15, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %22 = V_LSHR_B32_e64 %6, 4, implicit %exec - FLAT_STORE_DWORD %20, %22, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %22, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %23 = V_LSHR_B32_e64 %6, %33, implicit %exec - FLAT_STORE_DWORD %20, %23, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %23, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %25 = V_LSHR_B32_e32 %34, %34, implicit %exec - FLAT_STORE_DWORD %20, %25, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %25, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %26 = V_LSHRREV_B32_e32 11, %10, implicit %exec - FLAT_STORE_DWORD %20, %26, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %26, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) %28 = V_LSHR_B32_e32 %27, %35, implicit %exec - FLAT_STORE_DWORD %20, %28, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) + FLAT_STORE_DWORD %20, %28, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store 4 into %ir.gep.out) S_ENDPGM diff --git a/test/CodeGen/AMDGPU/flat-address-space.ll b/test/CodeGen/AMDGPU/flat-address-space.ll index c867e4fca229..e486b9c71a54 100644 --- a/test/CodeGen/AMDGPU/flat-address-space.ll +++ b/test/CodeGen/AMDGPU/flat-address-space.ll @@ -1,6 +1,7 @@ -; RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire < %s | FileCheck %s -; RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck %s +; RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=bonaire < %s | FileCheck -check-prefixes=CHECK,CIVI %s +; RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,CIVI %s ; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,HSA %s +; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefixes=CHECK,HSA,GFX9 %s ; Disable optimizations in case there are optimizations added that ; specialize away generic pointer accesses. @@ -172,6 +173,55 @@ define amdgpu_kernel void @flat_scratch_multidword_store() { ret void } +; CHECK-LABEL: {{^}}store_flat_i8_max_offset: +; CIVI: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}} +; GFX9: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:4095{{$}} +define amdgpu_kernel void @store_flat_i8_max_offset(i8 addrspace(4)* %fptr, i8 %x) #0 { + %fptr.offset = getelementptr inbounds i8, i8 addrspace(4)* %fptr, i64 4095 + store volatile i8 %x, i8 addrspace(4)* %fptr.offset + ret void +} + +; CHECK-LABEL: {{^}}store_flat_i8_max_offset_p1: +; CHECK: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}} +define amdgpu_kernel void @store_flat_i8_max_offset_p1(i8 addrspace(4)* %fptr, i8 %x) #0 { + %fptr.offset = getelementptr inbounds i8, i8 addrspace(4)* %fptr, i64 4096 + store volatile i8 %x, i8 addrspace(4)* %fptr.offset + ret void +} + +; CHECK-LABEL: {{^}}store_flat_i8_neg_offset: +; CHECK: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}} +define amdgpu_kernel void @store_flat_i8_neg_offset(i8 addrspace(4)* %fptr, i8 %x) #0 { + %fptr.offset = getelementptr inbounds i8, i8 addrspace(4)* %fptr, i64 -2 + store volatile i8 %x, i8 addrspace(4)* %fptr.offset + ret void +} + +; CHECK-LABEL: {{^}}load_flat_i8_max_offset: +; CIVI: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}{{$}} +; GFX9: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} offset:4095{{$}} +define amdgpu_kernel void @load_flat_i8_max_offset(i8 addrspace(4)* %fptr) #0 { + %fptr.offset = getelementptr inbounds i8, i8 addrspace(4)* %fptr, i64 4095 + %val = load volatile i8, i8 addrspace(4)* %fptr.offset + ret void +} + +; CHECK-LABEL: {{^}}load_flat_i8_max_offset_p1: +; CHECK: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}{{$}} +define amdgpu_kernel void @load_flat_i8_max_offset_p1(i8 addrspace(4)* %fptr) #0 { + %fptr.offset = getelementptr inbounds i8, i8 addrspace(4)* %fptr, i64 4096 + %val = load volatile i8, i8 addrspace(4)* %fptr.offset + ret void +} + +; CHECK-LABEL: {{^}}load_flat_i8_neg_offset: +; CHECK: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}{{$}} +define amdgpu_kernel void @load_flat_i8_neg_offset(i8 addrspace(4)* %fptr) #0 { + %fptr.offset = getelementptr inbounds i8, i8 addrspace(4)* %fptr, i64 -2 + %val = load volatile i8, i8 addrspace(4)* %fptr.offset + ret void +} + attributes #0 = { nounwind } attributes #1 = { nounwind convergent } -attributes #3 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/flat_atomics.ll b/test/CodeGen/AMDGPU/flat_atomics.ll index cc95d80570e0..8e153181decb 100644 --- a/test/CodeGen/AMDGPU/flat_atomics.ll +++ b/test/CodeGen/AMDGPU/flat_atomics.ll @@ -1,8 +1,10 @@ -; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CIVI %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CIVI %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s ; GCN-LABEL: {{^}}atomic_add_i32_offset: -; GCN: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} +; CIVI: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} +; GFX9: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16{{$}} define amdgpu_kernel void @atomic_add_i32_offset(i32 addrspace(4)* %out, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 @@ -10,8 +12,28 @@ entry: ret void } +; GCN-LABEL: {{^}}atomic_add_i32_max_offset: +; CIVI: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} +; GFX9: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:4092{{$}} +define amdgpu_kernel void @atomic_add_i32_max_offset(i32 addrspace(4)* %out, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 1023 + %val = atomicrmw volatile add i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i32_max_offset_p1: +; GCN: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} +define amdgpu_kernel void @atomic_add_i32_max_offset_p1(i32 addrspace(4)* %out, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 1024 + %val = atomicrmw volatile add i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + ; GCN-LABEL: {{^}}atomic_add_i32_ret_offset: -; GCN: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}} +; CIVI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GFX9: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_add_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { entry: @@ -22,7 +44,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_add_i32_addr64_offset: -; GCN: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; CIVI: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; GFX9: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} define amdgpu_kernel void @atomic_add_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index @@ -32,7 +55,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_add_i32_ret_addr64_offset: -; GCN: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; CIVI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GFX9: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_add_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { entry: @@ -82,7 +106,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_and_i32_offset: -; GCN: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; CIVI: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; GFX9: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} define amdgpu_kernel void @atomic_and_i32_offset(i32 addrspace(4)* %out, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 @@ -91,7 +116,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_and_i32_ret_offset: -; GCN: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; CIVI: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GFX9: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_and_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { entry: @@ -102,7 +128,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_and_i32_addr64_offset: -; GCN: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; CIVI: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; GFX9: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} define amdgpu_kernel void @atomic_and_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index @@ -112,7 +139,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_and_i32_ret_addr64_offset: -; GCN: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; CIVI: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GFX9: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_and_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { entry: @@ -162,7 +190,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_sub_i32_offset: -; GCN: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; CIVI: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; GFX9: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} define amdgpu_kernel void @atomic_sub_i32_offset(i32 addrspace(4)* %out, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 @@ -171,7 +200,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_sub_i32_ret_offset: -; GCN: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; CIVI: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GFX9: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_sub_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { entry: @@ -182,7 +212,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_sub_i32_addr64_offset: -; GCN: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; CIVI: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; GFX9: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} define amdgpu_kernel void @atomic_sub_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index @@ -192,7 +223,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_sub_i32_ret_addr64_offset: -; GCN: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; CIVI: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GFX9: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_sub_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { entry: @@ -242,7 +274,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_max_i32_offset: -; GCN: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; CIVI: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; GFX9: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} define amdgpu_kernel void @atomic_max_i32_offset(i32 addrspace(4)* %out, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 @@ -251,7 +284,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_max_i32_ret_offset: -; GCN: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; CIVI: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GFX9: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_max_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { entry: @@ -262,7 +296,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_max_i32_addr64_offset: -; GCN: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; CIVI: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; GFX9: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} define amdgpu_kernel void @atomic_max_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index @@ -272,7 +307,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_max_i32_ret_addr64_offset: -; GCN: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; CIVI: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GFX9: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_max_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { entry: @@ -322,7 +358,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_umax_i32_offset: -; GCN: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; CIVI: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; GFX9: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} define amdgpu_kernel void @atomic_umax_i32_offset(i32 addrspace(4)* %out, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 @@ -331,7 +368,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_umax_i32_ret_offset: -; GCN: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; CIVI: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GFX9: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_umax_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { entry: @@ -342,7 +380,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_umax_i32_addr64_offset: -; GCN: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; CIVI: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; GFX9: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} define amdgpu_kernel void @atomic_umax_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index @@ -352,7 +391,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_umax_i32_ret_addr64_offset: -; GCN: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; CIVI: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GFX9: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_umax_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { entry: @@ -402,7 +442,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_min_i32_offset: -; GCN: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; CIVI: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; GFX9: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} define amdgpu_kernel void @atomic_min_i32_offset(i32 addrspace(4)* %out, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 @@ -411,7 +452,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_min_i32_ret_offset: -; GCN: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; CIVI: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GFX9: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_min_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { entry: @@ -422,7 +464,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_min_i32_addr64_offset: -; GCN: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; CIVI: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; GFX9: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} define amdgpu_kernel void @atomic_min_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index @@ -432,7 +475,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_min_i32_ret_addr64_offset: -; GCN: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; CIVI: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GFX9: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_min_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { entry: @@ -482,7 +526,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_umin_i32_offset: -; GCN: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; CIVI: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; GFX9: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} define amdgpu_kernel void @atomic_umin_i32_offset(i32 addrspace(4)* %out, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 @@ -491,7 +536,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_umin_i32_ret_offset: -; GCN: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; CIVI: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GFX9: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_umin_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { entry: @@ -502,7 +548,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_umin_i32_addr64_offset: -; GCN: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; CIVI: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; GFX9: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} define amdgpu_kernel void @atomic_umin_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index @@ -512,7 +559,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_umin_i32_ret_addr64_offset: -; GCN: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; CIVI: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GFX9: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_umin_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { entry: @@ -562,7 +610,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_or_i32_offset: -; GCN: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}{{$}} +; CIVI: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; GFX9: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} define amdgpu_kernel void @atomic_or_i32_offset(i32 addrspace(4)* %out, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 @@ -571,7 +620,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_or_i32_ret_offset: -; GCN: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; CIVI: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GFX9: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_or_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { entry: @@ -582,7 +632,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_or_i32_addr64_offset: -; GCN: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}{{$}} +; CIVI: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; GFX9: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} define amdgpu_kernel void @atomic_or_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index @@ -592,7 +643,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_or_i32_ret_addr64_offset: -; GCN: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; CIVI: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GFX9: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_or_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { entry: @@ -642,7 +694,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_xchg_i32_offset: -; GCN: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}{{$}} +; CIVI: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; GFX9: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} define amdgpu_kernel void @atomic_xchg_i32_offset(i32 addrspace(4)* %out, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 @@ -651,7 +704,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_xchg_i32_ret_offset: -; GCN: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; CIVI: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GFX9: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_xchg_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { entry: @@ -662,7 +716,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_xchg_i32_addr64_offset: -; GCN: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}{{$}} +; CIVI: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; GFX9: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} define amdgpu_kernel void @atomic_xchg_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index @@ -672,7 +727,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_xchg_i32_ret_addr64_offset: -; GCN: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; CIVI: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GFX9: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_xchg_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { entry: @@ -724,7 +780,8 @@ entry: ; CMP_SWAP ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_offset: -; GCN: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} +; CIVI: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} +; GFX9: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] offset:16{{$}} define amdgpu_kernel void @atomic_cmpxchg_i32_offset(i32 addrspace(4)* %out, i32 %in, i32 %old) { entry: %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 @@ -733,7 +790,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_offset: -; GCN: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} +; CIVI: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} +; GFX9: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]] define amdgpu_kernel void @atomic_cmpxchg_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i32 %old) { entry: @@ -745,7 +803,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_addr64_offset: -; GCN: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} +; CIVI: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} +; GFX9: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] offset:16{{$}} define amdgpu_kernel void @atomic_cmpxchg_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index, i32 %old) { entry: %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index @@ -755,7 +814,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_addr64_offset: -; GCN: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; CIVI: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; GFX9: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]] define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index, i32 %old) { entry: @@ -808,7 +868,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_xor_i32_offset: -; GCN: flat_atomic_xor v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} +; CIVI: flat_atomic_xor v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} +; GFX9: flat_atomic_xor v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16{{$}} define amdgpu_kernel void @atomic_xor_i32_offset(i32 addrspace(4)* %out, i32 %in) { entry: %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 @@ -817,7 +878,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_xor_i32_ret_offset: -; GCN: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}} +; CIVI: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GFX9: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_xor_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { entry: @@ -828,7 +890,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_xor_i32_addr64_offset: -; GCN: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; CIVI: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +; GFX9: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} define amdgpu_kernel void @atomic_xor_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index @@ -838,7 +901,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_xor_i32_ret_addr64_offset: -; GCN: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; CIVI: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GFX9: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_xor_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { entry: @@ -888,7 +952,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_load_i32_offset: -; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} +; CIVI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} +; GFX9: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_load_i32_offset(i32 addrspace(4)* %in, i32 addrspace(4)* %out) { entry: @@ -909,7 +974,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_load_i32_addr64_offset: -; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; CIVI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; GFX9: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] offset:16 glc{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] define amdgpu_kernel void @atomic_load_i32_addr64_offset(i32 addrspace(4)* %in, i32 addrspace(4)* %out, i64 %index) { entry: @@ -932,7 +998,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_store_i32_offset: -; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} glc{{$}} +; CIVI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} glc{{$}} +; GFX9: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} offset:16 glc{{$}} define amdgpu_kernel void @atomic_store_i32_offset(i32 %in, i32 addrspace(4)* %out) { entry: %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 @@ -949,7 +1016,8 @@ entry: } ; GCN-LABEL: {{^}}atomic_store_i32_addr64_offset: -; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} glc{{$}} +; CIVI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} glc{{$}} +; GFX9: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} offset:16 glc{{$}} define amdgpu_kernel void @atomic_store_i32_addr64_offset(i32 %in, i32 addrspace(4)* %out, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index diff --git a/test/CodeGen/AMDGPU/global_smrd_cfg.ll b/test/CodeGen/AMDGPU/global_smrd_cfg.ll index a6a04151caa9..be6e3fd05ae7 100644 --- a/test/CodeGen/AMDGPU/global_smrd_cfg.ll +++ b/test/CodeGen/AMDGPU/global_smrd_cfg.ll @@ -72,6 +72,39 @@ bb22: ; preds = %bb20, %bb11 br i1 %tmp31, label %bb7, label %bb11 } +; one more test to ensure that aliasing store after the load +; is considered clobbering if load parent block is the same +; as a loop header block. + +; CHECK-LABEL: %bb1 + +; Load from %arg has alias store that is after the load +; but is considered clobbering because of the loop. + +; CHECK: flat_load_dword + +define amdgpu_kernel void @cfg_selfloop(i32 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture %arg1, i32 %arg2) #0 { +bb: + br label %bb1 + +bb2: + ret void + +bb1: + %tmp13 = phi i32 [ %tmp25, %bb1 ], [ 0, %bb ] + %tmp14 = srem i32 %tmp13, %arg2 + %tmp15 = sext i32 %tmp14 to i64 + %tmp16 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp15 + %tmp17 = load i32, i32 addrspace(1)* %tmp16, align 4, !tbaa !0 + %tmp19 = sext i32 %tmp13 to i64 + %tmp21 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i64 %tmp19 + store i32 %tmp17, i32 addrspace(1)* %tmp21, align 4, !tbaa !0 + %tmp25 = add nuw nsw i32 %tmp13, 1 + %tmp31 = icmp eq i32 %tmp25, 100 + br i1 %tmp31, label %bb2, label %bb1 +} + + attributes #0 = { "target-cpu"="fiji" } !0 = !{!1, !1, i64 0} diff --git a/test/CodeGen/AMDGPU/inserted-wait-states.mir b/test/CodeGen/AMDGPU/inserted-wait-states.mir index ff9fcd1c693f..c6fe6debd225 100644 --- a/test/CodeGen/AMDGPU/inserted-wait-states.mir +++ b/test/CodeGen/AMDGPU/inserted-wait-states.mir @@ -246,15 +246,15 @@ body: | S_BRANCH %bb.1 bb.1: - FLAT_STORE_DWORDX2 %vgpr0_vgpr1, %vgpr2_vgpr3, 0, 0, implicit %exec, implicit %flat_scr + FLAT_STORE_DWORDX2 %vgpr0_vgpr1, %vgpr2_vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr %vgpr3 = V_MOV_B32_e32 0, implicit %exec - FLAT_STORE_DWORDX3 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4, 0, 0, implicit %exec, implicit %flat_scr + FLAT_STORE_DWORDX3 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4, 0, 0, 0, implicit %exec, implicit %flat_scr %vgpr3 = V_MOV_B32_e32 0, implicit %exec - FLAT_STORE_DWORDX4 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit %exec, implicit %flat_scr + FLAT_STORE_DWORDX4 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, 0, implicit %exec, implicit %flat_scr %vgpr3 = V_MOV_B32_e32 0, implicit %exec - FLAT_ATOMIC_CMPSWAP_X2 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, implicit %exec, implicit %flat_scr + FLAT_ATOMIC_CMPSWAP_X2 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit %exec, implicit %flat_scr %vgpr3 = V_MOV_B32_e32 0, implicit %exec - FLAT_ATOMIC_FCMPSWAP_X2 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, implicit %exec, implicit %flat_scr + FLAT_ATOMIC_FCMPSWAP_X2 %vgpr0_vgpr1, %vgpr2_vgpr3_vgpr4_vgpr5, 0, 0, implicit %exec, implicit %flat_scr %vgpr3 = V_MOV_B32_e32 0, implicit %exec S_ENDPGM diff --git a/test/CodeGen/AMDGPU/limit-coalesce.mir b/test/CodeGen/AMDGPU/limit-coalesce.mir index 7d6d8a5891cd..d6b3d7b14cd2 100644 --- a/test/CodeGen/AMDGPU/limit-coalesce.mir +++ b/test/CodeGen/AMDGPU/limit-coalesce.mir @@ -57,15 +57,15 @@ body: | %4.sub1 = COPY %3.sub0 undef %5.sub0 = COPY %4.sub1 %5.sub1 = COPY %4.sub0 - FLAT_STORE_DWORDX2 %vgpr0_vgpr1, killed %5, 0, 0, implicit %exec, implicit %flat_scr + FLAT_STORE_DWORDX2 %vgpr0_vgpr1, killed %5, 0, 0, 0, implicit %exec, implicit %flat_scr %6 = IMPLICIT_DEF undef %7.sub0_sub1 = COPY %6 %7.sub2 = COPY %3.sub0 - FLAT_STORE_DWORDX3 %vgpr0_vgpr1, killed %7, 0, 0, implicit %exec, implicit %flat_scr + FLAT_STORE_DWORDX3 %vgpr0_vgpr1, killed %7, 0, 0, 0, implicit %exec, implicit %flat_scr %8 = IMPLICIT_DEF undef %9.sub0_sub1_sub2 = COPY %8 %9.sub3 = COPY %3.sub0 - FLAT_STORE_DWORDX4 %vgpr0_vgpr1, killed %9, 0, 0, implicit %exec, implicit %flat_scr + FLAT_STORE_DWORDX4 %vgpr0_vgpr1, killed %9, 0, 0, 0, implicit %exec, implicit %flat_scr ... diff --git a/test/CodeGen/AMDGPU/rename-independent-subregs-invalid-mac-operands.mir b/test/CodeGen/AMDGPU/rename-independent-subregs-invalid-mac-operands.mir index 1a0d68d81f97..31024277871d 100644 --- a/test/CodeGen/AMDGPU/rename-independent-subregs-invalid-mac-operands.mir +++ b/test/CodeGen/AMDGPU/rename-independent-subregs-invalid-mac-operands.mir @@ -58,12 +58,12 @@ body: | bb.3: %1 = COPY killed %17 - FLAT_STORE_DWORD undef %10, %1.sub2, 0, 0, implicit %exec, implicit %flat_scr + FLAT_STORE_DWORD undef %10, %1.sub2, 0, 0, 0, implicit %exec, implicit %flat_scr %14 = COPY %1.sub1 %16 = COPY killed %1.sub0 undef %15.sub0 = COPY killed %16 %15.sub1 = COPY killed %14 - FLAT_STORE_DWORDX2 undef %11, killed %15, 0, 0, implicit %exec, implicit %flat_scr + FLAT_STORE_DWORDX2 undef %11, killed %15, 0, 0, 0, implicit %exec, implicit %flat_scr S_ENDPGM ... diff --git a/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir b/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir index cd0d410368c7..ba937c927c70 100644 --- a/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir +++ b/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir @@ -214,26 +214,26 @@ body: | %15 = S_ADDC_U32 %7.sub1, %0.sub1, implicit-def dead %scc, implicit %scc %16 = REG_SEQUENCE %14, 1, %15, 2 %18 = COPY %16 - %17 = FLAT_LOAD_DWORD %18, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.uglygep45) + %17 = FLAT_LOAD_DWORD %18, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.uglygep45) %60 = V_BFE_U32 %17, 8, 8, implicit %exec %61 = V_LSHLREV_B32_e32 2, killed %60, implicit %exec %70 = V_ADD_I32_e32 %7.sub0, %61, implicit-def %vcc, implicit %exec %66 = COPY %13 %65 = V_ADDC_U32_e32 0, %66, implicit-def %vcc, implicit %vcc, implicit %exec %67 = REG_SEQUENCE %70, 1, killed %65, 2 - FLAT_STORE_DWORD %67, %30, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.tmp9) + FLAT_STORE_DWORD %67, %30, 0, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.tmp9) %37 = S_ADD_U32 %14, 4, implicit-def %scc %38 = S_ADDC_U32 %15, 0, implicit-def dead %scc, implicit %scc %71 = COPY killed %37 %72 = COPY killed %38 %41 = REG_SEQUENCE killed %71, 1, killed %72, 2 - %40 = FLAT_LOAD_DWORD killed %41, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.scevgep) + %40 = FLAT_LOAD_DWORD killed %41, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.scevgep) %73 = V_BFE_U32 %40, 8, 8, implicit %exec %74 = V_LSHLREV_B32_e32 2, killed %73, implicit %exec %83 = V_ADD_I32_e32 %7.sub0, %74, implicit-def %vcc, implicit %exec %78 = V_ADDC_U32_e32 0, %66, implicit-def %vcc, implicit %vcc, implicit %exec %80 = REG_SEQUENCE %83, 1, killed %78, 2 - FLAT_STORE_DWORD %80, %30, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.tmp17) + FLAT_STORE_DWORD %80, %30, 0, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.tmp17) %55 = S_ADD_U32 %0.sub0, 8, implicit-def %scc %56 = S_ADDC_U32 %0.sub1, 0, implicit-def dead %scc, implicit %scc %57 = REG_SEQUENCE %55, 1, killed %56, 2 @@ -377,26 +377,26 @@ body: | %15 = S_ADDC_U32 %7.sub1, %0.sub1, implicit-def dead %scc, implicit %scc %16 = REG_SEQUENCE %14, 1, %15, 2 %18 = COPY %16 - %17 = FLAT_LOAD_DWORD %18, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.uglygep45) + %17 = FLAT_LOAD_DWORD %18, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.uglygep45) %60 = V_BFE_U32 %17, 8, 8, implicit %exec %61 = V_LSHLREV_B32_e32 %84, killed %60, implicit %exec %70 = V_ADD_I32_e32 %7.sub0, %61, implicit-def %vcc, implicit %exec %66 = COPY %13 %65 = V_ADDC_U32_e32 0, %66, implicit-def %vcc, implicit %vcc, implicit %exec %67 = REG_SEQUENCE %70, 1, killed %65, 2 - FLAT_STORE_DWORD %67, %30, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.tmp9) + FLAT_STORE_DWORD %67, %30, 0, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.tmp9) %37 = S_ADD_U32 %14, 4, implicit-def %scc %38 = S_ADDC_U32 %15, 0, implicit-def dead %scc, implicit %scc %71 = COPY killed %37 %72 = COPY killed %38 %41 = REG_SEQUENCE killed %71, 1, killed %72, 2 - %40 = FLAT_LOAD_DWORD killed %41, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.scevgep) + %40 = FLAT_LOAD_DWORD killed %41, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.scevgep) %73 = V_BFE_U32 %40, 8, 8, implicit %exec %74 = V_LSHLREV_B32_e32 %84, killed %73, implicit %exec %83 = V_ADD_I32_e32 %7.sub0, %74, implicit-def %vcc, implicit %exec %78 = V_ADDC_U32_e32 0, %66, implicit-def %vcc, implicit %vcc, implicit %exec %80 = REG_SEQUENCE %83, 1, killed %78, 2 - FLAT_STORE_DWORD %80, %30, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.tmp17) + FLAT_STORE_DWORD %80, %30, 0, 0, 0, implicit %exec, implicit %flat_scr :: (store 4 into %ir.tmp17) %55 = S_ADD_U32 %0.sub0, 8, implicit-def %scc %56 = S_ADDC_U32 %0.sub1, 0, implicit-def dead %scc, implicit %scc %57 = REG_SEQUENCE %55, 1, killed %56, 2 diff --git a/test/CodeGen/AMDGPU/waitcnt.mir b/test/CodeGen/AMDGPU/waitcnt.mir index f754415dccb4..38662e83b359 100644 --- a/test/CodeGen/AMDGPU/waitcnt.mir +++ b/test/CodeGen/AMDGPU/waitcnt.mir @@ -51,21 +51,21 @@ name: flat_zero_waitcnt body: | bb.0: successors: %bb.1 - %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.global4) - %vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.global16) + %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.global4) + %vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.global16) %vgpr0 = V_MOV_B32_e32 %vgpr1, implicit %exec S_BRANCH %bb.1 bb.1: successors: %bb.2 - %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, implicit %exec, implicit %flat_scr - %vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.global16) + %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, 0, implicit %exec, implicit %flat_scr + %vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.global16) %vgpr0 = V_MOV_B32_e32 %vgpr1, implicit %exec S_BRANCH %bb.2 bb.2: - %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.flat4) - %vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.flat16) + %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 4 from %ir.flat4) + %vgpr3_vgpr4_vgpr5_vgpr6 = FLAT_LOAD_DWORDX4 %vgpr7_vgpr8, 0, 0, 0, implicit %exec, implicit %flat_scr :: (load 16 from %ir.flat16) %vgpr0 = V_MOV_B32_e32 %vgpr1, implicit %exec S_ENDPGM ... @@ -86,11 +86,11 @@ name: single_fallthrough_successor_no_end_block_wait body: | bb.0: successors: %bb.1 - %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, implicit %exec, implicit %flat_scr + %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, 0, implicit %exec, implicit %flat_scr bb.1: %vgpr3_vgpr4 = V_LSHLREV_B64 4, %vgpr7_vgpr8, implicit %exec - FLAT_STORE_DWORD %vgpr3_vgpr4, %vgpr0, 0, 0, implicit %exec, implicit %flat_scr + FLAT_STORE_DWORD %vgpr3_vgpr4, %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr S_ENDPGM ... --- @@ -114,15 +114,15 @@ name: single_branch_successor_not_next_block body: | bb.0: successors: %bb.2 - %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, implicit %exec, implicit %flat_scr + %vgpr0 = FLAT_LOAD_DWORD %vgpr1_vgpr2, 0, 0, 0, implicit %exec, implicit %flat_scr S_BRANCH %bb.2 bb.1: - FLAT_STORE_DWORD %vgpr8_vgpr9, %vgpr10, 0, 0, implicit %exec, implicit %flat_scr + FLAT_STORE_DWORD %vgpr8_vgpr9, %vgpr10, 0, 0, 0, implicit %exec, implicit %flat_scr S_ENDPGM bb.2: %vgpr3_vgpr4 = V_LSHLREV_B64 4, %vgpr7_vgpr8, implicit %exec - FLAT_STORE_DWORD %vgpr3_vgpr4, %vgpr0, 0, 0, implicit %exec, implicit %flat_scr + FLAT_STORE_DWORD %vgpr3_vgpr4, %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr S_ENDPGM ... diff --git a/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll b/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll index 05902c22fb98..6663a9210b87 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll +++ b/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll @@ -621,28 +621,18 @@ define arm_aapcscc [3 x i32] @test_tiny_int_arrays([2 x i32] %arr) { ; CHECK: liveins: %r0, %r1 ; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0 ; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1 -; CHECK: [[ARG_ARR0:%[0-9]+]](s64) = IMPLICIT_DEF -; CHECK: [[ARG_ARR1:%[0-9]+]](s64) = G_INSERT [[ARG_ARR0]], [[R0]](s32), 0 -; CHECK: [[ARG_ARR2:%[0-9]+]](s64) = G_INSERT [[ARG_ARR1]], [[R1]](s32), 32 -; CHECK: [[ARG_ARR:%[0-9]+]](s64) = COPY [[ARG_ARR2]] +; CHECK: [[ARG_ARR:%[0-9]+]](s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32) ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp -; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s64), 0 -; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s64), 32 +; CHECK: [[R0:%[0-9]+]](s32), [[R1:%[0-9]+]](s32) = G_UNMERGE_VALUES [[ARG_ARR]](s64) ; CHECK: %r0 = COPY [[R0]] ; CHECK: %r1 = COPY [[R1]] ; CHECK: BLX @tiny_int_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1 ; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0 ; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1 ; CHECK: [[R2:%[0-9]+]](s32) = COPY %r2 -; CHECK: [[RES_ARR0:%[0-9]+]](s96) = IMPLICIT_DEF -; CHECK: [[RES_ARR1:%[0-9]+]](s96) = G_INSERT [[RES_ARR0]], [[R0]](s32), 0 -; CHECK: [[RES_ARR2:%[0-9]+]](s96) = G_INSERT [[RES_ARR1]], [[R1]](s32), 32 -; CHECK: [[RES_ARR3:%[0-9]+]](s96) = G_INSERT [[RES_ARR2]], [[R2]](s32), 64 -; CHECK: [[RES_ARR:%[0-9]+]](s96) = COPY [[RES_ARR3]] +; CHECK: [[RES_ARR:%[0-9]+]](s96) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32) ; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp -; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[RES_ARR]](s96), 0 -; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[RES_ARR]](s96), 32 -; CHECK: [[R2:%[0-9]+]](s32) = G_EXTRACT [[RES_ARR]](s96), 64 +; CHECK: [[R0:%[0-9]+]](s32), [[R1:%[0-9]+]](s32), [[R2:%[0-9]+]](s32) = G_UNMERGE_VALUES [[RES_ARR]](s96) ; FIXME: This doesn't seem correct with regard to the AAPCS docs (which say ; that composite types larger than 4 bytes should be passed through memory), ; but it's what DAGISel does. We should fix it in the common code for both. @@ -664,19 +654,11 @@ define arm_aapcscc void @test_multiple_int_arrays([2 x i32] %arr0, [2 x i32] %ar ; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1 ; CHECK: [[R2:%[0-9]+]](s32) = COPY %r2 ; CHECK: [[R3:%[0-9]+]](s32) = COPY %r3 -; CHECK: [[ARG_ARR0_0:%[0-9]+]](s64) = IMPLICIT_DEF -; CHECK: [[ARG_ARR0_1:%[0-9]+]](s64) = G_INSERT [[ARG_ARR0_0]], [[R0]](s32), 0 -; CHECK: [[ARG_ARR0_2:%[0-9]+]](s64) = G_INSERT [[ARG_ARR0_1]], [[R1]](s32), 32 -; CHECK: [[ARG_ARR0:%[0-9]+]](s64) = COPY [[ARG_ARR0_2]] -; CHECK: [[ARG_ARR1_0:%[0-9]+]](s64) = IMPLICIT_DEF -; CHECK: [[ARG_ARR1_1:%[0-9]+]](s64) = G_INSERT [[ARG_ARR1_0]], [[R2]](s32), 0 -; CHECK: [[ARG_ARR1_2:%[0-9]+]](s64) = G_INSERT [[ARG_ARR1_1]], [[R3]](s32), 32 -; CHECK: [[ARG_ARR1:%[0-9]+]](s64) = COPY [[ARG_ARR1_2]] +; CHECK: [[ARG_ARR0:%[0-9]+]](s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32) +; CHECK: [[ARG_ARR1:%[0-9]+]](s64) = G_MERGE_VALUES [[R2]](s32), [[R3]](s32) ; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp -; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR0]](s64), 0 -; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR0]](s64), 32 -; CHECK: [[R2:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR1]](s64), 0 -; CHECK: [[R3:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR1]](s64), 32 +; CHECK: [[R0:%[0-9]+]](s32), [[R1:%[0-9]+]](s32) = G_UNMERGE_VALUES [[ARG_ARR0]](s64) +; CHECK: [[R2:%[0-9]+]](s32), [[R3:%[0-9]+]](s32) = G_UNMERGE_VALUES [[ARG_ARR1]](s64) ; CHECK: %r0 = COPY [[R0]] ; CHECK: %r1 = COPY [[R1]] ; CHECK: %r2 = COPY [[R2]] @@ -707,21 +689,9 @@ define arm_aapcscc void @test_large_int_arrays([20 x i32] %arr) { ; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]](s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]] ; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]] ; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]](s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]] -; CHECK: [[ARG_ARR0:%[0-9]+]](s640) = IMPLICIT_DEF -; CHECK: [[ARG_ARR1:%[0-9]+]](s640) = G_INSERT [[ARG_ARR0]], [[R0]](s32), 0 -; CHECK: [[ARG_ARR2:%[0-9]+]](s640) = G_INSERT [[ARG_ARR1]], [[R1]](s32), 32 -; CHECK: [[ARG_ARR3:%[0-9]+]](s640) = G_INSERT [[ARG_ARR2]], [[R2]](s32), 64 -; CHECK: [[ARG_ARR4:%[0-9]+]](s640) = G_INSERT [[ARG_ARR3]], [[R3]](s32), 96 -; CHECK: [[ARG_ARR5:%[0-9]+]](s640) = G_INSERT [[ARG_ARR4]], [[FIRST_STACK_ELEMENT]](s32), 128 -; CHECK: [[ARG_ARR6:%[0-9]+]](s640) = G_INSERT {{%[0-9]+}}, [[LAST_STACK_ELEMENT]](s32), 608 -; CHECK: [[ARG_ARR:%[0-9]+]](s640) = COPY [[ARG_ARR6]] +; CHECK: [[ARG_ARR:%[0-9]+]](s640) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32) ; CHECK: ADJCALLSTACKDOWN 64, 0, 14, _, implicit-def %sp, implicit %sp -; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s640), 0 -; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s640), 32 -; CHECK: [[R2:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s640), 64 -; CHECK: [[R3:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s640), 96 -; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s640), 128 -; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s640), 608 +; CHECK: [[R0:%[0-9]+]](s32), [[R1:%[0-9]+]](s32), [[R2:%[0-9]+]](s32), [[R3:%[0-9]+]](s32), [[FIRST_STACK_ELEMENT:%[0-9]+]](s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]](s32) = G_UNMERGE_VALUES [[ARG_ARR]](s640) ; CHECK: %r0 = COPY [[R0]] ; CHECK: %r1 = COPY [[R1]] ; CHECK: %r2 = COPY [[R2]] @@ -761,15 +731,9 @@ define arm_aapcscc [2 x float] @test_fp_arrays_aapcs([3 x double] %arr) { ; BIG: [[ARR1:%[0-9]+]](s64) = G_MERGE_VALUES [[ARR1_1]](s32), [[ARR1_0]](s32) ; CHECK: [[ARR2_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[ARR2_ID]] ; CHECK: [[ARR2:%[0-9]+]](s64) = G_LOAD [[ARR2_FI]]{{.*}}load 8 from %fixed-stack.[[ARR2_ID]] -; CHECK: [[ARR_MERGED_0:%[0-9]+]](s192) = IMPLICIT_DEF -; CHECK: [[ARR_MERGED_1:%[0-9]+]](s192) = G_INSERT [[ARR_MERGED_0]], [[ARR0]](s64), 0 -; CHECK: [[ARR_MERGED_2:%[0-9]+]](s192) = G_INSERT [[ARR_MERGED_1]], [[ARR1]](s64), 64 -; CHECK: [[ARR_MERGED_3:%[0-9]+]](s192) = G_INSERT [[ARR_MERGED_2]], [[ARR2]](s64), 128 -; CHECK: [[ARR_MERGED:%[0-9]+]](s192) = COPY [[ARR_MERGED_3]] +; CHECK: [[ARR_MERGED:%[0-9]+]](s192) = G_MERGE_VALUES [[ARR0]](s64), [[ARR1]](s64), [[ARR2]](s64) ; CHECK: ADJCALLSTACKDOWN 8, 0, 14, _, implicit-def %sp, implicit %sp -; CHECK: [[ARR0:%[0-9]+]](s64) = G_EXTRACT [[ARR_MERGED]](s192), 0 -; CHECK: [[ARR1:%[0-9]+]](s64) = G_EXTRACT [[ARR_MERGED]](s192), 64 -; CHECK: [[ARR2:%[0-9]+]](s64) = G_EXTRACT [[ARR_MERGED]](s192), 128 +; CHECK: [[ARR0:%[0-9]+]](s64), [[ARR1:%[0-9]+]](s64), [[ARR2:%[0-9]+]](s64) = G_UNMERGE_VALUES [[ARR_MERGED]](s192) ; CHECK: [[ARR0_0:%[0-9]+]](s32), [[ARR0_1:%[0-9]+]](s32) = G_UNMERGE_VALUES [[ARR0]](s64) ; LITTLE: %r0 = COPY [[ARR0_0]](s32) ; LITTLE: %r1 = COPY [[ARR0_1]](s32) @@ -787,13 +751,9 @@ define arm_aapcscc [2 x float] @test_fp_arrays_aapcs([3 x double] %arr) { ; CHECK: BLX @fp_arrays_aapcs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 ; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0 ; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1 -; CHECK: [[R_MERGED_0:%[0-9]+]](s64) = IMPLICIT_DEF -; CHECK: [[R_MERGED_1:%[0-9]+]](s64) = G_INSERT [[R_MERGED_0]], [[R0]](s32), 0 -; CHECK: [[R_MERGED_2:%[0-9]+]](s64) = G_INSERT [[R_MERGED_1]], [[R1]](s32), 32 -; CHECK: [[R_MERGED:%[0-9]+]](s64) = COPY [[R_MERGED_2]] +; CHECK: [[R_MERGED:%[0-9]+]](s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32) ; CHECK: ADJCALLSTACKUP 8, 0, 14, _, implicit-def %sp, implicit %sp -; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[R_MERGED]](s64), 0 -; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[R_MERGED]](s64), 32 +; CHECK: [[R0:%[0-9]+]](s32), [[R1:%[0-9]+]](s32) = G_UNMERGE_VALUES [[R_MERGED]](s64) ; CHECK: %r0 = COPY [[R0]] ; CHECK: %r1 = COPY [[R1]] ; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 @@ -826,33 +786,13 @@ define arm_aapcs_vfpcc [4 x float] @test_fp_arrays_aapcs_vfp([3 x double] %x, [3 ; CHECK: [[Z2:%[0-9]+]](s64) = G_LOAD [[Z2_FI]]{{.*}}load 8 ; CHECK: [[Z3_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Z3_ID]] ; CHECK: [[Z3:%[0-9]+]](s64) = G_LOAD [[Z3_FI]]{{.*}}load 8 -; CHECK: [[X_ARR_0:%[0-9]+]](s192) = IMPLICIT_DEF -; CHECK: [[X_ARR_1:%[0-9]+]](s192) = G_INSERT [[X_ARR_0]], [[X0]](s64), 0 -; CHECK: [[X_ARR_2:%[0-9]+]](s192) = G_INSERT [[X_ARR_1]], [[X1]](s64), 64 -; CHECK: [[X_ARR_3:%[0-9]+]](s192) = G_INSERT [[X_ARR_2]], [[X2]](s64), 128 -; CHECK: [[X_ARR:%[0-9]+]](s192) = COPY [[X_ARR_3]](s192) -; CHECK: [[Y_ARR_0:%[0-9]+]](s96) = IMPLICIT_DEF -; CHECK: [[Y_ARR_1:%[0-9]+]](s96) = G_INSERT [[Y_ARR_0]], [[Y0]](s32), 0 -; CHECK: [[Y_ARR_2:%[0-9]+]](s96) = G_INSERT [[Y_ARR_1]], [[Y1]](s32), 32 -; CHECK: [[Y_ARR_3:%[0-9]+]](s96) = G_INSERT [[Y_ARR_2]], [[Y2]](s32), 64 -; CHECK: [[Y_ARR:%[0-9]+]](s96) = COPY [[Y_ARR_3]](s96) -; CHECK: [[Z_ARR_0:%[0-9]+]](s256) = IMPLICIT_DEF -; CHECK: [[Z_ARR_1:%[0-9]+]](s256) = G_INSERT [[Z_ARR_0]], [[Z0]](s64), 0 -; CHECK: [[Z_ARR_2:%[0-9]+]](s256) = G_INSERT [[Z_ARR_1]], [[Z1]](s64), 64 -; CHECK: [[Z_ARR_3:%[0-9]+]](s256) = G_INSERT [[Z_ARR_2]], [[Z2]](s64), 128 -; CHECK: [[Z_ARR_4:%[0-9]+]](s256) = G_INSERT [[Z_ARR_3]], [[Z3]](s64), 192 -; CHECK: [[Z_ARR:%[0-9]+]](s256) = COPY [[Z_ARR_4]](s256) +; CHECK: [[X_ARR:%[0-9]+]](s192) = G_MERGE_VALUES [[X0]](s64), [[X1]](s64), [[X2]](s64) +; CHECK: [[Y_ARR:%[0-9]+]](s96) = G_MERGE_VALUES [[Y0]](s32), [[Y1]](s32), [[Y2]](s32) +; CHECK: [[Z_ARR:%[0-9]+]](s256) = G_MERGE_VALUES [[Z0]](s64), [[Z1]](s64), [[Z2]](s64), [[Z3]](s64) ; CHECK: ADJCALLSTACKDOWN 32, 0, 14, _, implicit-def %sp, implicit %sp -; CHECK: [[X0:%[0-9]+]](s64) = G_EXTRACT [[X_ARR]](s192), 0 -; CHECK: [[X1:%[0-9]+]](s64) = G_EXTRACT [[X_ARR]](s192), 64 -; CHECK: [[X2:%[0-9]+]](s64) = G_EXTRACT [[X_ARR]](s192), 128 -; CHECK: [[Y0:%[0-9]+]](s32) = G_EXTRACT [[Y_ARR]](s96), 0 -; CHECK: [[Y1:%[0-9]+]](s32) = G_EXTRACT [[Y_ARR]](s96), 32 -; CHECK: [[Y2:%[0-9]+]](s32) = G_EXTRACT [[Y_ARR]](s96), 64 -; CHECK: [[Z0:%[0-9]+]](s64) = G_EXTRACT [[Z_ARR]](s256), 0 -; CHECK: [[Z1:%[0-9]+]](s64) = G_EXTRACT [[Z_ARR]](s256), 64 -; CHECK: [[Z2:%[0-9]+]](s64) = G_EXTRACT [[Z_ARR]](s256), 128 -; CHECK: [[Z3:%[0-9]+]](s64) = G_EXTRACT [[Z_ARR]](s256), 192 +; CHECK: [[X0:%[0-9]+]](s64), [[X1:%[0-9]+]](s64), [[X2:%[0-9]+]](s64) = G_UNMERGE_VALUES [[X_ARR]](s192) +; CHECK: [[Y0:%[0-9]+]](s32), [[Y1:%[0-9]+]](s32), [[Y2:%[0-9]+]](s32) = G_UNMERGE_VALUES [[Y_ARR]](s96) +; CHECK: [[Z0:%[0-9]+]](s64), [[Z1:%[0-9]+]](s64), [[Z2:%[0-9]+]](s64), [[Z3:%[0-9]+]](s64) = G_UNMERGE_VALUES [[Z_ARR]](s256) ; CHECK: %d0 = COPY [[X0]](s64) ; CHECK: %d1 = COPY [[X1]](s64) ; CHECK: %d2 = COPY [[X2]](s64) @@ -880,17 +820,9 @@ define arm_aapcs_vfpcc [4 x float] @test_fp_arrays_aapcs_vfp([3 x double] %x, [3 ; CHECK: [[R1:%[0-9]+]](s32) = COPY %s1 ; CHECK: [[R2:%[0-9]+]](s32) = COPY %s2 ; CHECK: [[R3:%[0-9]+]](s32) = COPY %s3 -; CHECK: [[R_MERGED_0:%[0-9]+]](s128) = IMPLICIT_DEF -; CHECK: [[R_MERGED_1:%[0-9]+]](s128) = G_INSERT [[R_MERGED_0]], [[R0]](s32), 0 -; CHECK: [[R_MERGED_2:%[0-9]+]](s128) = G_INSERT [[R_MERGED_1]], [[R1]](s32), 32 -; CHECK: [[R_MERGED_3:%[0-9]+]](s128) = G_INSERT [[R_MERGED_2]], [[R2]](s32), 64 -; CHECK: [[R_MERGED_4:%[0-9]+]](s128) = G_INSERT [[R_MERGED_3]], [[R3]](s32), 96 -; CHECK: [[R_MERGED:%[0-9]+]](s128) = COPY [[R_MERGED_4]] +; CHECK: [[R_MERGED:%[0-9]+]](s128) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32) ; CHECK: ADJCALLSTACKUP 32, 0, 14, _, implicit-def %sp, implicit %sp -; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[R_MERGED]](s128), 0 -; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[R_MERGED]](s128), 32 -; CHECK: [[R2:%[0-9]+]](s32) = G_EXTRACT [[R_MERGED]](s128), 64 -; CHECK: [[R3:%[0-9]+]](s32) = G_EXTRACT [[R_MERGED]](s128), 96 +; CHECK: [[R0:%[0-9]+]](s32), [[R1:%[0-9]+]](s32), [[R2:%[0-9]+]](s32), [[R3:%[0-9]+]](s32) = G_UNMERGE_VALUES [[R_MERGED]](s128) ; CHECK: %s0 = COPY [[R0]] ; CHECK: %s1 = COPY [[R1]] ; CHECK: %s2 = COPY [[R2]] @@ -919,21 +851,9 @@ define arm_aapcscc [2 x i32*] @test_tough_arrays([6 x [4 x i32]] %arr) { ; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]](s32) = G_LOAD [[FIRST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[FIRST_STACK_ID]] ; CHECK: [[LAST_STACK_ELEMENT_FI:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[LAST_STACK_ID]] ; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]](s32) = G_LOAD [[LAST_STACK_ELEMENT_FI]]{{.*}}load 4 from %fixed-stack.[[LAST_STACK_ID]] -; CHECK: [[ARG_ARR0:%[0-9]+]](s768) = IMPLICIT_DEF -; CHECK: [[ARG_ARR1:%[0-9]+]](s768) = G_INSERT [[ARG_ARR0]], [[R0]](s32), 0 -; CHECK: [[ARG_ARR2:%[0-9]+]](s768) = G_INSERT [[ARG_ARR1]], [[R1]](s32), 32 -; CHECK: [[ARG_ARR3:%[0-9]+]](s768) = G_INSERT [[ARG_ARR2]], [[R2]](s32), 64 -; CHECK: [[ARG_ARR4:%[0-9]+]](s768) = G_INSERT [[ARG_ARR3]], [[R3]](s32), 96 -; CHECK: [[ARG_ARR5:%[0-9]+]](s768) = G_INSERT [[ARG_ARR4]], [[FIRST_STACK_ELEMENT]](s32), 128 -; CHECK: [[ARG_ARR6:%[0-9]+]](s768) = G_INSERT {{%[0-9]+}}, [[LAST_STACK_ELEMENT]](s32), 736 -; CHECK: [[ARG_ARR:%[0-9]+]](s768) = COPY [[ARG_ARR6]] +; CHECK: [[ARG_ARR:%[0-9]+]](s768) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32), [[R2]](s32), [[R3]](s32), [[FIRST_STACK_ELEMENT]](s32), {{.*}}, [[LAST_STACK_ELEMENT]](s32) ; CHECK: ADJCALLSTACKDOWN 80, 0, 14, _, implicit-def %sp, implicit %sp -; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s768), 0 -; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s768), 32 -; CHECK: [[R2:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s768), 64 -; CHECK: [[R3:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s768), 96 -; CHECK: [[FIRST_STACK_ELEMENT:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s768), 128 -; CHECK: [[LAST_STACK_ELEMENT:%[0-9]+]](s32) = G_EXTRACT [[ARG_ARR]](s768), 736 +; CHECK: [[R0:%[0-9]+]](s32), [[R1:%[0-9]+]](s32), [[R2:%[0-9]+]](s32), [[R3:%[0-9]+]](s32), [[FIRST_STACK_ELEMENT:%[0-9]+]](s32), {{.*}}, [[LAST_STACK_ELEMENT:%[0-9]+]](s32) = G_UNMERGE_VALUES [[ARG_ARR]](s768) ; CHECK: %r0 = COPY [[R0]] ; CHECK: %r1 = COPY [[R1]] ; CHECK: %r2 = COPY [[R2]] @@ -951,13 +871,9 @@ define arm_aapcscc [2 x i32*] @test_tough_arrays([6 x [4 x i32]] %arr) { ; CHECK: BLX @tough_arrays_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 ; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0 ; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1 -; CHECK: [[RES_ARR0:%[0-9]+]](s64) = IMPLICIT_DEF -; CHECK: [[RES_ARR1:%[0-9]+]](s64) = G_INSERT [[RES_ARR0]], [[R0]](s32), 0 -; CHECK: [[RES_ARR2:%[0-9]+]](s64) = G_INSERT [[RES_ARR1]], [[R1]](s32), 32 -; CHECK: [[RES_ARR:%[0-9]+]](s64) = COPY [[RES_ARR2]] +; CHECK: [[RES_ARR:%[0-9]+]](s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32) ; CHECK: ADJCALLSTACKUP 80, 0, 14, _, implicit-def %sp, implicit %sp -; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[RES_ARR]](s64), 0 -; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[RES_ARR]](s64), 32 +; CHECK: [[R0:%[0-9]+]](s32), [[R1:%[0-9]+]](s32) = G_UNMERGE_VALUES [[RES_ARR]](s64) ; CHECK: %r0 = COPY [[R0]] ; CHECK: %r1 = COPY [[R1]] ; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 @@ -966,65 +882,28 @@ entry: ret [2 x i32*] %r } -declare arm_aapcscc {i32, i32} @structs_target({i32, i32}, {i32*, float, i32, double}) +declare arm_aapcscc {i32, i32} @structs_target({i32, i32}) -define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x, {i32*, float, i32, double} %y) { +define arm_aapcscc {i32, i32} @test_structs({i32, i32} %x) { ; CHECK-LABEL: test_structs -; CHECK: fixedStack: -; CHECK-DAG: id: [[Y2_ID:[0-9]+]], type: default, offset: 0, size: 4, -; CHECK-DAG: id: [[Y3_ID:[0-9]+]], type: default, offset: 8, size: 8, -; CHECK: liveins: %r0, %r1, %r2, %r3 +; CHECK: liveins: %r0, %r1 ; CHECK-DAG: [[X0:%[0-9]+]](s32) = COPY %r0 ; CHECK-DAG: [[X1:%[0-9]+]](s32) = COPY %r1 -; CHECK-DAG: [[Y0:%[0-9]+]](s32) = COPY %r2 -; CHECK-DAG: [[Y1:%[0-9]+]](s32) = COPY %r3 -; CHECK: [[Y2_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Y2_ID]] -; CHECK: [[Y2:%[0-9]+]](s32) = G_LOAD [[Y2_ADDR]](p0){{.*}}load 4 -; CHECK: [[Y3_ADDR:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Y3_ID]] -; CHECK: [[Y3:%[0-9]+]](s64) = G_LOAD [[Y3_ADDR]](p0){{.*}}load 8 -; CHECK: [[X_0:%[0-9]+]](s64) = IMPLICIT_DEF -; CHECK: [[X_1:%[0-9]+]](s64) = G_INSERT [[X_0]], [[X0]](s32), 0 -; CHECK: [[X_2:%[0-9]+]](s64) = G_INSERT [[X_1]], [[X1]](s32), 32 -; CHECK: [[X:%[0-9]+]](s64) = COPY [[X_2]] -; CHECK: [[Y_0:%[0-9]+]](s192) = IMPLICIT_DEF -; CHECK: [[Y_1:%[0-9]+]](s192) = G_INSERT [[Y_0]], [[Y0]](s32), 0 -; CHECK: [[Y_2:%[0-9]+]](s192) = G_INSERT [[Y_1]], [[Y1]](s32), 32 -; CHECK: [[Y_3:%[0-9]+]](s192) = G_INSERT [[Y_2]], [[Y2]](s32), 64 -; CHECK: [[Y_4:%[0-9]+]](s192) = G_INSERT [[Y_3]], [[Y3]](s64), 128 -; CHECK: [[Y:%[0-9]+]](s192) = COPY [[Y_4]] -; CHECK: ADJCALLSTACKDOWN 16, 0, 14, _, implicit-def %sp, implicit %sp -; CHECK: [[X0:%[0-9]+]](s32) = G_EXTRACT [[X]](s64), 0 -; CHECK: [[X1:%[0-9]+]](s32) = G_EXTRACT [[X]](s64), 32 -; CHECK: [[Y0:%[0-9]+]](s32) = G_EXTRACT [[Y]](s192), 0 -; CHECK: [[Y1:%[0-9]+]](s32) = G_EXTRACT [[Y]](s192), 32 -; CHECK: [[Y2:%[0-9]+]](s32) = G_EXTRACT [[Y]](s192), 64 -; CHECK: [[Y3:%[0-9]+]](s64) = G_EXTRACT [[Y]](s192), 128 +; CHECK: [[X:%[0-9]+]](s64) = G_MERGE_VALUES [[X0]](s32), [[X1]](s32) +; CHECK: ADJCALLSTACKDOWN 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: [[X0:%[0-9]+]](s32), [[X1:%[0-9]+]](s32) = G_UNMERGE_VALUES [[X]](s64) ; CHECK-DAG: %r0 = COPY [[X0]](s32) ; CHECK-DAG: %r1 = COPY [[X1]](s32) -; CHECK-DAG: %r2 = COPY [[Y0]](s32) -; CHECK-DAG: %r3 = COPY [[Y1]](s32) -; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp -; CHECK: [[Y2_OFF:%[0-9]+]](s32) = G_CONSTANT i32 0 -; CHECK: [[Y2_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[Y2_OFF]](s32) -; CHECK: G_STORE [[Y2]](s32), [[Y2_ADDR]](p0){{.*}}store 4 -; CHECK: [[SP:%[0-9]+]](p0) = COPY %sp -; CHECK: [[Y3_OFF:%[0-9]+]](s32) = G_CONSTANT i32 8 -; CHECK: [[Y3_ADDR:%[0-9]+]](p0) = G_GEP [[SP]], [[Y3_OFF]](s32) -; CHECK: G_STORE [[Y3]](s64), [[Y3_ADDR]](p0){{.*}}store 8 -; CHECK: BLX @structs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit %r3, implicit-def %r0, implicit-def %r1 +; CHECK: BLX @structs_target, csr_aapcs, implicit-def %lr, implicit %sp, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1 ; CHECK: [[R0:%[0-9]+]](s32) = COPY %r0 ; CHECK: [[R1:%[0-9]+]](s32) = COPY %r1 -; CHECK: [[R_0:%[0-9]+]](s64) = IMPLICIT_DEF -; CHECK: [[R_1:%[0-9]+]](s64) = G_INSERT [[R_0]], [[R0]](s32), 0 -; CHECK: [[R_2:%[0-9]+]](s64) = G_INSERT [[R_1]], [[R1]](s32), 32 -; CHECK: [[R:%[0-9]+]](s64) = COPY [[R_2]] -; CHECK: ADJCALLSTACKUP 16, 0, 14, _, implicit-def %sp, implicit %sp -; CHECK: [[R0:%[0-9]+]](s32) = G_EXTRACT [[R]](s64), 0 -; CHECK: [[R1:%[0-9]+]](s32) = G_EXTRACT [[R]](s64), 32 +; CHECK: [[R:%[0-9]+]](s64) = G_MERGE_VALUES [[R0]](s32), [[R1]](s32) +; CHECK: ADJCALLSTACKUP 0, 0, 14, _, implicit-def %sp, implicit %sp +; CHECK: [[R0:%[0-9]+]](s32), [[R1:%[0-9]+]](s32) = G_UNMERGE_VALUES [[R]](s64) ; CHECK: %r0 = COPY [[R0]](s32) ; CHECK: %r1 = COPY [[R1]](s32) ; CHECK: BX_RET 14, _, implicit %r0, implicit %r1 - %r = notail call arm_aapcscc {i32, i32} @structs_target({i32, i32} %x, {i32*, float, i32, double} %y) + %r = notail call arm_aapcscc {i32, i32} @structs_target({i32, i32} %x) ret {i32, i32} %r } diff --git a/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll b/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll index 2881740b016f..c778caacd0f4 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll +++ b/test/CodeGen/ARM/GlobalISel/arm-isel-divmod.ll @@ -66,3 +66,24 @@ define arm_aapcscc i8 @test_udiv_i8(i8 %a, i8 %b) { ret i8 %r } +define arm_aapcscc i32 @test_srem_i32(i32 %x, i32 %y) { +; CHECK-LABEL: test_srem_i32: +; HWDIV: sdiv [[Q:r[0-9]+]], r0, r1 +; HWDIV: mul [[P:r[0-9]+]], [[Q]], r1 +; HWDIV: sub r0, r0, [[P]] +; SOFT-AEABI: blx __aeabi_idivmod +; SOFT-DEFAULT: blx __modsi3 + %r = srem i32 %x, %y + ret i32 %r +} + +define arm_aapcscc i32 @test_urem_i32(i32 %x, i32 %y) { +; CHECK-LABEL: test_urem_i32: +; HWDIV: udiv [[Q:r[0-9]+]], r0, r1 +; HWDIV: mul [[P:r[0-9]+]], [[Q]], r1 +; HWDIV: sub r0, r0, [[P]] +; SOFT-AEABI: blx __aeabi_uidivmod +; SOFT-DEFAULT: blx __umodsi3 + %r = urem i32 %x, %y + ret i32 %r +} diff --git a/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir b/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir index 6f3e09d328cf..c93e7fa0ec56 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir +++ b/test/CodeGen/ARM/GlobalISel/arm-legalize-divmod.mir @@ -11,6 +11,9 @@ define void @test_sdiv_i8() { ret void } define void @test_udiv_i8() { ret void } + + define void @test_srem_i32() { ret void } + define void @test_urem_i32() { ret void } ... --- name: test_sdiv_i32 @@ -228,3 +231,75 @@ body: | %r0 = COPY %2(s8) BX_RET 14, _, implicit %r0 ... +--- +name: test_srem_i32 +# CHECK-LABEL: name: test_srem_i32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1 + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; HWDIV: [[Q:%[0-9]+]](s32) = G_SDIV [[X]], [[Y]] + ; HWDIV: [[P:%[0-9]+]](s32) = G_MUL [[Q]], [[Y]] + ; HWDIV: [[R:%[0-9]+]](s32) = G_SUB [[X]], [[P]] + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BLX $__aeabi_idivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1 + ; SOFT-AEABI: [[R:%[0-9]+]](s32) = COPY %r1 + ; SOFT-DEFAULT: BLX $__modsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: [[R:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + %2(s32) = G_SREM %0, %1 + ; CHECK: %r0 = COPY [[R]] + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 +... +--- +name: test_urem_i32 +# CHECK-LABEL: name: test_urem_i32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + ; CHECK-DAG: [[X:%[0-9]+]](s32) = COPY %r0 + ; CHECK-DAG: [[Y:%[0-9]+]](s32) = COPY %r1 + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + ; HWDIV: [[Q:%[0-9]+]](s32) = G_UDIV [[X]], [[Y]] + ; HWDIV: [[P:%[0-9]+]](s32) = G_MUL [[Q]], [[Y]] + ; HWDIV: [[R:%[0-9]+]](s32) = G_SUB [[X]], [[P]] + ; SOFT: ADJCALLSTACKDOWN + ; SOFT-DAG: %r0 = COPY [[X]] + ; SOFT-DAG: %r1 = COPY [[Y]] + ; SOFT-AEABI: BLX $__aeabi_uidivmod, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0, implicit-def %r1 + ; SOFT-AEABI: [[R:%[0-9]+]](s32) = COPY %r1 + ; SOFT-DEFAULT: BLX $__umodsi3, {{.*}}, implicit %r0, implicit %r1, implicit-def %r0 + ; SOFT-DEFAULT: [[R:%[0-9]+]](s32) = COPY %r0 + ; SOFT: ADJCALLSTACKUP + %2(s32) = G_UREM %0, %1 + ; CHECK: %r0 = COPY [[R]] + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 +... diff --git a/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll b/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll index 34f00aebe1be..f2f9c5d2a81d 100644 --- a/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll +++ b/test/CodeGen/ARM/GlobalISel/arm-unsupported.ll @@ -65,6 +65,14 @@ define %large.struct @test_large_struct_return() { ret %large.struct %r } +%mixed.struct = type {i32*, float, i32} + +define %mixed.struct @test_mixed_struct(%mixed.struct %x) { +; CHECK: remark: {{.*}} unable to lower arguments: %mixed.struct (%mixed.struct)* +; CHECK-LABEL: warning: Instruction selection used fallback path for test_mixed_struct + ret %mixed.struct %x +} + define void @test_vararg_definition(i32 %a, ...) { ; CHECK: remark: {{.*}} unable to lower arguments: void (i32, ...)* ; CHECK-LABEL: warning: Instruction selection used fallback path for test_vararg_definition diff --git a/test/CodeGen/ARM/cortex-a57-misched-vfma.ll b/test/CodeGen/ARM/cortex-a57-misched-vfma.ll index 5f914323861a..e234e179ed07 100644 --- a/test/CodeGen/ARM/cortex-a57-misched-vfma.ll +++ b/test/CodeGen/ARM/cortex-a57-misched-vfma.ll @@ -156,3 +156,41 @@ define <2 x float> @Test4(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 %sub2 = fsub <2 x float> %sub1, %mul3 ret <2 x float> %sub2 } + +define float @Test5(float %f1, float %f2, float %f3) { +; CHECK: ********** MI Scheduling ********** +; CHECK: Test5:BB#0 + +; CHECK-DEFAULT: VNMLS +; CHECK-FAST: VFNMS +; CHECK: Latency : 9 +; CHECK: Successors: +; CHECK: data +; > VMLAS not-optimized latency to VMOVRS = 9 +; CHECK-SAME: Latency=9 + +; f1 * f2 - f3 ==> VNMLS/VFNMS + %mul = fmul float %f1, %f2 + %sub = fsub float %mul, %f3 + ret float %sub +} + + +define float @Test6(float %f1, float %f2, float %f3) { +; CHECK: ********** MI Scheduling ********** +; CHECK: Test6:BB#0 + +; CHECK-DEFAULT: VNMLA +; CHECK-FAST: VFNMA +; CHECK: Latency : 9 +; CHECK: Successors: +; CHECK: data +; > VMLAS not-optimized latency to VMOVRS = 9 +; CHECK-SAME: Latency=9 + +; f1 * f2 - f3 ==> VNMLA/VFNMA + %mul = fmul float %f1, %f2 + %sub1 = fsub float -0.0, %mul + %sub2 = fsub float %sub1, %f2 + ret float %sub2 +} diff --git a/test/CodeGen/ARM/debug-info-blocks.ll b/test/CodeGen/ARM/debug-info-blocks.ll index 1e9d890e9333..6019a9410b03 100644 --- a/test/CodeGen/ARM/debug-info-blocks.ll +++ b/test/CodeGen/ARM/debug-info-blocks.ll @@ -273,6 +273,6 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !160 = !DIFile(filename: "header.h", directory: "/Volumes/Sandbox/llvm") !161 = !{!"header2.h", !"/Volumes/Sandbox/llvm"} !162 = !{i32 1, !"Debug Info Version", i32 3} -!163 = !DIExpression(DW_OP_plus, 20, DW_OP_deref, DW_OP_plus, 4, DW_OP_deref, DW_OP_plus, 24) -!164 = !DIExpression(DW_OP_deref, DW_OP_plus, 24) -!165 = !DIExpression(DW_OP_deref, DW_OP_plus, 28) +!163 = !DIExpression(DW_OP_plus_uconst, 20, DW_OP_deref, DW_OP_plus_uconst, 4, DW_OP_deref, DW_OP_plus_uconst, 24) +!164 = !DIExpression(DW_OP_deref, DW_OP_plus_uconst, 24) +!165 = !DIExpression(DW_OP_deref, DW_OP_plus_uconst, 28) diff --git a/test/CodeGen/ARM/sincos.ll b/test/CodeGen/ARM/sincos.ll index 5be0044ddbd3..42a834d24b3e 100644 --- a/test/CodeGen/ARM/sincos.ll +++ b/test/CodeGen/ARM/sincos.ll @@ -1,10 +1,12 @@ ; RUN: llc < %s -mtriple=armv7-apple-ios6 -mcpu=cortex-a8 | FileCheck %s --check-prefix=NOOPT ; RUN: llc < %s -mtriple=armv7-apple-ios7 -mcpu=cortex-a8 | FileCheck %s --check-prefix=SINCOS -; RUN: llc < %s -mtriple=armv7-linux-gnu -mcpu=cortex-a8 | FileCheck %s --check-prefix=NOOPT-GNU +; RUN: llc < %s -mtriple=armv7-linux-gnu -mcpu=cortex-a8 | FileCheck %s --check-prefix=SINCOS-GNU ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a8 \ ; RUN: --enable-unsafe-fp-math | FileCheck %s --check-prefix=SINCOS-GNU -; Combine sin / cos into a single call. +; Combine sin / cos into a single call unless they may write errno (as +; captured by readnone attrbiute, controlled by clang -fmath-errno +; setting). ; rdar://12856873 define float @test1(float %x) nounwind { @@ -19,12 +21,28 @@ entry: ; NOOPT: bl _sinf ; NOOPT: bl _cosf -; NOOPT-GNU-LABEL: test1: -; NOOPT-GNU: bl sinf -; NOOPT-GNU: bl cosf + %call = tail call float @sinf(float %x) readnone + %call1 = tail call float @cosf(float %x) readnone + %add = fadd float %call, %call1 + ret float %add +} + +define float @test1_errno(float %x) nounwind { +entry: +; SINCOS-LABEL: test1_errno: +; SINCOS: bl _sinf +; SINCOS: bl _cosf - %call = tail call float @sinf(float %x) nounwind readnone - %call1 = tail call float @cosf(float %x) nounwind readnone +; SINCOS-GNU-LABEL: test1_errno: +; SINCOS-GNU: bl sinf +; SINCOS-GNU: bl cosf + +; NOOPT-LABEL: test1_errno: +; NOOPT: bl _sinf +; NOOPT: bl _cosf + + %call = tail call float @sinf(float %x) + %call1 = tail call float @cosf(float %x) %add = fadd float %call, %call1 ret float %add } @@ -41,16 +59,33 @@ entry: ; NOOPT: bl _sin ; NOOPT: bl _cos -; NOOPT-GNU-LABEL: test2: -; NOOPT-GNU: bl sin -; NOOPT-GNU: bl cos - %call = tail call double @sin(double %x) nounwind readnone - %call1 = tail call double @cos(double %x) nounwind readnone + %call = tail call double @sin(double %x) readnone + %call1 = tail call double @cos(double %x) readnone + %add = fadd double %call, %call1 + ret double %add +} + +define double @test2_errno(double %x) nounwind { +entry: +; SINCOS-LABEL: test2_errno: +; SINCOS: bl _sin +; SINCOS: bl _cos + +; SINCOS-GNU-LABEL: test2_errno: +; SINCOS-GNU: bl sin +; SINCOS-GNU: bl cos + +; NOOPT-LABEL: test2_errno: +; NOOPT: bl _sin +; NOOPT: bl _cos + + %call = tail call double @sin(double %x) + %call1 = tail call double @cos(double %x) %add = fadd double %call, %call1 ret double %add } -declare float @sinf(float) readonly -declare double @sin(double) readonly -declare float @cosf(float) readonly -declare double @cos(double) readonly +declare float @sinf(float) +declare double @sin(double) +declare float @cosf(float) +declare double @cos(double) diff --git a/test/CodeGen/ARM/swifterror.ll b/test/CodeGen/ARM/swifterror.ll index 78764202f627..3fd57c592bfb 100644 --- a/test/CodeGen/ARM/swifterror.ll +++ b/test/CodeGen/ARM/swifterror.ll @@ -528,3 +528,31 @@ entry: tail call void @acallee(i8* null) ret void } + + +declare swiftcc void @foo2(%swift_error** swifterror) + +; Make sure we properly assign registers during fast-isel. +; CHECK-O0-LABEL: testAssign +; CHECK-O0: mov r8, #0 +; CHECK-O0: bl _foo2 +; CHECK-O0: str r8, [s[[STK:p.*]]] +; CHECK-O0: ldr r0, [s[[STK]]] +; CHECK-O0: pop + +; CHECK-APPLE-LABEL: testAssign +; CHECK-APPLE: mov r8, #0 +; CHECK-APPLE: bl _foo2 +; CHECK-APPLE: mov r0, r8 + +define swiftcc %swift_error* @testAssign(i8* %error_ref) { +entry: + %error_ptr = alloca swifterror %swift_error* + store %swift_error* null, %swift_error** %error_ptr + call swiftcc void @foo2(%swift_error** swifterror %error_ptr) + br label %a + +a: + %error = load %swift_error*, %swift_error** %error_ptr + ret %swift_error* %error +} diff --git a/test/CodeGen/BPF/rodata_1.ll b/test/CodeGen/BPF/rodata_1.ll new file mode 100644 index 000000000000..5566f76bb75c --- /dev/null +++ b/test/CodeGen/BPF/rodata_1.ll @@ -0,0 +1,52 @@ +; RUN: llc < %s -march=bpfel -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -march=bpfeb -verify-machineinstrs | FileCheck %s + +; Source code: +; struct test_t1 { +; char a, b, c; +; }; +; struct test_t2 { +; int a, b, c, d, e; +; }; +; +; struct test_t1 g1; +; struct test_t2 g2; +; int test() +; { +; struct test_t1 t1 = {.c = 1}; +; struct test_t2 t2 = {.c = 1}; +; g1 = t1; +; g2 = t2; +; return 0; +; } + +%struct.test_t1 = type { i8, i8, i8 } +%struct.test_t2 = type { i32, i32, i32, i32, i32 } + +@test.t1 = private unnamed_addr constant %struct.test_t1 { i8 0, i8 0, i8 1 }, align 1 +@test.t2 = private unnamed_addr constant %struct.test_t2 { i32 0, i32 0, i32 1, i32 0, i32 0 }, align 4 +@g1 = common local_unnamed_addr global %struct.test_t1 zeroinitializer, align 1 +@g2 = common local_unnamed_addr global %struct.test_t2 zeroinitializer, align 4 + +; Function Attrs: nounwind +define i32 @test() local_unnamed_addr #0 { +; CHECK-LABEL: test: + +entry: + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds (%struct.test_t1, %struct.test_t1* @g1, i64 0, i32 0), i8* getelementptr inbounds (%struct.test_t1, %struct.test_t1* @test.t1, i64 0, i32 0), i64 3, i32 1, i1 false) + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* bitcast (%struct.test_t2* @g2 to i8*), i8* bitcast (%struct.test_t2* @test.t2 to i8*), i64 20, i32 4, i1 false) +; CHECK: r1 = <MCOperand Expr:(g1)>ll +; CHECK: r2 = 0 +; CHECK: *(u8 *)(r1 + 1) = r2 +; CHECK: r3 = 1 +; CHECK: *(u8 *)(r1 + 2) = r3 +; CHECK: r1 = <MCOperand Expr:(g2)>ll +; CHECK: *(u32 *)(r1 + 8) = r3 + ret i32 0 +} +; CHECK: .section .rodata,"a",@progbits + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1) #1 + +attributes #0 = { nounwind } +attributes #1 = { argmemonly nounwind } diff --git a/test/CodeGen/BPF/rodata_2.ll b/test/CodeGen/BPF/rodata_2.ll new file mode 100644 index 000000000000..74b3c3640c3f --- /dev/null +++ b/test/CodeGen/BPF/rodata_2.ll @@ -0,0 +1,51 @@ +; RUN: llc < %s -march=bpfel -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -march=bpfeb -verify-machineinstrs | FileCheck %s + +; Source code: +; struct test_t1 { +; char a; +; int b; +; }; +; struct test_t2 { +; char a, b; +; struct test_t1 c[2]; +; int d[2]; +; int e; +; }; +; struct test_t2 g; +; int test() +; { +; struct test_t2 t2 = {.c = {{}, {.b = 1}}, .d = {2, 3}}; +; g = t2; +; return 0; +; } + +%struct.test_t2 = type { i8, i8, [2 x %struct.test_t1], [2 x i32], i32 } +%struct.test_t1 = type { i8, i32 } + +@test.t2 = private unnamed_addr constant %struct.test_t2 { i8 0, i8 0, [2 x %struct.test_t1] [%struct.test_t1 zeroinitializer, %struct.test_t1 { i8 0, i32 1 }], [2 x i32] [i32 2, i32 3], i32 0 }, align 4 +@g = common local_unnamed_addr global %struct.test_t2 zeroinitializer, align 4 + +; Function Attrs: nounwind +define i32 @test() local_unnamed_addr #0 { +; CHECK-LABEL: test: + +entry: + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds (%struct.test_t2, %struct.test_t2* @g, i64 0, i32 0), i8* getelementptr inbounds (%struct.test_t2, %struct.test_t2* @test.t2, i64 0, i32 0), i64 32, i32 4, i1 false) +; CHECK: r1 = <MCOperand Expr:(g)>ll +; CHECK: r2 = 0 +; CHECK: *(u32 *)(r1 + 28) = r2 +; CHECK: r3 = 3 +; CHECK: *(u32 *)(r1 + 24) = r3 +; CHECK: r3 = 2 +; CHECK: *(u32 *)(r1 + 20) = r3 +; CHECK: r3 = 1 +; CHECK: *(u32 *)(r1 + 16) = r3 + ret i32 0 +} +; CHECK: .section .rodata.cst32,"aM",@progbits,32 + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1) #1 + +attributes #0 = { nounwind } +attributes #1 = { argmemonly nounwind } diff --git a/test/CodeGen/BPF/rodata_3.ll b/test/CodeGen/BPF/rodata_3.ll new file mode 100644 index 000000000000..814ce7645465 --- /dev/null +++ b/test/CodeGen/BPF/rodata_3.ll @@ -0,0 +1,41 @@ +; REQUIRES: x86_64-linux +; RUN: llc < %s -march=bpfel -verify-machineinstrs | FileCheck --check-prefix=CHECK-EL %s +; RUN: llc < %s -march=bpfeb -verify-machineinstrs | FileCheck --check-prefix=CHECK-EB %s +; +; This test requires little-endian host, so we specific x86_64-linux here. +; Source code: +; struct test_t1 { +; char a; +; int b, c, d; +; }; +; +; struct test_t1 g; +; int test() +; { +; struct test_t1 t1 = {.a = 1}; +; g = t1; +; return 0; +; } + +%struct.test_t1 = type { i8, i32, i32, i32 } + +@test.t1 = private unnamed_addr constant %struct.test_t1 { i8 1, i32 0, i32 0, i32 0 }, align 4 +@g = common local_unnamed_addr global %struct.test_t1 zeroinitializer, align 4 + +; Function Attrs: nounwind +define i32 @test() local_unnamed_addr #0 { +entry: + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds (%struct.test_t1, %struct.test_t1* @g, i64 0, i32 0), i8* getelementptr inbounds (%struct.test_t1, %struct.test_t1* @test.t1, i64 0, i32 0), i64 16, i32 4, i1 false) +; CHECK-EL: r2 = 1 +; CHECK-EL: *(u32 *)(r1 + 0) = r2 +; CHECK-EB: r2 = 16777216 +; CHECK-EB: *(u32 *)(r1 + 0) = r2 + ret i32 0 +} +; CHECK-EL: .section .rodata.cst16,"aM",@progbits,16 +; CHECK-EB: .section .rodata.cst16,"aM",@progbits,16 + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1) #1 + +attributes #0 = { nounwind } +attributes #1 = { argmemonly nounwind } diff --git a/test/CodeGen/BPF/rodata_4.ll b/test/CodeGen/BPF/rodata_4.ll new file mode 100644 index 000000000000..d6b9fba5be0a --- /dev/null +++ b/test/CodeGen/BPF/rodata_4.ll @@ -0,0 +1,43 @@ +; RUN: llc < %s -march=bpfel -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -march=bpfeb -verify-machineinstrs | FileCheck %s + +; Source code: +; struct test_t1 +; { +; short a; +; short b; +; char c; +; }; +; +; struct test_t1 g; +; int test() +; { +; struct test_t1 t1[] = {{50, 500, 5}, {60, 600, 6}, {70, 700, 7}, {80, 800, 8} }; +; +; g = t1[1]; +; return 0; +; } + +%struct.test_t1 = type { i16, i16, i8 } + +@test.t1 = private unnamed_addr constant [4 x %struct.test_t1] [%struct.test_t1 { i16 50, i16 500, i8 5 }, %struct.test_t1 { i16 60, i16 600, i8 6 }, %struct.test_t1 { i16 70, i16 700, i8 7 }, %struct.test_t1 { i16 80, i16 800, i8 8 }], align 2 +@g = common local_unnamed_addr global %struct.test_t1 zeroinitializer, align 2 + +; Function Attrs: nounwind +define i32 @test() local_unnamed_addr #0 { +; CHECK-LABEL: test: +entry: + tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* bitcast (%struct.test_t1* @g to i8*), i8* bitcast (%struct.test_t1* getelementptr inbounds ([4 x %struct.test_t1], [4 x %struct.test_t1]* @test.t1, i64 0, i64 1) to i8*), i64 6, i32 2, i1 false) +; CHECK: r2 = 600 +; CHECK: *(u16 *)(r1 + 2) = r2 +; CHECK: r2 = 60 +; CHECK: *(u16 *)(r1 + 0) = r2 + ret i32 0 +} +; CHECK .section .rodata,"a",@progbits + +; Function Attrs: argmemonly nounwind +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1) #1 + +attributes #0 = { nounwind } +attributes #1 = { argmemonly nounwind } diff --git a/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll b/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll new file mode 100644 index 000000000000..0abf8f873200 --- /dev/null +++ b/test/CodeGen/Hexagon/loop-idiom/pmpy-shiftconv-fail.ll @@ -0,0 +1,48 @@ +; RUN: opt -march=hexagon -hexagon-loop-idiom -S < %s | FileCheck %s +; REQUIRES: asserts +; +; Check for sane output, this used to crash. +; CHECK: define void @fred + +; The conversion of shifts from right to left failed, but the return +; code was not checked and the transformation proceeded. + +target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" +target triple = "hexagon" + +@A = common global [256 x i32] zeroinitializer, align 8 + +; Function Attrs: noinline nounwind +define void @fred() local_unnamed_addr #0 { +b0: + br label %b1 + +b1: ; preds = %b13, %b0 + %v2 = phi i32 [ 0, %b0 ], [ %v16, %b13 ] + br label %b3 + +b3: ; preds = %b3, %b1 + %v4 = phi i32 [ %v2, %b1 ], [ %v10, %b3 ] + %v5 = phi i32 [ 0, %b1 ], [ %v11, %b3 ] + %v6 = and i32 %v4, 1 + %v7 = icmp ne i32 %v6, 0 + %v8 = lshr i32 %v4, 1 + %v9 = xor i32 %v8, 123456789 + %v10 = select i1 %v7, i32 %v9, i32 %v8 + %v11 = add nuw nsw i32 %v5, 1 + %v12 = icmp ne i32 %v11, 8 + br i1 %v12, label %b3, label %b13 + +b13: ; preds = %b3 + %v14 = phi i32 [ %v10, %b3 ] + %v15 = getelementptr inbounds [256 x i32], [256 x i32]* @A, i32 0, i32 %v2 + store i32 %v14, i32* %v15, align 4 + %v16 = add nuw nsw i32 %v2, 1 + %v17 = icmp ne i32 %v16, 256 + br i1 %v17, label %b1, label %b18 + +b18: ; preds = %b13 + ret void +} + +attributes #0 = { noinline nounwind "target-cpu"="hexagonv60" } diff --git a/test/CodeGen/Hexagon/mulh.ll b/test/CodeGen/Hexagon/mulh.ll new file mode 100644 index 000000000000..0442e28d4089 --- /dev/null +++ b/test/CodeGen/Hexagon/mulh.ll @@ -0,0 +1,27 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +target triple = "hexagon" + +; CHECK-LABEL: danny: +; CHECK: r{{[0-9]+}} = mpy(r0,r1) +define i32 @danny(i32 %a0, i32 %a1) { +b2: + %v3 = sext i32 %a0 to i64 + %v4 = sext i32 %a1 to i64 + %v5 = mul nsw i64 %v3, %v4 + %v6 = ashr i64 %v5, 32 + %v7 = trunc i64 %v6 to i32 + ret i32 %v7 +} + +; CHECK-LABEL: sammy: +; CHECK: r{{[0-9]+}} = mpy(r0,r1) +define i32 @sammy(i32 %a0, i32 %a1) { +b2: + %v3 = sext i32 %a0 to i64 + %v4 = sext i32 %a1 to i64 + %v5 = mul nsw i64 %v3, %v4 + %v6 = lshr i64 %v5, 32 + %v7 = trunc i64 %v6 to i32 + ret i32 %v7 +} diff --git a/test/CodeGen/Hexagon/mux-kill.mir b/test/CodeGen/Hexagon/mux-kill.mir new file mode 100644 index 000000000000..6944050e3dab --- /dev/null +++ b/test/CodeGen/Hexagon/mux-kill.mir @@ -0,0 +1,15 @@ +# RUN: llc -march=hexagon -run-pass hexagon-gen-mux -o - %s -verify-machineinstrs | FileCheck %s +# CHECK: %r2 = C2_mux %p0, %r0, %r1 +--- +name: fred +tracksRegLiveness: true + +body: | + bb.0: + liveins: %d0, %p0 + + %r2 = A2_tfrt %p0, %r0 + %r0 = A2_tfr %r1 + %r2 = A2_tfrf %p0, killed %r1 +... + diff --git a/test/CodeGen/Hexagon/mux-kill2.mir b/test/CodeGen/Hexagon/mux-kill2.mir new file mode 100644 index 000000000000..5f34097af7cf --- /dev/null +++ b/test/CodeGen/Hexagon/mux-kill2.mir @@ -0,0 +1,17 @@ +# RUN: llc -march=hexagon -run-pass hexagon-gen-mux -o - -verify-machineinstrs %s | FileCheck %s +# CHECK: %r1 = C2_muxri %p0, 123, %r0 +# CHECK: %r2 = C2_muxir %p0, killed %r0, 321 +--- +name: fred +tracksRegLiveness: true + +body: | + bb.0: + liveins: %r0, %p0 + + %r2 = A2_tfrt %p0, %r0 + %r1 = C2_cmoveit %p0, 123 + %r1 = A2_tfrf %p0, killed %r0, implicit killed %r1 + %r2 = C2_cmoveif killed %p0, 321, implicit killed %r2 +... + diff --git a/test/CodeGen/Hexagon/store-imm-stack-object.ll b/test/CodeGen/Hexagon/store-imm-stack-object.ll new file mode 100644 index 000000000000..8de310953aee --- /dev/null +++ b/test/CodeGen/Hexagon/store-imm-stack-object.ll @@ -0,0 +1,86 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +target triple = "hexagon" + +; CHECK-LABEL: test1: +; CHECK: [[REG1:(r[0-9]+)]] = ##875770417 +; CHECK-DAG: memw(r29+#4) = [[REG1]] +; CHECK-DAG: memw(r29+#8) = #51 +; CHECK-DAG: memh(r29+#12) = #50 +; CHECK-DAG: memb(r29+#15) = #49 +define void @test1() { +b0: + %v1 = alloca [1 x i8], align 1 + %v2 = alloca i16, align 2 + %v3 = alloca i32, align 4 + %v4 = alloca i32, align 4 + %v5 = getelementptr inbounds [1 x i8], [1 x i8]* %v1, i32 0, i32 0 + call void @llvm.lifetime.start(i64 1, i8* %v5) + store i8 49, i8* %v5, align 1 + %v6 = bitcast i16* %v2 to i8* + call void @llvm.lifetime.start(i64 2, i8* %v6) + store i16 50, i16* %v2, align 2 + %v7 = bitcast i32* %v3 to i8* + call void @llvm.lifetime.start(i64 4, i8* %v7) + store i32 51, i32* %v3, align 4 + %v8 = bitcast i32* %v4 to i8* + call void @llvm.lifetime.start(i64 4, i8* %v8) + store i32 875770417, i32* %v4, align 4 + call void @test4(i8* %v5, i8* %v6, i8* %v7, i8* %v8) + call void @llvm.lifetime.end(i64 4, i8* %v8) + call void @llvm.lifetime.end(i64 4, i8* %v7) + call void @llvm.lifetime.end(i64 2, i8* %v6) + call void @llvm.lifetime.end(i64 1, i8* %v5) + ret void +} + +; CHECK-LABEL: test2: +; CHECK-DAG: memw(r29+#208) = #51 +; CHECK-DAG: memh(r29+#212) = r{{[0-9]+}} +; CHECK-DAG: memb(r29+#215) = r{{[0-9]+}} +define void @test2() { +b0: + %v1 = alloca [1 x i8], align 1 + %v2 = alloca i16, align 2 + %v3 = alloca i32, align 4 + %v4 = alloca i32, align 4 + %v5 = alloca [100 x i8], align 8 + %v6 = alloca [101 x i8], align 8 + %v7 = getelementptr inbounds [1 x i8], [1 x i8]* %v1, i32 0, i32 0 + call void @llvm.lifetime.start(i64 1, i8* %v7) + store i8 49, i8* %v7, align 1 + %v8 = bitcast i16* %v2 to i8* + call void @llvm.lifetime.start(i64 2, i8* %v8) + store i16 50, i16* %v2, align 2 + %v9 = bitcast i32* %v3 to i8* + call void @llvm.lifetime.start(i64 4, i8* %v9) + store i32 51, i32* %v3, align 4 + %v10 = bitcast i32* %v4 to i8* + call void @llvm.lifetime.start(i64 4, i8* %v10) + store i32 875770417, i32* %v4, align 4 + %v11 = getelementptr inbounds [100 x i8], [100 x i8]* %v5, i32 0, i32 0 + call void @llvm.lifetime.start(i64 100, i8* %v11) + call void @llvm.memset.p0i8.i32(i8* %v11, i8 0, i32 100, i32 8, i1 false) + store i8 50, i8* %v11, align 8 + %v12 = getelementptr inbounds [101 x i8], [101 x i8]* %v6, i32 0, i32 0 + call void @llvm.lifetime.start(i64 101, i8* %v12) + call void @llvm.memset.p0i8.i32(i8* %v12, i8 0, i32 101, i32 8, i1 false) + store i8 49, i8* %v12, align 8 + call void @test3(i8* %v7, i8* %v8, i8* %v9, i8* %v10, i8* %v11, i8* %v12) + call void @llvm.lifetime.end(i64 101, i8* %v12) + call void @llvm.lifetime.end(i64 100, i8* %v11) + call void @llvm.lifetime.end(i64 4, i8* %v10) + call void @llvm.lifetime.end(i64 4, i8* %v9) + call void @llvm.lifetime.end(i64 2, i8* %v8) + call void @llvm.lifetime.end(i64 1, i8* %v7) + ret void +} + +declare void @llvm.lifetime.start(i64, i8* nocapture) #0 +declare void @llvm.lifetime.end(i64, i8* nocapture) #0 +declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i32, i1) #0 + +declare void @test3(i8*, i8*, i8*, i8*, i8*, i8*) +declare void @test4(i8*, i8*, i8*, i8*) + +attributes #0 = { argmemonly nounwind "target-cpu"="hexagonv60" } diff --git a/test/CodeGen/Mips/2008-06-05-Carry.ll b/test/CodeGen/Mips/2008-06-05-Carry.ll index c61e1cdedea7..5e6092fc7848 100644 --- a/test/CodeGen/Mips/2008-06-05-Carry.ll +++ b/test/CodeGen/Mips/2008-06-05-Carry.ll @@ -2,20 +2,21 @@ define i64 @add64(i64 %u, i64 %v) nounwind { entry: +; CHECK-LABEL: add64: ; CHECK: addu -; CHECK: sltu +; CHECK-DAG: sltu +; CHECK-DAG: addu ; CHECK: addu -; CHECK: addu - %tmp2 = add i64 %u, %v + %tmp2 = add i64 %u, %v ret i64 %tmp2 } define i64 @sub64(i64 %u, i64 %v) nounwind { entry: -; CHECK: sub64 +; CHECK-LABEL: sub64 +; CHECK-DAG: sltu +; CHECK-DAG: subu ; CHECK: subu -; CHECK: sltu -; CHECK: addu ; CHECK: subu %tmp2 = sub i64 %u, %v ret i64 %tmp2 diff --git a/test/CodeGen/Mips/brundef.ll b/test/CodeGen/Mips/brundef.ll new file mode 100644 index 000000000000..802556c7cabd --- /dev/null +++ b/test/CodeGen/Mips/brundef.ll @@ -0,0 +1,26 @@ +; RUN: llc -march=mips -mcpu=mips32 -verify-machineinstrs -o /dev/null < %s +; Confirm that MachineInstr branch simplification preserves +; register operand flags, such as the <undef> flag. + +define void @ham() { +bb: + %tmp = alloca i32, align 4 + %tmp13 = ptrtoint i32* %tmp to i32 + %tmp70 = icmp eq i32 undef, -1 + br i1 %tmp70, label %bb72, label %bb40 + +bb72: ; preds = %bb72, %bb + br i1 undef, label %bb40, label %bb72 + +bb40: ; preds = %bb72, %bb + %tmp41 = phi i32 [ %tmp13, %bb72 ], [ %tmp13, %bb ] + %tmp55 = inttoptr i32 %tmp41 to i32* + %tmp58 = insertelement <2 x i32*> undef, i32* %tmp55, i32 1 + br label %bb59 + +bb59: ; preds = %bb59, %bb40 + %tmp60 = phi <2 x i32*> [ %tmp61, %bb59 ], [ %tmp58, %bb40 ] + %tmp61 = getelementptr i32, <2 x i32*> %tmp60, <2 x i32> <i32 -1, i32 1> + %tmp62 = extractelement <2 x i32*> %tmp61, i32 1 + br label %bb59 +} diff --git a/test/CodeGen/Mips/dsp-patterns.ll b/test/CodeGen/Mips/dsp-patterns.ll index 837c0d8bfc52..250d3eff37dc 100644 --- a/test/CodeGen/Mips/dsp-patterns.ll +++ b/test/CodeGen/Mips/dsp-patterns.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s -check-prefix=R1 -; RUN: llc -march=mips -mattr=dspr2 < %s | FileCheck %s -check-prefix=R2 +; RUN: llc -march=mips -mcpu=mips32r2 -mattr=dsp < %s | FileCheck %s -check-prefix=R1 +; RUN: llc -march=mips -mcpu=mips32r2 -mattr=dspr2 < %s | FileCheck %s -check-prefix=R2 ; R1-LABEL: test_lbux: ; R1: lbux ${{[0-9]+}} diff --git a/test/CodeGen/Mips/llcarry.ll b/test/CodeGen/Mips/llcarry.ll index fcf129420234..b7cc6fc8ea75 100644 --- a/test/CodeGen/Mips/llcarry.ll +++ b/test/CodeGen/Mips/llcarry.ll @@ -14,9 +14,9 @@ entry: %add = add nsw i64 %1, %0 store i64 %add, i64* @k, align 8 ; 16: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} -; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} -; 16: move ${{[0-9]+}}, $t8 ; 16: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} +; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} +; 16: move ${{[0-9]+}}, $24 ; 16: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} ret void } @@ -28,8 +28,8 @@ entry: %sub = sub nsw i64 %0, %1 ; 16: subu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} -; 16: move ${{[0-9]+}}, $t8 -; 16: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} +; 16: move ${{[0-9]+}}, $24 +; 16: subu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} ; 16: subu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} store i64 %sub, i64* @l, align 8 ret void @@ -41,8 +41,7 @@ entry: %add = add nsw i64 %0, 15 ; 16: addiu ${{[0-9]+}}, 15 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} -; 16: move ${{[0-9]+}}, $t8 -; 16: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} +; 16: move ${{[0-9]+}}, $24 ; 16: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} store i64 %add, i64* @m, align 8 ret void diff --git a/test/CodeGen/Mips/llvm-ir/add.ll b/test/CodeGen/Mips/llvm-ir/add.ll index a5ecdda94ce2..63884eb03b8c 100644 --- a/test/CodeGen/Mips/llvm-ir/add.ll +++ b/test/CodeGen/Mips/llvm-ir/add.ll @@ -1,35 +1,35 @@ ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefixes=ALL,NOT-R2-R6,GP32 +; RUN: -check-prefixes=ALL,NOT-R2-R6,GP32,PRE4 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefixes=ALL,NOT-R2-R6,GP32 +; RUN: -check-prefixes=ALL,NOT-R2-R6,GP32,GP32-CMOV ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefixes=ALL,R2-R6,GP32 +; RUN: -check-prefixes=ALL,R2-R6,GP32,GP32-CMOV ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefixes=ALL,R2-R6,GP32 +; RUN: -check-prefixes=ALL,R2-R6,GP32,GP32-CMOV ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefixes=ALL,R2-R6,GP32 +; RUN: -check-prefixes=ALL,R2-R6,GP32,GP32-CMOV ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ ; RUN: -check-prefixes=ALL,R2-R6,GP32 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64 +; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64,GP64-NOT-R2-R6 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64 +; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64,GP64-NOT-R2-R6 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64 +; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64,GP64-NOT-R2-R6 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefixes=ALL,R2-R6,GP64 +; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefixes=ALL,R2-R6,GP64 +; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefixes=ALL,R2-R6,GP64 +; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefixes=ALL,R2-R6,GP64 +; RUN: -check-prefixes=ALL,R2-R6,GP64,GP64-R2-R6 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -O2 -verify-machineinstrs | FileCheck %s \ -; RUN: -check-prefixes=ALL,MMR6,MM32 +; RUN: -check-prefixes=ALL,MMR3,MM32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR6,MM32 ; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -O2 | FileCheck %s \ -; RUN: -check-prefixes=ALL,MMR6,MM64 +; RUN: -check-prefixes=ALL,MM64 ; FIXME: This code sequence is inefficient as it should be 'subu $[[T0]], $zero, $[[T0]'. @@ -110,17 +110,17 @@ define signext i64 @add_i64(i64 signext %a, i64 signext %b) { entry: ; ALL-LABEL: add_i64: - ; GP32: addu $3, $5, $7 - ; GP32: sltu $[[T0:[0-9]+]], $3, $7 - ; GP32: addu $[[T1:[0-9]+]], $[[T0]], $6 - ; GP32: addu $2, $4, $[[T1]] + ; GP32-DAG: addu $[[T0:[0-9]+]], $4, $6 + ; GP32-DAG: addu $3, $5, $7 + ; GP32: sltu $[[T1:[0-9]+]], $3, $5 + ; GP32: addu $2, $[[T0]], $[[T1]] ; GP64: daddu $2, $4, $5 - ; MM32: addu16 $3, $5, $7 - ; MM32: sltu $[[T0:[0-9]+]], $3, $7 - ; MM32: addu $[[T1:[0-9]+]], $[[T0]], $6 - ; MM32: addu $2, $4, $[[T1]] + ; MM32-DAG: addu16 $3, $5, $7 + ; MM32-DAG: addu16 $[[T0:[0-9]+]], $4, $6 + ; MM32: sltu $[[T1:[0-9]+]], $3, $5 + ; MM32: addu16 $2, $[[T0]], $[[T1]] ; MM64: daddu $2, $4, $5 @@ -132,49 +132,108 @@ define signext i128 @add_i128(i128 signext %a, i128 signext %b) { entry: ; ALL-LABEL: add_i128: - ; GP32: lw $[[T0:[0-9]+]], 28($sp) - ; GP32: addu $[[T1:[0-9]+]], $7, $[[T0]] - ; GP32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]] - ; GP32: lw $[[T3:[0-9]+]], 24($sp) - ; GP32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]] - ; GP32: addu $[[T5:[0-9]+]], $6, $[[T4]] - ; GP32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]] - ; GP32: lw $[[T7:[0-9]+]], 20($sp) - ; GP32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]] - ; GP32: lw $[[T9:[0-9]+]], 16($sp) - ; GP32: addu $3, $5, $[[T8]] - ; GP32: sltu $[[T10:[0-9]+]], $3, $[[T7]] - ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T9]] - ; GP32: addu $2, $4, $[[T11]] - ; GP32: move $4, $[[T5]] - ; GP32: move $5, $[[T1]] - - ; GP64: daddu $3, $5, $7 - ; GP64: sltu $[[T0:[0-9]+]], $3, $7 - ; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6 - ; GP64: daddu $2, $4, $[[T1]] - - ; MM32: lw $[[T0:[0-9]+]], 28($sp) - ; MM32: addu $[[T1:[0-9]+]], $7, $[[T0]] - ; MM32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]] - ; MM32: lw $[[T3:[0-9]+]], 24($sp) - ; MM32: addu16 $[[T4:[0-9]+]], $[[T2]], $[[T3]] - ; MM32: addu16 $[[T5:[0-9]+]], $6, $[[T4]] - ; MM32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]] - ; MM32: lw $[[T7:[0-9]+]], 20($sp) - ; MM32: addu16 $[[T8:[0-9]+]], $[[T6]], $[[T7]] - ; MM32: lw $[[T9:[0-9]+]], 16($sp) - ; MM32: addu16 $[[T10:[0-9]+]], $5, $[[T8]] - ; MM32: sltu $[[T11:[0-9]+]], $[[T10]], $[[T7]] - ; MM32: addu $[[T12:[0-9]+]], $[[T11]], $[[T9]] - ; MM32: addu16 $[[T13:[0-9]+]], $4, $[[T12]] - ; MM32: move $4, $[[T5]] - ; MM32: move $5, $[[T1]] - + ; PRE4: move $[[R1:[0-9]+]], $5 + ; PRE4: move $[[R2:[0-9]+]], $4 + ; PRE4: lw $[[R3:[0-9]+]], 24($sp) + ; PRE4: addu $[[R4:[0-9]+]], $6, $[[R3]] + ; PRE4: lw $[[R5:[0-9]+]], 28($sp) + ; PRE4: addu $[[R6:[0-9]+]], $7, $[[R5]] + ; PRE4: sltu $[[R7:[0-9]+]], $[[R6]], $7 + ; PRE4: addu $[[R8:[0-9]+]], $[[R4]], $[[R7]] + ; PRE4: xor $[[R9:[0-9]+]], $[[R8]], $6 + ; PRE4: sltiu $[[R10:[0-9]+]], $[[R9]], 1 + ; PRE4: bnez $[[R10]], $BB5_2 + ; PRE4: sltu $[[R7]], $[[R8]], $6 + ; PRE4: lw $[[R12:[0-9]+]], 20($sp) + ; PRE4: addu $[[R13:[0-9]+]], $[[R1]], $[[R12]] + ; PRE4: lw $[[R14:[0-9]+]], 16($sp) + ; PRE4: addu $[[R15:[0-9]+]], $[[R13]], $[[R7]] + ; PRE4: addu $[[R16:[0-9]+]], $[[R2]], $[[R14]] + ; PRE4: sltu $[[R17:[0-9]+]], $[[R15]], $[[R13]] + ; PRE4: sltu $[[R18:[0-9]+]], $[[R13]], $[[R1]] + ; PRE4: addu $[[R19:[0-9]+]], $[[R16]], $[[R18]] + ; PRE4: addu $2, $[[R19]], $[[R17]] + + ; GP32-CMOV: lw $[[T0:[0-9]+]], 24($sp) + ; GP32-CMOV: addu $[[T1:[0-9]+]], $6, $[[T0]] + ; GP32-CMOV: lw $[[T2:[0-9]+]], 28($sp) + ; GP32-CMOV: addu $[[T3:[0-9]+]], $7, $[[T2]] + ; GP32-CMOV: sltu $[[T4:[0-9]+]], $[[T3]], $7 + ; GP32-CMOV: addu $[[T5:[0-9]+]], $[[T1]], $[[T4]] + ; GP32-CMOV: sltu $[[T6:[0-9]+]], $[[T5]], $6 + ; GP32-CMOV: xor $[[T7:[0-9]+]], $[[T5]], $6 + ; GP32-CMOV: movz $[[T8:[0-9]+]], $[[T4]], $[[T7]] + ; GP32-CMOV: lw $[[T9:[0-9]+]], 20($sp) + ; GP32-CMOV: addu $[[T10:[0-9]+]], $5, $[[T4]] + ; GP32-CMOV: addu $[[T11:[0-9]+]], $[[T10]], $[[T8]] + ; GP32-CMOV: lw $[[T12:[0-9]+]], 16($sp) + ; GP32-CMOV: sltu $[[T13:[0-9]+]], $[[T11]], $[[T10]] + ; GP32-CMOV: addu $[[T14:[0-9]+]], $4, $[[T12]] + ; GP32-CMOV: sltu $[[T15:[0-9]+]], $[[T10]], $5 + ; GP32-CMOV: addu $[[T16:[0-9]+]], $[[T14]], $[[T15]] + ; GP32-CMOV: addu $[[T17:[0-9]+]], $[[T16]], $[[T13]] + ; GP32-CMOV: move $4, $[[T5]] + ; GP32-CMOV: move $5, $[[T3]] + + ; GP64: daddu $[[T0:[0-9]+]], $4, $6 + ; GP64: daddu $[[T1:[0-9]+]], $5, $7 + ; GP64: sltu $[[T2:[0-9]+]], $[[T1]], $5 + ; GP64-NOT-R2-R6: dsll $[[T3:[0-9]+]], $[[T2]], 32 + ; GP64-NOT-R2-R6: dsrl $[[T4:[0-9]+]], $[[T3]], 32 + ; GP64-R2-R6: dext $[[T4:[0-9]+]], $[[T2]], 0, 32 + + ; GP64: daddu $2, $[[T0]], $[[T4]] + + ; MMR3: move $[[T1:[0-9]+]], $5 + ; MMR3-DAG: lw $[[T2:[0-9]+]], 32($sp) + ; MMR3: addu16 $[[T3:[0-9]+]], $6, $[[T2]] + ; MMR3-DAG: lw $[[T4:[0-9]+]], 36($sp) + ; MMR3: addu16 $[[T5:[0-9]+]], $7, $[[T4]] + ; MMR3: sltu $[[T6:[0-9]+]], $[[T5]], $7 + ; MMR3: addu16 $[[T7:[0-9]+]], $[[T3]], $[[T6]] + ; MMR3: sltu $[[T8:[0-9]+]], $[[T7]], $6 + ; MMR3: xor $[[T9:[0-9]+]], $[[T7]], $6 + ; MMR3: movz $[[T8]], $[[T6]], $[[T9]] + ; MMR3: lw $[[T10:[0-9]+]], 28($sp) + ; MMR3: addu16 $[[T11:[0-9]+]], $[[T1]], $[[T10]] + ; MMR3: addu16 $[[T12:[0-9]+]], $[[T11]], $[[T8]] + ; MMR3: lw $[[T13:[0-9]+]], 24($sp) + ; MMR3: sltu $[[T14:[0-9]+]], $[[T12]], $[[T11]] + ; MMR3: addu16 $[[T15:[0-9]+]], $4, $[[T13]] + ; MMR3: sltu $[[T16:[0-9]+]], $[[T11]], $[[T1]] + ; MMR3: addu16 $[[T17:[0-9]+]], $[[T15]], $[[T16]] + ; MMR3: addu16 $2, $2, $[[T14]] + + ; MMR6: move $[[T1:[0-9]+]], $5 + ; MMR6: move $[[T2:[0-9]+]], $4 + ; MMR6: lw $[[T3:[0-9]+]], 32($sp) + ; MMR6: addu16 $[[T4:[0-9]+]], $6, $[[T3]] + ; MMR6: lw $[[T5:[0-9]+]], 36($sp) + ; MMR6: addu16 $[[T6:[0-9]+]], $7, $[[T5]] + ; MMR6: sltu $[[T7:[0-9]+]], $[[T6]], $7 + ; MMR6: addu16 $[[T8:[0-9]+]], $[[T4]], $7 + ; MMR6: sltu $[[T9:[0-9]+]], $[[T8]], $6 + ; MMR6: xor $[[T10:[0-9]+]], $[[T4]], $6 + ; MMR6: sltiu $[[T11:[0-9]+]], $[[T10]], 1 + ; MMR6: seleqz $[[T12:[0-9]+]], $[[T9]], $[[T11]] + ; MMR6: selnez $[[T13:[0-9]+]], $[[T7]], $[[T11]] + ; MMR6: lw $[[T14:[0-9]+]], 24($sp) + ; MMR6: or $[[T15:[0-9]+]], $[[T13]], $[[T12]] + ; MMR6: addu16 $[[T16:[0-9]+]], $[[T2]], $[[T14]] + ; MMR6: lw $[[T17:[0-9]+]], 28($sp) + ; MMR6: addu16 $[[T18:[0-9]+]], $[[T1]], $[[T17]] + ; MMR6: addu16 $[[T19:[0-9]+]], $[[T18]], $[[T15]] + ; MMR6: sltu $[[T20:[0-9]+]], $[[T18]], $[[T1]] + ; MMR6: sltu $[[T21:[0-9]+]], $[[T17]], $[[T18]] + ; MMR6: addu16 $2, $[[T16]], $[[T20]] + ; MMR6: addu16 $2, $[[T20]], $[[T21]] + + ; MM64: daddu $[[T0:[0-9]+]], $4, $6 ; MM64: daddu $3, $5, $7 - ; MM64: sltu $[[T0:[0-9]+]], $3, $7 - ; MM64: daddu $[[T1:[0-9]+]], $[[T0]], $6 - ; MM64: daddu $2, $4, $[[T1]] + ; MM64: sltu $[[T1:[0-9]+]], $3, $5 + ; MM64: dsll $[[T2:[0-9]+]], $[[T1]], 32 + ; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32 + ; MM64: daddu $2, $[[T0]], $[[T3]] %r = add i128 %a, %b ret i128 %r @@ -249,17 +308,16 @@ define signext i32 @add_i32_4(i32 signext %a) { define signext i64 @add_i64_4(i64 signext %a) { ; ALL-LABEL: add_i64_4: - ; GP32: addiu $[[T0:[0-9]+]], $5, 4 - ; GP32: addiu $[[T1:[0-9]+]], $zero, 4 - ; GP32: sltu $[[T1]], $[[T0]], $[[T1]] - ; GP32: addu $2, $4, $[[T1]] + ; GP32: addiu $3, $5, 4 + ; GP32: sltu $[[T0:[0-9]+]], $3, $5 + ; GP32: addu $2, $4, $[[T0]] + + ; MM32: addiur2 $[[T1:[0-9]+]], $5, 4 + ; MM32: sltu $[[T2:[0-9]+]], $[[T1]], $5 + ; MM32: addu16 $2, $4, $[[T2]] ; GP64: daddiu $2, $4, 4 - ; MM32: addiu $[[T0:[0-9]+]], $5, 4 - ; MM32: li16 $[[T1:[0-9]+]], 4 - ; MM32: sltu $[[T2:[0-9]+]], $[[T0]], $[[T1]] - ; MM32: addu $2, $4, $[[T2]] ; MM64: daddiu $2, $4, 4 @@ -270,38 +328,67 @@ define signext i64 @add_i64_4(i64 signext %a) { define signext i128 @add_i128_4(i128 signext %a) { ; ALL-LABEL: add_i128_4: - ; GP32: addiu $[[T0:[0-9]+]], $7, 4 - ; GP32: addiu $[[T1:[0-9]+]], $zero, 4 - ; GP32: sltu $[[T1]], $[[T0]], $[[T1]] - ; GP32: addu $[[T2:[0-9]+]], $6, $[[T1]] - ; GP32: sltu $[[T1]], $[[T2]], $zero - ; GP32: addu $[[T3:[0-9]+]], $5, $[[T1]] - ; GP32: sltu $[[T1]], $[[T3]], $zero - ; GP32: addu $[[T1]], $4, $[[T1]] - ; GP32: move $4, $[[T2]] - ; GP32: move $5, $[[T0]] - - ; GP64: daddiu $[[T0:[0-9]+]], $5, 4 - ; GP64: daddiu $[[T1:[0-9]+]], $zero, 4 - ; GP64: sltu $[[T1]], $[[T0]], $[[T1]] - ; GP64: daddu $2, $4, $[[T1]] - - ; MM32: addiu $[[T0:[0-9]+]], $7, 4 - ; MM32: li16 $[[T1:[0-9]+]], 4 - ; MM32: sltu $[[T1]], $[[T0]], $[[T1]] - ; MM32: addu16 $[[T2:[0-9]+]], $6, $[[T1]] - ; MM32: li16 $[[T1]], 0 - ; MM32: sltu $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; MM32: addu16 $[[T3]], $5, $[[T3]] - ; MM32: sltu $[[T1]], $[[T3]], $[[T1]] - ; MM32: addu16 $[[T1]], $4, $[[T1]] - ; MM32: move $4, $[[T2]] - ; MM32: move $5, $[[T0]] + ; PRE4: move $[[T0:[0-9]+]], $5 + ; PRE4: addiu $[[T1:[0-9]+]], $7, 4 + ; PRE4: sltu $[[T2:[0-9]+]], $[[T1]], $7 + ; PRE4: xori $[[T3:[0-9]+]], $[[T2]], 1 + ; PRE4: bnez $[[T3]], $BB[[BB0:[0-9_]+]] + ; PRE4: addu $[[T4:[0-9]+]], $6, $[[T2]] + ; PRE4: sltu $[[T5:[0-9]+]], $[[T4]], $6 + ; PRE4; $BB[[BB0:[0-9]+]]: + ; PRE4: addu $[[T6:[0-9]+]], $[[T0]], $[[T5]] + ; PRE4: sltu $[[T7:[0-9]+]], $[[T6]], $[[T0]] + ; PRE4: addu $[[T8:[0-9]+]], $4, $[[T7]] + ; PRE4: move $4, $[[T4]] + + ; GP32-CMOV: addiu $[[T0:[0-9]+]], $7, 4 + ; GP32-CMOV: sltu $[[T1:[0-9]+]], $[[T0]], $7 + ; GP32-CMOV: addu $[[T2:[0-9]+]], $6, $[[T1]] + ; GP32-CMOV: sltu $[[T3:[0-9]+]], $[[T2]], $6 + ; GP32-CMOV: movz $[[T3]], $[[T1]], $[[T1]] + ; GP32-CMOV: addu $[[T4:[0-9]+]], $5, $[[T3]] + ; GP32-CMOV: sltu $[[T5:[0-9]+]], $[[T4]], $5 + ; GP32-CMOV: addu $[[T7:[0-9]+]], $4, $[[T5]] + ; GP32-CMOV: move $4, $[[T2]] + ; GP32-CMOV: move $5, $[[T0]] + + ; GP64: daddiu $[[T0:[0-9]+]], $5, 4 + ; GP64: sltu $[[T1:[0-9]+]], $[[T0]], $5 + ; GP64-NOT-R2-R6: dsll $[[T2:[0-9]+]], $[[T1]], 32 + ; GP64-NOT-R2-R6: dsrl $[[T3:[0-9]+]], $[[T2]], 32 + ; GP64-R2-R6: dext $[[T3:[0-9]+]], $[[T1]], 0, 32 + + ; GP64: daddu $2, $4, $[[T3]] + + ; MMR3: addiur2 $[[T0:[0-9]+]], $7, 4 + ; MMR3: sltu $[[T1:[0-9]+]], $[[T0]], $7 + ; MMR3: sltu $[[T2:[0-9]+]], $[[T0]], $7 + ; MMR3: addu16 $[[T3:[0-9]+]], $6, $[[T2]] + ; MMR3: sltu $[[T4:[0-9]+]], $[[T3]], $6 + ; MMR3: movz $[[T4]], $[[T2]], $[[T1]] + ; MMR3: addu16 $[[T6:[0-9]+]], $5, $[[T4]] + ; MMR3: sltu $[[T7:[0-9]+]], $[[T6]], $5 + ; MMR3: addu16 $2, $4, $[[T7]] + + ; MMR6: addiur2 $[[T1:[0-9]+]], $7, 4 + ; MMR6: sltu $[[T2:[0-9]+]], $[[T1]], $7 + ; MMR6: xori $[[T3:[0-9]+]], $[[T2]], 1 + ; MMR6: selnez $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; MMR6: addu16 $[[T5:[0-9]+]], $6, $[[T2]] + ; MMR6: sltu $[[T6:[0-9]+]], $[[T5]], $6 + ; MMR6: seleqz $[[T7:[0-9]+]], $[[T6]], $[[T3]] + ; MMR6: or $[[T8:[0-9]+]], $[[T4]], $[[T7]] + ; MMR6: addu16 $[[T9:[0-9]+]], $5, $[[T8]] + ; MMR6: sltu $[[T10:[0-9]+]], $[[T9]], $5 + ; MMR6: addu16 $[[T11:[0-9]+]], $4, $[[T10]] + ; MMR6: move $4, $7 + ; MMR6: move $5, $[[T1]] ; MM64: daddiu $[[T0:[0-9]+]], $5, 4 - ; MM64: daddiu $[[T1:[0-9]+]], $zero, 4 - ; MM64: sltu $[[T1]], $[[T0]], $[[T1]] - ; MM64: daddu $2, $4, $[[T1]] + ; MM64: sltu $[[T1:[0-9]+]], $[[T0]], $5 + ; MM64: dsll $[[T2:[0-9]+]], $[[T1]], 32 + ; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32 + ; MM64: daddu $2, $4, $[[T3]] %r = add i128 4, %a ret i128 %r @@ -380,16 +467,15 @@ define signext i64 @add_i64_3(i64 signext %a) { ; ALL-LABEL: add_i64_3: ; GP32: addiu $[[T0:[0-9]+]], $5, 3 - ; GP32: addiu $[[T1:[0-9]+]], $zero, 3 - ; GP32: sltu $[[T1]], $[[T0]], $[[T1]] + ; GP32: sltu $[[T1:[0-9]+]], $[[T0]], $5 ; GP32: addu $2, $4, $[[T1]] ; GP64: daddiu $2, $4, 3 - ; MM32: addiu $[[T0:[0-9]+]], $5, 3 - ; MM32: li16 $[[T1:[0-9]+]], 3 - ; MM32: sltu $[[T2:[0-9]+]], $[[T0]], $[[T1]] - ; MM32: addu $2, $4, $[[T2]] + ; MM32: move $[[T1:[0-9]+]], $5 + ; MM32: addius5 $[[T1]], 3 + ; MM32: sltu $[[T2:[0-9]+]], $[[T1]], $5 + ; MM32: addu16 $2, $4, $[[T2]] ; MM64: daddiu $2, $4, 3 @@ -400,38 +486,70 @@ define signext i64 @add_i64_3(i64 signext %a) { define signext i128 @add_i128_3(i128 signext %a) { ; ALL-LABEL: add_i128_3: - ; GP32: addiu $[[T0:[0-9]+]], $7, 3 - ; GP32: addiu $[[T1:[0-9]+]], $zero, 3 - ; GP32: sltu $[[T1]], $[[T0]], $[[T1]] - ; GP32: addu $[[T2:[0-9]+]], $6, $[[T1]] - ; GP32: sltu $[[T3:[0-9]+]], $[[T2]], $zero - ; GP32: addu $[[T4:[0-9]+]], $5, $[[T3]] - ; GP32: sltu $[[T5:[0-9]+]], $[[T4]], $zero - ; GP32: addu $[[T5]], $4, $[[T5]] - ; GP32: move $4, $[[T2]] - ; GP32: move $5, $[[T0]] - - ; GP64: daddiu $[[T0:[0-9]+]], $5, 3 - ; GP64: daddiu $[[T1:[0-9]+]], $zero, 3 - ; GP64: sltu $[[T1]], $[[T0]], $[[T1]] - ; GP64: daddu $2, $4, $[[T1]] - - ; MM32: addiu $[[T0:[0-9]+]], $7, 3 - ; MM32: li16 $[[T1:[0-9]+]], 3 - ; MM32: sltu $[[T1]], $[[T0]], $[[T1]] - ; MM32: addu16 $[[T2:[0-9]+]], $6, $[[T1]] - ; MM32: li16 $[[T3:[0-9]+]], 0 - ; MM32: sltu $[[T4:[0-9]+]], $[[T2]], $[[T3]] - ; MM32: addu16 $[[T4]], $5, $[[T4]] - ; MM32: sltu $[[T5:[0-9]+]], $[[T4]], $[[T3]] - ; MM32: addu16 $[[T5]], $4, $[[T5]] - ; MM32: move $4, $[[T2]] - ; MM32: move $5, $[[T0]] + ; PRE4: move $[[T0:[0-9]+]], $5 + ; PRE4: addiu $[[T1:[0-9]+]], $7, 3 + ; PRE4: sltu $[[T2:[0-9]+]], $[[T1]], $7 + ; PRE4: xori $[[T3:[0-9]+]], $[[T2]], 1 + ; PRE4: bnez $[[T3]], $BB[[BB0:[0-9_]+]] + ; PRE4: addu $[[T4:[0-9]+]], $6, $[[T2]] + ; PRE4: sltu $[[T5:[0-9]+]], $[[T4]], $6 + ; PRE4; $BB[[BB0:[0-9]+]]: + ; PRE4: addu $[[T6:[0-9]+]], $[[T0]], $[[T5]] + ; PRE4: sltu $[[T7:[0-9]+]], $[[T6]], $[[T0]] + ; PRE4: addu $[[T8:[0-9]+]], $4, $[[T7]] + ; PRE4: move $4, $[[T4]] + + ; GP32-CMOV: addiu $[[T0:[0-9]+]], $7, 3 + ; GP32-CMOV: sltu $[[T1:[0-9]+]], $[[T0]], $7 + ; GP32-CMOV: addu $[[T2:[0-9]+]], $6, $[[T1]] + ; GP32-CMOV: sltu $[[T3:[0-9]+]], $[[T2]], $6 + ; GP32-CMOV: movz $[[T3]], $[[T1]], $[[T1]] + ; GP32-CMOV: addu $[[T4:[0-9]+]], $5, $[[T3]] + ; GP32-CMOV: sltu $[[T5:[0-9]+]], $[[T4]], $5 + ; GP32-CMOV: addu $[[T7:[0-9]+]], $4, $[[T5]] + ; GP32-CMOV: move $4, $[[T2]] + ; GP32-CMOV: move $5, $[[T0]] + + ; GP64: daddiu $[[T0:[0-9]+]], $5, 3 + ; GP64: sltu $[[T1:[0-9]+]], $[[T0]], $5 + + ; GP64-NOT-R2-R6: dsll $[[T2:[0-9]+]], $[[T1]], 32 + ; GP64-NOT-R2-R6: dsrl $[[T3:[0-9]+]], $[[T2]], 32 + ; GP64-R2-R6: dext $[[T3:[0-9]+]], $[[T1]], 0, 32 + + ; GP64: daddu $2, $4, $[[T3]] + + ; MMR3: move $[[T1:[0-9]+]], $7 + ; MMR3: addius5 $[[T1]], 3 + ; MMR3: sltu $[[T2:[0-9]+]], $[[T1]], $7 + ; MMR3: sltu $[[T3:[0-9]+]], $[[T1]], $7 + ; MMR3: addu16 $[[T4:[0-9]+]], $6, $[[T3]] + ; MMR3: sltu $[[T5:[0-9]+]], $[[T4]], $6 + ; MMR3: movz $[[T5]], $[[T3]], $[[T2]] + ; MMR3: addu16 $[[T6:[0-9]+]], $5, $[[T5]] + ; MMR3: sltu $[[T7:[0-9]+]], $[[T6]], $5 + ; MMR3: addu16 $2, $4, $[[T7]] + + ; MMR6: move $[[T1:[0-9]+]], $7 + ; MMR6: addius5 $[[T1]], 3 + ; MMR6: sltu $[[T2:[0-9]+]], $[[T1]], $7 + ; MMR6: xori $[[T3:[0-9]+]], $[[T2]], 1 + ; MMR6: selnez $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; MMR6: addu16 $[[T5:[0-9]+]], $6, $[[T2]] + ; MMR6: sltu $[[T6:[0-9]+]], $[[T5]], $6 + ; MMR6: seleqz $[[T7:[0-9]+]], $[[T6]], $[[T3]] + ; MMR6: or $[[T8:[0-9]+]], $[[T4]], $[[T7]] + ; MMR6: addu16 $[[T9:[0-9]+]], $5, $[[T8]] + ; MMR6: sltu $[[T10:[0-9]+]], $[[T9]], $5 + ; MMR6: addu16 $[[T11:[0-9]+]], $4, $[[T10]] + ; MMR6: move $4, $[[T5]] + ; MMR6: move $5, $[[T1]] ; MM64: daddiu $[[T0:[0-9]+]], $5, 3 - ; MM64: daddiu $[[T1:[0-9]+]], $zero, 3 - ; MM64: sltu $[[T1]], $[[T0]], $[[T1]] - ; MM64: daddu $2, $4, $[[T1]] + ; MM64: sltu $[[T1:[0-9]+]], $[[T0]], $5 + ; MM64: dsll $[[T2:[0-9]+]], $[[T1]], 32 + ; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32 + ; MM64: daddu $2, $4, $[[T3]] %r = add i128 3, %a ret i128 %r diff --git a/test/CodeGen/Mips/llvm-ir/sub.ll b/test/CodeGen/Mips/llvm-ir/sub.ll index a730063c552f..655addb10a64 100644 --- a/test/CodeGen/Mips/llvm-ir/sub.ll +++ b/test/CodeGen/Mips/llvm-ir/sub.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefixes=NOT-R2-R6,GP32,GP32-NOT-MM,NOT-MM +; RUN: -check-prefixes=NOT-R2-R6,GP32,GP32-NOT-MM,NOT-MM,PRE4 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ ; RUN: -check-prefixes=NOT-R2-R6,GP32,GP32-NOT-MM,NOT-MM ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ @@ -11,25 +11,25 @@ ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ ; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \ -; RUN: -check-prefixes=GP32-MM,GP32,MM +; RUN: -check-prefixes=GP32-MM,GP32,MM32,MMR3 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=GP32-MM,GP32,MM +; RUN: -check-prefixes=GP32-MM,GP32,MM32,MMR6 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM +; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM,GP64-NOT-R2 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM +; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM,GP64-NOT-R2 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM +; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM,GP64-NOT-R2 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefixes=R2-R6,GP64,NOT-MM +; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefixes=R2-R6,GP64,NOT-MM +; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefixes=R2-R6,GP64,NOT-MM +; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefixes=R2-R6,GP64,NOT-MM +; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=GP64,MM +; RUN: -check-prefixes=GP64,MM64 define signext i1 @sub_i1(i1 signext %a, i1 signext %b) { entry: @@ -100,10 +100,15 @@ define signext i64 @sub_i64(i64 signext %a, i64 signext %b) { entry: ; ALL-LABEL: sub_i64: - ; GP32-NOT-MM subu $3, $5, $7 - ; GP32: sltu $[[T0:[0-9]+]], $5, $7 - ; GP32: addu $[[T1:[0-9]+]], $[[T0]], $6 - ; GP32: subu $2, $4, $[[T1]] + ; GP32-NOT-MM: sltu $[[T0:[0-9]+]], $5, $7 + ; GP32-NOT-MM: subu $2, $4, $6 + ; GP32-NOT-MM: subu $2, $2, $[[T0]] + ; GP32-NOT-MM: subu $3, $5, $7 + + ; MM32: sltu $[[T0:[0-9]+]], $5, $7 + ; MM32: subu16 $3, $4, $6 + ; MM32: subu16 $2, $3, $[[T0]] + ; MM32: subu16 $3, $5, $7 ; GP64: dsubu $2, $4, $5 @@ -115,42 +120,109 @@ define signext i128 @sub_i128(i128 signext %a, i128 signext %b) { entry: ; ALL-LABEL: sub_i128: - ; GP32-NOT-MM: lw $[[T0:[0-9]+]], 20($sp) - ; GP32-NOT-MM: sltu $[[T1:[0-9]+]], $5, $[[T0]] - ; GP32-NOT-MM: lw $[[T2:[0-9]+]], 16($sp) - ; GP32-NOT-MM: addu $[[T3:[0-9]+]], $[[T1]], $[[T2]] - ; GP32-NOT-MM: lw $[[T4:[0-9]+]], 24($sp) - ; GP32-NOT-MM: lw $[[T5:[0-9]+]], 28($sp) - ; GP32-NOT-MM: subu $[[T6:[0-9]+]], $7, $[[T5]] - ; GP32-NOT-MM: subu $2, $4, $[[T3]] - ; GP32-NOT-MM: sltu $[[T8:[0-9]+]], $6, $[[T4]] - ; GP32-NOT-MM: addu $[[T9:[0-9]+]], $[[T8]], $[[T0]] - ; GP32-NOT-MM: subu $3, $5, $[[T9]] - ; GP32-NOT-MM: sltu $[[T10:[0-9]+]], $7, $[[T5]] - ; GP32-NOT-MM: addu $[[T11:[0-9]+]], $[[T10]], $[[T4]] - ; GP32-NOT-MM: subu $4, $6, $[[T11]] - ; GP32-NOT-MM: move $5, $[[T6]] - - ; GP32-MM: lw $[[T0:[0-9]+]], 20($sp) - ; GP32-MM: sltu $[[T1:[0-9]+]], $[[T2:[0-9]+]], $[[T0]] - ; GP32-MM: lw $[[T3:[0-9]+]], 16($sp) - ; GP32-MM: addu $[[T3]], $[[T1]], $[[T3]] - ; GP32-MM: lw $[[T4:[0-9]+]], 24($sp) - ; GP32-MM: lw $[[T5:[0-9]+]], 28($sp) - ; GP32-MM: subu $[[T1]], $7, $[[T5]] - ; GP32-MM: subu16 $[[T3]], $[[T6:[0-9]+]], $[[T3]] - ; GP32-MM: sltu $[[T6]], $6, $[[T4]] - ; GP32-MM: addu16 $[[T0]], $[[T6]], $[[T0]] - ; GP32-MM: subu16 $[[T0]], $5, $[[T0]] - ; GP32-MM: sltu $[[T6]], $7, $[[T5]] - ; GP32-MM: addu $[[T6]], $[[T6]], $[[T4]] - ; GP32-MM: subu16 $[[T6]], $6, $[[T6]] - ; GP32-MM: move $[[T2]], $[[T1]] - - ; GP64: dsubu $3, $5, $7 - ; GP64: sltu $[[T0:[0-9]+]], $5, $7 - ; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6 - ; GP64: dsubu $2, $4, $[[T1]] +; PRE4: lw $[[T0:[0-9]+]], 24($sp) +; PRE4: lw $[[T1:[0-9]+]], 28($sp) +; PRE4: sltu $[[T2:[0-9]+]], $7, $[[T1]] +; PRE4: xor $[[T3:[0-9]+]], $6, $[[T0]] +; PRE4: sltiu $[[T4:[0-9]+]], $[[T3]], 1 +; PRE4: bnez $[[T4]] +; PRE4: move $[[T5:[0-9]+]], $[[T2]] +; PRE4: sltu $[[T5]], $6, $[[T0]] + +; PRE4: lw $[[T6:[0-9]+]], 20($sp) +; PRE4: subu $[[T7:[0-9]+]], $5, $[[T6]] +; PRE4: subu $[[T8:[0-9]+]], $[[T7]], $[[T5]] +; PRE4: sltu $[[T9:[0-9]+]], $[[T7]], $[[T5]] +; PRE4: sltu $[[T10:[0-9]+]], $5, $[[T6]] +; PRE4: lw $[[T11:[0-9]+]], 16($sp) +; PRE4: subu $[[T12:[0-9]+]], $4, $[[T11]] +; PRE4: subu $[[T13:[0-9]+]], $[[T12]], $[[T10]] +; PRE4: subu $[[T14:[0-9]+]], $[[T13]], $[[T9]] +; PRE4: subu $[[T15:[0-9]+]], $6, $[[T0]] +; PRE4: subu $[[T16:[0-9]+]], $[[T15]], $[[T2]] +; PRE4: subu $5, $7, $[[T1]] + +; MMR3: lw $[[T1:[0-9]+]], 48($sp) +; MMR3: sltu $[[T2:[0-9]+]], $6, $[[T1]] +; MMR3: xor $[[T3:[0-9]+]], $6, $[[T1]] +; MMR3: lw $[[T4:[0-9]+]], 52($sp) +; MMR3: sltu $[[T5:[0-9]+]], $7, $[[T4]] +; MMR3: movz $[[T6:[0-9]+]], $[[T5]], $[[T3]] +; MMR3: lw $[[T7:[0-8]+]], 44($sp) +; MMR3: subu16 $[[T8:[0-9]+]], $5, $[[T7]] +; MMR3: subu16 $[[T9:[0-9]+]], $[[T8]], $[[T6]] +; MMR3: sltu $[[T10:[0-9]+]], $[[T8]], $[[T2]] +; MMR3: sltu $[[T11:[0-9]+]], $5, $[[T7]] +; MMR3: lw $[[T12:[0-9]+]], 40($sp) +; MMR3: lw $[[T13:[0-9]+]], 12($sp) +; MMR3: subu16 $[[T14:[0-9]+]], $[[T13]], $[[T12]] +; MMR3: subu16 $[[T15:[0-9]+]], $[[T14]], $[[T11]] +; MMR3: subu16 $[[T16:[0-9]+]], $[[T15]], $[[T10]] +; MMR3: subu16 $[[T17:[0-9]+]], $6, $[[T1]] +; MMR3: subu16 $[[T18:[0-9]+]], $[[T17]], $7 +; MMR3: lw $[[T19:[0-9]+]], 8($sp) +; MMR3: lw $[[T20:[0-9]+]], 0($sp) +; MMR3: subu16 $5, $[[T19]], $[[T20]] + +; MMR6: move $[[T0:[0-9]+]], $7 +; MMR6: sw $[[T0]], 8($sp) +; MMR6: move $[[T1:[0-9]+]], $5 +; MMR6: sw $4, 12($sp) +; MMR6: lw $[[T2:[0-9]+]], 48($sp) +; MMR6: sltu $[[T3:[0-9]+]], $6, $[[T2]] +; MMR6: xor $[[T4:[0-9]+]], $6, $[[T2]] +; MMR6: sltiu $[[T5:[0-9]+]], $[[T4]], 1 +; MMR6: seleqz $[[T6:[0-9]+]], $[[T3]], $[[T5]] +; MMR6: lw $[[T7:[0-9]+]], 52($sp) +; MMR6: sltu $[[T8:[0-9]+]], $[[T0]], $[[T7]] +; MMR6: selnez $[[T9:[0-9]+]], $[[T8]], $[[T5]] +; MMR6: or $[[T10:[0-9]+]], $[[T9]], $[[T6]] +; MMR6: lw $[[T11:[0-9]+]], 44($sp) +; MMR6: subu16 $[[T12:[0-9]+]], $[[T1]], $[[T11]] +; MMR6: subu16 $[[T13:[0-9]+]], $[[T12]], $[[T7]] +; MMR6: sltu $[[T16:[0-9]+]], $[[T12]], $[[T7]] +; MMR6: sltu $[[T17:[0-9]+]], $[[T1]], $[[T11]] +; MMR6: lw $[[T18:[0-9]+]], 40($sp) +; MMR6: lw $[[T19:[0-9]+]], 12($sp) +; MMR6: subu16 $[[T20:[0-9]+]], $[[T19]], $[[T18]] +; MMR6: subu16 $[[T21:[0-9]+]], $[[T20]], $[[T17]] +; MMR6: subu16 $[[T22:[0-9]+]], $[[T21]], $[[T16]] +; MMR6: subu16 $[[T23:[0-9]+]], $6, $[[T2]] +; MMR6: subu16 $4, $[[T23]], $5 +; MMR6: lw $[[T24:[0-9]+]], 8($sp) +; MMR6: lw $[[T25:[0-9]+]], 0($sp) +; MMR6: subu16 $5, $[[T24]], $[[T25]] +; MMR6: lw $3, 4($sp) + +; FIXME: The sltu, dsll, dsrl pattern here occurs when an i32 is zero +; extended to 64 bits. Fortunately slt(i)(u) actually gives an i1. +; These should be combined away. + +; GP64-NOT-R2: dsubu $1, $4, $6 +; GP64-NOT-R2: sltu $[[T0:[0-9]+]], $5, $7 +; GP64-NOT-R2: dsll $[[T1:[0-9]+]], $[[T0]], 32 +; GP64-NOT-R2: dsrl $[[T2:[0-9]+]], $[[T1]], 32 +; GP64-NOT-R2: dsubu $2, $1, $[[T2]] +; GP64-NOT-R2: dsubu $3, $5, $7 + +; FIXME: Likewise for the sltu, dext here. + +; GP64-R2: dsubu $1, $4, $6 +; GP64-R2: sltu $[[T0:[0-9]+]], $5, $7 +; GP64-R2: dext $[[T1:[0-9]+]], $[[T0]], 0, 32 +; GP64-R2: dsubu $2, $1, $[[T1]] +; GP64-R2: dsubu $3, $5, $7 + +; FIXME: Again, redundant sign extension. Also, microMIPSR6 has the +; dext instruction which should be used here. + +; MM64: dsubu $[[T0:[0-9]+]], $4, $6 +; MM64: sltu $[[T1:[0-9]+]], $5, $7 +; MM64: dsll $[[T2:[0-9]+]], $[[T1]], 32 +; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32 +; MM64: dsubu $2, $[[T0]], $[[T3]] +; MM64: dsubu $3, $5, $7 +; MM64: jr $ra %r = sub i128 %a, %b ret i128 %r diff --git a/test/CodeGen/Mips/longbranch.ll b/test/CodeGen/Mips/longbranch.ll index 11bc6d390319..c616089c6df0 100644 --- a/test/CodeGen/Mips/longbranch.ll +++ b/test/CodeGen/Mips/longbranch.ll @@ -1,17 +1,17 @@ -; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -; RUN: llc -march=mipsel -force-mips-long-branch -O3 -relocation-model=pic < %s \ +; RUN: llc -march=mipsel -relocation-model=pic < %s -verify-machineinstrs | FileCheck %s +; RUN: llc -march=mipsel -force-mips-long-branch -O3 -relocation-model=pic < %s -verify-machineinstrs \ ; RUN: | FileCheck %s -check-prefix=O32 ; RUN: llc -march=mipsel -mcpu=mips32r6 -force-mips-long-branch -O3 \ -; RUN: -relocation-model=pic -asm-show-inst < %s | FileCheck %s -check-prefix=O32-R6 +; RUN: -relocation-model=pic -asm-show-inst < %s -verify-machineinstrs | FileCheck %s -check-prefix=O32-R6 ; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -force-mips-long-branch -O3 -relocation-model=pic \ -; RUN: < %s | FileCheck %s -check-prefix=N64 +; RUN: < %s -verify-machineinstrs | FileCheck %s -check-prefix=N64 ; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -force-mips-long-branch -O3 -relocation-model=pic \ -; RUN: < %s | FileCheck %s -check-prefix=N64 +; RUN: < %s -verify-machineinstrs | FileCheck %s -check-prefix=N64 ; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -force-mips-long-branch -O3 \ -; RUN: -relocation-model=pic -asm-show-inst < %s | FileCheck %s -check-prefix=N64-R6 +; RUN: -relocation-model=pic -asm-show-inst < %s -verify-machineinstrs | FileCheck %s -check-prefix=N64-R6 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=micromips \ -; RUN: -force-mips-long-branch -O3 -relocation-model=pic < %s | FileCheck %s -check-prefix=MICROMIPS -; RUN: llc -mtriple=mipsel-none-nacl -force-mips-long-branch -O3 -relocation-model=pic < %s \ +; RUN: -force-mips-long-branch -O3 -relocation-model=pic < %s -verify-machineinstrs | FileCheck %s -check-prefix=MICROMIPS +; RUN: llc -mtriple=mipsel-none-nacl -force-mips-long-branch -O3 -relocation-model=pic < %s -verify-machineinstrs \ ; RUN: | FileCheck %s -check-prefix=NACL @@ -59,9 +59,9 @@ end: ; Check for long branch expansion: ; O32: addiu $sp, $sp, -8 ; O32-NEXT: sw $ra, 0($sp) -; O32-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]])) +; O32-NEXT: lui $1, %hi(($BB0_[[BB2:[0-9]+]])-($[[BB1:BB[0-9_]+]])) ; O32-NEXT: bal $[[BB1]] -; O32-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]])) +; O32-NEXT: addiu $1, $1, %lo(($BB0_[[BB2]])-($[[BB1]])) ; O32-NEXT: $[[BB1]]: ; O32-NEXT: addu $1, $ra, $1 ; O32-NEXT: lw $ra, 0($sp) @@ -72,7 +72,7 @@ end: ; O32: lw $[[R1:[0-9]+]], %got(x)($[[GP]]) ; O32: addiu $[[R2:[0-9]+]], $zero, 1 ; O32: sw $[[R2]], 0($[[R1]]) -; O32: $[[BB2]]: +; O32: # BB#[[BB2]]: ; O32: jr $ra ; O32: nop @@ -90,10 +90,10 @@ end: ; Check for long branch expansion: ; N64: daddiu $sp, $sp, -16 ; N64-NEXT: sd $ra, 0($sp) -; N64-NEXT: daddiu $1, $zero, %hi([[BB2:\.LBB[0-9_]+]]-[[BB1:\.LBB[0-9_]+]]) +; N64-NEXT: daddiu $1, $zero, %hi(.LBB0_[[BB2:[0-9_]+]]-[[BB1:\.LBB[0-9_]+]]) ; N64-NEXT: dsll $1, $1, 16 ; N64-NEXT: bal [[BB1]] -; N64-NEXT: daddiu $1, $1, %lo([[BB2]]-[[BB1]]) +; N64-NEXT: daddiu $1, $1, %lo(.LBB0_[[BB2]]-[[BB1]]) ; N64-NEXT: [[BB1]]: ; N64-NEXT: daddu $1, $ra, $1 ; N64-NEXT: ld $ra, 0($sp) @@ -105,7 +105,7 @@ end: ; N64: addiu $[[R3:[0-9]+]], $zero, 1 ; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]]) ; N64: sw $[[R3]], 0($[[R2]]) -; N64: [[BB2]]: +; N64: # BB#[[BB2]]: ; N64: jr $ra ; N64: nop @@ -125,9 +125,9 @@ end: ; Check for long branch expansion: ; MICROMIPS: addiu $sp, $sp, -8 ; MICROMIPS-NEXT: sw $ra, 0($sp) -; MICROMIPS-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]])) +; MICROMIPS-NEXT: lui $1, %hi(($BB0_[[BB2:[0-9]+]])-($[[BB1:BB[0-9_]+]])) ; MICROMIPS-NEXT: bal $[[BB1]] -; MICROMIPS-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]])) +; MICROMIPS-NEXT: addiu $1, $1, %lo(($BB0_[[BB2]])-($[[BB1]])) ; MICROMIPS-NEXT: $[[BB1]]: ; MICROMIPS-NEXT: addu $1, $ra, $1 ; MICROMIPS-NEXT: lw $ra, 0($sp) @@ -138,7 +138,7 @@ end: ; MICROMIPS: lw $[[R1:[0-9]+]], %got(x)($[[GP]]) ; MICROMIPS: li16 $[[R2:[0-9]+]], 1 ; MICROMIPS: sw16 $[[R2]], 0($[[R1]]) -; MICROMIPS: $[[BB2]]: +; MICROMIPS: # BB#[[BB2]]: ; MICROMIPS: jrc $ra @@ -154,9 +154,9 @@ end: ; Check for long branch expansion: ; NACL: addiu $sp, $sp, -8 ; NACL-NEXT: sw $ra, 0($sp) -; NACL-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]])) +; NACL-NEXT: lui $1, %hi(($BB0_[[BB2:[0-9]+]])-($[[BB1:BB[0-9_]+]])) ; NACL-NEXT: bal $[[BB1]] -; NACL-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]])) +; NACL-NEXT: addiu $1, $1, %lo(($BB0_[[BB2]])-($[[BB1]])) ; NACL-NEXT: $[[BB1]]: ; NACL-NEXT: addu $1, $ra, $1 ; NACL-NEXT: lw $ra, 0($sp) @@ -169,7 +169,7 @@ end: ; NACL: addiu $[[R2:[0-9]+]], $zero, 1 ; NACL: sw $[[R2]], 0($[[R1]]) ; NACL: .p2align 4 -; NACL-NEXT: $[[BB2]]: +; NACL-NEXT: # BB#[[BB2]]: ; NACL: jr $ra ; NACL: nop } diff --git a/test/CodeGen/Mips/madd-msub.ll b/test/CodeGen/Mips/madd-msub.ll index 7baba005a072..3e1a2e8b9708 100644 --- a/test/CodeGen/Mips/madd-msub.ll +++ b/test/CodeGen/Mips/madd-msub.ll @@ -25,11 +25,11 @@ ; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}} ; 32R6-DAG: addu $[[T1:[0-9]+]], $[[T0]], $6 -; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $6 -; 32R6-DAG: sra $[[T3:[0-9]+]], $6, 31 -; 32R6-DAG: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]] -; 32R6-DAG: muh $[[T5:[0-9]+]], ${{[45]}}, ${{[45]}} -; 32R6-DAG: addu $2, $[[T5]], $[[T4]] +; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]] +; 32R6-DAG: muh $[[T3:[0-9]+]], ${{[45]}}, ${{[45]}} +; 32R6-DAG: sra $[[T4:[0-9]+]], $6, 31 +; 32R6-DAG: addu $[[T5:[0-9]+]], $[[T3]], $[[T4]] +; 32R6-DAG: addu $2, $[[T5]], $[[T2]] ; 64-DAG: sll $[[T0:[0-9]+]], $4, 0 ; 64-DAG: sll $[[T1:[0-9]+]], $5, 0 @@ -71,7 +71,7 @@ entry: ; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}} ; 32R6-DAG: addu $[[T1:[0-9]+]], $[[T0]], $6 -; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $6 +; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]] ; FIXME: There's a redundant move here. We should remove it ; 32R6-DAG: muhu $[[T3:[0-9]+]], ${{[45]}}, ${{[45]}} ; 32R6-DAG: addu $2, $[[T3]], $[[T2]] @@ -109,10 +109,10 @@ entry: ; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}} ; 32R6-DAG: addu $[[T1:[0-9]+]], $[[T0]], $7 -; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $7 -; 32R6-DAG: addu $[[T4:[0-9]+]], $[[T2]], $6 -; 32R6-DAG: muh $[[T5:[0-9]+]], ${{[45]}}, ${{[45]}} -; 32R6-DAG: addu $2, $[[T5]], $[[T4]] +; 32R6-DAG: sltu $[[T2:[0-9]+]], $[[T1]], $1 +; 32R6-DAG: muh $[[T3:[0-9]+]], ${{[45]}}, ${{[45]}} +; 32R6-DAG: addu $[[T4:[0-9]+]], $[[T3]], $6 +; 32R6-DAG: addu $2, $[[T4]], $[[T2]] ; 64-DAG: sll $[[T0:[0-9]+]], $4, 0 ; 64-DAG: sll $[[T1:[0-9]+]], $5, 0 @@ -134,6 +134,17 @@ entry: ret i64 %add } +; ALL-LABEL: madd4 +; ALL-NOT: madd ${{[0-9]+}}, ${{[0-9]+}} + +define i32 @madd4(i32 %a, i32 %b, i32 %c) { +entry: + %mul = mul nsw i32 %a, %b + %add = add nsw i32 %c, %mul + + ret i32 %add +} + ; ALL-LABEL: msub1: ; 32-DAG: sra $[[T0:[0-9]+]], $6, 31 @@ -148,13 +159,13 @@ entry: ; DSP-DAG: mfhi $2, $[[AC]] ; DSP-DAG: mflo $3, $[[AC]] -; 32R6-DAG: muh $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}} -; 32R6-DAG: mul $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}} -; 32R6-DAG: sltu $[[T3:[0-9]+]], $6, $[[T1]] -; 32R6-DAG: addu $[[T4:[0-9]+]], $[[T3]], $[[T0]] -; 32R6-DAG: sra $[[T5:[0-9]+]], $6, 31 -; 32R6-DAG: subu $2, $[[T5]], $[[T4]] -; 32R6-DAG: subu $3, $6, $[[T1]] +; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}} +; 32R6-DAG: sltu $[[T1:[0-9]+]], $6, $[[T0]] +; 32R6-DAG: muh $[[T2:[0-9]+]], ${{[45]}}, ${{[45]}} +; 32R6-DAG: sra $[[T3:[0-9]+]], $6, 31 +; 32R6-DAG: subu $[[T4:[0-9]+]], $[[T3]], $[[T2]] +; 32R6-DAG: subu $2, $[[T4]], $[[T1]] +; 32R6-DAG: subu $3, $6, $[[T0]] ; 64-DAG: sll $[[T0:[0-9]+]], $4, 0 ; 64-DAG: sll $[[T1:[0-9]+]], $5, 0 @@ -194,13 +205,12 @@ entry: ; DSP-DAG: mfhi $2, $[[AC]] ; DSP-DAG: mflo $3, $[[AC]] -; 32R6-DAG: muhu $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}} -; 32R6-DAG: mul $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}} - -; 32R6-DAG: sltu $[[T2:[0-9]+]], $6, $[[T1]] -; 32R6-DAG: addu $[[T3:[0-9]+]], $[[T2]], $[[T0]] -; 32R6-DAG: negu $2, $[[T3]] -; 32R6-DAG: subu $3, $6, $[[T1]] +; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}} +; 32R6-DAG: sltu $[[T1:[0-9]+]], $6, $[[T0]] +; 32R6-DAG: muhu $[[T2:[0-9]+]], ${{[45]}}, ${{[45]}} +; 32R6-DAG: negu $[[T3:[0-9]+]], $[[T2]] +; 32R6-DAG: subu $2, $[[T3]], $[[T1]] +; 32R6-DAG: subu $3, $6, $[[T0]] ; 64-DAG: d[[m:m]]ult $5, $4 ; 64-DAG: [[m]]flo $[[T0:[0-9]+]] @@ -234,12 +244,12 @@ entry: ; DSP-DAG: mfhi $2, $[[AC]] ; DSP-DAG: mflo $3, $[[AC]] -; 32R6-DAG: muh $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}} -; 32R6-DAG: mul $[[T1:[0-9]+]], ${{[45]}}, ${{[45]}} -; 32R6-DAG: sltu $[[T2:[0-9]+]], $7, $[[T1]] -; 32R6-DAG: addu $[[T3:[0-9]+]], $[[T2]], $[[T0]] -; 32R6-DAG: subu $2, $6, $[[T3]] -; 32R6-DAG: subu $3, $7, $[[T1]] +; 32R6-DAG: mul $[[T0:[0-9]+]], ${{[45]}}, ${{[45]}} +; 32R6-DAG: sltu $[[T1:[0-9]+]], $7, $[[T0]] +; 32R6-DAG: muh $[[T2:[0-9]+]], ${{[45]}}, ${{[45]}} +; 32R6-DAG: subu $[[T3:[0-9]+]], $6, $[[T2]] +; 32R6-DAG: subu $2, $[[T3]], $[[T1]] +; 32R6-DAG: subu $3, $7, $[[T0]] ; 64-DAG: sll $[[T0:[0-9]+]], $4, 0 ; 64-DAG: sll $[[T1:[0-9]+]], $5, 0 @@ -260,3 +270,14 @@ entry: %sub = sub nsw i64 %c, %mul ret i64 %sub } + +; ALL-LABEL: msub4 +; ALL-NOT: msub ${{[0-9]+}}, ${{[0-9]+}} + +define i32 @msub4(i32 %a, i32 %b, i32 %c) { +entry: + %mul = mul nsw i32 %a, %b + %sub = sub nsw i32 %c, %mul + + ret i32 %sub +} diff --git a/test/CodeGen/PowerPC/atomic-2.ll b/test/CodeGen/PowerPC/atomic-2.ll index 2039c1f57f17..f402cb78bd18 100644 --- a/test/CodeGen/PowerPC/atomic-2.ll +++ b/test/CodeGen/PowerPC/atomic-2.ll @@ -109,7 +109,7 @@ entry: %tmp = load atomic i64, i64* %mem acquire, align 64 ; CHECK-NOT: ldarx ; CHECK: ld [[VAL:r[0-9]+]] -; CHECK: cmpw [[CR:cr[0-9]+]], [[VAL]], [[VAL]] +; CHECK: cmpd [[CR:cr[0-9]+]], [[VAL]], [[VAL]] ; CHECK: bne- [[CR]], .+4 ; CHECK: isync ret i64 %tmp diff --git a/test/CodeGen/PowerPC/atomics-constant.ll b/test/CodeGen/PowerPC/atomics-constant.ll index a92ca813af85..77825c608a3b 100644 --- a/test/CodeGen/PowerPC/atomics-constant.ll +++ b/test/CodeGen/PowerPC/atomics-constant.ll @@ -11,7 +11,7 @@ define i64 @foo() { ; CHECK-NEXT: addis 3, 2, .LC0@toc@ha ; CHECK-NEXT: li 4, 0 ; CHECK-NEXT: ld 3, .LC0@toc@l(3) -; CHECK-NEXT: cmpw 7, 4, 4 +; CHECK-NEXT: cmpd 7, 4, 4 ; CHECK-NEXT: ld 3, 0(3) ; CHECK-NEXT: bne- 7, .+4 ; CHECK-NEXT: isync diff --git a/test/CodeGen/PowerPC/atomics-regression.ll b/test/CodeGen/PowerPC/atomics-regression.ll index 054d3a4146b0..d57b3a203791 100644 --- a/test/CodeGen/PowerPC/atomics-regression.ll +++ b/test/CodeGen/PowerPC/atomics-regression.ll @@ -23,7 +23,7 @@ define i8 @test2(i8* %ptr) { ; PPC64LE-LABEL: test2: ; PPC64LE: # BB#0: ; PPC64LE-NEXT: lbz 3, 0(3) -; PPC64LE-NEXT: cmpw 7, 3, 3 +; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 ; PPC64LE-NEXT: isync ; PPC64LE-NEXT: blr @@ -37,7 +37,7 @@ define i8 @test3(i8* %ptr) { ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: ori 2, 2, 0 ; PPC64LE-NEXT: lbz 3, 0(3) -; PPC64LE-NEXT: cmpw 7, 3, 3 +; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 ; PPC64LE-NEXT: isync ; PPC64LE-NEXT: blr @@ -67,7 +67,7 @@ define i16 @test6(i16* %ptr) { ; PPC64LE-LABEL: test6: ; PPC64LE: # BB#0: ; PPC64LE-NEXT: lhz 3, 0(3) -; PPC64LE-NEXT: cmpw 7, 3, 3 +; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 ; PPC64LE-NEXT: isync ; PPC64LE-NEXT: blr @@ -81,7 +81,7 @@ define i16 @test7(i16* %ptr) { ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: ori 2, 2, 0 ; PPC64LE-NEXT: lhz 3, 0(3) -; PPC64LE-NEXT: cmpw 7, 3, 3 +; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 ; PPC64LE-NEXT: isync ; PPC64LE-NEXT: blr @@ -111,7 +111,7 @@ define i32 @test10(i32* %ptr) { ; PPC64LE-LABEL: test10: ; PPC64LE: # BB#0: ; PPC64LE-NEXT: lwz 3, 0(3) -; PPC64LE-NEXT: cmpw 7, 3, 3 +; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 ; PPC64LE-NEXT: isync ; PPC64LE-NEXT: blr @@ -125,7 +125,7 @@ define i32 @test11(i32* %ptr) { ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: ori 2, 2, 0 ; PPC64LE-NEXT: lwz 3, 0(3) -; PPC64LE-NEXT: cmpw 7, 3, 3 +; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 ; PPC64LE-NEXT: isync ; PPC64LE-NEXT: blr @@ -155,7 +155,7 @@ define i64 @test14(i64* %ptr) { ; PPC64LE-LABEL: test14: ; PPC64LE: # BB#0: ; PPC64LE-NEXT: ld 3, 0(3) -; PPC64LE-NEXT: cmpw 7, 3, 3 +; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 ; PPC64LE-NEXT: isync ; PPC64LE-NEXT: blr @@ -169,7 +169,7 @@ define i64 @test15(i64* %ptr) { ; PPC64LE-NEXT: sync ; PPC64LE-NEXT: ori 2, 2, 0 ; PPC64LE-NEXT: ld 3, 0(3) -; PPC64LE-NEXT: cmpw 7, 3, 3 +; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 ; PPC64LE-NEXT: isync ; PPC64LE-NEXT: blr @@ -9566,7 +9566,7 @@ define i32 @test_ordering0(i32* %ptr1, i32* %ptr2) { ; PPC64LE-LABEL: test_ordering0: ; PPC64LE: # BB#0: ; PPC64LE-NEXT: lwz 4, 0(3) -; PPC64LE-NEXT: cmpw 7, 4, 4 +; PPC64LE-NEXT: cmpd 7, 4, 4 ; PPC64LE-NEXT: bne- 7, .+4 ; PPC64LE-NEXT: isync ; PPC64LE-NEXT: lwz 3, 0(3) @@ -9583,7 +9583,7 @@ define i32 @test_ordering1(i32* %ptr1, i32 %val1, i32* %ptr2) { ; PPC64LE-LABEL: test_ordering1: ; PPC64LE: # BB#0: ; PPC64LE-NEXT: lwz 3, 0(3) -; PPC64LE-NEXT: cmpw 7, 3, 3 +; PPC64LE-NEXT: cmpd 7, 3, 3 ; PPC64LE-NEXT: bne- 7, .+4 ; PPC64LE-NEXT: isync ; PPC64LE-NEXT: stw 4, 0(5) diff --git a/test/CodeGen/PowerPC/licm-tocReg.ll b/test/CodeGen/PowerPC/licm-tocReg.ll new file mode 100644 index 000000000000..ecdfcba6e3b7 --- /dev/null +++ b/test/CodeGen/PowerPC/licm-tocReg.ll @@ -0,0 +1,110 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s + +; The instructions ADDIStocHA/LDtocL are used to calculate the address of +; globals. The ones that are in bb.3.if.end could not be hoisted by Machine +; LICM due to BCTRL_LDinto_toc in bb2.if.then. This call causes the compiler +; to insert a save TOC to stack before the call and load into X2 to restore TOC +; after. By communicating to Machine LICM that X2 is guaranteed to have the +; same value before and after BCTRL_LDinto_toc, these instructions can be +; hoisted out of bb.3.if.end to outside of the loop. + +; Pre Machine LICM MIR +; +;body: +; bb.0.entry: +; successors: %bb.2.if.then(0x40000000), %bb.3.if.end(0x40000000) +; liveins: %x3 +; +; %4 = COPY %x3 +; %5 = ADDIStocHA %x2, @ga +; %6 = LDtocL @ga, killed %5 :: (load 8 from got) +; %7 = LWZ 0, %6 :: (volatile dereferenceable load 4 from @ga) +; %8 = ADDIStocHA %x2, @gb +; %9 = LDtocL @gb, killed %8 :: (load 8 from got) +; %10 = LWZ 0, killed %9 :: (volatile dereferenceable load 4 from @gb) +; %0 = LWZ 0, %6 :: (volatile dereferenceable load 4 from @ga) +; %11 = CMPW killed %7, killed %10 +; BCC 44, killed %11, %bb.2.if.then +; B %bb.3.if.end +; +; bb.2.if.then: +; %1 = PHI %0, %bb.0.entry, %3, %bb.3.if.end +; ADJCALLSTACKDOWN 32, 0, implicit-def dead %r1, implicit %r1 +; %20 = COPY %x2 +; STD %20, 24, %x1 :: (store 8 into stack + 24) +; %21 = EXTSW_32_64 %1 +; %x3 = COPY %21 +; %x12 = COPY %4 +; MTCTR8 %4, implicit-def %ctr8 +; BCTRL8_LDinto_toc 24, %x1, csr_svr464_altivec, implicit-def dead %lr8, implicit-def dead %x2, implicit %ctr8, implicit %rm, implicit %x3, implicit %x12, implicit %x2, implicit-def %r1, implicit-def %x3 +; ADJCALLSTACKUP 32, 0, implicit-def dead %r1, implicit %r1 +; %22 = COPY %x3 +; %x3 = COPY %22 +; BLR8 implicit %lr8, implicit %rm, implicit %x3 +; +; bb.3.if.end: +; successors: %bb.2.if.then(0x04000000), %bb.3.if.end(0x7c000000) +; +; %2 = PHI %0, %bb.0.entry, %3, %bb.3.if.end +; %12 = ADDI %2, 1 +; %13 = ADDIStocHA %x2, @ga +; %14 = LDtocL @ga, killed %13 :: (load 8 from got) +; STW killed %12, 0, %14 :: (volatile store 4 into @ga) +; %15 = LWZ 0, %14 :: (volatile dereferenceable load 4 from @ga) +; %16 = ADDIStocHA %x2, @gb +; %17 = LDtocL @gb, killed %16 :: (load 8 from got) +; %18 = LWZ 0, killed %17 :: (volatile dereferenceable load 4 from @gb) +; %3 = LWZ 0, %14 :: (volatile dereferenceable load 4 from @ga) +; %19 = CMPW killed %15, killed %18 +; BCC 44, killed %19, %bb.2.if.then +; B %bb.3.if.end + +@ga = external global i32, align 4 +@gb = external global i32, align 4 + +; Function Attrs: nounwind +define signext i32 @test(i32 (i32)* nocapture %FP) local_unnamed_addr #0 { +; CHECK-LABEL: test: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: addis 4, 2, .LC0@toc@ha +; CHECK-NEXT: addis 5, 2, .LC1@toc@ha +; CHECK-NEXT: ld 4, .LC0@toc@l(4) +; CHECK-NEXT: ld 5, .LC1@toc@l(5) +; CHECK-NEXT: lwz 6, 0(4) +; CHECK-NEXT: lwz 5, 0(5) +; CHECK-NEXT: cmpw 6, 5 +; CHECK-NEXT: lwz 5, 0(4) +; CHECK-NEXT: mr 4, 3 +; CHECK-NEXT: bgt 0, .LBB0_3 +; CHECK-NEXT: # BB#1: +; CHECK-NEXT: addis 3, 2, .LC0@toc@ha +; CHECK-NEXT: addis 6, 2, .LC1@toc@ha +; CHECK-NEXT: ld 3, .LC0@toc@l(3) +; CHECK-NEXT: ld 6, .LC1@toc@l(6) +; CHECK-NEXT: .p2align 5 +; CHECK-NEXT: .LBB0_2: # %if.end +; CHECK-NOT: addis {{[0-9]+}}, 2, .LC0@toc@ha +; CHECK-NOT: addis {{[0-9]+}}, 2, .LC1@toc@ha +; CHECK: blr +entry: + %0 = load volatile i32, i32* @ga, align 4 + %1 = load volatile i32, i32* @gb, align 4 + %cmp1 = icmp sgt i32 %0, %1 + %2 = load volatile i32, i32* @ga, align 4 + br i1 %cmp1, label %if.then, label %if.end + +if.then: ; preds = %if.end, %entry + %.lcssa = phi i32 [ %2, %entry ], [ %6, %if.end ] + %call = tail call signext i32 %FP(i32 signext %.lcssa) #1 + ret i32 %call + +if.end: ; preds = %entry, %if.end + %3 = phi i32 [ %6, %if.end ], [ %2, %entry ] + %inc = add nsw i32 %3, 1 + store volatile i32 %inc, i32* @ga, align 4 + %4 = load volatile i32, i32* @ga, align 4 + %5 = load volatile i32, i32* @gb, align 4 + %cmp = icmp sgt i32 %4, %5 + %6 = load volatile i32, i32* @ga, align 4 + br i1 %cmp, label %if.then, label %if.end +} diff --git a/test/CodeGen/PowerPC/logic-ops-on-compares.ll b/test/CodeGen/PowerPC/logic-ops-on-compares.ll index 5a507e9ff678..df021c20ea86 100644 --- a/test/CodeGen/PowerPC/logic-ops-on-compares.ll +++ b/test/CodeGen/PowerPC/logic-ops-on-compares.ll @@ -40,8 +40,8 @@ return: ; preds = %if.end, %if.then ret i32 %retval.0 } -define void @neg_truncate_i32_eq(i32 *%ptr) { -; CHECK-LABEL: neg_truncate_i32_eq: +define void @neg_truncate_i32(i32 *%ptr) { +; CHECK-LABEL: neg_truncate_i32: ; CHECK: # BB#0: # %entry ; CHECK-NEXT: lwz r3, 0(r3) ; CHECK-NEXT: rldicl. r3, r3, 0, 63 @@ -66,8 +66,8 @@ if.end29: ; preds = %if.else } ; Function Attrs: nounwind -define i64 @logic_eq_64(i64 %a, i64 %b, i64 %c) { -; CHECK-LABEL: logic_eq_64: +define i64 @logic_ne_64(i64 %a, i64 %b, i64 %c) { +; CHECK-LABEL: logic_ne_64: ; CHECK: xor r7, r3, r4 ; CHECK-NEXT: li r6, 55 ; CHECK-NEXT: xor r5, r5, r6 @@ -99,8 +99,8 @@ return: ; preds = %if.end, %if.then ret i64 %retval.0 } -define void @neg_truncate_i64_eq(i64 *%ptr) { -; CHECK-LABEL: neg_truncate_i64_eq: +define void @neg_truncate_i64(i64 *%ptr) { +; CHECK-LABEL: neg_truncate_i64: ; CHECK: # BB#0: # %entry ; CHECK-NEXT: ld r3, 0(r3) ; CHECK-NEXT: rldicl. r3, r3, 0, 63 @@ -124,67 +124,6 @@ if.end29: ; preds = %if.else } -; Function Attrs: nounwind -define i64 @logic_ne_64(i64 %a, i64 %b, i64 %c) { -; CHECK-LABEL: logic_ne_64: -; CHECK: xor r7, r3, r4 -; CHECK-NEXT: li r6, 55 -; CHECK-NEXT: addic r8, r7, -1 -; CHECK-NEXT: xor r5, r5, r6 -; CHECK-NEXT: subfe r7, r8, r7 -; CHECK-NEXT: cntlzd r5, r5 -; CHECK-NEXT: addic r12, r4, -1 -; CHECK-NEXT: rldicl r5, r5, 58, 63 -; CHECK-NEXT: subfe r6, r12, r4 -; CHECK-NEXT: and r6, r7, r6 -; CHECK-NEXT: or. r5, r6, r5 -; CHECK-NEXT: bc 4, 1 -entry: - %tobool = icmp ne i64 %a, %b - %tobool1 = icmp ne i64 %b, 0 - %or.cond = and i1 %tobool, %tobool1 - %tobool3 = icmp eq i64 %c, 55 - %or.cond5 = or i1 %or.cond, %tobool3 - br i1 %or.cond5, label %if.end, label %if.then - -if.then: ; preds = %entry - %call = tail call i64 @foo64(i64 %a) #2 - br label %return - -if.end: ; preds = %entry - %call4 = tail call i64 @bar64(i64 %b) #2 - br label %return - -return: ; preds = %if.end, %if.then - %retval.0 = phi i64 [ %call4, %if.end ], [ %call, %if.then ] - ret i64 %retval.0 -} - -define void @neg_truncate_i64_ne(i64 *%ptr) { -; CHECK-LABEL: neg_truncate_i64_ne: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: ld r3, 0(r3) -; CHECK-NEXT: andi. r3, r3, 1 -; CHECK-NEXT: bclr 12, 1, 0 -; CHECK-NEXT: # BB#1: # %if.end29.thread136 -; CHECK-NEXT: .LBB5_2: # %if.end29 -entry: - %0 = load i64, i64* %ptr, align 4 - %rem17127 = and i64 %0, 1 - %cmp18 = icmp ne i64 %rem17127, 0 - br label %if.else - -if.else: ; preds = %entry - br i1 %cmp18, label %if.end29, label %if.end29.thread136 - -if.end29.thread136: ; preds = %if.else - unreachable - -if.end29: ; preds = %if.else - ret void - -} - declare signext i32 @foo(i32 signext) declare signext i32 @bar(i32 signext) declare i64 @foo64(i64) diff --git a/test/CodeGen/PowerPC/ppc64-P9-mod.ll b/test/CodeGen/PowerPC/ppc64-P9-mod.ll new file mode 100644 index 000000000000..46e347becbb6 --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-P9-mod.ll @@ -0,0 +1,263 @@ +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-PWR8 -implicit-check-not mod[us][wd] + +@mod_resultsw = common local_unnamed_addr global i32 0, align 4 +@mod_resultud = common local_unnamed_addr global i64 0, align 8 +@div_resultsw = common local_unnamed_addr global i32 0, align 4 +@mod_resultuw = common local_unnamed_addr global i32 0, align 4 +@div_resultuw = common local_unnamed_addr global i32 0, align 4 +@div_resultsd = common local_unnamed_addr global i64 0, align 8 +@mod_resultsd = common local_unnamed_addr global i64 0, align 8 +@div_resultud = common local_unnamed_addr global i64 0, align 8 + +; Function Attrs: norecurse nounwind +define void @modulo_sw(i32 signext %a, i32 signext %b) local_unnamed_addr { +entry: + %rem = srem i32 %a, %b + store i32 %rem, i32* @mod_resultsw, align 4 + ret void +; CHECK-LABEL: modulo_sw +; CHECK: modsw {{[0-9]+}}, 3, 4 +; CHECK: blr +; CHECK-PWR8-LABEL: modulo_sw +; CHECK-PWR8: div +; CHECK-PWR8: mull +; CHECK-PWR8: sub +; CHECK-PWR8: blr +} + +; Function Attrs: norecurse nounwind readnone +define zeroext i32 @modulo_uw(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr { +entry: + %rem = urem i32 %a, %b + ret i32 %rem +; CHECK-LABEL: modulo_uw +; CHECK: moduw {{[0-9]+}}, 3, 4 +; CHECK: blr +; CHECK-PWR8-LABEL: modulo_uw +; CHECK-PWR8: div +; CHECK-PWR8: mull +; CHECK-PWR8: sub +; CHECK-PWR8: blr +} + +; Function Attrs: norecurse nounwind readnone +define i64 @modulo_sd(i64 %a, i64 %b) local_unnamed_addr { +entry: + %rem = srem i64 %a, %b + ret i64 %rem +; CHECK-LABEL: modulo_sd +; CHECK: modsd {{[0-9]+}}, 3, 4 +; CHECK: blr +; CHECK-PWR8-LABEL: modulo_sd +; CHECK-PWR8: div +; CHECK-PWR8: mull +; CHECK-PWR8: sub +; CHECK-PWR8: blr +} + +; Function Attrs: norecurse nounwind +define void @modulo_ud(i64 %a, i64 %b) local_unnamed_addr { +entry: + %rem = urem i64 %a, %b + store i64 %rem, i64* @mod_resultud, align 8 + ret void +; CHECK-LABEL: modulo_ud +; CHECK: modud {{[0-9]+}}, 3, 4 +; CHECK: blr +; CHECK-PWR8-LABEL: modulo_ud +; CHECK-PWR8: div +; CHECK-PWR8: mull +; CHECK-PWR8: sub +; CHECK-PWR8: blr +} + +; Function Attrs: norecurse nounwind +define void @modulo_div_sw(i32 signext %a, i32 signext %b) local_unnamed_addr { +entry: + %rem = srem i32 %a, %b + store i32 %rem, i32* @mod_resultsw, align 4 + %div = sdiv i32 %a, %b + store i32 %div, i32* @div_resultsw, align 4 + ret void +; CHECK-LABEL: modulo_div_sw +; CHECK-NOT: modsw +; CHECK: div +; CHECK-NOT: modsw +; CHECK: mull +; CHECK-NOT: modsw +; CHECK: sub +; CHECK: blr +; CHECK-PWR8-LABEL: modulo_div_sw +; CHECK-PWR8: div +; CHECK-PWR8: mull +; CHECK-PWR8: sub +; CHECK-PWR8: blr +} + +; Function Attrs: norecurse nounwind +define void @modulo_div_abc_sw(i32 signext %a, i32 signext %b, i32 signext %c) local_unnamed_addr { +entry: + %rem = srem i32 %a, %c + store i32 %rem, i32* @mod_resultsw, align 4 + %div = sdiv i32 %b, %c + store i32 %div, i32* @div_resultsw, align 4 + ret void +; CHECK-LABEL: modulo_div_abc_sw +; CHECK: modsw {{[0-9]+}}, 3, 5 +; CHECK: blr +; CHECK-PWR8-LABEL: modulo_div_abc_sw +; CHECK-PWR8: div +; CHECK-PWR8: mull +; CHECK-PWR8: sub +; CHECK-PWR8: blr +} + +; Function Attrs: norecurse nounwind +define void @modulo_div_uw(i32 zeroext %a, i32 zeroext %b) local_unnamed_addr { +entry: + %rem = urem i32 %a, %b + store i32 %rem, i32* @mod_resultuw, align 4 + %div = udiv i32 %a, %b + store i32 %div, i32* @div_resultuw, align 4 + ret void +; CHECK-LABEL: modulo_div_uw +; CHECK-NOT: modsw +; CHECK: div +; CHECK-NOT: modsw +; CHECK: mull +; CHECK-NOT: modsw +; CHECK: sub +; CHECK: blr +; CHECK-PWR8-LABEL: modulo_div_uw +; CHECK-PWR8: div +; CHECK-PWR8: mull +; CHECK-PWR8: sub +; CHECK-PWR8: blr +} + +; Function Attrs: norecurse nounwind +define void @modulo_div_swuw(i32 signext %a, i32 signext %b) local_unnamed_addr { +entry: + %rem = srem i32 %a, %b + store i32 %rem, i32* @mod_resultsw, align 4 + %div = udiv i32 %a, %b + store i32 %div, i32* @div_resultsw, align 4 + ret void +; CHECK-LABEL: modulo_div_swuw +; CHECK: modsw {{[0-9]+}}, 3, 4 +; CHECK: blr +; CHECK-PWR8-LABEL: modulo_div_swuw +; CHECK-PWR8: div +; CHECK-PWR8: mull +; CHECK-PWR8: sub +; CHECK-PWR8: blr +} + +; Function Attrs: norecurse nounwind +define void @modulo_div_udsd(i64 %a, i64 %b) local_unnamed_addr { +entry: + %rem = urem i64 %a, %b + store i64 %rem, i64* @mod_resultud, align 8 + %div = sdiv i64 %a, %b + store i64 %div, i64* @div_resultsd, align 8 + ret void +; CHECK-LABEL: modulo_div_udsd +; CHECK: modud {{[0-9]+}}, 3, 4 +; CHECK: blr +; CHECK-PWR8-LABEL: modulo_div_udsd +; CHECK-PWR8: div +; CHECK-PWR8: mull +; CHECK-PWR8: sub +; CHECK-PWR8: blr +} + +; Function Attrs: norecurse nounwind +define void @modulo_const32_sw(i32 signext %a) local_unnamed_addr { +entry: + %rem = srem i32 %a, 32 + store i32 %rem, i32* @mod_resultsw, align 4 + ret void +; CHECK-LABEL: modulo_const32_sw +; CHECK-NOT: modsw +; CHECK: srawi +; CHECK-NOT: modsw +; CHECK: addze +; CHECK-NOT: modsw +; CHECK: slwi +; CHECK-NOT: modsw +; CHECK: subf +; CHECK-NOT: modsw +; CHECK: blr +; CHECK-PWR8-LABEL: modulo_const32_sw +; CHECK-PWR8: srawi +; CHECK-PWR8: addze +; CHECK-PWR8: slwi +; CHECK-PWR8: subf +; CHECK-PWR8: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @modulo_const3_sw(i32 signext %a) local_unnamed_addr { +entry: + %rem = srem i32 %a, 3 + ret i32 %rem +; CHECK-LABEL: modulo_const3_sw +; CHECK-NOT: modsw +; CHECK: mull +; CHECK-NOT: modsw +; CHECK: sub +; CHECK-NOT: modsw +; CHECK: blr +; CHECK-PWR8-LABEL: modulo_const3_sw +; CHECK-PWR8: mull +; CHECK-PWR8: sub +; CHECK-PWR8: blr +} + +; Function Attrs: norecurse nounwind readnone +define signext i32 @const2_modulo_sw(i32 signext %a) local_unnamed_addr { +entry: + %rem = srem i32 2, %a + ret i32 %rem +; CHECK-LABEL: const2_modulo_sw +; CHECK: modsw {{[0-9]+}}, {{[0-9]+}}, 3 +; CHECK: blr +; CHECK-PWR8-LABEL: const2_modulo_sw +; CHECK-PWR8: div +; CHECK-PWR8: mull +; CHECK-PWR8: sub +; CHECK-PWR8: blr +} + +; Function Attrs: norecurse nounwind +; FIXME On power 9 this test will still produce modsw because the divide is in +; a different block than the remainder. Due to the nature of the SDAG we cannot +; see the div in the other block. +define void @blocks_modulo_div_sw(i32 signext %a, i32 signext %b, i32 signext %c) local_unnamed_addr { +entry: + %div = sdiv i32 %a, %b + store i32 %div, i32* @div_resultsw, align 4 + %cmp = icmp sgt i32 %c, 0 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + %rem = srem i32 %a, %b + store i32 %rem, i32* @mod_resultsw, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +; CHECK-LABEL: blocks_modulo_div_sw +; CHECK: div +; CHECK: modsw {{[0-9]+}}, 3, 4 +; CHECK: blr +; CHECK-PWR8-LABEL: blocks_modulo_div_sw +; CHECK-PWR8: div +; CHECK-PWR8: mull +; CHECK-PWR8: sub +; CHECK-PWR8: blr +} + + diff --git a/test/CodeGen/PowerPC/testComparesinesll.ll b/test/CodeGen/PowerPC/testComparesinesll.ll deleted file mode 100644 index 9e9369455857..000000000000 --- a/test/CodeGen/PowerPC/testComparesinesll.ll +++ /dev/null @@ -1,125 +0,0 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py - -@glob = common local_unnamed_addr global i64 0, align 8 - -define signext i32 @test_inesll(i64 %a, i64 %b) { -; CHECK-LABEL: test_inesll: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addic r4, r3, -1 -; CHECK-NEXT: subfe r3, r4, r3 -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, %b - %conv = zext i1 %cmp to i32 - ret i32 %conv -} - -define signext i32 @test_inesll_sext(i64 %a, i64 %b) { -; CHECK-LABEL: test_inesll_sext: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, %b - %sub = sext i1 %cmp to i32 - ret i32 %sub -} - -define signext i32 @test_inesll_z(i64 %a) { -; CHECK-LABEL: test_inesll_z: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addic r4, r3, -1 -; CHECK-NEXT: subfe r3, r4, r3 -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, 0 - %conv = zext i1 %cmp to i32 - ret i32 %conv -} - -define signext i32 @test_inesll_sext_z(i64 %a) { -; CHECK-LABEL: test_inesll_sext_z: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, 0 - %sub = sext i1 %cmp to i32 - ret i32 %sub -} - -define void @test_inesll_store(i64 %a, i64 %b) { -; CHECK-LABEL: test_inesll_store: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r12, .LC0@toc@l(r5) -; CHECK-NEXT: addic r5, r3, -1 -; CHECK-NEXT: subfe r3, r5, r3 -; CHECK-NEXT: std r3, 0(r12) -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, %b - %conv1 = zext i1 %cmp to i64 - store i64 %conv1, i64* @glob, align 8 - ret void -} - -define void @test_inesll_sext_store(i64 %a, i64 %b) { -; CHECK-LABEL: test_inesll_sext_store: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r12, .LC0@toc@l(r5) -; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r12) -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, %b - %conv1 = sext i1 %cmp to i64 - store i64 %conv1, i64* @glob, align 8 - ret void -} - -define void @test_inesll_z_store(i64 %a) { -; CHECK-LABEL: test_inesll_z_store: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha -; CHECK-NEXT: addic r5, r3, -1 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: subfe r3, r5, r3 -; CHECK-NEXT: std r3, 0(r4) -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, 0 - %conv1 = zext i1 %cmp to i64 - store i64 %conv1, i64* @glob, align 8 - ret void -} - -define void @test_inesll_sext_z_store(i64 %a) { -; CHECK-LABEL: test_inesll_sext_z_store: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha -; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r4) -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, 0 - %conv1 = sext i1 %cmp to i64 - store i64 %conv1, i64* @glob, align 8 - ret void -} diff --git a/test/CodeGen/PowerPC/testComparesineull.ll b/test/CodeGen/PowerPC/testComparesineull.ll deleted file mode 100644 index 7f0fed15157c..000000000000 --- a/test/CodeGen/PowerPC/testComparesineull.ll +++ /dev/null @@ -1,125 +0,0 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py - -@glob = common local_unnamed_addr global i64 0, align 8 - -define signext i32 @test_ineull(i64 %a, i64 %b) { -; CHECK-LABEL: test_ineull: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addic r4, r3, -1 -; CHECK-NEXT: subfe r3, r4, r3 -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, %b - %conv = zext i1 %cmp to i32 - ret i32 %conv -} - -define signext i32 @test_ineull_sext(i64 %a, i64 %b) { -; CHECK-LABEL: test_ineull_sext: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, %b - %sub = sext i1 %cmp to i32 - ret i32 %sub -} - -define signext i32 @test_ineull_z(i64 %a) { -; CHECK-LABEL: test_ineull_z: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addic r4, r3, -1 -; CHECK-NEXT: subfe r3, r4, r3 -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, 0 - %conv = zext i1 %cmp to i32 - ret i32 %conv -} - -define signext i32 @test_ineull_sext_z(i64 %a) { -; CHECK-LABEL: test_ineull_sext_z: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, 0 - %sub = sext i1 %cmp to i32 - ret i32 %sub -} - -define void @test_ineull_store(i64 %a, i64 %b) { -; CHECK-LABEL: test_ineull_store: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r12, .LC0@toc@l(r5) -; CHECK-NEXT: addic r5, r3, -1 -; CHECK-NEXT: subfe r3, r5, r3 -; CHECK-NEXT: std r3, 0(r12) -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, %b - %conv1 = zext i1 %cmp to i64 - store i64 %conv1, i64* @glob, align 8 - ret void -} - -define void @test_ineull_sext_store(i64 %a, i64 %b) { -; CHECK-LABEL: test_ineull_sext_store: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r12, .LC0@toc@l(r5) -; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r12) -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, %b - %conv1 = sext i1 %cmp to i64 - store i64 %conv1, i64* @glob, align 8 - ret void -} - -define void @test_ineull_z_store(i64 %a) { -; CHECK-LABEL: test_ineull_z_store: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha -; CHECK-NEXT: addic r5, r3, -1 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: subfe r3, r5, r3 -; CHECK-NEXT: std r3, 0(r4) -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, 0 - %conv1 = zext i1 %cmp to i64 - store i64 %conv1, i64* @glob, align 8 - ret void -} - -define void @test_ineull_sext_z_store(i64 %a) { -; CHECK-LABEL: test_ineull_sext_z_store: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha -; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r4) -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, 0 - %conv1 = sext i1 %cmp to i64 - store i64 %conv1, i64* @glob, align 8 - ret void -} diff --git a/test/CodeGen/PowerPC/testComparesllnesll.ll b/test/CodeGen/PowerPC/testComparesllnesll.ll deleted file mode 100644 index d87ff55739fc..000000000000 --- a/test/CodeGen/PowerPC/testComparesllnesll.ll +++ /dev/null @@ -1,125 +0,0 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py - -@glob = common local_unnamed_addr global i64 0, align 8 - -define i64 @test_llnesll(i64 %a, i64 %b) { -; CHECK-LABEL: test_llnesll: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addic r4, r3, -1 -; CHECK-NEXT: subfe r3, r4, r3 -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, %b - %conv1 = zext i1 %cmp to i64 - ret i64 %conv1 -} - -define i64 @test_llnesll_sext(i64 %a, i64 %b) { -; CHECK-LABEL: test_llnesll_sext: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, %b - %conv1 = sext i1 %cmp to i64 - ret i64 %conv1 -} - -define i64 @test_llnesll_z(i64 %a) { -; CHECK-LABEL: test_llnesll_z: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addic r4, r3, -1 -; CHECK-NEXT: subfe r3, r4, r3 -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, 0 - %conv1 = zext i1 %cmp to i64 - ret i64 %conv1 -} - -define i64 @test_llnesll_sext_z(i64 %a) { -; CHECK-LABEL: test_llnesll_sext_z: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, 0 - %conv1 = sext i1 %cmp to i64 - ret i64 %conv1 -} - -define void @test_llnesll_store(i64 %a, i64 %b) { -; CHECK-LABEL: test_llnesll_store: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r12, .LC0@toc@l(r5) -; CHECK-NEXT: addic r5, r3, -1 -; CHECK-NEXT: subfe r3, r5, r3 -; CHECK-NEXT: std r3, 0(r12) -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, %b - %conv1 = zext i1 %cmp to i64 - store i64 %conv1, i64* @glob, align 8 - ret void -} - -define void @test_llnesll_sext_store(i64 %a, i64 %b) { -; CHECK-LABEL: test_llnesll_sext_store: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r12, .LC0@toc@l(r5) -; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r12) -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, %b - %conv1 = sext i1 %cmp to i64 - store i64 %conv1, i64* @glob, align 8 - ret void -} - -define void @test_llnesll_z_store(i64 %a) { -; CHECK-LABEL: test_llnesll_z_store: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha -; CHECK-NEXT: addic r5, r3, -1 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: subfe r3, r5, r3 -; CHECK-NEXT: std r3, 0(r4) -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, 0 - %conv1 = zext i1 %cmp to i64 - store i64 %conv1, i64* @glob, align 8 - ret void -} - -define void @test_llnesll_sext_z_store(i64 %a) { -; CHECK-LABEL: test_llnesll_sext_z_store: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha -; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r4) -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, 0 - %conv1 = sext i1 %cmp to i64 - store i64 %conv1, i64* @glob, align 8 - ret void -} diff --git a/test/CodeGen/PowerPC/testComparesllneull.ll b/test/CodeGen/PowerPC/testComparesllneull.ll deleted file mode 100644 index 7309d5899068..000000000000 --- a/test/CodeGen/PowerPC/testComparesllneull.ll +++ /dev/null @@ -1,125 +0,0 @@ -; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ -; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ -; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py - -@glob = common local_unnamed_addr global i64 0, align 8 - -define i64 @test_llneull(i64 %a, i64 %b) { -; CHECK-LABEL: test_llneull: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: addic r4, r3, -1 -; CHECK-NEXT: subfe r3, r4, r3 -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, %b - %conv1 = zext i1 %cmp to i64 - ret i64 %conv1 -} - -define i64 @test_llneull_sext(i64 %a, i64 %b) { -; CHECK-LABEL: test_llneull_sext: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, %b - %conv1 = sext i1 %cmp to i64 - ret i64 %conv1 -} - -define i64 @test_llneull_z(i64 %a) { -; CHECK-LABEL: test_llneull_z: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addic r4, r3, -1 -; CHECK-NEXT: subfe r3, r4, r3 -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, 0 - %conv1 = zext i1 %cmp to i64 - ret i64 %conv1 -} - -define i64 @test_llneull_sext_z(i64 %a) { -; CHECK-LABEL: test_llneull_sext_z: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, 0 - %conv1 = sext i1 %cmp to i64 - ret i64 %conv1 -} - -define void @test_llneull_store(i64 %a, i64 %b) { -; CHECK-LABEL: test_llneull_store: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r12, .LC0@toc@l(r5) -; CHECK-NEXT: addic r5, r3, -1 -; CHECK-NEXT: subfe r3, r5, r3 -; CHECK-NEXT: std r3, 0(r12) -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, %b - %conv1 = zext i1 %cmp to i64 - store i64 %conv1, i64* @glob, align 8 - ret void -} - -define void @test_llneull_sext_store(i64 %a, i64 %b) { -; CHECK-LABEL: test_llneull_sext_store: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addis r5, r2, .LC0@toc@ha -; CHECK-NEXT: xor r3, r3, r4 -; CHECK-NEXT: ld r12, .LC0@toc@l(r5) -; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r12) -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, %b - %conv1 = sext i1 %cmp to i64 - store i64 %conv1, i64* @glob, align 8 - ret void -} - -define void @test_llneull_z_store(i64 %a) { -; CHECK-LABEL: test_llneull_z_store: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha -; CHECK-NEXT: addic r5, r3, -1 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: subfe r3, r5, r3 -; CHECK-NEXT: std r3, 0(r4) -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, 0 - %conv1 = zext i1 %cmp to i64 - store i64 %conv1, i64* @glob, align 8 - ret void -} - -define void @test_llneull_sext_z_store(i64 %a) { -; CHECK-LABEL: test_llneull_sext_z_store: -; CHECK: # BB#0: # %entry -; CHECK-NEXT: addis r4, r2, .LC0@toc@ha -; CHECK-NEXT: subfic r3, r3, 0 -; CHECK-NEXT: ld r4, .LC0@toc@l(r4) -; CHECK-NEXT: subfe r3, r3, r3 -; CHECK-NEXT: std r3, 0(r4) -; CHECK-NEXT: blr -entry: - %cmp = icmp ne i64 %a, 0 - %conv1 = sext i1 %cmp to i64 - store i64 %conv1, i64* @glob, align 8 - ret void -} diff --git a/test/CodeGen/PowerPC/vec_revb.ll b/test/CodeGen/PowerPC/vec_revb.ll new file mode 100644 index 000000000000..c09164bae13e --- /dev/null +++ b/test/CodeGen/PowerPC/vec_revb.ll @@ -0,0 +1,54 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s + +define <8 x i16> @testXXBRH(<8 x i16> %a) { +; CHECK-LABEL: testXXBRH: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: xxbrh 34, 34 +; CHECK-NEXT: blr + +entry: + %0 = bitcast <8 x i16> %a to <16 x i8> + %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> + %2 = bitcast <16 x i8> %1 to <8 x i16> + ret <8 x i16> %2 +} + +define <4 x i32> @testXXBRW(<4 x i32> %a) { +; CHECK-LABEL: testXXBRW: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: xxbrw 34, 34 +; CHECK-NEXT: blr + +entry: + %0 = bitcast <4 x i32> %a to <16 x i8> + %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12> + %2 = bitcast <16 x i8> %1 to <4 x i32> + ret <4 x i32> %2 +} + +define <2 x double> @testXXBRD(<2 x double> %a) { +; CHECK-LABEL: testXXBRD: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: xxbrd 34, 34 +; CHECK-NEXT: blr + +entry: + %0 = bitcast <2 x double> %a to <16 x i8> + %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8> + %2 = bitcast <16 x i8> %1 to <2 x double> + ret <2 x double> %2 +} + +define <1 x i128> @testXXBRQ(<1 x i128> %a) { +; CHECK-LABEL: testXXBRQ: +; CHECK: # BB#0: # %entry +; CHECK-NEXT: xxbrq 34, 34 +; CHECK-NEXT: blr + +entry: + %0 = bitcast <1 x i128> %a to <16 x i8> + %1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> + %2 = bitcast <16 x i8> %1 to <1 x i128> + ret <1 x i128> %2 +} diff --git a/test/CodeGen/SystemZ/fp-sincos-01.ll b/test/CodeGen/SystemZ/fp-sincos-01.ll index cd182a590eee..4a38d7afba2c 100644 --- a/test/CodeGen/SystemZ/fp-sincos-01.ll +++ b/test/CodeGen/SystemZ/fp-sincos-01.ll @@ -1,6 +1,6 @@ ; Test that combined sin/cos library call is emitted when appropriate -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s --check-prefix=CHECK-NOOPT +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s --check-prefix=CHECK-OPT ; RUN: llc < %s -mtriple=s390x-linux-gnu -enable-unsafe-fp-math | FileCheck %s --check-prefix=CHECK-OPT define float @f1(float %x) { @@ -8,10 +8,18 @@ define float @f1(float %x) { ; CHECK-OPT: brasl %r14, sincosf@PLT ; CHECK-OPT: le %f0, 164(%r15) ; CHECK-OPT: aeb %f0, 160(%r15) + %tmp1 = call float @sinf(float %x) readnone + %tmp2 = call float @cosf(float %x) readnone + %add = fadd float %tmp1, %tmp2 + ret float %add +} -; CHECK-NOOPT-LABEL: f1: -; CHECK-NOOPT: brasl %r14, sinf@PLT -; CHECK-NOOPT: brasl %r14, cosf@PLT +define float @f1_errno(float %x) { +; CHECK-OPT-LABEL: f1_errno: +; CHECK-OPT: brasl %r14, sinf@PLT +; CHECK-OPT: ler %f9, %f0 +; CHECK-OPT: brasl %r14, cosf@PLT +; CHECK-OPT: aebr %f0, %f9 %tmp1 = call float @sinf(float %x) %tmp2 = call float @cosf(float %x) %add = fadd float %tmp1, %tmp2 @@ -23,10 +31,18 @@ define double @f2(double %x) { ; CHECK-OPT: brasl %r14, sincos@PLT ; CHECK-OPT: ld %f0, 168(%r15) ; CHECK-OPT: adb %f0, 160(%r15) + %tmp1 = call double @sin(double %x) readnone + %tmp2 = call double @cos(double %x) readnone + %add = fadd double %tmp1, %tmp2 + ret double %add +} -; CHECK-NOOPT-LABEL: f2: -; CHECK-NOOPT: brasl %r14, sin@PLT -; CHECK-NOOPT: brasl %r14, cos@PLT +define double @f2_errno(double %x) { +; CHECK-OPT-LABEL: f2_errno: +; CHECK-OPT: brasl %r14, sin@PLT +; CHECK-OPT: ldr %f9, %f0 +; CHECK-OPT: brasl %r14, cos@PLT +; CHECK-OPT: adbr %f0, %f9 %tmp1 = call double @sin(double %x) %tmp2 = call double @cos(double %x) %add = fadd double %tmp1, %tmp2 @@ -37,20 +53,27 @@ define fp128 @f3(fp128 %x) { ; CHECK-OPT-LABEL: f3: ; CHECK-OPT: brasl %r14, sincosl@PLT ; CHECK-OPT: axbr + %tmp1 = call fp128 @sinl(fp128 %x) readnone + %tmp2 = call fp128 @cosl(fp128 %x) readnone + %add = fadd fp128 %tmp1, %tmp2 + ret fp128 %add +} -; CHECK-NOOPT-LABEL: f3: -; CHECK-NOOPT: brasl %r14, sinl@PLT -; CHECK-NOOPT: brasl %r14, cosl@PLT +define fp128 @f3_errno(fp128 %x) { +; CHECK-OPT-LABEL: f3_errno: +; CHECK-OPT: brasl %r14, sinl@PLT +; CHECK-OPT: brasl %r14, cosl@PLT +; CHECK-OPT: axbr %tmp1 = call fp128 @sinl(fp128 %x) %tmp2 = call fp128 @cosl(fp128 %x) %add = fadd fp128 %tmp1, %tmp2 ret fp128 %add } -declare float @sinf(float) readonly -declare double @sin(double) readonly -declare fp128 @sinl(fp128) readonly -declare float @cosf(float) readonly -declare double @cos(double) readonly -declare fp128 @cosl(fp128) readonly +declare float @sinf(float) +declare double @sin(double) +declare fp128 @sinl(fp128) +declare float @cosf(float) +declare double @cos(double) +declare fp128 @cosl(fp128) diff --git a/test/CodeGen/X86/2012-01-11-split-cv.ll b/test/CodeGen/X86/2012-01-11-split-cv.ll index 212acedafb94..34ec48a02517 100644 --- a/test/CodeGen/X86/2012-01-11-split-cv.ll +++ b/test/CodeGen/X86/2012-01-11-split-cv.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mattr=+avx -mtriple=i686-unknown-unknown | FileCheck %s define void @add18i16(<18 x i16>* nocapture sret %ret, <18 x i16>* %bp) nounwind { @@ -12,7 +12,6 @@ define void @add18i16(<18 x i16>* nocapture sret %ret, <18 x i16>* %bp) nounwind ; CHECK-NEXT: vmovups %ymm0, (%eax) ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retl $4 -; %b = load <18 x i16>, <18 x i16>* %bp, align 16 %x = add <18 x i16> zeroinitializer, %b store <18 x i16> %x, <18 x i16>* %ret, align 16 diff --git a/test/CodeGen/X86/StackColoring.ll b/test/CodeGen/X86/StackColoring.ll index 93888c470e2d..47c74175f949 100644 --- a/test/CodeGen/X86/StackColoring.ll +++ b/test/CodeGen/X86/StackColoring.ll @@ -582,12 +582,76 @@ if.end: ; preds = %if.then, %entry ret i32 %x.addr.0 } +;CHECK-LABEL: multi_segment: +;YESCOLOR: subq $256, %rsp +;NOFIRSTUSE: subq $256, %rsp +;NOCOLOR: subq $512, %rsp +define i1 @multi_segment(i1, i1) +{ +entry-block: + %foo = alloca [32 x i64] + %bar = alloca [32 x i64] + %foo_i8 = bitcast [32 x i64]* %foo to i8* + %bar_i8 = bitcast [32 x i64]* %bar to i8* + call void @llvm.lifetime.start.p0i8(i64 256, i8* %bar_i8) + call void @baz([32 x i64]* %bar, i32 1) + call void @llvm.lifetime.end.p0i8(i64 256, i8* %bar_i8) + call void @llvm.lifetime.start.p0i8(i64 256, i8* %foo_i8) + call void @baz([32 x i64]* %foo, i32 1) + call void @llvm.lifetime.end.p0i8(i64 256, i8* %foo_i8) + call void @llvm.lifetime.start.p0i8(i64 256, i8* %bar_i8) + call void @baz([32 x i64]* %bar, i32 1) + call void @llvm.lifetime.end.p0i8(i64 256, i8* %bar_i8) + ret i1 true +} + +;CHECK-LABEL: pr32488: +;YESCOLOR: subq $256, %rsp +;NOFIRSTUSE: subq $256, %rsp +;NOCOLOR: subq $512, %rsp +define i1 @pr32488(i1, i1) +{ +entry-block: + %foo = alloca [32 x i64] + %bar = alloca [32 x i64] + %foo_i8 = bitcast [32 x i64]* %foo to i8* + %bar_i8 = bitcast [32 x i64]* %bar to i8* + br i1 %0, label %if_false, label %if_true +if_false: + call void @llvm.lifetime.start.p0i8(i64 256, i8* %bar_i8) + call void @baz([32 x i64]* %bar, i32 0) + br i1 %1, label %if_false.1, label %onerr +if_false.1: + call void @llvm.lifetime.end.p0i8(i64 256, i8* %bar_i8) + br label %merge +if_true: + call void @llvm.lifetime.start.p0i8(i64 256, i8* %foo_i8) + call void @baz([32 x i64]* %foo, i32 1) + br i1 %1, label %if_true.1, label %onerr +if_true.1: + call void @llvm.lifetime.end.p0i8(i64 256, i8* %foo_i8) + br label %merge +merge: + ret i1 false +onerr: + call void @llvm.lifetime.end.p0i8(i64 256, i8* %foo_i8) + call void @llvm.lifetime.end.p0i8(i64 256, i8* %bar_i8) + call void @destructor() + ret i1 true +} + +%Data = type { [32 x i64] } + +declare void @destructor() + declare void @inita(i32*) declare void @initb(i32*,i32*,i32*) declare void @bar([100 x i32]* , [100 x i32]*) nounwind +declare void @baz([32 x i64]*, i32) + declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) nounwind declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) nounwind diff --git a/test/CodeGen/X86/add-sub-nsw-nuw.ll b/test/CodeGen/X86/add-sub-nsw-nuw.ll index f5bffb2386bd..d02736de55d3 100644 --- a/test/CodeGen/X86/add-sub-nsw-nuw.ll +++ b/test/CodeGen/X86/add-sub-nsw-nuw.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=i386-apple-darwin < %s | FileCheck %s ; PR30841: https://llvm.org/bugs/show_bug.cgi?id=30841 @@ -12,7 +12,6 @@ define i8 @PR30841(i64 %argc) { ; CHECK-NEXT: negl %eax ; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> ; CHECK-NEXT: retl -; entry: %or = or i64 %argc, -4294967296 br label %end diff --git a/test/CodeGen/X86/addcarry.ll b/test/CodeGen/X86/addcarry.ll index 3c84af4aa9ec..cffcfd8e8a42 100644 --- a/test/CodeGen/X86/addcarry.ll +++ b/test/CodeGen/X86/addcarry.ll @@ -81,6 +81,30 @@ entry: ret void } +define i8 @e(i32* nocapture %a, i32 %b) nounwind { +; CHECK-LABEL: e: +; CHECK: # BB#0: +; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def> +; CHECK-NEXT: movl (%rdi), %ecx +; CHECK-NEXT: leal (%rsi,%rcx), %edx +; CHECK-NEXT: addl %esi, %edx +; CHECK-NEXT: setb %al +; CHECK-NEXT: addl %esi, %ecx +; CHECK-NEXT: movl %edx, (%rdi) +; CHECK-NEXT: adcb $0, %al +; CHECK-NEXT: retq + %1 = load i32, i32* %a, align 4 + %2 = add i32 %1, %b + %3 = icmp ult i32 %2, %b + %4 = zext i1 %3 to i8 + %5 = add i32 %2, %b + store i32 %5, i32* %a, align 4 + %6 = icmp ult i32 %5, %b + %7 = zext i1 %6 to i8 + %8 = add nuw nsw i8 %7, %4 + ret i8 %8 +} + %scalar = type { [4 x i64] } define %scalar @pr31719(%scalar* nocapture readonly %this, %scalar %arg.b) { diff --git a/test/CodeGen/X86/avx-vperm2x128.ll b/test/CodeGen/X86/avx-vperm2x128.ll index f4a77c370db5..9a21f4b5caba 100644 --- a/test/CodeGen/X86/avx-vperm2x128.ll +++ b/test/CodeGen/X86/avx-vperm2x128.ll @@ -50,16 +50,10 @@ entry: } define <8 x float> @shuffle_v8f32_01230123_mem(<8 x float>* %pa, <8 x float>* %pb) nounwind uwtable readnone ssp { -; AVX1-LABEL: shuffle_v8f32_01230123_mem: -; AVX1: ## BB#0: ## %entry -; AVX1-NEXT: vmovaps (%rdi), %ymm0 -; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 -; AVX1-NEXT: retq -; -; AVX2-LABEL: shuffle_v8f32_01230123_mem: -; AVX2: ## BB#0: ## %entry -; AVX2-NEXT: vperm2f128 {{.*#+}} ymm0 = mem[0,1,0,1] -; AVX2-NEXT: retq +; ALL-LABEL: shuffle_v8f32_01230123_mem: +; ALL: ## BB#0: ## %entry +; ALL-NEXT: vperm2f128 {{.*#+}} ymm0 = mem[0,1,0,1] +; ALL-NEXT: retq entry: %a = load <8 x float>, <8 x float>* %pa %b = load <8 x float>, <8 x float>* %pb @@ -195,17 +189,15 @@ define <16 x i16> @shuffle_v16i16_4501_mem(<16 x i16>* %a, <16 x i16>* %b) nounw ; AVX1-LABEL: shuffle_v16i16_4501_mem: ; AVX1: ## BB#0: ## %entry ; AVX1-NEXT: vmovdqa (%rdi), %ymm0 -; AVX1-NEXT: vmovaps (%rsi), %ymm1 ; AVX1-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0 -; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = mem[0,1],ymm0[0,1] ; AVX1-NEXT: retq ; ; AVX2-LABEL: shuffle_v16i16_4501_mem: ; AVX2: ## BB#0: ## %entry ; AVX2-NEXT: vmovdqa (%rdi), %ymm0 -; AVX2-NEXT: vmovdqa (%rsi), %ymm1 ; AVX2-NEXT: vpaddw {{.*}}(%rip), %ymm0, %ymm0 -; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 +; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = mem[0,1],ymm0[0,1] ; AVX2-NEXT: retq entry: %c = load <16 x i16>, <16 x i16>* %a diff --git a/test/CodeGen/X86/bt.ll b/test/CodeGen/X86/bt.ll index cebcba38bd4f..064058115684 100644 --- a/test/CodeGen/X86/bt.ll +++ b/test/CodeGen/X86/bt.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s ; PR3253 @@ -24,7 +24,12 @@ define void @test2(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jb .LBB0_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB0_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = lshr i32 %x, %n %tmp3 = and i32 %tmp29, 1 @@ -44,7 +49,13 @@ define void @test2b(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jae .LBB1_1 -; +; CHECK-NEXT: # BB#2: # %UnifiedReturnBlock +; CHECK-NEXT: retq +; CHECK-NEXT: .LBB1_1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: retq entry: %tmp29 = lshr i32 %x, %n %tmp3 = and i32 1, %tmp29 @@ -64,7 +75,12 @@ define void @atest2(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jb .LBB2_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB2_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = ashr i32 %x, %n %tmp3 = and i32 %tmp29, 1 @@ -84,7 +100,13 @@ define void @atest2b(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jae .LBB3_1 -; +; CHECK-NEXT: # BB#2: # %UnifiedReturnBlock +; CHECK-NEXT: retq +; CHECK-NEXT: .LBB3_1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: retq entry: %tmp29 = ashr i32 %x, %n %tmp3 = and i32 1, %tmp29 @@ -104,7 +126,13 @@ define void @test3(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jae .LBB4_1 -; +; CHECK-NEXT: # BB#2: # %UnifiedReturnBlock +; CHECK-NEXT: retq +; CHECK-NEXT: .LBB4_1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: retq entry: %tmp29 = shl i32 1, %n %tmp3 = and i32 %tmp29, %x @@ -124,7 +152,13 @@ define void @test3b(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jae .LBB5_1 -; +; CHECK-NEXT: # BB#2: # %UnifiedReturnBlock +; CHECK-NEXT: retq +; CHECK-NEXT: .LBB5_1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: retq entry: %tmp29 = shl i32 1, %n %tmp3 = and i32 %x, %tmp29 @@ -144,7 +178,12 @@ define void @testne2(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jae .LBB6_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB6_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = lshr i32 %x, %n %tmp3 = and i32 %tmp29, 1 @@ -164,7 +203,12 @@ define void @testne2b(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jae .LBB7_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB7_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = lshr i32 %x, %n %tmp3 = and i32 1, %tmp29 @@ -184,7 +228,12 @@ define void @atestne2(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jae .LBB8_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB8_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = ashr i32 %x, %n %tmp3 = and i32 %tmp29, 1 @@ -204,7 +253,12 @@ define void @atestne2b(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jae .LBB9_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB9_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = ashr i32 %x, %n %tmp3 = and i32 1, %tmp29 @@ -224,7 +278,12 @@ define void @testne3(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jae .LBB10_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB10_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = shl i32 1, %n %tmp3 = and i32 %tmp29, %x @@ -244,7 +303,12 @@ define void @testne3b(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jae .LBB11_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB11_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = shl i32 1, %n %tmp3 = and i32 %x, %tmp29 @@ -264,7 +328,12 @@ define void @query2(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jae .LBB12_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB12_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = lshr i32 %x, %n %tmp3 = and i32 %tmp29, 1 @@ -284,7 +353,12 @@ define void @query2b(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jae .LBB13_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB13_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = lshr i32 %x, %n %tmp3 = and i32 1, %tmp29 @@ -304,7 +378,12 @@ define void @aquery2(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jae .LBB14_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB14_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = ashr i32 %x, %n %tmp3 = and i32 %tmp29, 1 @@ -324,7 +403,12 @@ define void @aquery2b(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jae .LBB15_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB15_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = ashr i32 %x, %n %tmp3 = and i32 1, %tmp29 @@ -344,7 +428,12 @@ define void @query3(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jae .LBB16_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB16_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = shl i32 1, %n %tmp3 = and i32 %tmp29, %x @@ -364,7 +453,12 @@ define void @query3b(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jae .LBB17_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB17_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = shl i32 1, %n %tmp3 = and i32 %x, %tmp29 @@ -384,7 +478,12 @@ define void @query3x(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jae .LBB18_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB18_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = shl i32 1, %n %tmp3 = and i32 %tmp29, %x @@ -404,7 +503,12 @@ define void @query3bx(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jae .LBB19_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB19_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = shl i32 1, %n %tmp3 = and i32 %x, %tmp29 @@ -424,7 +528,12 @@ define void @queryne2(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jb .LBB20_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB20_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = lshr i32 %x, %n %tmp3 = and i32 %tmp29, 1 @@ -444,7 +553,12 @@ define void @queryne2b(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jb .LBB21_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB21_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = lshr i32 %x, %n %tmp3 = and i32 1, %tmp29 @@ -464,7 +578,12 @@ define void @aqueryne2(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jb .LBB22_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB22_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = ashr i32 %x, %n %tmp3 = and i32 %tmp29, 1 @@ -484,7 +603,12 @@ define void @aqueryne2b(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jb .LBB23_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB23_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = ashr i32 %x, %n %tmp3 = and i32 1, %tmp29 @@ -504,7 +628,12 @@ define void @queryne3(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jb .LBB24_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB24_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = shl i32 1, %n %tmp3 = and i32 %tmp29, %x @@ -524,7 +653,12 @@ define void @queryne3b(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jb .LBB25_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB25_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = shl i32 1, %n %tmp3 = and i32 %x, %tmp29 @@ -544,7 +678,12 @@ define void @queryne3x(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jb .LBB26_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB26_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = shl i32 1, %n %tmp3 = and i32 %tmp29, %x @@ -564,7 +703,12 @@ define void @queryne3bx(i32 %x, i32 %n) nounwind { ; CHECK: # BB#0: # %entry ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: jb .LBB27_2 -; +; CHECK-NEXT: # BB#1: # %bb +; CHECK-NEXT: pushq %rax +; CHECK-NEXT: callq foo +; CHECK-NEXT: popq %rax +; CHECK-NEXT: .LBB27_2: # %UnifiedReturnBlock +; CHECK-NEXT: retq entry: %tmp29 = shl i32 1, %n %tmp3 = and i32 %x, %tmp29 @@ -588,7 +732,6 @@ define zeroext i1 @invert(i32 %flags, i32 %flag) nounwind { ; CHECK-NEXT: btl %esi, %edi ; CHECK-NEXT: setb %al ; CHECK-NEXT: retq -; %neg = xor i32 %flags, -1 %shl = shl i32 1, %flag %and = and i32 %shl, %neg @@ -598,8 +741,10 @@ define zeroext i1 @invert(i32 %flags, i32 %flag) nounwind { define zeroext i1 @extend(i32 %bit, i64 %bits) { ; CHECK-LABEL: extend: -; CHECK: # BB#0: -; CHECK-NEXT: btl %edi, %esi +; CHECK: # BB#0: # %entry +; CHECK-NEXT: btl %edi, %esi +; CHECK-NEXT: setb %al +; CHECK-NEXT: retq entry: %and = and i32 %bit, 31 %sh_prom = zext i32 %and to i64 diff --git a/test/CodeGen/X86/cmov-into-branch.ll b/test/CodeGen/X86/cmov-into-branch.ll index 6e4762b2e793..e38039501646 100644 --- a/test/CodeGen/X86/cmov-into-branch.ll +++ b/test/CodeGen/X86/cmov-into-branch.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s ; cmp with single-use load, should not form branch. @@ -9,7 +9,6 @@ define i32 @test1(double %a, double* nocapture %b, i32 %x, i32 %y) { ; CHECK-NEXT: cmovbel %edx, %esi ; CHECK-NEXT: movl %esi, %eax ; CHECK-NEXT: retq -; %load = load double, double* %b, align 8 %cmp = fcmp olt double %load, %a %cond = select i1 %cmp, i32 %x, i32 %y @@ -24,7 +23,6 @@ define i32 @test2(double %a, double %b, i32 %x, i32 %y) { ; CHECK-NEXT: cmovbel %esi, %edi ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq -; %cmp = fcmp ogt double %a, %b %cond = select i1 %cmp, i32 %x, i32 %y ret i32 %cond @@ -39,7 +37,6 @@ define i32 @test4(i32 %a, i32* nocapture %b, i32 %x, i32 %y) { ; CHECK-NEXT: cmovael %ecx, %edx ; CHECK-NEXT: addl %edx, %eax ; CHECK-NEXT: retq -; %load = load i32, i32* %b, align 4 %cmp = icmp ult i32 %load, %a %cond = select i1 %cmp, i32 %x, i32 %y @@ -56,7 +53,6 @@ define i32 @test5(i32 %a, i32* nocapture %b, i32 %x, i32 %y) { ; CHECK-NEXT: cmovael %edx, %ecx ; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: retq -; %load = load i32, i32* %b, align 4 %cmp = icmp ult i32 %load, %a %cmp1 = icmp ugt i32 %load, %a @@ -73,7 +69,6 @@ define i32 @weighted_select1(i32 %a, i32 %b) { ; CHECK-NEXT: cmovnel %edi, %esi ; CHECK-NEXT: movl %esi, %eax ; CHECK-NEXT: retq -; %cmp = icmp ne i32 %a, 0 %sel = select i1 %cmp, i32 %a, i32 %b, !prof !0 ret i32 %sel @@ -84,12 +79,12 @@ define i32 @weighted_select2(i32 %a, i32 %b) { ; CHECK-LABEL: weighted_select2: ; CHECK: # BB#0: ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: jne [[LABEL_BB5:.*]] -; CHECK: movl %esi, %edi -; CHECK-NEXT: [[LABEL_BB5]] +; CHECK-NEXT: jne .LBB5_2 +; CHECK-NEXT: # BB#1: # %select.false +; CHECK-NEXT: movl %esi, %edi +; CHECK-NEXT: .LBB5_2: # %select.end ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq -; %cmp = icmp ne i32 %a, 0 %sel = select i1 %cmp, i32 %a, i32 %b, !prof !1 ret i32 %sel @@ -103,14 +98,14 @@ define i32 @weighted_select3(i32 %a, i32 %b) { ; CHECK-LABEL: weighted_select3: ; CHECK: # BB#0: ; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: je [[LABEL_BB6:.*]] -; CHECK: movl %edi, %eax +; CHECK-NEXT: je .LBB6_1 +; CHECK-NEXT: # BB#2: # %select.end +; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq -; CHECK: [[LABEL_BB6]] +; CHECK-NEXT: .LBB6_1: # %select.false ; CHECK-NEXT: movl %esi, %edi ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq -; %cmp = icmp ne i32 %a, 0 %sel = select i1 %cmp, i32 %a, i32 %b, !prof !2 ret i32 %sel @@ -124,7 +119,6 @@ define i32 @unweighted_select(i32 %a, i32 %b) { ; CHECK-NEXT: cmovnel %edi, %esi ; CHECK-NEXT: movl %esi, %eax ; CHECK-NEXT: retq -; %cmp = icmp ne i32 %a, 0 %sel = select i1 %cmp, i32 %a, i32 %b, !prof !3 ret i32 %sel diff --git a/test/CodeGen/X86/combine-64bit-vec-binop.ll b/test/CodeGen/X86/combine-64bit-vec-binop.ll index 2842cb1d9b6e..2935a2095bbf 100644 --- a/test/CodeGen/X86/combine-64bit-vec-binop.ll +++ b/test/CodeGen/X86/combine-64bit-vec-binop.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.1 | FileCheck %s --check-prefix=SSE41 define double @test1_add(double %A, double %B) { @@ -6,7 +6,6 @@ define double @test1_add(double %A, double %B) { ; SSE41: # BB#0: ; SSE41-NEXT: paddd %xmm1, %xmm0 ; SSE41-NEXT: retq -; %1 = bitcast double %A to <2 x i32> %2 = bitcast double %B to <2 x i32> %add = add <2 x i32> %1, %2 @@ -19,7 +18,6 @@ define double @test2_add(double %A, double %B) { ; SSE41: # BB#0: ; SSE41-NEXT: paddw %xmm1, %xmm0 ; SSE41-NEXT: retq -; %1 = bitcast double %A to <4 x i16> %2 = bitcast double %B to <4 x i16> %add = add <4 x i16> %1, %2 @@ -32,7 +30,6 @@ define double @test3_add(double %A, double %B) { ; SSE41: # BB#0: ; SSE41-NEXT: paddb %xmm1, %xmm0 ; SSE41-NEXT: retq -; %1 = bitcast double %A to <8 x i8> %2 = bitcast double %B to <8 x i8> %add = add <8 x i8> %1, %2 @@ -45,7 +42,6 @@ define double @test1_sub(double %A, double %B) { ; SSE41: # BB#0: ; SSE41-NEXT: psubd %xmm1, %xmm0 ; SSE41-NEXT: retq -; %1 = bitcast double %A to <2 x i32> %2 = bitcast double %B to <2 x i32> %sub = sub <2 x i32> %1, %2 @@ -58,7 +54,6 @@ define double @test2_sub(double %A, double %B) { ; SSE41: # BB#0: ; SSE41-NEXT: psubw %xmm1, %xmm0 ; SSE41-NEXT: retq -; %1 = bitcast double %A to <4 x i16> %2 = bitcast double %B to <4 x i16> %sub = sub <4 x i16> %1, %2 @@ -71,7 +66,6 @@ define double @test3_sub(double %A, double %B) { ; SSE41: # BB#0: ; SSE41-NEXT: psubb %xmm1, %xmm0 ; SSE41-NEXT: retq -; %1 = bitcast double %A to <8 x i8> %2 = bitcast double %B to <8 x i8> %sub = sub <8 x i8> %1, %2 @@ -84,7 +78,6 @@ define double @test1_mul(double %A, double %B) { ; SSE41: # BB#0: ; SSE41-NEXT: pmulld %xmm1, %xmm0 ; SSE41-NEXT: retq -; %1 = bitcast double %A to <2 x i32> %2 = bitcast double %B to <2 x i32> %mul = mul <2 x i32> %1, %2 @@ -97,7 +90,6 @@ define double @test2_mul(double %A, double %B) { ; SSE41: # BB#0: ; SSE41-NEXT: pmullw %xmm1, %xmm0 ; SSE41-NEXT: retq -; %1 = bitcast double %A to <4 x i16> %2 = bitcast double %B to <4 x i16> %mul = mul <4 x i16> %1, %2 @@ -114,7 +106,6 @@ define double @test3_mul(double %A, double %B) { ; SSE41-NEXT: pmullw %xmm2, %xmm0 ; SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] ; SSE41-NEXT: retq -; %1 = bitcast double %A to <8 x i8> %2 = bitcast double %B to <8 x i8> %mul = mul <8 x i8> %1, %2 @@ -127,7 +118,6 @@ define double @test1_and(double %A, double %B) { ; SSE41: # BB#0: ; SSE41-NEXT: andps %xmm1, %xmm0 ; SSE41-NEXT: retq -; %1 = bitcast double %A to <2 x i32> %2 = bitcast double %B to <2 x i32> %and = and <2 x i32> %1, %2 @@ -140,7 +130,6 @@ define double @test2_and(double %A, double %B) { ; SSE41: # BB#0: ; SSE41-NEXT: andps %xmm1, %xmm0 ; SSE41-NEXT: retq -; %1 = bitcast double %A to <4 x i16> %2 = bitcast double %B to <4 x i16> %and = and <4 x i16> %1, %2 @@ -153,7 +142,6 @@ define double @test3_and(double %A, double %B) { ; SSE41: # BB#0: ; SSE41-NEXT: andps %xmm1, %xmm0 ; SSE41-NEXT: retq -; %1 = bitcast double %A to <8 x i8> %2 = bitcast double %B to <8 x i8> %and = and <8 x i8> %1, %2 @@ -166,7 +154,6 @@ define double @test1_or(double %A, double %B) { ; SSE41: # BB#0: ; SSE41-NEXT: orps %xmm1, %xmm0 ; SSE41-NEXT: retq -; %1 = bitcast double %A to <2 x i32> %2 = bitcast double %B to <2 x i32> %or = or <2 x i32> %1, %2 @@ -179,7 +166,6 @@ define double @test2_or(double %A, double %B) { ; SSE41: # BB#0: ; SSE41-NEXT: orps %xmm1, %xmm0 ; SSE41-NEXT: retq -; %1 = bitcast double %A to <4 x i16> %2 = bitcast double %B to <4 x i16> %or = or <4 x i16> %1, %2 @@ -192,7 +178,6 @@ define double @test3_or(double %A, double %B) { ; SSE41: # BB#0: ; SSE41-NEXT: orps %xmm1, %xmm0 ; SSE41-NEXT: retq -; %1 = bitcast double %A to <8 x i8> %2 = bitcast double %B to <8 x i8> %or = or <8 x i8> %1, %2 @@ -205,7 +190,6 @@ define double @test1_xor(double %A, double %B) { ; SSE41: # BB#0: ; SSE41-NEXT: xorps %xmm1, %xmm0 ; SSE41-NEXT: retq -; %1 = bitcast double %A to <2 x i32> %2 = bitcast double %B to <2 x i32> %xor = xor <2 x i32> %1, %2 @@ -218,7 +202,6 @@ define double @test2_xor(double %A, double %B) { ; SSE41: # BB#0: ; SSE41-NEXT: xorps %xmm1, %xmm0 ; SSE41-NEXT: retq -; %1 = bitcast double %A to <4 x i16> %2 = bitcast double %B to <4 x i16> %xor = xor <4 x i16> %1, %2 @@ -231,7 +214,6 @@ define double @test3_xor(double %A, double %B) { ; SSE41: # BB#0: ; SSE41-NEXT: xorps %xmm1, %xmm0 ; SSE41-NEXT: retq -; %1 = bitcast double %A to <8 x i8> %2 = bitcast double %B to <8 x i8> %xor = xor <8 x i8> %1, %2 @@ -244,7 +226,6 @@ define double @test_fadd(double %A, double %B) { ; SSE41: # BB#0: ; SSE41-NEXT: addps %xmm1, %xmm0 ; SSE41-NEXT: retq -; %1 = bitcast double %A to <2 x float> %2 = bitcast double %B to <2 x float> %add = fadd <2 x float> %1, %2 @@ -257,7 +238,6 @@ define double @test_fsub(double %A, double %B) { ; SSE41: # BB#0: ; SSE41-NEXT: subps %xmm1, %xmm0 ; SSE41-NEXT: retq -; %1 = bitcast double %A to <2 x float> %2 = bitcast double %B to <2 x float> %sub = fsub <2 x float> %1, %2 @@ -270,7 +250,6 @@ define double @test_fmul(double %A, double %B) { ; SSE41: # BB#0: ; SSE41-NEXT: mulps %xmm1, %xmm0 ; SSE41-NEXT: retq -; %1 = bitcast double %A to <2 x float> %2 = bitcast double %B to <2 x float> %mul = fmul <2 x float> %1, %2 diff --git a/test/CodeGen/X86/element-wise-atomic-memory-intrinsics.ll b/test/CodeGen/X86/element-wise-atomic-memory-intrinsics.ll index 4dc5b1ba0339..9dd184c8ab31 100644 --- a/test/CodeGen/X86/element-wise-atomic-memory-intrinsics.ll +++ b/test/CodeGen/X86/element-wise-atomic-memory-intrinsics.ll @@ -2,47 +2,47 @@ define i8* @test_memcpy1(i8* %P, i8* %Q) { ; CHECK: test_memcpy - call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 4 %P, i8* align 4 %Q, i64 1, i32 1) + call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* align 4 %Q, i32 1, i32 1) ret i8* %P + ; 3rd arg (%edx) -- length ; CHECK-DAG: movl $1, %edx - ; CHECK-DAG: movl $1, %ecx - ; CHECK: __llvm_memcpy_element_atomic_1 + ; CHECK: __llvm_memcpy_element_unordered_atomic_1 } define i8* @test_memcpy2(i8* %P, i8* %Q) { ; CHECK: test_memcpy2 - call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 4 %P, i8* align 4 %Q, i64 2, i32 2) + call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* align 4 %Q, i32 2, i32 2) ret i8* %P + ; 3rd arg (%edx) -- length ; CHECK-DAG: movl $2, %edx - ; CHECK-DAG: movl $2, %ecx - ; CHECK: __llvm_memcpy_element_atomic_2 + ; CHECK: __llvm_memcpy_element_unordered_atomic_2 } define i8* @test_memcpy4(i8* %P, i8* %Q) { ; CHECK: test_memcpy4 - call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 4 %P, i8* align 4 %Q, i64 4, i32 4) + call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* align 4 %Q, i32 4, i32 4) ret i8* %P + ; 3rd arg (%edx) -- length ; CHECK-DAG: movl $4, %edx - ; CHECK-DAG: movl $4, %ecx - ; CHECK: __llvm_memcpy_element_atomic_4 + ; CHECK: __llvm_memcpy_element_unordered_atomic_4 } define i8* @test_memcpy8(i8* %P, i8* %Q) { ; CHECK: test_memcpy8 - call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 8 %P, i8* align 8 %Q, i64 8, i32 8) + call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 8 %P, i8* align 8 %Q, i32 8, i32 8) ret i8* %P + ; 3rd arg (%edx) -- length ; CHECK-DAG: movl $8, %edx - ; CHECK-DAG: movl $8, %ecx - ; CHECK: __llvm_memcpy_element_atomic_8 + ; CHECK: __llvm_memcpy_element_unordered_atomic_8 } define i8* @test_memcpy16(i8* %P, i8* %Q) { ; CHECK: test_memcpy16 - call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 16 %P, i8* align 16 %Q, i64 16, i32 16) + call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 16 %P, i8* align 16 %Q, i32 16, i32 16) ret i8* %P + ; 3rd arg (%edx) -- length ; CHECK-DAG: movl $16, %edx - ; CHECK-DAG: movl $16, %ecx - ; CHECK: __llvm_memcpy_element_atomic_16 + ; CHECK: __llvm_memcpy_element_unordered_atomic_16 } define void @test_memcpy_args(i8** %Storage) { @@ -51,18 +51,15 @@ define void @test_memcpy_args(i8** %Storage) { %Src.addr = getelementptr i8*, i8** %Storage, i64 1 %Src = load i8*, i8** %Src.addr - ; First argument + ; 1st arg (%rdi) ; CHECK-DAG: movq (%rdi), [[REG1:%r.+]] ; CHECK-DAG: movq [[REG1]], %rdi - ; Second argument + ; 2nd arg (%rsi) ; CHECK-DAG: movq 8(%rdi), %rsi - ; Third argument + ; 3rd arg (%edx) -- length ; CHECK-DAG: movl $4, %edx - ; Fourth argument - ; CHECK-DAG: movl $4, %ecx - ; CHECK: __llvm_memcpy_element_atomic_4 - call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 4 %Dst, i8* align 4 %Src, i64 4, i32 4) - ret void + ; CHECK: __llvm_memcpy_element_unordered_atomic_4 + call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %Dst, i8* align 4 %Src, i32 4, i32 4) ret void } -declare void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* nocapture, i8* nocapture, i64, i32) nounwind +declare void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32) nounwind diff --git a/test/CodeGen/X86/fast-isel-select-sse.ll b/test/CodeGen/X86/fast-isel-select-sse.ll index 499fe5ba54a2..1b6bb36b77c8 100644 --- a/test/CodeGen/X86/fast-isel-select-sse.ll +++ b/test/CodeGen/X86/fast-isel-select-sse.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=SSE ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=SSE ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -verify-machineinstrs -mattr=avx | FileCheck %s --check-prefix=AVX @@ -29,7 +29,6 @@ define float @select_fcmp_oeq_f32(float %a, float %b, float %c, float %d) { ; AVX512-NEXT: vmovss %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovaps %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp oeq float %a, %b %2 = select i1 %1, float %c, float %d ret float %2 @@ -56,7 +55,6 @@ define double @select_fcmp_oeq_f64(double %a, double %b, double %c, double %d) { ; AVX512-NEXT: vmovsd %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovapd %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp oeq double %a, %b %2 = select i1 %1, double %c, double %d ret double %2 @@ -84,7 +82,6 @@ define float @select_fcmp_ogt_f32(float %a, float %b, float %c, float %d) { ; AVX512-NEXT: vmovss %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovaps %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp ogt float %a, %b %2 = select i1 %1, float %c, float %d ret float %2 @@ -112,7 +109,6 @@ define double @select_fcmp_ogt_f64(double %a, double %b, double %c, double %d) { ; AVX512-NEXT: vmovsd %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovapd %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp ogt double %a, %b %2 = select i1 %1, double %c, double %d ret double %2 @@ -140,7 +136,6 @@ define float @select_fcmp_oge_f32(float %a, float %b, float %c, float %d) { ; AVX512-NEXT: vmovss %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovaps %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp oge float %a, %b %2 = select i1 %1, float %c, float %d ret float %2 @@ -168,7 +163,6 @@ define double @select_fcmp_oge_f64(double %a, double %b, double %c, double %d) { ; AVX512-NEXT: vmovsd %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovapd %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp oge double %a, %b %2 = select i1 %1, double %c, double %d ret double %2 @@ -195,7 +189,6 @@ define float @select_fcmp_olt_f32(float %a, float %b, float %c, float %d) { ; AVX512-NEXT: vmovss %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovaps %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp olt float %a, %b %2 = select i1 %1, float %c, float %d ret float %2 @@ -222,7 +215,6 @@ define double @select_fcmp_olt_f64(double %a, double %b, double %c, double %d) { ; AVX512-NEXT: vmovsd %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovapd %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp olt double %a, %b %2 = select i1 %1, double %c, double %d ret double %2 @@ -249,7 +241,6 @@ define float @select_fcmp_ole_f32(float %a, float %b, float %c, float %d) { ; AVX512-NEXT: vmovss %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovaps %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp ole float %a, %b %2 = select i1 %1, float %c, float %d ret float %2 @@ -276,7 +267,6 @@ define double @select_fcmp_ole_f64(double %a, double %b, double %c, double %d) { ; AVX512-NEXT: vmovsd %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovapd %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp ole double %a, %b %2 = select i1 %1, double %c, double %d ret double %2 @@ -303,7 +293,6 @@ define float @select_fcmp_ord_f32(float %a, float %b, float %c, float %d) { ; AVX512-NEXT: vmovss %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovaps %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp ord float %a, %b %2 = select i1 %1, float %c, float %d ret float %2 @@ -330,7 +319,6 @@ define double @select_fcmp_ord_f64(double %a, double %b, double %c, double %d) { ; AVX512-NEXT: vmovsd %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovapd %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp ord double %a, %b %2 = select i1 %1, double %c, double %d ret double %2 @@ -357,7 +345,6 @@ define float @select_fcmp_uno_f32(float %a, float %b, float %c, float %d) { ; AVX512-NEXT: vmovss %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovaps %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp uno float %a, %b %2 = select i1 %1, float %c, float %d ret float %2 @@ -384,7 +371,6 @@ define double @select_fcmp_uno_f64(double %a, double %b, double %c, double %d) { ; AVX512-NEXT: vmovsd %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovapd %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp uno double %a, %b %2 = select i1 %1, double %c, double %d ret double %2 @@ -411,7 +397,6 @@ define float @select_fcmp_ugt_f32(float %a, float %b, float %c, float %d) { ; AVX512-NEXT: vmovss %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovaps %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp ugt float %a, %b %2 = select i1 %1, float %c, float %d ret float %2 @@ -438,7 +423,6 @@ define double @select_fcmp_ugt_f64(double %a, double %b, double %c, double %d) { ; AVX512-NEXT: vmovsd %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovapd %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp ugt double %a, %b %2 = select i1 %1, double %c, double %d ret double %2 @@ -465,7 +449,6 @@ define float @select_fcmp_uge_f32(float %a, float %b, float %c, float %d) { ; AVX512-NEXT: vmovss %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovaps %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp uge float %a, %b %2 = select i1 %1, float %c, float %d ret float %2 @@ -492,7 +475,6 @@ define double @select_fcmp_uge_f64(double %a, double %b, double %c, double %d) { ; AVX512-NEXT: vmovsd %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovapd %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp uge double %a, %b %2 = select i1 %1, double %c, double %d ret double %2 @@ -520,7 +502,6 @@ define float @select_fcmp_ult_f32(float %a, float %b, float %c, float %d) { ; AVX512-NEXT: vmovss %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovaps %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp ult float %a, %b %2 = select i1 %1, float %c, float %d ret float %2 @@ -548,7 +529,6 @@ define double @select_fcmp_ult_f64(double %a, double %b, double %c, double %d) { ; AVX512-NEXT: vmovsd %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovapd %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp ult double %a, %b %2 = select i1 %1, double %c, double %d ret double %2 @@ -576,7 +556,6 @@ define float @select_fcmp_ule_f32(float %a, float %b, float %c, float %d) { ; AVX512-NEXT: vmovss %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovaps %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp ule float %a, %b %2 = select i1 %1, float %c, float %d ret float %2 @@ -604,7 +583,6 @@ define double @select_fcmp_ule_f64(double %a, double %b, double %c, double %d) { ; AVX512-NEXT: vmovsd %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovapd %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp ule double %a, %b %2 = select i1 %1, double %c, double %d ret double %2 @@ -631,7 +609,6 @@ define float @select_fcmp_une_f32(float %a, float %b, float %c, float %d) { ; AVX512-NEXT: vmovss %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovaps %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp une float %a, %b %2 = select i1 %1, float %c, float %d ret float %2 @@ -658,7 +635,6 @@ define double @select_fcmp_une_f64(double %a, double %b, double %c, double %d) { ; AVX512-NEXT: vmovsd %xmm2, %xmm0, %xmm3 {%k1} ; AVX512-NEXT: vmovapd %xmm3, %xmm0 ; AVX512-NEXT: retq -; %1 = fcmp une double %a, %b %2 = select i1 %1, double %c, double %d ret double %2 diff --git a/test/CodeGen/X86/fp-logic-replace.ll b/test/CodeGen/X86/fp-logic-replace.ll index 308b42e10caa..e62b2f3db237 100644 --- a/test/CodeGen/X86/fp-logic-replace.ll +++ b/test/CodeGen/X86/fp-logic-replace.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding -mattr=+sse2 | FileCheck %s --check-prefix=SSE ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding -mattr=+avx | FileCheck %s --check-prefix=AVX ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=AVX512DQ diff --git a/test/CodeGen/X86/fp-logic.ll b/test/CodeGen/X86/fp-logic.ll index 973e0644b4e9..976470a83030 100644 --- a/test/CodeGen/X86/fp-logic.ll +++ b/test/CodeGen/X86/fp-logic.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=sse2 < %s | FileCheck %s ; PR22428: https://llvm.org/bugs/show_bug.cgi?id=22428 @@ -22,7 +22,6 @@ define i32 @f1(float %x, i32 %y) { ; CHECK-NEXT: movd %xmm0, %eax ; CHECK-NEXT: andl %edi, %eax ; CHECK-NEXT: retq -; %bc1 = bitcast float %x to i32 %and = and i32 %bc1, %y ret i32 %and @@ -36,7 +35,6 @@ define i32 @f2(float %x, i32 %y) { ; CHECK-NEXT: movd %xmm0, %eax ; CHECK-NEXT: andl %edi, %eax ; CHECK-NEXT: retq -; %bc1 = bitcast float %x to i32 %and = and i32 %y, %bc1 ret i32 %and @@ -50,7 +48,6 @@ define i32 @f3(float %x) { ; CHECK-NEXT: movd %xmm0, %eax ; CHECK-NEXT: andl $1, %eax ; CHECK-NEXT: retq -; %bc1 = bitcast float %x to i32 %and = and i32 %bc1, 1 ret i32 %and @@ -64,7 +61,6 @@ define i32 @f4(float %x) { ; CHECK-NEXT: movd %xmm0, %eax ; CHECK-NEXT: andl $2, %eax ; CHECK-NEXT: retq -; %bc1 = bitcast float %x to i32 %and = and i32 2, %bc1 ret i32 %and @@ -78,7 +74,6 @@ define float @f5(float %x, i32 %y) { ; CHECK-NEXT: movd %edi, %xmm1 ; CHECK-NEXT: pand %xmm1, %xmm0 ; CHECK-NEXT: retq -; %bc1 = bitcast float %x to i32 %and = and i32 %bc1, %y %bc2 = bitcast i32 %and to float @@ -93,7 +88,6 @@ define float @f6(float %x, i32 %y) { ; CHECK-NEXT: movd %edi, %xmm1 ; CHECK-NEXT: pand %xmm1, %xmm0 ; CHECK-NEXT: retq -; %bc1 = bitcast float %x to i32 %and = and i32 %y, %bc1 %bc2 = bitcast i32 %and to float @@ -108,7 +102,6 @@ define float @f7(float %x) { ; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: andps %xmm1, %xmm0 ; CHECK-NEXT: retq -; %bc1 = bitcast float %x to i32 %and = and i32 %bc1, 3 %bc2 = bitcast i32 %and to float @@ -123,7 +116,6 @@ define float @f8(float %x) { ; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: andps %xmm1, %xmm0 ; CHECK-NEXT: retq -; %bc1 = bitcast float %x to i32 %and = and i32 4, %bc1 %bc2 = bitcast i32 %and to float @@ -138,7 +130,6 @@ define i32 @f9(float %x, float %y) { ; CHECK-NEXT: pand %xmm1, %xmm0 ; CHECK-NEXT: movd %xmm0, %eax ; CHECK-NEXT: retq -; %bc1 = bitcast float %x to i32 %bc2 = bitcast float %y to i32 %and = and i32 %bc1, %bc2 @@ -152,7 +143,6 @@ define float @f10(float %x, float %y) { ; CHECK: # BB#0: ; CHECK-NEXT: andps %xmm1, %xmm0 ; CHECK-NEXT: retq -; %bc1 = bitcast float %x to i32 %bc2 = bitcast float %y to i32 %and = and i32 %bc1, %bc2 @@ -165,7 +155,6 @@ define float @or(float %x, float %y) { ; CHECK: # BB#0: ; CHECK-NEXT: orps %xmm1, %xmm0 ; CHECK-NEXT: retq -; %bc1 = bitcast float %x to i32 %bc2 = bitcast float %y to i32 %and = or i32 %bc1, %bc2 @@ -178,7 +167,6 @@ define float @xor(float %x, float %y) { ; CHECK: # BB#0: ; CHECK-NEXT: xorps %xmm1, %xmm0 ; CHECK-NEXT: retq -; %bc1 = bitcast float %x to i32 %bc2 = bitcast float %y to i32 %and = xor i32 %bc1, %bc2 @@ -192,7 +180,6 @@ define float @f7_or(float %x) { ; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: orps %xmm1, %xmm0 ; CHECK-NEXT: retq -; %bc1 = bitcast float %x to i32 %and = or i32 %bc1, 3 %bc2 = bitcast i32 %and to float @@ -205,7 +192,6 @@ define float @f7_xor(float %x) { ; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: xorps %xmm1, %xmm0 ; CHECK-NEXT: retq -; %bc1 = bitcast float %x to i32 %and = xor i32 %bc1, 3 %bc2 = bitcast i32 %and to float @@ -219,7 +205,6 @@ define double @doubles(double %x, double %y) { ; CHECK: # BB#0: ; CHECK-NEXT: andps %xmm1, %xmm0 ; CHECK-NEXT: retq -; %bc1 = bitcast double %x to i64 %bc2 = bitcast double %y to i64 %and = and i64 %bc1, %bc2 @@ -233,7 +218,6 @@ define double @f7_double(double %x) { ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; CHECK-NEXT: andps %xmm1, %xmm0 ; CHECK-NEXT: retq -; %bc1 = bitcast double %x to i64 %and = and i64 %bc1, 3 %bc2 = bitcast i64 %and to double @@ -250,7 +234,6 @@ define float @movmsk(float %x) { ; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: andps %xmm1, %xmm0 ; CHECK-NEXT: retq -; %bc1 = bitcast float %x to i32 %and = and i32 %bc1, 2147483648 %bc2 = bitcast i32 %and to float @@ -262,7 +245,6 @@ define double @bitcast_fabs(double %x) { ; CHECK: # BB#0: ; CHECK-NEXT: andps {{.*}}(%rip), %xmm0 ; CHECK-NEXT: retq -; %bc1 = bitcast double %x to i64 %and = and i64 %bc1, 9223372036854775807 %bc2 = bitcast i64 %and to double @@ -274,7 +256,6 @@ define float @bitcast_fneg(float %x) { ; CHECK: # BB#0: ; CHECK-NEXT: xorps {{.*}}(%rip), %xmm0 ; CHECK-NEXT: retq -; %bc1 = bitcast float %x to i32 %xor = xor i32 %bc1, 2147483648 %bc2 = bitcast i32 %xor to float @@ -286,7 +267,6 @@ define <2 x double> @bitcast_fabs_vec(<2 x double> %x) { ; CHECK: # BB#0: ; CHECK-NEXT: andps {{.*}}(%rip), %xmm0 ; CHECK-NEXT: retq -; %bc1 = bitcast <2 x double> %x to <2 x i64> %and = and <2 x i64> %bc1, <i64 9223372036854775807, i64 9223372036854775807> %bc2 = bitcast <2 x i64> %and to <2 x double> @@ -298,7 +278,6 @@ define <4 x float> @bitcast_fneg_vec(<4 x float> %x) { ; CHECK: # BB#0: ; CHECK-NEXT: xorps {{.*}}(%rip), %xmm0 ; CHECK-NEXT: retq -; %bc1 = bitcast <4 x float> %x to <4 x i32> %xor = xor <4 x i32> %bc1, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648> %bc2 = bitcast <4 x i32> %xor to <4 x float> diff --git a/test/CodeGen/X86/fp-select-cmp-and.ll b/test/CodeGen/X86/fp-select-cmp-and.ll index e012809cf480..651d7a3351c6 100644 --- a/test/CodeGen/X86/fp-select-cmp-and.ll +++ b/test/CodeGen/X86/fp-select-cmp-and.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.2 | FileCheck %s define double @test1(double %a, double %b, double %eps) { @@ -7,7 +7,6 @@ define double @test1(double %a, double %b, double %eps) { ; CHECK-NEXT: cmpltsd %xmm2, %xmm0 ; CHECK-NEXT: andpd %xmm1, %xmm0 ; CHECK-NEXT: retq -; %cmp = fcmp olt double %a, %eps %cond = select i1 %cmp, double %b, double 0.000000e+00 ret double %cond @@ -19,7 +18,6 @@ define double @test2(double %a, double %b, double %eps) { ; CHECK-NEXT: cmplesd %xmm2, %xmm0 ; CHECK-NEXT: andpd %xmm1, %xmm0 ; CHECK-NEXT: retq -; %cmp = fcmp ole double %a, %eps %cond = select i1 %cmp, double %b, double 0.000000e+00 ret double %cond @@ -32,7 +30,6 @@ define double @test3(double %a, double %b, double %eps) { ; CHECK-NEXT: andpd %xmm1, %xmm2 ; CHECK-NEXT: movapd %xmm2, %xmm0 ; CHECK-NEXT: retq -; %cmp = fcmp ogt double %a, %eps %cond = select i1 %cmp, double %b, double 0.000000e+00 ret double %cond @@ -45,7 +42,6 @@ define double @test4(double %a, double %b, double %eps) { ; CHECK-NEXT: andpd %xmm1, %xmm2 ; CHECK-NEXT: movapd %xmm2, %xmm0 ; CHECK-NEXT: retq -; %cmp = fcmp oge double %a, %eps %cond = select i1 %cmp, double %b, double 0.000000e+00 ret double %cond @@ -57,7 +53,6 @@ define double @test5(double %a, double %b, double %eps) { ; CHECK-NEXT: cmpltsd %xmm2, %xmm0 ; CHECK-NEXT: andnpd %xmm1, %xmm0 ; CHECK-NEXT: retq -; %cmp = fcmp olt double %a, %eps %cond = select i1 %cmp, double 0.000000e+00, double %b ret double %cond @@ -69,7 +64,6 @@ define double @test6(double %a, double %b, double %eps) { ; CHECK-NEXT: cmplesd %xmm2, %xmm0 ; CHECK-NEXT: andnpd %xmm1, %xmm0 ; CHECK-NEXT: retq -; %cmp = fcmp ole double %a, %eps %cond = select i1 %cmp, double 0.000000e+00, double %b ret double %cond @@ -82,7 +76,6 @@ define double @test7(double %a, double %b, double %eps) { ; CHECK-NEXT: andnpd %xmm1, %xmm2 ; CHECK-NEXT: movapd %xmm2, %xmm0 ; CHECK-NEXT: retq -; %cmp = fcmp ogt double %a, %eps %cond = select i1 %cmp, double 0.000000e+00, double %b ret double %cond @@ -95,7 +88,6 @@ define double @test8(double %a, double %b, double %eps) { ; CHECK-NEXT: andnpd %xmm1, %xmm2 ; CHECK-NEXT: movapd %xmm2, %xmm0 ; CHECK-NEXT: retq -; %cmp = fcmp oge double %a, %eps %cond = select i1 %cmp, double 0.000000e+00, double %b ret double %cond @@ -107,7 +99,6 @@ define float @test9(float %a, float %b, float %eps) { ; CHECK-NEXT: cmpltss %xmm2, %xmm0 ; CHECK-NEXT: andps %xmm1, %xmm0 ; CHECK-NEXT: retq -; %cmp = fcmp olt float %a, %eps %cond = select i1 %cmp, float %b, float 0.000000e+00 ret float %cond @@ -119,7 +110,6 @@ define float @test10(float %a, float %b, float %eps) { ; CHECK-NEXT: cmpless %xmm2, %xmm0 ; CHECK-NEXT: andps %xmm1, %xmm0 ; CHECK-NEXT: retq -; %cmp = fcmp ole float %a, %eps %cond = select i1 %cmp, float %b, float 0.000000e+00 ret float %cond @@ -132,7 +122,6 @@ define float @test11(float %a, float %b, float %eps) { ; CHECK-NEXT: andps %xmm1, %xmm2 ; CHECK-NEXT: movaps %xmm2, %xmm0 ; CHECK-NEXT: retq -; %cmp = fcmp ogt float %a, %eps %cond = select i1 %cmp, float %b, float 0.000000e+00 ret float %cond @@ -145,7 +134,6 @@ define float @test12(float %a, float %b, float %eps) { ; CHECK-NEXT: andps %xmm1, %xmm2 ; CHECK-NEXT: movaps %xmm2, %xmm0 ; CHECK-NEXT: retq -; %cmp = fcmp oge float %a, %eps %cond = select i1 %cmp, float %b, float 0.000000e+00 ret float %cond @@ -157,7 +145,6 @@ define float @test13(float %a, float %b, float %eps) { ; CHECK-NEXT: cmpltss %xmm2, %xmm0 ; CHECK-NEXT: andnps %xmm1, %xmm0 ; CHECK-NEXT: retq -; %cmp = fcmp olt float %a, %eps %cond = select i1 %cmp, float 0.000000e+00, float %b ret float %cond @@ -169,7 +156,6 @@ define float @test14(float %a, float %b, float %eps) { ; CHECK-NEXT: cmpless %xmm2, %xmm0 ; CHECK-NEXT: andnps %xmm1, %xmm0 ; CHECK-NEXT: retq -; %cmp = fcmp ole float %a, %eps %cond = select i1 %cmp, float 0.000000e+00, float %b ret float %cond @@ -182,7 +168,6 @@ define float @test15(float %a, float %b, float %eps) { ; CHECK-NEXT: andnps %xmm1, %xmm2 ; CHECK-NEXT: movaps %xmm2, %xmm0 ; CHECK-NEXT: retq -; %cmp = fcmp ogt float %a, %eps %cond = select i1 %cmp, float 0.000000e+00, float %b ret float %cond @@ -195,7 +180,6 @@ define float @test16(float %a, float %b, float %eps) { ; CHECK-NEXT: andnps %xmm1, %xmm2 ; CHECK-NEXT: movaps %xmm2, %xmm0 ; CHECK-NEXT: retq -; %cmp = fcmp oge float %a, %eps %cond = select i1 %cmp, float 0.000000e+00, float %b ret float %cond @@ -210,7 +194,6 @@ define float @test17(float %a, float %b, float %c, float %eps) { ; CHECK-NEXT: orps %xmm2, %xmm3 ; CHECK-NEXT: movaps %xmm3, %xmm0 ; CHECK-NEXT: retq -; %cmp = fcmp oge float %a, %eps %cond = select i1 %cmp, float %c, float %b ret float %cond @@ -225,7 +208,6 @@ define double @test18(double %a, double %b, double %c, double %eps) { ; CHECK-NEXT: orpd %xmm2, %xmm3 ; CHECK-NEXT: movapd %xmm3, %xmm0 ; CHECK-NEXT: retq -; %cmp = fcmp oge double %a, %eps %cond = select i1 %cmp, double %c, double %b ret double %cond diff --git a/test/CodeGen/X86/immediate_merging64.ll b/test/CodeGen/X86/immediate_merging64.ll index ea8ace12a868..4bc9d4af6440 100644 --- a/test/CodeGen/X86/immediate_merging64.ll +++ b/test/CodeGen/X86/immediate_merging64.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s ; Check that multiple instances of 64-bit constants encodable as @@ -14,7 +14,6 @@ define i1 @imm_multiple_users(i64 %a, i64* %b) optsize { ; CHECK-NEXT: cmpq %rax, %rdi ; CHECK-NEXT: sete %al ; CHECK-NEXT: retq -; store i64 -1, i64* %b, align 8 %cmp = icmp eq i64 %a, -1 ret i1 %cmp @@ -32,7 +31,6 @@ define void @memset_zero(i8* noalias nocapture %D) optsize { ; CHECK-NEXT: movq %rax, 7(%rdi) ; CHECK-NEXT: movq %rax, (%rdi) ; CHECK-NEXT: retq -; tail call void @llvm.memset.p0i8.i64(i8* %D, i8 0, i64 15, i32 1, i1 false) ret void } diff --git a/test/CodeGen/X86/lea-opt-with-debug.mir b/test/CodeGen/X86/lea-opt-with-debug.mir index 0a477706df15..03a745888b5a 100644 --- a/test/CodeGen/X86/lea-opt-with-debug.mir +++ b/test/CodeGen/X86/lea-opt-with-debug.mir @@ -49,7 +49,7 @@ !5 = !{i32 2, !"Dwarf Version", i32 4} !6 = !{i32 2, !"Debug Info Version", i32 3} !7 = !{i32 1, !"PIC Level", i32 2} - !8 = !DIExpression(DW_OP_plus, 8, DW_OP_stack_value) + !8 = !DIExpression(DW_OP_plus_uconst, 8, DW_OP_stack_value) !9 = distinct !DISubprogram(name: "fn1", scope: !1, file: !1, line: 7, type: !10, isLocal: false, isDefinition: true, scopeLine: 7, isOptimized: true, unit: !0, variables: !11) !10 = !DISubroutineType(types: !3) !11 = !{!12} diff --git a/test/CodeGen/X86/loop-search.ll b/test/CodeGen/X86/loop-search.ll index 6b29a726fc1f..fda4ecec0e6a 100644 --- a/test/CodeGen/X86/loop-search.ll +++ b/test/CodeGen/X86/loop-search.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s ; This test comes from PR27136 @@ -35,7 +35,6 @@ define zeroext i1 @search(i32 %needle, i32* nocapture readonly %haystack, i32 %c ; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill> ; CHECK-NEXT: retq -; entry: %cmp5 = icmp sgt i32 %count, 0 br i1 %cmp5, label %for.body.preheader, label %cleanup diff --git a/test/CodeGen/X86/mask-negated-bool.ll b/test/CodeGen/X86/mask-negated-bool.ll index c5c121c52966..779641cee7d2 100644 --- a/test/CodeGen/X86/mask-negated-bool.ll +++ b/test/CodeGen/X86/mask-negated-bool.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s define i32 @mask_negated_zext_bool1(i1 %x) { @@ -7,7 +7,6 @@ define i32 @mask_negated_zext_bool1(i1 %x) { ; CHECK-NEXT: andl $1, %edi ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq -; %ext = zext i1 %x to i32 %neg = sub i32 0, %ext %and = and i32 %neg, 1 @@ -19,7 +18,6 @@ define i32 @mask_negated_zext_bool2(i1 zeroext %x) { ; CHECK: # BB#0: ; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: retq -; %ext = zext i1 %x to i32 %neg = sub i32 0, %ext %and = and i32 %neg, 1 @@ -31,7 +29,6 @@ define <4 x i32> @mask_negated_zext_bool_vec(<4 x i1> %x) { ; CHECK: # BB#0: ; CHECK-NEXT: andps {{.*}}(%rip), %xmm0 ; CHECK-NEXT: retq -; %ext = zext <4 x i1> %x to <4 x i32> %neg = sub <4 x i32> zeroinitializer, %ext %and = and <4 x i32> %neg, <i32 1, i32 1, i32 1, i32 1> @@ -44,7 +41,6 @@ define i32 @mask_negated_sext_bool1(i1 %x) { ; CHECK-NEXT: andl $1, %edi ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq -; %ext = sext i1 %x to i32 %neg = sub i32 0, %ext %and = and i32 %neg, 1 @@ -56,7 +52,6 @@ define i32 @mask_negated_sext_bool2(i1 zeroext %x) { ; CHECK: # BB#0: ; CHECK-NEXT: movzbl %dil, %eax ; CHECK-NEXT: retq -; %ext = sext i1 %x to i32 %neg = sub i32 0, %ext %and = and i32 %neg, 1 @@ -68,7 +63,6 @@ define <4 x i32> @mask_negated_sext_bool_vec(<4 x i1> %x) { ; CHECK: # BB#0: ; CHECK-NEXT: andps {{.*}}(%rip), %xmm0 ; CHECK-NEXT: retq -; %ext = sext <4 x i1> %x to <4 x i32> %neg = sub <4 x i32> zeroinitializer, %ext %and = and <4 x i32> %neg, <i32 1, i32 1, i32 1, i32 1> diff --git a/test/CodeGen/X86/memset-2.ll b/test/CodeGen/X86/memset-2.ll index a02ef29ca6b3..1ac972048f12 100644 --- a/test/CodeGen/X86/memset-2.ll +++ b/test/CodeGen/X86/memset-2.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=i386-apple-darwin9 -mcpu=yonah < %s | FileCheck %s define fastcc void @t1() nounwind { @@ -10,7 +10,6 @@ define fastcc void @t1() nounwind { ; CHECK-NEXT: pushl $0 ; CHECK-NEXT: calll _memset ; CHECK-NEXT: addl $16, %esp -; entry: call void @llvm.memset.p0i8.i32(i8* null, i8 0, i32 188, i32 1, i1 false) unreachable @@ -23,7 +22,6 @@ define fastcc void @t2(i8 signext %c) nounwind { ; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $76, {{[0-9]+}}(%esp) ; CHECK-NEXT: calll _memset -; entry: call void @llvm.memset.p0i8.i32(i8* undef, i8 %c, i32 76, i32 1, i1 false) unreachable @@ -40,7 +38,6 @@ define void @t3(i8* nocapture %s, i8 %a) nounwind { ; CHECK-NEXT: movl %ecx, 4(%eax) ; CHECK-NEXT: movl %ecx, (%eax) ; CHECK-NEXT: retl -; entry: tail call void @llvm.memset.p0i8.i32(i8* %s, i8 %a, i32 8, i32 1, i1 false) ret void @@ -58,7 +55,6 @@ define void @t4(i8* nocapture %s, i8 %a) nounwind { ; CHECK-NEXT: movw %cx, 12(%eax) ; CHECK-NEXT: movb %cl, 14(%eax) ; CHECK-NEXT: retl -; entry: tail call void @llvm.memset.p0i8.i32(i8* %s, i8 %a, i32 15, i32 1, i1 false) ret void diff --git a/test/CodeGen/X86/memset-nonzero.ll b/test/CodeGen/X86/memset-nonzero.ll index 769fe87880b0..13258fd81de5 100644 --- a/test/CodeGen/X86/memset-nonzero.ll +++ b/test/CodeGen/X86/memset-nonzero.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=x86_64-unknown-unknown < %s -mattr=sse | FileCheck %s --check-prefix=SSE ; RUN: llc -mtriple=x86_64-unknown-unknown < %s -mattr=sse2 | FileCheck %s --check-prefix=SSE ; RUN: llc -mtriple=x86_64-unknown-unknown < %s -mattr=sse2,-slow-unaligned-mem-16 | FileCheck %s --check-prefix=SSE2FAST @@ -26,7 +26,6 @@ define void @memset_16_nonzero_bytes(i8* %x) { ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42] ; AVX-NEXT: vmovups %xmm0, (%rdi) ; AVX-NEXT: retq -; %call = tail call i8* @__memset_chk(i8* %x, i32 42, i64 16, i64 -1) ret void } @@ -54,7 +53,6 @@ define void @memset_32_nonzero_bytes(i8* %x) { ; AVX-NEXT: vmovups %ymm0, (%rdi) ; AVX-NEXT: vzeroupper ; AVX-NEXT: retq -; %call = tail call i8* @__memset_chk(i8* %x, i32 42, i64 32, i64 -1) ret void } @@ -89,7 +87,6 @@ define void @memset_64_nonzero_bytes(i8* %x) { ; AVX-NEXT: vmovups %ymm0, (%rdi) ; AVX-NEXT: vzeroupper ; AVX-NEXT: retq -; %call = tail call i8* @__memset_chk(i8* %x, i32 42, i64 64, i64 -1) ret void } @@ -138,7 +135,6 @@ define void @memset_128_nonzero_bytes(i8* %x) { ; AVX-NEXT: vmovups %ymm0, (%rdi) ; AVX-NEXT: vzeroupper ; AVX-NEXT: retq -; %call = tail call i8* @__memset_chk(i8* %x, i32 42, i64 128, i64 -1) ret void } @@ -189,7 +185,6 @@ define void @memset_256_nonzero_bytes(i8* %x) { ; AVX-NEXT: vmovups %ymm0, (%rdi) ; AVX-NEXT: vzeroupper ; AVX-NEXT: retq -; %call = tail call i8* @__memset_chk(i8* %x, i32 42, i64 256, i64 -1) ret void } @@ -231,7 +226,6 @@ define void @memset_16_nonconst_bytes(i8* %x, i8 %c) { ; AVX2-NEXT: vpbroadcastb %xmm0, %xmm0 ; AVX2-NEXT: vmovdqu %xmm0, (%rdi) ; AVX2-NEXT: retq -; tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 16, i32 1, i1 false) ret void } @@ -275,7 +269,6 @@ define void @memset_32_nonconst_bytes(i8* %x, i8 %c) { ; AVX2-NEXT: vmovdqu %ymm0, (%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 32, i32 1, i1 false) ret void } @@ -327,7 +320,6 @@ define void @memset_64_nonconst_bytes(i8* %x, i8 %c) { ; AVX2-NEXT: vmovdqu %ymm0, (%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 64, i32 1, i1 false) ret void } @@ -395,7 +387,6 @@ define void @memset_128_nonconst_bytes(i8* %x, i8 %c) { ; AVX2-NEXT: vmovdqu %ymm0, (%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 128, i32 1, i1 false) ret void } @@ -461,7 +452,6 @@ define void @memset_256_nonconst_bytes(i8* %x, i8 %c) { ; AVX2-NEXT: vmovdqu %ymm0, (%rdi) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq -; tail call void @llvm.memset.p0i8.i64(i8* %x, i8 %c, i64 256, i32 1, i1 false) ret void } diff --git a/test/CodeGen/X86/memset64-on-x86-32.ll b/test/CodeGen/X86/memset64-on-x86-32.ll index 861cb88b0f57..a7a3c61b1392 100644 --- a/test/CodeGen/X86/memset64-on-x86-32.ll +++ b/test/CodeGen/X86/memset64-on-x86-32.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=sse4.2 | FileCheck %s --check-prefix=FAST ; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=ssse3 | FileCheck %s --check-prefix=SLOW_32 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=ssse3 | FileCheck %s --check-prefix=SLOW_64 @@ -51,7 +51,6 @@ define void @bork() nounwind { ; SLOW_64-NEXT: movq $0, 8 ; SLOW_64-NEXT: movq $0, 0 ; SLOW_64-NEXT: retq -; call void @llvm.memset.p0i8.i64(i8* null, i8 0, i64 80, i32 4, i1 false) ret void } diff --git a/test/CodeGen/X86/negate-i1.ll b/test/CodeGen/X86/negate-i1.ll index f1678a1b22ff..13f831fd37b7 100644 --- a/test/CodeGen/X86/negate-i1.ll +++ b/test/CodeGen/X86/negate-i1.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s --check-prefix=X32 @@ -16,7 +16,6 @@ define i8 @select_i8_neg1_or_0(i1 %a) { ; X32-NEXT: andb $1, %al ; X32-NEXT: negb %al ; X32-NEXT: retl -; %b = sext i1 %a to i8 ret i8 %b } @@ -33,7 +32,6 @@ define i8 @select_i8_neg1_or_0_zeroext(i1 zeroext %a) { ; X32-NEXT: movb {{[0-9]+}}(%esp), %al ; X32-NEXT: negb %al ; X32-NEXT: retl -; %b = sext i1 %a to i8 ret i8 %b } @@ -53,7 +51,6 @@ define i16 @select_i16_neg1_or_0(i1 %a) { ; X32-NEXT: negl %eax ; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; X32-NEXT: retl -; %b = sext i1 %a to i16 ret i16 %b } @@ -72,7 +69,6 @@ define i16 @select_i16_neg1_or_0_zeroext(i1 zeroext %a) { ; X32-NEXT: negl %eax ; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; X32-NEXT: retl -; %b = sext i1 %a to i16 ret i16 %b } @@ -91,7 +87,6 @@ define i32 @select_i32_neg1_or_0(i1 %a) { ; X32-NEXT: andl $1, %eax ; X32-NEXT: negl %eax ; X32-NEXT: retl -; %b = sext i1 %a to i32 ret i32 %b } @@ -108,7 +103,6 @@ define i32 @select_i32_neg1_or_0_zeroext(i1 zeroext %a) { ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X32-NEXT: negl %eax ; X32-NEXT: retl -; %b = sext i1 %a to i32 ret i32 %b } @@ -129,7 +123,6 @@ define i64 @select_i64_neg1_or_0(i1 %a) { ; X32-NEXT: negl %eax ; X32-NEXT: movl %eax, %edx ; X32-NEXT: retl -; %b = sext i1 %a to i64 ret i64 %b } @@ -147,7 +140,6 @@ define i64 @select_i64_neg1_or_0_zeroext(i1 zeroext %a) { ; X32-NEXT: negl %eax ; X32-NEXT: movl %eax, %edx ; X32-NEXT: retl -; %b = sext i1 %a to i64 ret i64 %b } diff --git a/test/CodeGen/X86/negate-shift.ll b/test/CodeGen/X86/negate-shift.ll index 54ffc8e71e07..cbe2f9456fa1 100644 --- a/test/CodeGen/X86/negate-shift.ll +++ b/test/CodeGen/X86/negate-shift.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64 define i32 @neg_lshr_signbit(i32 %x) { @@ -7,7 +7,6 @@ define i32 @neg_lshr_signbit(i32 %x) { ; X64-NEXT: sarl $31, %edi ; X64-NEXT: movl %edi, %eax ; X64-NEXT: retq -; %sh = lshr i32 %x, 31 %neg = sub i32 0, %sh ret i32 %neg @@ -19,7 +18,6 @@ define i64 @neg_ashr_signbit(i64 %x) { ; X64-NEXT: shrq $63, %rdi ; X64-NEXT: movq %rdi, %rax ; X64-NEXT: retq -; %sh = ashr i64 %x, 63 %neg = sub i64 0, %sh ret i64 %neg @@ -30,7 +28,6 @@ define <4 x i32> @neg_ashr_signbit_vec(<4 x i32> %x) { ; X64: # BB#0: ; X64-NEXT: psrld $31, %xmm0 ; X64-NEXT: retq -; %sh = ashr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31> %neg = sub <4 x i32> zeroinitializer, %sh ret <4 x i32> %neg @@ -41,7 +38,6 @@ define <8 x i16> @neg_lshr_signbit_vec(<8 x i16> %x) { ; X64: # BB#0: ; X64-NEXT: psraw $15, %xmm0 ; X64-NEXT: retq -; %sh = lshr <8 x i16> %x, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> %neg = sub <8 x i16> zeroinitializer, %sh ret <8 x i16> %neg diff --git a/test/CodeGen/X86/negate.ll b/test/CodeGen/X86/negate.ll index 6f07378e0e46..5bdb11479afc 100644 --- a/test/CodeGen/X86/negate.ll +++ b/test/CodeGen/X86/negate.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s define i32 @negate_nuw(i32 %x) { @@ -6,7 +6,6 @@ define i32 @negate_nuw(i32 %x) { ; CHECK: # BB#0: ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: retq -; %neg = sub nuw i32 0, %x ret i32 %neg } @@ -16,7 +15,6 @@ define <4 x i32> @negate_nuw_vec(<4 x i32> %x) { ; CHECK: # BB#0: ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: retq -; %neg = sub nuw <4 x i32> zeroinitializer, %x ret <4 x i32> %neg } @@ -26,7 +24,6 @@ define i8 @negate_zero_or_minsigned_nsw(i8 %x) { ; CHECK: # BB#0: ; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: retq -; %signbit = and i8 %x, 128 %neg = sub nsw i8 0, %signbit ret i8 %neg @@ -37,7 +34,6 @@ define <4 x i32> @negate_zero_or_minsigned_nsw_vec(<4 x i32> %x) { ; CHECK: # BB#0: ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: retq -; %signbit = shl <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31> %neg = sub nsw <4 x i32> zeroinitializer, %signbit ret <4 x i32> %neg @@ -49,7 +45,6 @@ define i8 @negate_zero_or_minsigned(i8 %x) { ; CHECK-NEXT: shlb $7, %dil ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq -; %signbit = shl i8 %x, 7 %neg = sub i8 0, %signbit ret i8 %neg @@ -60,7 +55,6 @@ define <4 x i32> @negate_zero_or_minsigned_vec(<4 x i32> %x) { ; CHECK: # BB#0: ; CHECK-NEXT: andps {{.*}}(%rip), %xmm0 ; CHECK-NEXT: retq -; %signbit = and <4 x i32> %x, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648> %neg = sub <4 x i32> zeroinitializer, %signbit ret <4 x i32> %neg diff --git a/test/CodeGen/X86/negative-sin.ll b/test/CodeGen/X86/negative-sin.ll index bc38021b5620..94369e3e8d0f 100644 --- a/test/CodeGen/X86/negative-sin.ll +++ b/test/CodeGen/X86/negative-sin.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s declare double @sin(double %f) @@ -16,7 +16,6 @@ define double @strict(double %e) nounwind { ; CHECK-NEXT: vsubsd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq -; %f = fsub double 0.0, %e %g = call double @sin(double %f) readonly %h = fsub double 0.0, %g @@ -29,8 +28,7 @@ define double @strict(double %e) nounwind { define double @fast(double %e) nounwind { ; CHECK-LABEL: fast: ; CHECK: # BB#0: -; CHECK-NEXT: jmp sin -; +; CHECK-NEXT: jmp sin # TAILCALL %f = fsub fast double 0.0, %e %g = call double @sin(double %f) readonly %h = fsub fast double 0.0, %g @@ -42,8 +40,7 @@ define double @fast(double %e) nounwind { define double @nsz(double %e) nounwind { ; CHECK-LABEL: nsz: ; CHECK: # BB#0: -; CHECK-NEXT: jmp sin -; +; CHECK-NEXT: jmp sin # TAILCALL %f = fsub nsz double 0.0, %e %g = call double @sin(double %f) readonly %h = fsub nsz double 0.0, %g @@ -62,7 +59,6 @@ define double @semi_strict1(double %e) nounwind { ; CHECK-NEXT: vxorpd {{.*}}(%rip), %xmm0, %xmm0 ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq -; %f = fsub double 0.0, %e %g = call double @sin(double %f) readonly %h = fsub nsz double 0.0, %g @@ -80,7 +76,6 @@ define double @semi_strict2(double %e) nounwind { ; CHECK-NEXT: vaddsd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq -; %f = fsub nsz double 0.0, %e %g = call double @sin(double %f) readonly %h = fsub double 0.0, %g @@ -93,8 +88,7 @@ define double @semi_strict2(double %e) nounwind { define double @fn_attr(double %e) nounwind #0 { ; CHECK-LABEL: fn_attr: ; CHECK: # BB#0: -; CHECK-NEXT: jmp sin -; +; CHECK-NEXT: jmp sin # TAILCALL %f = fsub double 0.0, %e %g = call double @sin(double %f) readonly %h = fsub double 0.0, %g diff --git a/test/CodeGen/X86/no-sse2-avg.ll b/test/CodeGen/X86/no-sse2-avg.ll index 0ed0a7f74cb3..e4b97c17047c 100644 --- a/test/CodeGen/X86/no-sse2-avg.ll +++ b/test/CodeGen/X86/no-sse2-avg.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; REQUIRES: asserts ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s @@ -23,7 +23,6 @@ define <16 x i8> @PR27973() { ; CHECK-NEXT: movb $0, (%rdi) ; CHECK-NEXT: movq %rdi, %rax ; CHECK-NEXT: retq -; %t0 = zext <16 x i8> zeroinitializer to <16 x i32> %t1 = add nuw nsw <16 x i32> %t0, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> %t2 = lshr <16 x i32> %t1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> diff --git a/test/CodeGen/X86/not-and-simplify.ll b/test/CodeGen/X86/not-and-simplify.ll index 83b2be83d552..87aa10a6e296 100644 --- a/test/CodeGen/X86/not-and-simplify.ll +++ b/test/CodeGen/X86/not-and-simplify.ll @@ -1,5 +1,4 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-bmi | FileCheck %s --check-prefix=ALL --check-prefix=NO_BMI ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi | FileCheck %s --check-prefix=ALL --check-prefix=BMI diff --git a/test/CodeGen/X86/pr13577.ll b/test/CodeGen/X86/pr13577.ll index 1b1622513ea6..665df2c183bf 100644 --- a/test/CodeGen/X86/pr13577.ll +++ b/test/CodeGen/X86/pr13577.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-darwin | FileCheck %s ; CHECK-LABEL: LCPI0_0: @@ -12,12 +12,11 @@ define x86_fp80 @foo(x86_fp80 %a) { ; CHECK-NEXT: fldt {{[0-9]+}}(%rsp) ; CHECK-NEXT: fstpt -{{[0-9]+}}(%rsp) ; CHECK-NEXT: testb $-128, -{{[0-9]+}}(%rsp) -; CHECK-NEXT: flds LCPI0_0(%rip) -; CHECK-NEXT: flds LCPI0_1(%rip) +; CHECK-NEXT: flds {{.*}}(%rip) +; CHECK-NEXT: flds {{.*}}(%rip) ; CHECK-NEXT: fcmovne %st(1), %st(0) ; CHECK-NEXT: fstp %st(1) ; CHECK-NEXT: retq -; %1 = tail call x86_fp80 @copysignl(x86_fp80 0xK7FFF8000000000000000, x86_fp80 %a) nounwind readnone ret x86_fp80 %1 } @@ -34,7 +33,6 @@ define float @pr26070() { ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0] ; CHECK-NEXT: orps {{.*}}(%rip), %xmm0 ; CHECK-NEXT: retq -; %c = call float @copysignf(float 1.0, float undef) readnone ret float %c } diff --git a/test/CodeGen/X86/pr18014.ll b/test/CodeGen/X86/pr18014.ll index bb3b9c23f1e3..cba065002d57 100644 --- a/test/CodeGen/X86/pr18014.ll +++ b/test/CodeGen/X86/pr18014.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.1 | FileCheck %s ; Ensure PSRAD is generated as the condition is consumed by both PADD and @@ -14,7 +14,6 @@ define <4 x i32> @foo(<4 x i32>* %p, <4 x i1> %cond, <4 x i32> %v1, <4 x i32> %v ; CHECK-NEXT: movaps %xmm2, (%rdi) ; CHECK-NEXT: movdqa %xmm1, %xmm0 ; CHECK-NEXT: retq -; %sext_cond = sext <4 x i1> %cond to <4 x i32> %t1 = add <4 x i32> %v1, %sext_cond %t2 = select <4 x i1> %cond, <4 x i32> %v1, <4 x i32> %v2 diff --git a/test/CodeGen/X86/pr32368.ll b/test/CodeGen/X86/pr32368.ll new file mode 100644 index 000000000000..b0f0b123cca1 --- /dev/null +++ b/test/CodeGen/X86/pr32368.ll @@ -0,0 +1,153 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=CHECK --check-prefix=SSE +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=CHECK --check-prefix=AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512 + +define <4 x float> @PR32368_128(<4 x float>) { +; SSE-LABEL: PR32368_128: +; SSE: # BB#0: +; SSE-NEXT: andps {{.*}}(%rip), %xmm0 +; SSE-NEXT: addps %xmm0, %xmm0 +; SSE-NEXT: andps {{.*}}(%rip), %xmm0 +; SSE-NEXT: retq +; +; AVX1-LABEL: PR32368_128: +; AVX1: # BB#0: +; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 +; AVX1-NEXT: vaddps %xmm0, %xmm0, %xmm0 +; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: PR32368_128: +; AVX2: # BB#0: +; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %xmm1 +; AVX2-NEXT: vandps %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vaddps %xmm0, %xmm0, %xmm0 +; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %xmm1 +; AVX2-NEXT: vandps %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: PR32368_128: +; AVX512: # BB#0: +; AVX512-NEXT: vbroadcastss {{.*}}(%rip), %xmm1 +; AVX512-NEXT: vandps %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: vaddps %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vbroadcastss {{.*}}(%rip), %xmm1 +; AVX512-NEXT: vandps %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: retq + %2 = bitcast <4 x float> %0 to <4 x i32> + %3 = and <4 x i32> %2, <i32 -292, i32 -292, i32 -292, i32 -292> + %4 = bitcast <4 x i32> %3 to <4 x float> + %5 = fmul <4 x float> %4, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00> + %6 = bitcast <4 x float> %5 to <4 x i32> + %7 = and <4 x i32> %6, <i32 291, i32 291, i32 291, i32 291> + %8 = bitcast <4 x i32> %7 to <4 x float> + ret <4 x float> %8 +} + +define <8 x float> @PR32368_256(<8 x float>) { +; SSE-LABEL: PR32368_256: +; SSE: # BB#0: +; SSE-NEXT: movaps {{.*#+}} xmm2 = [4294967004,4294967004,4294967004,4294967004] +; SSE-NEXT: andps %xmm2, %xmm0 +; SSE-NEXT: andps %xmm2, %xmm1 +; SSE-NEXT: addps %xmm1, %xmm1 +; SSE-NEXT: addps %xmm0, %xmm0 +; SSE-NEXT: movaps {{.*#+}} xmm2 = [291,291,291,291] +; SSE-NEXT: andps %xmm2, %xmm0 +; SSE-NEXT: andps %xmm2, %xmm1 +; SSE-NEXT: retq +; +; AVX1-LABEL: PR32368_256: +; AVX1: # BB#0: +; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 +; AVX1-NEXT: vaddps %ymm0, %ymm0, %ymm0 +; AVX1-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: PR32368_256: +; AVX2: # BB#0: +; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %ymm1 +; AVX2-NEXT: vandps %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: vaddps %ymm0, %ymm0, %ymm0 +; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %ymm1 +; AVX2-NEXT: vandps %ymm1, %ymm0, %ymm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: PR32368_256: +; AVX512: # BB#0: +; AVX512-NEXT: vbroadcastss {{.*}}(%rip), %ymm1 +; AVX512-NEXT: vandps %ymm1, %ymm0, %ymm0 +; AVX512-NEXT: vaddps %ymm0, %ymm0, %ymm0 +; AVX512-NEXT: vbroadcastss {{.*}}(%rip), %ymm1 +; AVX512-NEXT: vandps %ymm1, %ymm0, %ymm0 +; AVX512-NEXT: retq + %2 = bitcast <8 x float> %0 to <8 x i32> + %3 = and <8 x i32> %2, <i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292> + %4 = bitcast <8 x i32> %3 to <8 x float> + %5 = fmul <8 x float> %4, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00> + %6 = bitcast <8 x float> %5 to <8 x i32> + %7 = and <8 x i32> %6, <i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291> + %8 = bitcast <8 x i32> %7 to <8 x float> + ret <8 x float> %8 +} + +define <16 x float> @PR32368_512(<16 x float>) { +; SSE-LABEL: PR32368_512: +; SSE: # BB#0: +; SSE-NEXT: movaps {{.*#+}} xmm4 = [4294967004,4294967004,4294967004,4294967004] +; SSE-NEXT: andps %xmm4, %xmm0 +; SSE-NEXT: andps %xmm4, %xmm1 +; SSE-NEXT: andps %xmm4, %xmm2 +; SSE-NEXT: andps %xmm4, %xmm3 +; SSE-NEXT: addps %xmm3, %xmm3 +; SSE-NEXT: addps %xmm2, %xmm2 +; SSE-NEXT: addps %xmm1, %xmm1 +; SSE-NEXT: addps %xmm0, %xmm0 +; SSE-NEXT: movaps {{.*#+}} xmm4 = [291,291,291,291] +; SSE-NEXT: andps %xmm4, %xmm0 +; SSE-NEXT: andps %xmm4, %xmm1 +; SSE-NEXT: andps %xmm4, %xmm2 +; SSE-NEXT: andps %xmm4, %xmm3 +; SSE-NEXT: retq +; +; AVX1-LABEL: PR32368_512: +; AVX1: # BB#0: +; AVX1-NEXT: vmovaps {{.*#+}} ymm2 = [4294967004,4294967004,4294967004,4294967004,4294967004,4294967004,4294967004,4294967004] +; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0 +; AVX1-NEXT: vandps %ymm2, %ymm1, %ymm1 +; AVX1-NEXT: vaddps %ymm1, %ymm1, %ymm1 +; AVX1-NEXT: vaddps %ymm0, %ymm0, %ymm0 +; AVX1-NEXT: vmovaps {{.*#+}} ymm2 = [291,291,291,291,291,291,291,291] +; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0 +; AVX1-NEXT: vandps %ymm2, %ymm1, %ymm1 +; AVX1-NEXT: retq +; +; AVX2-LABEL: PR32368_512: +; AVX2: # BB#0: +; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %ymm2 +; AVX2-NEXT: vandps %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vandps %ymm2, %ymm1, %ymm1 +; AVX2-NEXT: vaddps %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vaddps %ymm0, %ymm0, %ymm0 +; AVX2-NEXT: vbroadcastss {{.*}}(%rip), %ymm2 +; AVX2-NEXT: vandps %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vandps %ymm2, %ymm1, %ymm1 +; AVX2-NEXT: retq +; +; AVX512-LABEL: PR32368_512: +; AVX512: # BB#0: +; AVX512-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm0, %zmm0 +; AVX512-NEXT: vaddps %zmm0, %zmm0, %zmm0 +; AVX512-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm0, %zmm0 +; AVX512-NEXT: retq + %2 = bitcast <16 x float> %0 to <16 x i32> + %3 = and <16 x i32> %2, <i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292, i32 -292> + %4 = bitcast <16 x i32> %3 to <16 x float> + %5 = fmul <16 x float> %4, <float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00> + %6 = bitcast <16 x float> %5 to <16 x i32> + %7 = and <16 x i32> %6, <i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291, i32 291> + %8 = bitcast <16 x i32> %7 to <16 x float> + ret <16 x float> %8 +} diff --git a/test/CodeGen/X86/rem.ll b/test/CodeGen/X86/rem.ll index cc591e5ac00b..7b138f02eb4a 100644 --- a/test/CodeGen/X86/rem.ll +++ b/test/CodeGen/X86/rem.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s define i32 @test1(i32 %X) { @@ -19,7 +19,6 @@ define i32 @test1(i32 %X) { ; CHECK-NEXT: subl %eax, %ecx ; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: retl -; %tmp1 = srem i32 %X, 255 ret i32 %tmp1 } @@ -35,7 +34,6 @@ define i32 @test2(i32 %X) { ; CHECK-NEXT: andl $-256, %ecx ; CHECK-NEXT: subl %ecx, %eax ; CHECK-NEXT: retl -; %tmp1 = srem i32 %X, 256 ret i32 %tmp1 } @@ -54,7 +52,6 @@ define i32 @test3(i32 %X) { ; CHECK-NEXT: subl %eax, %ecx ; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: retl -; %tmp1 = urem i32 %X, 255 ret i32 %tmp1 } @@ -64,7 +61,6 @@ define i32 @test4(i32 %X) { ; CHECK: # BB#0: ; CHECK-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: retl -; %tmp1 = urem i32 %X, 256 ret i32 %tmp1 } @@ -77,8 +73,8 @@ define i32 @test5(i32 %X) nounwind readnone { ; CHECK-NEXT: idivl {{[0-9]+}}(%esp) ; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: retl -; entry: %0 = srem i32 41, %X ret i32 %0 } + diff --git a/test/CodeGen/X86/sar_fold64.ll b/test/CodeGen/X86/sar_fold64.ll index 213ca95fc78d..66ad8c3f40fa 100644 --- a/test/CodeGen/X86/sar_fold64.ll +++ b/test/CodeGen/X86/sar_fold64.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s define i32 @shl48sar47(i64 %a) #0 { @@ -8,7 +8,6 @@ define i32 @shl48sar47(i64 %a) #0 { ; CHECK-NEXT: addl %eax, %eax ; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> ; CHECK-NEXT: retq -; %1 = shl i64 %a, 48 %2 = ashr exact i64 %1, 47 %3 = trunc i64 %2 to i32 @@ -22,7 +21,6 @@ define i32 @shl48sar49(i64 %a) #0 { ; CHECK-NEXT: shrq %rax ; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> ; CHECK-NEXT: retq -; %1 = shl i64 %a, 48 %2 = ashr exact i64 %1, 49 %3 = trunc i64 %2 to i32 @@ -36,7 +34,6 @@ define i32 @shl56sar55(i64 %a) #0 { ; CHECK-NEXT: addl %eax, %eax ; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> ; CHECK-NEXT: retq -; %1 = shl i64 %a, 56 %2 = ashr exact i64 %1, 55 %3 = trunc i64 %2 to i32 @@ -50,7 +47,6 @@ define i32 @shl56sar57(i64 %a) #0 { ; CHECK-NEXT: shrq %rax ; CHECK-NEXT: # kill: %EAX<def> %EAX<kill> %RAX<kill> ; CHECK-NEXT: retq -; %1 = shl i64 %a, 56 %2 = ashr exact i64 %1, 57 %3 = trunc i64 %2 to i32 @@ -64,7 +60,6 @@ define i8 @all_sign_bit_ashr(i8 %x) { ; CHECK-NEXT: negb %dil ; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq -; %and = and i8 %x, 1 %neg = sub i8 0, %and %sar = ashr i8 %neg, 6 @@ -79,7 +74,6 @@ define <4 x i32> @all_sign_bit_ashr_vec(<4 x i32> %x) { ; CHECK-NEXT: psubd %xmm0, %xmm1 ; CHECK-NEXT: movdqa %xmm1, %xmm0 ; CHECK-NEXT: retq -; %and = and <4 x i32> %x, <i32 1, i32 1, i32 1 , i32 1> %neg = sub <4 x i32> zeroinitializer, %and %sar = ashr <4 x i32> %neg, <i32 1, i32 31, i32 5, i32 0> diff --git a/test/CodeGen/X86/select-with-and-or.ll b/test/CodeGen/X86/select-with-and-or.ll index f49da8576d18..45e4384d0fa1 100644 --- a/test/CodeGen/X86/select-with-and-or.ll +++ b/test/CodeGen/X86/select-with-and-or.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s define <4 x i32> @test1(<4 x float> %a, <4 x float> %b, <4 x i32> %c) { @@ -7,7 +7,6 @@ define <4 x i32> @test1(<4 x float> %a, <4 x float> %b, <4 x i32> %c) { ; CHECK-NEXT: vcmpnleps %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vandps %xmm2, %xmm0, %xmm0 ; CHECK-NEXT: retq -; %f = fcmp ult <4 x float> %a, %b %r = select <4 x i1> %f, <4 x i32> %c, <4 x i32> zeroinitializer ret <4 x i32> %r @@ -19,7 +18,6 @@ define <4 x i32> @test2(<4 x float> %a, <4 x float> %b, <4 x i32> %c) { ; CHECK-NEXT: vcmpnleps %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vorps %xmm2, %xmm0, %xmm0 ; CHECK-NEXT: retq -; %f = fcmp ult <4 x float> %a, %b %r = select <4 x i1> %f, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c ret <4 x i32> %r @@ -31,7 +29,6 @@ define <4 x i32> @test3(<4 x float> %a, <4 x float> %b, <4 x i32> %c) { ; CHECK-NEXT: vcmpleps %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vandps %xmm2, %xmm0, %xmm0 ; CHECK-NEXT: retq -; %f = fcmp ult <4 x float> %a, %b %r = select <4 x i1> %f, <4 x i32> zeroinitializer, <4 x i32> %c ret <4 x i32> %r @@ -43,7 +40,6 @@ define <4 x i32> @test4(<4 x float> %a, <4 x float> %b, <4 x i32> %c) { ; CHECK-NEXT: vcmpleps %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vorps %xmm2, %xmm0, %xmm0 ; CHECK-NEXT: retq -; %f = fcmp ult <4 x float> %a, %b %r = select <4 x i1> %f, <4 x i32> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> ret <4 x i32> %r @@ -54,7 +50,6 @@ define <4 x i32> @test5(<4 x float> %a, <4 x float> %b, <4 x i32> %c) { ; CHECK: # BB#0: ; CHECK-NEXT: vcmpnleps %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: retq -; %f = fcmp ult <4 x float> %a, %b %r = sext <4 x i1> %f to <4 x i32> ret <4 x i32> %r @@ -65,7 +60,6 @@ define <4 x i32> @test6(<4 x float> %a, <4 x float> %b, <4 x i32> %c) { ; CHECK: # BB#0: ; CHECK-NEXT: vcmpleps %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: retq -; %not.f = fcmp oge <4 x float> %a, %b %r = sext <4 x i1> %not.f to <4 x i32> ret <4 x i32> %r @@ -77,7 +71,6 @@ define <4 x i32> @test7(<4 x float> %a, <4 x float> %b, <4 x i32>* %p) { ; CHECK-NEXT: vcmpnleps %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vandps (%rdi), %xmm0, %xmm0 ; CHECK-NEXT: retq -; %f = fcmp ult <4 x float> %a, %b %l = load <4 x i32>, <4 x i32>* %p, align 16 %r = select <4 x i1> %f, <4 x i32> %l, <4 x i32> zeroinitializer @@ -92,7 +85,6 @@ define <2 x double> @test1f(<2 x double> %a, <2 x double> %b, <2 x double> %c) { ; CHECK-NEXT: vcmpltpd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vandpd %xmm2, %xmm0, %xmm0 ; CHECK-NEXT: retq -; %f = fcmp ogt <2 x double> %a, %b %r = select <2 x i1> %f, <2 x double> %c, <2 x double> zeroinitializer ret <2 x double> %r @@ -104,7 +96,6 @@ define <2 x double> @test2f(<2 x double> %a, <2 x double> %b, <2 x double> %c) { ; CHECK-NEXT: vcmplepd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vorpd %xmm2, %xmm0, %xmm0 ; CHECK-NEXT: retq -; %f = fcmp oge <2 x double> %a, %b %r = select <2 x i1> %f, <2 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff>, <2 x double> %c ret <2 x double> %r @@ -116,7 +107,6 @@ define <2 x double> @test3f(<2 x double> %a, <2 x double> %b, <2 x double> %c) { ; CHECK-NEXT: vcmpnltpd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vandpd %xmm2, %xmm0, %xmm0 ; CHECK-NEXT: retq -; %f = fcmp olt <2 x double> %a, %b %r = select <2 x i1> %f, <2 x double> zeroinitializer, <2 x double> %c ret <2 x double> %r @@ -128,7 +118,6 @@ define <2 x double> @test4f(<2 x double> %a, <2 x double> %b, <2 x double> %c) { ; CHECK-NEXT: vcmpnlepd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vorpd %xmm2, %xmm0, %xmm0 ; CHECK-NEXT: retq -; %f = fcmp ole <2 x double> %a, %b %r = select <2 x i1> %f, <2 x double> %c, <2 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff> ret <2 x double> %r @@ -139,7 +128,6 @@ define <2 x double> @test5f(<2 x double> %a, <2 x double> %b, <2 x double> %c) { ; CHECK: # BB#0: ; CHECK-NEXT: vcmpnlepd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: retq -; %f = fcmp ugt <2 x double> %a, %b %r = select <2 x i1> %f, <2 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff>, <2 x double> zeroinitializer ret <2 x double> %r @@ -150,7 +138,6 @@ define <2 x double> @test6f(<2 x double> %a, <2 x double> %b, <2 x double> %c) { ; CHECK: # BB#0: ; CHECK-NEXT: vcmpltpd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: retq -; %f = fcmp ule <2 x double> %a, %b %r = select <2 x i1> %f, <2 x double> zeroinitializer, <2 x double> <double 0xffffffffffffffff, double 0xffffffffffffffff> ret <2 x double> %r @@ -162,7 +149,6 @@ define <2 x double> @test7f(<2 x double> %a, <2 x double> %b, <2 x double>* %p) ; CHECK-NEXT: vcmpeqpd %xmm1, %xmm0, %xmm0 ; CHECK-NEXT: vandpd (%rdi), %xmm0, %xmm0 ; CHECK-NEXT: retq -; %f = fcmp oeq <2 x double> %a, %b %l = load <2 x double>, <2 x double>* %p, align 16 %r = select <2 x i1> %f, <2 x double> %l, <2 x double> zeroinitializer diff --git a/test/CodeGen/X86/sext-setcc-self.ll b/test/CodeGen/X86/sext-setcc-self.ll index e739d21e64e0..9cbd3d85b381 100644 --- a/test/CodeGen/X86/sext-setcc-self.ll +++ b/test/CodeGen/X86/sext-setcc-self.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s define <4 x i32> @test_ueq(<4 x float> %in) { @@ -6,7 +6,6 @@ define <4 x i32> @test_ueq(<4 x float> %in) { ; CHECK: # BB#0: ; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 ; CHECK-NEXT: retq -; %t0 = fcmp ueq <4 x float> %in, %in %t1 = sext <4 x i1> %t0 to <4 x i32> ret <4 x i32> %t1 @@ -17,7 +16,6 @@ define <4 x i32> @test_uge(<4 x float> %in) { ; CHECK: # BB#0: ; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 ; CHECK-NEXT: retq -; %t0 = fcmp uge <4 x float> %in, %in %t1 = sext <4 x i1> %t0 to <4 x i32> ret <4 x i32> %t1 @@ -28,7 +26,6 @@ define <4 x i32> @test_ule(<4 x float> %in) { ; CHECK: # BB#0: ; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 ; CHECK-NEXT: retq -; %t0 = fcmp ule <4 x float> %in, %in %t1 = sext <4 x i1> %t0 to <4 x i32> ret <4 x i32> %t1 @@ -39,7 +36,6 @@ define <4 x i32> @test_one(<4 x float> %in) { ; CHECK: # BB#0: ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: retq -; %t0 = fcmp one <4 x float> %in, %in %t1 = sext <4 x i1> %t0 to <4 x i32> ret <4 x i32> %t1 @@ -50,7 +46,6 @@ define <4 x i32> @test_ogt(<4 x float> %in) { ; CHECK: # BB#0: ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: retq -; %t0 = fcmp ogt <4 x float> %in, %in %t1 = sext <4 x i1> %t0 to <4 x i32> ret <4 x i32> %t1 @@ -61,7 +56,6 @@ define <4 x i32> @test_olt(<4 x float> %in) { ; CHECK: # BB#0: ; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: retq -; %t0 = fcmp olt <4 x float> %in, %in %t1 = sext <4 x i1> %t0 to <4 x i32> ret <4 x i32> %t1 diff --git a/test/CodeGen/X86/shift-pcmp.ll b/test/CodeGen/X86/shift-pcmp.ll index adfd2f143d17..f509da2674bc 100644 --- a/test/CodeGen/X86/shift-pcmp.ll +++ b/test/CodeGen/X86/shift-pcmp.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -o - -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE ; RUN: llc < %s -o - -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX @@ -14,7 +14,6 @@ define <8 x i16> @foo(<8 x i16> %a, <8 x i16> %b) { ; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq -; %icmp = icmp eq <8 x i16> %a, %b %zext = zext <8 x i1> %icmp to <8 x i16> %shl = shl nuw nsw <8 x i16> %zext, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5> @@ -34,7 +33,6 @@ define <8 x i16> @bar(<8 x i16> %a, <8 x i16> %b) { ; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq -; %icmp = icmp eq <8 x i16> %a, %b %zext = zext <8 x i1> %icmp to <8 x i16> %shl = shl nuw nsw <8 x i16> %zext, <i16 5, i16 undef, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5> diff --git a/test/CodeGen/X86/sincos-opt.ll b/test/CodeGen/X86/sincos-opt.ll index f0dff3b806c5..e2fd63eab30f 100644 --- a/test/CodeGen/X86/sincos-opt.ll +++ b/test/CodeGen/X86/sincos-opt.ll @@ -1,10 +1,12 @@ ; RUN: llc < %s -mtriple=x86_64-apple-macosx10.9.0 -mcpu=core2 | FileCheck %s --check-prefix=OSX_SINCOS ; RUN: llc < %s -mtriple=x86_64-apple-macosx10.8.0 -mcpu=core2 | FileCheck %s --check-prefix=OSX_NOOPT -; RUN: llc < %s -mtriple=x86_64-pc-linux-gnu -mcpu=core2 | FileCheck %s --check-prefix=GNU_NOOPT -; RUN: llc < %s -mtriple=x86_64-pc-linux-gnu -mcpu=core2 -enable-unsafe-fp-math | FileCheck %s --check-prefix=GNU_SINCOS -; RUN: llc < %s -mtriple=x86_64-pc-linux-gnux32 -mcpu=core2 -enable-unsafe-fp-math | FileCheck %s --check-prefix=GNUX32_SINCOS +; RUN: llc < %s -mtriple=x86_64-pc-linux-gnu -mcpu=core2 | FileCheck %s --check-prefix=GNU_SINCOS +; RUN: llc < %s -mtriple=x86_64-pc-linux-gnu -mcpu=core2 -enable-unsafe-fp-math | FileCheck %s --check-prefix=GNU_SINCOS_FASTMATH +; RUN: llc < %s -mtriple=x86_64-pc-linux-gnux32 -mcpu=core2 -enable-unsafe-fp-math | FileCheck %s --check-prefix=GNU_SINCOS_FASTMATH -; Combine sin / cos into a single call. +; Combine sin / cos into a single call unless they may write errno (as +; captured by readnone attrbiute, controlled by clang -fmath-errno +; setting). ; rdar://13087969 ; rdar://13599493 @@ -15,25 +17,44 @@ entry: ; GNU_SINCOS: movss 4(%rsp), %xmm0 ; GNU_SINCOS: addss (%rsp), %xmm0 -; GNUX32_SINCOS-LABEL: test1: -; GNUX32_SINCOS: callq sincosf -; GNUX32_SINCOS: movss 4(%esp), %xmm0 -; GNUX32_SINCOS: addss (%esp), %xmm0 - -; GNU_NOOPT: test1 -; GNU_NOOPT: callq sinf -; GNU_NOOPT: callq cosf +; GNU_SINCOS_FASTMATH-LABEL: test1: +; GNU_SINCOS_FASTMATH: callq sincosf +; GNU_SINCOS_FASTMATH: movss 4(%{{[re]}}sp), %xmm0 +; GNU_SINCOS_FASTMATH: addss (%{{[re]}}sp), %xmm0 ; OSX_SINCOS-LABEL: test1: ; OSX_SINCOS: callq ___sincosf_stret ; OSX_SINCOS: movshdup {{.*}} xmm1 = xmm0[1,1,3,3] ; OSX_SINCOS: addss %xmm1, %xmm0 -; OSX_NOOPT: test1 +; OSX_NOOPT-LABEL: test1: ; OSX_NOOPT: callq _sinf ; OSX_NOOPT: callq _cosf - %call = tail call float @sinf(float %x) nounwind readnone - %call1 = tail call float @cosf(float %x) nounwind readnone + %call = tail call float @sinf(float %x) readnone + %call1 = tail call float @cosf(float %x) readnone + %add = fadd float %call, %call1 + ret float %add +} + +define float @test1_errno(float %x) nounwind { +entry: +; GNU_SINCOS-LABEL: test1_errno: +; GNU_SINCOS: callq sinf +; GNU_SINCOS: callq cosf + +; GNU_SINCOS_FASTMATH-LABEL: test1_errno: +; GNU_SINCOS_FASTMATH: callq sinf +; GNU_SINCOS_FASTMATH: callq cosf + +; OSX_SINCOS-LABEL: test1_errno: +; OSX_SINCOS: callq _sinf +; OSX_SINCOS: callq _cosf + +; OSX_NOOPT-LABEL: test1_errno: +; OSX_NOOPT: callq _sinf +; OSX_NOOPT: callq _cosf + %call = tail call float @sinf(float %x) + %call1 = tail call float @cosf(float %x) %add = fadd float %call, %call1 ret float %add } @@ -45,24 +66,43 @@ entry: ; GNU_SINCOS: movsd 16(%rsp), %xmm0 ; GNU_SINCOS: addsd 8(%rsp), %xmm0 -; GNUX32_SINCOS-LABEL: test2: -; GNUX32_SINCOS: callq sincos -; GNUX32_SINCOS: movsd 16(%esp), %xmm0 -; GNUX32_SINCOS: addsd 8(%esp), %xmm0 - -; GNU_NOOPT: test2: -; GNU_NOOPT: callq sin -; GNU_NOOPT: callq cos +; GNU_SINCOS_FASTMATH-LABEL: test2: +; GNU_SINCOS_FASTMATH: callq sincos +; GNU_SINCOS_FASTMATH: movsd 16(%{{[re]}}sp), %xmm0 +; GNU_SINCOS_FASTMATH: addsd 8(%{{[re]}}sp), %xmm0 ; OSX_SINCOS-LABEL: test2: ; OSX_SINCOS: callq ___sincos_stret ; OSX_SINCOS: addsd %xmm1, %xmm0 -; OSX_NOOPT: test2 +; OSX_NOOPT-LABEL: test2: +; OSX_NOOPT: callq _sin +; OSX_NOOPT: callq _cos + %call = tail call double @sin(double %x) readnone + %call1 = tail call double @cos(double %x) readnone + %add = fadd double %call, %call1 + ret double %add +} + +define double @test2_errno(double %x) nounwind { +entry: +; GNU_SINCOS-LABEL: test2_errno: +; GNU_SINCOS: callq sin +; GNU_SINCOS: callq cos + +; GNU_SINCOS_FASTMATH-LABEL: test2_errno: +; GNU_SINCOS_FASTMATH: callq sin +; GNU_SINCOS_FASTMATH: callq cos + +; OSX_SINCOS-LABEL: test2_errno: +; OSX_SINCOS: callq _sin +; OSX_SINCOS: callq _cos + +; OSX_NOOPT-LABEL: test2_errno: ; OSX_NOOPT: callq _sin ; OSX_NOOPT: callq _cos - %call = tail call double @sin(double %x) nounwind readnone - %call1 = tail call double @cos(double %x) nounwind readnone + %call = tail call double @sin(double %x) + %call1 = tail call double @cos(double %x) %add = fadd double %call, %call1 ret double %add } @@ -70,29 +110,40 @@ entry: define x86_fp80 @test3(x86_fp80 %x) nounwind { entry: ; GNU_SINCOS-LABEL: test3: +; GNU_SINCOS: callq sincosl +; GNU_SINCOS: fldt 16(%rsp) +; GNU_SINCOS: fldt 32(%rsp) +; GNU_SINCOS: faddp %st(1) + +; GNU_SINCOS_FASTMATH-LABEL: test3: +; GNU_SINCOS_FASTMATH: fsin +; GNU_SINCOS_FASTMATH: fcos +; GNU_SINCOS_FASTMATH: faddp %st(1) +; GNU_SINCOS_FASTMATH: ret + %call = tail call x86_fp80 @sinl(x86_fp80 %x) readnone + %call1 = tail call x86_fp80 @cosl(x86_fp80 %x) readnone + %add = fadd x86_fp80 %call, %call1 + ret x86_fp80 %add +} + +define x86_fp80 @test3_errno(x86_fp80 %x) nounwind { +entry: +; GNU_SINCOS-LABEL: test3_errno: ; GNU_SINCOS: callq sinl ; GNU_SINCOS: callq cosl -; GNU_SINCOS: ret -; GNUX32_SINCOS-LABEL: test3: -; GNUX32_SINCOS: callq sinl -; GNUX32_SINCOS: callq cosl -; GNUX32_SINCOS: ret - -; GNU_NOOPT: test3: -; GNU_NOOPT: callq sinl -; GNU_NOOPT: callq cosl - - %call = tail call x86_fp80 @sinl(x86_fp80 %x) nounwind - %call1 = tail call x86_fp80 @cosl(x86_fp80 %x) nounwind +; GNU_SINCOS_FASTMATH-LABEL: test3_errno: +; GNU_SINCOS_FASTMATH: callq sinl +; GNU_SINCOS_FASTMATH: callq cosl + %call = tail call x86_fp80 @sinl(x86_fp80 %x) + %call1 = tail call x86_fp80 @cosl(x86_fp80 %x) %add = fadd x86_fp80 %call, %call1 ret x86_fp80 %add } -declare float @sinf(float) readonly -declare double @sin(double) readonly -declare float @cosf(float) readonly -declare double @cos(double) readonly - +declare float @sinf(float) +declare double @sin(double) +declare float @cosf(float) +declare double @cos(double) declare x86_fp80 @sinl(x86_fp80) declare x86_fp80 @cosl(x86_fp80) diff --git a/test/CodeGen/X86/sse-intrinsics-x86-upgrade.ll b/test/CodeGen/X86/sse-intrinsics-x86-upgrade.ll index 77497d38c897..2ecba887f7cb 100644 --- a/test/CodeGen/X86/sse-intrinsics-x86-upgrade.ll +++ b/test/CodeGen/X86/sse-intrinsics-x86-upgrade.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | FileCheck %s define void @test_x86_sse_storeu_ps(i8* %a0, <4 x float> %a1) { diff --git a/test/CodeGen/X86/sse41-intrinsics-x86-upgrade.ll b/test/CodeGen/X86/sse41-intrinsics-x86-upgrade.ll index 26af37e30295..9bda90a23023 100644 --- a/test/CodeGen/X86/sse41-intrinsics-x86-upgrade.ll +++ b/test/CodeGen/X86/sse41-intrinsics-x86-upgrade.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse4.1 | FileCheck %s ; This test works just like the non-upgrade one except that it only checks @@ -230,7 +230,6 @@ define <16 x i8> @max_epi8(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK: ## BB#0: ; CHECK-NEXT: pmaxsb %xmm1, %xmm0 ; CHECK-NEXT: retl -; %res = call <16 x i8> @llvm.x86.sse41.pmaxsb(<16 x i8> %a0, <16 x i8> %a1) ret <16 x i8> %res } @@ -241,7 +240,6 @@ define <16 x i8> @min_epi8(<16 x i8> %a0, <16 x i8> %a1) { ; CHECK: ## BB#0: ; CHECK-NEXT: pminsb %xmm1, %xmm0 ; CHECK-NEXT: retl -; %res = call <16 x i8> @llvm.x86.sse41.pminsb(<16 x i8> %a0, <16 x i8> %a1) ret <16 x i8> %res } @@ -252,7 +250,6 @@ define <8 x i16> @max_epu16(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK: ## BB#0: ; CHECK-NEXT: pmaxuw %xmm1, %xmm0 ; CHECK-NEXT: retl -; %res = call <8 x i16> @llvm.x86.sse41.pmaxuw(<8 x i16> %a0, <8 x i16> %a1) ret <8 x i16> %res } @@ -263,7 +260,6 @@ define <8 x i16> @min_epu16(<8 x i16> %a0, <8 x i16> %a1) { ; CHECK: ## BB#0: ; CHECK-NEXT: pminuw %xmm1, %xmm0 ; CHECK-NEXT: retl -; %res = call <8 x i16> @llvm.x86.sse41.pminuw(<8 x i16> %a0, <8 x i16> %a1) ret <8 x i16> %res } @@ -274,7 +270,6 @@ define <4 x i32> @max_epi32(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK: ## BB#0: ; CHECK-NEXT: pmaxsd %xmm1, %xmm0 ; CHECK-NEXT: retl -; %res = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %a0, <4 x i32> %a1) ret <4 x i32> %res } @@ -285,7 +280,6 @@ define <4 x i32> @min_epi32(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK: ## BB#0: ; CHECK-NEXT: pminsd %xmm1, %xmm0 ; CHECK-NEXT: retl -; %res = call <4 x i32> @llvm.x86.sse41.pminsd(<4 x i32> %a0, <4 x i32> %a1) ret <4 x i32> %res } @@ -296,7 +290,6 @@ define <4 x i32> @max_epu32(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK: ## BB#0: ; CHECK-NEXT: pmaxud %xmm1, %xmm0 ; CHECK-NEXT: retl -; %res = call <4 x i32> @llvm.x86.sse41.pmaxud(<4 x i32> %a0, <4 x i32> %a1) ret <4 x i32> %res } @@ -307,7 +300,6 @@ define <4 x i32> @min_epu32(<4 x i32> %a0, <4 x i32> %a1) { ; CHECK: ## BB#0: ; CHECK-NEXT: pminud %xmm1, %xmm0 ; CHECK-NEXT: retl -; %res = call <4 x i32> @llvm.x86.sse41.pminud(<4 x i32> %a0, <4 x i32> %a1) ret <4 x i32> %res } diff --git a/test/CodeGen/X86/stack-folding-int-avx512.ll b/test/CodeGen/X86/stack-folding-int-avx512.ll index 38e19efb7132..362e656b4f22 100644 --- a/test/CodeGen/X86/stack-folding-int-avx512.ll +++ b/test/CodeGen/X86/stack-folding-int-avx512.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vbmi < %s | FileCheck %s +; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vbmi,+avx512cd < %s | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-unknown" @@ -450,6 +450,24 @@ define <64 x i8> @stack_fold_palignr_maskz(<64 x i8> %a0, <64 x i8> %a1, i64 %ma ret <64 x i8> %4 } +define <16 x i32> @stack_fold_vpconflictd(<16 x i32> %a0) { + ;CHECK-LABEL: stack_fold_vpconflictd + ;CHECK: vpconflictd {{-?[0-9]*}}(%rsp), {{%zmm[0-9][0-9]*}} {{.*#+}} 64-byte Folded Reload + %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() + %2 = call <16 x i32> @llvm.x86.avx512.mask.conflict.d.512(<16 x i32> %a0, <16 x i32> undef, i16 -1) + ret <16 x i32> %2 +} +declare <16 x i32> @llvm.x86.avx512.mask.conflict.d.512(<16 x i32>, <16 x i32>, i16) nounwind readonly + +define <8 x i64> @stack_fold_vpconflictq(<8 x i64> %a0) { + ;CHECK-LABEL: stack_fold_vpconflictq + ;CHECK: vpconflictq {{-?[0-9]*}}(%rsp), {{%zmm[0-9][0-9]*}} {{.*#+}} 64-byte Folded Reload + %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() + %2 = call <8 x i64> @llvm.x86.avx512.mask.conflict.q.512(<8 x i64> %a0, <8 x i64> undef, i8 -1) + ret <8 x i64> %2 +} +declare <8 x i64> @llvm.x86.avx512.mask.conflict.q.512(<8 x i64>, <8 x i64>, i8) nounwind readnone + define i64 @stack_fold_pcmpeqb(<64 x i8> %a0, <64 x i8> %a1) { ;CHECK-LABEL: stack_fold_pcmpeqb ;CHECK: vpcmpeqb {{-?[0-9]*}}(%rsp), {{%zmm[0-9][0-9]*}}, {{%k[0-7]}} {{.*#+}} 64-byte Folded Reload @@ -486,6 +504,61 @@ define i32 @stack_fold_pcmpeqw(<32 x i16> %a0, <32 x i16> %a1) { ret i32 %3 } +define i16 @stack_fold_pcmpeqd_mask(<16 x i32> %a0, <16 x i32> %a1, <16 x i32>* %a2, i16 %mask) { + ;CHECK-LABEL: stack_fold_pcmpeqd_mask + ;CHECK: vpcmpeqd {{-?[0-9]*}}(%rsp), {{%zmm[0-9][0-9]*}}, {{%k[0-7]}} {{{%k[0-7]}}} {{.*#+}} 64-byte Folded Reload + %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() + ; load and add are here to keep the operations below the side effecting block and to avoid folding the wrong load + %2 = load <16 x i32>, <16 x i32>* %a2 + %3 = add <16 x i32> %a1, %2 + %4 = bitcast i16 %mask to <16 x i1> + %5 = icmp eq <16 x i32> %3, %a0 + %6 = and <16 x i1> %4, %5 + %7 = bitcast <16 x i1> %6 to i16 + ret i16 %7 +} + +define i16 @stack_fold_pcmpeqd_mask_commuted(<16 x i32> %a0, <16 x i32> %a1, <16 x i32>* %a2, i16 %mask) { + ;CHECK-LABEL: stack_fold_pcmpeqd_mask_commuted + ;CHECK: vpcmpeqd {{-?[0-9]*}}(%rsp), {{%zmm[0-9][0-9]*}}, {{%k[0-7]}} {{{%k[0-7]}}} {{.*#+}} 64-byte Folded Reload + %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() + ; load and add are here to keep the operations below the side effecting block and to avoid folding the wrong load + %2 = load <16 x i32>, <16 x i32>* %a2 + %3 = add <16 x i32> %a1, %2 + %4 = bitcast i16 %mask to <16 x i1> + %5 = icmp eq <16 x i32> %a0, %3 + %6 = and <16 x i1> %4, %5 + %7 = bitcast <16 x i1> %6 to i16 + ret i16 %7 +} + +define i16 @stack_fold_pcmpled_mask(<16 x i32> %a0, <16 x i32> %a1, <16 x i32>* %a2, i16 %mask) { + ;CHECK-LABEL: stack_fold_pcmpled_mask + ;CHECK: vpcmpled {{-?[0-9]*}}(%rsp), {{%zmm[0-9][0-9]*}}, {{%k[0-7]}} {{{%k[0-7]}}} {{.*#+}} 64-byte Folded Reload + %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() + ; load and add are here to keep the operations below the side effecting block and to avoid folding the wrong load + %2 = load <16 x i32>, <16 x i32>* %a2 + %3 = add <16 x i32> %a1, %2 + %4 = bitcast i16 %mask to <16 x i1> + %5 = icmp sge <16 x i32> %a0, %3 + %6 = and <16 x i1> %4, %5 + %7 = bitcast <16 x i1> %6 to i16 + ret i16 %7 +} + +define i16 @stack_fold_pcmpleud(<16 x i32> %a0, <16 x i32> %a1, <16 x i32>* %a2, i16 %mask) { + ;CHECK-LABEL: stack_fold_pcmpleud + ;CHECK: vpcmpleud {{-?[0-9]*}}(%rsp), {{%zmm[0-9][0-9]*}}, {{%k[0-7]}} {{.*#+}} 64-byte Folded Reload + %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() + %2 = load <16 x i32>, <16 x i32>* %a2 + %3 = add <16 x i32> %a1, %2 + %4 = bitcast i16 %mask to <16 x i1> + %5 = icmp uge <16 x i32> %a0, %3 + %6 = and <16 x i1> %5, %4 + %7 = bitcast <16 x i1> %6 to i16 + ret i16 %7 +} + define <64 x i8> @stack_fold_permbvar(<64 x i8> %a0, <64 x i8> %a1) { ;CHECK-LABEL: stack_fold_permbvar ;CHECK: vpermb {{-?[0-9]*}}(%rsp), {{%zmm[0-9][0-9]*}}, {{%zmm[0-9][0-9]*}} {{.*#+}} 64-byte Folded Reload @@ -740,6 +813,24 @@ define <8 x i16> @stack_fold_pinsrw(<8 x i16> %a0, i16 %a1) { ret <8 x i16> %2 } +define <16 x i32> @stack_fold_vplzcntd(<16 x i32> %a0) { + ;CHECK-LABEL: stack_fold_vplzcntd + ;CHECK: vplzcntd {{-?[0-9]*}}(%rsp), {{%zmm[0-9][0-9]*}} {{.*#+}} 64-byte Folded Reload + %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() + %2 = call <16 x i32> @llvm.ctlz.v16i32(<16 x i32> %a0) + ret <16 x i32> %2 +} +declare <16 x i32> @llvm.ctlz.v16i32(<16 x i32>) nounwind readonly + +define <8 x i64> @stack_fold_vplzcntq(<8 x i64> %a0) { + ;CHECK-LABEL: stack_fold_vplzcntq + ;CHECK: vplzcntq {{-?[0-9]*}}(%rsp), {{%zmm[0-9][0-9]*}} {{.*#+}} 64-byte Folded Reload + %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() + %2 = call <8 x i64> @llvm.ctlz.v8i64(<8 x i64> %a0) + ret <8 x i64> %2 +} +declare <8 x i64> @llvm.ctlz.v8i64(<8 x i64>) nounwind readnone + define <32 x i16> @stack_fold_pmaddubsw_zmm(<64 x i8> %a0, <64 x i8> %a1) { ;CHECK-LABEL: stack_fold_pmaddubsw_zmm ;CHECK: vpmaddubsw {{-?[0-9]*}}(%rsp), {{%zmm[0-9][0-9]*}}, {{%zmm[0-9][0-9]*}} {{.*#+}} 64-byte Folded Reload diff --git a/test/CodeGen/X86/stack-folding-int-avx512vl.ll b/test/CodeGen/X86/stack-folding-int-avx512vl.ll index 7ce798f778a3..26e97ea4e599 100644 --- a/test/CodeGen/X86/stack-folding-int-avx512vl.ll +++ b/test/CodeGen/X86/stack-folding-int-avx512vl.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+avx512bw,+avx512dq,+avx512vbmi < %s | FileCheck %s +; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+avx512bw,+avx512dq,+avx512vbmi,+avx512cd < %s | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-unknown" @@ -81,6 +81,42 @@ define <16 x i16> @stack_fold_pavgw_ymm(<16 x i16> %a0, <16 x i16> %a1) { } declare <16 x i16> @llvm.x86.avx2.pavg.w(<16 x i16>, <16 x i16>) nounwind readnone +define <4 x i32> @stack_fold_vpconflictd(<4 x i32> %a0) { + ;CHECK-LABEL: stack_fold_vpconflictd + ;CHECK: vpconflictd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload + %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() + %2 = call <4 x i32> @llvm.x86.avx512.mask.conflict.d.128(<4 x i32> %a0, <4 x i32> undef, i8 -1) + ret <4 x i32> %2 +} +declare <4 x i32> @llvm.x86.avx512.mask.conflict.d.128(<4 x i32>, <4 x i32>, i8) nounwind readonly + +define <8 x i32> @stack_fold_vpconflictd_ymm(<8 x i32> %a0) { + ;CHECK-LABEL: stack_fold_vpconflictd_ymm + ;CHECK: vpconflictd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload + %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() + %2 = call <8 x i32> @llvm.x86.avx512.mask.conflict.d.256(<8 x i32> %a0, <8 x i32> undef, i8 -1) + ret <8 x i32> %2 +} +declare <8 x i32> @llvm.x86.avx512.mask.conflict.d.256(<8 x i32>, <8 x i32>, i8) nounwind readonly + +define <2 x i64> @stack_fold_vpconflictq(<2 x i64> %a0) { + ;CHECK-LABEL: stack_fold_vpconflictq + ;CHECK: vpconflictq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload + %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() + %2 = call <2 x i64> @llvm.x86.avx512.mask.conflict.q.128(<2 x i64> %a0, <2 x i64> undef, i8 -1) + ret <2 x i64> %2 +} +declare <2 x i64> @llvm.x86.avx512.mask.conflict.q.128(<2 x i64>, <2 x i64>, i8) nounwind readnone + +define <4 x i64> @stack_fold_vpconflictq_ymm(<4 x i64> %a0) { + ;CHECK-LABEL: stack_fold_vpconflictq_ymm + ;CHECK: vpconflictq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload + %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() + %2 = call <4 x i64> @llvm.x86.avx512.mask.conflict.q.256(<4 x i64> %a0, <4 x i64> undef, i8 -1) + ret <4 x i64> %2 +} +declare <4 x i64> @llvm.x86.avx512.mask.conflict.q.256(<4 x i64>, <4 x i64>, i8) nounwind readnone + define <4 x i32> @stack_fold_extracti32x4(<8 x i32> %a0, <8 x i32> %a1) { ;CHECK-LABEL: stack_fold_extracti32x4 ;CHECK: vextracti128 $1, {{%ymm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 16-byte Folded Spill @@ -708,6 +744,42 @@ define <16 x i16> @stack_fold_permwvar(<16 x i16> %a0, <16 x i16> %a1) { } declare <16 x i16> @llvm.x86.avx512.mask.permvar.hi.256(<16 x i16>, <16 x i16>, <16 x i16>, i16) nounwind readonly +define <4 x i32> @stack_fold_vplzcntd(<4 x i32> %a0) { + ;CHECK-LABEL: stack_fold_vplzcntd + ;CHECK: vplzcntd {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload + %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() + %2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %a0) + ret <4 x i32> %2 +} +declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>) nounwind readonly + +define <8 x i32> @stack_fold_vplzcntd_ymm(<8 x i32> %a0) { + ;CHECK-LABEL: stack_fold_vplzcntd_ymm + ;CHECK: vplzcntd {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload + %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() + %2 = call <8 x i32> @llvm.ctlz.v8i32(<8 x i32> %a0) + ret <8 x i32> %2 +} +declare <8 x i32> @llvm.ctlz.v8i32(<8 x i32>) nounwind readonly + +define <2 x i64> @stack_fold_vplzcntq(<2 x i64> %a0) { + ;CHECK-LABEL: stack_fold_vplzcntq + ;CHECK: vplzcntq {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload + %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() + %2 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a0) + ret <2 x i64> %2 +} +declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>) nounwind readnone + +define <4 x i64> @stack_fold_vplzcntq_ymm(<4 x i64> %a0) { + ;CHECK-LABEL: stack_fold_vplzcntq_ymm + ;CHECK: vplzcntq {{-?[0-9]*}}(%rsp), {{%ymm[0-9][0-9]*}} {{.*#+}} 32-byte Folded Reload + %1 = tail call <2 x i64> asm sideeffect "nop", "=x,~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"() + %2 = call <4 x i64> @llvm.ctlz.v4i64(<4 x i64> %a0) + ret <4 x i64> %2 +} +declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>) nounwind readnone + define <8 x i16> @stack_fold_pmaddubsw(<16 x i8> %a0, <16 x i8> %a1) { ;CHECK-LABEL: stack_fold_pmaddubsw ;CHECK: vpmaddubsw {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}}, {{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte Folded Reload diff --git a/test/CodeGen/X86/statepoint-live-in.ll b/test/CodeGen/X86/statepoint-live-in.ll index aaa4d7c8422a..0179d37ad4e1 100644 --- a/test/CodeGen/X86/statepoint-live-in.ll +++ b/test/CodeGen/X86/statepoint-live-in.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -O3 < %s | FileCheck %s target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.11.0" @@ -16,7 +16,6 @@ define void @test1(i32 %a) gc "statepoint-example" { ; CHECK-NEXT: Ltmp0: ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq -; entry: ; We expect the argument to be passed in an extra register to bar %statepoint_token1 = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 1, i32 %a) @@ -49,7 +48,6 @@ define void @test2(i32 %a, i32 %b) gc "statepoint-example" { ; CHECK-NEXT: popq %rbx ; CHECK-NEXT: popq %rbp ; CHECK-NEXT: retq -; entry: ; Because the first call clobbers esi, we have to move the values into ; new registers. Note that they stay in the registers for both calls. @@ -68,7 +66,6 @@ define void @test3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 % ; CHECK-NEXT: Ltmp3: ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq -; entry: ; We directly reference the argument slot %statepoint_token1 = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 9, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i) @@ -89,7 +86,6 @@ define void @test4(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 % ; CHECK-NEXT: Ltmp4: ; CHECK-NEXT: popq %rax ; CHECK-NEXT: retq -; entry: %statepoint_token1 = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 26, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n, i32 %o, i32 %p, i32 %q, i32 %r, i32 %s, i32 %t, i32 %u, i32 %v, i32 %w, i32 %x, i32 %y, i32 %z) ret void @@ -111,7 +107,6 @@ define i32 addrspace(1)* @test5(i32 %a, i32 addrspace(1)* %p) gc "statepoint-ex ; CHECK-NEXT: movq (%rsp), %rax ; CHECK-NEXT: popq %rcx ; CHECK-NEXT: retq -; entry: %token = call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 1, i32 %a, i32 addrspace(1)* %p, i32 addrspace(1)* %p) %p2 = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token %token, i32 9, i32 9) @@ -139,7 +134,6 @@ define void @test6(i32 %a) gc "statepoint-example" { ; CHECK-NEXT: addq $16, %rsp ; CHECK-NEXT: popq %rbx ; CHECK-NEXT: retq -; entry: call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @baz, i32 0, i32 0, i32 0, i32 1, i32 %a) call token (i64, i32, void ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_isVoidf(i64 2882400000, i32 0, void ()* @bar, i32 0, i32 2, i32 0, i32 1, i32 %a) diff --git a/test/CodeGen/X86/swifterror.ll b/test/CodeGen/X86/swifterror.ll index 5704d1919988..1ecd33743d21 100644 --- a/test/CodeGen/X86/swifterror.ll +++ b/test/CodeGen/X86/swifterror.ll @@ -712,3 +712,111 @@ trueBB: falseBB: ret void } + + +declare swiftcc void @foo2(%swift_error** swifterror) + +; Make sure we properly assign registers during fast-isel. +; CHECK-O0-LABEL: testAssign +; CHECK-O0: pushq %r12 +; CHECK-O0: xorl [[ZERO:%[a-z0-9]+]], [[ZERO]] +; CHECK-O0: movl [[ZERO]], %r12d +; CHECK-O0: callq _foo2 +; CHECK-O0: movq %r12, [[SLOT:[-a-z0-9\(\)\%]*]] +; +; CHECK-O0: movq [[SLOT]], %rax +; CHECK-O0: popq %r12 +; CHECK-O0: retq + +; CHECK-APPLE-LABEL: testAssign +; CHECK-APPLE: pushq %r12 +; CHECK-APPLE: xorl %r12d, %r12d +; CHECK-APPLE: callq _foo2 +; CHECK-APPLE: movq %r12, %rax +; CHECK-APPLE: popq %r12 +; CHECK-APPLE: retq + +define swiftcc %swift_error* @testAssign(i8* %error_ref) { +entry: + %error_ptr = alloca swifterror %swift_error* + store %swift_error* null, %swift_error** %error_ptr + call swiftcc void @foo2(%swift_error** swifterror %error_ptr) + br label %a + +a: + %error = load %swift_error*, %swift_error** %error_ptr + ret %swift_error* %error +} + +; CHECK-O0-LABEL: testAssign2 +; CHECK-O0: movq %r12, {{.*}} +; CHECK-O0: movq %r12, [[SLOT:[-a-z0-9\(\)\%]*]] +; CHECK-O0: jmp +; CHECK-O0: movq [[SLOT]], %rax +; CHECK-O0: movq %rax, [[SLOT2:[-a-z0-9\(\)\%]*]] +; CHECK-O0: movq [[SLOT2]], %r12 +; CHECK-O0: retq + +; CHECK-APPLE-LABEL: testAssign2 +; CHECK-APPLE: movq %r12, %rax +; CHECK-APPLE: retq +define swiftcc %swift_error* @testAssign2(i8* %error_ref, %swift_error** swifterror %err) { +entry: + br label %a + +a: + %error = load %swift_error*, %swift_error** %err + ret %swift_error* %error +} + +; CHECK-O0-LABEL: testAssign3 +; CHECK-O0: callq _foo2 +; CHECK-O0: movq %r12, [[SLOT:[-a-z0-9\(\)\%]*]] +; CHECK-O0: movq [[SLOT]], %rax +; CHECK-O0: movq %rax, [[SLOT2:[-a-z0-9\(\)\%]*]] +; CHECK-O0: movq [[SLOT2]], %r12 +; CHECK-O0: addq $24, %rsp +; CHECK-O0: retq + +; CHECK-APPLE-LABEL: testAssign3 +; CHECK-APPLE: callq _foo2 +; CHECK-APPLE: movq %r12, %rax +; CHECK-APPLE: retq + +define swiftcc %swift_error* @testAssign3(i8* %error_ref, %swift_error** swifterror %err) { +entry: + call swiftcc void @foo2(%swift_error** swifterror %err) + br label %a + +a: + %error = load %swift_error*, %swift_error** %err + ret %swift_error* %error +} + + +; CHECK-O0-LABEL: testAssign4 +; CHECK-O0: callq _foo2 +; CHECK-O0: xorl %ecx, %ecx +; CHECK-O0: movl %ecx, %eax +; CHECK-O0: movq %rax, [[SLOT:[-a-z0-9\(\)\%]*]] +; CHECK-O0: movq [[SLOT]], %rax +; CHECK-O0: movq %rax, [[SLOT2:[-a-z0-9\(\)\%]*]] +; CHECK-O0: movq [[SLOT2]], %r12 +; CHECK-O0: retq + +; CHECK-APPLE-LABEL: testAssign4 +; CHECK-APPLE: callq _foo2 +; CHECK-APPLE: xorl %eax, %eax +; CHECK-APPLE: xorl %r12d, %r12d +; CHECK-APPLE: retq + +define swiftcc %swift_error* @testAssign4(i8* %error_ref, %swift_error** swifterror %err) { +entry: + call swiftcc void @foo2(%swift_error** swifterror %err) + store %swift_error* null, %swift_error** %err + br label %a + +a: + %error = load %swift_error*, %swift_error** %err + ret %swift_error* %error +} diff --git a/test/CodeGen/X86/urem-i8-constant.ll b/test/CodeGen/X86/urem-i8-constant.ll index 45717f985c23..2a659b20de8f 100644 --- a/test/CodeGen/X86/urem-i8-constant.ll +++ b/test/CodeGen/X86/urem-i8-constant.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s define i8 @foo(i8 %tmp325) { @@ -14,7 +14,6 @@ define i8 @foo(i8 %tmp325) { ; CHECK-NEXT: subb %al, %cl ; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: retl -; %t546 = urem i8 %tmp325, 37 ret i8 %t546 } diff --git a/test/CodeGen/X86/urem-power-of-two.ll b/test/CodeGen/X86/urem-power-of-two.ll index 469c573443ea..1b56c87aad5f 100644 --- a/test/CodeGen/X86/urem-power-of-two.ll +++ b/test/CodeGen/X86/urem-power-of-two.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s ; The easy case: a constant power-of-2 divisor. @@ -9,7 +9,6 @@ define i64 @const_pow_2(i64 %x) { ; CHECK-NEXT: andl $31, %edi ; CHECK-NEXT: movq %rdi, %rax ; CHECK-NEXT: retq -; %urem = urem i64 %x, 32 ret i64 %urem } @@ -25,7 +24,6 @@ define i25 @shift_left_pow_2(i25 %x, i25 %y) { ; CHECK-NEXT: addl $33554431, %eax # imm = 0x1FFFFFF ; CHECK-NEXT: andl %edi, %eax ; CHECK-NEXT: retq -; %shl = shl i25 1, %y %urem = urem i25 %x, %shl ret i25 %urem @@ -43,7 +41,6 @@ define i16 @shift_right_pow_2(i16 %x, i16 %y) { ; CHECK-NEXT: andl %edi, %eax ; CHECK-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill> ; CHECK-NEXT: retq -; %shr = lshr i16 -32768, %y %urem = urem i16 %x, %shr ret i16 %urem @@ -61,7 +58,6 @@ define i8 @and_pow_2(i8 %x, i8 %y) { ; CHECK-NEXT: movzbl %ah, %eax # NOREX ; CHECK-NEXT: # kill: %AL<def> %AL<kill> %EAX<kill> ; CHECK-NEXT: retq -; %and = and i8 %y, 4 %urem = urem i8 %x, %and ret i8 %urem @@ -74,7 +70,6 @@ define <4 x i32> @vec_const_pow_2(<4 x i32> %x) { ; CHECK: # BB#0: ; CHECK-NEXT: andps {{.*}}(%rip), %xmm0 ; CHECK-NEXT: retq -; %urem = urem <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16> ret <4 x i32> %urem } diff --git a/test/CodeGen/X86/vec3.ll b/test/CodeGen/X86/vec3.ll index 8eaf9f4f48e4..e9c47ffd21c6 100644 --- a/test/CodeGen/X86/vec3.ll +++ b/test/CodeGen/X86/vec3.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse | FileCheck %s define <3 x float> @fadd(<3 x float> %v, float %d) { @@ -7,7 +7,6 @@ define <3 x float> @fadd(<3 x float> %v, float %d) { ; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,3] ; CHECK-NEXT: addps %xmm1, %xmm0 ; CHECK-NEXT: retq -; %ins = insertelement <3 x float> undef, float %d, i32 0 %splat = shufflevector <3 x float> %ins, <3 x float> undef, <3 x i32> zeroinitializer %add = fadd <3 x float> %splat, %v @@ -23,7 +22,6 @@ define <3 x float> @fdiv(<3 x float> %v, float %d) { ; CHECK-NEXT: divps %xmm0, %xmm1 ; CHECK-NEXT: movaps %xmm1, %xmm0 ; CHECK-NEXT: retq -; %ins = insertelement <3 x float> undef, float %d, i32 0 %splat = shufflevector <3 x float> %ins, <3 x float> undef, <3 x i32> zeroinitializer %div = fdiv <3 x float> %splat, %v diff --git a/test/CodeGen/X86/vector-compare-combines.ll b/test/CodeGen/X86/vector-compare-combines.ll index c25474d92f9c..bd7cbfb4bac0 100644 --- a/test/CodeGen/X86/vector-compare-combines.ll +++ b/test/CodeGen/X86/vector-compare-combines.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE42 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1 @@ -17,7 +17,6 @@ define <4 x i32> @PR27924_cmpeq(<4 x i32> %a, <4 x i32> %b) { ; AVX: # BB#0: ; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; AVX-NEXT: retq -; %cmp = icmp sgt <4 x i32> %a, %b %max = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> %b %sse_max = tail call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %a, <4 x i32> %b) @@ -36,7 +35,6 @@ define <4 x i32> @PR27924_cmpgt(<4 x i32> %a, <4 x i32> %b) { ; AVX: # BB#0: ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 ; AVX-NEXT: retq -; %cmp = icmp sgt <4 x i32> %a, %b %max = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> %b %sse_max = tail call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %a, <4 x i32> %b) diff --git a/test/CodeGen/X86/vector-shuffle-256-v16.ll b/test/CodeGen/X86/vector-shuffle-256-v16.ll index fad5586dd77c..d34728df29b7 100644 --- a/test/CodeGen/X86/vector-shuffle-256-v16.ll +++ b/test/CodeGen/X86/vector-shuffle-256-v16.ll @@ -1559,6 +1559,24 @@ define <16 x i16> @shuffle_v16i16_17_18_19_20_21_22_23_zz_25_26_27_28_29_30_31_z ret <16 x i16> %shuffle } +define <16 x i16> @shuffle_v16i16_06_07_01_02_07_00_04_05_14_15_09_10_15_08_12_13(<16 x i16> %a) { +; AVX1-LABEL: shuffle_v16i16_06_07_01_02_07_00_04_05_14_15_09_10_15_08_12_13: +; AVX1: # BB#0: +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [12,13,14,15,2,3,4,5,14,15,0,1,8,9,10,11] +; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 +; AVX1-NEXT: retq +; +; AVX2OR512VL-LABEL: shuffle_v16i16_06_07_01_02_07_00_04_05_14_15_09_10_15_08_12_13: +; AVX2OR512VL: # BB#0: +; AVX2OR512VL-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[12,13,14,15,2,3,4,5,14,15,0,1,8,9,10,11,28,29,30,31,18,19,20,21,30,31,16,17,24,25,26,27] +; AVX2OR512VL-NEXT: retq + %1 = shufflevector <16 x i16> %a, <16 x i16> undef, <16 x i32> <i32 6, i32 7, i32 1, i32 2, i32 7, i32 0, i32 4, i32 5, i32 14, i32 15, i32 9, i32 10, i32 15, i32 8, i32 12, i32 13> + ret <16 x i16> %1 +} + ; ; Shuffle to logical bit shifts ; diff --git a/test/CodeGen/X86/vzero-excess.ll b/test/CodeGen/X86/vzero-excess.ll index 0ed90741b61e..9ddafec65182 100644 --- a/test/CodeGen/X86/vzero-excess.ll +++ b/test/CodeGen/X86/vzero-excess.ll @@ -1,4 +1,4 @@ -; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s ; In the following 4 tests, the existing call to VZU/VZA ensures clean state before diff --git a/test/CodeGen/X86/x86-interleaved-access.ll b/test/CodeGen/X86/x86-interleaved-access.ll index 74214aa1b8b7..ec8bce1b43cc 100644 --- a/test/CodeGen/X86/x86-interleaved-access.ll +++ b/test/CodeGen/X86/x86-interleaved-access.ll @@ -9,8 +9,8 @@ define <4 x double> @load_factorf64_4(<16 x double>* %ptr) { ; AVX-NEXT: vmovupd 32(%rdi), %ymm1 ; AVX-NEXT: vmovupd 64(%rdi), %ymm2 ; AVX-NEXT: vmovupd 96(%rdi), %ymm3 -; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm4 -; AVX-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm5 +; AVX-NEXT: vperm2f128 {{.*#+}} ymm4 = ymm0[0,1],ymm2[0,1] +; AVX-NEXT: vperm2f128 {{.*#+}} ymm5 = ymm1[0,1],ymm3[0,1] ; AVX-NEXT: vhaddpd %ymm5, %ymm4, %ymm4 ; AVX-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm2[2,3] ; AVX-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm1[2,3],ymm3[2,3] @@ -37,8 +37,8 @@ define <4 x double> @load_factorf64_2(<16 x double>* %ptr) { ; AVX-NEXT: vmovupd 32(%rdi), %ymm1 ; AVX-NEXT: vmovupd 64(%rdi), %ymm2 ; AVX-NEXT: vmovupd 96(%rdi), %ymm3 -; AVX-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm4 -; AVX-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm5 +; AVX-NEXT: vperm2f128 {{.*#+}} ymm4 = ymm0[0,1],ymm2[0,1] +; AVX-NEXT: vperm2f128 {{.*#+}} ymm5 = ymm1[0,1],ymm3[0,1] ; AVX-NEXT: vunpcklpd {{.*#+}} ymm4 = ymm4[0],ymm5[0],ymm4[2],ymm5[2] ; AVX-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm2[2,3] ; AVX-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm1[2,3],ymm3[2,3] @@ -53,25 +53,15 @@ define <4 x double> @load_factorf64_2(<16 x double>* %ptr) { } define <4 x double> @load_factorf64_1(<16 x double>* %ptr) { -; AVX1-LABEL: load_factorf64_1: -; AVX1: # BB#0: -; AVX1-NEXT: vmovups (%rdi), %ymm0 -; AVX1-NEXT: vmovups 32(%rdi), %ymm1 -; AVX1-NEXT: vinsertf128 $1, 64(%rdi), %ymm0, %ymm0 -; AVX1-NEXT: vinsertf128 $1, 96(%rdi), %ymm1, %ymm1 -; AVX1-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2] -; AVX1-NEXT: vmulpd %ymm0, %ymm0, %ymm0 -; AVX1-NEXT: retq -; -; AVX2-LABEL: load_factorf64_1: -; AVX2: # BB#0: -; AVX2-NEXT: vmovupd (%rdi), %ymm0 -; AVX2-NEXT: vmovupd 32(%rdi), %ymm1 -; AVX2-NEXT: vinsertf128 $1, 64(%rdi), %ymm0, %ymm0 -; AVX2-NEXT: vinsertf128 $1, 96(%rdi), %ymm1, %ymm1 -; AVX2-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2] -; AVX2-NEXT: vmulpd %ymm0, %ymm0, %ymm0 -; AVX2-NEXT: retq +; AVX-LABEL: load_factorf64_1: +; AVX: # BB#0: +; AVX-NEXT: vmovupd (%rdi), %ymm0 +; AVX-NEXT: vmovupd 32(%rdi), %ymm1 +; AVX-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[0,1],mem[0,1] +; AVX-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm1[0,1],mem[0,1] +; AVX-NEXT: vunpcklpd {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[2],ymm1[2] +; AVX-NEXT: vmulpd %ymm0, %ymm0, %ymm0 +; AVX-NEXT: retq %wide.vec = load <16 x double>, <16 x double>* %ptr, align 16 %strided.v0 = shufflevector <16 x double> %wide.vec, <16 x double> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> %strided.v3 = shufflevector <16 x double> %wide.vec, <16 x double> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12> @@ -86,8 +76,8 @@ define <4 x i64> @load_factori64_4(<16 x i64>* %ptr) { ; AVX1-NEXT: vmovupd 32(%rdi), %ymm1 ; AVX1-NEXT: vmovupd 64(%rdi), %ymm2 ; AVX1-NEXT: vmovupd 96(%rdi), %ymm3 -; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm4 -; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm5 +; AVX1-NEXT: vperm2f128 {{.*#+}} ymm4 = ymm0[0,1],ymm2[0,1] +; AVX1-NEXT: vperm2f128 {{.*#+}} ymm5 = ymm1[0,1],ymm3[0,1] ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm0[2,3],ymm2[2,3] ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm1 = ymm1[2,3],ymm3[2,3] ; AVX1-NEXT: vunpcklpd {{.*#+}} ymm2 = ymm4[0],ymm5[0],ymm4[2],ymm5[2] @@ -113,8 +103,8 @@ define <4 x i64> @load_factori64_4(<16 x i64>* %ptr) { ; AVX2-NEXT: vmovdqu 32(%rdi), %ymm1 ; AVX2-NEXT: vmovdqu 64(%rdi), %ymm2 ; AVX2-NEXT: vmovdqu 96(%rdi), %ymm3 -; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm4 -; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm1, %ymm5 +; AVX2-NEXT: vperm2i128 {{.*#+}} ymm4 = ymm0[0,1],ymm2[0,1] +; AVX2-NEXT: vperm2i128 {{.*#+}} ymm5 = ymm1[0,1],ymm3[0,1] ; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm2[2,3] ; AVX2-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm1[2,3],ymm3[2,3] ; AVX2-NEXT: vpunpcklqdq {{.*#+}} ymm2 = ymm4[0],ymm5[0],ymm4[2],ymm5[2] diff --git a/test/DebugInfo/COFF/array-odr-violation.ll b/test/DebugInfo/COFF/array-odr-violation.ll index 471c18f00afd..1041a90f0343 100644 --- a/test/DebugInfo/COFF/array-odr-violation.ll +++ b/test/DebugInfo/COFF/array-odr-violation.ll @@ -65,7 +65,7 @@ attributes #1 = { nounwind readnone } !llvm.dbg.cu = !{!2, !11} !llvm.ident = !{!13, !13} -!llvm.module.flags = !{!14, !18, !19, !20} +!llvm.module.flags = !{!18, !19, !20} !0 = !DIGlobalVariableExpression(var: !1) !1 = distinct !DIGlobalVariable(name: "a", linkageName: "\01?a@@3TYYSTYPE@@A", scope: !2, file: !3, line: 2, type: !6, isLocal: false, isDefinition: true) @@ -81,10 +81,6 @@ attributes #1 = { nounwind readnone } !11 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !12, producer: "clang version 5.0.0 ", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !4) !12 = !DIFile(filename: "b.cpp", directory: "C:\5Csrc\5Cllvm-project\5Cbuild", checksumkind: CSK_MD5, checksum: "9cfd390d8827beab36769147bb037abc") !13 = !{!"clang version 5.0.0 "} -!14 = !{i32 6, !"Linker Options", !15} -!15 = !{!16, !17} -!16 = !{!"/DEFAULTLIB:libcmt.lib"} -!17 = !{!"/DEFAULTLIB:oldnames.lib"} !18 = !{i32 2, !"CodeView", i32 1} !19 = !{i32 2, !"Debug Info Version", i32 3} !20 = !{i32 1, !"PIC Level", i32 2} diff --git a/test/DebugInfo/COFF/inlining-same-name.ll b/test/DebugInfo/COFF/inlining-same-name.ll index fda5a6dc6ff5..4a9c9924135d 100644 --- a/test/DebugInfo/COFF/inlining-same-name.ll +++ b/test/DebugInfo/COFF/inlining-same-name.ll @@ -39,12 +39,11 @@ define void @main(i32* %i.i) !dbg !16 { ret void } -!llvm.module.flags = !{!0, !1, !2} +!llvm.module.flags = !{!0, !1} !llvm.dbg.cu = !{!4} !0 = !{i32 2, !"CodeView", i32 1} !1 = !{i32 2, !"Debug Info Version", i32 3} -!2 = !{i32 6, !"Linker Options", !{}} !4 = distinct !DICompileUnit(language: DW_LANG_D, file: !5, producer: "LDC (http://wiki.dlang.org/LDC)", isOptimized: false, runtimeVersion: 1, emissionKind: FullDebug) !5 = !DIFile(filename: "opover2.d", directory: "C:\5CLDC\5Cninja-ldc\5C..\5Cldc\5Ctests\5Cd2\5Cdmd-testsuite\5Crunnable") !6 = !DILocation(line: 302, column: 9, scope: !7, inlinedAt: !15) diff --git a/test/DebugInfo/Generic/block-asan.ll b/test/DebugInfo/Generic/block-asan.ll index f1f8b35df27c..73df59bf3d5d 100644 --- a/test/DebugInfo/Generic/block-asan.ll +++ b/test/DebugInfo/Generic/block-asan.ll @@ -13,7 +13,7 @@ ; Check that the location of the ASAN instrumented __block variable is ; correct. -; CHECK: !DIExpression(DW_OP_plus, 8, DW_OP_deref, DW_OP_plus, 24) +; CHECK: !DIExpression(DW_OP_plus_uconst, 8, DW_OP_deref, DW_OP_plus_uconst, 24) target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" @@ -79,7 +79,7 @@ attributes #3 = { nounwind } !19 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) !20 = !DIDerivedType(tag: DW_TAG_member, name: "__size", size: 32, align: 32, offset: 160, file: !1, scope: !5, baseType: !19) !21 = !DIDerivedType(tag: DW_TAG_member, name: "x", size: 32, align: 32, offset: 192, file: !1, scope: !5, baseType: !19) -!22 = !DIExpression(DW_OP_plus, 8, DW_OP_deref, DW_OP_plus, 24) +!22 = !DIExpression(DW_OP_plus_uconst, 8, DW_OP_deref, DW_OP_plus_uconst, 24) !23 = !DILocation(line: 4, column: 15, scope: !4) !24 = !DILocation(line: 4, column: 3, scope: !4) !25 = !DILocation(line: 5, column: 3, scope: !4) diff --git a/test/DebugInfo/Inputs/dwarfdump-str-offsets-dwp.x86_64.o b/test/DebugInfo/Inputs/dwarfdump-str-offsets-dwp.x86_64.o Binary files differnew file mode 100644 index 000000000000..b3c73f72d246 --- /dev/null +++ b/test/DebugInfo/Inputs/dwarfdump-str-offsets-dwp.x86_64.o diff --git a/test/DebugInfo/Inputs/dwarfdump-str-offsets.s b/test/DebugInfo/Inputs/dwarfdump-str-offsets.s index e0a634c7c4a2..f395f4b872c1 100644 --- a/test/DebugInfo/Inputs/dwarfdump-str-offsets.s +++ b/test/DebugInfo/Inputs/dwarfdump-str-offsets.s @@ -248,253 +248,3 @@ TU_split_5_type: .byte 0 # NULL .byte 0 # NULL TU_split_5_end: -# Test object to verify dwarfdump handles v5 string offset tables. -# We have 2 v5 CUs, a v5 TU, and a split v5 CU and TU. -# -# To generate the test object: -# llvm-mc -triple x86_64-unknown-linux dwarfdump-str-offsets.s -filetype=obj \ -# -o dwarfdump-str-offsets.elf-x86-64 - - .section .debug_str,"MS",@progbits,1 -str_producer: - .asciz "Handmade DWARF producer" -str_CU1: - .asciz "Compile_Unit_1" -str_CU1_dir: - .asciz "/home/test/CU1" -str_CU2: - .asciz "Compile_Unit_2" -str_CU2_dir: - .asciz "/home/test/CU2" -str_TU: - .asciz "Type_Unit" -str_TU_type: - .asciz "MyStruct" - -# Every unit contributes to the string_offsets table. - .section .debug_str_offsets,"",@progbits -# CU1's contribution - .long .debug_str_offsets_segment0_end-.debug_str_offsets_base0 - .short 5 # DWARF version - .short 0 # Padding -.debug_str_offsets_base0: - .long str_producer - .long str_CU1 - .long str_CU1_dir -.debug_str_offsets_segment0_end: -# CU2's contribution - .long .debug_str_offsets_segment1_end-.debug_str_offsets_base1 - .short 5 # DWARF version - .short 0 # Padding -.debug_str_offsets_base1: - .long str_producer - .long str_CU2 - .long str_CU2_dir -.debug_str_offsets_segment1_end: -# The TU's contribution - .long .debug_str_offsets_segment2_end-.debug_str_offsets_base2 - .short 5 # DWARF version - .short 0 # Padding -.debug_str_offsets_base2: - .long str_TU - .long str_TU_type -.debug_str_offsets_segment2_end: - - .section .debug_str.dwo,"MS",@progbits,1 -dwo_str_CU_5_producer: - .asciz "Handmade split DWARF producer" -dwo_str_CU_5_name: - .asciz "V5_split_compile_unit" -dwo_str_CU_5_comp_dir: - .asciz "/home/test/splitCU" -dwo_str_TU_5: - .asciz "V5_split_type_unit" -dwo_str_TU_5_type: - .asciz "V5_split_Mystruct" - - .section .debug_str_offsets.dwo,"",@progbits -# The split CU's contribution - .long .debug_dwo_str_offsets_segment0_end-.debug_dwo_str_offsets_base0 - .short 5 # DWARF version - .short 0 # Padding -.debug_dwo_str_offsets_base0: - .long dwo_str_CU_5_producer-.debug_str.dwo - .long dwo_str_CU_5_name-.debug_str.dwo - .long dwo_str_CU_5_comp_dir-.debug_str.dwo -.debug_dwo_str_offsets_segment0_end: -# The split TU's contribution - .long .debug_dwo_str_offsets_segment1_end-.debug_dwo_str_offsets_base1 - .short 5 # DWARF version - .short 0 # Padding -.debug_dwo_str_offsets_base1: - .long dwo_str_TU_5-.debug_str.dwo - .long dwo_str_TU_5_type-.debug_str.dwo -.debug_dwo_str_offsets_segment1_end: - -# All CUs/TUs use the same abbrev section for simplicity. - .section .debug_abbrev,"",@progbits - .byte 0x01 # Abbrev code - .byte 0x11 # DW_TAG_compile_unit - .byte 0x00 # DW_CHILDREN_no - .byte 0x25 # DW_AT_producer - .byte 0x1a # DW_FORM_strx - .byte 0x03 # DW_AT_name - .byte 0x1a # DW_FORM_strx - .byte 0x72 # DW_AT_str_offsets_base - .byte 0x17 # DW_FORM_sec_offset - .byte 0x1b # DW_AT_comp_dir - .byte 0x1a # DW_FORM_strx - .byte 0x00 # EOM(1) - .byte 0x00 # EOM(2) - .byte 0x02 # Abbrev code - .byte 0x41 # DW_TAG_type_unit - .byte 0x01 # DW_CHILDREN_yes - .byte 0x03 # DW_AT_name - .byte 0x1a # DW_FORM_strx - .byte 0x72 # DW_AT_str_offsets_base - .byte 0x17 # DW_FORM_sec_offset - .byte 0x00 # EOM(1) - .byte 0x00 # EOM(2) - .byte 0x03 # Abbrev code - .byte 0x13 # DW_TAG_structure_type - .byte 0x00 # DW_CHILDREN_no (no members) - .byte 0x03 # DW_AT_name - .byte 0x1a # DW_FORM_strx - .byte 0x00 # EOM(1) - .byte 0x00 # EOM(2) - .byte 0x00 # EOM(3) - -# And a .dwo copy for the .dwo sections. - .section .debug_abbrev.dwo,"",@progbits - .byte 0x01 # Abbrev code - .byte 0x11 # DW_TAG_compile_unit - .byte 0x00 # DW_CHILDREN_no - .byte 0x25 # DW_AT_producer - .byte 0x1a # DW_FORM_strx - .byte 0x03 # DW_AT_name - .byte 0x1a # DW_FORM_strx - .byte 0x72 # DW_AT_str_offsets_base - .byte 0x17 # DW_FORM_sec_offset - .byte 0x1b # DW_AT_comp_dir - .byte 0x1a # DW_FORM_strx - .byte 0x00 # EOM(1) - .byte 0x00 # EOM(2) - .byte 0x02 # Abbrev code - .byte 0x41 # DW_TAG_type_unit - .byte 0x01 # DW_CHILDREN_yes - .byte 0x03 # DW_AT_name - .byte 0x1a # DW_FORM_strx - .byte 0x72 # DW_AT_str_offsets_base - .byte 0x17 # DW_FORM_sec_offset - .byte 0x00 # EOM(1) - .byte 0x00 # EOM(2) - .byte 0x03 # Abbrev code - .byte 0x13 # DW_TAG_structure_type - .byte 0x00 # DW_CHILDREN_no (no members) - .byte 0x03 # DW_AT_name - .byte 0x1a # DW_FORM_strx - .byte 0x00 # EOM(1) - .byte 0x00 # EOM(2) - .byte 0x00 # EOM(3) - - .section .debug_info,"",@progbits - -# DWARF v5 CU header. - .long CU1_5_end-CU1_5_version # Length of Unit -CU1_5_version: - .short 5 # DWARF version number - .byte 1 # DWARF Unit Type - .byte 8 # Address Size (in bytes) - .long .debug_abbrev # Offset Into Abbrev. Section -# The compile-unit DIE, which has a DW_AT_producer, DW_AT_name, -# DW_AT_str_offsets and DW_AT_compdir. - .byte 1 # Abbreviation code - .byte 0 # The index of the producer string - .byte 1 # The index of the CU name string - .long .debug_str_offsets_base0 - .byte 2 # The index of the comp dir string - .byte 0 # NULL -CU1_5_end: - -# DWARF v5 CU header - .long CU2_5_end-CU2_5_version # Length of Unit -CU2_5_version: - .short 5 # DWARF version number - .byte 1 # DWARF Unit Type - .byte 8 # Address Size (in bytes) - .long .debug_abbrev # Offset Into Abbrev. Section -# The compile-unit DIE, which has a DW_AT_producer, DW_AT_name, -# DW_AT_str_offsets and DW_AT_compdir. - .byte 1 # Abbreviation code - .byte 0 # The index of the producer string - .byte 1 # The index of the CU name string - .long .debug_str_offsets_base1 - .byte 2 # The index of the comp dir string - .byte 0 # NULL -CU2_5_end: - - .section .debug_types,"",@progbits -# DWARF v5 Type unit header. -TU_5_start: - .long TU_5_end-TU_5_version # Length of Unit -TU_5_version: - .short 5 # DWARF version number - .byte 2 # DWARF Unit Type - .byte 8 # Address Size (in bytes) - .long .debug_abbrev # Offset Into Abbrev. Section - .quad 0x0011223344556677 # Type Signature - .long TU_5_type-TU_5_start # Type offset -# The type-unit DIE, which has a name. - .byte 2 # Abbreviation code - .byte 0 # Index of the unit type name string - .long .debug_str_offsets_base2 # offset into the str_offsets section -# The type DIE, which has a name. -TU_5_type: - .byte 3 # Abbreviation code - .byte 1 # Index of the type name string - .byte 0 # NULL - .byte 0 # NULL -TU_5_end: - - .section .debug_info.dwo,"",@progbits - -# DWARF v5 split CU header. - .long CU_split_5_end-CU_split_5_version # Length of Unit -CU_split_5_version: - .short 5 # DWARF version number - .byte 1 # DWARF Unit Type - .byte 8 # Address Size (in bytes) - .long .debug_abbrev.dwo # Offset Into Abbrev Section -# The compile-unit DIE, which has a DW_AT_producer, DW_AT_name, -# DW_AT_str_offsets and DW_AT_compdir. - .byte 1 # Abbreviation code - .byte 0 # The index of the producer string - .byte 1 # The index of the CU name string - .long .debug_dwo_str_offsets_base0-.debug_str_offsets.dwo - .byte 2 # The index of the comp dir string - .byte 0 # NULL -CU_split_5_end: - - .section .debug_types.dwo,"",@progbits - -# DWARF v5 split type unit header. -TU_split_5_start: - .long TU_split_5_end-TU_split_5_version # Length of Unit -TU_split_5_version: - .short 5 # DWARF version number - .byte 6 # DWARF Unit Type - .byte 8 # Address Size (in bytes) - .long .debug_abbrev.dwo # Offset Into Abbrev Section - .quad 0x8899aabbccddeeff # Type Signature - .long TU_split_5_type-TU_split_5_start # Type offset -# The type-unit DIE, which has a name. - .byte 2 # Abbreviation code - .byte 0 # The index of the type unit name string - .long .debug_dwo_str_offsets_base1-.debug_str_offsets.dwo -# The type DIE, which has a name. -TU_split_5_type: - .byte 3 # Abbreviation code - .byte 1 # The index of the type name string - .byte 0 # NULL - .byte 0 # NULL -TU_split_5_end: diff --git a/test/DebugInfo/Inputs/dwarfdump-test-zlib.cc b/test/DebugInfo/Inputs/dwarfdump-test-zlib.cc index 966a465f9046..6c506381aa5d 100644 --- a/test/DebugInfo/Inputs/dwarfdump-test-zlib.cc +++ b/test/DebugInfo/Inputs/dwarfdump-test-zlib.cc @@ -22,6 +22,7 @@ int main() { // $ cp dwarfdump-test-zlib.cc /tmp/dbginfo // $ cd /tmp/dbginfo // $ clang++ -g dwarfdump-test-zlib.cc -Wl,--compress-debug-sections=zlib -o dwarfdump-test-zlib.elf-x86-64 +// $ clang++ -g dwarfdump-test-zlib.cc -Wa,--compress-debug-sections=zlib -c -o dwarfdump-test-zlib.o.elf-x86-64 // $ clang++ -g dwarfdump-test-zlib.cc -Wl,--compress-debug-sections=zlib-gnu -o dwarfdump-test-zlibgnu.elf-x86-64 // llvm-readobj -sections can be used to see that outputs really contain the compressed sections, also output in both -// cases is slightly smaller, that is because of compression.
\ No newline at end of file +// cases is slightly smaller, that is because of compression. diff --git a/test/DebugInfo/Inputs/dwarfdump-test-zlib.o.elf-x86-64 b/test/DebugInfo/Inputs/dwarfdump-test-zlib.o.elf-x86-64 Binary files differnew file mode 100644 index 000000000000..55f5cb0d157c --- /dev/null +++ b/test/DebugInfo/Inputs/dwarfdump-test-zlib.o.elf-x86-64 diff --git a/test/DebugInfo/MIR/ARM/split-superreg-complex.mir b/test/DebugInfo/MIR/ARM/split-superreg-complex.mir index 2e8d9977a649..0ebde3c1eb35 100644 --- a/test/DebugInfo/MIR/ARM/split-superreg-complex.mir +++ b/test/DebugInfo/MIR/ARM/split-superreg-complex.mir @@ -57,7 +57,7 @@ !17 = !{!18} !18 = !DISubrange(count: 4) !19 = !DILocation(line: 4, column: 13, scope: !9) - !20 = !DIExpression(DW_OP_plus, 1, DW_OP_minus, 1) + !20 = !DIExpression(DW_OP_plus_uconst, 1, DW_OP_constu, 1, DW_OP_minus) !21 = !DILocation(line: 4, column: 7, scope: !9) !22 = !DILocation(line: 5, column: 9, scope: !9) !23 = !DILocation(line: 5, column: 18, scope: !9) diff --git a/test/DebugInfo/PDB/Inputs/unknown-symbol.yaml b/test/DebugInfo/PDB/Inputs/unknown-symbol.yaml new file mode 100644 index 000000000000..a2966c437879 --- /dev/null +++ b/test/DebugInfo/PDB/Inputs/unknown-symbol.yaml @@ -0,0 +1,10 @@ +--- +DbiStream: + Modules: + - Module: unknown-symbol.yaml + Modi: + Records: + - Kind: S_ANNOTATION + UnknownSym: + Data: 123456789ABCDEF0 +... diff --git a/test/DebugInfo/PDB/pdb-unknown-symbol.test b/test/DebugInfo/PDB/pdb-unknown-symbol.test new file mode 100644 index 000000000000..3d2547ee51a9 --- /dev/null +++ b/test/DebugInfo/PDB/pdb-unknown-symbol.test @@ -0,0 +1,6 @@ +; RUN: llvm-pdbutil yaml2pdb -pdb=%t.pdb %p/Inputs/unknown-symbol.yaml +; RUN: llvm-pdbutil pdb2yaml -minimal -module-syms -no-file-headers %t.pdb | FileCheck %s + +CHECK: - Kind: S_ANNOTATION +CHECK: UnknownSym: +CHECK: Data: 123456789ABCDEF0 diff --git a/test/DebugInfo/PDB/pdb-yaml-types.test b/test/DebugInfo/PDB/pdb-yaml-types.test deleted file mode 100644 index f65d9edaa549..000000000000 --- a/test/DebugInfo/PDB/pdb-yaml-types.test +++ /dev/null @@ -1,74 +0,0 @@ -RUN: llvm-pdbutil pdb2yaml -tpi-stream %p/Inputs/big-read.pdb > %t.yaml -RUN: FileCheck -check-prefix=YAML %s < %t.yaml -RUN: llvm-pdbutil yaml2pdb %t.yaml -pdb %t.pdb -RUN: llvm-pdbutil raw -tpi-records %t.pdb | FileCheck %s --check-prefix=PDB - -Only verify the beginning of the type stream. - -YAML: TpiStream: -YAML-NEXT: Version: VC80 -YAML-NEXT: Records: -YAML-NEXT: - Kind: LF_ARGLIST -YAML-NEXT: ArgList: -YAML-NEXT: ArgIndices: [ ] -YAML-NEXT: - Kind: LF_PROCEDURE -YAML-NEXT: Procedure: -YAML-NEXT: ReturnType: 3 -YAML-NEXT: CallConv: NearC -YAML-NEXT: Options: [ None ] -YAML-NEXT: ParameterCount: 0 -YAML-NEXT: ArgumentList: 4096 -YAML-NEXT: - Kind: LF_PROCEDURE -YAML-NEXT: Procedure: -YAML-NEXT: ReturnType: 116 -YAML-NEXT: CallConv: NearC -YAML-NEXT: Options: [ None ] -YAML-NEXT: ParameterCount: 0 -YAML-NEXT: ArgumentList: 4096 - -This test is mostly checking to make sure we include the type index offset -table, and eventually hash codes. The type index offsets should be similar to -what are already present in big-read.pdb. - -PDB: Type Info Stream (TPI) { -PDB-NEXT: TPI Version: 20040203 -PDB-NEXT: Record count: 728 -PDB-NEXT: Records [ -PDB-NEXT: { -PDB-NEXT: ArgList (0x1000) { -PDB-NEXT: TypeLeafKind: LF_ARGLIST (0x1201) -PDB-NEXT: NumArgs: 0 -PDB-NEXT: Arguments [ -PDB-NEXT: ] -PDB-NEXT: } -PDB-NEXT: } -PDB-NEXT: { -PDB-NEXT: Procedure (0x1001) { -PDB-NEXT: TypeLeafKind: LF_PROCEDURE (0x1008) -PDB-NEXT: ReturnType: void (0x3) -PDB-NEXT: CallingConvention: NearC (0x0) -PDB-NEXT: FunctionOptions [ (0x0) -PDB-NEXT: ] -PDB-NEXT: NumParameters: 0 -PDB-NEXT: ArgListType: () (0x1000) -PDB-NEXT: } -PDB-NEXT: } -PDB-NEXT: { -PDB-NEXT: Procedure (0x1002) { -PDB-NEXT: TypeLeafKind: LF_PROCEDURE (0x1008) -PDB-NEXT: ReturnType: int (0x74) -PDB-NEXT: CallingConvention: NearC (0x0) -PDB-NEXT: FunctionOptions [ (0x0) -PDB-NEXT: ] -PDB-NEXT: NumParameters: 0 -PDB-NEXT: ArgListType: () (0x1000) -PDB-NEXT: } -PDB-NEXT: } -... -PDB: TypeIndexOffsets [ -PDB-NEXT: Index: 0x1000, Offset: 0 -PDB-NEXT: Index: 0x106c, Offset: 8,116 -PDB-NEXT: Index: 0x1118, Offset: 16,372 -PDB-NEXT: Index: 0x11df, Offset: 24,564 -PDB-NEXT: Index: 0x128e, Offset: 32,752 -PDB-NEXT: ] diff --git a/test/DebugInfo/PDB/pdbdump-debug-subsections.test b/test/DebugInfo/PDB/pdbdump-debug-subsections.test index 52f7bb52da2a..4338f11587ce 100644 --- a/test/DebugInfo/PDB/pdbdump-debug-subsections.test +++ b/test/DebugInfo/PDB/pdbdump-debug-subsections.test @@ -1,6 +1,5 @@ ; RUN: llvm-pdbutil yaml2pdb -pdb=%t.pdb %p/Inputs/debug-subsections.yaml ; RUN: llvm-pdbutil pdb2yaml -all -no-file-headers %t.pdb | FileCheck --check-prefix=YAML %s -; RUN: llvm-pdbutil raw -subsections=all %t.pdb | FileCheck --check-prefix=RAW %s YAML: Modules: YAML-NEXT: - Module: Foo.obj @@ -61,150 +60,7 @@ YAML-NEXT: EndDelta: 0 YAML-NEXT: Columns: YAML-NEXT: - !InlineeLines YAML-NEXT: HasExtraFiles: false -YAML-NEXT: Sites: +YAML-NEXT: Sites: YAML-NEXT: - FileName: 'f:\dd\externalapis\windows\10\sdk\inc\winerror.h' YAML-NEXT: LineNum: 26950 YAML-NEXT: Inlinee: 22767 - - -RAW: DBI Stream { -RAW: Modules [ -RAW-NEXT: { -RAW-NEXT: Name: Foo.obj -RAW: Subsections [ -RAW-NEXT: CrossModuleExports [ -RAW-NEXT: Export { -RAW-NEXT: Local: 0x12F4 -RAW-NEXT: Global: 0x2443 -RAW-NEXT: } -RAW-NEXT: Export { -RAW-NEXT: Local: 0x80001083 -RAW-NEXT: Global: 0x23A3 -RAW-NEXT: } -RAW-NEXT: ] -RAW-NEXT: ] -RAW-NEXT: } -RAW-NEXT: { -RAW-NEXT: Name: Bar.obj -RAW: Subsections [ -RAW-NEXT: CrossModuleExports [ -RAW-NEXT: Export { -RAW-NEXT: Local: 0x10A9 -RAW-NEXT: Global: 0x17D1 -RAW-NEXT: } -RAW-NEXT: Export { -RAW-NEXT: Local: 0x10C9 -RAW-NEXT: Global: 0x1245 -RAW-NEXT: } -RAW-NEXT: ] -RAW-NEXT: CrossModuleImports [ -RAW-NEXT: ModuleImport { -RAW-NEXT: Module: Foo.obj -RAW-NEXT: Imports: [0x12F4, 0x80001083] -RAW-NEXT: } -RAW-NEXT: ] -RAW-NEXT: ] -RAW-NEXT: } -RAW-NEXT: { -RAW-NEXT: Name: d:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj -RAW: Subsections [ -RAW-NEXT: FileChecksums { -RAW-NEXT: Checksum { -RAW-NEXT: FileName: d:\src\llvm\test\debuginfo\pdb\inputs\empty.cpp -RAW-NEXT: Kind: MD5 (0x1) -RAW-NEXT: Checksum ( -RAW-NEXT: 0000: A0A5BD0D 3ECD93FC 29D19DE8 26FBF4BC |....>...)...&...| -RAW-NEXT: ) -RAW-NEXT: } -RAW-NEXT: Checksum { -RAW-NEXT: FileName: f:\dd\externalapis\windows\10\sdk\inc\winerror.h -RAW-NEXT: Kind: MD5 (0x1) -RAW-NEXT: Checksum ( -RAW-NEXT: 0000: 1154D69F 5B265019 6E1FC34F 4134E56B |.T..[&P.n..OA4.k| -RAW-NEXT: ) -RAW-NEXT: } -RAW-NEXT: } -RAW-NEXT: Lines { -RAW-NEXT: RelocSegment: 1 -RAW-NEXT: RelocOffset: 100016 -RAW-NEXT: CodeSize: 10 -RAW-NEXT: HasColumns: No -RAW-NEXT: FileEntry { -RAW-NEXT: FileName: d:\src\llvm\test\debuginfo\pdb\inputs\empty.cpp -RAW-NEXT: Line { -RAW-NEXT: Offset: 0 -RAW-NEXT: LineNumberStart: 5 -RAW-NEXT: EndDelta: 0 -RAW-NEXT: IsStatement: Yes -RAW-NEXT: } -RAW-NEXT: Line { -RAW-NEXT: Offset: 3 -RAW-NEXT: LineNumberStart: 6 -RAW-NEXT: EndDelta: 0 -RAW-NEXT: IsStatement: Yes -RAW-NEXT: } -RAW-NEXT: Line { -RAW-NEXT: Offset: 8 -RAW-NEXT: LineNumberStart: 7 -RAW-NEXT: EndDelta: 0 -RAW-NEXT: IsStatement: Yes -RAW-NEXT: } -RAW-NEXT: } -RAW-NEXT: } -RAW-NEXT: InlineeLines { -RAW-NEXT: HasExtraFiles: No -RAW-NEXT: Lines [ -RAW-NEXT: Inlinee { -RAW-NEXT: FileName: f:\dd\externalapis\windows\10\sdk\inc\winerror.h -RAW-NEXT: Function { -RAW-NEXT: Index: 0x58ef (unknown function) -RAW-NEXT: } -RAW-NEXT: SourceLine: 26950 -RAW-NEXT: } -RAW-NEXT: ] -RAW-NEXT: } -RAW-NEXT: ] -RAW-NEXT: } -RAW-NEXT: { -RAW-NEXT: Name: ObjFileSubsections -RAW-NEXT: Debug Stream Index: 11 -RAW-NEXT: Object File Name: ObjFileSubsections -RAW-NEXT: Num Files: 0 -RAW-NEXT: Source File Name Idx: 0 -RAW-NEXT: Pdb File Name Idx: 0 -RAW-NEXT: Line Info Byte Size: 0 -RAW-NEXT: C13 Line Info Byte Size: 116 -RAW-NEXT: Symbol Byte Size: 4 -RAW-NEXT: Type Server Index: 0 -RAW-NEXT: Has EC Info: No -RAW-NEXT: Subsections [ -RAW-NEXT: String Table [ -RAW-NEXT: String1 -RAW-NEXT: String2 -RAW-NEXT: String3 -RAW-NEXT: ] -RAW-NEXT: Symbols [ -RAW-NEXT: { -RAW-NEXT: ObjectName { -RAW-NEXT: Signature: 0x0 -RAW-NEXT: ObjectName: ObjFileSubsections -RAW-NEXT: } -RAW-NEXT: } -RAW-NEXT: ] -RAW-NEXT: FrameData [ -RAW-NEXT: Frame { -RAW-NEXT: Rva: 6 -RAW-NEXT: CodeSize: 1 -RAW-NEXT: LocalSize: 2 -RAW-NEXT: ParamsSize: 4 -RAW-NEXT: MaxStackSize: 3 -RAW-NEXT: FrameFunc: MyFunc -RAW-NEXT: PrologSize: 5 -RAW-NEXT: SavedRegsSize: 7 -RAW-NEXT: Flags: 0 -RAW-NEXT: } -RAW-NEXT: ] -RAW-NEXT: ] -RAW-NEXT: } -RAW-NEXT: ] -RAW-NEXT: } diff --git a/test/DebugInfo/PDB/pdbdump-headers.test b/test/DebugInfo/PDB/pdbdump-headers.test index 82fe91dd20aa..fa9a25108fac 100644 --- a/test/DebugInfo/PDB/pdbdump-headers.test +++ b/test/DebugInfo/PDB/pdbdump-headers.test @@ -1,2901 +1,1082 @@ -; RUN: llvm-pdbutil raw -headers -string-table -tpi-records -tpi-record-bytes -module-syms \ -; RUN: -sym-record-bytes -globals -publics -module-files \ -; RUN: -stream-summary -stream-blocks -ipi-records -ipi-record-bytes \ -; RUN: -section-contribs -section-map -section-headers -subsections=all \ -; RUN: -tpi-hash -fpo -page-stats %p/Inputs/empty.pdb | FileCheck -check-prefix=EMPTY %s ; RUN: llvm-pdbutil raw -all %p/Inputs/empty.pdb | FileCheck -check-prefix=ALL %s -; RUN: llvm-pdbutil raw -headers -modules -module-files \ +; RUN: llvm-pdbutil raw -summary -modules -files \ ; RUN: %p/Inputs/big-read.pdb | FileCheck -check-prefix=BIG %s -; RUN: not llvm-pdbutil raw -headers %p/Inputs/bad-block-size.pdb 2>&1 | FileCheck -check-prefix=BAD-BLOCK-SIZE %s +; RUN: not llvm-pdbutil raw -summary %p/Inputs/bad-block-size.pdb 2>&1 | FileCheck -check-prefix=BAD-BLOCK-SIZE %s -; EMPTY: FileHeaders { -; EMPTY-NEXT: BlockSize: 4096 -; EMPTY-NEXT: FreeBlockMap: 2 -; EMPTY-NEXT: NumBlocks: 25 -; EMPTY-NEXT: NumDirectoryBytes: 136 -; EMPTY-NEXT: Unknown1: 0 -; EMPTY-NEXT: BlockMapAddr: 24 -; EMPTY-NEXT: NumDirectoryBlocks: 1 -; EMPTY-NEXT: DirectoryBlocks: [23] -; EMPTY-NEXT: NumStreams: 17 -; EMPTY-NEXT: } -; EMPTY-NEXT: Streams [ -; EMPTY-NEXT: Stream 0: [Old MSF Directory] (40 bytes) -; EMPTY-NEXT: Stream 1: [PDB Stream] (118 bytes) -; EMPTY-NEXT: Stream 2: [TPI Stream] (5392 bytes) -; EMPTY-NEXT: Stream 3: [DBI Stream] (739 bytes) -; EMPTY-NEXT: Stream 4: [IPI Stream] (784 bytes) -; EMPTY-NEXT: Stream 5: [Named Stream "/LinkInfo"] (0 bytes) -; EMPTY-NEXT: Stream 6: [Global Symbol Hash] (556 bytes) -; EMPTY-NEXT: Stream 7: [Public Symbol Hash] (604 bytes) -; EMPTY-NEXT: Stream 8: [Public Symbol Records] (104 bytes) -; EMPTY-NEXT: Stream 9: [Named Stream "/src/headerblock"] (0 bytes) -; EMPTY-NEXT: Stream 10: [Section Header Data] (160 bytes) -; EMPTY-NEXT: Stream 11: [New FPO Data] (32 bytes) -; EMPTY-NEXT: Stream 12: [Module "d:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj"] (308 bytes) -; EMPTY-NEXT: Stream 13: [Named Stream "/names"] (239 bytes) -; EMPTY-NEXT: Stream 14: [Module "* Linker *"] (520 bytes) -; EMPTY-NEXT: Stream 15: [TPI Hash] (308 bytes) -; EMPTY-NEXT: Stream 16: [IPI Hash] (68 bytes) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Msf Free Pages: [3, 4, 5, 8, 9] -; EMPTY-NEXT: Orphaned Pages: [] -; EMPTY-NEXT: Multiply Used Pages: [] -; EMPTY-NEXT: Use After Free Pages: [] -; EMPTY-NEXT: StreamBlocks [ -; EMPTY-NEXT: Stream 0: [8] -; EMPTY-NEXT: Stream 1: [19] -; EMPTY-NEXT: Stream 2: [18, 17] -; EMPTY-NEXT: Stream 3: [14] -; EMPTY-NEXT: Stream 4: [20] -; EMPTY-NEXT: Stream 5: [] -; EMPTY-NEXT: Stream 6: [11] -; EMPTY-NEXT: Stream 7: [13] -; EMPTY-NEXT: Stream 8: [12] -; EMPTY-NEXT: Stream 9: [] -; EMPTY-NEXT: Stream 10: [10] -; EMPTY-NEXT: Stream 11: [15] -; EMPTY-NEXT: Stream 12: [6] -; EMPTY-NEXT: Stream 13: [16] -; EMPTY-NEXT: Stream 14: [7] -; EMPTY-NEXT: Stream 15: [21] -; EMPTY-NEXT: Stream 16: [22] -; EMPTY-NEXT: ] -; EMPTY-NEXT: String Table { -; EMPTY-NEXT: 'd:\src\llvm\test\debuginfo\pdb\inputs\predefined c++ attributes (compiler internal)' -; EMPTY-NEXT: 'd:\src\llvm\test\debuginfo\pdb\inputs\empty.cpp' -; EMPTY-NEXT: '$T0 $ebp = $eip $T0 4 + ^ = $ebp $T0 ^ = $esp $T0 8 + = ' -; EMPTY-NEXT: } -; EMPTY-NEXT: PDB Stream { -; EMPTY-NEXT: Version: 20000404 -; EMPTY-NEXT: Signature: 0x54E507E2 -; EMPTY-NEXT: Age: 1 -; EMPTY-NEXT: Guid: {0B355641-86A0-A249-896F-9988FAE52FF0} -; EMPTY-NEXT: Features: 0x1 -; EMPTY-NEXT: Named Streams { -; EMPTY-NEXT: /names: 13 -; EMPTY-NEXT: /LinkInfo: 5 -; EMPTY-NEXT: /src/headerblock: 9 -; EMPTY-NEXT: } -; EMPTY-NEXT: } -; EMPTY-NEXT: Type Info Stream (TPI) { -; EMPTY-NEXT: TPI Version: 20040203 -; EMPTY-NEXT: Record count: 75 -; EMPTY-NEXT: Records [ -; EMPTY-NEXT: { -; EMPTY-NEXT: ArgList (0x1000) { -; EMPTY-NEXT: TypeLeafKind: LF_ARGLIST (0x1201) -; EMPTY-NEXT: NumArgs: 0 -; EMPTY-NEXT: Arguments [ -; EMPTY-NEXT: ] -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 00000000 |....| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: Procedure (0x1001) { -; EMPTY-NEXT: TypeLeafKind: LF_PROCEDURE (0x1008) -; EMPTY-NEXT: ReturnType: int (0x74) -; EMPTY-NEXT: CallingConvention: NearC (0x0) -; EMPTY-NEXT: FunctionOptions [ (0x0) -; EMPTY-NEXT: ] -; EMPTY-NEXT: NumParameters: 0 -; EMPTY-NEXT: ArgListType: () (0x1000) -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 74000000 00000000 00100000 |t...........| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: FieldList (0x1002) { -; EMPTY-NEXT: TypeLeafKind: LF_FIELDLIST (0x1203) -; EMPTY-NEXT: Enumerator { -; EMPTY-NEXT: TypeLeafKind: LF_ENUMERATE (0x1502) -; EMPTY-NEXT: AccessSpecifier: Public (0x3) -; EMPTY-NEXT: EnumValue: 1 -; EMPTY-NEXT: Name: apartment -; EMPTY-NEXT: } -; EMPTY-NEXT: Enumerator { -; EMPTY-NEXT: TypeLeafKind: LF_ENUMERATE (0x1502) -; EMPTY-NEXT: AccessSpecifier: Public (0x3) -; EMPTY-NEXT: EnumValue: 2 -; EMPTY-NEXT: Name: single -; EMPTY-NEXT: } -; EMPTY-NEXT: Enumerator { -; EMPTY-NEXT: TypeLeafKind: LF_ENUMERATE (0x1502) -; EMPTY-NEXT: AccessSpecifier: Public (0x3) -; EMPTY-NEXT: EnumValue: 3 -; EMPTY-NEXT: Name: free -; EMPTY-NEXT: } -; EMPTY-NEXT: Enumerator { -; EMPTY-NEXT: TypeLeafKind: LF_ENUMERATE (0x1502) -; EMPTY-NEXT: AccessSpecifier: Public (0x3) -; EMPTY-NEXT: EnumValue: 4 -; EMPTY-NEXT: Name: neutral -; EMPTY-NEXT: } -; EMPTY-NEXT: Enumerator { -; EMPTY-NEXT: TypeLeafKind: LF_ENUMERATE (0x1502) -; EMPTY-NEXT: AccessSpecifier: Public (0x3) -; EMPTY-NEXT: EnumValue: 5 -; EMPTY-NEXT: Name: both -; EMPTY-NEXT: } -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 02150300 01006170 6172746D 656E7400 |......apartment.| -; EMPTY-NEXT: 0010: 02150300 02007369 6E676C65 00F3F2F1 |......single....| -; EMPTY-NEXT: 0020: 02150300 03006672 656500F1 02150300 |......free......| -; EMPTY-NEXT: 0030: 04006E65 75747261 6C00F2F1 02150300 |..neutral.......| -; EMPTY-NEXT: 0040: 0500626F 746800F1 |..both..| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY: Hash { -; EMPTY-NEXT: Number of Hash Buckets: 262143 -; EMPTY-NEXT: Hash Key Size: 4 -; EMPTY-NEXT: Values: [205956, 163561, 59811, 208239, 16377, 247078, 194342, 254156, 194536, 167492, 185421, 119540, 261871, 198119, 48056, 251486, 134580, 148190, 113636, 53336, 55779, 220695, 198114, 148734, 81128, 60158, 217249, 174209, 159978, 249504, 141941, 238785, 6214, 94935, 151449, 135589, 73373, 96512, 254299, 17744, 239514, 173189, 130544, 204437, 238560, 144673, 115151, 197306, 256035, 101096, 231280, 52156, 48854, 170035, 177041, 102745, 16947, 183703, 98548, 35693, 171328, 203640, 139292, 49018, 43821, 202555, 165040, 215835, 142625, 52534, 44186, 103930, 110942, 17991, 213215] -; EMPTY-NEXT: Adjusters [ -; EMPTY-NEXT: ] -; EMPTY-NEXT: } -; EMPTY-NEXT: TypeIndexOffsets [ -; EMPTY-NEXT: Index: 0x1000, Offset: 0 -; EMPTY-NEXT: ] -; EMPTY: Type Info Stream (IPI) { -; EMPTY-NEXT: IPI Version: 20040203 -; EMPTY-NEXT: Record count: 15 -; EMPTY-NEXT: Records [ -; EMPTY-NEXT: { -; EMPTY-NEXT: UdtModSourceLine (0x1000) { -; EMPTY-NEXT: TypeLeafKind: LF_UDT_MOD_SRC_LINE (0x1607) -; EMPTY-NEXT: UDT: __vc_attributes::threadingAttribute (0x100B) -; EMPTY-NEXT: SourceFile: <unknown simple type> (0x1) -; EMPTY-NEXT: LineNumber: 481 -; EMPTY-NEXT: Module: 1 -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 0B100000 01000000 E1010000 0100F2F1 |................| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: UdtModSourceLine (0x1001) { -; EMPTY-NEXT: TypeLeafKind: LF_UDT_MOD_SRC_LINE (0x1607) -; EMPTY-NEXT: UDT: __vc_attributes::event_receiverAttribute (0x1017) -; EMPTY-NEXT: SourceFile: <unknown simple type> (0x1) -; EMPTY-NEXT: LineNumber: 194 -; EMPTY-NEXT: Module: 1 -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 17100000 01000000 C2000000 0100F2F1 |................| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: UdtModSourceLine (0x1002) { -; EMPTY-NEXT: TypeLeafKind: LF_UDT_MOD_SRC_LINE (0x1607) -; EMPTY-NEXT: UDT: __vc_attributes::aggregatableAttribute (0x1021) -; EMPTY-NEXT: SourceFile: <unknown simple type> (0x1) -; EMPTY-NEXT: LineNumber: 603 -; EMPTY-NEXT: Module: 1 -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 21100000 01000000 5B020000 0100F2F1 |!.......[.......| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: UdtModSourceLine (0x1003) { -; EMPTY-NEXT: TypeLeafKind: LF_UDT_MOD_SRC_LINE (0x1607) -; EMPTY-NEXT: UDT: __vc_attributes::event_sourceAttribute (0x102C) -; EMPTY-NEXT: SourceFile: <unknown simple type> (0x1) -; EMPTY-NEXT: LineNumber: 1200 -; EMPTY-NEXT: Module: 1 -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 2C100000 01000000 B0040000 0100F2F1 |,...............| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: UdtModSourceLine (0x1004) { -; EMPTY-NEXT: TypeLeafKind: LF_UDT_MOD_SRC_LINE (0x1607) -; EMPTY-NEXT: UDT: __vc_attributes::moduleAttribute (0x103A) -; EMPTY-NEXT: SourceFile: <unknown simple type> (0x1) -; EMPTY-NEXT: LineNumber: 540 -; EMPTY-NEXT: Module: 1 -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 3A100000 01000000 1C020000 0100F2F1 |:...............| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: UdtModSourceLine (0x1005) { -; EMPTY-NEXT: TypeLeafKind: LF_UDT_MOD_SRC_LINE (0x1607) -; EMPTY-NEXT: UDT: __vc_attributes::helper_attributes::usageAttribute (0x1042) -; EMPTY-NEXT: SourceFile: <unknown simple type> (0x1) -; EMPTY-NEXT: LineNumber: 108 -; EMPTY-NEXT: Module: 1 -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 42100000 01000000 6C000000 0100F2F1 |B.......l.......| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: UdtModSourceLine (0x1006) { -; EMPTY-NEXT: TypeLeafKind: LF_UDT_MOD_SRC_LINE (0x1607) -; EMPTY-NEXT: UDT: __vc_attributes::helper_attributes::v1_alttypeAttribute (0x104A) -; EMPTY-NEXT: SourceFile: <unknown simple type> (0x1) -; EMPTY-NEXT: LineNumber: 96 -; EMPTY-NEXT: Module: 1 -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 4A100000 01000000 60000000 0100F2F1 |J.......`.......| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: StringId (0x1007) { -; EMPTY-NEXT: TypeLeafKind: LF_STRING_ID (0x1605) -; EMPTY-NEXT: Id: 0x0 -; EMPTY-NEXT: StringData: d:\src\llvm\test\DebugInfo\PDB\Inputs -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 00000000 643A5C73 72635C6C 6C766D5C |....d:\src\llvm\| -; EMPTY-NEXT: 0010: 74657374 5C446562 7567496E 666F5C50 |test\DebugInfo\P| -; EMPTY-NEXT: 0020: 44425C49 6E707574 7300F2F1 |DB\Inputs...| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: StringId (0x1008) { -; EMPTY-NEXT: TypeLeafKind: LF_STRING_ID (0x1605) -; EMPTY-NEXT: Id: 0x0 -; EMPTY-NEXT: StringData: C:\Program Files (x86)\Microsoft Visual Studio 12.0\VC\BIN\cl.exe -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 00000000 433A5C50 726F6772 616D2046 |....C:\Program F| -; EMPTY-NEXT: 0010: 696C6573 20287838 36295C4D 6963726F |iles (x86)\Micro| -; EMPTY-NEXT: 0020: 736F6674 20566973 75616C20 53747564 |soft Visual Stud| -; EMPTY-NEXT: 0030: 696F2031 322E305C 56435C42 494E5C63 |io 12.0\VC\BIN\c| -; EMPTY-NEXT: 0040: 6C2E6578 6500F2F1 |l.exe...| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: StringId (0x1009) { -; EMPTY-NEXT: TypeLeafKind: LF_STRING_ID (0x1605) -; EMPTY-NEXT: Id: 0x0 -; EMPTY-NEXT: StringData: empty.cpp -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 00000000 656D7074 792E6370 7000F2F1 |....empty.cpp...| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: StringId (0x100A) { -; EMPTY-NEXT: TypeLeafKind: LF_STRING_ID (0x1605) -; EMPTY-NEXT: Id: 0x0 -; EMPTY-NEXT: StringData: d:\src\llvm\test\DebugInfo\PDB\Inputs\vc120.pdb -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 00000000 643A5C73 72635C6C 6C766D5C |....d:\src\llvm\| -; EMPTY-NEXT: 0010: 74657374 5C446562 7567496E 666F5C50 |test\DebugInfo\P| -; EMPTY-NEXT: 0020: 44425C49 6E707574 735C7663 3132302E |DB\Inputs\vc120.| -; EMPTY-NEXT: 0030: 70646200 |pdb.| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: StringId (0x100B) { -; EMPTY-NEXT: TypeLeafKind: LF_STRING_ID (0x1605) -; EMPTY-NEXT: Id: 0x0 -; EMPTY-NEXT: StringData: -Zi -MT -I"C:\Program Files (x86)\Microsoft Visual Studio 12.0\VC\INCLUDE" -I"C:\Program Files (x86)\Microsoft Visual Studio 12.0\VC\ATLMFC\INCLUDE" -I"C:\Program Files (x86)\Windows Kits\8.1\include\shared" -I"C:\Program Files (x86)\Windows -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 00000000 2D5A6920 2D4D5420 2D492243 |....-Zi -MT -I"C| -; EMPTY-NEXT: 0010: 3A5C5072 6F677261 6D204669 6C657320 |:\Program Files | -; EMPTY-NEXT: 0020: 28783836 295C4D69 63726F73 6F667420 |(x86)\Microsoft | -; EMPTY-NEXT: 0030: 56697375 616C2053 74756469 6F203132 |Visual Studio 12| -; EMPTY-NEXT: 0040: 2E305C56 435C494E 434C5544 4522202D |.0\VC\INCLUDE" -| -; EMPTY-NEXT: 0050: 4922433A 5C50726F 6772616D 2046696C |I"C:\Program Fil| -; EMPTY-NEXT: 0060: 65732028 78383629 5C4D6963 726F736F |es (x86)\Microso| -; EMPTY-NEXT: 0070: 66742056 69737561 6C205374 7564696F |ft Visual Studio| -; EMPTY-NEXT: 0080: 2031322E 305C5643 5C41544C 4D46435C | 12.0\VC\ATLMFC\| -; EMPTY-NEXT: 0090: 494E434C 55444522 202D4922 433A5C50 |INCLUDE" -I"C:\P| -; EMPTY-NEXT: 00A0: 726F6772 616D2046 696C6573 20287838 |rogram Files (x8| -; EMPTY-NEXT: 00B0: 36295C57 696E646F 7773204B 6974735C |6)\Windows Kits\| -; EMPTY-NEXT: 00C0: 382E315C 696E636C 7564655C 73686172 |8.1\include\shar| -; EMPTY-NEXT: 00D0: 65642220 2D492243 3A5C5072 6F677261 |ed" -I"C:\Progra| -; EMPTY-NEXT: 00E0: 6D204669 6C657320 28783836 295C5769 |m Files (x86)\Wi| -; EMPTY-NEXT: 00F0: 6E646F77 7300F2F1 |ndows...| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: StringList (0x100C) { -; EMPTY-NEXT: TypeLeafKind: LF_SUBSTR_LIST (0x1604) -; EMPTY-NEXT: NumStrings: 1 -; EMPTY-NEXT: Strings [ -; EMPTY-NEXT: String: -Zi -MT -I"C:\Program Files (x86)\Microsoft Visual Studio 12.0\VC\INCLUDE" -I"C:\Program Files (x86)\Microsoft Visual Studio 12.0\VC\ATLMFC\INCLUDE" -I"C:\Program Files (x86)\Windows Kits\8.1\include\shared" -I"C:\Program Files (x86)\Windows -; EMPTY-NEXT: ] -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 01000000 0B100000 |........| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: StringId (0x100D) { -; EMPTY-NEXT: TypeLeafKind: LF_STRING_ID (0x1605) -; EMPTY-NEXT: Id: "-Zi -MT -I"C:\Program Files (x86)\Microsoft Visual Studio 12.0\VC\INCLUDE" -I"C:\Program Files (x86)\Microsoft Visual Studio 12.0\VC\ATLMFC\INCLUDE" -I"C:\Program Files (x86)\Windows Kits\8.1\include\shared" -I"C:\Program Files (x86)\Windows" (0x100C) -; EMPTY-NEXT: StringData: Kits\8.1\include\um" -I"C:\Program Files (x86)\Windows Kits\8.1\include\winrt" -TP -X -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 0C100000 204B6974 735C382E 315C696E |.... Kits\8.1\in| -; EMPTY-NEXT: 0010: 636C7564 655C756D 22202D49 22433A5C |clude\um" -I"C:\| -; EMPTY-NEXT: 0020: 50726F67 72616D20 46696C65 73202878 |Program Files (x| -; EMPTY-NEXT: 0030: 3836295C 57696E64 6F777320 4B697473 |86)\Windows Kits| -; EMPTY-NEXT: 0040: 5C382E31 5C696E63 6C756465 5C77696E |\8.1\include\win| -; EMPTY-NEXT: 0050: 72742220 2D545020 2D5800F1 |rt" -TP -X..| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: BuildInfo (0x100E) { -; EMPTY-NEXT: TypeLeafKind: LF_BUILDINFO (0x1603) -; EMPTY-NEXT: NumArgs: 5 -; EMPTY-NEXT: Arguments [ -; EMPTY-NEXT: ArgType: d:\src\llvm\test\DebugInfo\PDB\Inputs (0x1007) -; EMPTY-NEXT: ArgType: C:\Program Files (x86)\Microsoft Visual Studio 12.0\VC\BIN\cl.exe (0x1008) -; EMPTY-NEXT: ArgType: empty.cpp (0x1009) -; EMPTY-NEXT: ArgType: d:\src\llvm\test\DebugInfo\PDB\Inputs\vc120.pdb (0x100A) -; EMPTY-NEXT: ArgType: Kits\8.1\include\um" -I"C:\Program Files (x86)\Windows Kits\8.1\include\winrt" -TP -X (0x100D) -; EMPTY-NEXT: ] -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 05000710 00000810 00000910 00000A10 |................| -; EMPTY-NEXT: 0010: 00000D10 0000F2F1 |........| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: TypeIndexOffsets [ -; EMPTY-NEXT: Index: 0x1000, Offset: 0 -; EMPTY-NEXT: ] -; EMPTY-NEXT: ] -; EMPTY-NEXT: } -; EMPTY: DBI Stream { -; EMPTY-NEXT: Dbi Version: 19990903 -; EMPTY-NEXT: Age: 1 -; EMPTY-NEXT: Incremental Linking: Yes -; EMPTY-NEXT: Has CTypes: No -; EMPTY-NEXT: Is Stripped: No -; EMPTY-NEXT: Machine Type: x86 -; EMPTY-NEXT: Symbol Record Stream Index: 8 -; EMPTY-NEXT: Public Symbol Stream Index: 7 -; EMPTY-NEXT: Global Symbol Stream Index: 6 -; EMPTY-NEXT: Toolchain Version: 12.0 -; EMPTY-NEXT: mspdb120.dll version: 12.0.31101 -; EMPTY-NEXT: Modules [ -; EMPTY-NEXT: { -; EMPTY-NEXT: Name: d:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj -; EMPTY-NEXT: Debug Stream Index: 12 -; EMPTY-NEXT: Object File Name: d:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj -; EMPTY-NEXT: Num Files: 1 -; EMPTY-NEXT: Source File Name Idx: 0 -; EMPTY-NEXT: Pdb File Name Idx: 0 -; EMPTY-NEXT: Line Info Byte Size: 0 -; EMPTY-NEXT: C13 Line Info Byte Size: 88 -; EMPTY-NEXT: Symbol Byte Size: 208 -; EMPTY-NEXT: Type Server Index: 0 -; EMPTY-NEXT: Has EC Info: No -; EMPTY-NEXT: 1 Contributing Source Files [ -; EMPTY-NEXT: d:\src\llvm\test\debuginfo\pdb\inputs\empty.cpp -; EMPTY-NEXT: ] -; EMPTY-NEXT: Symbols [ -; EMPTY-NEXT: { -; EMPTY-NEXT: ObjectName { -; EMPTY-NEXT: Signature: 0x0 -; EMPTY-NEXT: ObjectName: d:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 00000000 643A5C73 72635C6C 6C766D5C |....d:\src\llvm\| -; EMPTY-NEXT: 0010: 74657374 5C446562 7567496E 666F5C50 |test\DebugInfo\P| -; EMPTY-NEXT: 0020: 44425C49 6E707574 735C656D 7074792E |DB\Inputs\empty.| -; EMPTY-NEXT: 0030: 6F626A00 |obj.| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: CompilerFlags3 { -; EMPTY-NEXT: Language: Cpp (0x1) -; EMPTY-NEXT: Flags [ (0x2000) -; EMPTY-NEXT: SecurityChecks (0x2000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Machine: Pentium3 (0x7) -; EMPTY-NEXT: FrontendVersion: 18.0.31101.0 -; EMPTY-NEXT: BackendVersion: 18.0.31101.0 -; EMPTY-NEXT: VersionName: Microsoft (R) Optimizing Compiler -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 01200000 07001200 00007D79 00001200 |. ........}y....| -; EMPTY-NEXT: 0010: 00007D79 00004D69 63726F73 6F667420 |..}y..Microsoft | -; EMPTY-NEXT: 0020: 28522920 4F707469 6D697A69 6E672043 |(R) Optimizing C| -; EMPTY-NEXT: 0030: 6F6D7069 6C657200 |ompiler.| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: ProcStart { -; EMPTY-NEXT: Kind: S_GPROC32 (0x1110) -; EMPTY-NEXT: PtrParent: 0x0 -; EMPTY-NEXT: PtrEnd: 0xC4 -; EMPTY-NEXT: PtrNext: 0x0 -; EMPTY-NEXT: CodeSize: 0xA -; EMPTY-NEXT: DbgStart: 0x3 -; EMPTY-NEXT: DbgEnd: 0x8 -; EMPTY-NEXT: FunctionType: int () (0x1001) -; EMPTY-NEXT: Segment: 0x1 -; EMPTY-NEXT: Flags [ (0x1) -; EMPTY-NEXT: HasFP (0x1) -; EMPTY-NEXT: ] -; EMPTY-NEXT: DisplayName: main -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 00000000 C4000000 00000000 0A000000 |................| -; EMPTY-NEXT: 0010: 03000000 08000000 01100000 10000000 |................| -; EMPTY-NEXT: 0020: 0100016D 61696E00 |...main.| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: FrameProc { -; EMPTY-NEXT: TotalFrameBytes: 0x0 -; EMPTY-NEXT: PaddingFrameBytes: 0x0 -; EMPTY-NEXT: OffsetToPadding: 0x0 -; EMPTY-NEXT: BytesOfCalleeSavedRegisters: 0x0 -; EMPTY-NEXT: OffsetOfExceptionHandler: 0x0 -; EMPTY-NEXT: SectionIdOfExceptionHandler: 0x0 -; EMPTY-NEXT: Flags [ (0x128200) -; EMPTY-NEXT: AsynchronousExceptionHandling (0x200) -; EMPTY-NEXT: OptimizedForSpeed (0x100000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 00000000 00000000 00000000 00000000 |................| -; EMPTY-NEXT: 0010: 00000000 00000082 12000000 |............| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: BlockEnd { -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: BuildInfo { -; EMPTY-NEXT: BuildId: 4110 -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 0E100000 |....| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: ] -; EMPTY-NEXT: Subsections [ -; EMPTY-NEXT: Lines { -; EMPTY-NEXT: RelocSegment: 1 -; EMPTY-NEXT: RelocOffset: 16 -; EMPTY-NEXT: CodeSize: 10 -; EMPTY-NEXT: HasColumns: No -; EMPTY-NEXT: FileEntry { -; EMPTY-NEXT: FileName: d:\src\llvm\test\debuginfo\pdb\inputs\empty.cpp -; EMPTY-NEXT: Line { -; EMPTY-NEXT: Offset: 0 -; EMPTY-NEXT: LineNumberStart: 5 -; EMPTY-NEXT: EndDelta: 0 -; EMPTY-NEXT: IsStatement: Yes -; EMPTY-NEXT: } -; EMPTY-NEXT: Line { -; EMPTY-NEXT: Offset: 3 -; EMPTY-NEXT: LineNumberStart: 6 -; EMPTY-NEXT: EndDelta: 0 -; EMPTY-NEXT: IsStatement: Yes -; EMPTY-NEXT: } -; EMPTY-NEXT: Line { -; EMPTY-NEXT: Offset: 8 -; EMPTY-NEXT: LineNumberStart: 7 -; EMPTY-NEXT: EndDelta: 0 -; EMPTY-NEXT: IsStatement: Yes -; EMPTY-NEXT: } -; EMPTY-NEXT: } -; EMPTY-NEXT: } -; EMPTY-NEXT: FileChecksums { -; EMPTY-NEXT: Checksum { -; EMPTY-NEXT: FileName: d:\src\llvm\test\debuginfo\pdb\inputs\empty.cpp -; EMPTY-NEXT: Kind: MD5 (0x1) -; EMPTY-NEXT: Checksum ( -; EMPTY-NEXT: 0000: A0A5BD0D 3ECD93FC 29D19DE8 26FBF4BC |....>...)...&...| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: } -; EMPTY-NEXT: ] -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: Name: * Linker * -; EMPTY-NEXT: Debug Stream Index: 14 -; EMPTY-NEXT: Object File Name: -; EMPTY-NEXT: Num Files: 0 -; EMPTY-NEXT: Source File Name Idx: 0 -; EMPTY-NEXT: Pdb File Name Idx: 1 -; EMPTY-NEXT: Line Info Byte Size: 0 -; EMPTY-NEXT: C13 Line Info Byte Size: 0 -; EMPTY-NEXT: Symbol Byte Size: 516 -; EMPTY-NEXT: Type Server Index: 0 -; EMPTY-NEXT: Has EC Info: No -; EMPTY-NEXT: 0 Contributing Source Files [ -; EMPTY-NEXT: ] -; EMPTY-NEXT: Symbols [ -; EMPTY-NEXT: { -; EMPTY-NEXT: ObjectName { -; EMPTY-NEXT: Signature: 0x0 -; EMPTY-NEXT: ObjectName: * Linker * -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 00000000 2A204C69 6E6B6572 202A0000 |....* Linker *..| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: CompilerFlags3 { -; EMPTY-NEXT: Language: Link (0x7) -; EMPTY-NEXT: Flags [ (0x0) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Machine: Intel80386 (0x3) -; EMPTY-NEXT: FrontendVersion: 0.0.0.0 -; EMPTY-NEXT: BackendVersion: 12.0.31101.0 -; EMPTY-NEXT: VersionName: Microsoft (R) LINK -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 07000000 03000000 00000000 00000C00 |................| -; EMPTY-NEXT: 0010: 00007D79 00004D69 63726F73 6F667420 |..}y..Microsoft | -; EMPTY-NEXT: 0020: 28522920 4C494E4B 00000000 |(R) LINK....| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: EnvBlock { -; EMPTY-NEXT: Entries [ -; EMPTY-NEXT: cwd -; EMPTY-NEXT: d:\src\llvm\test\DebugInfo\PDB\Inputs -; EMPTY-NEXT: exe -; EMPTY-NEXT: C:\Program Files (x86)\Microsoft Visual Studio 12.0\VC\BIN\link.exe -; EMPTY-NEXT: pdb -; EMPTY-NEXT: d:\src\llvm\test\DebugInfo\PDB\Inputs\empty.pdb -; EMPTY-NEXT: ] -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 00637764 00643A5C 7372635C 6C6C766D |.cwd.d:\src\llvm| -; EMPTY-NEXT: 0010: 5C746573 745C4465 62756749 6E666F5C |\test\DebugInfo\| -; EMPTY-NEXT: 0020: 5044425C 496E7075 74730065 78650043 |PDB\Inputs.exe.C| -; EMPTY-NEXT: 0030: 3A5C5072 6F677261 6D204669 6C657320 |:\Program Files | -; EMPTY-NEXT: 0040: 28783836 295C4D69 63726F73 6F667420 |(x86)\Microsoft | -; EMPTY-NEXT: 0050: 56697375 616C2053 74756469 6F203132 |Visual Studio 12| -; EMPTY-NEXT: 0060: 2E305C56 435C4249 4E5C6C69 6E6B2E65 |.0\VC\BIN\link.e| -; EMPTY-NEXT: 0070: 78650070 64620064 3A5C7372 635C6C6C |xe.pdb.d:\src\ll| -; EMPTY-NEXT: 0080: 766D5C74 6573745C 44656275 67496E66 |vm\test\DebugInf| -; EMPTY-NEXT: 0090: 6F5C5044 425C496E 70757473 5C656D70 |o\PDB\Inputs\emp| -; EMPTY-NEXT: 00A0: 74792E70 64620000 |ty.pdb..| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: Trampoline { -; EMPTY-NEXT: Type: TrampIncremental (0x0) -; EMPTY-NEXT: Size: 5 -; EMPTY-NEXT: ThunkOff: 5 -; EMPTY-NEXT: TargetOff: 16 -; EMPTY-NEXT: ThunkSection: 1 -; EMPTY-NEXT: TargetSection: 1 -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 00000500 05000000 10000000 01000100 |................| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: Section { -; EMPTY-NEXT: SectionNumber: 1 -; EMPTY-NEXT: Alignment: 12 -; EMPTY-NEXT: Rva: 4096 -; EMPTY-NEXT: Length: 4122 -; EMPTY-NEXT: Characteristics [ (0x60000020) -; EMPTY-NEXT: IMAGE_SCN_CNT_CODE (0x20) -; EMPTY-NEXT: IMAGE_SCN_MEM_EXECUTE (0x20000000) -; EMPTY-NEXT: IMAGE_SCN_MEM_READ (0x40000000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Name: .text -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 01000C00 00100000 1A100000 20000060 |............ ..`| -; EMPTY-NEXT: 0010: 2E746578 74000000 |.text...| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: COFF Group { -; EMPTY-NEXT: Size: 4122 -; EMPTY-NEXT: Characteristics [ (0x60000020) -; EMPTY-NEXT: IMAGE_SCN_CNT_CODE (0x20) -; EMPTY-NEXT: IMAGE_SCN_MEM_EXECUTE (0x20000000) -; EMPTY-NEXT: IMAGE_SCN_MEM_READ (0x40000000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Offset: 0 -; EMPTY-NEXT: Segment: 1 -; EMPTY-NEXT: Name: .text$mn -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 1A100000 20000060 00000000 01002E74 |.... ..`.......t| -; EMPTY-NEXT: 0010: 65787424 6D6E0000 |ext$mn..| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: Section { -; EMPTY-NEXT: SectionNumber: 2 -; EMPTY-NEXT: Alignment: 12 -; EMPTY-NEXT: Rva: 12288 -; EMPTY-NEXT: Length: 690 -; EMPTY-NEXT: Characteristics [ (0x40000040) -; EMPTY-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA (0x40) -; EMPTY-NEXT: IMAGE_SCN_MEM_READ (0x40000000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Name: .rdata -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 02000C00 00300000 B2020000 40000040 |.....0......@..@| -; EMPTY-NEXT: 0010: 2E726461 74610000 |.rdata..| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: COFF Group { -; EMPTY-NEXT: Size: 323 -; EMPTY-NEXT: Characteristics [ (0x40000040) -; EMPTY-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA (0x40) -; EMPTY-NEXT: IMAGE_SCN_MEM_READ (0x40000000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Offset: 0 -; EMPTY-NEXT: Segment: 2 -; EMPTY-NEXT: Name: .rdata -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 43010000 40000040 00000000 02002E72 |C...@..@.......r| -; EMPTY-NEXT: 0010: 64617461 00000000 |data....| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: COFF Group { -; EMPTY-NEXT: Size: 0 -; EMPTY-NEXT: Characteristics [ (0x40000040) -; EMPTY-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA (0x40) -; EMPTY-NEXT: IMAGE_SCN_MEM_READ (0x40000000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Offset: 323 -; EMPTY-NEXT: Segment: 2 -; EMPTY-NEXT: Name: .edata -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 00000000 40000040 43010000 02002E65 |....@..@C......e| -; EMPTY-NEXT: 0010: 64617461 00000000 |data....| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: COFF Group { -; EMPTY-NEXT: Size: 366 -; EMPTY-NEXT: Characteristics [ (0x40000040) -; EMPTY-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA (0x40) -; EMPTY-NEXT: IMAGE_SCN_MEM_READ (0x40000000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Offset: 324 -; EMPTY-NEXT: Segment: 2 -; EMPTY-NEXT: Name: .rdata$debug -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 6E010000 40000040 44010000 02002E72 |n...@..@D......r| -; EMPTY-NEXT: 0010: 64617461 24646562 75670000 |data$debug..| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: Section { -; EMPTY-NEXT: SectionNumber: 3 -; EMPTY-NEXT: Alignment: 12 -; EMPTY-NEXT: Rva: 16384 -; EMPTY-NEXT: Length: 4 -; EMPTY-NEXT: Characteristics [ (0xC0000040) -; EMPTY-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA (0x40) -; EMPTY-NEXT: IMAGE_SCN_MEM_READ (0x40000000) -; EMPTY-NEXT: IMAGE_SCN_MEM_WRITE (0x80000000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Name: .data -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 03000C00 00400000 04000000 400000C0 |.....@......@...| -; EMPTY-NEXT: 0010: 2E646174 61000000 |.data...| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: COFF Group { -; EMPTY-NEXT: Size: 4 -; EMPTY-NEXT: Characteristics [ (0xC0000080) -; EMPTY-NEXT: IMAGE_SCN_CNT_UNINITIALIZED_DATA (0x80) -; EMPTY-NEXT: IMAGE_SCN_MEM_READ (0x40000000) -; EMPTY-NEXT: IMAGE_SCN_MEM_WRITE (0x80000000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Offset: 0 -; EMPTY-NEXT: Segment: 3 -; EMPTY-NEXT: Name: .bss -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 04000000 800000C0 00000000 03002E62 |...............b| -; EMPTY-NEXT: 0010: 73730000 |ss..| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: Section { -; EMPTY-NEXT: SectionNumber: 4 -; EMPTY-NEXT: Alignment: 12 -; EMPTY-NEXT: Rva: 20480 -; EMPTY-NEXT: Length: 8 -; EMPTY-NEXT: Characteristics [ (0x42000040) -; EMPTY-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA (0x40) -; EMPTY-NEXT: IMAGE_SCN_MEM_DISCARDABLE (0x2000000) -; EMPTY-NEXT: IMAGE_SCN_MEM_READ (0x40000000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Name: .reloc -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 04000C00 00500000 08000000 40000042 |.....P......@..B| -; EMPTY-NEXT: 0010: 2E72656C 6F630000 |.reloc..| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: ] -; EMPTY-NEXT: Subsections [ -; EMPTY-NEXT: ] -; EMPTY-NEXT: } -; EMPTY-NEXT: ] -; EMPTY-NEXT: } -; EMPTY-NEXT: Section Contributions [ -; EMPTY-NEXT: Contribution { -; EMPTY-NEXT: ISect: 1 -; EMPTY-NEXT: Off: 0 -; EMPTY-NEXT: Size: 10 -; EMPTY-NEXT: Characteristics [ (0x60000020) -; EMPTY-NEXT: IMAGE_SCN_CNT_CODE (0x20) -; EMPTY-NEXT: IMAGE_SCN_MEM_EXECUTE (0x20000000) -; EMPTY-NEXT: IMAGE_SCN_MEM_READ (0x40000000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Module { -; EMPTY-NEXT: Index: 1 -; EMPTY-NEXT: Name: * Linker * -; EMPTY-NEXT: } -; EMPTY-NEXT: Data CRC: 0 -; EMPTY-NEXT: Reloc CRC: 0 -; EMPTY-NEXT: } -; EMPTY-NEXT: Contribution { -; EMPTY-NEXT: ISect: 1 -; EMPTY-NEXT: Off: 16 -; EMPTY-NEXT: Size: 10 -; EMPTY-NEXT: Characteristics [ (0x60500020) -; EMPTY-NEXT: IMAGE_SCN_ALIGN_16BYTES (0x500000) -; EMPTY-NEXT: IMAGE_SCN_CNT_CODE (0x20) -; EMPTY-NEXT: IMAGE_SCN_MEM_EXECUTE (0x20000000) -; EMPTY-NEXT: IMAGE_SCN_MEM_READ (0x40000000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Module { -; EMPTY-NEXT: Index: 0 -; EMPTY-NEXT: Name: d:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj -; EMPTY-NEXT: } -; EMPTY-NEXT: Data CRC: 3617027124 -; EMPTY-NEXT: Reloc CRC: 0 -; EMPTY-NEXT: } -; EMPTY-NEXT: Contribution { -; EMPTY-NEXT: ISect: 2 -; EMPTY-NEXT: Off: 0 -; EMPTY-NEXT: Size: 56 -; EMPTY-NEXT: Characteristics [ (0x40000040) -; EMPTY-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA (0x40) -; EMPTY-NEXT: IMAGE_SCN_MEM_READ (0x40000000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Module { -; EMPTY-NEXT: Index: 1 -; EMPTY-NEXT: Name: * Linker * -; EMPTY-NEXT: } -; EMPTY-NEXT: Data CRC: 0 -; EMPTY-NEXT: Reloc CRC: 0 -; EMPTY-NEXT: } -; EMPTY-NEXT: Contribution { -; EMPTY-NEXT: ISect: 2 -; EMPTY-NEXT: Off: 324 -; EMPTY-NEXT: Size: 72 -; EMPTY-NEXT: Characteristics [ (0x40300040) -; EMPTY-NEXT: IMAGE_SCN_ALIGN_4BYTES (0x300000) -; EMPTY-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA (0x40) -; EMPTY-NEXT: IMAGE_SCN_MEM_READ (0x40000000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Module { -; EMPTY-NEXT: Index: 1 -; EMPTY-NEXT: Name: * Linker * -; EMPTY-NEXT: } -; EMPTY-NEXT: Data CRC: 0 -; EMPTY-NEXT: Reloc CRC: 0 -; EMPTY-NEXT: } -; EMPTY-NEXT: Contribution { -; EMPTY-NEXT: ISect: 2 -; EMPTY-NEXT: Off: 396 -; EMPTY-NEXT: Size: 20 -; EMPTY-NEXT: Characteristics [ (0x40300040) -; EMPTY-NEXT: IMAGE_SCN_ALIGN_4BYTES (0x300000) -; EMPTY-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA (0x40) -; EMPTY-NEXT: IMAGE_SCN_MEM_READ (0x40000000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Module { -; EMPTY-NEXT: Index: 1 -; EMPTY-NEXT: Name: * Linker * -; EMPTY-NEXT: } -; EMPTY-NEXT: Data CRC: 0 -; EMPTY-NEXT: Reloc CRC: 0 -; EMPTY-NEXT: } -; EMPTY-NEXT: Contribution { -; EMPTY-NEXT: ISect: 3 -; EMPTY-NEXT: Off: 0 -; EMPTY-NEXT: Size: 4 -; EMPTY-NEXT: Characteristics [ (0xC0300080) -; EMPTY-NEXT: IMAGE_SCN_ALIGN_4BYTES (0x300000) -; EMPTY-NEXT: IMAGE_SCN_CNT_UNINITIALIZED_DATA (0x80) -; EMPTY-NEXT: IMAGE_SCN_MEM_READ (0x40000000) -; EMPTY-NEXT: IMAGE_SCN_MEM_WRITE (0x80000000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Module { -; EMPTY-NEXT: Index: 0 -; EMPTY-NEXT: Name: d:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj -; EMPTY-NEXT: } -; EMPTY-NEXT: Data CRC: 0 -; EMPTY-NEXT: Reloc CRC: 0 -; EMPTY-NEXT: } -; EMPTY-NEXT: ] -; EMPTY-NEXT: Section Map [ -; EMPTY-NEXT: Entry { -; EMPTY-NEXT: Flags [ (0x10D) -; EMPTY-NEXT: AddressIs32Bit (0x8) -; EMPTY-NEXT: Execute (0x4) -; EMPTY-NEXT: IsSelector (0x100) -; EMPTY-NEXT: Read (0x1) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Ovl: 0 -; EMPTY-NEXT: Group: 0 -; EMPTY-NEXT: Frame: 1 -; EMPTY-NEXT: SecName: 65535 -; EMPTY-NEXT: ClassName: 65535 -; EMPTY-NEXT: Offset: 0 -; EMPTY-NEXT: SecByteLength: 4122 -; EMPTY-NEXT: } -; EMPTY-NEXT: Entry { -; EMPTY-NEXT: Flags [ (0x109) -; EMPTY-NEXT: AddressIs32Bit (0x8) -; EMPTY-NEXT: IsSelector (0x100) -; EMPTY-NEXT: Read (0x1) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Ovl: 0 -; EMPTY-NEXT: Group: 0 -; EMPTY-NEXT: Frame: 2 -; EMPTY-NEXT: SecName: 65535 -; EMPTY-NEXT: ClassName: 65535 -; EMPTY-NEXT: Offset: 0 -; EMPTY-NEXT: SecByteLength: 690 -; EMPTY-NEXT: } -; EMPTY-NEXT: Entry { -; EMPTY-NEXT: Flags [ (0x10B) -; EMPTY-NEXT: AddressIs32Bit (0x8) -; EMPTY-NEXT: IsSelector (0x100) -; EMPTY-NEXT: Read (0x1) -; EMPTY-NEXT: Write (0x2) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Ovl: 0 -; EMPTY-NEXT: Group: 0 -; EMPTY-NEXT: Frame: 3 -; EMPTY-NEXT: SecName: 65535 -; EMPTY-NEXT: ClassName: 65535 -; EMPTY-NEXT: Offset: 0 -; EMPTY-NEXT: SecByteLength: 4 -; EMPTY-NEXT: } -; EMPTY-NEXT: Entry { -; EMPTY-NEXT: Flags [ (0x109) -; EMPTY-NEXT: AddressIs32Bit (0x8) -; EMPTY-NEXT: IsSelector (0x100) -; EMPTY-NEXT: Read (0x1) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Ovl: 0 -; EMPTY-NEXT: Group: 0 -; EMPTY-NEXT: Frame: 4 -; EMPTY-NEXT: SecName: 65535 -; EMPTY-NEXT: ClassName: 65535 -; EMPTY-NEXT: Offset: 0 -; EMPTY-NEXT: SecByteLength: 8 -; EMPTY-NEXT: } -; EMPTY-NEXT: Entry { -; EMPTY-NEXT: Flags [ (0x208) -; EMPTY-NEXT: AddressIs32Bit (0x8) -; EMPTY-NEXT: IsAbsoluteAddress (0x200) -; EMPTY-NEXT: ] -; EMPTY-NEXT: Ovl: 0 -; EMPTY-NEXT: Group: 0 -; EMPTY-NEXT: Frame: 0 -; EMPTY-NEXT: SecName: 65535 -; EMPTY-NEXT: ClassName: 65535 -; EMPTY-NEXT: Offset: 0 -; EMPTY-NEXT: SecByteLength: 4294967295 -; EMPTY-NEXT: } -; EMPTY-NEXT: ] -; EMPTY-NEXT: Globals Stream { -; EMPTY-NEXT: Stream number: 6 -; EMPTY-NEXT: Number of buckets: 2 -; EMPTY-NEXT: Hash Buckets: [0, 12] -; EMPTY-NEXT: } -; EMPTY-NEXT: Publics Stream { -; EMPTY-NEXT: Stream number: 7 -; EMPTY-NEXT: SymHash: 556 -; EMPTY-NEXT: AddrMap: 8 -; EMPTY-NEXT: Number of buckets: 2 -; EMPTY-NEXT: Hash Buckets: [0, 12] -; EMPTY-NEXT: Address Map: [36, 0] -; EMPTY-NEXT: Thunk Map: [4112] -; EMPTY-NEXT: Section Offsets: [4096, 1] -; EMPTY-NEXT: Symbols [ -; EMPTY-NEXT: { -; EMPTY-NEXT: PublicSym { -; EMPTY-NEXT: Type: 0 -; EMPTY-NEXT: Seg: 3 -; EMPTY-NEXT: Off: 0 -; EMPTY-NEXT: Name: ?__purecall@@3PAXA -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 00000000 00000000 03003F5F 5F707572 |..........?__pur| -; EMPTY-NEXT: 0010: 6563616C 6C404033 50415841 00000000 |ecall@@3PAXA....| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: PublicSym { -; EMPTY-NEXT: Type: 2 -; EMPTY-NEXT: Seg: 1 -; EMPTY-NEXT: Off: 16 -; EMPTY-NEXT: Name: _main -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 02000000 10000000 01005F6D 61696E00 |.........._main.| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: ProcRef { -; EMPTY-NEXT: SumName: 0 -; EMPTY-NEXT: SymOffset: 120 -; EMPTY-NEXT: Mod: 1 -; EMPTY-NEXT: Name: main -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 00000000 78000000 01006D61 696E0000 |....x.....main..| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: DataSym { -; EMPTY-NEXT: Kind: S_GDATA32 (0x110D) -; EMPTY-NEXT: Type: void* (0x403) -; EMPTY-NEXT: DisplayName: __purecall -; EMPTY-NEXT: } -; EMPTY-NEXT: Bytes ( -; EMPTY-NEXT: 0000: 03040000 00000000 03005F5F 70757265 |..........__pure| -; EMPTY-NEXT: 0010: 63616C6C 00000000 |call....| -; EMPTY-NEXT: ) -; EMPTY-NEXT: } -; EMPTY-NEXT: ] -; EMPTY-NEXT: } -; EMPTY-NEXT: Section Headers [ -; EMPTY-NEXT: { -; EMPTY-NEXT: Name: .text -; EMPTY-NEXT: Virtual Size: 4122 -; EMPTY-NEXT: Virtual Address: 4096 -; EMPTY-NEXT: Size of Raw Data: 4608 -; EMPTY-NEXT: File Pointer to Raw Data: 1024 -; EMPTY-NEXT: File Pointer to Relocations: 0 -; EMPTY-NEXT: File Pointer to Linenumbers: 0 -; EMPTY-NEXT: Number of Relocations: 0 -; EMPTY-NEXT: Number of Linenumbers: 0 -; EMPTY-NEXT: Characteristics [ (0x60000020) -; EMPTY-NEXT: IMAGE_SCN_CNT_CODE (0x20) -; EMPTY-NEXT: IMAGE_SCN_MEM_EXECUTE (0x20000000) -; EMPTY-NEXT: IMAGE_SCN_MEM_READ (0x40000000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: Name: .rdata -; EMPTY-NEXT: Virtual Size: 690 -; EMPTY-NEXT: Virtual Address: 12288 -; EMPTY-NEXT: Size of Raw Data: 1024 -; EMPTY-NEXT: File Pointer to Raw Data: 5632 -; EMPTY-NEXT: File Pointer to Relocations: 0 -; EMPTY-NEXT: File Pointer to Linenumbers: 0 -; EMPTY-NEXT: Number of Relocations: 0 -; EMPTY-NEXT: Number of Linenumbers: 0 -; EMPTY-NEXT: Characteristics [ (0x40000040) -; EMPTY-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA (0x40) -; EMPTY-NEXT: IMAGE_SCN_MEM_READ (0x40000000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: Name: .data -; EMPTY-NEXT: Virtual Size: 4 -; EMPTY-NEXT: Virtual Address: 16384 -; EMPTY-NEXT: Size of Raw Data: 0 -; EMPTY-NEXT: File Pointer to Raw Data: 0 -; EMPTY-NEXT: File Pointer to Relocations: 0 -; EMPTY-NEXT: File Pointer to Linenumbers: 0 -; EMPTY-NEXT: Number of Relocations: 0 -; EMPTY-NEXT: Number of Linenumbers: 0 -; EMPTY-NEXT: Characteristics [ (0xC0000040) -; EMPTY-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA (0x40) -; EMPTY-NEXT: IMAGE_SCN_MEM_READ (0x40000000) -; EMPTY-NEXT: IMAGE_SCN_MEM_WRITE (0x80000000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: Name: .reloc -; EMPTY-NEXT: Virtual Size: 8 -; EMPTY-NEXT: Virtual Address: 20480 -; EMPTY-NEXT: Size of Raw Data: 512 -; EMPTY-NEXT: File Pointer to Raw Data: 6656 -; EMPTY-NEXT: File Pointer to Relocations: 0 -; EMPTY-NEXT: File Pointer to Linenumbers: 0 -; EMPTY-NEXT: Number of Relocations: 0 -; EMPTY-NEXT: Number of Linenumbers: 0 -; EMPTY-NEXT: Characteristics [ (0x42000040) -; EMPTY-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA (0x40) -; EMPTY-NEXT: IMAGE_SCN_MEM_DISCARDABLE (0x2000000) -; EMPTY-NEXT: IMAGE_SCN_MEM_READ (0x40000000) -; EMPTY-NEXT: ] -; EMPTY-NEXT: } -; EMPTY-NEXT: ] -; EMPTY: New FPO [ -; EMPTY-NEXT: { -; EMPTY-NEXT: Offset: 4112 -; EMPTY-NEXT: Size: 10 -; EMPTY-NEXT: Number of locals: 0 -; EMPTY-NEXT: Number of params: 0 -; EMPTY-NEXT: Size of Prolog: 0 -; EMPTY-NEXT: Number of Saved Registers: 0 -; EMPTY-NEXT: Has SEH: No -; EMPTY-NEXT: Use BP: No -; EMPTY-NEXT: Frame Pointer: 0 -; EMPTY-NEXT: } -; EMPTY-NEXT: { -; EMPTY-NEXT: Offset: 0 -; EMPTY-NEXT: Size: 134 -; EMPTY-NEXT: Number of locals: 3 -; EMPTY-NEXT: Number of params: 4 -; EMPTY-NEXT: Size of Prolog: 0 -; EMPTY-NEXT: Number of Saved Registers: 0 -; EMPTY-NEXT: Has SEH: No -; EMPTY-NEXT: Use BP: No -; EMPTY-NEXT: Frame Pointer: 0 -; EMPTY-NEXT: } -; EMPTY-NEXT: ] +ALL: Summary +ALL-NEXT: ============================================================ +ALL-NEXT: Block Size: 4096 +ALL-NEXT: Number of blocks: 25 +ALL-NEXT: Number of streams: 17 +ALL-NEXT: Signature: 1424295906 +ALL-NEXT: Age: 1 +ALL-NEXT: GUID: {0B355641-86A0-A249-896F-9988FAE52FF0} +ALL-NEXT: Features: 0x1 +ALL-NEXT: Has Debug Info: true +ALL-NEXT: Has Types: true +ALL-NEXT: Has IDs: true +ALL-NEXT: Has Globals: true +ALL-NEXT: Has Publics: true +ALL-NEXT: Is incrementally linked: true +ALL-NEXT: Has conflicting types: false +ALL-NEXT: Is stripped: false +ALL: Streams +ALL-NEXT: ============================================================ +ALL-NEXT: Stream 0: [Old MSF Directory] (40 bytes) +ALL-NEXT: Stream 1: [PDB Stream] (118 bytes) +ALL-NEXT: Stream 2: [TPI Stream] (5392 bytes) +ALL-NEXT: Stream 3: [DBI Stream] (739 bytes) +ALL-NEXT: Stream 4: [IPI Stream] (784 bytes) +ALL-NEXT: Stream 5: [Named Stream "/LinkInfo"] (0 bytes) +ALL-NEXT: Stream 6: [Global Symbol Hash] (556 bytes) +ALL-NEXT: Stream 7: [Public Symbol Hash] (604 bytes) +ALL-NEXT: Stream 8: [Public Symbol Records] (104 bytes) +ALL-NEXT: Stream 9: [Named Stream "/src/headerblock"] (0 bytes) +ALL-NEXT: Stream 10: [Section Header Data] (160 bytes) +ALL-NEXT: Stream 11: [New FPO Data] (32 bytes) +ALL-NEXT: Stream 12: [Module "d:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj"] (308 bytes) +ALL-NEXT: Stream 13: [Named Stream "/names"] (239 bytes) +ALL-NEXT: Stream 14: [Module "* Linker *"] (520 bytes) +ALL-NEXT: Stream 15: [TPI Hash] (308 bytes) +ALL-NEXT: Stream 16: [IPI Hash] (68 bytes) +ALL: String Table +ALL-NEXT: ============================================================ +ALL-NEXT: ID | String +ALL-NEXT: 1 | 'd:\src\llvm\test\debuginfo\pdb\inputs\predefined c++ attributes (compiler internal)' +ALL-NEXT: 86 | 'd:\src\llvm\test\debuginfo\pdb\inputs\empty.cpp' +ALL-NEXT: 134 | '$T0 $ebp = $eip $T0 4 + ^ = $ebp $T0 ^ = $esp $T0 8 + = ' +ALL: Modules +ALL-NEXT: ============================================================ +ALL-NEXT: Mod 0000 | Name: `d:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj`: +ALL-NEXT: Obj: `d:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj`: +ALL-NEXT: debug stream: 12, # files: 1, has ec info: false +ALL-NEXT: Mod 0001 | Name: `* Linker *`: +ALL-NEXT: Obj: ``: +ALL-NEXT: debug stream: 14, # files: 0, has ec info: false +ALL: Files +ALL-NEXT: ============================================================ +ALL-NEXT: Mod 0000 | `d:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj`: +ALL-NEXT: - (MD5: A0A5BD0D3ECD93FC29D19DE826FBF4BC) d:\src\llvm\test\debuginfo\pdb\inputs\empty.cpp +ALL-NEXT: Mod 0001 | `* Linker *`: +ALL: Lines +ALL-NEXT: ============================================================ +ALL-NEXT: Mod 0000 | `d:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj`: +ALL-NEXT: d:\src\llvm\test\debuginfo\pdb\inputs\empty.cpp (MD5: A0A5BD0D3ECD93FC29D19DE826FBF4BC) +ALL-NEXT: 0001:00000010-0000001A, line/addr entries = 3 +ALL-NEXT: 5 00000010 6 00000013 7 00000018 +ALL: Mod 0001 | `* Linker *`: +ALL: Inlinee Lines +ALL-NEXT: ============================================================ +ALL-NEXT: Mod 0000 | `d:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj`: +ALL-NEXT: Mod 0001 | `* Linker *`: +ALL: Types (TPI Stream) +ALL-NEXT: ============================================================ +ALL-NEXT: Showing 75 records +ALL-NEXT: 0x1000 | LF_ARGLIST [size = 8, hash = 205956] +ALL-NEXT: 0x1001 | LF_PROCEDURE [size = 16, hash = 163561] +ALL-NEXT: return type = 0x0074 (int), # args = 0, param list = 0x1000 +ALL-NEXT: calling conv = cdecl, options = None +ALL-NEXT: 0x1002 | LF_FIELDLIST [size = 76, hash = 59811] +ALL-NEXT: - LF_ENUMERATE [apartment = 1] +ALL-NEXT: - LF_ENUMERATE [single = 2] +ALL-NEXT: - LF_ENUMERATE [free = 3] +ALL-NEXT: - LF_ENUMERATE [neutral = 4] +ALL-NEXT: - LF_ENUMERATE [both = 5] +ALL-NEXT: 0x1003 | LF_ENUM [size = 120, hash = 208239] +ALL-NEXT: name: `__vc_attributes::threadingAttribute::threading_e` +ALL-NEXT: unique name: `.?AW4threading_e@threadingAttribute@__vc_attributes@@` +ALL-NEXT: field list: 0x1002, underlying type: 0x0074 (int) +ALL-NEXT: options: has unique name | is nested +ALL-NEXT: 0x1004 | LF_STRUCTURE [size = 100, hash = 16377] +ALL-NEXT: class name: `__vc_attributes::threadingAttribute` +ALL-NEXT: unique name: `.?AUthreadingAttribute@__vc_attributes@@` +ALL-NEXT: vtable: <no type>, base list: <no type>, field list: <no type> +ALL-NEXT: options: forward ref | has unique name +ALL-NEXT: 0x1005 | LF_POINTER [size = 12, hash = 247078] +ALL-NEXT: referent = 0x1004, mode = pointer, opts = const, kind = ptr32 +ALL-NEXT: 0x1006 | LF_ARGLIST [size = 12, hash = 194342] +ALL-NEXT: 0x1003: `__vc_attributes::threadingAttribute::threading_e` +ALL-NEXT: 0x1007 | LF_MFUNCTION [size = 28, hash = 254156] +ALL-NEXT: return type = 1, # args = 0x1006, param list = 0x0003 (void) +ALL-NEXT: class type = 0x1004, this type = 0x1005, this adjust = 0 +ALL-NEXT: calling conv = thiscall, options = constructor +ALL-NEXT: 0x1008 | LF_MFUNCTION [size = 28, hash = 194536] +ALL-NEXT: return type = 0, # args = 0x1000, param list = 0x0003 (void) +ALL-NEXT: class type = 0x1004, this type = 0x1005, this adjust = 0 +ALL-NEXT: calling conv = thiscall, options = constructor +ALL-NEXT: 0x1009 | LF_METHODLIST [size = 20, hash = 167492] +ALL-NEXT: - Method [type = 0x1007, vftable offset = -1, attrs = public] +ALL-NEXT: - Method [type = 0x1008, vftable offset = -1, attrs = public] +ALL-NEXT: 0x100A | LF_FIELDLIST [size = 68, hash = 185421] +ALL-NEXT: - LF_NESTTYPE [name = `threading_e`, parent = 0x1003] +ALL-NEXT: - LF_METHOD [name = `threadingAttribute`, # overloads = 2, overload list = 0x1009] +ALL-NEXT: - LF_MEMBER [name = `value`, Type = 0x1003, offset = 0, attrs = public] +ALL-NEXT: 0x100B | LF_STRUCTURE [size = 100, hash = 119540] +ALL-NEXT: class name: `__vc_attributes::threadingAttribute` +ALL-NEXT: unique name: `.?AUthreadingAttribute@__vc_attributes@@` +ALL-NEXT: vtable: <no type>, base list: <no type>, field list: 0x100A +ALL-NEXT: options: has ctor / dtor | contains nested class | has unique name +ALL-NEXT: 0x100C | LF_FIELDLIST [size = 48, hash = 261871] +ALL-NEXT: - LF_ENUMERATE [native = 0] +ALL-NEXT: - LF_ENUMERATE [com = 1] +ALL-NEXT: - LF_ENUMERATE [managed = 2] +ALL-NEXT: 0x100D | LF_ENUM [size = 120, hash = 198119] +ALL-NEXT: name: `__vc_attributes::event_receiverAttribute::type_e` +ALL-NEXT: unique name: `.?AW4type_e@event_receiverAttribute@__vc_attributes@@` +ALL-NEXT: field list: 0x100C, underlying type: 0x0074 (int) +ALL-NEXT: options: has unique name | is nested +ALL-NEXT: 0x100E | LF_STRUCTURE [size = 112, hash = 48056] +ALL-NEXT: class name: `__vc_attributes::event_receiverAttribute` +ALL-NEXT: unique name: `.?AUevent_receiverAttribute@__vc_attributes@@` +ALL-NEXT: vtable: <no type>, base list: <no type>, field list: <no type> +ALL-NEXT: options: forward ref | has unique name +ALL-NEXT: 0x100F | LF_POINTER [size = 12, hash = 251486] +ALL-NEXT: referent = 0x100E, mode = pointer, opts = const, kind = ptr32 +ALL-NEXT: 0x1010 | LF_ARGLIST [size = 16, hash = 134580] +ALL-NEXT: 0x100D: `__vc_attributes::event_receiverAttribute::type_e` +ALL-NEXT: 0x0030 (bool): `bool` +ALL-NEXT: 0x1011 | LF_MFUNCTION [size = 28, hash = 148190] +ALL-NEXT: return type = 2, # args = 0x1010, param list = 0x0003 (void) +ALL-NEXT: class type = 0x100E, this type = 0x100F, this adjust = 0 +ALL-NEXT: calling conv = thiscall, options = constructor +ALL-NEXT: 0x1012 | LF_ARGLIST [size = 12, hash = 113636] +ALL-NEXT: 0x100D: `__vc_attributes::event_receiverAttribute::type_e` +ALL-NEXT: 0x1013 | LF_MFUNCTION [size = 28, hash = 53336] +ALL-NEXT: return type = 1, # args = 0x1012, param list = 0x0003 (void) +ALL-NEXT: class type = 0x100E, this type = 0x100F, this adjust = 0 +ALL-NEXT: calling conv = thiscall, options = constructor +ALL-NEXT: 0x1014 | LF_MFUNCTION [size = 28, hash = 55779] +ALL-NEXT: return type = 0, # args = 0x1000, param list = 0x0003 (void) +ALL-NEXT: class type = 0x100E, this type = 0x100F, this adjust = 0 +ALL-NEXT: calling conv = thiscall, options = constructor +ALL-NEXT: 0x1015 | LF_METHODLIST [size = 28, hash = 220695] +ALL-NEXT: - Method [type = 0x1011, vftable offset = -1, attrs = public] +ALL-NEXT: - Method [type = 0x1013, vftable offset = -1, attrs = public] +ALL-NEXT: - Method [type = 0x1014, vftable offset = -1, attrs = public] +ALL-NEXT: 0x1016 | LF_FIELDLIST [size = 96, hash = 198114] +ALL-NEXT: - LF_NESTTYPE [name = `type_e`, parent = 0x100D] +ALL-NEXT: - LF_METHOD [name = `event_receiverAttribute`, # overloads = 3, overload list = 0x1015] +ALL-NEXT: - LF_MEMBER [name = `type`, Type = 0x100D, offset = 0, attrs = public] +ALL-NEXT: - LF_MEMBER [name = `layout_dependent`, Type = 0x0030 (bool), offset = 4, attrs = public] +ALL-NEXT: 0x1017 | LF_STRUCTURE [size = 112, hash = 148734] +ALL-NEXT: class name: `__vc_attributes::event_receiverAttribute` +ALL-NEXT: unique name: `.?AUevent_receiverAttribute@__vc_attributes@@` +ALL-NEXT: vtable: <no type>, base list: <no type>, field list: 0x1016 +ALL-NEXT: options: has ctor / dtor | contains nested class | has unique name +ALL-NEXT: 0x1018 | LF_FIELDLIST [size = 48, hash = 81128] +ALL-NEXT: - LF_ENUMERATE [never = 0] +ALL-NEXT: - LF_ENUMERATE [allowed = 1] +ALL-NEXT: - LF_ENUMERATE [always = 2] +ALL-NEXT: 0x1019 | LF_ENUM [size = 116, hash = 60158] +ALL-NEXT: name: `__vc_attributes::aggregatableAttribute::type_e` +ALL-NEXT: unique name: `.?AW4type_e@aggregatableAttribute@__vc_attributes@@` +ALL-NEXT: field list: 0x1018, underlying type: 0x0074 (int) +ALL-NEXT: options: has unique name | is nested +ALL-NEXT: 0x101A | LF_STRUCTURE [size = 108, hash = 217249] +ALL-NEXT: class name: `__vc_attributes::aggregatableAttribute` +ALL-NEXT: unique name: `.?AUaggregatableAttribute@__vc_attributes@@` +ALL-NEXT: vtable: <no type>, base list: <no type>, field list: <no type> +ALL-NEXT: options: forward ref | has unique name +ALL-NEXT: 0x101B | LF_POINTER [size = 12, hash = 174209] +ALL-NEXT: referent = 0x101A, mode = pointer, opts = const, kind = ptr32 +ALL-NEXT: 0x101C | LF_ARGLIST [size = 12, hash = 159978] +ALL-NEXT: 0x1019: `__vc_attributes::aggregatableAttribute::type_e` +ALL-NEXT: 0x101D | LF_MFUNCTION [size = 28, hash = 249504] +ALL-NEXT: return type = 1, # args = 0x101C, param list = 0x0003 (void) +ALL-NEXT: class type = 0x101A, this type = 0x101B, this adjust = 0 +ALL-NEXT: calling conv = thiscall, options = constructor +ALL-NEXT: 0x101E | LF_MFUNCTION [size = 28, hash = 141941] +ALL-NEXT: return type = 0, # args = 0x1000, param list = 0x0003 (void) +ALL-NEXT: class type = 0x101A, this type = 0x101B, this adjust = 0 +ALL-NEXT: calling conv = thiscall, options = constructor +ALL-NEXT: 0x101F | LF_METHODLIST [size = 20, hash = 238785] +ALL-NEXT: - Method [type = 0x101D, vftable offset = -1, attrs = public] +ALL-NEXT: - Method [type = 0x101E, vftable offset = -1, attrs = public] +ALL-NEXT: 0x1020 | LF_FIELDLIST [size = 68, hash = 6214] +ALL-NEXT: - LF_NESTTYPE [name = `type_e`, parent = 0x1019] +ALL-NEXT: - LF_METHOD [name = `aggregatableAttribute`, # overloads = 2, overload list = 0x101F] +ALL-NEXT: - LF_MEMBER [name = `type`, Type = 0x1019, offset = 0, attrs = public] +ALL-NEXT: 0x1021 | LF_STRUCTURE [size = 108, hash = 94935] +ALL-NEXT: class name: `__vc_attributes::aggregatableAttribute` +ALL-NEXT: unique name: `.?AUaggregatableAttribute@__vc_attributes@@` +ALL-NEXT: vtable: <no type>, base list: <no type>, field list: 0x1020 +ALL-NEXT: options: has ctor / dtor | contains nested class | has unique name +ALL-NEXT: 0x1022 | LF_ENUM [size = 116, hash = 151449] +ALL-NEXT: name: `__vc_attributes::event_sourceAttribute::type_e` +ALL-NEXT: unique name: `.?AW4type_e@event_sourceAttribute@__vc_attributes@@` +ALL-NEXT: field list: 0x100C, underlying type: 0x0074 (int) +ALL-NEXT: options: has unique name | is nested +ALL-NEXT: 0x1023 | LF_FIELDLIST [size = 28, hash = 135589] +ALL-NEXT: - LF_ENUMERATE [speed = 0] +ALL-NEXT: - LF_ENUMERATE [size = 1] +ALL-NEXT: 0x1024 | LF_ENUM [size = 124, hash = 73373] +ALL-NEXT: name: `__vc_attributes::event_sourceAttribute::optimize_e` +ALL-NEXT: unique name: `.?AW4optimize_e@event_sourceAttribute@__vc_attributes@@` +ALL-NEXT: field list: 0x1023, underlying type: 0x0074 (int) +ALL-NEXT: options: has unique name | is nested +ALL-NEXT: 0x1025 | LF_STRUCTURE [size = 108, hash = 96512] +ALL-NEXT: class name: `__vc_attributes::event_sourceAttribute` +ALL-NEXT: unique name: `.?AUevent_sourceAttribute@__vc_attributes@@` +ALL-NEXT: vtable: <no type>, base list: <no type>, field list: <no type> +ALL-NEXT: options: forward ref | has unique name +ALL-NEXT: 0x1026 | LF_POINTER [size = 12, hash = 254299] +ALL-NEXT: referent = 0x1025, mode = pointer, opts = const, kind = ptr32 +ALL-NEXT: 0x1027 | LF_ARGLIST [size = 12, hash = 17744] +ALL-NEXT: 0x1022: `__vc_attributes::event_sourceAttribute::type_e` +ALL-NEXT: 0x1028 | LF_MFUNCTION [size = 28, hash = 239514] +ALL-NEXT: return type = 1, # args = 0x1027, param list = 0x0003 (void) +ALL-NEXT: class type = 0x1025, this type = 0x1026, this adjust = 0 +ALL-NEXT: calling conv = thiscall, options = constructor +ALL-NEXT: 0x1029 | LF_MFUNCTION [size = 28, hash = 173189] +ALL-NEXT: return type = 0, # args = 0x1000, param list = 0x0003 (void) +ALL-NEXT: class type = 0x1025, this type = 0x1026, this adjust = 0 +ALL-NEXT: calling conv = thiscall, options = constructor +ALL-NEXT: 0x102A | LF_METHODLIST [size = 20, hash = 130544] +ALL-NEXT: - Method [type = 0x1028, vftable offset = -1, attrs = public] +ALL-NEXT: - Method [type = 0x1029, vftable offset = -1, attrs = public] +ALL-NEXT: 0x102B | LF_FIELDLIST [size = 128, hash = 204437] +ALL-NEXT: - LF_NESTTYPE [name = `type_e`, parent = 0x1022] +ALL-NEXT: - LF_NESTTYPE [name = `optimize_e`, parent = 0x1024] +ALL-NEXT: - LF_METHOD [name = `event_sourceAttribute`, # overloads = 2, overload list = 0x102A] +ALL-NEXT: - LF_MEMBER [name = `type`, Type = 0x1022, offset = 0, attrs = public] +ALL-NEXT: - LF_MEMBER [name = `optimize`, Type = 0x1024, offset = 4, attrs = public] +ALL-NEXT: - LF_MEMBER [name = `decorate`, Type = 0x0030 (bool), offset = 8, attrs = public] +ALL-NEXT: 0x102C | LF_STRUCTURE [size = 108, hash = 238560] +ALL-NEXT: class name: `__vc_attributes::event_sourceAttribute` +ALL-NEXT: unique name: `.?AUevent_sourceAttribute@__vc_attributes@@` +ALL-NEXT: vtable: <no type>, base list: <no type>, field list: 0x102B +ALL-NEXT: options: has ctor / dtor | contains nested class | has unique name +ALL-NEXT: 0x102D | LF_FIELDLIST [size = 92, hash = 144673] +ALL-NEXT: - LF_ENUMERATE [dll = 1] +ALL-NEXT: - LF_ENUMERATE [exe = 2] +ALL-NEXT: - LF_ENUMERATE [service = 3] +ALL-NEXT: - LF_ENUMERATE [unspecified = 4] +ALL-NEXT: - LF_ENUMERATE [EXE = 2] +ALL-NEXT: - LF_ENUMERATE [SERVICE = 3] +ALL-NEXT: 0x102E | LF_ENUM [size = 104, hash = 115151] +ALL-NEXT: name: `__vc_attributes::moduleAttribute::type_e` +ALL-NEXT: unique name: `.?AW4type_e@moduleAttribute@__vc_attributes@@` +ALL-NEXT: field list: 0x102D, underlying type: 0x0074 (int) +ALL-NEXT: options: has unique name | is nested +ALL-NEXT: 0x102F | LF_STRUCTURE [size = 96, hash = 197306] +ALL-NEXT: class name: `__vc_attributes::moduleAttribute` +ALL-NEXT: unique name: `.?AUmoduleAttribute@__vc_attributes@@` +ALL-NEXT: vtable: <no type>, base list: <no type>, field list: <no type> +ALL-NEXT: options: forward ref | has unique name +ALL-NEXT: 0x1030 | LF_POINTER [size = 12, hash = 256035] +ALL-NEXT: referent = 0x102F, mode = pointer, opts = const, kind = ptr32 +ALL-NEXT: 0x1031 | LF_MODIFIER [size = 12, hash = 101096] +ALL-NEXT: referent = 0x0070 (char), modifiers = const +ALL-NEXT: 0x1032 | LF_POINTER [size = 12, hash = 231280] +ALL-NEXT: referent = 0x1031, mode = pointer, opts = None, kind = ptr32 +ALL-NEXT: 0x1033 | LF_ARGLIST [size = 68, hash = 52156] +ALL-NEXT: 0x102E: `__vc_attributes::moduleAttribute::type_e` +ALL-NEXT: 0x1032: `const char*` +ALL-NEXT: 0x1032: `const char*` +ALL-NEXT: 0x1032: `const char*` +ALL-NEXT: 0x0074 (int): `int` +ALL-NEXT: 0x0030 (bool): `bool` +ALL-NEXT: 0x1032: `const char*` +ALL-NEXT: 0x0074 (int): `int` +ALL-NEXT: 0x1032: `const char*` +ALL-NEXT: 0x1032: `const char*` +ALL-NEXT: 0x0074 (int): `int` +ALL-NEXT: 0x0030 (bool): `bool` +ALL-NEXT: 0x0030 (bool): `bool` +ALL-NEXT: 0x1032: `const char*` +ALL-NEXT: 0x1032: `const char*` +ALL-NEXT: 0x1034 | LF_MFUNCTION [size = 28, hash = 48854] +ALL-NEXT: return type = 15, # args = 0x1033, param list = 0x0003 (void) +ALL-NEXT: class type = 0x102F, this type = 0x1030, this adjust = 0 +ALL-NEXT: calling conv = thiscall, options = constructor +ALL-NEXT: 0x1035 | LF_ARGLIST [size = 12, hash = 170035] +ALL-NEXT: 0x102E: `__vc_attributes::moduleAttribute::type_e` +ALL-NEXT: 0x1036 | LF_MFUNCTION [size = 28, hash = 177041] +ALL-NEXT: return type = 1, # args = 0x1035, param list = 0x0003 (void) +ALL-NEXT: class type = 0x102F, this type = 0x1030, this adjust = 0 +ALL-NEXT: calling conv = thiscall, options = constructor +ALL-NEXT: 0x1037 | LF_MFUNCTION [size = 28, hash = 102745] +ALL-NEXT: return type = 0, # args = 0x1000, param list = 0x0003 (void) +ALL-NEXT: class type = 0x102F, this type = 0x1030, this adjust = 0 +ALL-NEXT: calling conv = thiscall, options = constructor +ALL-NEXT: 0x1038 | LF_METHODLIST [size = 28, hash = 16947] +ALL-NEXT: - Method [type = 0x1034, vftable offset = -1, attrs = public] +ALL-NEXT: - Method [type = 0x1036, vftable offset = -1, attrs = public] +ALL-NEXT: - Method [type = 0x1037, vftable offset = -1, attrs = public] +ALL-NEXT: 0x1039 | LF_FIELDLIST [size = 356, hash = 183703] +ALL-NEXT: - LF_NESTTYPE [name = `type_e`, parent = 0x102E] +ALL-NEXT: - LF_METHOD [name = `moduleAttribute`, # overloads = 3, overload list = 0x1038] +ALL-NEXT: - LF_MEMBER [name = `type`, Type = 0x102E, offset = 0, attrs = public] +ALL-NEXT: - LF_MEMBER [name = `name`, Type = 0x1032, offset = 4, attrs = public] +ALL-NEXT: - LF_MEMBER [name = `version`, Type = 0x1032, offset = 8, attrs = public] +ALL-NEXT: - LF_MEMBER [name = `uuid`, Type = 0x1032, offset = 12, attrs = public] +ALL-NEXT: - LF_MEMBER [name = `lcid`, Type = 0x0074 (int), offset = 16, attrs = public] +ALL-NEXT: - LF_MEMBER [name = `control`, Type = 0x0030 (bool), offset = 20, attrs = public] +ALL-NEXT: - LF_MEMBER [name = `helpstring`, Type = 0x1032, offset = 24, attrs = public] +ALL-NEXT: - LF_MEMBER [name = `helpstringcontext`, Type = 0x0074 (int), offset = 28, attrs = public] +ALL-NEXT: - LF_MEMBER [name = `helpstringdll`, Type = 0x1032, offset = 32, attrs = public] +ALL-NEXT: - LF_MEMBER [name = `helpfile`, Type = 0x1032, offset = 36, attrs = public] +ALL-NEXT: - LF_MEMBER [name = `helpcontext`, Type = 0x0074 (int), offset = 40, attrs = public] +ALL-NEXT: - LF_MEMBER [name = `hidden`, Type = 0x0030 (bool), offset = 44, attrs = public] +ALL-NEXT: - LF_MEMBER [name = `restricted`, Type = 0x0030 (bool), offset = 45, attrs = public] +ALL-NEXT: - LF_MEMBER [name = `custom`, Type = 0x1032, offset = 48, attrs = public] +ALL-NEXT: - LF_MEMBER [name = `resource_name`, Type = 0x1032, offset = 52, attrs = public] +ALL-NEXT: 0x103A | LF_STRUCTURE [size = 96, hash = 98548] +ALL-NEXT: class name: `__vc_attributes::moduleAttribute` +ALL-NEXT: unique name: `.?AUmoduleAttribute@__vc_attributes@@` +ALL-NEXT: vtable: <no type>, base list: <no type>, field list: 0x1039 +ALL-NEXT: options: has ctor / dtor | contains nested class | has unique name +ALL-NEXT: 0x103B | LF_FIELDLIST [size = 756, hash = 35693] +ALL-NEXT: - LF_ENUMERATE [eAnyUsage = 0] +ALL-NEXT: - LF_ENUMERATE [eCoClassUsage = 1] +ALL-NEXT: - LF_ENUMERATE [eCOMInterfaceUsage = 2] +ALL-NEXT: - LF_ENUMERATE [eInterfaceUsage = 6] +ALL-NEXT: - LF_ENUMERATE [eMemberUsage = 8] +ALL-NEXT: - LF_ENUMERATE [eMethodUsage = 16] +ALL-NEXT: - LF_ENUMERATE [eInterfaceMethodUsage = 32] +ALL-NEXT: - LF_ENUMERATE [eInterfaceMemberUsage = 64] +ALL-NEXT: - LF_ENUMERATE [eCoClassMemberUsage = 128] +ALL-NEXT: - LF_ENUMERATE [eCoClassMethodUsage = 256] +ALL-NEXT: - LF_ENUMERATE [eGlobalMethodUsage = 768] +ALL-NEXT: - LF_ENUMERATE [eGlobalDataUsage = 1024] +ALL-NEXT: - LF_ENUMERATE [eClassUsage = 2048] +ALL-NEXT: - LF_ENUMERATE [eInterfaceParameterUsage = 4096] +ALL-NEXT: - LF_ENUMERATE [eMethodParameterUsage = 12288] +ALL-NEXT: - LF_ENUMERATE [eIDLModuleUsage = 16384] +ALL-NEXT: - LF_ENUMERATE [eAnonymousUsage = 32768] +ALL-NEXT: - LF_ENUMERATE [eTypedefUsage = 65536] +ALL-NEXT: - LF_ENUMERATE [eUnionUsage = 131072] +ALL-NEXT: - LF_ENUMERATE [eEnumUsage = 262144] +ALL-NEXT: - LF_ENUMERATE [eDefineTagUsage = 524288] +ALL-NEXT: - LF_ENUMERATE [eStructUsage = 1048576] +ALL-NEXT: - LF_ENUMERATE [eLocalUsage = 2097152] +ALL-NEXT: - LF_ENUMERATE [ePropertyUsage = 4194304] +ALL-NEXT: - LF_ENUMERATE [eEventUsage = 8388608] +ALL-NEXT: - LF_ENUMERATE [eTemplateUsage = 16777216] +ALL-NEXT: - LF_ENUMERATE [eModuleUsage = 16777216] +ALL-NEXT: - LF_ENUMERATE [eIllegalUsage = 33554432] +ALL-NEXT: - LF_ENUMERATE [eAsynchronousUsage = 67108864] +ALL-NEXT: - LF_ENUMERATE [eAnyIDLUsage = 4161535] +ALL-NEXT: 0x103C | LF_ENUM [size = 140, hash = 171328] +ALL-NEXT: name: `__vc_attributes::helper_attributes::usageAttribute::usage_e` +ALL-NEXT: unique name: `.?AW4usage_e@usageAttribute@helper_attributes@__vc_attributes@@` +ALL-NEXT: field list: 0x103B, underlying type: 0x0074 (int) +ALL-NEXT: options: has unique name | is nested +ALL-NEXT: 0x103D | LF_STRUCTURE [size = 128, hash = 203640] +ALL-NEXT: class name: `__vc_attributes::helper_attributes::usageAttribute` +ALL-NEXT: unique name: `.?AUusageAttribute@helper_attributes@__vc_attributes@@` +ALL-NEXT: vtable: <no type>, base list: <no type>, field list: <no type> +ALL-NEXT: options: forward ref | has unique name +ALL-NEXT: 0x103E | LF_POINTER [size = 12, hash = 139292] +ALL-NEXT: referent = 0x103D, mode = pointer, opts = const, kind = ptr32 +ALL-NEXT: 0x103F | LF_ARGLIST [size = 12, hash = 49018] +ALL-NEXT: 0x0075 (unsigned): `unsigned` +ALL-NEXT: 0x1040 | LF_MFUNCTION [size = 28, hash = 43821] +ALL-NEXT: return type = 1, # args = 0x103F, param list = 0x0003 (void) +ALL-NEXT: class type = 0x103D, this type = 0x103E, this adjust = 0 +ALL-NEXT: calling conv = thiscall, options = constructor +ALL-NEXT: 0x1041 | LF_FIELDLIST [size = 60, hash = 202555] +ALL-NEXT: - LF_NESTTYPE [name = `usage_e`, parent = 0x103C] +ALL-NEXT: - LF_ONEMETHOD [name = `usageAttribute`] +ALL-NEXT: type = 0x1040, vftable offset = -1, attrs = public +ALL-NEXT: - LF_MEMBER [name = `value`, Type = 0x0075 (unsigned), offset = 0, attrs = public] +ALL-NEXT: 0x1042 | LF_STRUCTURE [size = 128, hash = 165040] +ALL-NEXT: class name: `__vc_attributes::helper_attributes::usageAttribute` +ALL-NEXT: unique name: `.?AUusageAttribute@helper_attributes@__vc_attributes@@` +ALL-NEXT: vtable: <no type>, base list: <no type>, field list: 0x1041 +ALL-NEXT: options: has ctor / dtor | contains nested class | has unique name +ALL-NEXT: 0x1043 | LF_FIELDLIST [size = 68, hash = 215835] +ALL-NEXT: - LF_ENUMERATE [eBoolean = 0] +ALL-NEXT: - LF_ENUMERATE [eInteger = 1] +ALL-NEXT: - LF_ENUMERATE [eFloat = 2] +ALL-NEXT: - LF_ENUMERATE [eDouble = 3] +ALL-NEXT: 0x1044 | LF_ENUM [size = 148, hash = 142625] +ALL-NEXT: name: `__vc_attributes::helper_attributes::v1_alttypeAttribute::type_e` +ALL-NEXT: unique name: `.?AW4type_e@v1_alttypeAttribute@helper_attributes@__vc_attributes@@` +ALL-NEXT: field list: 0x1043, underlying type: 0x0074 (int) +ALL-NEXT: options: has unique name | is nested +ALL-NEXT: 0x1045 | LF_STRUCTURE [size = 140, hash = 52534] +ALL-NEXT: class name: `__vc_attributes::helper_attributes::v1_alttypeAttribute` +ALL-NEXT: unique name: `.?AUv1_alttypeAttribute@helper_attributes@__vc_attributes@@` +ALL-NEXT: vtable: <no type>, base list: <no type>, field list: <no type> +ALL-NEXT: options: forward ref | has unique name +ALL-NEXT: 0x1046 | LF_POINTER [size = 12, hash = 44186] +ALL-NEXT: referent = 0x1045, mode = pointer, opts = const, kind = ptr32 +ALL-NEXT: 0x1047 | LF_ARGLIST [size = 12, hash = 103930] +ALL-NEXT: 0x1044: `__vc_attributes::helper_attributes::v1_alttypeAttribute::type_e` +ALL-NEXT: 0x1048 | LF_MFUNCTION [size = 28, hash = 110942] +ALL-NEXT: return type = 1, # args = 0x1047, param list = 0x0003 (void) +ALL-NEXT: class type = 0x1045, this type = 0x1046, this adjust = 0 +ALL-NEXT: calling conv = thiscall, options = constructor +ALL-NEXT: 0x1049 | LF_FIELDLIST [size = 64, hash = 17991] +ALL-NEXT: - LF_NESTTYPE [name = `type_e`, parent = 0x1044] +ALL-NEXT: - LF_ONEMETHOD [name = `v1_alttypeAttribute`] +ALL-NEXT: type = 0x1048, vftable offset = -1, attrs = public +ALL-NEXT: - LF_MEMBER [name = `type`, Type = 0x1044, offset = 0, attrs = public] +ALL-NEXT: 0x104A | LF_STRUCTURE [size = 140, hash = 213215] +ALL-NEXT: class name: `__vc_attributes::helper_attributes::v1_alttypeAttribute` +ALL-NEXT: unique name: `.?AUv1_alttypeAttribute@helper_attributes@__vc_attributes@@` +ALL-NEXT: vtable: <no type>, base list: <no type>, field list: 0x1049 +ALL-NEXT: options: has ctor / dtor | contains nested class | has unique name +ALL: Type Index Offsets: +ALL-NEXT: TI: 0x1000, Offset: 0 +ALL: Hash Adjusters: +ALL: Types (IPI Stream) +ALL-NEXT: ============================================================ +ALL-NEXT: Showing 15 records +ALL-NEXT: 0x1000 | LF_UDT_MOD_SRC_LINE [size = 20, hash = 7186] +ALL-NEXT: udt = 0x100B, mod = 1, file = 1, line = 481 +ALL-NEXT: 0x1001 | LF_UDT_MOD_SRC_LINE [size = 20, hash = 7198] +ALL-NEXT: udt = 0x1017, mod = 1, file = 1, line = 194 +ALL-NEXT: 0x1002 | LF_UDT_MOD_SRC_LINE [size = 20, hash = 7180] +ALL-NEXT: udt = 0x1021, mod = 1, file = 1, line = 603 +ALL-NEXT: 0x1003 | LF_UDT_MOD_SRC_LINE [size = 20, hash = 7191] +ALL-NEXT: udt = 0x102C, mod = 1, file = 1, line = 1200 +ALL-NEXT: 0x1004 | LF_UDT_MOD_SRC_LINE [size = 20, hash = 7201] +ALL-NEXT: udt = 0x103A, mod = 1, file = 1, line = 540 +ALL-NEXT: 0x1005 | LF_UDT_MOD_SRC_LINE [size = 20, hash = 7241] +ALL-NEXT: udt = 0x1042, mod = 1, file = 1, line = 108 +ALL-NEXT: 0x1006 | LF_UDT_MOD_SRC_LINE [size = 20, hash = 7249] +ALL-NEXT: udt = 0x104A, mod = 1, file = 1, line = 96 +ALL-NEXT: 0x1007 | LF_STRING_ID [size = 48, hash = 80727] ID: <no type>, String: d:\src\llvm\test\DebugInfo\PDB\Inputs +ALL-NEXT: 0x1008 | LF_STRING_ID [size = 76, hash = 154177] ID: <no type>, String: C:\Program Files (x86)\Microsoft Visual Studio 12.0\VC\BIN\cl.exe +ALL-NEXT: 0x1009 | LF_STRING_ID [size = 20, hash = 75189] ID: <no type>, String: empty.cpp +ALL-NEXT: 0x100A | LF_STRING_ID [size = 56, hash = 253662] ID: <no type>, String: d:\src\llvm\test\DebugInfo\PDB\Inputs\vc120.pdb +ALL-NEXT: 0x100B | LF_STRING_ID [size = 252, hash = 193467] ID: <no type>, String: -Zi -MT -I"C:\Program Files (x86)\Microsoft Visual Studio 12.0\VC\INCLUDE" -I"C:\Program Files (x86)\Microsoft Visual Studio 12.0\VC\ATLMFC\INCLUDE" -I"C:\Program Files (x86)\Windows Kits\8.1\include\shared" -I"C:\Program Files (x86)\Windows +ALL-NEXT: 0x100C | LF_SUBSTR_LIST [size = 12, hash = 222705] +ALL-NEXT: 0x100B: `-Zi -MT -I"C:\Program Files (x86)\Microsoft Visual Studio 12.0\VC\INCLUDE" -I"C:\Program Files (x86)\Microsoft Visual Studio 12.0\VC\ATLMFC\INCLUDE" -I"C:\Program Files (x86)\Windows Kits\8.1\include\shared" -I"C:\Program Files (x86)\Windows` +ALL-NEXT: 0x100D | LF_STRING_ID [size = 96, hash = 186099] ID: 0x100C, String: Kits\8.1\include\um" -I"C:\Program Files (x86)\Windows Kits\8.1\include\winrt" -TP -X +ALL-NEXT: 0x100E | LF_BUILDINFO [size = 28, hash = 257108] +ALL-NEXT: 0x1007: `d:\src\llvm\test\DebugInfo\PDB\Inputs` +ALL-NEXT: 0x1008: `C:\Program Files (x86)\Microsoft Visual Studio 12.0\VC\BIN\cl.exe` +ALL-NEXT: 0x1009: `empty.cpp` +ALL-NEXT: 0x100A: `d:\src\llvm\test\DebugInfo\PDB\Inputs\vc120.pdb` +ALL-NEXT: 0x100D: ` Kits\8.1\include\um" -I"C:\Program Files (x86)\Windows Kits\8.1\include\winrt" -TP -X` +ALL: Type Index Offsets: +ALL-NEXT: TI: 0x1000, Offset: 0 +ALL: Hash Adjusters: +ALL: Public Symbols +ALL-NEXT: ============================================================ +ALL-NEXT: - S_PUB32 [size = 36] `?__purecall@@3PAXA` +ALL-NEXT: type = <no type>, addr = 0003:0000 +ALL-NEXT: - S_PUB32 [size = 20] `_main` +ALL-NEXT: type = 0x0002 (<unknown simple type>), addr = 0001:0016 +ALL-NEXT: - S_PROCREF [size = 20] `main` +ALL-NEXT: module = 1, sum name = 0, offset = 120 +ALL-NEXT: - S_GDATA32 [size = 28] `__purecall` +ALL-NEXT: type = 0x0403 (void*), addr = 0003:0000 +ALL: Symbols +ALL-NEXT: ============================================================ +ALL-NEXT: Mod 0000 | `d:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj`: +ALL-NEXT: - S_OBJNAME [size = 56] sig=0, `d:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj` +ALL-NEXT: - S_COMPILE3 [size = 60] +ALL-NEXT: machine = intel pentium 3, Ver = Microsoft (R) Optimizing Compiler, language = c++ +ALL-NEXT: frontend = 18.0.31101.0, backend = 18.0.31101.0 +ALL-NEXT: flags = security checks +ALL-NEXT: - S_GPROC32 [size = 44] `main` +ALL-NEXT: parent = 0, addr = 0001:0016, code size = 10, end = 196 +ALL-NEXT: debug start = 3, debug end = 8, flags = has fp +ALL-NEXT: - S_FRAMEPROC [size = 32] +ALL-NEXT: size = 0, padding size = 0, offset to padding = 0 +ALL-NEXT: bytes of callee saved registers = 0, exception handler addr = 0000:0000 +ALL-NEXT: flags = has async eh | opt speed +ALL-NEXT: - S_END [size = 4] +ALL-NEXT: - S_BUILDINFO [size = 8] BuildId = `4110` +ALL-NEXT: Mod 0001 | `* Linker *`: +ALL-NEXT: - S_OBJNAME [size = 20] sig=0, `* Linker *` +ALL-NEXT: - S_COMPILE3 [size = 48] +ALL-NEXT: machine = intel 80386, Ver = Microsoft (R) LINK, language = link +ALL-NEXT: frontend = 0.0.0.0, backend = 12.0.31101.0 +ALL-NEXT: flags = none +ALL-NEXT: - S_ENVBLOCK [size = 172] +ALL-NEXT: - cwd +ALL-NEXT: - d:\src\llvm\test\DebugInfo\PDB\Inputs +ALL-NEXT: - exe +ALL-NEXT: - C:\Program Files (x86)\Microsoft Visual Studio 12.0\VC\BIN\link.exe +ALL-NEXT: - pdb +ALL-NEXT: - d:\src\llvm\test\DebugInfo\PDB\Inputs\empty.pdb +ALL-NEXT: - S_TRAMPOLINE [size = 20] +ALL-NEXT: type = tramp incremental, size = 5, source = 0001:0005, target = 0001:0005 +ALL-NEXT: - S_SECTION [size = 28] `.text` +ALL-NEXT: length = 4122, alignment = 12, rva = 4096, section # = 1, characteristics = 1610612768 +ALL-NEXT: - S_COFFGROUP [size = 28] `.text$mn` +ALL-NEXT: length = 4122, addr = 0001:0000, characteristics = 1610612768 +ALL-NEXT: - S_SECTION [size = 28] `.rdata` +ALL-NEXT: length = 690, alignment = 12, rva = 12288, section # = 2, characteristics = 1073741888 +ALL-NEXT: - S_COFFGROUP [size = 28] `.rdata` +ALL-NEXT: length = 323, addr = 0002:0000, characteristics = 1073741888 +ALL-NEXT: - S_COFFGROUP [size = 28] `.edata` +ALL-NEXT: length = 0, addr = 0002:0323, characteristics = 1073741888 +ALL-NEXT: - S_COFFGROUP [size = 32] `.rdata$debug` +ALL-NEXT: length = 366, addr = 0002:0324, characteristics = 1073741888 +ALL-NEXT: - S_SECTION [size = 28] `.data` +ALL-NEXT: length = 4, alignment = 12, rva = 16384, section # = 3, characteristics = 3221225536 +ALL-NEXT: - S_COFFGROUP [size = 24] `.bss` +ALL-NEXT: length = 4, addr = 0003:0000, characteristics = 3221225600 +ALL-NEXT: - S_SECTION [size = 28] `.reloc` +ALL-NEXT: length = 8, alignment = 12, rva = 20480, section # = 4, characteristics = 1107296320 +ALL: Section Contributions +ALL-NEXT: ============================================================ +ALL-NEXT: SC | mod = 1, 0001:0000, size = 10, data crc = 0, reloc crc = 0 +ALL-NEXT: IMAGE_SCN_CNT_CODE | IMAGE_SCN_MEM_EXECUTE | IMAGE_SCN_MEM_READ +ALL-NEXT: SC | mod = 0, 0001:0016, size = 10, data crc = 3617027124, reloc crc = 0 +ALL-NEXT: IMAGE_SCN_CNT_CODE | IMAGE_SCN_ALIGN_16BYTES | IMAGE_SCN_MEM_EXECUTE | +ALL-NEXT: IMAGE_SCN_MEM_READ +ALL-NEXT: SC | mod = 1, 0002:0000, size = 56, data crc = 0, reloc crc = 0 +ALL-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA | IMAGE_SCN_MEM_READ +ALL-NEXT: SC | mod = 1, 0002:0324, size = 72, data crc = 0, reloc crc = 0 +ALL-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA | IMAGE_SCN_ALIGN_4BYTES | IMAGE_SCN_MEM_READ +ALL-NEXT: SC | mod = 1, 0002:0396, size = 20, data crc = 0, reloc crc = 0 +ALL-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA | IMAGE_SCN_ALIGN_4BYTES | IMAGE_SCN_MEM_READ +ALL-NEXT: SC | mod = 0, 0003:0000, size = 4, data crc = 0, reloc crc = 0 +ALL-NEXT: IMAGE_SCN_CNT_UNINITIALIZED_DATA | IMAGE_SCN_ALIGN_4BYTES | IMAGE_SCN_MEM_READ | +ALL-NEXT: IMAGE_SCN_MEM_WRITE +ALL: Section Map +ALL-NEXT: ============================================================ +ALL-NEXT: Section 0000 | ovl = 0, group = 0, frame = 0, name = 1 +ALL-NEXT: class = 65535, offset = 0, size = 4122 +ALL-NEXT: flags = read | execute | 32 bit addr | selector +ALL-NEXT: Section 0001 | ovl = 1, group = 0, frame = 0, name = 2 +ALL-NEXT: class = 65535, offset = 0, size = 690 +ALL-NEXT: flags = read | 32 bit addr | selector +ALL-NEXT: Section 0002 | ovl = 2, group = 0, frame = 0, name = 3 +ALL-NEXT: class = 65535, offset = 0, size = 4 +ALL-NEXT: flags = read | write | 32 bit addr | selector +ALL-NEXT: Section 0003 | ovl = 3, group = 0, frame = 0, name = 4 +ALL-NEXT: class = 65535, offset = 0, size = 8 +ALL-NEXT: flags = read | 32 bit addr | selector +ALL-NEXT: Section 0004 | ovl = 4, group = 0, frame = 0, name = 0 +ALL-NEXT: class = 65535, offset = 0, size = 4294967295 +ALL-NEXT: flags = 32 bit addr | absolute addr -; ALL: FileHeaders { -; ALL: BlockSize: 4096 -; ALL: FreeBlockMap: 2 -; ALL: NumBlocks: 25 -; ALL: NumDirectoryBytes: 136 -; ALL: Unknown1: 0 -; ALL: BlockMapAddr: 24 -; ALL: NumDirectoryBlocks: 1 -; ALL: DirectoryBlocks: [23] -; ALL: NumStreams: 17 -; ALL: } -; ALL: Streams [ -; ALL: Stream 0: [Old MSF Directory] (40 bytes) -; ALL: Stream 1: [PDB Stream] (118 bytes) -; ALL: Stream 2: [TPI Stream] (5392 bytes) -; ALL: Stream 3: [DBI Stream] (739 bytes) -; ALL: Stream 4: [IPI Stream] (784 bytes) -; ALL: Stream 5: [Named Stream "/LinkInfo"] (0 bytes) -; ALL: Stream 6: [Global Symbol Hash] (556 bytes) -; ALL: Stream 7: [Public Symbol Hash] (604 bytes) -; ALL: Stream 8: [Public Symbol Records] (104 bytes) -; ALL: Stream 9: [Named Stream "/src/headerblock"] (0 bytes) -; ALL: Stream 10: [Section Header Data] (160 bytes) -; ALL: Stream 11: [New FPO Data] (32 bytes) -; ALL: Stream 12: [Module "d:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj"] (308 bytes) -; ALL: Stream 13: [Named Stream "/names"] (239 bytes) -; ALL: Stream 14: [Module "* Linker *"] (520 bytes) -; ALL: Stream 15: [TPI Hash] (308 bytes) -; ALL: Stream 16: [IPI Hash] (68 bytes) -; ALL: ] -; ALL: Msf Free Pages: [3, 4, 5, 8, 9] -; ALL: Orphaned Pages: [] -; ALL: Multiply Used Pages: [] -; ALL: Use After Free Pages: [] -; ALL: StreamBlocks [ -; ALL: Stream 0: [8] -; ALL: Stream 1: [19] -; ALL: Stream 2: [18, 17] -; ALL: Stream 3: [14] -; ALL: Stream 4: [20] -; ALL: Stream 5: [] -; ALL: Stream 6: [11] -; ALL: Stream 7: [13] -; ALL: Stream 8: [12] -; ALL: Stream 9: [] -; ALL: Stream 10: [10] -; ALL: Stream 11: [15] -; ALL: Stream 12: [6] -; ALL: Stream 13: [16] -; ALL: Stream 14: [7] -; ALL: Stream 15: [21] -; ALL: Stream 16: [22] -; ALL: ] -; ALL: PDB Stream { -; ALL: Version: 20000404 -; ALL: Signature: 0x54E507E2 -; ALL: Age: 1 -; ALL: Guid: {0B355641-86A0-A249-896F-9988FAE52FF0} -; ALL: Features: 0x1 -; ALL: } -; ALL: Type Info Stream (IPI) { -; ALL: IPI Version: 20040203 -; ALL: Record count: 15 -; ALL: Records [ -; ALL: { -; ALL: UdtModSourceLine (0x1000) { -; ALL: TypeLeafKind: LF_UDT_MOD_SRC_LINE (0x1607) -; ALL: UDT: __vc_attributes::threadingAttribute (0x100B) -; ALL: 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debug stream: 26, # files: 10, has ec info: false +BIG-NEXT: Mod 0014 | Name: `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\matherr_detection.obj`: +BIG-NEXT: Obj: `C:\PROGRA~2\MI0E91~1.0\VC\LIB\MSVCRT.lib`: +BIG-NEXT: debug stream: 27, # files: 1, has ec info: false +BIG-NEXT: Mod 0015 | Name: `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\ucrt_detection.obj`: +BIG-NEXT: Obj: `C:\PROGRA~2\MI0E91~1.0\VC\LIB\MSVCRT.lib`: +BIG-NEXT: debug stream: 28, # files: 1, has ec info: false +BIG-NEXT: Mod 0016 | Name: `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\argv_mode.obj`: +BIG-NEXT: Obj: `C:\PROGRA~2\MI0E91~1.0\VC\LIB\MSVCRT.lib`: +BIG-NEXT: debug stream: 29, # files: 1, has ec info: false +BIG-NEXT: Mod 0017 | Name: `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\commit_mode.obj`: +BIG-NEXT: Obj: `C:\PROGRA~2\MI0E91~1.0\VC\LIB\MSVCRT.lib`: +BIG-NEXT: debug stream: 30, # files: 1, has ec info: false +BIG-NEXT: Mod 0018 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`f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\invalid_parameter_handler.obj`: +BIG-NEXT: Obj: `C:\PROGRA~2\MI0E91~1.0\VC\LIB\MSVCRT.lib`: +BIG-NEXT: debug stream: 35, # files: 1, has ec info: false +BIG-NEXT: Mod 0023 | Name: `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\matherr.obj`: +BIG-NEXT: Obj: `C:\PROGRA~2\MI0E91~1.0\VC\LIB\MSVCRT.lib`: +BIG-NEXT: debug stream: 36, # files: 2, has ec info: false +BIG-NEXT: Mod 0024 | Name: `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\new_mode.obj`: +BIG-NEXT: Obj: `C:\PROGRA~2\MI0E91~1.0\VC\LIB\MSVCRT.lib`: +BIG-NEXT: debug stream: 37, # files: 1, has ec info: false +BIG-NEXT: Mod 0025 | Name: `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\thread_locale.obj`: +BIG-NEXT: Obj: `C:\PROGRA~2\MI0E91~1.0\VC\LIB\MSVCRT.lib`: +BIG-NEXT: debug stream: 38, # files: 1, has ec info: false +BIG-NEXT: Mod 0026 | Name: `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\tncleanup.obj`: +BIG-NEXT: Obj: `C:\PROGRA~2\MI0E91~1.0\VC\LIB\MSVCRT.lib`: +BIG-NEXT: debug stream: 39, # files: 21, has ec info: false +BIG-NEXT: Mod 0027 | Name: `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\exe_main.obj`: +BIG-NEXT: Obj: `C:\PROGRA~2\MI0E91~1.0\VC\LIB\MSVCRT.lib`: +BIG-NEXT: debug stream: 40, # files: 26, has ec info: false +BIG-NEXT: Mod 0028 | Name: `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\initializers.obj`: +BIG-NEXT: Obj: `C:\PROGRA~2\MI0E91~1.0\VC\LIB\MSVCRT.lib`: +BIG-NEXT: debug stream: 41, # files: 20, has ec info: false +BIG-NEXT: Mod 0029 | Name: `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\utility.obj`: +BIG-NEXT: Obj: `C:\PROGRA~2\MI0E91~1.0\VC\LIB\MSVCRT.lib`: +BIG-NEXT: debug stream: 42, # files: 20, has ec info: false +BIG-NEXT: Mod 0030 | Name: `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\ucrt_stubs.obj`: +BIG-NEXT: Obj: `C:\PROGRA~2\MI0E91~1.0\VC\LIB\MSVCRT.lib`: +BIG-NEXT: debug stream: 43, # files: 1, has ec info: false +BIG-NEXT: Mod 0031 | Name: `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\utility_desktop.obj`: +BIG-NEXT: Obj: `C:\PROGRA~2\MI0E91~1.0\VC\LIB\MSVCRT.lib`: +BIG-NEXT: debug stream: 44, # files: 20, has ec info: false +BIG-NEXT: Mod 0032 | Name: `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\default_precision.obj`: +BIG-NEXT: Obj: `C:\PROGRA~2\MI0E91~1.0\VC\LIB\MSVCRT.lib`: +BIG-NEXT: debug stream: 45, # files: 20, has ec info: false +BIG-NEXT: Mod 0033 | Name: `Import:KERNEL32.dll`: +BIG-NEXT: Obj: `C:\PROGRA~2\WI3CF2~1\10\Lib\10.0.10586.0\um\x86\kernel32.lib`: +BIG-NEXT: debug stream: 47, # files: 0, has ec info: false +BIG-NEXT: Mod 0034 | Name: `KERNEL32.dll`: +BIG-NEXT: Obj: `C:\PROGRA~2\WI3CF2~1\10\Lib\10.0.10586.0\um\x86\kernel32.lib`: +BIG-NEXT: debug stream: 46, # files: 0, has ec info: false +BIG-NEXT: Mod 0035 | Name: `Import:VCRUNTIME140.dll`: +BIG-NEXT: Obj: `C:\PROGRA~2\MI0E91~1.0\VC\LIB\vcruntime.lib`: +BIG-NEXT: debug stream: 49, # files: 0, has ec info: false +BIG-NEXT: Mod 0036 | Name: `VCRUNTIME140.dll`: +BIG-NEXT: Obj: `C:\PROGRA~2\MI0E91~1.0\VC\LIB\vcruntime.lib`: +BIG-NEXT: debug stream: 48, # files: 0, has ec info: false +BIG-NEXT: Mod 0037 | Name: `Import:api-ms-win-crt-stdio-l1-1-0.dll`: +BIG-NEXT: Obj: `C:\PROGRA~2\WI3CF2~1\10\Lib\10.0.10586.0\ucrt\x86\ucrt.lib`: +BIG-NEXT: debug stream: 59, # files: 0, has ec info: false +BIG-NEXT: Mod 0038 | Name: `api-ms-win-crt-stdio-l1-1-0.dll`: +BIG-NEXT: Obj: `C:\PROGRA~2\WI3CF2~1\10\Lib\10.0.10586.0\ucrt\x86\ucrt.lib`: +BIG-NEXT: debug stream: 58, # files: 0, has ec info: false +BIG-NEXT: Mod 0039 | Name: `Import:api-ms-win-crt-runtime-l1-1-0.dll`: +BIG-NEXT: Obj: `C:\PROGRA~2\WI3CF2~1\10\Lib\10.0.10586.0\ucrt\x86\ucrt.lib`: +BIG-NEXT: debug stream: 57, # files: 0, has ec info: false +BIG-NEXT: Mod 0040 | Name: `api-ms-win-crt-runtime-l1-1-0.dll`: +BIG-NEXT: Obj: `C:\PROGRA~2\WI3CF2~1\10\Lib\10.0.10586.0\ucrt\x86\ucrt.lib`: +BIG-NEXT: debug stream: 56, # files: 0, has ec info: false +BIG-NEXT: Mod 0041 | Name: `Import:api-ms-win-crt-math-l1-1-0.dll`: +BIG-NEXT: Obj: `C:\PROGRA~2\WI3CF2~1\10\Lib\10.0.10586.0\ucrt\x86\ucrt.lib`: +BIG-NEXT: debug stream: 55, # files: 0, has ec info: false +BIG-NEXT: Mod 0042 | Name: `api-ms-win-crt-math-l1-1-0.dll`: +BIG-NEXT: Obj: `C:\PROGRA~2\WI3CF2~1\10\Lib\10.0.10586.0\ucrt\x86\ucrt.lib`: +BIG-NEXT: debug stream: 54, # files: 0, has ec info: false +BIG-NEXT: Mod 0043 | Name: `Import:api-ms-win-crt-locale-l1-1-0.dll`: +BIG-NEXT: Obj: `C:\PROGRA~2\WI3CF2~1\10\Lib\10.0.10586.0\ucrt\x86\ucrt.lib`: +BIG-NEXT: debug stream: 53, # files: 0, has ec info: false +BIG-NEXT: Mod 0044 | Name: `api-ms-win-crt-locale-l1-1-0.dll`: +BIG-NEXT: Obj: `C:\PROGRA~2\WI3CF2~1\10\Lib\10.0.10586.0\ucrt\x86\ucrt.lib`: +BIG-NEXT: debug stream: 52, # files: 0, has ec info: false +BIG-NEXT: Mod 0045 | Name: `Import:api-ms-win-crt-heap-l1-1-0.dll`: +BIG-NEXT: Obj: `C:\PROGRA~2\WI3CF2~1\10\Lib\10.0.10586.0\ucrt\x86\ucrt.lib`: +BIG-NEXT: debug stream: 51, # files: 0, has ec info: false +BIG-NEXT: Mod 0046 | Name: `api-ms-win-crt-heap-l1-1-0.dll`: +BIG-NEXT: Obj: `C:\PROGRA~2\WI3CF2~1\10\Lib\10.0.10586.0\ucrt\x86\ucrt.lib`: +BIG-NEXT: debug stream: 50, # files: 0, has ec info: false +BIG-NEXT: Mod 0047 | Name: `* Linker *`: +BIG-NEXT: Obj: ``: +BIG-NEXT: debug stream: 60, # files: 0, has ec info: false +BIG: Files +BIG-NEXT: ============================================================ +BIG-NEXT: Mod 0000 | `D:\src\llvm\test\tools\llvm-symbolizer\pdb\Inputs\test.obj`: +BIG-NEXT: - (MD5: A20261917ADC01A12CBDBF778BC6CCC8) d:\src\llvm\test\tools\llvm-symbolizer\pdb\inputs\test.cpp +BIG-NEXT: Mod 0001 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\_cpu_disp_.obj`: +BIG-NEXT: - (MD5: 928553F8BA198C9030B65FA10B6B3DD2) f:\dd\externalapis\unifiedcrt\inc\malloc.h +BIG-NEXT: - (MD5: 377E41F4DAE6F93EA819B4EFCF229F08) f:\dd\externalapis\unifiedcrt\inc\string.h +BIG-NEXT: - (MD5: A5976652B404EDDDBDA326FF9A9488A3) f:\dd\externalapis\unifiedcrt\inc\corecrt_memcpy_s.h +BIG-NEXT: - (MD5: 8A16383C445FDABF21BDBAC3825E8133) f:\dd\externalapis\windows\8.1\sdk\inc\evntprov.h +BIG-NEXT: - (MD5: 9393435BC7FDE9F624E309D56629171A) f:\dd\vctools\crt\vcruntime\inc\internal_shared.h +BIG-NEXT: - (MD5: DCC558DEFD73C17745F94CC5A98632D9) f:\dd\externalapis\windows\8.1\sdk\inc\stralign.h +BIG-NEXT: - (MD5: 493F2CAB7A6BE4175748A9FC6C4A38FB) f:\dd\externalapis\windows\8.1\sdk\inc\basetsd.h +BIG-NEXT: - (MD5: E4963431577926D9BA190CD6C10F8743) f:\dd\vctools\crt\vcruntime\inc\i386\xmmintrin.h +BIG-NEXT: - (MD5: B38ACA278420B7C5F25A50AD159CACA0) f:\dd\externalapis\windows\8.1\sdk\inc\winerror.h +BIG-NEXT: - (MD5: 2D923CBDE24BB8F217FE09A5F7D88929) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstring.h +BIG-NEXT: - (MD5: 884E12AC852D3B4E1E625A0F01595A68) f:\dd\vctools\crt\vcstartup\src\misc\i386\cpu_disp.c +BIG-NEXT: - (MD5: C3412F163DF064CCDEF8CFBE0A387550) f:\dd\externalapis\windows\8.1\sdk\inc\winbase.h +BIG-NEXT: - (MD5: ADDFD8BEB612E9A30D5FB7C44F9F3D37) f:\dd\externalapis\windows\8.1\sdk\inc\winnt.h +BIG-NEXT: - (MD5: 386A22AB644E999820C7C22FCE5DB574) f:\dd\externalapis\unifiedcrt\inc\ctype.h +BIG-NEXT: Mod 0002 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\_initsect_.obj`: +BIG-NEXT: - (MD5: 9393435BC7FDE9F624E309D56629171A) f:\dd\vctools\crt\vcruntime\inc\internal_shared.h +BIG-NEXT: - (MD5: C3412F163DF064CCDEF8CFBE0A387550) f:\dd\externalapis\windows\8.1\sdk\inc\winbase.h +BIG-NEXT: - (MD5: DD3FFC8C4284997F6762C449313244B2) f:\dd\vctools\crt\vcstartup\src\rtc\initsect.cpp +BIG-NEXT: - (MD5: DCC558DEFD73C17745F94CC5A98632D9) f:\dd\externalapis\windows\8.1\sdk\inc\stralign.h +BIG-NEXT: - (MD5: 928553F8BA198C9030B65FA10B6B3DD2) f:\dd\externalapis\unifiedcrt\inc\malloc.h +BIG-NEXT: - (MD5: 493F2CAB7A6BE4175748A9FC6C4A38FB) f:\dd\externalapis\windows\8.1\sdk\inc\basetsd.h +BIG-NEXT: - (MD5: E4963431577926D9BA190CD6C10F8743) f:\dd\vctools\crt\vcruntime\inc\i386\xmmintrin.h +BIG-NEXT: - (MD5: 2D923CBDE24BB8F217FE09A5F7D88929) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstring.h +BIG-NEXT: - (MD5: B38ACA278420B7C5F25A50AD159CACA0) f:\dd\externalapis\windows\8.1\sdk\inc\winerror.h +BIG-NEXT: - (MD5: C44C7E39EE3B3A4EF6B3211EC0110AA8) f:\dd\externalapis\unifiedcrt\inc\stdlib.h +BIG-NEXT: - (MD5: ADDFD8BEB612E9A30D5FB7C44F9F3D37) f:\dd\externalapis\windows\8.1\sdk\inc\winnt.h +BIG-NEXT: - (MD5: 386A22AB644E999820C7C22FCE5DB574) f:\dd\externalapis\unifiedcrt\inc\ctype.h +BIG-NEXT: - (MD5: 8A16383C445FDABF21BDBAC3825E8133) f:\dd\externalapis\windows\8.1\sdk\inc\evntprov.h +BIG-NEXT: - (MD5: CA7D066706A198EA5999B084AAB0CE58) f:\dd\externalapis\windows\8.1\sdk\inc\guiddef.h +BIG-NEXT: - (MD5: F9FC1E83CBE1A51209ED1C05BB0F70B2) f:\dd\externalapis\windows\8.1\sdk\inc\winuser.h +BIG-NEXT: - (MD5: A40485987BE01BAF5F57569A41DAB837) f:\dd\vctools\crt\vcruntime\inc\vcruntime_new.h +BIG-NEXT: - (MD5: 377E41F4DAE6F93EA819B4EFCF229F08) f:\dd\externalapis\unifiedcrt\inc\string.h +BIG-NEXT: - (MD5: 96C01EE8E4C01B90601D93353838EBF8) f:\dd\externalapis\unifiedcrt\inc\corecrt_memory.h +BIG-NEXT: - (MD5: A5976652B404EDDDBDA326FF9A9488A3) f:\dd\externalapis\unifiedcrt\inc\corecrt_memcpy_s.h +BIG-NEXT: Mod 0003 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\_sehprolg4_.obj`: +BIG-NEXT: - (MD5: E562BB073C88A6A3791CE9FBDC64E7A7) f:\dd\vctools\crt\vcstartup\src\eh\i386\sehprolg4.asm +BIG-NEXT: Mod 0004 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\_chandler4gs_.obj`: +BIG-NEXT: - (MD5: 928553F8BA198C9030B65FA10B6B3DD2) f:\dd\externalapis\unifiedcrt\inc\malloc.h +BIG-NEXT: - (MD5: 377E41F4DAE6F93EA819B4EFCF229F08) f:\dd\externalapis\unifiedcrt\inc\string.h +BIG-NEXT: - (MD5: A5976652B404EDDDBDA326FF9A9488A3) f:\dd\externalapis\unifiedcrt\inc\corecrt_memcpy_s.h +BIG-NEXT: - (MD5: 8A16383C445FDABF21BDBAC3825E8133) f:\dd\externalapis\windows\8.1\sdk\inc\evntprov.h +BIG-NEXT: - (MD5: 9393435BC7FDE9F624E309D56629171A) f:\dd\vctools\crt\vcruntime\inc\internal_shared.h +BIG-NEXT: - (MD5: DCC558DEFD73C17745F94CC5A98632D9) f:\dd\externalapis\windows\8.1\sdk\inc\stralign.h +BIG-NEXT: - (MD5: 493F2CAB7A6BE4175748A9FC6C4A38FB) f:\dd\externalapis\windows\8.1\sdk\inc\basetsd.h +BIG-NEXT: - (MD5: E4963431577926D9BA190CD6C10F8743) f:\dd\vctools\crt\vcruntime\inc\i386\xmmintrin.h +BIG-NEXT: - (MD5: B38ACA278420B7C5F25A50AD159CACA0) f:\dd\externalapis\windows\8.1\sdk\inc\winerror.h +BIG-NEXT: - (MD5: 2D923CBDE24BB8F217FE09A5F7D88929) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstring.h +BIG-NEXT: - (MD5: D014BFD91FD6D4163AF92452CBC9EEA0) f:\dd\vctools\crt\vcstartup\src\eh\i386\chandler4gs.c +BIG-NEXT: - (MD5: C3412F163DF064CCDEF8CFBE0A387550) f:\dd\externalapis\windows\8.1\sdk\inc\winbase.h +BIG-NEXT: - (MD5: ADDFD8BEB612E9A30D5FB7C44F9F3D37) f:\dd\externalapis\windows\8.1\sdk\inc\winnt.h +BIG-NEXT: - (MD5: 386A22AB644E999820C7C22FCE5DB574) f:\dd\externalapis\unifiedcrt\inc\ctype.h +BIG-NEXT: Mod 0005 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\_secchk_.obj`: +BIG-NEXT: - (MD5: 928553F8BA198C9030B65FA10B6B3DD2) f:\dd\externalapis\unifiedcrt\inc\malloc.h +BIG-NEXT: - (MD5: 377E41F4DAE6F93EA819B4EFCF229F08) f:\dd\externalapis\unifiedcrt\inc\string.h +BIG-NEXT: - (MD5: A5976652B404EDDDBDA326FF9A9488A3) f:\dd\externalapis\unifiedcrt\inc\corecrt_memcpy_s.h +BIG-NEXT: - (MD5: 8A16383C445FDABF21BDBAC3825E8133) f:\dd\externalapis\windows\8.1\sdk\inc\evntprov.h +BIG-NEXT: - (MD5: 9393435BC7FDE9F624E309D56629171A) f:\dd\vctools\crt\vcruntime\inc\internal_shared.h +BIG-NEXT: - (MD5: DCC558DEFD73C17745F94CC5A98632D9) f:\dd\externalapis\windows\8.1\sdk\inc\stralign.h +BIG-NEXT: - (MD5: 493F2CAB7A6BE4175748A9FC6C4A38FB) f:\dd\externalapis\windows\8.1\sdk\inc\basetsd.h +BIG-NEXT: - (MD5: E4963431577926D9BA190CD6C10F8743) f:\dd\vctools\crt\vcruntime\inc\i386\xmmintrin.h +BIG-NEXT: - (MD5: B38ACA278420B7C5F25A50AD159CACA0) f:\dd\externalapis\windows\8.1\sdk\inc\winerror.h +BIG-NEXT: - (MD5: 2D923CBDE24BB8F217FE09A5F7D88929) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstring.h +BIG-NEXT: - (MD5: 6C34B4E5ACA82CB0D6BD6CB8C059C9C9) f:\dd\vctools\crt\vcstartup\src\eh\i386\secchk.c +BIG-NEXT: - (MD5: C3412F163DF064CCDEF8CFBE0A387550) f:\dd\externalapis\windows\8.1\sdk\inc\winbase.h +BIG-NEXT: - (MD5: ADDFD8BEB612E9A30D5FB7C44F9F3D37) f:\dd\externalapis\windows\8.1\sdk\inc\winnt.h +BIG-NEXT: - (MD5: 386A22AB644E999820C7C22FCE5DB574) f:\dd\externalapis\unifiedcrt\inc\ctype.h +BIG-NEXT: Mod 0006 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\gs_cookie.obj`: +BIG-NEXT: - (MD5: DCC558DEFD73C17745F94CC5A98632D9) f:\dd\externalapis\windows\8.1\sdk\inc\stralign.h +BIG-NEXT: - (MD5: 377E41F4DAE6F93EA819B4EFCF229F08) f:\dd\externalapis\unifiedcrt\inc\string.h +BIG-NEXT: - (MD5: A5976652B404EDDDBDA326FF9A9488A3) f:\dd\externalapis\unifiedcrt\inc\corecrt_memcpy_s.h +BIG-NEXT: - (MD5: B38ACA278420B7C5F25A50AD159CACA0) f:\dd\externalapis\windows\8.1\sdk\inc\winerror.h +BIG-NEXT: - (MD5: 2D923CBDE24BB8F217FE09A5F7D88929) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstring.h +BIG-NEXT: - (MD5: C3412F163DF064CCDEF8CFBE0A387550) f:\dd\externalapis\windows\8.1\sdk\inc\winbase.h +BIG-NEXT: - (MD5: 493F2CAB7A6BE4175748A9FC6C4A38FB) f:\dd\externalapis\windows\8.1\sdk\inc\basetsd.h +BIG-NEXT: - (MD5: ADDFD8BEB612E9A30D5FB7C44F9F3D37) f:\dd\externalapis\windows\8.1\sdk\inc\winnt.h +BIG-NEXT: - (MD5: 386A22AB644E999820C7C22FCE5DB574) f:\dd\externalapis\unifiedcrt\inc\ctype.h +BIG-NEXT: Mod 0007 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\gs_report.obj`: +BIG-NEXT: - (MD5: 928553F8BA198C9030B65FA10B6B3DD2) f:\dd\externalapis\unifiedcrt\inc\malloc.h +BIG-NEXT: - (MD5: 377E41F4DAE6F93EA819B4EFCF229F08) f:\dd\externalapis\unifiedcrt\inc\string.h +BIG-NEXT: - (MD5: A5976652B404EDDDBDA326FF9A9488A3) f:\dd\externalapis\unifiedcrt\inc\corecrt_memcpy_s.h +BIG-NEXT: - (MD5: 8A16383C445FDABF21BDBAC3825E8133) f:\dd\externalapis\windows\8.1\sdk\inc\evntprov.h +BIG-NEXT: - (MD5: 9393435BC7FDE9F624E309D56629171A) f:\dd\vctools\crt\vcruntime\inc\internal_shared.h +BIG-NEXT: - (MD5: DCC558DEFD73C17745F94CC5A98632D9) f:\dd\externalapis\windows\8.1\sdk\inc\stralign.h +BIG-NEXT: - (MD5: 493F2CAB7A6BE4175748A9FC6C4A38FB) f:\dd\externalapis\windows\8.1\sdk\inc\basetsd.h +BIG-NEXT: - (MD5: E4963431577926D9BA190CD6C10F8743) f:\dd\vctools\crt\vcruntime\inc\i386\xmmintrin.h +BIG-NEXT: - (MD5: B38ACA278420B7C5F25A50AD159CACA0) f:\dd\externalapis\windows\8.1\sdk\inc\winerror.h +BIG-NEXT: - (MD5: 2D923CBDE24BB8F217FE09A5F7D88929) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstring.h +BIG-NEXT: - (MD5: 87566AA39C18DD3CEAC021002D34B63D) f:\dd\vctools\crt\vcstartup\src\gs\gs_report.c +BIG-NEXT: - (MD5: C3412F163DF064CCDEF8CFBE0A387550) f:\dd\externalapis\windows\8.1\sdk\inc\winbase.h +BIG-NEXT: - (MD5: ADDFD8BEB612E9A30D5FB7C44F9F3D37) f:\dd\externalapis\windows\8.1\sdk\inc\winnt.h +BIG-NEXT: - (MD5: 386A22AB644E999820C7C22FCE5DB574) f:\dd\externalapis\unifiedcrt\inc\ctype.h +BIG-NEXT: Mod 0008 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\gs_support.obj`: +BIG-NEXT: - (MD5: DCC558DEFD73C17745F94CC5A98632D9) f:\dd\externalapis\windows\8.1\sdk\inc\stralign.h +BIG-NEXT: - (MD5: 377E41F4DAE6F93EA819B4EFCF229F08) f:\dd\externalapis\unifiedcrt\inc\string.h +BIG-NEXT: - (MD5: A5976652B404EDDDBDA326FF9A9488A3) f:\dd\externalapis\unifiedcrt\inc\corecrt_memcpy_s.h +BIG-NEXT: - (MD5: B38ACA278420B7C5F25A50AD159CACA0) f:\dd\externalapis\windows\8.1\sdk\inc\winerror.h +BIG-NEXT: - (MD5: 2D923CBDE24BB8F217FE09A5F7D88929) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstring.h +BIG-NEXT: - (MD5: C3412F163DF064CCDEF8CFBE0A387550) f:\dd\externalapis\windows\8.1\sdk\inc\winbase.h +BIG-NEXT: - (MD5: 493F2CAB7A6BE4175748A9FC6C4A38FB) f:\dd\externalapis\windows\8.1\sdk\inc\basetsd.h +BIG-NEXT: - (MD5: ADDFD8BEB612E9A30D5FB7C44F9F3D37) f:\dd\externalapis\windows\8.1\sdk\inc\winnt.h +BIG-NEXT: - (MD5: 386A22AB644E999820C7C22FCE5DB574) f:\dd\externalapis\unifiedcrt\inc\ctype.h +BIG-NEXT: - (MD5: 57AC84319EF78F67DAA9372FDA8CBFCC) f:\dd\vctools\crt\vcstartup\src\gs\gs_support.c +BIG-NEXT: Mod 0009 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\checkcfg.obj`: +BIG-NEXT: - (MD5: 928553F8BA198C9030B65FA10B6B3DD2) f:\dd\externalapis\unifiedcrt\inc\malloc.h +BIG-NEXT: - (MD5: 377E41F4DAE6F93EA819B4EFCF229F08) f:\dd\externalapis\unifiedcrt\inc\string.h +BIG-NEXT: - (MD5: A5976652B404EDDDBDA326FF9A9488A3) f:\dd\externalapis\unifiedcrt\inc\corecrt_memcpy_s.h +BIG-NEXT: - (MD5: 8A16383C445FDABF21BDBAC3825E8133) f:\dd\externalapis\windows\8.1\sdk\inc\evntprov.h +BIG-NEXT: - (MD5: 9393435BC7FDE9F624E309D56629171A) f:\dd\vctools\crt\vcruntime\inc\internal_shared.h +BIG-NEXT: - (MD5: DCC558DEFD73C17745F94CC5A98632D9) f:\dd\externalapis\windows\8.1\sdk\inc\stralign.h +BIG-NEXT: - (MD5: 493F2CAB7A6BE4175748A9FC6C4A38FB) f:\dd\externalapis\windows\8.1\sdk\inc\basetsd.h +BIG-NEXT: - (MD5: E4963431577926D9BA190CD6C10F8743) f:\dd\vctools\crt\vcruntime\inc\i386\xmmintrin.h +BIG-NEXT: - (MD5: B38ACA278420B7C5F25A50AD159CACA0) f:\dd\externalapis\windows\8.1\sdk\inc\winerror.h +BIG-NEXT: - (MD5: 2D923CBDE24BB8F217FE09A5F7D88929) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstring.h +BIG-NEXT: - (MD5: 9552C4FC4125F9D7D3A8B5FD18B7BCCF) f:\dd\vctools\crt\vcstartup\src\misc\checkcfg.c +BIG-NEXT: - (MD5: C3412F163DF064CCDEF8CFBE0A387550) f:\dd\externalapis\windows\8.1\sdk\inc\winbase.h +BIG-NEXT: - (MD5: ADDFD8BEB612E9A30D5FB7C44F9F3D37) f:\dd\externalapis\windows\8.1\sdk\inc\winnt.h +BIG-NEXT: - (MD5: 386A22AB644E999820C7C22FCE5DB574) f:\dd\externalapis\unifiedcrt\inc\ctype.h +BIG-NEXT: Mod 0010 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\guard_support.obj`: +BIG-NEXT: - (MD5: DCC558DEFD73C17745F94CC5A98632D9) f:\dd\externalapis\windows\8.1\sdk\inc\stralign.h +BIG-NEXT: - (MD5: 377E41F4DAE6F93EA819B4EFCF229F08) f:\dd\externalapis\unifiedcrt\inc\string.h +BIG-NEXT: - (MD5: A5976652B404EDDDBDA326FF9A9488A3) f:\dd\externalapis\unifiedcrt\inc\corecrt_memcpy_s.h +BIG-NEXT: - (MD5: B38ACA278420B7C5F25A50AD159CACA0) f:\dd\externalapis\windows\8.1\sdk\inc\winerror.h +BIG-NEXT: - (MD5: 2D923CBDE24BB8F217FE09A5F7D88929) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstring.h +BIG-NEXT: - (MD5: C3412F163DF064CCDEF8CFBE0A387550) f:\dd\externalapis\windows\8.1\sdk\inc\winbase.h +BIG-NEXT: - (MD5: 493F2CAB7A6BE4175748A9FC6C4A38FB) f:\dd\externalapis\windows\8.1\sdk\inc\basetsd.h +BIG-NEXT: - (MD5: ADDFD8BEB612E9A30D5FB7C44F9F3D37) f:\dd\externalapis\windows\8.1\sdk\inc\winnt.h +BIG-NEXT: - (MD5: 386A22AB644E999820C7C22FCE5DB574) f:\dd\externalapis\unifiedcrt\inc\ctype.h +BIG-NEXT: - (MD5: 8BFBA3D0672A148A9FB0E9F0A6BC256D) f:\dd\vctools\crt\vcstartup\src\misc\guard_support.c +BIG-NEXT: Mod 0011 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\loadcfg.obj`: +BIG-NEXT: - (MD5: DCC558DEFD73C17745F94CC5A98632D9) f:\dd\externalapis\windows\8.1\sdk\inc\stralign.h +BIG-NEXT: - (MD5: 377E41F4DAE6F93EA819B4EFCF229F08) f:\dd\externalapis\unifiedcrt\inc\string.h +BIG-NEXT: - (MD5: A5976652B404EDDDBDA326FF9A9488A3) f:\dd\externalapis\unifiedcrt\inc\corecrt_memcpy_s.h +BIG-NEXT: - (MD5: B38ACA278420B7C5F25A50AD159CACA0) f:\dd\externalapis\windows\8.1\sdk\inc\winerror.h +BIG-NEXT: - (MD5: 2D923CBDE24BB8F217FE09A5F7D88929) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstring.h +BIG-NEXT: - (MD5: C3412F163DF064CCDEF8CFBE0A387550) f:\dd\externalapis\windows\8.1\sdk\inc\winbase.h +BIG-NEXT: - (MD5: 493F2CAB7A6BE4175748A9FC6C4A38FB) f:\dd\externalapis\windows\8.1\sdk\inc\basetsd.h +BIG-NEXT: - (MD5: ADDFD8BEB612E9A30D5FB7C44F9F3D37) f:\dd\externalapis\windows\8.1\sdk\inc\winnt.h +BIG-NEXT: - (MD5: 386A22AB644E999820C7C22FCE5DB574) f:\dd\externalapis\unifiedcrt\inc\ctype.h +BIG-NEXT: Mod 0012 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\dyn_tls_dtor.obj`: +BIG-NEXT: - (MD5: DCC558DEFD73C17745F94CC5A98632D9) f:\dd\externalapis\windows\8.1\sdk\inc\stralign.h +BIG-NEXT: - (MD5: 377E41F4DAE6F93EA819B4EFCF229F08) f:\dd\externalapis\unifiedcrt\inc\string.h +BIG-NEXT: - (MD5: A5976652B404EDDDBDA326FF9A9488A3) f:\dd\externalapis\unifiedcrt\inc\corecrt_memcpy_s.h +BIG-NEXT: - (MD5: B38ACA278420B7C5F25A50AD159CACA0) f:\dd\externalapis\windows\8.1\sdk\inc\winerror.h +BIG-NEXT: - (MD5: 2D923CBDE24BB8F217FE09A5F7D88929) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstring.h +BIG-NEXT: - (MD5: 23CC88BD1D9451C2CE5F824306E16E4D) f:\dd\externalapis\unifiedcrt\inc\math.h +BIG-NEXT: - (MD5: C3412F163DF064CCDEF8CFBE0A387550) f:\dd\externalapis\windows\8.1\sdk\inc\winbase.h +BIG-NEXT: - (MD5: 493F2CAB7A6BE4175748A9FC6C4A38FB) f:\dd\externalapis\windows\8.1\sdk\inc\basetsd.h +BIG-NEXT: - (MD5: ADDFD8BEB612E9A30D5FB7C44F9F3D37) f:\dd\externalapis\windows\8.1\sdk\inc\winnt.h +BIG-NEXT: - (MD5: 386A22AB644E999820C7C22FCE5DB574) f:\dd\externalapis\unifiedcrt\inc\ctype.h +BIG-NEXT: - (MD5: EE3858E06B118BDBAAE53F5E55B0BB0C) f:\dd\vctools\crt\vcstartup\src\utility\dyn_tls_dtor.c +BIG-NEXT: Mod 0013 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\dyn_tls_init.obj`: +BIG-NEXT: - (MD5: DCC558DEFD73C17745F94CC5A98632D9) f:\dd\externalapis\windows\8.1\sdk\inc\stralign.h +BIG-NEXT: - (MD5: 377E41F4DAE6F93EA819B4EFCF229F08) f:\dd\externalapis\unifiedcrt\inc\string.h +BIG-NEXT: - (MD5: A5976652B404EDDDBDA326FF9A9488A3) f:\dd\externalapis\unifiedcrt\inc\corecrt_memcpy_s.h +BIG-NEXT: - (MD5: B38ACA278420B7C5F25A50AD159CACA0) f:\dd\externalapis\windows\8.1\sdk\inc\winerror.h +BIG-NEXT: - (MD5: 2D923CBDE24BB8F217FE09A5F7D88929) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstring.h +BIG-NEXT: - (MD5: C3412F163DF064CCDEF8CFBE0A387550) f:\dd\externalapis\windows\8.1\sdk\inc\winbase.h +BIG-NEXT: - (MD5: 493F2CAB7A6BE4175748A9FC6C4A38FB) f:\dd\externalapis\windows\8.1\sdk\inc\basetsd.h +BIG-NEXT: - (MD5: ADDFD8BEB612E9A30D5FB7C44F9F3D37) f:\dd\externalapis\windows\8.1\sdk\inc\winnt.h +BIG-NEXT: - (MD5: 386A22AB644E999820C7C22FCE5DB574) f:\dd\externalapis\unifiedcrt\inc\ctype.h +BIG-NEXT: - (MD5: 9DA48F59075BBAAAB4F7FC4575F34405) f:\dd\vctools\crt\vcstartup\src\utility\dyn_tls_init.c +BIG-NEXT: Mod 0014 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\matherr_detection.obj`: +BIG-NEXT: - (MD5: 2DF28D8BA8B7AAAA67C94719B214B060) f:\dd\vctools\crt\vcstartup\src\utility\matherr_detection.c +BIG-NEXT: Mod 0015 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\ucrt_detection.obj`: +BIG-NEXT: - (MD5: 737902C62D7458629D0DDD52E122C033) f:\dd\vctools\crt\vcstartup\src\utility\ucrt_detection.c +BIG-NEXT: Mod 0016 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\argv_mode.obj`: +BIG-NEXT: - (MD5: 634D3D57BDE292817F77F8DBF366E2D2) f:\dd\vctools\crt\vcstartup\src\defaults\argv_mode.cpp +BIG-NEXT: Mod 0017 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\commit_mode.obj`: +BIG-NEXT: - (MD5: CF5B0F6243121A3F5E206E07CA457128) f:\dd\vctools\crt\vcstartup\src\defaults\commit_mode.cpp +BIG-NEXT: Mod 0018 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\default_local_stdio_options.obj`: +BIG-NEXT: - (MD5: 928553F8BA198C9030B65FA10B6B3DD2) f:\dd\externalapis\unifiedcrt\inc\malloc.h +BIG-NEXT: - (MD5: 493F2CAB7A6BE4175748A9FC6C4A38FB) f:\dd\externalapis\windows\8.1\sdk\inc\basetsd.h +BIG-NEXT: - (MD5: E4963431577926D9BA190CD6C10F8743) f:\dd\vctools\crt\vcruntime\inc\i386\xmmintrin.h +BIG-NEXT: - (MD5: E6391682D136711F96E730F4D6162E0C) f:\dd\vctools\crt\vcstartup\src\defaults\default_local_stdio_options.cpp +BIG-NEXT: - (MD5: C3412F163DF064CCDEF8CFBE0A387550) f:\dd\externalapis\windows\8.1\sdk\inc\winbase.h +BIG-NEXT: - (MD5: 23CC88BD1D9451C2CE5F824306E16E4D) f:\dd\externalapis\unifiedcrt\inc\math.h +BIG-NEXT: - (MD5: C44C7E39EE3B3A4EF6B3211EC0110AA8) f:\dd\externalapis\unifiedcrt\inc\stdlib.h +BIG-NEXT: - (MD5: DCC558DEFD73C17745F94CC5A98632D9) f:\dd\externalapis\windows\8.1\sdk\inc\stralign.h +BIG-NEXT: - (MD5: ADDFD8BEB612E9A30D5FB7C44F9F3D37) f:\dd\externalapis\windows\8.1\sdk\inc\winnt.h +BIG-NEXT: - (MD5: 386A22AB644E999820C7C22FCE5DB574) f:\dd\externalapis\unifiedcrt\inc\ctype.h +BIG-NEXT: - (MD5: CA7D066706A198EA5999B084AAB0CE58) f:\dd\externalapis\windows\8.1\sdk\inc\guiddef.h +BIG-NEXT: - (MD5: 2D923CBDE24BB8F217FE09A5F7D88929) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstring.h +BIG-NEXT: - (MD5: B38ACA278420B7C5F25A50AD159CACA0) f:\dd\externalapis\windows\8.1\sdk\inc\winerror.h +BIG-NEXT: - (MD5: 2D5E699DF1BED89FCCCCCF0DCFC49050) f:\dd\externalapis\unifiedcrt\inc\stdio.h +BIG-NEXT: - (MD5: 2443DB19DCC585E308F60DAFEF1D4C4C) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstdio.h +BIG-NEXT: - (MD5: 79921ECB03C5C56E28D771ADF8910FD8) f:\dd\externalapis\unifiedcrt\inc\corecrt_stdio_config.h +BIG-NEXT: - (MD5: 7C388EF80868D8301B5A908485637FEE) f:\dd\vctools\crt\vcstartup\inc\vcstartup_internal.h +BIG-NEXT: - (MD5: 377E41F4DAE6F93EA819B4EFCF229F08) f:\dd\externalapis\unifiedcrt\inc\string.h +BIG-NEXT: - (MD5: 96C01EE8E4C01B90601D93353838EBF8) f:\dd\externalapis\unifiedcrt\inc\corecrt_memory.h +BIG-NEXT: - (MD5: A5976652B404EDDDBDA326FF9A9488A3) f:\dd\externalapis\unifiedcrt\inc\corecrt_memcpy_s.h +BIG-NEXT: - (MD5: 9393435BC7FDE9F624E309D56629171A) f:\dd\vctools\crt\vcruntime\inc\internal_shared.h +BIG-NEXT: - (MD5: A40485987BE01BAF5F57569A41DAB837) f:\dd\vctools\crt\vcruntime\inc\vcruntime_new.h +BIG-NEXT: - (MD5: 303C50A7BC924CD426BAA20C7F16192C) f:\dd\vctools\crt\vcruntime\inc\vadefs.h +BIG-NEXT: - (MD5: F9FC1E83CBE1A51209ED1C05BB0F70B2) f:\dd\externalapis\windows\8.1\sdk\inc\winuser.h +BIG-NEXT: Mod 0019 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\denormal_control.obj`: +BIG-NEXT: - (MD5: 0513001DBCB8CB8F8561DC117FD943BA) f:\dd\vctools\crt\vcstartup\src\defaults\denormal_control.cpp +BIG-NEXT: Mod 0020 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\env_mode.obj`: +BIG-NEXT: - (MD5: 5B7121FC3210A120D7B70CB668D8EF0C) f:\dd\vctools\crt\vcstartup\src\defaults\env_mode.cpp +BIG-NEXT: Mod 0021 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\file_mode.obj`: +BIG-NEXT: - (MD5: 749603C05EB2FB5024819A3107DA9A7D) f:\dd\vctools\crt\vcstartup\src\defaults\file_mode.cpp +BIG-NEXT: Mod 0022 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\invalid_parameter_handler.obj`: +BIG-NEXT: - (MD5: 0C385FD7C6DB91E0BA7C72C1AB680BE6) f:\dd\vctools\crt\vcstartup\src\defaults\invalid_parameter_handler.cpp +BIG-NEXT: Mod 0023 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\matherr.obj`: +BIG-NEXT: - (MD5: F8B3DAD79F14E4169CCBA611203C89CD) f:\dd\vctools\crt\vcstartup\src\defaults\matherr.cpp +BIG-NEXT: - (MD5: 23CC88BD1D9451C2CE5F824306E16E4D) f:\dd\externalapis\unifiedcrt\inc\math.h +BIG-NEXT: Mod 0024 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\new_mode.obj`: +BIG-NEXT: - (MD5: 4F22B6A5E4E0D01E8C000B17F2B2640D) f:\dd\vctools\crt\vcstartup\src\defaults\new_mode.cpp +BIG-NEXT: Mod 0025 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\thread_locale.obj`: +BIG-NEXT: - (MD5: 435F5F51541F7D6565DF6BE20F8AC8A3) f:\dd\vctools\crt\vcstartup\src\defaults\thread_locale.cpp +BIG-NEXT: Mod 0026 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\tncleanup.obj`: +BIG-NEXT: - (MD5: 9393435BC7FDE9F624E309D56629171A) f:\dd\vctools\crt\vcruntime\inc\internal_shared.h +BIG-NEXT: - (MD5: C3412F163DF064CCDEF8CFBE0A387550) f:\dd\externalapis\windows\8.1\sdk\inc\winbase.h +BIG-NEXT: - (MD5: 984A18787250F7F6D0506E6BC1FD7991) f:\dd\vctools\crt\vcstartup\src\eh\tncleanup.cpp +BIG-NEXT: - (MD5: DCC558DEFD73C17745F94CC5A98632D9) f:\dd\externalapis\windows\8.1\sdk\inc\stralign.h +BIG-NEXT: - (MD5: 928553F8BA198C9030B65FA10B6B3DD2) f:\dd\externalapis\unifiedcrt\inc\malloc.h +BIG-NEXT: - (MD5: 493F2CAB7A6BE4175748A9FC6C4A38FB) f:\dd\externalapis\windows\8.1\sdk\inc\basetsd.h +BIG-NEXT: - (MD5: E4963431577926D9BA190CD6C10F8743) f:\dd\vctools\crt\vcruntime\inc\i386\xmmintrin.h +BIG-NEXT: - (MD5: 2D923CBDE24BB8F217FE09A5F7D88929) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstring.h +BIG-NEXT: - (MD5: B38ACA278420B7C5F25A50AD159CACA0) f:\dd\externalapis\windows\8.1\sdk\inc\winerror.h +BIG-NEXT: - (MD5: 2465A06B1F50CD26AD5EC7D20DA6DB3D) f:\dd\vctools\crt\vcruntime\inc\vcruntime_typeinfo.h +BIG-NEXT: - (MD5: 385CF08DA92F72075026067CE03F8402) f:\dd\vctools\crt\vcruntime\inc\vcruntime_exception.h +BIG-NEXT: - (MD5: C44C7E39EE3B3A4EF6B3211EC0110AA8) f:\dd\externalapis\unifiedcrt\inc\stdlib.h +BIG-NEXT: - (MD5: ADDFD8BEB612E9A30D5FB7C44F9F3D37) f:\dd\externalapis\windows\8.1\sdk\inc\winnt.h +BIG-NEXT: - (MD5: 386A22AB644E999820C7C22FCE5DB574) f:\dd\externalapis\unifiedcrt\inc\ctype.h +BIG-NEXT: - (MD5: 8A16383C445FDABF21BDBAC3825E8133) f:\dd\externalapis\windows\8.1\sdk\inc\evntprov.h +BIG-NEXT: - (MD5: CA7D066706A198EA5999B084AAB0CE58) f:\dd\externalapis\windows\8.1\sdk\inc\guiddef.h +BIG-NEXT: - (MD5: F9FC1E83CBE1A51209ED1C05BB0F70B2) f:\dd\externalapis\windows\8.1\sdk\inc\winuser.h +BIG-NEXT: - (MD5: A40485987BE01BAF5F57569A41DAB837) f:\dd\vctools\crt\vcruntime\inc\vcruntime_new.h +BIG-NEXT: - (MD5: 377E41F4DAE6F93EA819B4EFCF229F08) f:\dd\externalapis\unifiedcrt\inc\string.h +BIG-NEXT: - (MD5: 96C01EE8E4C01B90601D93353838EBF8) f:\dd\externalapis\unifiedcrt\inc\corecrt_memory.h +BIG-NEXT: - (MD5: A5976652B404EDDDBDA326FF9A9488A3) f:\dd\externalapis\unifiedcrt\inc\corecrt_memcpy_s.h +BIG-NEXT: Mod 0027 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\exe_main.obj`: +BIG-NEXT: - (MD5: 928553F8BA198C9030B65FA10B6B3DD2) f:\dd\externalapis\unifiedcrt\inc\malloc.h +BIG-NEXT: - (MD5: 493F2CAB7A6BE4175748A9FC6C4A38FB) f:\dd\externalapis\windows\8.1\sdk\inc\basetsd.h +BIG-NEXT: - (MD5: E4963431577926D9BA190CD6C10F8743) f:\dd\vctools\crt\vcruntime\inc\i386\xmmintrin.h +BIG-NEXT: - (MD5: B71A807A307A52C400179EF5D3FAA1A7) f:\dd\vctools\crt\vcstartup\src\startup\exe_main.cpp +BIG-NEXT: - (MD5: C3412F163DF064CCDEF8CFBE0A387550) f:\dd\externalapis\windows\8.1\sdk\inc\winbase.h +BIG-NEXT: - (MD5: 23CC88BD1D9451C2CE5F824306E16E4D) f:\dd\externalapis\unifiedcrt\inc\math.h +BIG-NEXT: - (MD5: 2D5E699DF1BED89FCCCCCF0DCFC49050) f:\dd\externalapis\unifiedcrt\inc\stdio.h +BIG-NEXT: - (MD5: 2443DB19DCC585E308F60DAFEF1D4C4C) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstdio.h +BIG-NEXT: - (MD5: 79921ECB03C5C56E28D771ADF8910FD8) f:\dd\externalapis\unifiedcrt\inc\corecrt_stdio_config.h +BIG-NEXT: - (MD5: C44C7E39EE3B3A4EF6B3211EC0110AA8) f:\dd\externalapis\unifiedcrt\inc\stdlib.h +BIG-NEXT: - (MD5: DCC558DEFD73C17745F94CC5A98632D9) f:\dd\externalapis\windows\8.1\sdk\inc\stralign.h +BIG-NEXT: - (MD5: ADDFD8BEB612E9A30D5FB7C44F9F3D37) f:\dd\externalapis\windows\8.1\sdk\inc\winnt.h +BIG-NEXT: - (MD5: 386A22AB644E999820C7C22FCE5DB574) f:\dd\externalapis\unifiedcrt\inc\ctype.h +BIG-NEXT: - (MD5: CA7D066706A198EA5999B084AAB0CE58) f:\dd\externalapis\windows\8.1\sdk\inc\guiddef.h +BIG-NEXT: - (MD5: 2D923CBDE24BB8F217FE09A5F7D88929) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstring.h +BIG-NEXT: - (MD5: B38ACA278420B7C5F25A50AD159CACA0) f:\dd\externalapis\windows\8.1\sdk\inc\winerror.h +BIG-NEXT: - (MD5: 36A3069CD09EC9F92668000F200D5545) f:\dd\vctools\crt\vcstartup\src\startup\exe_common.inl +BIG-NEXT: - (MD5: 7C388EF80868D8301B5A908485637FEE) f:\dd\vctools\crt\vcstartup\inc\vcstartup_internal.h +BIG-NEXT: - (MD5: 377E41F4DAE6F93EA819B4EFCF229F08) f:\dd\externalapis\unifiedcrt\inc\string.h +BIG-NEXT: - (MD5: 96C01EE8E4C01B90601D93353838EBF8) f:\dd\externalapis\unifiedcrt\inc\corecrt_memory.h +BIG-NEXT: - (MD5: A5976652B404EDDDBDA326FF9A9488A3) f:\dd\externalapis\unifiedcrt\inc\corecrt_memcpy_s.h +BIG-NEXT: - (MD5: 9393435BC7FDE9F624E309D56629171A) f:\dd\vctools\crt\vcruntime\inc\internal_shared.h +BIG-NEXT: - (MD5: A40485987BE01BAF5F57569A41DAB837) f:\dd\vctools\crt\vcruntime\inc\vcruntime_new.h +BIG-NEXT: - (MD5: 8A16383C445FDABF21BDBAC3825E8133) f:\dd\externalapis\windows\8.1\sdk\inc\evntprov.h +BIG-NEXT: - (MD5: 303C50A7BC924CD426BAA20C7F16192C) f:\dd\vctools\crt\vcruntime\inc\vadefs.h +BIG-NEXT: - (MD5: F9FC1E83CBE1A51209ED1C05BB0F70B2) f:\dd\externalapis\windows\8.1\sdk\inc\winuser.h +BIG-NEXT: Mod 0028 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\initializers.obj`: +BIG-NEXT: - (MD5: 928553F8BA198C9030B65FA10B6B3DD2) f:\dd\externalapis\unifiedcrt\inc\malloc.h +BIG-NEXT: - (MD5: 493F2CAB7A6BE4175748A9FC6C4A38FB) f:\dd\externalapis\windows\8.1\sdk\inc\basetsd.h +BIG-NEXT: - (MD5: E4963431577926D9BA190CD6C10F8743) f:\dd\vctools\crt\vcruntime\inc\i386\xmmintrin.h +BIG-NEXT: - (MD5: C3412F163DF064CCDEF8CFBE0A387550) f:\dd\externalapis\windows\8.1\sdk\inc\winbase.h +BIG-NEXT: - (MD5: 23CC88BD1D9451C2CE5F824306E16E4D) f:\dd\externalapis\unifiedcrt\inc\math.h +BIG-NEXT: - (MD5: C44C7E39EE3B3A4EF6B3211EC0110AA8) f:\dd\externalapis\unifiedcrt\inc\stdlib.h +BIG-NEXT: - (MD5: DCC558DEFD73C17745F94CC5A98632D9) f:\dd\externalapis\windows\8.1\sdk\inc\stralign.h +BIG-NEXT: - (MD5: ADDFD8BEB612E9A30D5FB7C44F9F3D37) f:\dd\externalapis\windows\8.1\sdk\inc\winnt.h +BIG-NEXT: - (MD5: 386A22AB644E999820C7C22FCE5DB574) f:\dd\externalapis\unifiedcrt\inc\ctype.h +BIG-NEXT: - (MD5: CA7D066706A198EA5999B084AAB0CE58) f:\dd\externalapis\windows\8.1\sdk\inc\guiddef.h +BIG-NEXT: - (MD5: 2D923CBDE24BB8F217FE09A5F7D88929) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstring.h +BIG-NEXT: - (MD5: B38ACA278420B7C5F25A50AD159CACA0) f:\dd\externalapis\windows\8.1\sdk\inc\winerror.h +BIG-NEXT: - (MD5: 7C388EF80868D8301B5A908485637FEE) f:\dd\vctools\crt\vcstartup\inc\vcstartup_internal.h +BIG-NEXT: - (MD5: 377E41F4DAE6F93EA819B4EFCF229F08) f:\dd\externalapis\unifiedcrt\inc\string.h +BIG-NEXT: - (MD5: 96C01EE8E4C01B90601D93353838EBF8) f:\dd\externalapis\unifiedcrt\inc\corecrt_memory.h +BIG-NEXT: - (MD5: A5976652B404EDDDBDA326FF9A9488A3) f:\dd\externalapis\unifiedcrt\inc\corecrt_memcpy_s.h +BIG-NEXT: - (MD5: 9393435BC7FDE9F624E309D56629171A) f:\dd\vctools\crt\vcruntime\inc\internal_shared.h +BIG-NEXT: - (MD5: A40485987BE01BAF5F57569A41DAB837) f:\dd\vctools\crt\vcruntime\inc\vcruntime_new.h +BIG-NEXT: - (MD5: 8A16383C445FDABF21BDBAC3825E8133) f:\dd\externalapis\windows\8.1\sdk\inc\evntprov.h +BIG-NEXT: - (MD5: F9FC1E83CBE1A51209ED1C05BB0F70B2) f:\dd\externalapis\windows\8.1\sdk\inc\winuser.h +BIG-NEXT: Mod 0029 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\utility.obj`: +BIG-NEXT: - (MD5: 928553F8BA198C9030B65FA10B6B3DD2) f:\dd\externalapis\unifiedcrt\inc\malloc.h +BIG-NEXT: - (MD5: 493F2CAB7A6BE4175748A9FC6C4A38FB) f:\dd\externalapis\windows\8.1\sdk\inc\basetsd.h +BIG-NEXT: - (MD5: E4963431577926D9BA190CD6C10F8743) f:\dd\vctools\crt\vcruntime\inc\i386\xmmintrin.h +BIG-NEXT: - (MD5: 2D42DDF1AAE9B3491E4BB346255346D5) f:\dd\vctools\crt\vcstartup\src\utility\utility.cpp +BIG-NEXT: - (MD5: C3412F163DF064CCDEF8CFBE0A387550) f:\dd\externalapis\windows\8.1\sdk\inc\winbase.h +BIG-NEXT: - (MD5: 23CC88BD1D9451C2CE5F824306E16E4D) f:\dd\externalapis\unifiedcrt\inc\math.h +BIG-NEXT: - (MD5: C44C7E39EE3B3A4EF6B3211EC0110AA8) f:\dd\externalapis\unifiedcrt\inc\stdlib.h +BIG-NEXT: - (MD5: DCC558DEFD73C17745F94CC5A98632D9) f:\dd\externalapis\windows\8.1\sdk\inc\stralign.h +BIG-NEXT: - (MD5: ADDFD8BEB612E9A30D5FB7C44F9F3D37) f:\dd\externalapis\windows\8.1\sdk\inc\winnt.h +BIG-NEXT: - (MD5: 386A22AB644E999820C7C22FCE5DB574) f:\dd\externalapis\unifiedcrt\inc\ctype.h +BIG-NEXT: - (MD5: CA7D066706A198EA5999B084AAB0CE58) f:\dd\externalapis\windows\8.1\sdk\inc\guiddef.h +BIG-NEXT: - (MD5: 2D923CBDE24BB8F217FE09A5F7D88929) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstring.h +BIG-NEXT: - (MD5: B38ACA278420B7C5F25A50AD159CACA0) f:\dd\externalapis\windows\8.1\sdk\inc\winerror.h +BIG-NEXT: - (MD5: 7C388EF80868D8301B5A908485637FEE) f:\dd\vctools\crt\vcstartup\inc\vcstartup_internal.h +BIG-NEXT: - (MD5: 377E41F4DAE6F93EA819B4EFCF229F08) f:\dd\externalapis\unifiedcrt\inc\string.h +BIG-NEXT: - (MD5: 96C01EE8E4C01B90601D93353838EBF8) f:\dd\externalapis\unifiedcrt\inc\corecrt_memory.h +BIG-NEXT: - (MD5: A5976652B404EDDDBDA326FF9A9488A3) f:\dd\externalapis\unifiedcrt\inc\corecrt_memcpy_s.h +BIG-NEXT: - (MD5: 9393435BC7FDE9F624E309D56629171A) f:\dd\vctools\crt\vcruntime\inc\internal_shared.h +BIG-NEXT: - (MD5: A40485987BE01BAF5F57569A41DAB837) f:\dd\vctools\crt\vcruntime\inc\vcruntime_new.h +BIG-NEXT: - (MD5: F9FC1E83CBE1A51209ED1C05BB0F70B2) f:\dd\externalapis\windows\8.1\sdk\inc\winuser.h +BIG-NEXT: Mod 0030 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\ucrt_stubs.obj`: +BIG-NEXT: - (MD5: 20976B3B6CD70F2DF77312D18D9C8D32) f:\dd\vctools\crt\vcstartup\src\utility\ucrt_stubs.cpp +BIG-NEXT: Mod 0031 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\utility_desktop.obj`: +BIG-NEXT: - (MD5: 928553F8BA198C9030B65FA10B6B3DD2) f:\dd\externalapis\unifiedcrt\inc\malloc.h +BIG-NEXT: - (MD5: 493F2CAB7A6BE4175748A9FC6C4A38FB) f:\dd\externalapis\windows\8.1\sdk\inc\basetsd.h +BIG-NEXT: - (MD5: E4963431577926D9BA190CD6C10F8743) f:\dd\vctools\crt\vcruntime\inc\i386\xmmintrin.h +BIG-NEXT: - (MD5: CC9AAE4BAA114C08FFC7F1515EC09E4C) f:\dd\vctools\crt\vcstartup\src\utility\utility_desktop.cpp +BIG-NEXT: - (MD5: C3412F163DF064CCDEF8CFBE0A387550) f:\dd\externalapis\windows\8.1\sdk\inc\winbase.h +BIG-NEXT: - (MD5: 23CC88BD1D9451C2CE5F824306E16E4D) f:\dd\externalapis\unifiedcrt\inc\math.h +BIG-NEXT: - (MD5: C44C7E39EE3B3A4EF6B3211EC0110AA8) f:\dd\externalapis\unifiedcrt\inc\stdlib.h +BIG-NEXT: - (MD5: DCC558DEFD73C17745F94CC5A98632D9) f:\dd\externalapis\windows\8.1\sdk\inc\stralign.h +BIG-NEXT: - (MD5: ADDFD8BEB612E9A30D5FB7C44F9F3D37) f:\dd\externalapis\windows\8.1\sdk\inc\winnt.h +BIG-NEXT: - (MD5: 386A22AB644E999820C7C22FCE5DB574) f:\dd\externalapis\unifiedcrt\inc\ctype.h +BIG-NEXT: - (MD5: CA7D066706A198EA5999B084AAB0CE58) f:\dd\externalapis\windows\8.1\sdk\inc\guiddef.h +BIG-NEXT: - (MD5: 2D923CBDE24BB8F217FE09A5F7D88929) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstring.h +BIG-NEXT: - (MD5: B38ACA278420B7C5F25A50AD159CACA0) f:\dd\externalapis\windows\8.1\sdk\inc\winerror.h +BIG-NEXT: - (MD5: 7C388EF80868D8301B5A908485637FEE) f:\dd\vctools\crt\vcstartup\inc\vcstartup_internal.h +BIG-NEXT: - (MD5: 377E41F4DAE6F93EA819B4EFCF229F08) f:\dd\externalapis\unifiedcrt\inc\string.h +BIG-NEXT: - (MD5: 96C01EE8E4C01B90601D93353838EBF8) f:\dd\externalapis\unifiedcrt\inc\corecrt_memory.h +BIG-NEXT: - (MD5: A5976652B404EDDDBDA326FF9A9488A3) f:\dd\externalapis\unifiedcrt\inc\corecrt_memcpy_s.h +BIG-NEXT: - (MD5: 9393435BC7FDE9F624E309D56629171A) f:\dd\vctools\crt\vcruntime\inc\internal_shared.h +BIG-NEXT: - (MD5: A40485987BE01BAF5F57569A41DAB837) f:\dd\vctools\crt\vcruntime\inc\vcruntime_new.h +BIG-NEXT: - (MD5: F9FC1E83CBE1A51209ED1C05BB0F70B2) f:\dd\externalapis\windows\8.1\sdk\inc\winuser.h +BIG-NEXT: Mod 0032 | `f:\dd\vctools\crt\vcstartup\build\md\msvcrt_kernel32\obj1r\i386\default_precision.obj`: +BIG-NEXT: - (MD5: 377E41F4DAE6F93EA819B4EFCF229F08) f:\dd\externalapis\unifiedcrt\inc\string.h +BIG-NEXT: - (MD5: 96C01EE8E4C01B90601D93353838EBF8) f:\dd\externalapis\unifiedcrt\inc\corecrt_memory.h +BIG-NEXT: - (MD5: A5976652B404EDDDBDA326FF9A9488A3) f:\dd\externalapis\unifiedcrt\inc\corecrt_memcpy_s.h +BIG-NEXT: - (MD5: 9621B7E7C6A138B5185711F98CCC568E) f:\dd\vctools\crt\vcstartup\src\defaults\default_precision.cpp +BIG-NEXT: - (MD5: 9393435BC7FDE9F624E309D56629171A) f:\dd\vctools\crt\vcruntime\inc\internal_shared.h +BIG-NEXT: - (MD5: A40485987BE01BAF5F57569A41DAB837) f:\dd\vctools\crt\vcruntime\inc\vcruntime_new.h +BIG-NEXT: - (MD5: F9FC1E83CBE1A51209ED1C05BB0F70B2) f:\dd\externalapis\windows\8.1\sdk\inc\winuser.h +BIG-NEXT: - (MD5: 928553F8BA198C9030B65FA10B6B3DD2) f:\dd\externalapis\unifiedcrt\inc\malloc.h +BIG-NEXT: - (MD5: 493F2CAB7A6BE4175748A9FC6C4A38FB) f:\dd\externalapis\windows\8.1\sdk\inc\basetsd.h +BIG-NEXT: - (MD5: E4963431577926D9BA190CD6C10F8743) f:\dd\vctools\crt\vcruntime\inc\i386\xmmintrin.h +BIG-NEXT: - (MD5: C3412F163DF064CCDEF8CFBE0A387550) f:\dd\externalapis\windows\8.1\sdk\inc\winbase.h +BIG-NEXT: - (MD5: 7C388EF80868D8301B5A908485637FEE) f:\dd\vctools\crt\vcstartup\inc\vcstartup_internal.h +BIG-NEXT: - (MD5: 23CC88BD1D9451C2CE5F824306E16E4D) f:\dd\externalapis\unifiedcrt\inc\math.h +BIG-NEXT: - (MD5: C44C7E39EE3B3A4EF6B3211EC0110AA8) f:\dd\externalapis\unifiedcrt\inc\stdlib.h +BIG-NEXT: - (MD5: DCC558DEFD73C17745F94CC5A98632D9) f:\dd\externalapis\windows\8.1\sdk\inc\stralign.h +BIG-NEXT: - (MD5: ADDFD8BEB612E9A30D5FB7C44F9F3D37) f:\dd\externalapis\windows\8.1\sdk\inc\winnt.h +BIG-NEXT: - (MD5: 386A22AB644E999820C7C22FCE5DB574) f:\dd\externalapis\unifiedcrt\inc\ctype.h +BIG-NEXT: - (MD5: CA7D066706A198EA5999B084AAB0CE58) f:\dd\externalapis\windows\8.1\sdk\inc\guiddef.h +BIG-NEXT: - (MD5: 2D923CBDE24BB8F217FE09A5F7D88929) f:\dd\externalapis\unifiedcrt\inc\corecrt_wstring.h +BIG-NEXT: - (MD5: B38ACA278420B7C5F25A50AD159CACA0) f:\dd\externalapis\windows\8.1\sdk\inc\winerror.h +BIG-NEXT: Mod 0033 | `Import:KERNEL32.dll`: +BIG-NEXT: Mod 0034 | `KERNEL32.dll`: +BIG-NEXT: Mod 0035 | `Import:VCRUNTIME140.dll`: +BIG-NEXT: Mod 0036 | `VCRUNTIME140.dll`: +BIG-NEXT: Mod 0037 | `Import:api-ms-win-crt-stdio-l1-1-0.dll`: +BIG-NEXT: Mod 0038 | `api-ms-win-crt-stdio-l1-1-0.dll`: +BIG-NEXT: Mod 0039 | `Import:api-ms-win-crt-runtime-l1-1-0.dll`: +BIG-NEXT: Mod 0040 | `api-ms-win-crt-runtime-l1-1-0.dll`: +BIG-NEXT: Mod 0041 | `Import:api-ms-win-crt-math-l1-1-0.dll`: +BIG-NEXT: Mod 0042 | `api-ms-win-crt-math-l1-1-0.dll`: +BIG-NEXT: Mod 0043 | `Import:api-ms-win-crt-locale-l1-1-0.dll`: +BIG-NEXT: Mod 0044 | `api-ms-win-crt-locale-l1-1-0.dll`: +BIG-NEXT: Mod 0045 | `Import:api-ms-win-crt-heap-l1-1-0.dll`: +BIG-NEXT: Mod 0046 | `api-ms-win-crt-heap-l1-1-0.dll`: +BIG-NEXT: Mod 0047 | `* Linker *`: + +BAD-BLOCK-SIZE: Native PDB Error: The PDB file is corrupt. Does not contain superblock diff --git a/test/DebugInfo/PDB/pdbdump-merge-ids-and-types.test b/test/DebugInfo/PDB/pdbdump-merge-ids-and-types.test index 2639490f542a..f25e9024453b 100644 --- a/test/DebugInfo/PDB/pdbdump-merge-ids-and-types.test +++ b/test/DebugInfo/PDB/pdbdump-merge-ids-and-types.test @@ -1,65 +1,51 @@ ; RUN: llvm-pdbutil yaml2pdb -pdb=%t.1.pdb %p/Inputs/merge-ids-and-types-1.yaml ; RUN: llvm-pdbutil yaml2pdb -pdb=%t.2.pdb %p/Inputs/merge-ids-and-types-2.yaml ; RUN: llvm-pdbutil merge -pdb=%t.3.pdb %t.1.pdb %t.2.pdb -; RUN: llvm-pdbutil raw -tpi-records %t.3.pdb | FileCheck -check-prefix=TPI-TYPES %s -; RUN: llvm-pdbutil raw -tpi-records %t.3.pdb | FileCheck -check-prefix=INTMAIN %s -; RUN: llvm-pdbutil raw -tpi-records %t.3.pdb | FileCheck -check-prefix=VOIDMAIN %s -; RUN: llvm-pdbutil raw -ipi-records %t.3.pdb | FileCheck -check-prefix=IPI-TYPES %s -; RUN: llvm-pdbutil raw -ipi-records %t.3.pdb | FileCheck -check-prefix=IPI-NAMES %s -; RUN: llvm-pdbutil raw -ipi-records %t.3.pdb | FileCheck -check-prefix=IPI-UDT %s +; RUN: llvm-pdbutil raw -types %t.3.pdb | FileCheck -check-prefix=TPI-TYPES %s +; RUN: llvm-pdbutil raw -ids %t.3.pdb | FileCheck -check-prefix=IPI-TYPES %s -TPI-TYPES: Type Info Stream (TPI) -TPI-TYPES: Record count: 9 -TPI-TYPES-DAG: TypeLeafKind: LF_POINTER -TPI-TYPES-DAG: TypeLeafKind: LF_FIELDLIST -TPI-TYPES-DAG: TypeLeafKind: LF_ARGLIST -TPI-TYPES-DAG: TypeLeafKind: LF_STRUCTURE -TPI-TYPES-DAG: TypeLeafKind: LF_MEMBER -TPI-TYPES-DAG: TypeLeafKind: LF_POINTER -TPI-TYPES-DAG: TypeLeafKind: LF_ARGLIST -TPI-TYPES-DAG: TypeLeafKind: LF_MFUNCTION -TPI-TYPES-DAG: TypeLeafKind: LF_PROCEDURE -TPI-TYPES-DAG: TypeLeafKind: LF_PROCEDURE -TPI-TYPES-DAG: TypeLeafKind: LF_ARGLIST +TPI-TYPES: Types (TPI Stream) +TPI-TYPES-NEXT: ============================================================ +TPI-TYPES-NEXT: Showing 9 records +TPI-TYPES-NEXT: 0x1000 | LF_POINTER [size = 12] +TPI-TYPES-NEXT: referent = 0x0470 (char*), mode = pointer, opts = None, kind = ptr32 +TPI-TYPES-NEXT: 0x1001 | LF_FIELDLIST [size = 24] +TPI-TYPES-NEXT: - LF_MEMBER [name = `FooMember`, Type = 0x0403 (void*), offset = 0, attrs = public] +TPI-TYPES-NEXT: 0x1002 | LF_ARGLIST [size = 16] +TPI-TYPES-NEXT: 0x0074 (int): `int` +TPI-TYPES-NEXT: 0x1000: `char**` +TPI-TYPES-NEXT: 0x1003 | LF_STRUCTURE [size = 36] +TPI-TYPES-NEXT: class name: `FooBar` +TPI-TYPES-NEXT: unique name: `FooBar` +TPI-TYPES-NEXT: vtable: <no type>, base list: <no type>, field list: 0x1001 +TPI-TYPES-NEXT: options: has unique name +TPI-TYPES-NEXT: 0x1004 | LF_POINTER [size = 12] +TPI-TYPES-NEXT: referent = 0x1003, mode = pointer, opts = None, kind = ptr32 +TPI-TYPES-NEXT: 0x1005 | LF_ARGLIST [size = 12] +TPI-TYPES-NEXT: 0x0074 (int): `int` +TPI-TYPES-NEXT: 0x1006 | LF_MFUNCTION [size = 28] +TPI-TYPES-NEXT: return type = 1, # args = 0x1005, param list = 0x0003 (void) +TPI-TYPES-NEXT: class type = 0x1003, this type = 0x1004, this adjust = 0 +TPI-TYPES-NEXT: calling conv = thiscall, options = constructor +TPI-TYPES-NEXT: 0x1007 | LF_PROCEDURE [size = 16] +TPI-TYPES-NEXT: return type = 0x0074 (int), # args = 2, param list = 0x1002 +TPI-TYPES-NEXT: calling conv = cdecl, options = None +TPI-TYPES-NEXT: 0x1008 | LF_PROCEDURE [size = 16] +TPI-TYPES-NEXT: return type = 0x0003 (void), # args = 2, param list = 0x1002 +TPI-TYPES-NEXT: calling conv = cdecl, options = None -; Both procedures should use the same arglist even though they have a different -; return type. -INTMAIN: ArgList ([[ID:.*]]) -INTMAIN-NEXT: TypeLeafKind: LF_ARGLIST -INTMAIN-NEXT: NumArgs: 2 -INTMAIN-NEXT: Arguments [ -INTMAIN-NEXT: ArgType: int -INTMAIN-NEXT: ArgType: char** -INTMAIN: TypeLeafKind: LF_PROCEDURE -INTMAIN: ReturnType: int -INTMAIN: NumParameters: 2 -INTMAIN-NEXT: ArgListType: (int, char**) ([[ID]]) - -VOIDMAIN: ArgList ([[ID:.*]]) -VOIDMAIN-NEXT: TypeLeafKind: LF_ARGLIST -VOIDMAIN-NEXT: NumArgs: 2 -VOIDMAIN-NEXT: Arguments [ -VOIDMAIN-NEXT: ArgType: int -VOIDMAIN-NEXT: ArgType: char** -VOIDMAIN: TypeLeafKind: LF_PROCEDURE -VOIDMAIN: ReturnType: void -VOIDMAIN: NumParameters: 2 -VOIDMAIN-NEXT: ArgListType: (int, char**) ([[ID]]) - -IPI-TYPES: Type Info Stream (IPI) -IPI-TYPES: Record count: 6 -IPI-TYPES-DAG: TypeLeafKind: LF_FUNC_ID -IPI-TYPES-DAG: TypeLeafKind: LF_MFUNC_ID -IPI-TYPES-DAG: TypeLeafKind: LF_UDT_MOD_SRC_LINE -IPI-TYPES-DAG: TypeLeafKind: LF_FUNC_ID -IPI-TYPES-DAG: TypeLeafKind: LF_FUNC_ID -IPI-TYPES-DAG: TypeLeafKind: LF_MFUNC_ID - -IPI-NAMES-DAG: Name: main -IPI-NAMES-DAG: Name: FooMethod -IPI-NAMES-DAG: Name: main2 -IPI-NAMES-DAG: Name: foo -IPI-NAMES-DAG: Name: FooMethod2 - -IPI-UDT: TypeLeafKind: LF_UDT_MOD_SRC_LINE -IPI-UDT-NEXT: UDT: FooBar +IPI-TYPES: Types (IPI Stream) +IPI-TYPES-NEXT: ============================================================ +IPI-TYPES-NEXT: Showing 6 records +IPI-TYPES-NEXT: 0x1000 | LF_FUNC_ID [size = 20] +IPI-TYPES-NEXT: name = main, type = 0x1007, parent scope = <no type> +IPI-TYPES-NEXT: 0x1001 | LF_MFUNC_ID [size = 24] +IPI-TYPES-NEXT: name = FooMethod, type = 0x1006, class type = 0x1003 +IPI-TYPES-NEXT: 0x1002 | LF_UDT_MOD_SRC_LINE [size = 20] +IPI-TYPES-NEXT: udt = 0x1003, mod = 0, file = 0, line = 0 +IPI-TYPES-NEXT: 0x1003 | LF_FUNC_ID [size = 20] +IPI-TYPES-NEXT: name = main2, type = 0x1007, parent scope = <no type> +IPI-TYPES-NEXT: 0x1004 | LF_FUNC_ID [size = 16] +IPI-TYPES-NEXT: name = foo, type = 0x1008, parent scope = <no type> +IPI-TYPES-NEXT: 0x1005 | LF_MFUNC_ID [size = 24] +IPI-TYPES-NEXT: name = FooMethod2, type = 0x1006, class type = 0x1003 diff --git a/test/DebugInfo/PDB/pdbdump-mergeids.test b/test/DebugInfo/PDB/pdbdump-mergeids.test index 1c0a8704af2a..441ce4d8dbc8 100644 --- a/test/DebugInfo/PDB/pdbdump-mergeids.test +++ b/test/DebugInfo/PDB/pdbdump-mergeids.test @@ -1,31 +1,24 @@ ; RUN: llvm-pdbutil yaml2pdb -pdb=%t.1.pdb %p/Inputs/merge-ids-1.yaml ; RUN: llvm-pdbutil yaml2pdb -pdb=%t.2.pdb %p/Inputs/merge-ids-2.yaml ; RUN: llvm-pdbutil merge -pdb=%t.3.pdb %t.1.pdb %t.2.pdb -; RUN: llvm-pdbutil raw -ipi-records %t.3.pdb | FileCheck -check-prefix=MERGED %s -; RUN: llvm-pdbutil raw -ipi-records %t.3.pdb | FileCheck -check-prefix=SUBSTRS %s -; RUN: llvm-pdbutil raw -tpi-records %t.3.pdb | FileCheck -check-prefix=TPI-EMPTY %s +; RUN: llvm-pdbutil raw -ids %t.3.pdb | FileCheck -check-prefix=MERGED %s +; RUN: llvm-pdbutil raw -types %t.3.pdb | FileCheck -check-prefix=TPI-EMPTY %s -MERGED: Type Info Stream (IPI) -MERGED: Record count: 8 -MERGED-DAG: StringData: One -MERGED-DAG: StringData: Two -MERGED-DAG: StringData: SubOne -MERGED-DAG: StringData: SubTwo -MERGED-DAG: StringData: Main -MERGED-DAG: TypeLeafKind: LF_SUBSTR_LIST -MERGED-DAG: StringData: OnlyInFirst -MERGED-DAG: StringData: OnlyInSecond +MERGED: Types (IPI Stream) +MERGED-NEXT: ============================================================ +MERGED-NEXT: Showing 8 records +MERGED-NEXT: 0x1000 | LF_STRING_ID [size = 12] ID: <no type>, String: One +MERGED-NEXT: 0x1001 | LF_STRING_ID [size = 12] ID: <no type>, String: Two +MERGED-NEXT: 0x1002 | LF_STRING_ID [size = 20] ID: <no type>, String: OnlyInFirst +MERGED-NEXT: 0x1003 | LF_STRING_ID [size = 16] ID: <no type>, String: SubOne +MERGED-NEXT: 0x1004 | LF_STRING_ID [size = 16] ID: <no type>, String: SubTwo +MERGED-NEXT: 0x1005 | LF_SUBSTR_LIST [size = 16] +MERGED-NEXT: 0x1003: `SubOne` +MERGED-NEXT: 0x1004: `SubTwo` +MERGED-NEXT: 0x1006 | LF_STRING_ID [size = 16] ID: 0x1005, String: Main +MERGED-NEXT: 0x1007 | LF_STRING_ID [size = 24] ID: <no type>, String: OnlyInSecond -SUBSTRS: StringList -SUBSTRS: TypeLeafKind: LF_SUBSTR_LIST -SUBSTRS-NEXT: NumStrings: 2 -SUBSTRS-NEXT: Strings [ -SUBSTRS-NEXT: SubOne -SUBSTRS-NEXT: SubTwo -SUBSTRS: StringId -SUBSTRS-NEXT: TypeLeafKind: LF_STRING_ID -SUBSTRS-NEXT: Id: "SubOne" "SubTwo" -SUBSTRS-NEXT: StringData: Main - -TPI-EMPTY: Record count: 0 +TPI-EMPTY: Types (TPI Stream) +TPI-EMPTY-NEXT: ============================================================ +TPI-EMPTY-NEXT: Showing 0 records diff --git a/test/DebugInfo/PDB/pdbdump-mergetypes.test b/test/DebugInfo/PDB/pdbdump-mergetypes.test index 8d32b4d176f2..9aae40543697 100644 --- a/test/DebugInfo/PDB/pdbdump-mergetypes.test +++ b/test/DebugInfo/PDB/pdbdump-mergetypes.test @@ -1,24 +1,36 @@ -; RUN: llvm-pdbutil yaml2pdb -pdb=%t.1.pdb %p/Inputs/merge-types-1.yaml
-; RUN: llvm-pdbutil yaml2pdb -pdb=%t.2.pdb %p/Inputs/merge-types-2.yaml
-; RUN: llvm-pdbutil merge -pdb=%t.3.pdb %t.1.pdb %t.2.pdb
-; RUN: llvm-pdbutil raw -tpi-records %t.3.pdb | FileCheck -check-prefix=MERGED %s
-; RUN: llvm-pdbutil raw -tpi-records %t.3.pdb | FileCheck -check-prefix=ARGLIST %s
-
-
-MERGED: Type Info Stream (TPI)
-MERGED: Record count: 9
-MERGED-DAG: PointeeType: unsigned
-MERGED-DAG: PointeeType: unsigned*
-MERGED-DAG: PointeeType: unsigned**
-MERGED-DAG: PointeeType: __int64
-MERGED-DAG: PointeeType: __int64*
-MERGED-DAG: Name: OnlyInMerge1
-MERGED-DAG: Name: OnlyInMerge2
-MERGED-DAG: TypeLeafKind: LF_ARGLIST
-
-ARGLIST: TypeLeafKind: LF_ARGLIST
-ARGLIST-NEXT: NumArgs: 3
-ARGLIST-NEXT: Arguments [
-ARGLIST-NEXT: ArgType: unsigned
-ARGLIST-NEXT: ArgType: unsigned*
-ARGLIST-NEXT: ArgType: unsigned**
++; RUN: llvm-pdbutil yaml2pdb -pdb=%t.1.pdb %p/Inputs/merge-types-1.yaml +; RUN: llvm-pdbutil yaml2pdb -pdb=%t.2.pdb %p/Inputs/merge-types-2.yaml +; RUN: llvm-pdbutil merge -pdb=%t.3.pdb %t.1.pdb %t.2.pdb +; RUN: llvm-pdbutil raw -types %t.3.pdb | FileCheck -check-prefix=MERGED %s + + +MERGED: Types (TPI Stream) +MERGED-NEXT: ============================================================ +MERGED-NEXT: Showing 9 records +MERGED-NEXT: 0x1000 | LF_POINTER [size = 12] +MERGED-NEXT: referent = 0x0075 (unsigned), mode = pointer, opts = None, kind = ptr32 +MERGED-NEXT: 0x1001 | LF_POINTER [size = 12] +MERGED-NEXT: referent = 0x0076 (__int64), mode = pointer, opts = None, kind = ptr32 +MERGED-NEXT: 0x1002 | LF_STRUCTURE [size = 48] +MERGED-NEXT: class name: `OnlyInMerge1` +MERGED-NEXT: unique name: `OnlyInMerge1` +MERGED-NEXT: vtable: <no type>, base list: <no type>, field list: <no type> +MERGED-NEXT: options: forward ref | has unique name +MERGED-NEXT: 0x1003 | LF_POINTER [size = 12] +MERGED-NEXT: referent = 0x1000, mode = pointer, opts = None, kind = ptr32 +MERGED-NEXT: 0x1004 | LF_POINTER [size = 12] +MERGED-NEXT: referent = 0x1003, mode = pointer, opts = None, kind = ptr32 +MERGED-NEXT: 0x1005 | LF_POINTER [size = 12] +MERGED-NEXT: referent = 0x1001, mode = pointer, opts = None, kind = ptr32 +MERGED-NEXT: 0x1006 | LF_ARGLIST [size = 20] +MERGED-NEXT: 0x0075 (unsigned): `unsigned` +MERGED-NEXT: 0x1000: `unsigned*` +MERGED-NEXT: 0x1003: `unsigned**` +MERGED-NEXT: 0x1007 | LF_PROCEDURE [size = 16] +MERGED-NEXT: return type = 0x0075 (unsigned), # args = 0, param list = 0x1006 +MERGED-NEXT: calling conv = cdecl, options = None +MERGED-NEXT: 0x1008 | LF_STRUCTURE [size = 48] +MERGED-NEXT: class name: `OnlyInMerge2` +MERGED-NEXT: unique name: `OnlyInMerge2` +MERGED-NEXT: vtable: <no type>, base list: <no type>, field list: <no type> +MERGED-NEXT: options: forward ref | has unique name diff --git a/test/DebugInfo/PDB/pdbdump-raw-blocks.test b/test/DebugInfo/PDB/pdbdump-raw-blocks.test index 14e1f86fc029..b695d5a1c4cd 100644 --- a/test/DebugInfo/PDB/pdbdump-raw-blocks.test +++ b/test/DebugInfo/PDB/pdbdump-raw-blocks.test @@ -1,35 +1,29 @@ -; RUN: llvm-pdbutil raw -block-data=0 %p/Inputs/empty.pdb | FileCheck --check-prefix=BLOCK0 %s
-; RUN: llvm-pdbutil raw -block-data=0-1 %p/Inputs/empty.pdb | FileCheck --check-prefix=BLOCK01 %s
-; RUN: not llvm-pdbutil raw -block-data=0,1 %p/Inputs/empty.pdb 2>&1 | FileCheck --check-prefix=BADSYNTAX %s
-; RUN: not llvm-pdbutil raw -block-data=0a1 %p/Inputs/empty.pdb 2>&1 | FileCheck --check-prefix=BADSYNTAX %s
-; RUN: not llvm-pdbutil raw -block-data=0- %p/Inputs/empty.pdb 2>&1 | FileCheck --check-prefix=BADSYNTAX %s
-
-BLOCK0: Block Data {
-BLOCK0-NEXT: Block 0 (
-BLOCK0-NEXT: 0000: 4D696372 6F736F66 7420432F 432B2B20 |Microsoft C/C++ |
-BLOCK0-NEXT: 0010: 4D534620 372E3030 0D0A1A44 53000000 |MSF 7.00...DS...|
-BLOCK0-NEXT: 0020: 00100000 02000000 19000000 88000000 |................|
-BLOCK0-NEXT: 0030: 00000000 18000000 00000000 00000000 |................|
-BLOCK0: 0FE0: 00000000 00000000 00000000 00000000 |................|
-BLOCK0-NEXT: 0FF0: 00000000 00000000 00000000 00000000 |................|
-BLOCK0-NEXT: )
-BLOCK0-NEXT: }
-
-BLOCK01: Block Data {
-BLOCK01-NEXT: Block 0 (
-BLOCK01-NEXT: 0000: 4D696372 6F736F66 7420432F 432B2B20 |Microsoft C/C++ |
-BLOCK01-NEXT: 0010: 4D534620 372E3030 0D0A1A44 53000000 |MSF 7.00...DS...|
-BLOCK01-NEXT: 0020: 00100000 02000000 19000000 88000000 |................|
-BLOCK01-NEXT: 0030: 00000000 18000000 00000000 00000000 |................|
-BLOCK01: 0FE0: 00000000 00000000 00000000 00000000 |................|
-BLOCK01-NEXT: 0FF0: 00000000 00000000 00000000 00000000 |................|
-BLOCK01-NEXT: )
-BLOCK01-NEXT: Block 1 (
-BLOCK01-NEXT: 0000: C0FCFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................|
-BLOCK01-NEXT: 0010: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................|
-BLOCK01: 0FE0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................|
-BLOCK01-NEXT: 0FF0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................|
-BLOCK01-NEXT: )
-BLOCK01-NEXT: }
-
-BADSYNTAX: Argument '{{.*}}' invalid format.
+; RUN: llvm-pdbutil raw -block-data=0 %p/Inputs/empty.pdb | FileCheck --check-prefix=BLOCK0 %s +; RUN: llvm-pdbutil raw -block-data=0-1 %p/Inputs/empty.pdb | FileCheck --check-prefix=BLOCK01 %s +; RUN: not llvm-pdbutil raw -block-data=0,1 %p/Inputs/empty.pdb 2>&1 | FileCheck --check-prefix=BADSYNTAX %s +; RUN: not llvm-pdbutil raw -block-data=0a1 %p/Inputs/empty.pdb 2>&1 | FileCheck --check-prefix=BADSYNTAX %s +; RUN: not llvm-pdbutil raw -block-data=0- %p/Inputs/empty.pdb 2>&1 | FileCheck --check-prefix=BADSYNTAX %s + +BLOCK0: MSF Blocks +BLOCK0-NEXT: ============================================================ +BLOCK0-NEXT: Block 0 ( +BLOCK0-NEXT: 0000: 4D696372 6F736F66 7420432F 432B2B20 4D534620 372E3030 0D0A1A44 53000000 |Microsoft C/C++ MSF 7.00...DS...| +BLOCK0-NEXT: 0020: 00100000 02000000 19000000 88000000 00000000 18000000 00000000 00000000 |................................| +BLOCK0-NEXT: 0040: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 |................................| +BLOCK0-NEXT: 0060: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 |................................| +BLOCK0-NOT: Block 1 ( + +BLOCK01: MSF Blocks +BLOCK01-NEXT: ============================================================ +BLOCK01-NEXT: Block 0 ( +BLOCK01-NEXT: 0000: 4D696372 6F736F66 7420432F 432B2B20 4D534620 372E3030 0D0A1A44 53000000 |Microsoft C/C++ MSF 7.00...DS...| +BLOCK01-NEXT: 0020: 00100000 02000000 19000000 88000000 00000000 18000000 00000000 00000000 |................................| +BLOCK01-NEXT: 0040: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 |................................| +BLOCK01-NEXT: 0060: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 |................................| +BLOCK01: Block 1 ( +BLOCK01-NEXT: 0000: C0FCFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................................| +BLOCK01-NEXT: 0020: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................................| +BLOCK01-NEXT: 0040: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................................| +BLOCK01-NOT: Block 2 ( + +BADSYNTAX: Argument '{{.*}}' invalid format. diff --git a/test/DebugInfo/PDB/pdbdump-raw-stream.test b/test/DebugInfo/PDB/pdbdump-raw-stream.test index 846960a0964a..2f8e05ad0583 100644 --- a/test/DebugInfo/PDB/pdbdump-raw-stream.test +++ b/test/DebugInfo/PDB/pdbdump-raw-stream.test @@ -1,23 +1,28 @@ -; RUN: llvm-pdbutil raw -stream-data=1 %p/Inputs/empty.pdb | FileCheck --check-prefix=STREAM1 %s
-; RUN: not llvm-pdbutil raw -stream-data=100 %p/Inputs/empty.pdb 2>&1 | FileCheck --check-prefix=INVALIDSTREAM %s
-
-STREAM1: Stream Data {
-STREAM1-NEXT: Stream {
-STREAM1-NEXT: Index: 1
-STREAM1-NEXT: Type: PDB Stream
-STREAM1-NEXT: Size: 118
-STREAM1-NEXT: Blocks: [19]
-STREAM1-NEXT: Data (
-STREAM1-NEXT: 0000: 942E3101 E207E554 01000000 0B355641 |..1....T.....5VA|
-STREAM1-NEXT: 0010: 86A0A249 896F9988 FAE52FF0 22000000 |...I.o..../."...|
-STREAM1-NEXT: 0020: 2F4C696E 6B496E66 6F002F6E 616D6573 |/LinkInfo./names|
-STREAM1-NEXT: 0030: 002F7372 632F6865 61646572 626C6F63 |./src/headerbloc|
-STREAM1-NEXT: 0040: 6B000300 00000600 00000100 00001A00 |k...............|
-STREAM1-NEXT: 0050: 00000000 00001100 00000900 00000A00 |................|
-STREAM1-NEXT: 0060: 00000D00 00000000 00000500 00000000 |................|
-STREAM1-NEXT: 0070: 00004191 3201 |..A.2.|
-STREAM1-NEXT: )
-STREAM1-NEXT: }
-STREAM1-NEXT: }
-
-INVALIDSTREAM: Native PDB Error: The specified stream could not be loaded.
+; RUN: llvm-pdbutil raw -stream-data=1 %p/Inputs/empty.pdb | FileCheck --check-prefix=STREAM %s +; RUN: llvm-pdbutil raw -stream-data=100 %p/Inputs/empty.pdb 2>&1 | FileCheck --check-prefix=INVALIDSTREAM %s +; RUN: llvm-pdbutil raw -stream-data=1,100 %p/Inputs/empty.pdb 2>&1 | FileCheck --check-prefix=BOTH %s + +STREAM: Stream Data +STREAM-NEXT: ============================================================ +STREAM-NEXT: Stream 1 (118 bytes): PDB Stream +STREAM-NEXT: Data ( +STREAM-NEXT: 0000: 942E3101 E207E554 01000000 0B355641 86A0A249 896F9988 FAE52FF0 22000000 |..1....T.....5VA...I.o..../."...| +STREAM-NEXT: 0020: 2F4C696E 6B496E66 6F002F6E 616D6573 002F7372 632F6865 61646572 626C6F63 |/LinkInfo./names./src/headerbloc| +STREAM-NEXT: 0040: 6B000300 00000600 00000100 00001A00 00000000 00001100 00000900 00000A00 |k...............................| +STREAM-NEXT: 0060: 00000D00 00000000 00000500 00000000 00004191 3201 |..................A.2.| +STREAM-NEXT: ) + +INVALIDSTREAM: Stream Data +INVALIDSTREAM-NEXT: ============================================================ +INVALIDSTREAM-NEXT: Stream 100: Not present + +BOTH: Stream Data +BOTH-NEXT: ============================================================ +BOTH-NEXT: Stream 1 (118 bytes): PDB Stream +BOTH-NEXT: Data ( +BOTH-NEXT: 0000: 942E3101 E207E554 01000000 0B355641 86A0A249 896F9988 FAE52FF0 22000000 |..1....T.....5VA...I.o..../."...| +BOTH-NEXT: 0020: 2F4C696E 6B496E66 6F002F6E 616D6573 002F7372 632F6865 61646572 626C6F63 |/LinkInfo./names./src/headerbloc| +BOTH-NEXT: 0040: 6B000300 00000600 00000100 00001A00 00000000 00001100 00000900 00000A00 |k...............................| +BOTH-NEXT: 0060: 00000D00 00000000 00000500 00000000 00004191 3201 |..................A.2.| +BOTH-NEXT: ) +BOTH-NEXT: Stream 100: Not present diff --git a/test/DebugInfo/PDB/pdbdump-readwrite.test b/test/DebugInfo/PDB/pdbdump-readwrite.test index ee53f3b4cd2a..51ebd754545f 100644 --- a/test/DebugInfo/PDB/pdbdump-readwrite.test +++ b/test/DebugInfo/PDB/pdbdump-readwrite.test @@ -3,48 +3,33 @@ RUN: -pdb-stream -string-table -tpi-stream -stream-directory \ RUN: -stream-metadata %p/Inputs/empty.pdb > %t.1 RUN: llvm-pdbutil yaml2pdb -pdb=%t.2 %t.1 -RUN: llvm-pdbutil raw -headers -string-table -tpi-records %p/Inputs/empty.pdb | FileCheck %s -RUN: llvm-pdbutil raw -headers -string-table -tpi-records %t.2 | FileCheck %s +RUN: llvm-pdbutil raw -summary -string-table -types %p/Inputs/empty.pdb | FileCheck %s +RUN: llvm-pdbutil raw -summary -string-table -types %t.2 | FileCheck %s -CHECK: FileHeaders { -CHECK-NEXT: BlockSize: 4096 -CHECK-NEXT: FreeBlockMap: -CHECK-NEXT: NumBlocks: -CHECK-NEXT: NumDirectoryBytes: -CHECK-NEXT: Unknown1: 0 -CHECK-NEXT: BlockMapAddr: -CHECK-NEXT: NumDirectoryBlocks: 1 -CHECK-NEXT: DirectoryBlocks: -CHECK-NEXT: NumStreams: -CHECK-NEXT: } -CHECK: String Table { -CHECK-DAG: 'd:\src\llvm\test\debuginfo\pdb\inputs\predefined c++ attributes (compiler internal)' -CHECK-DAG: 'd:\src\llvm\test\debuginfo\pdb\inputs\empty.cpp' -CHECK-DAG: '$T0 $ebp = $eip $T0 4 + ^ = $ebp $T0 ^ = $esp $T0 8 + = ' -CHECK-NEXT: } -CHECK: PDB Stream { -CHECK-NEXT: Version: 20000404 -CHECK-NEXT: Signature: 0x54E507E2 -CHECK-NEXT: Age: 1 -CHECK-NEXT: Guid: {0B355641-86A0-A249-896F-9988FAE52FF0} -CHECK-NEXT: Features: 0x1 -CHECK-NEXT: Named Streams { -CHECK: /names: -CHECK: } -CHECK-NEXT: } -CHECK: Type Info Stream (TPI) { -CHECK-NEXT: TPI Version: 20040203 -CHECK-NEXT: Record count: 75 -CHECK: DBI Stream { -CHECK-NEXT: Dbi Version: 19990903 -CHECK-NEXT: Age: 1 -CHECK-NEXT: Incremental Linking: Yes -CHECK-NEXT: Has CTypes: No -CHECK-NEXT: Is Stripped: No -CHECK-NEXT: Machine Type: x86 -CHECK-NEXT: Symbol Record Stream Index: -CHECK-NEXT: Public Symbol Stream Index: -CHECK-NEXT: Global Symbol Stream Index: -CHECK-NEXT: Toolchain Version: 12.0 -CHECK-NEXT: mspdb120.dll version: 12.0.31101 -CHECK-NEXT: } + +CHECK: Summary +CHECK-NEXT: ============================================================ +CHECK-NEXT: Block Size: 4096 +CHECK-NEXT: Number of blocks: +CHECK-NEXT: Number of streams: +CHECK-NEXT: Signature: 1424295906 +CHECK-NEXT: Age: 1 +CHECK-NEXT: GUID: {0B355641-86A0-A249-896F-9988FAE52FF0} +CHECK-NEXT: Features: 0x1 +CHECK-NEXT: Has Debug Info: true +CHECK-NEXT: Has Types: true +CHECK-NEXT: Has IDs: true +CHECK-NEXT: Has Globals: +CHECK-NEXT: Has Publics: +CHECK-NEXT: Is incrementally linked: true +CHECK-NEXT: Has conflicting types: false +CHECK-NEXT: Is stripped: false +CHECK: String Table +CHECK-NEXT: ============================================================ +CHECK-NEXT: ID | String +CHECK-NEXT: {{.*}} | 'd:\src\llvm\test\debuginfo\pdb\inputs\predefined c++ attributes (compiler internal)' +CHECK-NEXT: {{.*}} | 'd:\src\llvm\test\debuginfo\pdb\inputs\empty.cpp' +CHECK-NEXT: {{.*}} | '$T0 $ebp = $eip $T0 4 + ^ = $ebp $T0 ^ = $esp $T0 8 + = ' +CHECK: Types (TPI Stream) +CHECK-NEXT: ============================================================ +CHECK-NEXT: Showing 75 records diff --git a/test/DebugInfo/X86/block-capture.ll b/test/DebugInfo/X86/block-capture.ll index 168040507eef..14927eef59d4 100644 --- a/test/DebugInfo/X86/block-capture.ll +++ b/test/DebugInfo/X86/block-capture.ll @@ -123,7 +123,7 @@ attributes #3 = { nounwind } !66 = !DILocation(line: 2, column: 20, scope: !8) !67 = !DILocation(line: 2, column: 21, scope: !8) !68 = !DILocalVariable(name: "block", line: 2, scope: !8, file: !5, type: !25) -!69 = !DIExpression(DW_OP_deref, DW_OP_plus, 32) +!69 = !DIExpression(DW_OP_deref, DW_OP_plus_uconst, 32) !70 = !DILocation(line: 2, column: 9, scope: !8) !71 = !DILocation(line: 2, column: 23, scope: !72) !72 = distinct !DILexicalBlock(line: 2, column: 21, file: !1, scope: !8) diff --git a/test/DebugInfo/X86/debug-info-block-captured-self.ll b/test/DebugInfo/X86/debug-info-block-captured-self.ll index 1085eaef0d4e..e1620af50255 100644 --- a/test/DebugInfo/X86/debug-info-block-captured-self.ll +++ b/test/DebugInfo/X86/debug-info-block-captured-self.ll @@ -107,5 +107,5 @@ define internal void @"__24-[Main initWithContext:]_block_invoke_2"(i8* %.block_ !106 = !DILocation(line: 40, scope: !42) !107 = !DIFile(filename: "llvm/tools/clang/test/CodeGenObjC/debug-info-block-captured-self.m", directory: "") !108 = !{i32 1, !"Debug Info Version", i32 3} -!109 = !DIExpression(DW_OP_plus, 32, DW_OP_deref) -!110 = !DIExpression(DW_OP_plus, 32, DW_OP_deref) +!109 = !DIExpression(DW_OP_plus_uconst, 32, DW_OP_deref) +!110 = !DIExpression(DW_OP_plus_uconst, 32, DW_OP_deref) diff --git a/test/DebugInfo/X86/debug-info-blocks.ll b/test/DebugInfo/X86/debug-info-blocks.ll index 859eef804bb1..b79ad89be27d 100644 --- a/test/DebugInfo/X86/debug-info-blocks.ll +++ b/test/DebugInfo/X86/debug-info-blocks.ll @@ -380,4 +380,4 @@ attributes #3 = { nounwind } !108 = !DILocation(line: 61, scope: !36) !109 = !DILocation(line: 62, scope: !36) !110 = !{i32 1, !"Debug Info Version", i32 3} -!111 = !DIExpression(DW_OP_deref, DW_OP_plus, 32) +!111 = !DIExpression(DW_OP_deref, DW_OP_plus_uconst, 32) diff --git a/test/DebugInfo/X86/double-declare.ll b/test/DebugInfo/X86/double-declare.ll new file mode 100644 index 000000000000..8ed4319b323a --- /dev/null +++ b/test/DebugInfo/X86/double-declare.ll @@ -0,0 +1,44 @@ +; RUN: llc -mtriple=x86_64-apple-darwin -O0 -filetype=obj -o - < %s | llvm-dwarfdump -debug-dump=info - | FileCheck %s +; PR33157. Don't crash on duplicate dbg.declare. +; CHECK: DW_TAG_formal_parameter +; CHECK: DW_AT_location [DW_FORM_exprloc] +; CHECK-NOT: DW_AT_location +@g = external global i32 +@h = external global i32 + +declare void @llvm.dbg.declare(metadata, metadata, metadata) + +define void @f(i32* byval %p, i1 %c) !dbg !5 { + br i1 %c, label %x, label %y + +x: + call void @llvm.dbg.declare(metadata i32* %p, metadata !10, metadata !DIExpression()), !dbg !12 + store i32 42, i32* @g, !dbg !12 + br label %done + +y: + call void @llvm.dbg.declare(metadata i32* %p, metadata !10, metadata !DIExpression()), !dbg !12 + store i32 42, i32* @h, !dbg !12 + br label %done + +done: + ret void +} + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!22, !23} + +!0 = distinct !DICompileUnit(language: DW_LANG_ObjC, file: !1, producer: "clang version 5.0.0 ", isOptimized: true, runtimeVersion: 2, emissionKind: FullDebug) +!1 = !DIFile(filename: "<stdin>", directory: "C:\5Csrc\5Cllvm-project\5Cbuild") +!5 = distinct !DISubprogram(name: "f", isLocal: true, isDefinition: true, scopeLine: 37, flags: DIFlagPrototyped, isOptimized: true, unit: !0, type: !99, scope: !1) +!6 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!10 = !DILocalVariable(name: "aRect", arg: 1, scope: !11, file: !1, line: 38, type: !6) +!11 = distinct !DILexicalBlock(scope: !98, file: !1, line: 38) +!12 = !DILocation(line: 43, scope: !11, inlinedAt: !13) +!13 = distinct !DILocation(line: 43, scope: !5) +!22 = !{i32 2, !"Dwarf Version", i32 4} +!23 = !{i32 2, !"Debug Info Version", i32 3} +!62 = !{!10} +!98 = distinct !DISubprogram(name: "NSMaxX", scope: !1, file: !1, line: 27, isLocal: true, isDefinition: true, scopeLine: 27, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !62, type: !99) +!99 = !DISubroutineType(types: !100) +!100 = !{null} diff --git a/test/DebugInfo/X86/dw_op_minus.ll b/test/DebugInfo/X86/dw_op_minus.ll index 8e65b489c27b..30bf58378005 100644 --- a/test/DebugInfo/X86/dw_op_minus.ll +++ b/test/DebugInfo/X86/dw_op_minus.ll @@ -10,7 +10,7 @@ ; Capture(buf); ; } ; } -; The interesting part is !DIExpression(DW_OP_minus, 400) +; The interesting part is !DIExpression(DW_OP_constu, 400, DW_OP_minus) target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" @@ -56,7 +56,7 @@ declare void @Capture(i32*) !14 = !{i32 2, !"Debug Info Version", i32 3} !15 = !{!"clang version 3.8.0 (trunk 248518) (llvm/trunk 248512)"} !16 = !DILocation(line: 5, column: 3, scope: !4) -!17 = !DIExpression(DW_OP_minus, 400) +!17 = !DIExpression(DW_OP_constu, 400, DW_OP_minus) !18 = !DILocation(line: 5, column: 7, scope: !4) !19 = !DILocation(line: 6, column: 11, scope: !4) !20 = !DILocation(line: 6, column: 3, scope: !4) diff --git a/test/DebugInfo/X86/dw_op_minus_direct.ll b/test/DebugInfo/X86/dw_op_minus_direct.ll index 8d346be532e8..69f4b2c3ef6a 100644 --- a/test/DebugInfo/X86/dw_op_minus_direct.ll +++ b/test/DebugInfo/X86/dw_op_minus_direct.ll @@ -51,7 +51,7 @@ attributes #1 = { nounwind readnone } !10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) !11 = !{!12} !12 = !DILocalVariable(name: "i", arg: 1, scope: !7, file: !1, line: 1, type: !10) -!13 = !DIExpression(DW_OP_minus, 1, DW_OP_stack_value) +!13 = !DIExpression(DW_OP_constu, 1, DW_OP_minus, DW_OP_stack_value) !14 = !DILocation(line: 1, column: 13, scope: !7) !15 = !DILocation(line: 2, column: 11, scope: !7) !16 = !DILocation(line: 2, column: 3, scope: !7) diff --git a/test/DebugInfo/X86/safestack-byval.ll b/test/DebugInfo/X86/safestack-byval.ll index 42e94698818c..8742c90bc298 100644 --- a/test/DebugInfo/X86/safestack-byval.ll +++ b/test/DebugInfo/X86/safestack-byval.ll @@ -14,7 +14,7 @@ ; } ; CHECK: ![[ZZZ:.*]] = !DILocalVariable(name: "zzz", -; CHECK: ![[ZZZ_EXPR:.*]] = !DIExpression(DW_OP_deref, DW_OP_minus, 400) +; CHECK: ![[ZZZ_EXPR:.*]] = !DIExpression(DW_OP_deref, DW_OP_constu, 400, DW_OP_minus) ; CHECK: DBG_VALUE {{.*}} ![[ZZZ]], ![[ZZZ_EXPR]] %struct.S = type { [100 x i32] } @@ -79,7 +79,7 @@ attributes #2 = { argmemonly nounwind } !20 = !{i32 2, !"Debug Info Version", i32 3} !21 = !{!"clang version 3.8.0 (trunk 254107) (llvm/trunk 254109)"} !22 = !DILocation(line: 8, column: 9, scope: !12) -!23 = !DIExpression(DW_OP_deref, DW_OP_minus, 400) +!23 = !DIExpression(DW_OP_deref, DW_OP_constu, 400, DW_OP_minus) !24 = !DILocation(line: 8, column: 28, scope: !12) !25 = !DIExpression() !26 = !DILocation(line: 9, column: 10, scope: !12) diff --git a/test/DebugInfo/X86/stack-value-dwarf2.ll b/test/DebugInfo/X86/stack-value-dwarf2.ll index 61595f7861fe..b653784ec668 100644 --- a/test/DebugInfo/X86/stack-value-dwarf2.ll +++ b/test/DebugInfo/X86/stack-value-dwarf2.ll @@ -93,4 +93,4 @@ attributes #1 = { nounwind readnone } !15 = !DISubprogram(name: "<(lambda at test.ii:87:58)>", scope: !0, file: !1, line: 27, type: !6, isLocal: false, isDefinition: false, scopeLine: 27, flags: DIFlagPublic | DIFlagPrototyped, isOptimized: true, templateParams: !2) !16 = distinct !DILocation(line: 99, column: 21, scope: !17) !17 = !DILexicalBlockFile(scope: !5, file: !1, discriminator: 2) -!18 = !DIExpression(DW_OP_plus, 4, DW_OP_stack_value, DW_OP_LLVM_fragment, 64, 32) +!18 = !DIExpression(DW_OP_plus_uconst, 4, DW_OP_stack_value, DW_OP_LLVM_fragment, 64, 32) diff --git a/test/DebugInfo/X86/unattached-global.ll b/test/DebugInfo/X86/unattached-global.ll index 5d4be7377ef4..5e9af695c8dc 100644 --- a/test/DebugInfo/X86/unattached-global.ll +++ b/test/DebugInfo/X86/unattached-global.ll @@ -12,7 +12,7 @@ target triple = "x86_64-unknown-linux-gnu" !1 = !{!2} !2 = !DIGlobalVariableExpression(var: !3, expr: !4) !3 = distinct !DIGlobalVariable(name: "a", scope: null, isLocal: false, isDefinition: true, type: !6) -!4 = !DIExpression(DW_OP_plus, 4) +!4 = !DIExpression(DW_OP_plus_uconst, 4) !5 = !DIFile(filename: "<stdin>", directory: "/") !6 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) diff --git a/test/DebugInfo/dwarfdump-str-offsets-dwp.test b/test/DebugInfo/dwarfdump-str-offsets-dwp.test new file mode 100644 index 000000000000..ceca3225f075 --- /dev/null +++ b/test/DebugInfo/dwarfdump-str-offsets-dwp.test @@ -0,0 +1,56 @@ +RUN: llvm-dwarfdump %p/Inputs/dwarfdump-str-offsets-dwp.x86_64.o | FileCheck %s + +; Verify that the correct strings from each unit are displayed and that the +; index for the .debug_str_offsets section has the right values. + +; CHECK: Compile Unit +; CHECK-NOT: NULL +; CHECK: DW_TAG_compile_unit +; CHECK-NEXT: DW_AT_producer [DW_FORM_strx] ( indexed (00000000) string = "Handmade DWARF producer") +; CHECK-NEXT: DW_AT_name [DW_FORM_strx] ( indexed (00000001) string = "Compile_Unit_1") +; CHECK-NEXT: DW_AT_str_offsets_base [DW_FORM_sec_offset] (0x00000008) +; CHECK-NEXT: DW_AT_name [DW_FORM_strx] ( indexed (00000002) string = "/home/test/CU1") +; CHECK-NOT: NULL + +; CHECK: Compile Unit +; CHECK-NOT: NULL +; CHECK: DW_TAG_compile_unit +; CHECK-NEXT: DW_AT_producer [DW_FORM_strx] ( indexed (00000000) string = "Handmade DWARF producer") +; CHECK-NEXT: DW_AT_name [DW_FORM_strx] ( indexed (00000001) string = "Compile_Unit_2") +; CHECK-NEXT: DW_AT_str_offsets_base [DW_FORM_sec_offset] (0x00000008) +; CHECK-NEXT: DW_AT_name [DW_FORM_strx] ( indexed (00000002) string = "/home/test/CU2") +; +; CHECK: Type Unit +; CHECK-NOT: NULL +; CHECK: DW_TAG_type_unit +; CHECK-NEXT: DW_AT_name [DW_FORM_strx] ( indexed (00000000) string = "Type_Unit_1") +; CHECK-NEXT: DW_AT_str_offsets_base [DW_FORM_sec_offset] (0x0000001c) +; CHECK-NOT: NULL +; CHECK: DW_TAG_structure_type +; CHECK-NEXT: DW_AT_name [DW_FORM_strx] ( indexed (00000001) string = "MyStruct_1") +; +; CHECK: Type Unit +; CHECK-NOT: NULL +; CHECK: DW_TAG_type_unit +; CHECK-NEXT: DW_AT_name [DW_FORM_strx] ( indexed (00000000) string = "Type_Unit_2") +; CHECK-NEXT: DW_AT_str_offsets_base [DW_FORM_sec_offset] (0x0000001c) +; CHECK-NOT: NULL +; CHECK: DW_TAG_structure_type +; CHECK-NEXT: DW_AT_name [DW_FORM_strx] ( indexed (00000001) string = "MyStruct_2") + +; Verify the correct offets of the compile and type units contributions in the +; index tables. + +; CHECK: .debug_cu_index contents: +; CHECK-NOT: contents: +; CHECK: 1 0xddeeaaddbbaabbee [{{0x[0-9a-f]*, 0x[0-9a-f]*}}) [{{0x[0-9a-f]*, 0x[0-9a-f]*}}) +; CHECK-SAME: [0x00000000 +; CHECK-NEXT: 2 0xff00ffeeffaaff00 [{{0x[0-9a-f]*, 0x[0-9a-f]*}}) [{{0x[0-9a-f]*, 0x[0-9a-f]*}}) +; CHECK-SAME: [0x00000024 + +; CHECK: .debug_tu_index contents: +; CHECK-NOT: contents: +; CHECK: 1 0xeeaaddbbaabbeedd [{{0x[0-9a-f]*, 0x[0-9a-f]*}}) [{{0x[0-9a-f]*, 0x[0-9a-f]*}}) +; CHECK-SAME: [0x00000000 +; CHECK-NEXT: 2 0x00ffeeffaaff00ff [{{0x[0-9a-f]*, 0x[0-9a-f]*}}) [{{0x[0-9a-f]*, 0x[0-9a-f]*}}) +; CHECK: [0x00000024 diff --git a/test/DebugInfo/dwarfdump-zlib.test b/test/DebugInfo/dwarfdump-zlib.test index d3ef806f3f87..82f29afdebde 100644 --- a/test/DebugInfo/dwarfdump-zlib.test +++ b/test/DebugInfo/dwarfdump-zlib.test @@ -1,6 +1,7 @@ REQUIRES: zlib RUN: llvm-dwarfdump %p/Inputs/dwarfdump-test-zlib.elf-x86-64 | FileCheck %s +RUN: llvm-dwarfdump %p/Inputs/dwarfdump-test-zlib.o.elf-x86-64 | FileCheck %s RUN: llvm-dwarfdump %p/Inputs/dwarfdump-test-zlibgnu.elf-x86-64 | FileCheck %s CHECK: .debug_abbrev contents @@ -10,3 +11,7 @@ CHECK: .debug_abbrev contents // that sections names are properly shown in zlib-gnu style (without additional 'z' prefix). CHECK: .debug_info contents CHECK: 0x00000000: Compile Unit: length = 0x00000144 version = 0x0004 abbr_offset = 0x0000 addr_size = 0x08 (next unit at 0x00000148) + +// Also check that relocations in the .zdebug sections are handled correctly: +CHECK: DW_AT_ranges {{.*}} (0x00000000{{$}} +CHECK-NEXT: [0x diff --git a/test/Instrumentation/InstrProfiling/always_inline.ll b/test/Instrumentation/InstrProfiling/always_inline.ll new file mode 100644 index 000000000000..4be7848c9b6f --- /dev/null +++ b/test/Instrumentation/InstrProfiling/always_inline.ll @@ -0,0 +1,28 @@ +; Check that '__attribute__((always_inline)) inline' functions are inlined. + +; RUN: opt < %s -mtriple=x86_64-apple-macosx10.10.0 -instrprof -inline -S | FileCheck %s + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.13.0" + +@__profn_foo = linkonce_odr hidden constant [3 x i8] c"foo" + +; CHECK-LABEL: @main +; CHECK-NOT: call +define i32 @main() { +entry: + %call = call i32 @foo() + ret i32 %call +} + +declare void @llvm.instrprof.increment(i8*, i64, i32, i32) #0 + +; CHECK-NOT: define available_externally i32 @foo +define available_externally i32 @foo() #1 { +entry: + call void @llvm.instrprof.increment(i8* getelementptr inbounds ([3 x i8], [3 x i8]* @__profn_foo, i32 0, i32 0), i64 0, i32 1, i32 0) + ret i32 0 +} + +attributes #0 = { nounwind } +attributes #1 = { alwaysinline } diff --git a/test/Instrumentation/SanitizerCoverage/inline-8bit-counters.ll b/test/Instrumentation/SanitizerCoverage/inline-8bit-counters.ll index 4df6ffeb5a8c..5b5b75117fb5 100644 --- a/test/Instrumentation/SanitizerCoverage/inline-8bit-counters.ll +++ b/test/Instrumentation/SanitizerCoverage/inline-8bit-counters.ll @@ -10,4 +10,4 @@ entry: ; CHECK: store i8 %1, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @__sancov_gen_, i64 0, i64 0), !nosanitize ret void } -; CHECK: call void @__sanitizer_cov_8bit_counters_init(i8* bitcast (i8** @__start___sancov_counters to i8*), i8* bitcast (i8** @__stop___sancov_counters to i8*)) +; CHECK: call void @__sanitizer_cov_8bit_counters_init(i8* bitcast (i8** @__start___sancov_cntrs to i8*), i8* bitcast (i8** @__stop___sancov_cntrs to i8*)) diff --git a/test/LTO/Resolution/X86/Inputs/dead-strip-fulllto.ll b/test/LTO/Resolution/X86/Inputs/dead-strip-fulllto.ll new file mode 100644 index 000000000000..66754889f8ba --- /dev/null +++ b/test/LTO/Resolution/X86/Inputs/dead-strip-fulllto.ll @@ -0,0 +1,16 @@ +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define void @live1() { + call void @live2() + ret void +} + +declare void @live2() + +define void @dead1() { + call void @dead2() + ret void +} + +declare void @dead2() diff --git a/test/LTO/Resolution/X86/dead-strip-fulllto.ll b/test/LTO/Resolution/X86/dead-strip-fulllto.ll new file mode 100644 index 000000000000..a9be2751c81f --- /dev/null +++ b/test/LTO/Resolution/X86/dead-strip-fulllto.ll @@ -0,0 +1,37 @@ +; RUN: opt -module-summary -o %t %s +; RUN: opt -module-summary -o %t2 %S/Inputs/dead-strip-fulllto.ll +; RUN: llvm-lto2 run %t -r %t,main,px -r %t,live1,p -r %t,live2,p -r %t,dead2,p \ +; RUN: %t2 -r %t2,live1,p -r %t2,live2, -r %t2,dead1,p -r %t2,dead2, \ +; RUN: -save-temps -o %t3 +; RUN: llvm-nm %t3.0 | FileCheck --check-prefix=FULL %s +; RUN: llvm-nm %t3.1 | FileCheck --check-prefix=THIN %s + +; FULL-NOT: dead +; FULL: U live1 +; FULL: T live2 +; FULL: T main + +; THIN-NOT: dead +; THIN: T live1 +; THIN: U live2 + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define void @main() { + call void @live1() + ret void +} + +declare void @live1() + +define void @live2() { + ret void +} + +define void @dead2() { + ret void +} + +!0 = !{i32 1, !"ThinLTO", i32 0} +!llvm.module.flags = !{ !0 } diff --git a/test/LTO/Resolution/X86/symtab-elf.ll b/test/LTO/Resolution/X86/symtab-elf.ll index 1683b061c6d6..d5f0fbe3700d 100644 --- a/test/LTO/Resolution/X86/symtab-elf.ll +++ b/test/LTO/Resolution/X86/symtab-elf.ll @@ -6,8 +6,8 @@ target triple = "x86_64-unknown-linux-gnu" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" ; CHECK-NOT: linker opts: -!0 = !{i32 6, !"Linker Options", !{!{!"/include:foo"}}} -!llvm.module.flags = !{ !0 } +!0 = !{!"/include:foo"} +!llvm.linker.options = !{ !0 } @g1 = global i32 0 diff --git a/test/LTO/Resolution/X86/symtab.ll b/test/LTO/Resolution/X86/symtab.ll index b7bc11749016..fecea0a1e7b4 100644 --- a/test/LTO/Resolution/X86/symtab.ll +++ b/test/LTO/Resolution/X86/symtab.ll @@ -9,8 +9,8 @@ target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" source_filename = "src.c" ; CHECK: linker opts: /include:foo -!0 = !{i32 6, !"Linker Options", !{!{!"/include:foo"}}} -!llvm.module.flags = !{ !0 } +!0 = !{!"/include:foo"} +!llvm.linker.options = !{ !0 } ; CHECK: D------X _fun define i32 @fun() { diff --git a/test/LibDriver/use-paths.test b/test/LibDriver/use-paths.test new file mode 100644 index 000000000000..971c216127e6 --- /dev/null +++ b/test/LibDriver/use-paths.test @@ -0,0 +1,24 @@ +llvm-lib should behave like "link.exe /lib" and use relative paths to describe +archive members. + +First, get in a clean working directory. +RUN: rm -rf %t && mkdir -p %t && cd %t + +Make foo/a.obj and foo/b.obj. +RUN: mkdir foo +RUN: llvm-mc -triple=x86_64-pc-windows-msvc -filetype=obj -o foo/a.obj %S/Inputs/a.s +RUN: llvm-mc -triple=x86_64-pc-windows-msvc -filetype=obj -o foo/b.obj %S/Inputs/b.s + +RUN: llvm-lib -out:foo.lib foo/a.obj foo/b.obj +RUN: llvm-ar t foo.lib | FileCheck %s + +FIXME: We should probably use backslashes on Windows to better match MSVC tools. +CHECK: foo/a.obj +CHECK: foo/b.obj + +Do it again with absolute paths and see that we get something. +RUN: llvm-lib -out:foo.lib %t/foo/a.obj %t/foo/b.obj +RUN: llvm-ar t foo.lib | FileCheck %s --check-prefix=ABS + +ABS: {{.*}}/foo/a.obj +ABS: {{.*}}/foo/b.obj diff --git a/test/MC/AMDGPU/flat-gfx9.s b/test/MC/AMDGPU/flat-gfx9.s new file mode 100644 index 000000000000..5f93a7371b8b --- /dev/null +++ b/test/MC/AMDGPU/flat-gfx9.s @@ -0,0 +1,40 @@ +// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI -check-prefix=GCN %s + +// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding 2>&1 %s | FileCheck -check-prefix=GFX9-ERR -check-prefix=GCNERR %s +// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding 2>&1 %s | FileCheck -check-prefix=VI-ERR -check-prefix=GCNERR %s + + +flat_load_dword v1, v[3:4] offset:0 +// GCN: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x00,0x01] + +flat_load_dword v1, v[3:4] offset:-1 +// GCN-ERR: :35: error: failed parsing operand. + +// FIXME: Error on VI in wrong column +flat_load_dword v1, v[3:4] offset:4095 +// GFX9: flat_load_dword v1, v[3:4] offset:4095 ; encoding: [0xff,0x0f,0x50,0xdc,0x03,0x00,0x00,0x01] +// VIERR: :1: error: invalid operand for instruction + +flat_load_dword v1, v[3:4] offset:4096 +// GCNERR: :28: error: invalid operand for instruction + +flat_load_dword v1, v[3:4] offset:4 glc +// GFX9: flat_load_dword v1, v[3:4] offset:4 glc ; encoding: [0x04,0x00,0x51,0xdc,0x03,0x00,0x00,0x01] +// VIERR: :1: error: invalid operand for instruction + +flat_load_dword v1, v[3:4] offset:4 glc slc +// GFX9: flat_load_dword v1, v[3:4] offset:4 glc slc ; encoding: [0x04,0x00,0x53,0xdc,0x03,0x00,0x00,0x01] +// VIERR: :1: error: invalid operand for instruction + +flat_atomic_add v[3:4], v5 offset:8 slc +// GFX9: flat_atomic_add v[3:4], v5 offset:8 slc ; encoding: [0x08,0x00,0x0a,0xdd,0x03,0x05,0x00,0x00] +// VIERR: :1: error: invalid operand for instruction + +flat_atomic_swap v[3:4], v5 offset:16 +// GFX9: flat_atomic_swap v[3:4], v5 offset:16 ; encoding: [0x10,0x00,0x00,0xdd,0x03,0x05,0x00,0x00] +// VIERR: :1: error: invalid operand for instruction + +flat_store_dword v[3:4], v1 offset:16 +// GFX9: flat_store_dword v[3:4], v1 offset:16 ; encoding: [0x10,0x00,0x70,0xdc,0x03,0x01,0x00,0x00] +// VIERR: :1: error: invalid operand for instruction diff --git a/test/MC/AMDGPU/flat.s b/test/MC/AMDGPU/flat.s index 4e81799fe9f9..d8cad131d1e4 100644 --- a/test/MC/AMDGPU/flat.s +++ b/test/MC/AMDGPU/flat.s @@ -49,9 +49,10 @@ flat_store_dword v[3:4], v1 slc // FIXME: For atomic instructions, glc must be placed immediately following // the data regiser. These forms aren't currently supported: +// FIXME: offset:0 required // flat_atomic_add v1, v[3:4], v5 slc glc -flat_atomic_add v1 v[3:4], v5 glc slc +flat_atomic_add v1, v[3:4], v5 offset:0 glc slc // NOSI: error: // CI: flat_atomic_add v1, v[3:4], v5 glc slc ; encoding: [0x00,0x00,0xcb,0xdc,0x03,0x05,0x00,0x01] // VI: flat_atomic_add v1, v[3:4], v5 glc slc ; encoding: [0x00,0x00,0x0b,0xdd,0x03,0x05,0x00,0x01] diff --git a/test/MC/COFF/cv-compiler-info.ll b/test/MC/COFF/cv-compiler-info.ll index 6c33a25c1f46..f7cd17397d61 100644 --- a/test/MC/COFF/cv-compiler-info.ll +++ b/test/MC/COFF/cv-compiler-info.ll @@ -13,7 +13,7 @@ entry: attributes #0 = { nounwind sspstrong "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } !llvm.dbg.cu = !{!0} -!llvm.module.flags = !{!3, !7, !8} +!llvm.module.flags = !{!7, !8} !llvm.ident = !{!9} !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "clang version 4.0.0 ", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) @@ -35,10 +35,6 @@ attributes #0 = { nounwind sspstrong "correctly-rounded-divide-sqrt-fp-math"="fa ; CHECK-NOT: .short 4412 # Record kind: S_COMPILE3 !1 = !DIFile(filename: "D:\5Csrc\5Cscopes\5Cfoo.cpp", directory: "D:\5Csrc\5Cscopes\5Cclang") !2 = !{} -!3 = !{i32 6, !"Linker Options", !4} -!4 = !{!5, !6} -!5 = !{!"/DEFAULTLIB:libcmtd.lib"} -!6 = !{!"/DEFAULTLIB:oldnames.lib"} !7 = !{i32 2, !"CodeView", i32 1} !8 = !{i32 2, !"Debug Info Version", i32 3} !9 = !{!"clang version 4.0.0 "} diff --git a/test/MC/COFF/linker-options.ll b/test/MC/COFF/linker-options.ll index afc55af692d2..24ac84da1e2d 100755 --- a/test/MC/COFF/linker-options.ll +++ b/test/MC/COFF/linker-options.ll @@ -1,8 +1,10 @@ ; RUN: llc -O0 -mtriple=i386-pc-win32 -filetype=asm -o - %s | FileCheck %s -!0 = !{i32 6, !"Linker Options", !{!{!"/DEFAULTLIB:msvcrt.lib"}, !{!"/DEFAULTLIB:msvcrt.lib", !"/DEFAULTLIB:secur32.lib"}, !{!"/DEFAULTLIB:\22C:\5Cpath to\5Casan_rt.lib\22"}, !{!"\22/with spaces\22"}}} - -!llvm.module.flags = !{ !0 } +!0 = !{!"/DEFAULTLIB:msvcrt.lib"} +!1 = !{!"/DEFAULTLIB:msvcrt.lib", !"/DEFAULTLIB:secur32.lib"} +!2 = !{!"/DEFAULTLIB:\22C:\5Cpath to\5Casan_rt.lib\22"} +!3 = !{!"\22/with spaces\22"} +!llvm.linker.options = !{!0, !1, !2, !3} define dllexport void @foo() { ret void diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding.txt index a6d079297bcf..25ed35fcb1c0 100644 --- a/test/MC/Disassembler/PowerPC/ppc64-encoding.txt +++ b/test/MC/Disassembler/PowerPC/ppc64-encoding.txt @@ -352,6 +352,18 @@ # CHECK: divweu. 2, 3, 4 0x7c 0x43 0x23 0x17 +# CHECK: modsw 2, 3, 4 +0x7c 0x43 0x26 0x16 + +# CHECK: moduw 2, 3, 4 +0x7c 0x43 0x22 0x16 + +# CHECK: modsd 2, 3, 4 +0x7c 0x43 0x26 0x12 + +# CHECK: modud 2, 3, 4 +0x7c 0x43 0x22 0x12 + # CHECK: mulld 2, 3, 4 0x7c 0x43 0x21 0xd2 diff --git a/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt b/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt index 9ddc286d8aaa..9dc994010551 100644 --- a/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt +++ b/test/MC/Disassembler/PowerPC/ppc64le-encoding.txt @@ -349,6 +349,18 @@ # CHECK: divweu. 2, 3, 4 0x17 0x23 0x43 0x7c +# CHECK: modsw 2, 3, 4 +0x16 0x26 0x43 0x7c + +# CHECK: moduw 2, 3, 4 +0x16 0x22 0x43 0x7c + +# CHECK: modsd 2, 3, 4 +0x12 0x26 0x43 0x7c + +# CHECK: modud 2, 3, 4 +0x12 0x22 0x43 0x7c + # CHECK: mulld 2, 3, 4 0xd2 0x21 0x43 0x7c diff --git a/test/MC/ELF/section.s b/test/MC/ELF/section.s index 03a0f22e580b..c3f7d426ba56 100644 --- a/test/MC/ELF/section.s +++ b/test/MC/ELF/section.s @@ -267,3 +267,15 @@ bar: // CHECK-NEXT: SHF_TLS // CHECK-NEXT: SHF_WRITE // CHECK-NEXT: ] + +// Test SHT_LLVM_ODRTAB + +.section .odrtab,"e",@llvm_odrtab +// ASM: .section .odrtab,"e",@llvm_odrtab + +// CHECK: Section { +// CHECK: Name: .odrtab +// CHECK-NEXT: Type: SHT_LLVM_ODRTAB +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_EXCLUDE +// CHECK-NEXT: ] diff --git a/test/MC/MachO/linker-options.ll b/test/MC/MachO/linker-options.ll index 09ebd0f91567..d9d7a4a46d8f 100644 --- a/test/MC/MachO/linker-options.ll +++ b/test/MC/MachO/linker-options.ll @@ -27,6 +27,7 @@ ; CHECK-OBJ: ] ; CHECK-OBJ: } -!0 = !{i32 6, !"Linker Options", !{!{!"-lz"}, !{!"-framework", !"Cocoa"}, !{!"-lmath"}}} - -!llvm.module.flags = !{ !0 } +!0 = !{!"-lz"} +!1 = !{!"-framework", !"Cocoa"} +!2 = !{!"-lmath"} +!llvm.linker.options = !{!0, !1, !2} diff --git a/test/MC/PowerPC/ppc64-encoding.s b/test/MC/PowerPC/ppc64-encoding.s index a772ca44986c..237dd5cfd727 100644 --- a/test/MC/PowerPC/ppc64-encoding.s +++ b/test/MC/PowerPC/ppc64-encoding.s @@ -493,6 +493,19 @@ # FIXME: divweuo 2, 3, 4 # FIXME: divweuo. 2, 3, 4 +# CHECK-BE: modsw 2, 3, 4 # encoding: [0x7c,0x43,0x26,0x16] +# CHECK-LE: modsw 2, 3, 4 # encoding: [0x16,0x26,0x43,0x7c] + modsw 2, 3, 4 +# CHECK-BE: moduw 2, 3, 4 # encoding: [0x7c,0x43,0x22,0x16] +# CHECK-LE: moduw 2, 3, 4 # encoding: [0x16,0x22,0x43,0x7c] + moduw 2, 3, 4 +# CHECK-BE: modsd 2, 3, 4 # encoding: [0x7c,0x43,0x26,0x12] +# CHECK-LE: modsd 2, 3, 4 # encoding: [0x12,0x26,0x43,0x7c] + modsd 2, 3, 4 +# CHECK-BE: modud 2, 3, 4 # encoding: [0x7c,0x43,0x22,0x12] +# CHECK-LE: modud 2, 3, 4 # encoding: [0x12,0x22,0x43,0x7c] + modud 2, 3, 4 + # CHECK-BE: mulld 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd2] # CHECK-LE: mulld 2, 3, 4 # encoding: [0xd2,0x21,0x43,0x7c] mulld 2, 3, 4 diff --git a/test/MC/WebAssembly/external-data.ll b/test/MC/WebAssembly/external-data.ll index 91e05b3f13a6..6914736ac671 100644 --- a/test/MC/WebAssembly/external-data.ll +++ b/test/MC/WebAssembly/external-data.ll @@ -2,10 +2,10 @@ ; Verify relocations are correctly generated for addresses of externals ; in the data section. -declare i32 @f1(...) +@myimport = external global i32, align 4 @foo = global i64 7, align 4 -@far = local_unnamed_addr global i32 (...)* @f1, align 4 +@bar = hidden global i32* @myimport, align 4 ; CHECK: - Type: DATA ; CHECK: Relocations: diff --git a/test/MC/WebAssembly/external-func-address.ll b/test/MC/WebAssembly/external-func-address.ll new file mode 100644 index 000000000000..4022b2c9bae9 --- /dev/null +++ b/test/MC/WebAssembly/external-func-address.ll @@ -0,0 +1,25 @@ +; RUN: llc -mtriple wasm32-unknown-unknown-wasm -filetype=obj %s -o - | obj2yaml | FileCheck %s +; Verify that addresses of external functions generate correctly typed +; imports and relocations or type R_TABLE_INDEX_I32. + +declare void @f1() #1 +@ptr_to_f1 = hidden global void ()* @f1, align 4 + + +; CHECK: - Type: IMPORT +; CHECK: Imports: +; CHECK: - Module: env +; CHECK: Field: f1 +; CHECK: Kind: FUNCTION +; CHECK: SigIndex: 0 +; CHECK: - Type: ELEM +; CHECK: Segments: +; CHECK: - Offset: +; CHECK: Opcode: I32_CONST +; CHECK: Value: 0 +; CHECK: Functions: [ 0 ] +; CHECK: - Type: DATA +; CHECK: Relocations: +; CHECK: - Type: R_WEBASSEMBLY_TABLE_INDEX_I32 +; CHECK: Index: 0 +; CHECK: Offset: 0x00000006 diff --git a/test/MC/WebAssembly/func-address.ll b/test/MC/WebAssembly/func-address.ll new file mode 100644 index 000000000000..c0a9d9a801ff --- /dev/null +++ b/test/MC/WebAssembly/func-address.ll @@ -0,0 +1,48 @@ +; RUN: llc -mtriple wasm32-unknown-unknown-wasm -O2 -filetype=obj %s -o - | llvm-readobj -r -s -expand-relocs | FileCheck %s + +declare i32 @import1() +declare i32 @import2() +declare i32 @import3() + +; call the imports to make sure they are included in the imports section +define hidden void @call_imports() #0 { +entry: + %call = call i32 @import1() + %call1 = call i32 @import2() + ret void +} + +; take the address of the third import. This should generate a TABLE_INDEX +; relocation with index of 0 since its the first and only address taken +; function. +define hidden void @call_indirect() #0 { +entry: + %adr = alloca i32 ()*, align 4 + store i32 ()* @import3, i32 ()** %adr, align 4 + ret void +} + +; CHECK: Section { +; CHECK: Type: ELEM (0x9) +; CHECK: Size: 7 +; CHECK: Offset: 165 +; CHECK: } + +; CHECK: Relocations [ +; CHECK: Section (9) CODE { +; CHECK: Relocation { +; CHECK: Type: R_WEBASSEMBLY_FUNCTION_INDEX_LEB (0) +; CHECK: Offset: 0x4 +; CHECK: Index: 0x0 +; CHECK: } +; CHECK: Relocation { +; CHECK: Type: R_WEBASSEMBLY_FUNCTION_INDEX_LEB (0) +; CHECK: Offset: 0xB +; CHECK: Index: 0x1 +; CHECK: } +; CHECK: Relocation { +; CHECK: Type: R_WEBASSEMBLY_TABLE_INDEX_SLEB (1) +; CHECK: Offset: 0x1A +; CHECK: Index: 0x0 +; CHECK: } +; CHECK: } diff --git a/test/ThinLTO/X86/cfi-icall.ll b/test/ThinLTO/X86/cfi-icall.ll new file mode 100644 index 000000000000..ef5d33c8a5a0 --- /dev/null +++ b/test/ThinLTO/X86/cfi-icall.ll @@ -0,0 +1,29 @@ +; RUN: opt -thinlto-bc %s -o %t1.bc +; RUN: llvm-lto2 run -thinlto-distributed-indexes %t1.bc -o %t.out -save-temps \ +; RUN: -r %t1.bc,foo,plx \ +; RUN: -r %t1.bc,bar,x +; RUN: llvm-bcanalyzer -dump %t.out.index.bc | FileCheck %s --check-prefix=COMBINED + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define i1 @foo(i8* %p) !type !0 { +entry: + %x = call i1 @llvm.type.test(i8* %p, metadata !"typeid1") + ret i1 %x +} + +declare !type !0 void @bar() + +declare i1 @llvm.type.test(i8* %ptr, metadata %type) nounwind readnone + +!0 = !{i64 0, !"typeid1"} + +; COMBINED: <GLOBALVAL_SUMMARY_BLOCK +; COMBINED: <CFI_FUNCTION_DEFS op0=0 op1=3/> +; COMBINED: <CFI_FUNCTION_DECLS op0=3 op1=3/> +; COMBINED: </GLOBALVAL_SUMMARY_BLOCK> + +; COMBINED: <STRTAB_BLOCK +; COMBINED-NEXT: <BLOB abbrevid=4/> blob data = 'foobar' +; COMBINED-NEXT: </STRTAB_BLOCK> diff --git a/test/Transforms/CodeExtractor/live_shrink.ll b/test/Transforms/CodeExtractor/live_shrink.ll new file mode 100644 index 000000000000..c25ed2b622cd --- /dev/null +++ b/test/Transforms/CodeExtractor/live_shrink.ll @@ -0,0 +1,67 @@ +; RUN: opt -S -partial-inliner -skip-partial-inlining-cost-analysis < %s | FileCheck %s +; RUN: opt -S -passes=partial-inliner -skip-partial-inlining-cost-analysis < %s | FileCheck %s + +%class.A = type { i32 } +@cond = local_unnamed_addr global i32 0, align 4 + +; Function Attrs: uwtable +define void @_Z3foov() local_unnamed_addr { +bb: + %tmp = alloca %class.A, align 4 + %tmp1 = bitcast %class.A* %tmp to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %tmp1) + %tmp2 = load i32, i32* @cond, align 4, !tbaa !2 + %tmp3 = icmp eq i32 %tmp2, 0 + br i1 %tmp3, label %bb4, label %bb5 + +bb4: ; preds = %bb + call void @_ZN1A7memfuncEv(%class.A* nonnull %tmp) + br label %bb5 + +bb5: ; preds = %bb4, %bb + call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %tmp1) + ret void +} + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) + +declare void @_ZN1A7memfuncEv(%class.A*) local_unnamed_addr + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) + +; Function Attrs: uwtable +define void @_Z3goov() local_unnamed_addr { +; CHECK-LABEL: @_Z3goov() +bb: +; CHECK: bb: +; CHECK-NOT: alloca +; CHECK-NOT: bitcast +; CHECK-NOT: llvm.lifetime +; CHECK: br i1 +; CHECK: codeRepl.i: +; CHECK: call void @_Z3foov.1_ + + tail call void @_Z3foov() + ret void +} + +; CHECK-LABEL: define internal void @_Z3foov.1_ +; CHECK: newFuncRoot: +; CHECK-NEXT: %tmp = alloca %class.A +; CHECK-NEXT: %tmp1 = bitcast %class.A* %tmp to i8* +; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %tmp1) +; CHECK: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %tmp1) +; CHECK-NEXT: br label %bb5.exitStub + + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang version 5.0.0 (trunk 304489)"} +!2 = !{!3, !3, i64 0} +!3 = !{!"int", !4, i64 0} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C++ TBAA"} diff --git a/test/Transforms/CodeExtractor/live_shrink_gep.ll b/test/Transforms/CodeExtractor/live_shrink_gep.ll new file mode 100644 index 000000000000..ac6aa4fbda43 --- /dev/null +++ b/test/Transforms/CodeExtractor/live_shrink_gep.ll @@ -0,0 +1,66 @@ +; RUN: opt -S -partial-inliner -skip-partial-inlining-cost-analysis < %s | FileCheck %s +; RUN: opt -S -passes=partial-inliner -skip-partial-inlining-cost-analysis < %s | FileCheck %s + +%class.A = type { i8 } + +@cond = local_unnamed_addr global i32 0, align 4 + +; Function Attrs: uwtable +define void @_Z3foov() local_unnamed_addr { +bb: + %tmp = alloca %class.A, align 1 + %tmp1 = getelementptr inbounds %class.A, %class.A* %tmp, i64 0, i32 0 + call void @llvm.lifetime.start.p0i8(i64 1, i8* nonnull %tmp1) + %tmp2 = load i32, i32* @cond, align 4, !tbaa !2 + %tmp3 = icmp eq i32 %tmp2, 0 + br i1 %tmp3, label %bb4, label %bb5 + +bb4: ; preds = %bb + call void @_ZN1A7memfuncEv(%class.A* nonnull %tmp) + br label %bb5 + +bb5: ; preds = %bb4, %bb + call void @llvm.lifetime.end.p0i8(i64 1, i8* nonnull %tmp1) + ret void +} + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) + +declare void @_ZN1A7memfuncEv(%class.A*) local_unnamed_addr + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) + +; Function Attrs: uwtable +define void @_Z3goov() local_unnamed_addr { +; CHECK-LABEL: @_Z3goov() +bb: +; CHECK: bb: +; CHECK-NOT: alloca +; CHECK-NOT: getelementptr +; CHECK-NOT: llvm.lifetime +; CHECK: br i1 +; CHECK: codeRepl.i: +; CHECK: call void @_Z3foov.1_ + tail call void @_Z3foov() + ret void +} + +; CHECK-LABEL: define internal void @_Z3foov.1_ +; CHECK: newFuncRoot: +; CHECK-NEXT: %tmp = alloca %class.A +; CHECK-NEXT: %tmp1 = getelementptr +; CHECK-NEXT: call void @llvm.lifetime.start.p0i8 +; CHECK: call void @llvm.lifetime.end.p0i8 +; CHECK-NEXT: br label %bb5.exitStub + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang version 5.0.0 (trunk 304489)"} +!2 = !{!3, !3, i64 0} +!3 = !{!"int", !4, i64 0} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C++ TBAA"} diff --git a/test/Transforms/CodeExtractor/live_shrink_hoist.ll b/test/Transforms/CodeExtractor/live_shrink_hoist.ll new file mode 100644 index 000000000000..d1b310f01769 --- /dev/null +++ b/test/Transforms/CodeExtractor/live_shrink_hoist.ll @@ -0,0 +1,66 @@ +; RUN: opt -S -partial-inliner -max-num-inline-blocks=2 -skip-partial-inlining-cost-analysis < %s | FileCheck %s +; RUN: opt -S -passes=partial-inliner -max-num-inline-blocks=2 -skip-partial-inlining-cost-analysis < %s | FileCheck %s + +%class.A = type { i32 } + +@cond = local_unnamed_addr global i32 0, align 4 + +; Function Attrs: uwtable +define void @_Z3foov() local_unnamed_addr { +bb: + %tmp = alloca %class.A, align 4 + %tmp1 = bitcast %class.A* %tmp to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %tmp1) + %tmp2 = load i32, i32* @cond, align 4, !tbaa !2 + %tmp3 = icmp eq i32 %tmp2, 0 + br i1 %tmp3, label %bb4, label %bb9 + +bb4: ; preds = %bb + call void @_ZN1A7memfuncEv(%class.A* nonnull %tmp) + %tmp5 = getelementptr inbounds %class.A, %class.A* %tmp, i64 0, i32 0 + %tmp6 = load i32, i32* %tmp5, align 4, !tbaa !6 + %tmp7 = icmp sgt i32 %tmp6, 0 + br i1 %tmp7, label %bb9, label %bb8 + +bb8: ; preds = %bb4 + call void @_ZN1A7memfuncEv(%class.A* nonnull %tmp) + br label %bb9 + +bb9: ; preds = %bb8, %bb4, %bb + call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %tmp1) + ret void +} + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) + +declare void @_ZN1A7memfuncEv(%class.A*) local_unnamed_addr + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) + +; Function Attrs: uwtable +define void @_Z3goov() local_unnamed_addr { +bb: + tail call void @_Z3foov() + ret void +} + +; CHECK-LABEL: define internal void @_Z3foov.1_ +; CHECK: bb9: +; CHECK: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %tmp1) +; CHECK: br label %.exitStub + + + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang version 5.0.0 (trunk 304489)"} +!2 = !{!3, !3, i64 0} +!3 = !{!"int", !4, i64 0} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C++ TBAA"} +!6 = !{!7, !3, i64 0} +!7 = !{!"_ZTS1A", !3, i64 0} diff --git a/test/Transforms/CodeExtractor/live_shrink_multiple.ll b/test/Transforms/CodeExtractor/live_shrink_multiple.ll new file mode 100644 index 000000000000..8d9045c7267b --- /dev/null +++ b/test/Transforms/CodeExtractor/live_shrink_multiple.ll @@ -0,0 +1,66 @@ +; RUN: opt -S -partial-inliner -skip-partial-inlining-cost-analysis < %s | FileCheck %s +; RUN: opt -S -passes=partial-inliner -skip-partial-inlining-cost-analysis < %s | FileCheck %s + +%class.A = type { i32 } +@cond = local_unnamed_addr global i32 0, align 4 + +; Function Attrs: uwtable +define void @_Z3foov() local_unnamed_addr { +bb: + %tmp = alloca %class.A, align 4 + %tmp1 = alloca %class.A, align 4 + %tmp2 = bitcast %class.A* %tmp to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %tmp2) + %tmp3 = bitcast %class.A* %tmp1 to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %tmp3) + %tmp4 = load i32, i32* @cond, align 4, !tbaa !2 + %tmp5 = icmp eq i32 %tmp4, 0 + br i1 %tmp5, label %bb6, label %bb7 + +bb6: ; preds = %bb + call void @_ZN1A7memfuncEv(%class.A* nonnull %tmp) + br label %bb7 + +bb7: ; preds = %bb6, %bb + call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %tmp3) + call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %tmp2) + ret void +} + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) + +declare void @_ZN1A7memfuncEv(%class.A*) local_unnamed_addr + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) + +; Function Attrs: uwtable +define void @_Z3goov() local_unnamed_addr { +bb: + tail call void @_Z3foov() + ret void +} + +; CHECK-LABEL: define internal void @_Z3foov.1_ +; CHECK: newFuncRoot: +; CHECK-NEXT: alloca +; CHECK-NEXT: bitcast +; CHECK-NEXT: call void @llvm.lifetime.start.p0i8 +; CHECK-NEXT: alloca +; CHECK-NEXT: bitcast +; CHECK-NEXT: call void @llvm.lifetime.start.p0i8 +; CHECK: call void @llvm.lifetime.end.p0i8 +; CHECK-NEXT: call void @llvm.lifetime.end.p0i8 +; CHECK-NEXT: br label {{.*}}exitStub + + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang version 5.0.0 (trunk 304489)"} +!2 = !{!3, !3, i64 0} +!3 = !{!"int", !4, i64 0} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C++ TBAA"} diff --git a/test/Transforms/CodeExtractor/live_shrink_unsafe.ll b/test/Transforms/CodeExtractor/live_shrink_unsafe.ll new file mode 100644 index 000000000000..ea6458cc46ec --- /dev/null +++ b/test/Transforms/CodeExtractor/live_shrink_unsafe.ll @@ -0,0 +1,94 @@ +; The expected behavior of this file is expected to change when partial +; inlining legality check is enhanced. + +; RUN: opt -S -partial-inliner -skip-partial-inlining-cost-analysis < %s | FileCheck %s +; RUN: opt -S -passes=partial-inliner -skip-partial-inlining-cost-analysis < %s | FileCheck %s + +%class.A = type { i32 } + +@cond = local_unnamed_addr global i32 0, align 4 +@condptr = external local_unnamed_addr global i32*, align 8 + +; Function Attrs: uwtable +define void @_Z3foo_unknown_mem_accessv() local_unnamed_addr { +bb: + %tmp = alloca %class.A, align 4 + %tmp1 = alloca %class.A, align 4 + %tmp2 = bitcast %class.A* %tmp to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %tmp2) + %tmp3 = bitcast %class.A* %tmp1 to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %tmp3) + %tmp4 = load i32*, i32** @condptr, align 8, !tbaa !2 + %tmp5 = load i32, i32* %tmp4, align 4, !tbaa !6 + %tmp6 = icmp eq i32 %tmp5, 0 + br i1 %tmp6, label %bb7, label %bb8 + +bb7: ; preds = %bb + call void @_ZN1A7memfuncEv(%class.A* nonnull %tmp) + br label %bb8 + +bb8: ; preds = %bb7, %bb + call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %tmp3) + call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %tmp2) + ret void +} + +declare void @_Z3barv() local_unnamed_addr +declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) +declare void @_ZN1A7memfuncEv(%class.A*) local_unnamed_addr +declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) + +define void @_Z3foo_unknown_calli(i32 %arg) local_unnamed_addr { +bb: + %tmp = alloca %class.A, align 4 + %tmp1 = bitcast %class.A* %tmp to i8* + call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %tmp1) + tail call void @_Z3barv() + %tmp2 = icmp eq i32 %arg, 0 + br i1 %tmp2, label %bb3, label %bb4 + +bb3: ; preds = %bb + call void @_ZN1A7memfuncEv(%class.A* nonnull %tmp) + br label %bb4 + +bb4: ; preds = %bb3, %bb + call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %tmp1) + ret void +} + +define void @_Z3goov() local_unnamed_addr { +; CHECK-LABEL: @_Z3goov +; CHECK-NEXT: bb: +; CHECK: alloca +; CHECK: lifetime +bb: + call void @_Z3foo_unknown_mem_accessv() + %tmp = load i32, i32* @cond, align 4, !tbaa !2 + tail call void @_Z3foo_unknown_calli(i32 %tmp) + ret void +} + +; CHECK-LABEL define internal void @_Z3foo_unknown_calli.1_bb3 +; CHECK: newFuncRoot: +; CHECK-NEXT: br label %bb3 + +; CHECK: bb4.exitStub: +; CHECK-NEXT: ret void + +; CHECK: bb3: +; CHECK-NOT: lifetime.ed +; CHECK: br label %bb4.exitStub + + + +!llvm.module.flags = !{!0} +!llvm.ident = !{!1} + +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{!"clang version 5.0.0 (trunk 304489)"} +!2 = !{!3, !3, i64 0} +!3 = !{!"any pointer", !4, i64 0} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C++ TBAA"} +!6 = !{!7, !7, i64 0} +!7 = !{!"int", !4, i64 0} diff --git a/test/Transforms/CrossDSOCFI/cfi_functions.ll b/test/Transforms/CrossDSOCFI/cfi_functions.ll new file mode 100644 index 000000000000..ccbde51b2115 --- /dev/null +++ b/test/Transforms/CrossDSOCFI/cfi_functions.ll @@ -0,0 +1,23 @@ +; Test that types referenced in ThinLTO-style !cfi.functions are known to __cfi_check. +; RUN: opt -S -cross-dso-cfi < %s | FileCheck %s +; RUN: opt -S -passes=cross-dso-cfi < %s | FileCheck %s + +; CHECK: define void @__cfi_check( +; CHECK: switch i64 +; CHECK-NEXT: i64 1234, label +; CHECK-NEXT: i64 5678, label +; CHECK-NEXT: ] + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +!cfi.functions = !{!0, !1} +!llvm.module.flags = !{!6} + +!0 = !{!"f", i8 0, !2, !4} +!1 = !{!"g", i8 1, !3, !5} +!2 = !{i64 0, !"typeid1"} +!3 = !{i64 0, !"typeid2"} +!4 = !{i64 0, i64 1234} +!5 = !{i64 0, i64 5678} +!6 = !{i32 4, !"Cross-DSO CFI", i32 1} diff --git a/test/Transforms/EarlyCSE/pr33406.ll b/test/Transforms/EarlyCSE/pr33406.ll new file mode 100644 index 000000000000..4d3312e1f0ac --- /dev/null +++ b/test/Transforms/EarlyCSE/pr33406.ll @@ -0,0 +1,26 @@ +; RUN: opt -early-cse-memssa -S %s | FileCheck %s + +; CHECK: define void @patatino() { +; CHECK: for.cond: +; CHECK-NEXT: br i1 true, label %if.end, label %for.inc +; CHECK: if.end: +; CHECK-NEXT: %tinkywinky = load i32, i32* @b +; CHECK-NEXT: br i1 true, label %for.inc, label %for.inc +; CHECK: for.inc: +; CHECK-NEXT: ret void + + +@b = external global i32 + +define void @patatino() { +for.cond: + br i1 true, label %if.end, label %for.inc + +if.end: + %tinkywinky = load i32, i32* @b + store i32 %tinkywinky, i32* @b + br i1 true, label %for.inc, label %for.inc + +for.inc: + ret void +} diff --git a/test/Transforms/GVN/pr32314.ll b/test/Transforms/GVN/pr32314.ll new file mode 100644 index 000000000000..90d14f6fc49c --- /dev/null +++ b/test/Transforms/GVN/pr32314.ll @@ -0,0 +1,53 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -S -gvn < %s | FileCheck %s + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +; The load in the loop can not bypass the data from the previous loop. The store above it in the loop aliases. +define void @foo() { +; CHECK-LABEL: @foo( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[A:%.*]] = alloca [3 x i32], align 4 +; CHECK-NEXT: br label [[FOR_BODY:%.*]] +; CHECK: for.cond.cleanup: +; CHECK-NEXT: ret void +; CHECK: for.body: +; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 1, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[P_017:%.*]] = phi i32* [ undef, [[ENTRY]] ], [ [[ARRAYIDX3:%.*]], [[FOR_BODY]] ] +; CHECK-NEXT: [[TMP0:%.*]] = add nsw i64 [[INDVARS_IV]], -1 +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [3 x i32], [3 x i32]* [[A]], i64 0, i64 [[TMP0]] +; CHECK-NEXT: store i32 50, i32* [[ARRAYIDX]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[INDVARS_IV]], 1 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[P_017]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP1]] to i32 +; CHECK-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[ARRAYIDX3]] = getelementptr inbounds [3 x i32], [3 x i32]* [[A]], i64 0, i64 [[INDVARS_IV]] +; CHECK-NEXT: store i32 60, i32* [[ARRAYIDX3]], align 4 +; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 +; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], 3 +; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_BODY]], label [[FOR_COND_CLEANUP:%.*]] +; +entry: + %a = alloca [3 x i32], align 4 + br label %for.body + +for.cond.cleanup: ; preds = %for.body + ret void + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 1, %entry ], [ %indvars.iv.next, %for.body ] + %p.017 = phi i32* [ undef, %entry ], [ %arrayidx3, %for.body ] + %0 = add nsw i64 %indvars.iv, -1 + %arrayidx = getelementptr inbounds [3 x i32], [3 x i32]* %a, i64 0, i64 %0 + store i32 50, i32* %arrayidx, align 4 + %1 = shl i64 %indvars.iv, 1 + %2 = load i32, i32* %p.017, align 4 + %3 = trunc i64 %1 to i32 + %add1 = add nsw i32 %2, %3 + %arrayidx3 = getelementptr inbounds [3 x i32], [3 x i32]* %a, i64 0, i64 %indvars.iv + store i32 60, i32* %arrayidx3, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp ne i64 %indvars.iv.next, 3 + br i1 %exitcond, label %for.body, label %for.cond.cleanup +} diff --git a/test/Transforms/GlobalMerge/debug-info.ll b/test/Transforms/GlobalMerge/debug-info.ll index 97e0bb2148e9..8d60f3662431 100644 --- a/test/Transforms/GlobalMerge/debug-info.ll +++ b/test/Transforms/GlobalMerge/debug-info.ll @@ -17,7 +17,7 @@ define void @use1() { ; CHECK: [[AVAR]] = !DIGlobalVariable(name: "a", scope: null, isLocal: false, isDefinition: true) ; CHECK: [[B]] = !DIGlobalVariableExpression(var: [[BVAR:![0-9]+]], expr: [[EXPR:![0-9]+]]) ; CHECK: [[BVAR]] = !DIGlobalVariable(name: "b", scope: null, isLocal: false, isDefinition: true) -; CHECK: [[EXPR]] = !DIExpression(DW_OP_plus, 4) +; CHECK: [[EXPR]] = !DIExpression(DW_OP_plus_uconst, 4) !llvm.module.flags = !{!4, !5} diff --git a/test/Transforms/Inline/always-inline.ll b/test/Transforms/Inline/always-inline.ll index 5366b5a16cc7..791eb94779b7 100644 --- a/test/Transforms/Inline/always-inline.ll +++ b/test/Transforms/Inline/always-inline.ll @@ -305,3 +305,14 @@ entry: ret void ; CHECK: ret void } + +define void @inner14() readnone nounwind { +; CHECK: define void @inner14 + ret void +} + +define void @outer14() { +; CHECK: call void @inner14 + call void @inner14() + ret void +} diff --git a/test/Transforms/InstCombine/debuginfo-dce.ll b/test/Transforms/InstCombine/debuginfo-dce.ll index 086743e80820..50b8f1c6068e 100644 --- a/test/Transforms/InstCombine/debuginfo-dce.ll +++ b/test/Transforms/InstCombine/debuginfo-dce.ll @@ -93,12 +93,12 @@ entry: ret void, !dbg !32 } -; CHECK: ![[LOAD_EXPR]] = !DIExpression(DW_OP_deref, DW_OP_plus, 0) -; CHECK: ![[BITCAST_EXPR]] = !DIExpression(DW_OP_plus, 0) -; CHECK: ![[GEP0_EXPR]] = !DIExpression(DW_OP_minus, 8, DW_OP_plus, 0, DW_OP_stack_value) -; CHECK: ![[GEP1_EXPR]] = !DIExpression(DW_OP_minus, 8, DW_OP_stack_value, +; CHECK: ![[LOAD_EXPR]] = !DIExpression(DW_OP_deref, DW_OP_plus_uconst, 0) +; CHECK: ![[BITCAST_EXPR]] = !DIExpression(DW_OP_plus_uconst, 0) +; CHECK: ![[GEP0_EXPR]] = !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_plus_uconst, 0, DW_OP_stack_value) +; CHECK: ![[GEP1_EXPR]] = !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_stack_value, ; CHECK-SAME: DW_OP_LLVM_fragment, 0, 32) -; CHECK: ![[GEP2_EXPR]] = !DIExpression(DW_OP_minus, 8, DW_OP_stack_value) +; CHECK: ![[GEP2_EXPR]] = !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_stack_value) ; Function Attrs: nounwind readnone declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 @@ -130,7 +130,7 @@ attributes #1 = { nounwind readnone } !17 = !{!18} !18 = !DILocalVariable(name: "entry", scope: !14, file: !1, line: 6, type: !4) !19 = !DILocation(line: 6, column: 17, scope: !14) -!20 = !DIExpression(DW_OP_plus, 0) +!20 = !DIExpression(DW_OP_plus_uconst, 0) !21 = !DILocation(line: 11, column: 1, scope: !14) !22 = distinct !DISubprogram(name: "scan", scope: !1, file: !1, line: 4, type: !15, isLocal: false, isDefinition: true, scopeLine: 5, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !17) !23 = !DILocation(line: 6, column: 17, scope: !22) diff --git a/test/Transforms/InstCombine/element-atomic-memcpy-to-loads.ll b/test/Transforms/InstCombine/element-atomic-memcpy-to-loads.ll index 107440f10a5a..230ac1796671 100644 --- a/test/Transforms/InstCombine/element-atomic-memcpy-to-loads.ll +++ b/test/Transforms/InstCombine/element-atomic-memcpy-to-loads.ll @@ -1,10 +1,11 @@ ; RUN: opt -instcombine -unfold-element-atomic-memcpy-max-elements=8 -S < %s | FileCheck %s +; Temporarily an expected failure until inst combine is updated in the next patch target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" -; Test basic unfolding -define void @test1(i8* %Src, i8* %Dst) { -; CHECK-LABEL: test1 -; CHECK-NOT: llvm.memcpy.element.atomic +; Test basic unfolding -- unordered load & store +define void @test1a(i8* %Src, i8* %Dst) { +; CHECK-LABEL: test1a +; CHECK-NOT: llvm.memcpy.element.unordered.atomic ; CHECK-DAG: %memcpy_unfold.src_casted = bitcast i8* %Src to i32* ; CHECK-DAG: %memcpy_unfold.dst_casted = bitcast i8* %Dst to i32* @@ -21,7 +22,7 @@ define void @test1(i8* %Src, i8* %Dst) { ; CHECK-DAG: [[VAL4:%[^\s]+]] = load atomic i32, i32* %{{[^\s]+}} unordered, align 4 ; CHECK-DAG: store atomic i32 [[VAL4]], i32* %{{[^\s]+}} unordered, align 4 entry: - call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 4 %Dst, i8* align 8 %Src, i64 4, i32 4) + call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 8 %Dst, i8* align 4 %Src, i32 16, i32 4) ret void } @@ -31,9 +32,9 @@ define void @test2(i8* %Src, i8* %Dst) { ; CHECK-NOT: load ; CHECK-NOT: store -; CHECK: llvm.memcpy.element.atomic +; CHECK: llvm.memcpy.element.unordered.atomic entry: - call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 4 %Dst, i8* align 4 %Src, i64 1000, i32 4) + call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 8 %Dst, i8* align 4 %Src, i32 256, i32 4) ret void } @@ -43,16 +44,16 @@ define void @test3(i8* %Src, i8* %Dst) { ; CHECK-NOT: load ; CHECK-NOT: store -; CHECK: llvm.memcpy.element.atomic +; CHECK: llvm.memcpy.element.unordered.atomic entry: - call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 64 %Dst, i8* align 64 %Src, i64 4, i32 64) + call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 64 %Dst, i8* align 64 %Src, i32 64, i32 64) ret void } ; Test that we will eliminate redundant bitcasts define void @test4(i64* %Src, i64* %Dst) { ; CHECK-LABEL: test4 -; CHECK-NOT: llvm.memcpy.element.atomic +; CHECK-NOT: llvm.memcpy.element.unordered.atomic ; CHECK-NOT: bitcast @@ -76,17 +77,18 @@ define void @test4(i64* %Src, i64* %Dst) { entry: %Src.casted = bitcast i64* %Src to i8* %Dst.casted = bitcast i64* %Dst to i8* - call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 16 %Dst.casted, i8* align 16 %Src.casted, i64 4, i32 8) + call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 16 %Dst.casted, i8* align 16 %Src.casted, i32 32, i32 8) ret void } +; Test that 0-length unordered atomic memcpy gets removed. define void @test5(i8* %Src, i8* %Dst) { ; CHECK-LABEL: test5 -; CHECK-NOT: llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 64 %Dst, i8* align 64 %Src, i64 0, i32 64) +; CHECK-NOT: llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 64 %Dst, i8* align 64 %Src, i32 0, i32 8) entry: - call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 64 %Dst, i8* align 64 %Src, i64 0, i32 64) + call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 64 %Dst, i8* align 64 %Src, i32 0, i32 8) ret void } -declare void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* nocapture, i8* nocapture, i64, i32) +declare void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32) nounwind diff --git a/test/Transforms/InstCombine/ffs-1.ll b/test/Transforms/InstCombine/ffs-1.ll index d27fb5d89f09..af4ee85216ef 100644 --- a/test/Transforms/InstCombine/ffs-1.ll +++ b/test/Transforms/InstCombine/ffs-1.ll @@ -1,12 +1,12 @@ ; Test that the ffs* library call simplifier works correctly. ; -; RUN: opt < %s -instcombine -S | FileCheck %s -; RUN: opt < %s -mtriple i386-pc-linux -instcombine -S | FileCheck %s -check-prefix=CHECK-FFS -; RUN: opt -instcombine -mtriple=arm64-apple-ios9.0 -S %s | FileCheck --check-prefix=CHECK-FFS %s -; RUN: opt -instcombine -mtriple=arm64-apple-tvos9.0 -S %s | FileCheck --check-prefix=CHECK-FFS %s -; RUN: opt -instcombine -mtriple=thumbv7k-apple-watchos2.0 -S %s | FileCheck --check-prefix=CHECK-FFS %s -; RUN: opt -instcombine -mtriple=x86_64-apple-macosx10.11 -S %s | FileCheck --check-prefix=CHECK-FFS %s -; RUN: opt -instcombine -mtriple=x86_64-freebsd-gnu -S %s | FileCheck --check-prefix=CHECK-FFS %s +; RUN: opt < %s -instcombine -S | FileCheck %s --check-prefix=ALL --check-prefix=GENERIC +; RUN: opt < %s -instcombine -mtriple i386-pc-linux -S | FileCheck %s --check-prefix=ALL --check-prefix=TARGET +; RUN: opt < %s -instcombine -mtriple=arm64-apple-ios9.0 -S | FileCheck %s --check-prefix=ALL --check-prefix=TARGET +; RUN: opt < %s -instcombine -mtriple=arm64-apple-tvos9.0 -S | FileCheck %s --check-prefix=ALL --check-prefix=TARGET +; RUN: opt < %s -instcombine -mtriple=thumbv7k-apple-watchos2.0 -S | FileCheck %s --check-prefix=ALL --check-prefix=TARGET +; RUN: opt < %s -instcombine -mtriple=x86_64-apple-macosx10.11 -S | FileCheck %s --check-prefix=ALL --check-prefix=TARGET +; RUN: opt < %s -instcombine -mtriple=x86_64-freebsd-gnu -S | FileCheck %s --check-prefix=ALL --check-prefix=TARGET declare i32 @ffs(i32) declare i32 @ffsl(i32) @@ -15,123 +15,179 @@ declare i32 @ffsll(i64) ; Check ffs(0) -> 0. define i32 @test_simplify1() { -; CHECK-LABEL: @test_simplify1( +; ALL-LABEL: @test_simplify1( +; ALL-NEXT: ret i32 0 +; %ret = call i32 @ffs(i32 0) ret i32 %ret -; CHECK-NEXT: ret i32 0 } define i32 @test_simplify2() { -; CHECK-FFS-LABEL: @test_simplify2( +; GENERIC-LABEL: @test_simplify2( +; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsl(i32 0) +; GENERIC-NEXT: ret i32 [[RET]] +; +; TARGET-LABEL: @test_simplify2( +; TARGET-NEXT: ret i32 0 +; %ret = call i32 @ffsl(i32 0) ret i32 %ret -; CHECK-FFS-NEXT: ret i32 0 } define i32 @test_simplify3() { -; CHECK-FFS-LABEL: @test_simplify3( +; GENERIC-LABEL: @test_simplify3( +; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsll(i64 0) +; GENERIC-NEXT: ret i32 [[RET]] +; +; TARGET-LABEL: @test_simplify3( +; TARGET-NEXT: ret i32 0 +; %ret = call i32 @ffsll(i64 0) ret i32 %ret -; CHECK-FFS-NEXT: ret i32 0 } ; Check ffs(c) -> cttz(c) + 1, where 'c' is a constant. define i32 @test_simplify4() { -; CHECK-LABEL: @test_simplify4( +; ALL-LABEL: @test_simplify4( +; ALL-NEXT: ret i32 1 +; %ret = call i32 @ffs(i32 1) ret i32 %ret -; CHECK-NEXT: ret i32 1 } define i32 @test_simplify5() { -; CHECK-LABEL: @test_simplify5( +; ALL-LABEL: @test_simplify5( +; ALL-NEXT: ret i32 12 +; %ret = call i32 @ffs(i32 2048) ret i32 %ret -; CHECK-NEXT: ret i32 12 } define i32 @test_simplify6() { -; CHECK-LABEL: @test_simplify6( +; ALL-LABEL: @test_simplify6( +; ALL-NEXT: ret i32 17 +; %ret = call i32 @ffs(i32 65536) ret i32 %ret -; CHECK-NEXT: ret i32 17 } define i32 @test_simplify7() { -; CHECK-FFS-LABEL: @test_simplify7( +; GENERIC-LABEL: @test_simplify7( +; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsl(i32 65536) +; GENERIC-NEXT: ret i32 [[RET]] +; +; TARGET-LABEL: @test_simplify7( +; TARGET-NEXT: ret i32 17 +; %ret = call i32 @ffsl(i32 65536) ret i32 %ret -; CHECK-FFS-NEXT: ret i32 17 } define i32 @test_simplify8() { -; CHECK-FFS-LABEL: @test_simplify8( +; GENERIC-LABEL: @test_simplify8( +; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsll(i64 1024) +; GENERIC-NEXT: ret i32 [[RET]] +; +; TARGET-LABEL: @test_simplify8( +; TARGET-NEXT: ret i32 11 +; %ret = call i32 @ffsll(i64 1024) ret i32 %ret -; CHECK-FFS-NEXT: ret i32 11 } define i32 @test_simplify9() { -; CHECK-FFS-LABEL: @test_simplify9( +; GENERIC-LABEL: @test_simplify9( +; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsll(i64 65536) +; GENERIC-NEXT: ret i32 [[RET]] +; +; TARGET-LABEL: @test_simplify9( +; TARGET-NEXT: ret i32 17 +; %ret = call i32 @ffsll(i64 65536) ret i32 %ret -; CHECK-FFS-NEXT: ret i32 17 } define i32 @test_simplify10() { -; CHECK-FFS-LABEL: @test_simplify10( +; GENERIC-LABEL: @test_simplify10( +; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsll(i64 17179869184) +; GENERIC-NEXT: ret i32 [[RET]] +; +; TARGET-LABEL: @test_simplify10( +; TARGET-NEXT: ret i32 35 +; %ret = call i32 @ffsll(i64 17179869184) ret i32 %ret -; CHECK-FFS-NEXT: ret i32 35 } define i32 @test_simplify11() { -; CHECK-FFS-LABEL: @test_simplify11( +; GENERIC-LABEL: @test_simplify11( +; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsll(i64 281474976710656) +; GENERIC-NEXT: ret i32 [[RET]] +; +; TARGET-LABEL: @test_simplify11( +; TARGET-NEXT: ret i32 49 +; %ret = call i32 @ffsll(i64 281474976710656) ret i32 %ret -; CHECK-FFS-NEXT: ret i32 49 } define i32 @test_simplify12() { -; CHECK-FFS-LABEL: @test_simplify12( +; GENERIC-LABEL: @test_simplify12( +; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsll(i64 1152921504606846976) +; GENERIC-NEXT: ret i32 [[RET]] +; +; TARGET-LABEL: @test_simplify12( +; TARGET-NEXT: ret i32 61 +; %ret = call i32 @ffsll(i64 1152921504606846976) ret i32 %ret -; CHECK-FFS-NEXT: ret i32 61 } ; Check ffs(x) -> x != 0 ? (i32)llvm.cttz(x) + 1 : 0. define i32 @test_simplify13(i32 %x) { -; CHECK-LABEL: @test_simplify13( +; ALL-LABEL: @test_simplify13( +; ALL-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 %x, i1 true) +; ALL-NEXT: [[TMP1:%.*]] = add nuw nsw i32 [[CTTZ]], 1 +; ALL-NEXT: [[TMP2:%.*]] = icmp ne i32 %x, 0 +; ALL-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 0 +; ALL-NEXT: ret i32 [[TMP3]] +; %ret = call i32 @ffs(i32 %x) -; CHECK-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 true) -; CHECK-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i32 [[CTTZ]], 1 -; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 %x, 0 -; CHECK-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[INC]], i32 0 ret i32 %ret -; CHECK-NEXT: ret i32 [[RET]] } define i32 @test_simplify14(i32 %x) { -; CHECK-FFS-LABEL: @test_simplify14( +; GENERIC-LABEL: @test_simplify14( +; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsl(i32 %x) +; GENERIC-NEXT: ret i32 [[RET]] +; +; TARGET-LABEL: @test_simplify14( +; TARGET-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 %x, i1 true) +; TARGET-NEXT: [[TMP1:%.*]] = add nuw nsw i32 [[CTTZ]], 1 +; TARGET-NEXT: [[TMP2:%.*]] = icmp ne i32 %x, 0 +; TARGET-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 0 +; TARGET-NEXT: ret i32 [[TMP3]] +; %ret = call i32 @ffsl(i32 %x) -; CHECK-FFS-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 true) -; CHECK-FFS-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i32 [[CTTZ]], 1 -; CHECK-FFS-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 %x, 0 -; CHECK-FFS-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[INC]], i32 0 ret i32 %ret -; CHECK-FFS-NEXT: ret i32 [[RET]] } define i32 @test_simplify15(i64 %x) { -; CHECK-FFS-LABEL: @test_simplify15( +; GENERIC-LABEL: @test_simplify15( +; GENERIC-NEXT: [[RET:%.*]] = call i32 @ffsll(i64 %x) +; GENERIC-NEXT: ret i32 [[RET]] +; +; TARGET-LABEL: @test_simplify15( +; TARGET-NEXT: [[CTTZ:%.*]] = call i64 @llvm.cttz.i64(i64 %x, i1 true) +; TARGET-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[CTTZ]], 1 +; TARGET-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32 +; TARGET-NEXT: [[TMP3:%.*]] = icmp ne i64 %x, 0 +; TARGET-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 0 +; TARGET-NEXT: ret i32 [[TMP4]] +; %ret = call i32 @ffsll(i64 %x) -; CHECK-FFS-NEXT: [[CTTZ:%[a-z0-9]+]] = call i64 @llvm.cttz.i64(i64 %x, i1 true) -; CHECK-FFS-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i64 [[CTTZ]], 1 -; CHECK-FFS-NEXT: [[TRUNC:%[a-z0-9]+]] = trunc i64 [[INC]] to i32 -; CHECK-FFS-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i64 %x, 0 -; CHECK-FFS-NEXT: [[RET:%[a-z0-9]+]] = select i1 [[CMP]], i32 [[TRUNC]], i32 0 ret i32 %ret -; CHECK-FFS-NEXT: ret i32 [[RET]] } + diff --git a/test/Transforms/InstCombine/lshr.ll b/test/Transforms/InstCombine/lshr.ll index 71b25177162b..4cdcb98f730c 100644 --- a/test/Transforms/InstCombine/lshr.ll +++ b/test/Transforms/InstCombine/lshr.ll @@ -122,10 +122,19 @@ define <2 x i8> @bool_zext_splat(<2 x i1> %x) { ret <2 x i8> %hibit } -; FIXME: The replicated sign bits are all that's left. This could be ashr+zext. - -define i16 @smear_sign_and_widen(i4 %x) { +define i32 @smear_sign_and_widen(i8 %x) { ; CHECK-LABEL: @smear_sign_and_widen( +; CHECK-NEXT: [[TMP1:%.*]] = ashr i8 %x, 7 +; CHECK-NEXT: [[HIBIT:%.*]] = zext i8 [[TMP1]] to i32 +; CHECK-NEXT: ret i32 [[HIBIT]] +; + %sext = sext i8 %x to i32 + %hibit = lshr i32 %sext, 24 + ret i32 %hibit +} + +define i16 @smear_sign_and_widen_should_not_change_type(i4 %x) { +; CHECK-LABEL: @smear_sign_and_widen_should_not_change_type( ; CHECK-NEXT: [[SEXT:%.*]] = sext i4 %x to i16 ; CHECK-NEXT: [[HIBIT:%.*]] = lshr i16 [[SEXT]], 12 ; CHECK-NEXT: ret i16 [[HIBIT]] @@ -137,8 +146,8 @@ define i16 @smear_sign_and_widen(i4 %x) { define <2 x i8> @smear_sign_and_widen_splat(<2 x i6> %x) { ; CHECK-LABEL: @smear_sign_and_widen_splat( -; CHECK-NEXT: [[SEXT:%.*]] = sext <2 x i6> %x to <2 x i8> -; CHECK-NEXT: [[HIBIT:%.*]] = lshr <2 x i8> [[SEXT]], <i8 2, i8 2> +; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i6> %x, <i6 2, i6 2> +; CHECK-NEXT: [[HIBIT:%.*]] = zext <2 x i6> [[TMP1]] to <2 x i8> ; CHECK-NEXT: ret <2 x i8> [[HIBIT]] ; %sext = sext <2 x i6> %x to <2 x i8> diff --git a/test/Transforms/InstCombine/onehot_merge.ll b/test/Transforms/InstCombine/onehot_merge.ll index 496d847b5321..47a4ca4b628b 100644 --- a/test/Transforms/InstCombine/onehot_merge.ll +++ b/test/Transforms/InstCombine/onehot_merge.ll @@ -33,3 +33,79 @@ bb: ret i1 %or } +; Same as above but with operands commuted one of the ands, but not the other. +define i1 @foo1_and_commuted(i32 %k, i32 %c1, i32 %c2) { +; CHECK-LABEL: @foo1_and_commuted( +; CHECK-NEXT: [[K2:%.*]] = mul i32 [[K:%.*]], [[K]] +; CHECK-NEXT: [[TMP:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 -2147483648, [[C2:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = or i32 [[TMP]], [[TMP4]] +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[K2]], [[TMP0]] +; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], [[TMP0]] +; CHECK-NEXT: ret i1 [[TMP2]] +; + %k2 = mul i32 %k, %k ; to trick the complexity sorting + %tmp = shl i32 1, %c1 + %tmp4 = lshr i32 -2147483648, %c2 + %tmp1 = and i32 %k2, %tmp + %tmp2 = icmp eq i32 %tmp1, 0 + %tmp5 = and i32 %tmp4, %k2 + %tmp6 = icmp eq i32 %tmp5, 0 + %or = or i1 %tmp2, %tmp6 + ret i1 %or +} + +define i1 @or_consts(i32 %k, i32 %c1, i32 %c2) { +; CHECK-LABEL: @or_consts( +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[K:%.*]], 12 +; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 12 +; CHECK-NEXT: ret i1 [[TMP2]] +; + %tmp1 = and i32 4, %k + %tmp2 = icmp ne i32 %tmp1, 0 + %tmp5 = and i32 8, %k + %tmp6 = icmp ne i32 %tmp5, 0 + %or = and i1 %tmp2, %tmp6 + ret i1 %or +} + +define i1 @foo1_or(i32 %k, i32 %c1, i32 %c2) { +; CHECK-LABEL: @foo1_or( +; CHECK-NEXT: [[TMP:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 -2147483648, [[C2:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[TMP]], [[TMP4]] +; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]] +; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]] +; CHECK-NEXT: ret i1 [[TMP3]] +; + %tmp = shl i32 1, %c1 + %tmp4 = lshr i32 -2147483648, %c2 + %tmp1 = and i32 %tmp, %k + %tmp2 = icmp ne i32 %tmp1, 0 + %tmp5 = and i32 %tmp4, %k + %tmp6 = icmp ne i32 %tmp5, 0 + %or = and i1 %tmp2, %tmp6 + ret i1 %or +} + +; Same as above but with operands commuted one of the ors, but not the other. +define i1 @foo1_or_commuted(i32 %k, i32 %c1, i32 %c2) { +; CHECK-LABEL: @foo1_or_commuted( +; CHECK-NEXT: [[K2:%.*]] = mul i32 [[K:%.*]], [[K]] +; CHECK-NEXT: [[TMP:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[TMP4:%.*]] = lshr i32 -2147483648, [[C2:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[TMP]], [[TMP4]] +; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K2]], [[TMP1]] +; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]] +; CHECK-NEXT: ret i1 [[TMP3]] +; + %k2 = mul i32 %k, %k ; to trick the complexity sorting + %tmp = shl i32 1, %c1 + %tmp4 = lshr i32 -2147483648, %c2 + %tmp1 = and i32 %k2, %tmp + %tmp2 = icmp ne i32 %tmp1, 0 + %tmp5 = and i32 %tmp4, %k2 + %tmp6 = icmp ne i32 %tmp5, 0 + %or = and i1 %tmp2, %tmp6 + ret i1 %or +} diff --git a/test/Transforms/InstCombine/or-xor.ll b/test/Transforms/InstCombine/or-xor.ll index f2bc290d79a4..485f9612376a 100644 --- a/test/Transforms/InstCombine/or-xor.ll +++ b/test/Transforms/InstCombine/or-xor.ll @@ -114,6 +114,17 @@ define i32 @test10(i32 %A, i32 %B) { ret i32 %or } +define i32 @test10_commuted(i32 %A, i32 %B) { +; CHECK-LABEL: @test10_commuted( +; CHECK-NEXT: ret i32 -1 +; + %xor1 = xor i32 %B, %A + %not = xor i32 %A, -1 + %xor2 = xor i32 %not, %B + %or = or i32 %xor2, %xor1 + ret i32 %or +} + ; (x | y) & ((~x) ^ y) -> (x & y) define i32 @test11(i32 %x, i32 %y) { ; CHECK-LABEL: @test11( @@ -300,3 +311,36 @@ define i8 @or_xor_or(i8 %x) { ret i8 %or2 } +define i8 @test17(i8 %A, i8 %B) { +; CHECK-LABEL: @test17( +; CHECK-NEXT: [[XOR1:%.*]] = xor i8 [[B:%.*]], [[A:%.*]] +; CHECK-NEXT: [[NOT:%.*]] = xor i8 [[A]], 33 +; CHECK-NEXT: [[XOR2:%.*]] = xor i8 [[NOT]], [[B]] +; CHECK-NEXT: [[OR:%.*]] = or i8 [[XOR1]], [[XOR2]] +; CHECK-NEXT: [[RES:%.*]] = mul i8 [[OR]], [[XOR2]] +; CHECK-NEXT: ret i8 [[RES]] +; + %xor1 = xor i8 %B, %A + %not = xor i8 %A, 33 + %xor2 = xor i8 %not, %B + %or = or i8 %xor1, %xor2 + %res = mul i8 %or, %xor2 ; to increase the use count for the xor + ret i8 %res +} + +define i8 @test18(i8 %A, i8 %B) { +; CHECK-LABEL: @test18( +; CHECK-NEXT: [[XOR1:%.*]] = xor i8 [[B:%.*]], [[A:%.*]] +; CHECK-NEXT: [[NOT:%.*]] = xor i8 [[A]], 33 +; CHECK-NEXT: [[XOR2:%.*]] = xor i8 [[NOT]], [[B]] +; CHECK-NEXT: [[OR:%.*]] = or i8 [[XOR2]], [[XOR1]] +; CHECK-NEXT: [[RES:%.*]] = mul i8 [[OR]], [[XOR2]] +; CHECK-NEXT: ret i8 [[RES]] +; + %xor1 = xor i8 %B, %A + %not = xor i8 %A, 33 + %xor2 = xor i8 %not, %B + %or = or i8 %xor2, %xor1 + %res = mul i8 %or, %xor2 ; to increase the use count for the xor + ret i8 %res +} diff --git a/test/Transforms/InstCombine/select-with-bitwise-ops.ll b/test/Transforms/InstCombine/select-with-bitwise-ops.ll index 68b73af21a8d..faeb4e046aca 100644 --- a/test/Transforms/InstCombine/select-with-bitwise-ops.ll +++ b/test/Transforms/InstCombine/select-with-bitwise-ops.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -instcombine -S | FileCheck %s +target datalayout = "n8:16:32:64" + define i32 @select_icmp_eq_and_1_0_or_2(i32 %x, i32 %y) { ; CHECK-LABEL: @select_icmp_eq_and_1_0_or_2( ; CHECK-NEXT: [[AND:%.*]] = shl i32 %x, 1 @@ -295,3 +297,269 @@ define i32 @test67(i16 %x) { ret i32 %3 } +define i32 @test68(i32 %x, i32 %y) { +; CHECK-LABEL: @test68( +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8 +; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[TMP1]], -1 +; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2 +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[OR]] +; CHECK-NEXT: ret i32 [[SELECT]] +; + %and = and i32 %x, 128 + %cmp = icmp eq i32 %and, 0 + %or = or i32 %y, 2 + %select = select i1 %cmp, i32 %y, i32 %or + ret i32 %select +} + +define i32 @test69(i32 %x, i32 %y) { +; CHECK-LABEL: @test69( +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i8 +; CHECK-NEXT: [[CMP:%.*]] = icmp slt i8 [[TMP1]], 0 +; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2 +; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[OR]] +; CHECK-NEXT: ret i32 [[SELECT]] +; + %and = and i32 %x, 128 + %cmp = icmp ne i32 %and, 0 + %or = or i32 %y, 2 + %select = select i1 %cmp, i32 %y, i32 %or + ret i32 %select +} + +define i32 @shift_no_xor_multiuse_or(i32 %x, i32 %y) { +; CHECK-LABEL: @shift_no_xor_multiuse_or( +; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2 +; CHECK-NEXT: [[AND:%.*]] = shl i32 [[X:%.*]], 1 +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 2 +; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y]] +; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[OR]] +; CHECK-NEXT: ret i32 [[RES]] +; + %and = and i32 %x, 1 + %cmp = icmp eq i32 %and, 0 + %or = or i32 %y, 2 + %select = select i1 %cmp, i32 %y, i32 %or + %res = mul i32 %select, %or ; to bump up use count of the Or + ret i32 %res +} + +define i32 @no_shift_no_xor_multiuse_or(i32 %x, i32 %y) { +; CHECK-LABEL: @no_shift_no_xor_multiuse_or( +; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096 +; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 4096 +; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], [[Y]] +; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP1]], [[OR]] +; CHECK-NEXT: ret i32 [[RES]] +; + %and = and i32 %x, 4096 + %cmp = icmp eq i32 %and, 0 + %or = or i32 %y, 4096 + %select = select i1 %cmp, i32 %y, i32 %or + %res = mul i32 %select, %or ; to bump up use count of the Or + ret i32 %res +} + +define i32 @no_shift_xor_multiuse_or(i32 %x, i32 %y) { +; CHECK-LABEL: @no_shift_xor_multiuse_or( +; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096 +; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 4096 +; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND]], 4096 +; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y]] +; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[OR]] +; CHECK-NEXT: ret i32 [[RES]] +; + %and = and i32 %x, 4096 + %cmp = icmp ne i32 0, %and + %or = or i32 %y, 4096 + %select = select i1 %cmp, i32 %y, i32 %or + %res = mul i32 %select, %or ; to bump up use count of the Or + ret i32 %res +} + +; TODO this increased the number of instructions +define i32 @shift_xor_multiuse_or(i32 %x, i32 %y) { +; CHECK-LABEL: @shift_xor_multiuse_or( +; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2048 +; CHECK-NEXT: [[AND:%.*]] = lshr i32 [[X:%.*]], 1 +; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[AND]], 2048 +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 2048 +; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], [[Y]] +; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP3]], [[OR]] +; CHECK-NEXT: ret i32 [[RES]] +; + %and = and i32 %x, 4096 + %cmp = icmp ne i32 0, %and + %or = or i32 %y, 2048 + %select = select i1 %cmp, i32 %y, i32 %or + %res = mul i32 %select, %or ; to bump up use count of the Or + ret i32 %res +} + +define i32 @shift_no_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) { +; CHECK-LABEL: @shift_no_xor_multiuse_cmp( +; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1 +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i32 [[AND]], 1 +; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]] +; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]] +; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[SELECT2]] +; CHECK-NEXT: ret i32 [[RES]] +; + %and = and i32 %x, 1 + %cmp = icmp eq i32 %and, 0 + %or = or i32 %y, 2 + %select = select i1 %cmp, i32 %y, i32 %or + %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp + %res = mul i32 %select, %select2 + ret i32 %res +} + +define i32 @no_shift_no_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) { +; CHECK-LABEL: @no_shift_no_xor_multiuse_cmp( +; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096 +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], [[Y:%.*]] +; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]] +; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP1]], [[SELECT2]] +; CHECK-NEXT: ret i32 [[RES]] +; + %and = and i32 %x, 4096 + %cmp = icmp eq i32 %and, 0 + %or = or i32 %y, 4096 + %select = select i1 %cmp, i32 %y, i32 %or + %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp + %res = mul i32 %select, %select2 + ret i32 %res +} + +define i32 @no_shift_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) { +; CHECK-LABEL: @no_shift_xor_multiuse_cmp( +; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096 +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND]], 4096 +; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y:%.*]] +; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]] +; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[SELECT2]] +; CHECK-NEXT: ret i32 [[RES]] +; + %and = and i32 %x, 4096 + %cmp = icmp ne i32 0, %and + %or = or i32 %y, 4096 + %select = select i1 %cmp, i32 %y, i32 %or + %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp + %res = mul i32 %select, %select2 + ret i32 %res +} + +; TODO this increased the number of instructions +define i32 @shift_xor_multiuse_cmp(i32 %x, i32 %y, i32 %z, i32 %w) { +; CHECK-LABEL: @shift_xor_multiuse_cmp( +; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096 +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = lshr exact i32 [[AND]], 1 +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 2048 +; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], [[Y:%.*]] +; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]] +; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP3]], [[SELECT2]] +; CHECK-NEXT: ret i32 [[RES]] +; + %and = and i32 %x, 4096 + %cmp = icmp ne i32 0, %and + %or = or i32 %y, 2048 + %select = select i1 %cmp, i32 %y, i32 %or + %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp + %res = mul i32 %select, %select2 + ret i32 %res +} + +; TODO this increased the number of instructions +define i32 @shift_no_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32 %w) { +; CHECK-LABEL: @shift_no_xor_multiuse_cmp_or( +; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 1 +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0 +; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2 +; CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i32 [[AND]], 1 +; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y]] +; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]] +; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[SELECT2]] +; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[OR]] +; CHECK-NEXT: ret i32 [[RES2]] +; + %and = and i32 %x, 1 + %cmp = icmp eq i32 %and, 0 + %or = or i32 %y, 2 + %select = select i1 %cmp, i32 %y, i32 %or + %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp + %res = mul i32 %select, %select2 + %res2 = mul i32 %res, %or ; to bump up the use count of the or + ret i32 %res2 +} + +define i32 @no_shift_no_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32 %w) { +; CHECK-LABEL: @no_shift_no_xor_multiuse_cmp_or( +; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096 +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0 +; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 4096 +; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], [[Y]] +; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]] +; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP1]], [[SELECT2]] +; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[OR]] +; CHECK-NEXT: ret i32 [[RES2]] +; + %and = and i32 %x, 4096 + %cmp = icmp eq i32 %and, 0 + %or = or i32 %y, 4096 + %select = select i1 %cmp, i32 %y, i32 %or + %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp + %res = mul i32 %select, %select2 + %res2 = mul i32 %res, %or ; to bump up the use count of the or + ret i32 %res2 +} + +; TODO this increased the number of instructions +define i32 @no_shift_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32 %w) { +; CHECK-LABEL: @no_shift_xor_multiuse_cmp_or( +; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096 +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0 +; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 4096 +; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[AND]], 4096 +; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], [[Y]] +; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]] +; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP2]], [[SELECT2]] +; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[OR]] +; CHECK-NEXT: ret i32 [[RES2]] +; + %and = and i32 %x, 4096 + %cmp = icmp ne i32 0, %and + %or = or i32 %y, 4096 + %select = select i1 %cmp, i32 %y, i32 %or + %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp + %res = mul i32 %select, %select2 + %res2 = mul i32 %res, %or ; to bump up the use count of the or + ret i32 %res2 +} + +; TODO this increased the number of instructions +define i32 @shift_xor_multiuse_cmp_or(i32 %x, i32 %y, i32 %z, i32 %w) { +; CHECK-LABEL: @shift_xor_multiuse_cmp_or( +; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], 4096 +; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0 +; CHECK-NEXT: [[OR:%.*]] = or i32 [[Y:%.*]], 2048 +; CHECK-NEXT: [[TMP1:%.*]] = lshr exact i32 [[AND]], 1 +; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], 2048 +; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], [[Y]] +; CHECK-NEXT: [[SELECT2:%.*]] = select i1 [[CMP]], i32 [[Z:%.*]], i32 [[W:%.*]] +; CHECK-NEXT: [[RES:%.*]] = mul i32 [[TMP3]], [[SELECT2]] +; CHECK-NEXT: [[RES2:%.*]] = mul i32 [[RES]], [[OR]] +; CHECK-NEXT: ret i32 [[RES2]] +; + %and = and i32 %x, 4096 + %cmp = icmp ne i32 0, %and + %or = or i32 %y, 2048 + %select = select i1 %cmp, i32 %y, i32 %or + %select2 = select i1 %cmp, i32 %z, i32 %w ; to bump up use count of the cmp + %res = mul i32 %select, %select2 + %res2 = mul i32 %res, %or ; to bump up the use count of the or + ret i32 %res2 +} diff --git a/test/Transforms/InstCombine/shift.ll b/test/Transforms/InstCombine/shift.ll index ce8e2fcd38b9..68bbf35d1e65 100644 --- a/test/Transforms/InstCombine/shift.ll +++ b/test/Transforms/InstCombine/shift.ll @@ -1306,3 +1306,13 @@ define <2 x i8> @lshr_demanded_bits_splat(<2 x i8> %x) { ret <2 x i8> %shr } +; Make sure known bits works correctly with non power of 2 bit widths. +define i7 @test65(i7 %a, i7 %b) { +; CHECK-LABEL: @test65( +; CHECK-NEXT: ret i7 0 +; + %shiftamt = and i7 %b, 6 ; this ensures the shift amount is even and less than the bit width. + %x = lshr i7 42, %shiftamt ; 42 has a zero in every even numbered bit and a one in every odd bit. + %y = and i7 %x, 1 ; this extracts the lsb which should be 0 because we shifted an even number of bits and all even bits of the shift input are 0. + ret i7 %y +} diff --git a/test/Transforms/InstCombine/xor2.ll b/test/Transforms/InstCombine/xor2.ll index 3afbf632f6e1..49e6b999fbce 100644 --- a/test/Transforms/InstCombine/xor2.ll +++ b/test/Transforms/InstCombine/xor2.ll @@ -325,3 +325,36 @@ define i32 @test14(i32 %a, i32 %b, i32 %c) { ret i32 %xor } +define i8 @test15(i8 %A, i8 %B) { +; CHECK-LABEL: @test15( +; CHECK-NEXT: [[XOR1:%.*]] = xor i8 [[B:%.*]], [[A:%.*]] +; CHECK-NEXT: [[NOT:%.*]] = xor i8 [[A]], 33 +; CHECK-NEXT: [[XOR2:%.*]] = xor i8 [[NOT]], [[B]] +; CHECK-NEXT: [[AND:%.*]] = and i8 [[XOR1]], [[XOR2]] +; CHECK-NEXT: [[RES:%.*]] = mul i8 [[AND]], [[XOR2]] +; CHECK-NEXT: ret i8 [[RES]] +; + %xor1 = xor i8 %B, %A + %not = xor i8 %A, 33 + %xor2 = xor i8 %not, %B + %and = and i8 %xor1, %xor2 + %res = mul i8 %and, %xor2 ; to increase the use count for the xor + ret i8 %res +} + +define i8 @test16(i8 %A, i8 %B) { +; CHECK-LABEL: @test16( +; CHECK-NEXT: [[XOR1:%.*]] = xor i8 [[B:%.*]], [[A:%.*]] +; CHECK-NEXT: [[NOT:%.*]] = xor i8 [[A]], 33 +; CHECK-NEXT: [[XOR2:%.*]] = xor i8 [[NOT]], [[B]] +; CHECK-NEXT: [[AND:%.*]] = and i8 [[XOR2]], [[XOR1]] +; CHECK-NEXT: [[RES:%.*]] = mul i8 [[AND]], [[XOR2]] +; CHECK-NEXT: ret i8 [[RES]] +; + %xor1 = xor i8 %B, %A + %not = xor i8 %A, 33 + %xor2 = xor i8 %not, %B + %and = and i8 %xor2, %xor1 + %res = mul i8 %and, %xor2 ; to increase the use count for the xor + ret i8 %res +} diff --git a/test/Transforms/LoopIdiom/X86/unordered-atomic-memcpy.ll b/test/Transforms/LoopIdiom/X86/unordered-atomic-memcpy.ll index ec93847178b5..d52378b864ff 100644 --- a/test/Transforms/LoopIdiom/X86/unordered-atomic-memcpy.ll +++ b/test/Transforms/LoopIdiom/X86/unordered-atomic-memcpy.ll @@ -5,7 +5,7 @@ target triple = "x86_64-unknown-linux-gnu" ;; memcpy.atomic formation (atomic load & store) define void @test1(i64 %Size) nounwind ssp { ; CHECK-LABEL: @test1( -; CHECK: call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 1 %Dest, i8* align 1 %Base, i64 %Size, i32 1) +; CHECK: call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %Dest, i8* align 1 %Base, i64 %Size, i32 1) ; CHECK-NOT: store ; CHECK: ret void bb.nph: @@ -30,7 +30,7 @@ for.end: ; preds = %for.body, %entry ;; memcpy.atomic formation (atomic store, normal load) define void @test2(i64 %Size) nounwind ssp { ; CHECK-LABEL: @test2( -; CHECK: call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 1 %Dest, i8* align 1 %Base, i64 %Size, i32 1) +; CHECK: call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %Dest, i8* align 1 %Base, i64 %Size, i32 1) ; CHECK-NOT: store ; CHECK: ret void bb.nph: @@ -55,7 +55,7 @@ for.end: ; preds = %for.body, %entry ;; memcpy.atomic formation rejection (atomic store, normal load w/ no align) define void @test2b(i64 %Size) nounwind ssp { ; CHECK-LABEL: @test2b( -; CHECK-NOT: call void @llvm.memcpy.element.atomic +; CHECK-NOT: call void @llvm.memcpy.element.unordered.atomic ; CHECK: store ; CHECK: ret void bb.nph: @@ -80,7 +80,7 @@ for.end: ; preds = %for.body, %entry ;; memcpy.atomic formation rejection (atomic store, normal load w/ bad align) define void @test2c(i64 %Size) nounwind ssp { ; CHECK-LABEL: @test2c( -; CHECK-NOT: call void @llvm.memcpy.element.atomic +; CHECK-NOT: call void @llvm.memcpy.element.unordered.atomic ; CHECK: store ; CHECK: ret void bb.nph: @@ -105,7 +105,7 @@ for.end: ; preds = %for.body, %entry ;; memcpy.atomic formation rejection (atomic store w/ bad align, normal load) define void @test2d(i64 %Size) nounwind ssp { ; CHECK-LABEL: @test2d( -; CHECK-NOT: call void @llvm.memcpy.element.atomic +; CHECK-NOT: call void @llvm.memcpy.element.unordered.atomic ; CHECK: store ; CHECK: ret void bb.nph: @@ -131,7 +131,7 @@ for.end: ; preds = %for.body, %entry ;; memcpy.atomic formation (normal store, atomic load) define void @test3(i64 %Size) nounwind ssp { ; CHECK-LABEL: @test3( -; CHECK: call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 1 %Dest, i8* align 1 %Base, i64 %Size, i32 1) +; CHECK: call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %Dest, i8* align 1 %Base, i64 %Size, i32 1) ; CHECK-NOT: store ; CHECK: ret void bb.nph: @@ -156,7 +156,7 @@ for.end: ; preds = %for.body, %entry ;; memcpy.atomic formation rejection (normal store w/ no align, atomic load) define void @test3b(i64 %Size) nounwind ssp { ; CHECK-LABEL: @test3b( -; CHECK-NOT: call void @llvm.memcpy.element.atomic +; CHECK-NOT: call void @llvm.memcpy.element.unordered.atomic ; CHECK: store ; CHECK: ret void bb.nph: @@ -181,7 +181,7 @@ for.end: ; preds = %for.body, %entry ;; memcpy.atomic formation rejection (normal store, atomic load w/ bad align) define void @test3c(i64 %Size) nounwind ssp { ; CHECK-LABEL: @test3c( -; CHECK-NOT: call void @llvm.memcpy.element.atomic +; CHECK-NOT: call void @llvm.memcpy.element.unordered.atomic ; CHECK: store ; CHECK: ret void bb.nph: @@ -206,7 +206,7 @@ for.end: ; preds = %for.body, %entry ;; memcpy.atomic formation rejection (normal store w/ bad align, atomic load) define void @test3d(i64 %Size) nounwind ssp { ; CHECK-LABEL: @test3d( -; CHECK-NOT: call void @llvm.memcpy.element.atomic +; CHECK-NOT: call void @llvm.memcpy.element.unordered.atomic ; CHECK: store ; CHECK: ret void bb.nph: @@ -232,7 +232,7 @@ for.end: ; preds = %for.body, %entry ;; memcpy.atomic formation rejection (atomic load, ordered-atomic store) define void @test4(i64 %Size) nounwind ssp { ; CHECK-LABEL: @test4( -; CHECK-NOT: call void @llvm.memcpy.element.atomic +; CHECK-NOT: call void @llvm.memcpy.element.unordered.atomic ; CHECK: store ; CHECK: ret void bb.nph: @@ -257,7 +257,7 @@ for.end: ; preds = %for.body, %entry ;; memcpy.atomic formation rejection (ordered-atomic load, unordered-atomic store) define void @test5(i64 %Size) nounwind ssp { ; CHECK-LABEL: @test5( -; CHECK-NOT: call void @llvm.memcpy.element.atomic +; CHECK-NOT: call void @llvm.memcpy.element.unordered.atomic ; CHECK: store ; CHECK: ret void bb.nph: @@ -282,7 +282,8 @@ for.end: ; preds = %for.body, %entry ;; memcpy.atomic formation (atomic load & store) -- element size 2 define void @test6(i64 %Size) nounwind ssp { ; CHECK-LABEL: @test6( -; CHECK: call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 2 %Dest{{[0-9]*}}, i8* align 2 %Base{{[0-9]*}}, i64 %Size, i32 2) +; CHECK: [[Sz:%[0-9]+]] = shl i64 %Size, 1 +; CHECK: call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 2 %Dest{{[0-9]*}}, i8* align 2 %Base{{[0-9]*}}, i64 [[Sz]], i32 2) ; CHECK-NOT: store ; CHECK: ret void bb.nph: @@ -307,7 +308,8 @@ for.end: ; preds = %for.body, %entry ;; memcpy.atomic formation (atomic load & store) -- element size 4 define void @test7(i64 %Size) nounwind ssp { ; CHECK-LABEL: @test7( -; CHECK: call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 4 %Dest{{[0-9]*}}, i8* align 4 %Base{{[0-9]*}}, i64 %Size, i32 4) +; CHECK: [[Sz:%[0-9]+]] = shl i64 %Size, 2 +; CHECK: call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 4 %Dest{{[0-9]*}}, i8* align 4 %Base{{[0-9]*}}, i64 [[Sz]], i32 4) ; CHECK-NOT: store ; CHECK: ret void bb.nph: @@ -332,7 +334,8 @@ for.end: ; preds = %for.body, %entry ;; memcpy.atomic formation (atomic load & store) -- element size 8 define void @test8(i64 %Size) nounwind ssp { ; CHECK-LABEL: @test8( -; CHECK: call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 8 %Dest{{[0-9]*}}, i8* align 8 %Base{{[0-9]*}}, i64 %Size, i32 8) +; CHECK: [[Sz:%[0-9]+]] = shl i64 %Size, 3 +; CHECK: call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 8 %Dest{{[0-9]*}}, i8* align 8 %Base{{[0-9]*}}, i64 [[Sz]], i32 8) ; CHECK-NOT: store ; CHECK: ret void bb.nph: @@ -357,7 +360,8 @@ for.end: ; preds = %for.body, %entry ;; memcpy.atomic formation rejection (atomic load & store) -- element size 16 define void @test9(i64 %Size) nounwind ssp { ; CHECK-LABEL: @test9( -; CHECK: call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 16 %Dest{{[0-9]*}}, i8* align 16 %Base{{[0-9]*}}, i64 %Size, i32 16) +; CHECK: [[Sz:%[0-9]+]] = shl i64 %Size, 4 +; CHECK: call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 16 %Dest{{[0-9]*}}, i8* align 16 %Base{{[0-9]*}}, i64 [[Sz]], i32 16) ; CHECK-NOT: store ; CHECK: ret void bb.nph: @@ -382,7 +386,7 @@ for.end: ; preds = %for.body, %entry ;; memcpy.atomic formation rejection (atomic load & store) -- element size 32 define void @test10(i64 %Size) nounwind ssp { ; CHECK-LABEL: @test10( -; CHECK-NOT: call void @llvm.memcpy.element.atomic +; CHECK-NOT: call void @llvm.memcpy.element.unordered.atomic ; CHECK: store ; CHECK: ret void bb.nph: diff --git a/test/Transforms/LoopIdiom/unordered-atomic-memcpy-noarch.ll b/test/Transforms/LoopIdiom/unordered-atomic-memcpy-noarch.ll index b2528f1c2457..341a7a0baebf 100644 --- a/test/Transforms/LoopIdiom/unordered-atomic-memcpy-noarch.ll +++ b/test/Transforms/LoopIdiom/unordered-atomic-memcpy-noarch.ll @@ -5,7 +5,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 ;; Will not create call due to a max element size of 0 define void @test1(i64 %Size) nounwind ssp { ; CHECK-LABEL: @test1( -; CHECK-NOT: call void @llvm.memcpy.element.atomic +; CHECK-NOT: call void @llvm.memcpy.element.unordered.atomic ; CHECK: store ; CHECK: ret void bb.nph: diff --git a/test/Transforms/LowerTypeTests/Inputs/import-icall.yaml b/test/Transforms/LowerTypeTests/Inputs/import-icall.yaml new file mode 100644 index 000000000000..17b634acd0e1 --- /dev/null +++ b/test/Transforms/LowerTypeTests/Inputs/import-icall.yaml @@ -0,0 +1,19 @@ +--- +TypeIdMap: + typeid1: + TTRes: + Kind: AllOnes + SizeM1BitWidth: 7 + typeid2: + TTRes: + Kind: Single + SizeM1BitWidth: 0 +WithGlobalValueDeadStripping: false +CfiFunctionDefs: + - local_a + - local_b + - does_not_exist +CfiFunctionDecls: + - external + - external_weak +... diff --git a/test/Transforms/LowerTypeTests/export-icall.ll b/test/Transforms/LowerTypeTests/export-icall.ll new file mode 100644 index 000000000000..ad3604899306 --- /dev/null +++ b/test/Transforms/LowerTypeTests/export-icall.ll @@ -0,0 +1,70 @@ +; RUN: opt -S -lowertypetests -lowertypetests-summary-action=export -lowertypetests-read-summary=%S/Inputs/use-typeid1-typeid2.yaml -lowertypetests-write-summary=%t < %s | FileCheck %s +; RUN: FileCheck --check-prefix=SUMMARY %s < %t + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define void @h(i8 %x) !type !2 { + ret void +} + +declare !type !8 void @f(i32 %x) + +!cfi.functions = !{!0, !1, !3, !4, !5, !6} + +; declaration of @h with a different type is ignored +!0 = !{!"h", i8 1, !7} + +; extern_weak declaration of @h with a different type is ignored as well +!1 = !{!"h", i8 2, !8} +!2 = !{i64 0, !"typeid1"} + +; definition of @f replaces types on the IR declaration above +!3 = !{!"f", i8 0, !2} +!4 = !{!"external", i8 1, !2} +!5 = !{!"external_weak", i8 2, !2} +!6 = !{!"g", i8 0, !7} +!7 = !{i64 0, !"typeid2"} +!8 = !{i64 0, !"typeid3"} + + +; CHECK-DAG: @__typeid_typeid1_global_addr = hidden alias i8, bitcast (void ()* [[JT1:.*]] to i8*) +; CHECK-DAG: @__typeid_typeid1_align = hidden alias i8, inttoptr (i8 3 to i8*) +; CHECK-DAG: @__typeid_typeid1_size_m1 = hidden alias i8, inttoptr (i64 3 to i8*) + +; CHECK-DAG: @h = alias void (i8), bitcast (void ()* [[JT1]] to void (i8)*) +; CHECK-DAG: @f = alias void (i32), {{.*}}getelementptr {{.*}}void ()* [[JT1]] +; CHECK-DAG: @external.cfi_jt = hidden alias void (), {{.*}}getelementptr {{.*}}void ()* [[JT1]] +; CHECK-DAG: @external_weak.cfi_jt = hidden alias void (), {{.*}}getelementptr {{.*}}void ()* [[JT1]] + +; CHECK-DAG: @__typeid_typeid2_global_addr = hidden alias i8, bitcast (void ()* [[JT2:.*]] to i8*) + +; CHECK-DAG: @g = alias void (), void ()* [[JT2]] + +; CHECK-DAG: define internal void @h.cfi(i8 {{.*}}) !type !{{.*}} +; CHECK-DAG: declare !type !{{.*}} void @external() +; CHECK-DAG: declare !type !{{.*}} void @external_weak() +; CHECK-DAG: declare !type !{{.*}} void @f.cfi(i32) +; CHECK-DAG: declare !type !{{.*}} void @g.cfi() + + +; SUMMARY: TypeIdMap: +; SUMMARY-NEXT: typeid1: +; SUMMARY-NEXT: TTRes: +; SUMMARY-NEXT: Kind: AllOnes +; SUMMARY-NEXT: SizeM1BitWidth: 7 +; SUMMARY-NEXT: WPDRes: +; SUMMARY-NEXT: typeid2: +; SUMMARY-NEXT: TTRes: +; SUMMARY-NEXT: Kind: Single +; SUMMARY-NEXT: SizeM1BitWidth: 0 +; SUMMARY-NEXT: WPDRes: + +; SUMMARY: CfiFunctionDefs: +; SUMMARY-NEXT: - f +; SUMMARY-NEXT: - g +; SUMMARY-NEXT: - h +; SUMMARY-NEXT: CfiFunctionDecls: +; SUMMARY-NEXT: - external +; SUMMARY-NEXT: - external_weak +; SUMMARY-NEXT: ... diff --git a/test/Transforms/LowerTypeTests/import-icall.ll b/test/Transforms/LowerTypeTests/import-icall.ll new file mode 100644 index 000000000000..ddeb7fb5c9a2 --- /dev/null +++ b/test/Transforms/LowerTypeTests/import-icall.ll @@ -0,0 +1,40 @@ +; RUN: opt -S -lowertypetests -lowertypetests-summary-action=import -lowertypetests-read-summary=%S/Inputs/import-icall.yaml < %s | FileCheck %s + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define i8 @local_a() { + call void @external() + call void @external_weak() + ret i8 1 +} + +define internal i8 @local_b() { + %x = call i8 @local_a() + ret i8 %x +} + +define i8 @use_b() { + %x = call i8 @local_b() + ret i8 %x +} + + +declare void @external() +declare extern_weak void @external_weak() + +; CHECK: define hidden i8 @local_a.cfi() { +; CHECK-NEXT: call void @external.cfi_jt() +; CHECK-NEXT: call void select (i1 icmp ne (void ()* @external_weak, void ()* null), void ()* @external_weak.cfi_jt, void ()* null)() +; CHECK-NEXT: ret i8 1 +; CHECK-NEXT: } + +; internal @local_b is not the same function as "local_b" in the summary. +; CHECK: define internal i8 @local_b() { +; CHECK-NEXT: call i8 @local_a() + +; CHECK: declare void @external() +; CHECK: declare extern_weak void @external_weak() +; CHECK: declare i8 @local_a() +; CHECK: declare hidden void @external.cfi_jt() +; CHECK: declare hidden void @external_weak.cfi_jt() diff --git a/test/Transforms/PGOProfile/memop_size_opt.ll b/test/Transforms/PGOProfile/memop_size_opt.ll index 19a2b7ed293b..e11f235a48e7 100644 --- a/test/Transforms/PGOProfile/memop_size_opt.ll +++ b/test/Transforms/PGOProfile/memop_size_opt.ll @@ -38,7 +38,7 @@ for.body3: ; MEMOP_OPT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 1, i32 1, i1 false) ; MEMOP_OPT: br label %[[MERGE_LABEL:.*]] ; MEMOP_OPT: [[DEFAULT_LABEL]]: -; MEMOP_OPT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %conv, i32 1, i1 false){{[[:space:]]}} +; MEMOP_OPT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst, i8* %src, i64 %conv, i32 1, i1 false), !prof [[NEWVP:![0-9]+]] ; MEMOP_OPT: br label %[[MERGE_LABEL]] ; MEMOP_OPT: [[MERGE_LABEL]]: ; MEMOP_OPT: switch i64 %conv, label %[[DEFAULT_LABEL2:.*]] [ @@ -48,11 +48,16 @@ for.body3: ; MEMOP_OPT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst2, i8* %src2, i64 1, i32 1, i1 false) ; MEMOP_OPT: br label %[[MERGE_LABEL2:.*]] ; MEMOP_OPT: [[DEFAULT_LABEL2]]: -; MEMOP_OPT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst2, i8* %src2, i64 %conv, i32 1, i1 false){{[[:space:]]}} +; MEMOP_OPT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %dst2, i8* %src2, i64 %conv, i32 1, i1 false), !prof [[NEWVP]] ; MEMOP_OPT: br label %[[MERGE_LABEL2]] ; MEMOP_OPT: [[MERGE_LABEL2]]: ; MEMOP_OPT: br label %for.inc ; MEMOP_OPT: [[SWITCH_BW]] = !{!"branch_weights", i32 457, i32 99} +; Should be 457 total left (original total count 556, minus 99 from specialized +; value 1, which is removed from VP array. Also, we only end up with 5 total +; values, since the default max number of promotions is 5 and therefore +; the rest of the values are ignored when extracting the VP metadata. +; MEMOP_OPT: [[NEWVP]] = !{!"VP", i32 1, i64 457, i64 2, i64 88, i64 3, i64 77, i64 9, i64 72, i64 4, i64 66} for.inc: %inc = add nsw i32 %j.0, 1 diff --git a/test/Transforms/RewriteStatepointsForGC/drop-invalid-metadata.ll b/test/Transforms/RewriteStatepointsForGC/drop-invalid-metadata.ll new file mode 100644 index 000000000000..105afa9def5c --- /dev/null +++ b/test/Transforms/RewriteStatepointsForGC/drop-invalid-metadata.ll @@ -0,0 +1,92 @@ +; RUN: opt -S -rewrite-statepoints-for-gc < %s | FileCheck %s + +; This test checks that metadata that's invalid after RS4GC is dropped. +; We can miscompile if optimizations scheduled after RS4GC uses the +; metadata that's infact invalid. + +declare void @bar() + +declare void @baz(i32) +; Confirm that loadedval instruction does not contain invariant.load metadata. +; but contains the range metadata. +; Since loadedval is not marked invariant, it will prevent incorrectly sinking +; %loadedval in LICM and avoid creation of an unrelocated use of %baseaddr. +define void @test_invariant_load() gc "statepoint-example" { +; CHECK-LABEL: @test_invariant_load +; CHECK: %loadedval = load i32, i32 addrspace(1)* %baseaddr, align 8, !range !0 +bb: + br label %outerloopHdr + +outerloopHdr: ; preds = %bb6, %bb + %baseaddr = phi i32 addrspace(1)* [ undef, %bb ], [ %tmp4, %bb6 ] +; LICM may sink this load to exit block after RS4GC because it's tagged invariant. + %loadedval = load i32, i32 addrspace(1)* %baseaddr, align 8, !range !0, !invariant.load !1 + br label %innerloopHdr + +innerloopHdr: ; preds = %innerlooplatch, %outerloopHdr + %tmp4 = phi i32 addrspace(1)* [ %baseaddr, %outerloopHdr ], [ %gep, %innerlooplatch ] + br label %innermostloophdr + +innermostloophdr: ; preds = %bb6, %innerloopHdr + br i1 undef, label %exitblock, label %bb6 + +bb6: ; preds = %innermostloophdr + switch i32 undef, label %innermostloophdr [ + i32 0, label %outerloopHdr + i32 1, label %innerlooplatch + ] + +innerlooplatch: ; preds = %bb6 + call void @bar() + %gep = getelementptr inbounds i32, i32 addrspace(1)* %tmp4, i64 8 + br label %innerloopHdr + +exitblock: ; preds = %innermostloophdr + %tmp13 = add i32 42, %loadedval + call void @baz(i32 %tmp13) + unreachable +} + +; drop the noalias metadata. +define void @test_noalias(i32 %x, i32 addrspace(1)* %p, i32 addrspace(1)* %q) gc "statepoint-example" { +; CHECK-LABEL: test_noalias +; CHECK: %y = load i32, i32 addrspace(1)* %q, align 16 +; CHECK: gc.statepoint +; CHECK: %p.relocated +; CHECK-NEXT: %p.relocated.casted = bitcast i8 addrspace(1)* %p.relocated to i32 addrspace(1)* +; CHECK-NEXT: store i32 %x, i32 addrspace(1)* %p.relocated.casted, align 16 +entry: + %y = load i32, i32 addrspace(1)* %q, align 16, !noalias !3 + call void @baz(i32 %x) + store i32 %x, i32 addrspace(1)* %p, align 16, !noalias !4 + ret void +} + +; drop the dereferenceable metadata +define void @test_dereferenceable(i32 addrspace(1)* addrspace(1)* %p, i32 %x, i32 addrspace(1)* %q) gc "statepoint-example" { +; CHECK-LABEL: test_dereferenceable +; CHECK: %v1 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* %p +; CHECK-NEXT: %v2 = load i32, i32 addrspace(1)* %v1 +; CHECK: gc.statepoint + %v1 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* %p, !dereferenceable !5 + %v2 = load i32, i32 addrspace(1)* %v1 + call void @baz(i32 %x) + store i32 %v2, i32 addrspace(1)* %q, align 16 + ret void +} + +declare token @llvm.experimental.gc.statepoint.p0f_isVoidi32f(i64, i32, void (i32)*, i32, i32, ...) + +; Function Attrs: nounwind readonly +declare i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(token, i32, i32) #0 + +declare token @llvm.experimental.gc.statepoint.p0f_isVoidf(i64, i32, void ()*, i32, i32, ...) + +attributes #0 = { nounwind readonly } + +!0 = !{i32 0, i32 2147483647} +!1 = !{} +!2 = !{i32 10, i32 1} +!3 = !{!3} +!4 = !{!4} +!5 = !{i64 8} diff --git a/test/Transforms/SLPVectorizer/X86/arith-add.ll b/test/Transforms/SLPVectorizer/X86/arith-add.ll index 0266758b27d2..22b2c7422933 100644 --- a/test/Transforms/SLPVectorizer/X86/arith-add.ll +++ b/test/Transforms/SLPVectorizer/X86/arith-add.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -mtriple=x86_64-unknown -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE +; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=slm -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SLM ; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1 ; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2 ; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=knl -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512 --check-prefix=AVX512F @@ -38,6 +39,25 @@ define void @add_v8i64() { ; SSE-NEXT: store <2 x i64> [[TMP12]], <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @c64, i32 0, i64 6) to <2 x i64>*), align 8 ; SSE-NEXT: ret void ; +; SLM-LABEL: @add_v8i64( +; SLM-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([8 x i64]* @a64 to <2 x i64>*), align 8 +; SLM-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @a64, i32 0, i64 2) to <2 x i64>*), align 8 +; SLM-NEXT: [[TMP3:%.*]] = load <2 x i64>, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @a64, i32 0, i64 4) to <2 x i64>*), align 8 +; SLM-NEXT: [[TMP4:%.*]] = load <2 x i64>, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @a64, i32 0, i64 6) to <2 x i64>*), align 8 +; SLM-NEXT: [[TMP5:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([8 x i64]* @b64 to <2 x i64>*), align 8 +; SLM-NEXT: [[TMP6:%.*]] = load <2 x i64>, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @b64, i32 0, i64 2) to <2 x i64>*), align 8 +; SLM-NEXT: [[TMP7:%.*]] = load <2 x i64>, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @b64, i32 0, i64 4) to <2 x i64>*), align 8 +; SLM-NEXT: [[TMP8:%.*]] = load <2 x i64>, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @b64, i32 0, i64 6) to <2 x i64>*), align 8 +; SLM-NEXT: [[TMP9:%.*]] = add <2 x i64> [[TMP1]], [[TMP5]] +; SLM-NEXT: [[TMP10:%.*]] = add <2 x i64> [[TMP2]], [[TMP6]] +; SLM-NEXT: [[TMP11:%.*]] = add <2 x i64> [[TMP3]], [[TMP7]] +; SLM-NEXT: [[TMP12:%.*]] = add <2 x i64> [[TMP4]], [[TMP8]] +; SLM-NEXT: store <2 x i64> [[TMP9]], <2 x i64>* bitcast ([8 x i64]* @c64 to <2 x i64>*), align 8 +; SLM-NEXT: store <2 x i64> [[TMP10]], <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @c64, i32 0, i64 2) to <2 x i64>*), align 8 +; SLM-NEXT: store <2 x i64> [[TMP11]], <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @c64, i32 0, i64 4) to <2 x i64>*), align 8 +; SLM-NEXT: store <2 x i64> [[TMP12]], <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @c64, i32 0, i64 6) to <2 x i64>*), align 8 +; SLM-NEXT: ret void +; ; AVX-LABEL: @add_v8i64( ; AVX-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([8 x i64]* @a64 to <4 x i64>*), align 8 ; AVX-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @a64, i32 0, i64 4) to <4 x i64>*), align 8 @@ -111,6 +131,25 @@ define void @add_v16i32() { ; SSE-NEXT: store <4 x i32> [[TMP12]], <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @c32, i32 0, i64 12) to <4 x i32>*), align 4 ; SSE-NEXT: ret void ; +; SLM-LABEL: @add_v16i32( +; SLM-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([16 x i32]* @a32 to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @a32, i32 0, i64 4) to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @a32, i32 0, i64 8) to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP4:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @a32, i32 0, i64 12) to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP5:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([16 x i32]* @b32 to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP6:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @b32, i32 0, i64 4) to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP7:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @b32, i32 0, i64 8) to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP8:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @b32, i32 0, i64 12) to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP9:%.*]] = add <4 x i32> [[TMP1]], [[TMP5]] +; SLM-NEXT: [[TMP10:%.*]] = add <4 x i32> [[TMP2]], [[TMP6]] +; SLM-NEXT: [[TMP11:%.*]] = add <4 x i32> [[TMP3]], [[TMP7]] +; SLM-NEXT: [[TMP12:%.*]] = add <4 x i32> [[TMP4]], [[TMP8]] +; SLM-NEXT: store <4 x i32> [[TMP9]], <4 x i32>* bitcast ([16 x i32]* @c32 to <4 x i32>*), align 4 +; SLM-NEXT: store <4 x i32> [[TMP10]], <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @c32, i32 0, i64 4) to <4 x i32>*), align 4 +; SLM-NEXT: store <4 x i32> [[TMP11]], <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @c32, i32 0, i64 8) to <4 x i32>*), align 4 +; SLM-NEXT: store <4 x i32> [[TMP12]], <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @c32, i32 0, i64 12) to <4 x i32>*), align 4 +; SLM-NEXT: ret void +; ; AVX-LABEL: @add_v16i32( ; AVX-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([16 x i32]* @a32 to <8 x i32>*), align 4 ; AVX-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @a32, i32 0, i64 8) to <8 x i32>*), align 4 @@ -216,6 +255,25 @@ define void @add_v32i16() { ; SSE-NEXT: store <8 x i16> [[TMP12]], <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @c16, i32 0, i64 24) to <8 x i16>*), align 2 ; SSE-NEXT: ret void ; +; SLM-LABEL: @add_v32i16( +; SLM-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([32 x i16]* @a16 to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @a16, i32 0, i64 8) to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP3:%.*]] = load <8 x i16>, <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @a16, i32 0, i64 16) to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP4:%.*]] = load <8 x i16>, <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @a16, i32 0, i64 24) to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP5:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([32 x i16]* @b16 to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP6:%.*]] = load <8 x i16>, <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16, i32 0, i64 8) to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP7:%.*]] = load <8 x i16>, <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16, i32 0, i64 16) to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP8:%.*]] = load <8 x i16>, <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16, i32 0, i64 24) to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP9:%.*]] = add <8 x i16> [[TMP1]], [[TMP5]] +; SLM-NEXT: [[TMP10:%.*]] = add <8 x i16> [[TMP2]], [[TMP6]] +; SLM-NEXT: [[TMP11:%.*]] = add <8 x i16> [[TMP3]], [[TMP7]] +; SLM-NEXT: [[TMP12:%.*]] = add <8 x i16> [[TMP4]], [[TMP8]] +; SLM-NEXT: store <8 x i16> [[TMP9]], <8 x i16>* bitcast ([32 x i16]* @c16 to <8 x i16>*), align 2 +; SLM-NEXT: store <8 x i16> [[TMP10]], <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @c16, i32 0, i64 8) to <8 x i16>*), align 2 +; SLM-NEXT: store <8 x i16> [[TMP11]], <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @c16, i32 0, i64 16) to <8 x i16>*), align 2 +; SLM-NEXT: store <8 x i16> [[TMP12]], <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @c16, i32 0, i64 24) to <8 x i16>*), align 2 +; SLM-NEXT: ret void +; ; AVX-LABEL: @add_v32i16( ; AVX-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([32 x i16]* @a16 to <16 x i16>*), align 2 ; AVX-NEXT: [[TMP2:%.*]] = load <16 x i16>, <16 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @a16, i32 0, i64 16) to <16 x i16>*), align 2 diff --git a/test/Transforms/SLPVectorizer/X86/arith-fp.ll b/test/Transforms/SLPVectorizer/X86/arith-fp.ll index e00ed849ee4b..119cf594c905 100644 --- a/test/Transforms/SLPVectorizer/X86/arith-fp.ll +++ b/test/Transforms/SLPVectorizer/X86/arith-fp.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -mtriple=x86_64-unknown -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE +; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=slm -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SLM ; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX ; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX ; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skx -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX @@ -69,13 +70,32 @@ define <2 x double> @buildvector_mul_2f64(<2 x double> %a, <2 x double> %b) { } define <2 x double> @buildvector_div_2f64(<2 x double> %a, <2 x double> %b) { -; CHECK-LABEL: @buildvector_div_2f64( -; CHECK-NEXT: [[TMP1:%.*]] = fdiv <2 x double> [[A:%.*]], [[B:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i32 0 -; CHECK-NEXT: [[R0:%.*]] = insertelement <2 x double> undef, double [[TMP2]], i32 0 -; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP1]], i32 1 -; CHECK-NEXT: [[R1:%.*]] = insertelement <2 x double> [[R0]], double [[TMP3]], i32 1 -; CHECK-NEXT: ret <2 x double> [[R1]] +; SSE-LABEL: @buildvector_div_2f64( +; SSE-NEXT: [[TMP1:%.*]] = fdiv <2 x double> [[A:%.*]], [[B:%.*]] +; SSE-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i32 0 +; SSE-NEXT: [[R0:%.*]] = insertelement <2 x double> undef, double [[TMP2]], i32 0 +; SSE-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP1]], i32 1 +; SSE-NEXT: [[R1:%.*]] = insertelement <2 x double> [[R0]], double [[TMP3]], i32 1 +; SSE-NEXT: ret <2 x double> [[R1]] +; +; SLM-LABEL: @buildvector_div_2f64( +; SLM-NEXT: [[A0:%.*]] = extractelement <2 x double> [[A:%.*]], i32 0 +; SLM-NEXT: [[A1:%.*]] = extractelement <2 x double> [[A]], i32 1 +; SLM-NEXT: [[B0:%.*]] = extractelement <2 x double> [[B:%.*]], i32 0 +; SLM-NEXT: [[B1:%.*]] = extractelement <2 x double> [[B]], i32 1 +; SLM-NEXT: [[C0:%.*]] = fdiv double [[A0]], [[B0]] +; SLM-NEXT: [[C1:%.*]] = fdiv double [[A1]], [[B1]] +; SLM-NEXT: [[R0:%.*]] = insertelement <2 x double> undef, double [[C0]], i32 0 +; SLM-NEXT: [[R1:%.*]] = insertelement <2 x double> [[R0]], double [[C1]], i32 1 +; SLM-NEXT: ret <2 x double> [[R1]] +; +; AVX-LABEL: @buildvector_div_2f64( +; AVX-NEXT: [[TMP1:%.*]] = fdiv <2 x double> [[A:%.*]], [[B:%.*]] +; AVX-NEXT: [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i32 0 +; AVX-NEXT: [[R0:%.*]] = insertelement <2 x double> undef, double [[TMP2]], i32 0 +; AVX-NEXT: [[TMP3:%.*]] = extractelement <2 x double> [[TMP1]], i32 1 +; AVX-NEXT: [[R1:%.*]] = insertelement <2 x double> [[R0]], double [[TMP3]], i32 1 +; AVX-NEXT: ret <2 x double> [[R1]] ; %a0 = extractelement <2 x double> %a, i32 0 %a1 = extractelement <2 x double> %a, i32 1 @@ -317,17 +337,48 @@ define <4 x double> @buildvector_mul_4f64(<4 x double> %a, <4 x double> %b) { } define <4 x double> @buildvector_div_4f64(<4 x double> %a, <4 x double> %b) { -; CHECK-LABEL: @buildvector_div_4f64( -; CHECK-NEXT: [[TMP1:%.*]] = fdiv <4 x double> [[A:%.*]], [[B:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x double> [[TMP1]], i32 0 -; CHECK-NEXT: [[R0:%.*]] = insertelement <4 x double> undef, double [[TMP2]], i32 0 -; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x double> [[TMP1]], i32 1 -; CHECK-NEXT: [[R1:%.*]] = insertelement <4 x double> [[R0]], double [[TMP3]], i32 1 -; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x double> [[TMP1]], i32 2 -; CHECK-NEXT: [[R2:%.*]] = insertelement <4 x double> [[R1]], double [[TMP4]], i32 2 -; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x double> [[TMP1]], i32 3 -; CHECK-NEXT: [[R3:%.*]] = insertelement <4 x double> [[R2]], double [[TMP5]], i32 3 -; CHECK-NEXT: ret <4 x double> [[R3]] +; SSE-LABEL: @buildvector_div_4f64( +; SSE-NEXT: [[TMP1:%.*]] = fdiv <4 x double> [[A:%.*]], [[B:%.*]] +; SSE-NEXT: [[TMP2:%.*]] = extractelement <4 x double> [[TMP1]], i32 0 +; SSE-NEXT: [[R0:%.*]] = insertelement <4 x double> undef, double [[TMP2]], i32 0 +; SSE-NEXT: [[TMP3:%.*]] = extractelement <4 x double> [[TMP1]], i32 1 +; SSE-NEXT: [[R1:%.*]] = insertelement <4 x double> [[R0]], double [[TMP3]], i32 1 +; SSE-NEXT: [[TMP4:%.*]] = extractelement <4 x double> [[TMP1]], i32 2 +; SSE-NEXT: [[R2:%.*]] = insertelement <4 x double> [[R1]], double [[TMP4]], i32 2 +; SSE-NEXT: [[TMP5:%.*]] = extractelement <4 x double> [[TMP1]], i32 3 +; SSE-NEXT: [[R3:%.*]] = insertelement <4 x double> [[R2]], double [[TMP5]], i32 3 +; SSE-NEXT: ret <4 x double> [[R3]] +; +; SLM-LABEL: @buildvector_div_4f64( +; SLM-NEXT: [[A0:%.*]] = extractelement <4 x double> [[A:%.*]], i32 0 +; SLM-NEXT: [[A1:%.*]] = extractelement <4 x double> [[A]], i32 1 +; SLM-NEXT: [[A2:%.*]] = extractelement <4 x double> [[A]], i32 2 +; SLM-NEXT: [[A3:%.*]] = extractelement <4 x double> [[A]], i32 3 +; SLM-NEXT: [[B0:%.*]] = extractelement <4 x double> [[B:%.*]], i32 0 +; SLM-NEXT: [[B1:%.*]] = extractelement <4 x double> [[B]], i32 1 +; SLM-NEXT: [[B2:%.*]] = extractelement <4 x double> [[B]], i32 2 +; SLM-NEXT: [[B3:%.*]] = extractelement <4 x double> [[B]], i32 3 +; SLM-NEXT: [[C0:%.*]] = fdiv double [[A0]], [[B0]] +; SLM-NEXT: [[C1:%.*]] = fdiv double [[A1]], [[B1]] +; SLM-NEXT: [[C2:%.*]] = fdiv double [[A2]], [[B2]] +; SLM-NEXT: [[C3:%.*]] = fdiv double [[A3]], [[B3]] +; SLM-NEXT: [[R0:%.*]] = insertelement <4 x double> undef, double [[C0]], i32 0 +; SLM-NEXT: [[R1:%.*]] = insertelement <4 x double> [[R0]], double [[C1]], i32 1 +; SLM-NEXT: [[R2:%.*]] = insertelement <4 x double> [[R1]], double [[C2]], i32 2 +; SLM-NEXT: [[R3:%.*]] = insertelement <4 x double> [[R2]], double [[C3]], i32 3 +; SLM-NEXT: ret <4 x double> [[R3]] +; +; AVX-LABEL: @buildvector_div_4f64( +; AVX-NEXT: [[TMP1:%.*]] = fdiv <4 x double> [[A:%.*]], [[B:%.*]] +; AVX-NEXT: [[TMP2:%.*]] = extractelement <4 x double> [[TMP1]], i32 0 +; AVX-NEXT: [[R0:%.*]] = insertelement <4 x double> undef, double [[TMP2]], i32 0 +; AVX-NEXT: [[TMP3:%.*]] = extractelement <4 x double> [[TMP1]], i32 1 +; AVX-NEXT: [[R1:%.*]] = insertelement <4 x double> [[R0]], double [[TMP3]], i32 1 +; AVX-NEXT: [[TMP4:%.*]] = extractelement <4 x double> [[TMP1]], i32 2 +; AVX-NEXT: [[R2:%.*]] = insertelement <4 x double> [[R1]], double [[TMP4]], i32 2 +; AVX-NEXT: [[TMP5:%.*]] = extractelement <4 x double> [[TMP1]], i32 3 +; AVX-NEXT: [[R3:%.*]] = insertelement <4 x double> [[R2]], double [[TMP5]], i32 3 +; AVX-NEXT: ret <4 x double> [[R3]] ; %a0 = extractelement <4 x double> %a, i32 0 %a1 = extractelement <4 x double> %a, i32 1 @@ -745,25 +796,80 @@ define <8 x double> @buildvector_mul_8f64(<8 x double> %a, <8 x double> %b) { } define <8 x double> @buildvector_div_8f64(<8 x double> %a, <8 x double> %b) { -; CHECK-LABEL: @buildvector_div_8f64( -; CHECK-NEXT: [[TMP1:%.*]] = fdiv <8 x double> [[A:%.*]], [[B:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x double> [[TMP1]], i32 0 -; CHECK-NEXT: [[R0:%.*]] = insertelement <8 x double> undef, double [[TMP2]], i32 0 -; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x double> [[TMP1]], i32 1 -; CHECK-NEXT: [[R1:%.*]] = insertelement <8 x double> [[R0]], double [[TMP3]], i32 1 -; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x double> [[TMP1]], i32 2 -; CHECK-NEXT: [[R2:%.*]] = insertelement <8 x double> [[R1]], double [[TMP4]], i32 2 -; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x double> [[TMP1]], i32 3 -; CHECK-NEXT: [[R3:%.*]] = insertelement <8 x double> [[R2]], double [[TMP5]], i32 3 -; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x double> [[TMP1]], i32 4 -; CHECK-NEXT: [[R4:%.*]] = insertelement <8 x double> [[R3]], double [[TMP6]], i32 4 -; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x double> [[TMP1]], i32 5 -; CHECK-NEXT: [[R5:%.*]] = insertelement <8 x double> [[R4]], double [[TMP7]], i32 5 -; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x double> [[TMP1]], i32 6 -; CHECK-NEXT: [[R6:%.*]] = insertelement <8 x double> [[R5]], double [[TMP8]], i32 6 -; CHECK-NEXT: [[TMP9:%.*]] = extractelement <8 x double> [[TMP1]], i32 7 -; CHECK-NEXT: [[R7:%.*]] = insertelement <8 x double> [[R6]], double [[TMP9]], i32 7 -; CHECK-NEXT: ret <8 x double> [[R7]] +; SSE-LABEL: @buildvector_div_8f64( +; SSE-NEXT: [[TMP1:%.*]] = fdiv <8 x double> [[A:%.*]], [[B:%.*]] +; SSE-NEXT: [[TMP2:%.*]] = extractelement <8 x double> [[TMP1]], i32 0 +; SSE-NEXT: [[R0:%.*]] = insertelement <8 x double> undef, double [[TMP2]], i32 0 +; SSE-NEXT: [[TMP3:%.*]] = extractelement <8 x double> [[TMP1]], i32 1 +; SSE-NEXT: [[R1:%.*]] = insertelement <8 x double> [[R0]], double [[TMP3]], i32 1 +; SSE-NEXT: [[TMP4:%.*]] = extractelement <8 x double> [[TMP1]], i32 2 +; SSE-NEXT: [[R2:%.*]] = insertelement <8 x double> [[R1]], double [[TMP4]], i32 2 +; SSE-NEXT: [[TMP5:%.*]] = extractelement <8 x double> [[TMP1]], i32 3 +; SSE-NEXT: [[R3:%.*]] = insertelement <8 x double> [[R2]], double [[TMP5]], i32 3 +; SSE-NEXT: [[TMP6:%.*]] = extractelement <8 x double> [[TMP1]], i32 4 +; SSE-NEXT: [[R4:%.*]] = insertelement <8 x double> [[R3]], double [[TMP6]], i32 4 +; SSE-NEXT: [[TMP7:%.*]] = extractelement <8 x double> [[TMP1]], i32 5 +; SSE-NEXT: [[R5:%.*]] = insertelement <8 x double> [[R4]], double [[TMP7]], i32 5 +; SSE-NEXT: [[TMP8:%.*]] = extractelement <8 x double> [[TMP1]], i32 6 +; SSE-NEXT: [[R6:%.*]] = insertelement <8 x double> [[R5]], double [[TMP8]], i32 6 +; SSE-NEXT: [[TMP9:%.*]] = extractelement <8 x double> [[TMP1]], i32 7 +; SSE-NEXT: [[R7:%.*]] = insertelement <8 x double> [[R6]], double [[TMP9]], i32 7 +; SSE-NEXT: ret <8 x double> [[R7]] +; +; SLM-LABEL: @buildvector_div_8f64( +; SLM-NEXT: [[A0:%.*]] = extractelement <8 x double> [[A:%.*]], i32 0 +; SLM-NEXT: [[A1:%.*]] = extractelement <8 x double> [[A]], i32 1 +; SLM-NEXT: [[A2:%.*]] = extractelement <8 x double> [[A]], i32 2 +; SLM-NEXT: [[A3:%.*]] = extractelement <8 x double> [[A]], i32 3 +; SLM-NEXT: [[A4:%.*]] = extractelement <8 x double> [[A]], i32 4 +; SLM-NEXT: [[A5:%.*]] = extractelement <8 x double> [[A]], i32 5 +; SLM-NEXT: [[A6:%.*]] = extractelement <8 x double> [[A]], i32 6 +; SLM-NEXT: [[A7:%.*]] = extractelement <8 x double> [[A]], i32 7 +; SLM-NEXT: [[B0:%.*]] = extractelement <8 x double> [[B:%.*]], i32 0 +; SLM-NEXT: [[B1:%.*]] = extractelement <8 x double> [[B]], i32 1 +; SLM-NEXT: [[B2:%.*]] = extractelement <8 x double> [[B]], i32 2 +; SLM-NEXT: [[B3:%.*]] = extractelement <8 x double> [[B]], i32 3 +; SLM-NEXT: [[B4:%.*]] = extractelement <8 x double> [[B]], i32 4 +; SLM-NEXT: [[B5:%.*]] = extractelement <8 x double> [[B]], i32 5 +; SLM-NEXT: [[B6:%.*]] = extractelement <8 x double> [[B]], i32 6 +; SLM-NEXT: [[B7:%.*]] = extractelement <8 x double> [[B]], i32 7 +; SLM-NEXT: [[C0:%.*]] = fdiv double [[A0]], [[B0]] +; SLM-NEXT: [[C1:%.*]] = fdiv double [[A1]], [[B1]] +; SLM-NEXT: [[C2:%.*]] = fdiv double [[A2]], [[B2]] +; SLM-NEXT: [[C3:%.*]] = fdiv double [[A3]], [[B3]] +; SLM-NEXT: [[C4:%.*]] = fdiv double [[A4]], [[B4]] +; SLM-NEXT: [[C5:%.*]] = fdiv double [[A5]], [[B5]] +; SLM-NEXT: [[C6:%.*]] = fdiv double [[A6]], [[B6]] +; SLM-NEXT: [[C7:%.*]] = fdiv double [[A7]], [[B7]] +; SLM-NEXT: [[R0:%.*]] = insertelement <8 x double> undef, double [[C0]], i32 0 +; SLM-NEXT: [[R1:%.*]] = insertelement <8 x double> [[R0]], double [[C1]], i32 1 +; SLM-NEXT: [[R2:%.*]] = insertelement <8 x double> [[R1]], double [[C2]], i32 2 +; SLM-NEXT: [[R3:%.*]] = insertelement <8 x double> [[R2]], double [[C3]], i32 3 +; SLM-NEXT: [[R4:%.*]] = insertelement <8 x double> [[R3]], double [[C4]], i32 4 +; SLM-NEXT: [[R5:%.*]] = insertelement <8 x double> [[R4]], double [[C5]], i32 5 +; SLM-NEXT: [[R6:%.*]] = insertelement <8 x double> [[R5]], double [[C6]], i32 6 +; SLM-NEXT: [[R7:%.*]] = insertelement <8 x double> [[R6]], double [[C7]], i32 7 +; SLM-NEXT: ret <8 x double> [[R7]] +; +; AVX-LABEL: @buildvector_div_8f64( +; AVX-NEXT: [[TMP1:%.*]] = fdiv <8 x double> [[A:%.*]], [[B:%.*]] +; AVX-NEXT: [[TMP2:%.*]] = extractelement <8 x double> [[TMP1]], i32 0 +; AVX-NEXT: [[R0:%.*]] = insertelement <8 x double> undef, double [[TMP2]], i32 0 +; AVX-NEXT: [[TMP3:%.*]] = extractelement <8 x double> [[TMP1]], i32 1 +; AVX-NEXT: [[R1:%.*]] = insertelement <8 x double> [[R0]], double [[TMP3]], i32 1 +; AVX-NEXT: [[TMP4:%.*]] = extractelement <8 x double> [[TMP1]], i32 2 +; AVX-NEXT: [[R2:%.*]] = insertelement <8 x double> [[R1]], double [[TMP4]], i32 2 +; AVX-NEXT: [[TMP5:%.*]] = extractelement <8 x double> [[TMP1]], i32 3 +; AVX-NEXT: [[R3:%.*]] = insertelement <8 x double> [[R2]], double [[TMP5]], i32 3 +; AVX-NEXT: [[TMP6:%.*]] = extractelement <8 x double> [[TMP1]], i32 4 +; AVX-NEXT: [[R4:%.*]] = insertelement <8 x double> [[R3]], double [[TMP6]], i32 4 +; AVX-NEXT: [[TMP7:%.*]] = extractelement <8 x double> [[TMP1]], i32 5 +; AVX-NEXT: [[R5:%.*]] = insertelement <8 x double> [[R4]], double [[TMP7]], i32 5 +; AVX-NEXT: [[TMP8:%.*]] = extractelement <8 x double> [[TMP1]], i32 6 +; AVX-NEXT: [[R6:%.*]] = insertelement <8 x double> [[R5]], double [[TMP8]], i32 6 +; AVX-NEXT: [[TMP9:%.*]] = extractelement <8 x double> [[TMP1]], i32 7 +; AVX-NEXT: [[R7:%.*]] = insertelement <8 x double> [[R6]], double [[TMP9]], i32 7 +; AVX-NEXT: ret <8 x double> [[R7]] ; %a0 = extractelement <8 x double> %a, i32 0 %a1 = extractelement <8 x double> %a, i32 1 diff --git a/test/Transforms/SLPVectorizer/X86/arith-mul.ll b/test/Transforms/SLPVectorizer/X86/arith-mul.ll index 95875d7f01fd..4763a9a2bf12 100644 --- a/test/Transforms/SLPVectorizer/X86/arith-mul.ll +++ b/test/Transforms/SLPVectorizer/X86/arith-mul.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -mtriple=x86_64-unknown -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE +; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=slm -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SLM ; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1 ; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2 ; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=knl -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512 --check-prefix=AVX512F @@ -54,6 +55,41 @@ define void @mul_v8i64() { ; SSE-NEXT: store i64 [[R7]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @c64, i32 0, i64 7), align 8 ; SSE-NEXT: ret void ; +; SLM-LABEL: @mul_v8i64( +; SLM-NEXT: [[A0:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @a64, i32 0, i64 0), align 8 +; SLM-NEXT: [[A1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @a64, i32 0, i64 1), align 8 +; SLM-NEXT: [[A2:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @a64, i32 0, i64 2), align 8 +; SLM-NEXT: [[A3:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @a64, i32 0, i64 3), align 8 +; SLM-NEXT: [[A4:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @a64, i32 0, i64 4), align 8 +; SLM-NEXT: [[A5:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @a64, i32 0, i64 5), align 8 +; SLM-NEXT: [[A6:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @a64, i32 0, i64 6), align 8 +; SLM-NEXT: [[A7:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @a64, i32 0, i64 7), align 8 +; SLM-NEXT: [[B0:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @b64, i32 0, i64 0), align 8 +; SLM-NEXT: [[B1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @b64, i32 0, i64 1), align 8 +; SLM-NEXT: [[B2:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @b64, i32 0, i64 2), align 8 +; SLM-NEXT: [[B3:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @b64, i32 0, i64 3), align 8 +; SLM-NEXT: [[B4:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @b64, i32 0, i64 4), align 8 +; SLM-NEXT: [[B5:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @b64, i32 0, i64 5), align 8 +; SLM-NEXT: [[B6:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @b64, i32 0, i64 6), align 8 +; SLM-NEXT: [[B7:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @b64, i32 0, i64 7), align 8 +; SLM-NEXT: [[R0:%.*]] = mul i64 [[A0]], [[B0]] +; SLM-NEXT: [[R1:%.*]] = mul i64 [[A1]], [[B1]] +; SLM-NEXT: [[R2:%.*]] = mul i64 [[A2]], [[B2]] +; SLM-NEXT: [[R3:%.*]] = mul i64 [[A3]], [[B3]] +; SLM-NEXT: [[R4:%.*]] = mul i64 [[A4]], [[B4]] +; SLM-NEXT: [[R5:%.*]] = mul i64 [[A5]], [[B5]] +; SLM-NEXT: [[R6:%.*]] = mul i64 [[A6]], [[B6]] +; SLM-NEXT: [[R7:%.*]] = mul i64 [[A7]], [[B7]] +; SLM-NEXT: store i64 [[R0]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @c64, i32 0, i64 0), align 8 +; SLM-NEXT: store i64 [[R1]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @c64, i32 0, i64 1), align 8 +; SLM-NEXT: store i64 [[R2]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @c64, i32 0, i64 2), align 8 +; SLM-NEXT: store i64 [[R3]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @c64, i32 0, i64 3), align 8 +; SLM-NEXT: store i64 [[R4]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @c64, i32 0, i64 4), align 8 +; SLM-NEXT: store i64 [[R5]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @c64, i32 0, i64 5), align 8 +; SLM-NEXT: store i64 [[R6]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @c64, i32 0, i64 6), align 8 +; SLM-NEXT: store i64 [[R7]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @c64, i32 0, i64 7), align 8 +; SLM-NEXT: ret void +; ; AVX1-LABEL: @mul_v8i64( ; AVX1-NEXT: [[A0:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @a64, i32 0, i64 0), align 8 ; AVX1-NEXT: [[A1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @a64, i32 0, i64 1), align 8 @@ -162,6 +198,25 @@ define void @mul_v16i32() { ; SSE-NEXT: store <4 x i32> [[TMP12]], <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @c32, i32 0, i64 12) to <4 x i32>*), align 4 ; SSE-NEXT: ret void ; +; SLM-LABEL: @mul_v16i32( +; SLM-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([16 x i32]* @a32 to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @a32, i32 0, i64 4) to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @a32, i32 0, i64 8) to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP4:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @a32, i32 0, i64 12) to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP5:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([16 x i32]* @b32 to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP6:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @b32, i32 0, i64 4) to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP7:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @b32, i32 0, i64 8) to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP8:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @b32, i32 0, i64 12) to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP9:%.*]] = mul <4 x i32> [[TMP1]], [[TMP5]] +; SLM-NEXT: [[TMP10:%.*]] = mul <4 x i32> [[TMP2]], [[TMP6]] +; SLM-NEXT: [[TMP11:%.*]] = mul <4 x i32> [[TMP3]], [[TMP7]] +; SLM-NEXT: [[TMP12:%.*]] = mul <4 x i32> [[TMP4]], [[TMP8]] +; SLM-NEXT: store <4 x i32> [[TMP9]], <4 x i32>* bitcast ([16 x i32]* @c32 to <4 x i32>*), align 4 +; SLM-NEXT: store <4 x i32> [[TMP10]], <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @c32, i32 0, i64 4) to <4 x i32>*), align 4 +; SLM-NEXT: store <4 x i32> [[TMP11]], <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @c32, i32 0, i64 8) to <4 x i32>*), align 4 +; SLM-NEXT: store <4 x i32> [[TMP12]], <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @c32, i32 0, i64 12) to <4 x i32>*), align 4 +; SLM-NEXT: ret void +; ; AVX-LABEL: @mul_v16i32( ; AVX-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([16 x i32]* @a32 to <8 x i32>*), align 4 ; AVX-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @a32, i32 0, i64 8) to <8 x i32>*), align 4 @@ -267,6 +322,25 @@ define void @mul_v32i16() { ; SSE-NEXT: store <8 x i16> [[TMP12]], <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @c16, i32 0, i64 24) to <8 x i16>*), align 2 ; SSE-NEXT: ret void ; +; SLM-LABEL: @mul_v32i16( +; SLM-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([32 x i16]* @a16 to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @a16, i32 0, i64 8) to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP3:%.*]] = load <8 x i16>, <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @a16, i32 0, i64 16) to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP4:%.*]] = load <8 x i16>, <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @a16, i32 0, i64 24) to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP5:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([32 x i16]* @b16 to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP6:%.*]] = load <8 x i16>, <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16, i32 0, i64 8) to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP7:%.*]] = load <8 x i16>, <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16, i32 0, i64 16) to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP8:%.*]] = load <8 x i16>, <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16, i32 0, i64 24) to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP9:%.*]] = mul <8 x i16> [[TMP1]], [[TMP5]] +; SLM-NEXT: [[TMP10:%.*]] = mul <8 x i16> [[TMP2]], [[TMP6]] +; SLM-NEXT: [[TMP11:%.*]] = mul <8 x i16> [[TMP3]], [[TMP7]] +; SLM-NEXT: [[TMP12:%.*]] = mul <8 x i16> [[TMP4]], [[TMP8]] +; SLM-NEXT: store <8 x i16> [[TMP9]], <8 x i16>* bitcast ([32 x i16]* @c16 to <8 x i16>*), align 2 +; SLM-NEXT: store <8 x i16> [[TMP10]], <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @c16, i32 0, i64 8) to <8 x i16>*), align 2 +; SLM-NEXT: store <8 x i16> [[TMP11]], <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @c16, i32 0, i64 16) to <8 x i16>*), align 2 +; SLM-NEXT: store <8 x i16> [[TMP12]], <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @c16, i32 0, i64 24) to <8 x i16>*), align 2 +; SLM-NEXT: ret void +; ; AVX-LABEL: @mul_v32i16( ; AVX-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([32 x i16]* @a16 to <16 x i16>*), align 2 ; AVX-NEXT: [[TMP2:%.*]] = load <16 x i16>, <16 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @a16, i32 0, i64 16) to <16 x i16>*), align 2 diff --git a/test/Transforms/SLPVectorizer/X86/arith-sub.ll b/test/Transforms/SLPVectorizer/X86/arith-sub.ll index 85838369e226..2bbaaca02d88 100644 --- a/test/Transforms/SLPVectorizer/X86/arith-sub.ll +++ b/test/Transforms/SLPVectorizer/X86/arith-sub.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -mtriple=x86_64-unknown -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE +; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=slm -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SLM ; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX1 ; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX2 ; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=knl -basicaa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512 --check-prefix=AVX512F @@ -38,6 +39,25 @@ define void @sub_v8i64() { ; SSE-NEXT: store <2 x i64> [[TMP12]], <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @c64, i32 0, i64 6) to <2 x i64>*), align 8 ; SSE-NEXT: ret void ; +; SLM-LABEL: @sub_v8i64( +; SLM-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([8 x i64]* @a64 to <2 x i64>*), align 8 +; SLM-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @a64, i32 0, i64 2) to <2 x i64>*), align 8 +; SLM-NEXT: [[TMP3:%.*]] = load <2 x i64>, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @a64, i32 0, i64 4) to <2 x i64>*), align 8 +; SLM-NEXT: [[TMP4:%.*]] = load <2 x i64>, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @a64, i32 0, i64 6) to <2 x i64>*), align 8 +; SLM-NEXT: [[TMP5:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([8 x i64]* @b64 to <2 x i64>*), align 8 +; SLM-NEXT: [[TMP6:%.*]] = load <2 x i64>, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @b64, i32 0, i64 2) to <2 x i64>*), align 8 +; SLM-NEXT: [[TMP7:%.*]] = load <2 x i64>, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @b64, i32 0, i64 4) to <2 x i64>*), align 8 +; SLM-NEXT: [[TMP8:%.*]] = load <2 x i64>, <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @b64, i32 0, i64 6) to <2 x i64>*), align 8 +; SLM-NEXT: [[TMP9:%.*]] = sub <2 x i64> [[TMP1]], [[TMP5]] +; SLM-NEXT: [[TMP10:%.*]] = sub <2 x i64> [[TMP2]], [[TMP6]] +; SLM-NEXT: [[TMP11:%.*]] = sub <2 x i64> [[TMP3]], [[TMP7]] +; SLM-NEXT: [[TMP12:%.*]] = sub <2 x i64> [[TMP4]], [[TMP8]] +; SLM-NEXT: store <2 x i64> [[TMP9]], <2 x i64>* bitcast ([8 x i64]* @c64 to <2 x i64>*), align 8 +; SLM-NEXT: store <2 x i64> [[TMP10]], <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @c64, i32 0, i64 2) to <2 x i64>*), align 8 +; SLM-NEXT: store <2 x i64> [[TMP11]], <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @c64, i32 0, i64 4) to <2 x i64>*), align 8 +; SLM-NEXT: store <2 x i64> [[TMP12]], <2 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @c64, i32 0, i64 6) to <2 x i64>*), align 8 +; SLM-NEXT: ret void +; ; AVX-LABEL: @sub_v8i64( ; AVX-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([8 x i64]* @a64 to <4 x i64>*), align 8 ; AVX-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @a64, i32 0, i64 4) to <4 x i64>*), align 8 @@ -111,6 +131,25 @@ define void @sub_v16i32() { ; SSE-NEXT: store <4 x i32> [[TMP12]], <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @c32, i32 0, i64 12) to <4 x i32>*), align 4 ; SSE-NEXT: ret void ; +; SLM-LABEL: @sub_v16i32( +; SLM-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([16 x i32]* @a32 to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @a32, i32 0, i64 4) to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @a32, i32 0, i64 8) to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP4:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @a32, i32 0, i64 12) to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP5:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([16 x i32]* @b32 to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP6:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @b32, i32 0, i64 4) to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP7:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @b32, i32 0, i64 8) to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP8:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @b32, i32 0, i64 12) to <4 x i32>*), align 4 +; SLM-NEXT: [[TMP9:%.*]] = sub <4 x i32> [[TMP1]], [[TMP5]] +; SLM-NEXT: [[TMP10:%.*]] = sub <4 x i32> [[TMP2]], [[TMP6]] +; SLM-NEXT: [[TMP11:%.*]] = sub <4 x i32> [[TMP3]], [[TMP7]] +; SLM-NEXT: [[TMP12:%.*]] = sub <4 x i32> [[TMP4]], [[TMP8]] +; SLM-NEXT: store <4 x i32> [[TMP9]], <4 x i32>* bitcast ([16 x i32]* @c32 to <4 x i32>*), align 4 +; SLM-NEXT: store <4 x i32> [[TMP10]], <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @c32, i32 0, i64 4) to <4 x i32>*), align 4 +; SLM-NEXT: store <4 x i32> [[TMP11]], <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @c32, i32 0, i64 8) to <4 x i32>*), align 4 +; SLM-NEXT: store <4 x i32> [[TMP12]], <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @c32, i32 0, i64 12) to <4 x i32>*), align 4 +; SLM-NEXT: ret void +; ; AVX-LABEL: @sub_v16i32( ; AVX-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([16 x i32]* @a32 to <8 x i32>*), align 4 ; AVX-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @a32, i32 0, i64 8) to <8 x i32>*), align 4 @@ -216,6 +255,25 @@ define void @sub_v32i16() { ; SSE-NEXT: store <8 x i16> [[TMP12]], <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @c16, i32 0, i64 24) to <8 x i16>*), align 2 ; SSE-NEXT: ret void ; +; SLM-LABEL: @sub_v32i16( +; SLM-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([32 x i16]* @a16 to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @a16, i32 0, i64 8) to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP3:%.*]] = load <8 x i16>, <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @a16, i32 0, i64 16) to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP4:%.*]] = load <8 x i16>, <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @a16, i32 0, i64 24) to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP5:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([32 x i16]* @b16 to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP6:%.*]] = load <8 x i16>, <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16, i32 0, i64 8) to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP7:%.*]] = load <8 x i16>, <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16, i32 0, i64 16) to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP8:%.*]] = load <8 x i16>, <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @b16, i32 0, i64 24) to <8 x i16>*), align 2 +; SLM-NEXT: [[TMP9:%.*]] = sub <8 x i16> [[TMP1]], [[TMP5]] +; SLM-NEXT: [[TMP10:%.*]] = sub <8 x i16> [[TMP2]], [[TMP6]] +; SLM-NEXT: [[TMP11:%.*]] = sub <8 x i16> [[TMP3]], [[TMP7]] +; SLM-NEXT: [[TMP12:%.*]] = sub <8 x i16> [[TMP4]], [[TMP8]] +; SLM-NEXT: store <8 x i16> [[TMP9]], <8 x i16>* bitcast ([32 x i16]* @c16 to <8 x i16>*), align 2 +; SLM-NEXT: store <8 x i16> [[TMP10]], <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @c16, i32 0, i64 8) to <8 x i16>*), align 2 +; SLM-NEXT: store <8 x i16> [[TMP11]], <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @c16, i32 0, i64 16) to <8 x i16>*), align 2 +; SLM-NEXT: store <8 x i16> [[TMP12]], <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @c16, i32 0, i64 24) to <8 x i16>*), align 2 +; SLM-NEXT: ret void +; ; AVX-LABEL: @sub_v32i16( ; AVX-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([32 x i16]* @a16 to <16 x i16>*), align 2 ; AVX-NEXT: [[TMP2:%.*]] = load <16 x i16>, <16 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @a16, i32 0, i64 16) to <16 x i16>*), align 2 diff --git a/test/Transforms/SafeStack/X86/debug-loc.ll b/test/Transforms/SafeStack/X86/debug-loc.ll index 88cda693b293..d6b217142bfe 100644 --- a/test/Transforms/SafeStack/X86/debug-loc.ll +++ b/test/Transforms/SafeStack/X86/debug-loc.ll @@ -37,10 +37,10 @@ entry: ; CHECK-DAG: ![[VAR_ARG]] = !DILocalVariable(name: "zzz" ; 100 aligned up to 8 -; CHECK-DAG: ![[EXPR_ARG]] = !DIExpression(DW_OP_minus, 104) +; CHECK-DAG: ![[EXPR_ARG]] = !DIExpression(DW_OP_constu, 104, DW_OP_minus ; CHECK-DAG: ![[VAR_LOCAL]] = !DILocalVariable(name: "xxx" -; CHECK-DAG: ![[EXPR_LOCAL]] = !DIExpression(DW_OP_minus, 208) +; CHECK-DAG: ![[EXPR_LOCAL]] = !DIExpression(DW_OP_constu, 208, DW_OP_minus ; Function Attrs: nounwind readnone declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 diff --git a/test/Transforms/SafeStack/X86/debug-loc2.ll b/test/Transforms/SafeStack/X86/debug-loc2.ll index 8059a722fd45..731516c3c65e 100644 --- a/test/Transforms/SafeStack/X86/debug-loc2.ll +++ b/test/Transforms/SafeStack/X86/debug-loc2.ll @@ -84,8 +84,8 @@ attributes #4 = { nounwind } !13 = !DILocation(line: 5, column: 3, scope: !6) !14 = !DILocation(line: 6, column: 3, scope: !6) -; CHECK-DAG: ![[X1_EXPR]] = !DIExpression(DW_OP_deref, DW_OP_minus, 4) -; CHECK-DAG: ![[X2_EXPR]] = !DIExpression(DW_OP_deref, DW_OP_minus, 8) +; CHECK-DAG: ![[X1_EXPR]] = !DIExpression(DW_OP_deref, DW_OP_constu, 4, DW_OP_minus) +; CHECK-DAG: ![[X2_EXPR]] = !DIExpression(DW_OP_deref, DW_OP_constu, 8, DW_OP_minus) !15 = !DIExpression(DW_OP_deref) !16 = !DILocation(line: 5, column: 7, scope: !6) !17 = !DILocation(line: 8, column: 3, scope: !6) @@ -95,4 +95,4 @@ attributes #4 = { nounwind } !21 = !DILocation(line: 10, column: 1, scope: !22) !22 = !DILexicalBlockFile(scope: !6, file: !1, discriminator: 1) !23 = !DIExpression() -!24 = !DIExpression(DW_OP_minus, 42) +!24 = !DIExpression(DW_OP_constu, 42, DW_OP_minus) diff --git a/test/Transforms/Util/PredicateInfo/pr33456.ll b/test/Transforms/Util/PredicateInfo/pr33456.ll new file mode 100644 index 000000000000..f1cc83a071b9 --- /dev/null +++ b/test/Transforms/Util/PredicateInfo/pr33456.ll @@ -0,0 +1,68 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -print-predicateinfo -analyze < %s 2>&1 | FileCheck %s +; Don't insert predicate info for conditions with a single target. +@a = global i32 1, align 4 +@d = common global i32 0, align 4 +@c = common global i32 0, align 4 +@b = common global i32 0, align 4 +@e = common global i32 0, align 4 + +define i32 @main() { +; CHECK-LABEL: @main( +; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @d, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0 +; CHECK-NEXT: br i1 [[TMP2]], label [[TMP3:%.*]], label [[TMP13:%.*]] +; CHECK: [[TMP4:%.*]] = load i32, i32* @a, align 4 +; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* @c, align 4 +; CHECK-NEXT: [[TMP6:%.*]] = icmp slt i32 [[TMP5]], 1 +; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP9:%.*]] +; CHECK: [[TMP8:%.*]] = icmp eq i32 [[TMP4]], 0 +; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9]], label [[TMP9]] +; CHECK: [[DOT0:%.*]] = phi i32 [ [[TMP4]], [[TMP7]] ], [ [[TMP4]], [[TMP7]] ], [ [[DOT1:%.*]], [[TMP13]] ], [ [[TMP4]], [[TMP3]] ] +; CHECK-NEXT: [[TMP10:%.*]] = load i32, i32* @b, align 4 +; CHECK-NEXT: [[TMP11:%.*]] = sdiv i32 [[TMP10]], [[DOT0]] +; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[TMP11]], 0 +; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13]], label [[TMP13]] +; CHECK: [[DOT1]] = phi i32 [ [[DOT0]], [[TMP9]] ], [ [[DOT0]], [[TMP9]] ], [ undef, [[TMP0:%.*]] ] +; CHECK-NEXT: [[TMP14:%.*]] = load i32, i32* @e, align 4 +; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i32 [[TMP14]], 0 +; CHECK-NEXT: br i1 [[TMP15]], label [[TMP16:%.*]], label [[TMP9]] +; CHECK: ret i32 0 +; + %1 = load i32, i32* @d, align 4 + %2 = icmp eq i32 %1, 0 + br i1 %2, label %3, label %13 + +; <label>:3: ; preds = %0 + %4 = load i32, i32* @a, align 4 + %5 = load i32, i32* @c, align 4 + %6 = icmp slt i32 %5, 1 + br i1 %6, label %7, label %9 + +; <label>:7: ; preds = %3 + %8 = icmp eq i32 %4, 0 + br i1 %8, label %9, label %9 + +; <label>:9: ; preds = %13, %7, %7, %3 + %.0 = phi i32 [ %4, %7 ], [ %4, %7 ], [ %.1, %13 ], [ %4, %3 ] + %10 = load i32, i32* @b, align 4 + %11 = sdiv i32 %10, %.0 + %12 = icmp eq i32 %11, 0 + br i1 %12, label %13, label %13 + +; <label>:13: ; preds = %9, %9, %0 + %.1 = phi i32 [ %.0, %9 ], [ %.0, %9 ], [ undef, %0 ] + %14 = load i32, i32* @e, align 4 + %15 = icmp eq i32 %14, 0 + br i1 %15, label %16, label %9 + +; <label>:16: ; preds = %13 + ret i32 0 +} + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) + diff --git a/test/Transforms/Util/PredicateInfo/pr33457.ll b/test/Transforms/Util/PredicateInfo/pr33457.ll new file mode 100644 index 000000000000..b975ade9321d --- /dev/null +++ b/test/Transforms/Util/PredicateInfo/pr33457.ll @@ -0,0 +1,93 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -print-predicateinfo -analyze < %s 2>&1 | FileCheck %s +; Don't insert predicate info for conditions with a single target. +@a = global i32 6, align 4 +@c = global i32 -1, align 4 +@e = common global i32 0, align 4 +@.str = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1 +@d = common global i32 0, align 4 +@b = common global [6 x i32] zeroinitializer, align 16 + +; Function Attrs: nounwind ssp uwtable +define i32 @main() { +; CHECK-LABEL: @main( +; CHECK-NEXT: store i32 6, i32* @e, align 4 +; CHECK-NEXT: br label [[TMP1:%.*]] +; CHECK: [[TMP2:%.*]] = load i32, i32* @d, align 4 +; CHECK-NEXT: [[TMP3:%.*]] = sext i32 [[TMP2]] to i64 +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds [6 x i32], [6 x i32]* @b, i64 0, i64 [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 +; CHECK-NEXT: [[TMP6:%.*]] = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 [[TMP5]]) +; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* @a, align 4 +; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP7]], 0 +; CHECK-NEXT: br i1 [[TMP8]], label %thread-pre-split, label [[TMP9:%.*]] +; CHECK: [[TMP10:%.*]] = load i32, i32* @e, align 4 +; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 [[TMP10]], 0 +; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP12]] +; CHECK: thread-pre-split: +; CHECK-NEXT: [[DOTPR:%.*]] = load i32, i32* @e, align 4 +; CHECK-NEXT: br label [[TMP12]] +; CHECK: [[TMP13:%.*]] = phi i32 [ [[DOTPR]], %thread-pre-split ], [ [[TMP10]], [[TMP9]] ], [ [[TMP10]], [[TMP9]] ] +; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 +; CHECK-NEXT: br i1 [[TMP14]], label [[TMP15:%.*]], label [[TMP15]] +; CHECK: br i1 [[TMP14]], label [[TMP16:%.*]], label [[TMP17:%.*]] +; CHECK: br label [[TMP17]] +; CHECK: [[DOT0:%.*]] = phi i32 [ 1, [[TMP16]] ], [ -1, [[TMP15]] ] +; CHECK-NEXT: [[TMP18:%.*]] = and i32 [[DOT0]], 8693 +; CHECK-NEXT: [[TMP19:%.*]] = load i32, i32* @c, align 4 +; CHECK-NEXT: [[TMP20:%.*]] = xor i32 [[TMP18]], [[TMP19]] +; CHECK-NEXT: [[TMP21:%.*]] = xor i32 [[TMP20]], -1 +; CHECK-NEXT: store i32 [[TMP21]], i32* @d, align 4 +; CHECK-NEXT: [[TMP22:%.*]] = icmp slt i32 [[TMP20]], -2 +; CHECK-NEXT: br i1 [[TMP22]], label [[TMP1]], label [[TMP23:%.*]] +; CHECK: ret i32 0 +; + store i32 6, i32* @e, align 4 + br label %1 + +; <label>:1: ; preds = %17, %0 + %2 = load i32, i32* @d, align 4 + %3 = sext i32 %2 to i64 + %4 = getelementptr inbounds [6 x i32], [6 x i32]* @b, i64 0, i64 %3 + %5 = load i32, i32* %4, align 4 + %6 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %5) #2 + %7 = load i32, i32* @a, align 4 + %8 = icmp eq i32 %7, 0 + br i1 %8, label %thread-pre-split, label %9 + +; <label>:9: ; preds = %1 + %10 = load i32, i32* @e, align 4 + %11 = icmp eq i32 %10, 0 + br i1 %11, label %12, label %12 + +thread-pre-split: ; preds = %1 + %.pr = load i32, i32* @e, align 4 + br label %12 + +; <label>:12: ; preds = %thread-pre-split, %9, %9 + %13 = phi i32 [ %.pr, %thread-pre-split ], [ %10, %9 ], [ %10, %9 ] + %14 = icmp ne i32 %13, 0 + br i1 %14, label %15, label %15 + +; <label>:15: ; preds = %12, %12 + br i1 %14, label %16, label %17 + +; <label>:16: ; preds = %15 + br label %17 + +; <label>:17: ; preds = %16, %15 + %.0 = phi i32 [ 1, %16 ], [ -1, %15 ] + %18 = and i32 %.0, 8693 + %19 = load i32, i32* @c, align 4 + %20 = xor i32 %18, %19 + %21 = xor i32 %20, -1 + store i32 %21, i32* @d, align 4 + %22 = icmp slt i32 %20, -2 + br i1 %22, label %1, label %23 + +; <label>:23: ; preds = %17 + ret i32 0 +} + +declare i32 @printf(i8*, ...) + diff --git a/test/Verifier/element-wise-atomic-memory-intrinsics.ll b/test/Verifier/element-wise-atomic-memory-intrinsics.ll index 5690cd721407..470c861c5057 100644 --- a/test/Verifier/element-wise-atomic-memory-intrinsics.ll +++ b/test/Verifier/element-wise-atomic-memory-intrinsics.ll @@ -1,17 +1,25 @@ ; RUN: not opt -verify < %s 2>&1 | FileCheck %s -define void @test_memcpy(i8* %P, i8* %Q) { +define void @test_memcpy(i8* %P, i8* %Q, i32 %A, i32 %E) { + ; CHECK: element size of the element-wise unordered atomic memory intrinsic must be a constant int + call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* align 4 %Q, i32 1, i32 %E) ; CHECK: element size of the element-wise atomic memory intrinsic must be a power of 2 - call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 2 %P, i8* align 2 %Q, i64 4, i32 3) + call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* align 4 %Q, i32 1, i32 3) + ; CHECK: constant length must be a multiple of the element size in the element-wise atomic memory intrinsic + call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* align 4 %Q, i32 7, i32 4) + + ; CHECK: incorrect alignment of the destination argument + call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* %P, i8* align 4 %Q, i32 1, i32 1) ; CHECK: incorrect alignment of the destination argument - call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 2 %P, i8* align 4 %Q, i64 4, i32 4) + call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 1 %P, i8* align 4 %Q, i32 4, i32 4) ; CHECK: incorrect alignment of the source argument - call void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* align 4 %P, i8* align 2 %Q, i64 4, i32 4) + call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* %Q, i32 1, i32 1) + ; CHECK: incorrect alignment of the source argument + call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* align 4 %P, i8* align 1 %Q, i32 4, i32 4) ret void } -declare void @llvm.memcpy.element.atomic.p0i8.p0i8(i8* nocapture, i8* nocapture, i64, i32) nounwind - +declare void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32) nounwind ; CHECK: input module is broken! diff --git a/test/lit.cfg b/test/lit.cfg index 5e903c26657e..ed1ba2d11b1a 100644 --- a/test/lit.cfg +++ b/test/lit.cfg @@ -301,7 +301,7 @@ for pattern in [r"\bbugpoint\b(?!-)", r"\bllvm-modextract\b", r"\bllvm-nm\b", r"\bllvm-objdump\b", - r"\bllvm-pdbdump\b", + r"\bllvm-pdbutil\b", r"\bllvm-profdata\b", r"\bllvm-ranlib\b", r"\bllvm-readobj\b", diff --git a/test/tools/llvm-cvtres/Inputs/combined.obj.coff b/test/tools/llvm-cvtres/Inputs/combined.obj.coff Binary files differnew file mode 100644 index 000000000000..bbb670b258e7 --- /dev/null +++ b/test/tools/llvm-cvtres/Inputs/combined.obj.coff diff --git a/test/tools/llvm-cvtres/Inputs/languages.rc b/test/tools/llvm-cvtres/Inputs/languages.rc new file mode 100644 index 000000000000..081b3a77bebc --- /dev/null +++ b/test/tools/llvm-cvtres/Inputs/languages.rc @@ -0,0 +1,36 @@ +#include "windows.h"
+
+LANGUAGE LANG_ENGLISH, SUBLANG_ENGLISH_US
+randomdat RCDATA
+{
+ "this is a random bit of data that means nothing\0",
+ 0x23a9,
+ 0x140e,
+ 194292,
+}
+
+LANGUAGE LANG_CHINESE, SUBLANG_CHINESE_SIMPLIFIED
+randomdat RCDATA
+{
+ "zhe4 shi4 yi1ge4 sui2ji1 de shu4ju4, zhe4 yi4wei4zhe shen2me\0",
+ 0x23a9,
+ 0x140e,
+ 194292,
+}
+
+LANGUAGE LANG_GERMAN, SUBLANG_GERMAN_LUXEMBOURG
+randomdat RCDATA
+{
+ "Dies ist ein zufälliges Bit von Daten, die nichts bedeutet\0",
+ 0x23a9,
+ 0x140e,
+ 194292,
+}
+
+LANGUAGE LANG_CHINESE, SUBLANG_CHINESE_SIMPLIFIED
+myaccelerators ACCELERATORS
+{
+ "^C", 999, VIRTKEY, ALT
+ "D", 1100, VIRTKEY, CONTROL, SHIFT
+ "^R", 444, ASCII, NOINVERT
+}
diff --git a/test/tools/llvm-cvtres/Inputs/languages.res b/test/tools/llvm-cvtres/Inputs/languages.res Binary files differnew file mode 100644 index 000000000000..31da6166d7f6 --- /dev/null +++ b/test/tools/llvm-cvtres/Inputs/languages.res diff --git a/test/tools/llvm-cvtres/Inputs/test_resource.obj.coff.arm b/test/tools/llvm-cvtres/Inputs/test_resource.obj.coff.arm Binary files differnew file mode 100644 index 000000000000..ca2f9a4fd04e --- /dev/null +++ b/test/tools/llvm-cvtres/Inputs/test_resource.obj.coff.arm diff --git a/test/tools/llvm-cvtres/Inputs/test_resource.obj.coff.x64 b/test/tools/llvm-cvtres/Inputs/test_resource.obj.coff.x64 Binary files differnew file mode 100644 index 000000000000..4620f97f0af1 --- /dev/null +++ b/test/tools/llvm-cvtres/Inputs/test_resource.obj.coff.x64 diff --git a/test/tools/llvm-cvtres/basic.test b/test/tools/llvm-cvtres/basic.test deleted file mode 100644 index fcebef22f650..000000000000 --- a/test/tools/llvm-cvtres/basic.test +++ /dev/null @@ -1,4 +0,0 @@ -; RUN: llvm-cvtres /h > %t -; RUN: FileCheck -input-file=%t %s -check-prefix=HELP_TEST - -; HELP_TEST: OVERVIEW: Resource Converter diff --git a/test/tools/llvm-cvtres/combined.test b/test/tools/llvm-cvtres/combined.test new file mode 100644 index 000000000000..084a0ea0cdec --- /dev/null +++ b/test/tools/llvm-cvtres/combined.test @@ -0,0 +1,313 @@ +// Check that cvtres properly handles merging multiple .res files. +// The inputs were generated with the following commands, using the original Windows +// rc.exe: +// > rc /fo test_resource.res /nologo test_resource.rc +// > rc /fo languages.res /nologo languages.rc +// The object file we are comparing against was generated with this command using +// the original Windows cvtres.exe. +// > cvtres /machine:X86 /readonly /nologo /out:combined.obj.coff \ +// languages.res test_resource.res + +RUN: llvm-cvtres /verbose /out:%t %p/Inputs/languages.res %p/Inputs/test_resource.res +RUN: llvm-readobj -coff-resources -section-data %t | FileCheck %s + +CHECK: Resources [ +CHECK-NEXT: Total Number of Resources: 12 +CHECK-DAG: Number of String Entries: 1 +CHECK-NEXT: Number of ID Entries: 5 +CHECK-NEXT: Type: STRINGARRAY [ +CHECK-NEXT: Table Offset: 0x40 +CHECK-NEXT: Number of String Entries: 1 +CHECK-NEXT: Number of ID Entries: 0 +CHECK-NEXT: Name: MYRESOURCE [ +CHECK-NEXT: Table Offset: 0xE8 +CHECK-NEXT: Number of String Entries: 0 +CHECK-NEXT: Number of ID Entries: 1 +CHECK-NEXT: Language: (ID 1033) [ +CHECK-NEXT: Entry Offset: 0x1D8 +CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +CHECK-NEXT: Major Version: 0 +CHECK-NEXT: Minor Version: 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: Type: kRT_BITMAP (ID 2) [ +CHECK-NEXT: Table Offset: 0x58 +CHECK-NEXT: Number of String Entries: 2 +CHECK-NEXT: Number of ID Entries: 0 +CHECK-NEXT: Name: CURSOR [ +CHECK-NEXT: Table Offset: 0x100 +CHECK-NEXT: Number of String Entries: 0 +CHECK-NEXT: Number of ID Entries: 1 +CHECK-NEXT: Language: (ID 1033) [ +CHECK-NEXT: Entry Offset: 0x1E8 +CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +CHECK-NEXT: Major Version: 0 +CHECK-NEXT: Minor Version: 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: Name: OKAY [ +CHECK-NEXT: Table Offset: 0x118 +CHECK-NEXT: Number of String Entries: 0 +CHECK-NEXT: Number of ID Entries: 1 +CHECK-NEXT: Language: (ID 1033) [ +CHECK-NEXT: Entry Offset: 0x1F8 +CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +CHECK-NEXT: Major Version: 0 +CHECK-NEXT: Minor Version: 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: Type: kRT_MENU (ID 4) [ +CHECK-NEXT: Table Offset: 0x78 +CHECK-NEXT: Number of String Entries: 1 +CHECK-NEXT: Number of ID Entries: 1 +CHECK-NEXT: Name: "EAT" [ +CHECK-NEXT: Table Offset: 0x130 +CHECK-NEXT: Number of String Entries: 0 +CHECK-NEXT: Number of ID Entries: 1 +CHECK-NEXT: Language: (ID 3081) [ +CHECK-NEXT: Entry Offset: 0x208 +CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +CHECK-NEXT: Major Version: 0 +CHECK-NEXT: Minor Version: 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: Name: (ID 14432) [ +CHECK-NEXT: Table Offset: 0x148 +CHECK-NEXT: Number of String Entries: 0 +CHECK-NEXT: Number of ID Entries: 1 +CHECK-NEXT: Language: (ID 2052) [ +CHECK-NEXT: Entry Offset: 0x218 +CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +CHECK-NEXT: Major Version: 0 +CHECK-NEXT: Minor Version: 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: Type: kRT_DIALOG (ID 5) [ +CHECK-NEXT: Table Offset: 0x98 +CHECK-NEXT: Number of String Entries: 1 +CHECK-NEXT: Number of ID Entries: 0 +CHECK-NEXT: Name: TESTDIALOG [ +CHECK-NEXT: Table Offset: 0x160 +CHECK-NEXT: Number of String Entries: 0 +CHECK-NEXT: Number of ID Entries: 1 +CHECK-NEXT: Language: (ID 1033) [ +CHECK-NEXT: Entry Offset: 0x228 +CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +CHECK-NEXT: Major Version: 0 +CHECK-NEXT: Minor Version: 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: Type: kRT_ACCELERATOR (ID 9) [ +CHECK-NEXT: Table Offset: 0xB0 +CHECK-NEXT: Number of String Entries: 1 +CHECK-NEXT: Number of ID Entries: 1 +CHECK-NEXT: Name: MYACCELERATORS [ +CHECK-NEXT: Table Offset: 0x178 +CHECK-NEXT: Number of String Entries: 0 +CHECK-NEXT: Number of ID Entries: 2 +CHECK-NEXT: Language: (ID 1033) [ +CHECK-NEXT: Entry Offset: 0x238 +CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +CHECK-NEXT: Major Version: 0 +CHECK-NEXT: Minor Version: 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: ] +CHECK-NEXT: Language: (ID 2052) [ +CHECK-NEXT: Entry Offset: 0x248 +CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +CHECK-NEXT: Major Version: 0 +CHECK-NEXT: Minor Version: 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: Name: (ID 12) [ +CHECK-NEXT: Table Offset: 0x198 +CHECK-NEXT: Number of String Entries: 0 +CHECK-NEXT: Number of ID Entries: 1 +CHECK-NEXT: Language: (ID 1033) [ +CHECK-NEXT: Entry Offset: 0x258 +CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +CHECK-NEXT: Major Version: 0 +CHECK-NEXT: Minor Version: 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: Type: kRT_RCDATA (ID 10) [ +CHECK-NEXT: Table Offset: 0xD0 +CHECK-NEXT: Number of String Entries: 1 +CHECK-NEXT: Number of ID Entries: 0 +CHECK-NEXT: Name: RANDOMDAT [ +CHECK-NEXT: Table Offset: 0x1B0 +CHECK-NEXT: Number of String Entries: 0 +CHECK-NEXT: Number of ID Entries: 3 +CHECK-NEXT: Language: (ID 1033) [ +CHECK-NEXT: Entry Offset: 0x268 +CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +CHECK-NEXT: Major Version: 0 +CHECK-NEXT: Minor Version: 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: ] +CHECK-NEXT: Language: (ID 2052) [ +CHECK-NEXT: Entry Offset: 0x278 +CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +CHECK-NEXT: Major Version: 0 +CHECK-NEXT: Minor Version: 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: ] +CHECK-NEXT: Language: (ID 4103) [ +CHECK-NEXT: Entry Offset: 0x288 +CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +CHECK-NEXT: Major Version: 0 +CHECK-NEXT: Minor Version: 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-DAG: .rsrc$02 Data ( +CHECK-NEXT: 0000: 74686973 20697320 61207261 6E646F6D |this is a random| +CHECK-NEXT: 0010: 20626974 206F6620 64617461 20746861 | bit of data tha| +CHECK-NEXT: 0020: 74206D65 616E7320 6E6F7468 696E6700 |t means nothing.| +CHECK-NEXT: 0030: A9230E14 F4F60000 7A686534 20736869 |.#......zhe4 shi| +CHECK-NEXT: 0040: 34207969 31676534 20737569 326A6931 |4 yi1ge4 sui2ji1| +CHECK-NEXT: 0050: 20646520 73687534 6A75342C 207A6865 | de shu4ju4, zhe| +CHECK-NEXT: 0060: 34207969 34776569 347A6865 20736865 |4 yi4wei4zhe she| +CHECK-NEXT: 0070: 6E326D65 00A9230E 14F4F600 00000000 |n2me..#.........| +CHECK-NEXT: 0080: 44696573 20697374 2065696E 207A7566 |Dies ist ein zuf| +CHECK-NEXT: 0090: C3A46C6C 69676573 20426974 20766F6E |..lliges Bit von| +CHECK-NEXT: 00A0: 20446174 656E2C20 64696520 6E696368 | Daten, die nich| +CHECK-NEXT: 00B0: 74732062 65646575 74657400 A9230E14 |ts bedeutet..#..| +CHECK-NEXT: 00C0: F4F60000 00000000 11000300 E7030000 |................| +CHECK-NEXT: 00D0: 0D004400 4C040000 82001200 BC010000 |..D.L...........| +CHECK-NEXT: 00E0: 11000300 E7030000 0D004400 4C040000 |..........D.L...| +CHECK-NEXT: 00F0: 82001200 BC010000 28000000 10000000 |........(.......| +CHECK-NEXT: 0100: 10000000 01001800 00000000 00030000 |................| +CHECK-NEXT: 0110: C40E0000 C40E0000 00000000 00000000 |................| +CHECK-NEXT: 0120: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0130: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0140: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0150: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0160: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0170: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0180: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0190: FFFFFFFF FF7F7F7F 7C7C7C78 78787575 |........|||xxxuu| +CHECK-NEXT: 01A0: 75FFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |u...............| +CHECK-NEXT: 01B0: FFFFFFFF FFFFFFFF FFFFFFFF 979797FF |................| +CHECK-NEXT: 01C0: FFFFFFFF FF838383 AAAAAADB DBDB7979 |..............yy| +CHECK-NEXT: 01D0: 79757575 FFFFFFFF FFFFFFFF FFFFFFFF |yuuu............| +CHECK-NEXT: 01E0: FFFFFFFF FFFFFFFF FFFFFFFF 9C9C9C98 |................| +CHECK-NEXT: 01F0: 9898FFFF FF888888 DBDBDBB7 B7B77D7D |..............}}| +CHECK-NEXT: 0200: 7DFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |}...............| +CHECK-NEXT: 0210: FFFFFFFF FFFFFFFF FFFFFFFF A0A0A09C |................| +CHECK-NEXT: 0220: 9C9C9393 93ADADAD F2F2F284 84848181 |................| +CHECK-NEXT: 0230: 81FFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0240: FFFFFFFF FFFFFFFF FFFFFFFF A4A4A4D7 |................| +CHECK-NEXT: 0250: D7D79D9D 9DD0D0D0 EEEEEE91 91918D8D |................| +CHECK-NEXT: 0260: 8DFFFFFF FFFFFF81 81817E7E 7EFFFFFF |..........~~~...| +CHECK-NEXT: 0270: FFFFFFFF FFFFFFFF FFFFFFFF A9A9A9F2 |................| +CHECK-NEXT: 0280: F2F2E5E5 E5E2E2E2 95959591 91918D8D |................| +CHECK-NEXT: 0290: 8D898989 868686FF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 02A0: FFFFFFFF FFFFFFFF FFFFFFFF ADADADF2 |................| +CHECK-NEXT: 02B0: F2F2E1E1 E1DFDFDF E7E7E7E4 E4E4BBBB |................| +CHECK-NEXT: 02C0: BB8E8E8E FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 02D0: FFFFFFFF FFFFFFFF FFFFFFFF B5B5B5F2 |................| +CHECK-NEXT: 02E0: F2F2E8E8 E8E7E7E7 EAEAEAC6 C6C69E9E |................| +CHECK-NEXT: 02F0: 9EFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0300: FFFFFFFF FFFFFFFF FFFFFFFF B9B9B9F4 |................| +CHECK-NEXT: 0310: F4F4ECEC ECEDEDED CBCBCBA7 A7A7FFFF |................| +CHECK-NEXT: 0320: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0330: FFFFFFFF FFFFFFFF FFFFFFFF BDBDBDF7 |................| +CHECK-NEXT: 0340: F7F7EFEF EFD0D0D0 AFAFAFFF FFFFFFFF |................| +CHECK-NEXT: 0350: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0360: FFFFFFFF FFFFFFFF FFFFFFFF C1C1C1F7 |................| +CHECK-NEXT: 0370: F7F7D5D5 D5B6B6B6 FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0380: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0390: FFFFFFFF FFFFFFFF FFFFFFFF C4C4C4D9 |................| +CHECK-NEXT: 03A0: D9D9BEBE BEFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 03B0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 03C0: FFFFFFFF FFFFFFFF FFFFFFFF C8C8C8C5 |................| +CHECK-NEXT: 03D0: C5C5FFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 03E0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 03F0: FFFFFFFF FFFFFFFF FFFFFFFF CBCBCBFF |................| +CHECK-NEXT: 0400: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0410: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0420: 28000000 10000000 10000000 01001800 |(...............| +CHECK-NEXT: 0430: 00000000 00030000 C40E0000 C40E0000 |................| +CHECK-NEXT: 0440: 00000000 00000000 FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0450: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0460: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0470: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0480: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0490: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 04A0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 04B0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 04C0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 04D0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 04E0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 04F0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0500: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0510: FFFFFFFF A0E3A901 B31801B3 1801B318 |................| +CHECK-NEXT: 0520: 01B31801 B31801B3 1861D06F FFFFFFFF |.........a.o....| +CHECK-NEXT: 0530: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0540: FFFFFFFF 01B31800 D7331CDB 49DBF9E2 |.........3..I...| +CHECK-NEXT: 0550: 9BEFAF00 D73300D7 3301B318 FFFFFFFF |.....3..3.......| +CHECK-NEXT: 0560: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0570: FFFFFFFF 01B31800 DE55F6FE F9DBFAE7 |.........U......| +CHECK-NEXT: 0580: FEFFFE86 EFAE00DE 5501B318 FFFFFFFF |........U.......| +CHECK-NEXT: 0590: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 05A0: FFFFFFFF 01B31800 E676DBFB EC00E676 |.........v.....v| +CHECK-NEXT: 05B0: 57EFA5FB FFFD55EE A401B318 FFFFFFFF |W.....U.........| +CHECK-NEXT: 05C0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 05D0: FFFFFFFF 01B31800 ED9800ED 9800ED98 |................| +CHECK-NEXT: 05E0: 00ED9887 F7CFFEFF FF01B318 FFFFFFFF |................| +CHECK-NEXT: 05F0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0600: FFFFFFFF 01B31800 F4BA00F4 BA00F4BA |................| +CHECK-NEXT: 0610: 00F4BA00 F4BA9CFB E401B318 FFFFFFFF |................| +CHECK-NEXT: 0620: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0630: FFFFFFFF 01B31800 FBDB00FB DB00FBDB |................| +CHECK-NEXT: 0640: 00FBDB00 FBDB00FB DB01B318 FFFFFFFF |................| +CHECK-NEXT: 0650: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0660: FFFFFFFF 9FE2A801 B31801B3 1801B318 |................| +CHECK-NEXT: 0670: 01B31801 B31801B3 1861D06F FFFFFFFF |.........a.o....| +CHECK-NEXT: 0680: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0690: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 06A0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 06B0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 06C0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 06D0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 06E0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 06F0: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0700: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0710: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0720: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0730: FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF |................| +CHECK-NEXT: 0740: FFFFFFFF FFFFFFFF 00000000 00006400 |..............d.| +CHECK-NEXT: 0750: 79007500 00000000 65007300 68006100 |y.u.....e.s.h.a.| +CHECK-NEXT: 0760: 6C006100 00008000 66006B00 61006F00 |l.a.....f.k.a.o.| +CHECK-NEXT: 0770: 79006100 00000000 0000C080 00000000 |y.a.............| +CHECK-NEXT: 0780: 02000A00 0A00C800 2C010000 00005400 |........,.....T.| +CHECK-NEXT: 0790: 65007300 74000000 01000250 00000000 |e.s.t......P....| +CHECK-NEXT: 07A0: 0A000A00 E6000E00 0100FFFF 82004300 |..............C.| +CHECK-NEXT: 07B0: 6F006E00 74006900 6E007500 65003A00 |o.n.t.i.n.u.e.:.| +CHECK-NEXT: 07C0: 00000000 00000150 00000000 42008600 |.......P....B...| +CHECK-NEXT: 07D0: A1000D00 0200FFFF 80002600 4F004B00 |..........&.O.K.| +CHECK-NEXT: 07E0: 00000000 00000000 11005800 A4000000 |..........X.....| +CHECK-NEXT: 07F0: 0D004800 2E160000 82001200 BC010000 |..H.............| +CHECK-NEXT: 0800: 00000000 00006400 66006900 73006800 |......d.f.i.s.h.| +CHECK-NEXT: 0810: 00000000 65007300 61006C00 61006400 |....e.s.a.l.a.d.| +CHECK-NEXT: 0820: 00008000 66006400 75006300 6B000000 |....f.d.u.c.k...| +CHECK-NEXT: 0830: 74686973 20697320 61207573 65722064 |this is a user d| +CHECK-NEXT: 0840: 6566696E 65642072 65736F75 72636500 |efined resource.| +CHECK-NEXT: 0850: 69742063 6F6E7461 696E7320 6D616E79 |it contains many| +CHECK-NEXT: 0860: 20737472 696E6773 00000000 00000000 | strings........| +CHECK-NEXT: ) diff --git a/test/tools/llvm-cvtres/help.test b/test/tools/llvm-cvtres/help.test new file mode 100644 index 000000000000..ed76e1f126e3 --- /dev/null +++ b/test/tools/llvm-cvtres/help.test @@ -0,0 +1,13 @@ +; RUN: llvm-cvtres /h > %t +; RUN: FileCheck -input-file=%t %s -check-prefix=HELP_TEST + +; HELP_TEST: OVERVIEW: Resource Converter +; HELP_TEST-DAG: USAGE: cvtres [options] <inputs> +; HELP_TEST-DAG: OPTIONS: +; HELP_TEST-NEXT: /DEFINE:symbol +; HELP_TEST-NEXT: /FOLDDUPS: +; HELP_TEST-NEXT: /MACHINE:{ARM|EBC|IA64|X64|X86} +; HELP_TEST-DAG: /NOLOGO +; HELP_TEST-NEXT: /OUT:filename +; HELP_TEST-NEXT: /READONLY +; HELP_TEST-NEXT: /VERBOSE diff --git a/test/tools/llvm-cvtres/machine.test b/test/tools/llvm-cvtres/machine.test new file mode 100644 index 000000000000..58096d1d8ed1 --- /dev/null +++ b/test/tools/llvm-cvtres/machine.test @@ -0,0 +1,59 @@ +// Check that cvtres properly generates COFF for different machine types. The +// only things that changes with machine type are the machine constant listed +// in the COFF header, and the relocation types in the relocation tables. +// The input was generated with the following command, using the original Windows +// rc.exe: +// > rc /fo test_resource.res /nologo test_resource.rc +// The object files we are comparing against were generated with these commands +// using the original Windows cvtres.exe. +// > cvtres /machine:X86 /readonly /nologo /out:test_resource.obj.coff \ +// test_resource.res +// > cvtres /machine:X64 /readonly /nologo /out:test_resource.obj.coff.x64 \ +// test_resource.res +// > cvtres /machine:ARM /readonly /nologo /out:test_resource.obj.coff.x64 \ +// test_resource.res + +RUN: llvm-cvtres /machine:X86 /out:%t %p/Inputs/test_resource.res +RUN: llvm-readobj -h -relocations %t | FileCheck %s -check-prefix=X86 + +RUN: llvm-cvtres /machine:X64 /out:%t %p/Inputs/test_resource.res +RUN: llvm-readobj -h -relocations %t | FileCheck %s -check-prefix=X64 + +RUN: llvm-cvtres /machine:ARM /out:%t %p/Inputs/test_resource.res +RUN: llvm-readobj -h -relocations %t | FileCheck %s -check-prefix=ARM + +X86: Machine: IMAGE_FILE_MACHINE_I386 (0x14C) +X86-DAG: Relocations [ +X86-DAG: .rsrc$01 { +X86-NEXT: 0x1E8 IMAGE_REL_I386_DIR32NB $R000000 +X86-NEXT: 0x198 IMAGE_REL_I386_DIR32NB $R000018 +X86-NEXT: 0x1A8 IMAGE_REL_I386_DIR32NB $R000340 +X86-NEXT: 0x1C8 IMAGE_REL_I386_DIR32NB $R000668 +X86-NEXT: 0x1D8 IMAGE_REL_I386_DIR32NB $R000698 +X86-NEXT: 0x1F8 IMAGE_REL_I386_DIR32NB $R000708 +X86-NEXT: 0x1B8 IMAGE_REL_I386_DIR32NB $R000720 +X86-NEXT: 0x188 IMAGE_REL_I386_DIR32NB $R000750 + +X64: Machine: IMAGE_FILE_MACHINE_AMD64 (0x8664) +X64-DAG: Relocations [ +X64-DAG: .rsrc$01 { +X64-NEXT: 0x1E8 IMAGE_REL_AMD64_ADDR32NB $R000000 +X64-NEXT: 0x198 IMAGE_REL_AMD64_ADDR32NB $R000018 +X64-NEXT: 0x1A8 IMAGE_REL_AMD64_ADDR32NB $R000340 +X64-NEXT: 0x1C8 IMAGE_REL_AMD64_ADDR32NB $R000668 +X64-NEXT: 0x1D8 IMAGE_REL_AMD64_ADDR32NB $R000698 +X64-NEXT: 0x1F8 IMAGE_REL_AMD64_ADDR32NB $R000708 +X64-NEXT: 0x1B8 IMAGE_REL_AMD64_ADDR32NB $R000720 +X64-NEXT: 0x188 IMAGE_REL_AMD64_ADDR32NB $R000750 + +ARM: Machine: IMAGE_FILE_MACHINE_ARMNT (0x1C4) +ARM-DAG: Relocations [ +ARM-DAG: .rsrc$01 { +ARM-NEXT: 0x1E8 IMAGE_REL_ARM_ADDR32NB $R000000 +ARM-NEXT: 0x198 IMAGE_REL_ARM_ADDR32NB $R000018 +ARM-NEXT: 0x1A8 IMAGE_REL_ARM_ADDR32NB $R000340 +ARM-NEXT: 0x1C8 IMAGE_REL_ARM_ADDR32NB $R000668 +ARM-NEXT: 0x1D8 IMAGE_REL_ARM_ADDR32NB $R000698 +ARM-NEXT: 0x1F8 IMAGE_REL_ARM_ADDR32NB $R000708 +ARM-NEXT: 0x1B8 IMAGE_REL_ARM_ADDR32NB $R000720 +ARM-NEXT: 0x188 IMAGE_REL_ARM_ADDR32NB $R000750 diff --git a/test/tools/llvm-cvtres/object.test b/test/tools/llvm-cvtres/object.test index 8117ecc910c9..95522b17bd07 100644 --- a/test/tools/llvm-cvtres/object.test +++ b/test/tools/llvm-cvtres/object.test @@ -3,107 +3,138 @@ // rc.exe: // > rc /fo test_resource.res /nologo test_resource.rc // The object file we are comparing against was generated with this command using -// the original cvtres. -// > cvtres /machine:X86 /readonly /nologo /out:test_resource.o test_resource.res +// the original Windows cvtres.exe. +// > cvtres /machine:X86 /readonly /nologo /out:test_resource.obj.coff \ +// test_resource.res -RUN: llvm-cvtres /out:%t %p/Inputs/test_resource.res +RUN: llvm-cvtres /verbose /out:%t %p/Inputs/test_resource.res RUN: llvm-readobj -coff-resources -section-data %t | FileCheck %s -CHECK: Resources [ -CHECK-NEXT: String Name Entries: 1 -CHECK-NEXT: ID Entries: 4 -CHECK-NEXT: Type: STRINGARRAY [ -CHECK-NEXT: String Name Entries: 1 -CHECK-NEXT: ID Entries: 0 -CHECK-NEXT: Name: MYRESOURCE [ -CHECK-NEXT: String Name Entries: 0 -CHECK-NEXT: ID Entries: 1 -CHECK-NEXT: Language: (ID 1033) [ -CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) -CHECK-NEXT: Major Version: 0 -CHECK-NEXT: Minor Version: 0 -CHECK-NEXT: ] -CHECK-NEXT: ] -CHECK-NEXT: ] -CHECK-NEXT: Type: kRT_BITMAP (ID 2) [ -CHECK-NEXT: String Name Entries: 2 -CHECK-NEXT: ID Entries: 0 -CHECK-NEXT: Name: CURSOR [ -CHECK-NEXT: String Name Entries: 0 -CHECK-NEXT: ID Entries: 1 -CHECK-NEXT: Language: (ID 1033) [ -CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) -CHECK-NEXT: Major Version: 0 -CHECK-NEXT: Minor Version: 0 -CHECK-NEXT: ] -CHECK-NEXT: ] -CHECK-NEXT: Name: OKAY [ -CHECK-NEXT: String Name Entries: 0 -CHECK-NEXT: ID Entries: 1 -CHECK-NEXT: Language: (ID 1033) [ -CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) -CHECK-NEXT: Major Version: 0 -CHECK-NEXT: Minor Version: 0 -CHECK-NEXT: ] -CHECK-NEXT: ] -CHECK-NEXT: ] -CHECK-NEXT: Type: kRT_MENU (ID 4) [ -CHECK-NEXT: String Name Entries: 1 -CHECK-NEXT: ID Entries: 1 -CHECK-NEXT: Name: "EAT" [ -CHECK-NEXT: String Name Entries: 0 -CHECK-NEXT: ID Entries: 1 -CHECK-NEXT: Language: (ID 3081) [ -CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) -CHECK-NEXT: Major Version: 0 -CHECK-NEXT: Minor Version: 0 -CHECK-NEXT: ] -CHECK-NEXT: ] -CHECK-NEXT: Name: (ID 14432) [ -CHECK-NEXT: String Name Entries: 0 -CHECK-NEXT: ID Entries: 1 -CHECK-NEXT: Language: (ID 2052) [ -CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) -CHECK-NEXT: Major Version: 0 -CHECK-NEXT: Minor Version: 0 -CHECK-NEXT: ] -CHECK-NEXT: ] -CHECK-NEXT: ] -CHECK-NEXT: Type: kRT_DIALOG (ID 5) [ -CHECK-NEXT: String Name Entries: 1 -CHECK-NEXT: ID Entries: 0 -CHECK-NEXT: Name: TESTDIALOG [ -CHECK-NEXT: String Name Entries: 0 -CHECK-NEXT: ID Entries: 1 -CHECK-NEXT: Language: (ID 1033) [ -CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) -CHECK-NEXT: Major Version: 0 -CHECK-NEXT: Minor Version: 0 -CHECK-NEXT: ] -CHECK-NEXT: ] -CHECK-NEXT: ] -CHECK-NEXT: Type: kRT_ACCELERATOR (ID 9) [ -CHECK-NEXT: String Name Entries: 1 -CHECK-NEXT: ID Entries: 1 -CHECK-NEXT: Name: MYACCELERATORS [ -CHECK-NEXT: String Name Entries: 0 -CHECK-NEXT: ID Entries: 1 -CHECK-NEXT: Language: (ID 1033) [ -CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) -CHECK-NEXT: Major Version: 0 -CHECK-NEXT: Minor Version: 0 -CHECK-NEXT: ] -CHECK-NEXT: ] -CHECK-NEXT: Name: (ID 12) [ -CHECK-NEXT: String Name Entries: 0 -CHECK-NEXT: ID Entries: 1 -CHECK-NEXT: Language: (ID 1033) [ -CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) -CHECK-NEXT: Major Version: 0 -CHECK-NEXT: Minor Version: 0 -CHECK-NEXT: ] -CHECK-NEXT: ] -CHECK-NEXT: ] +CHECK: Resources [ +CHECK-NEXT: Total Number of Resources: 8 +CHECK-DAG: Number of String Entries: 1 +CHECK-NEXT: Number of ID Entries: 4 +CHECK-NEXT: Type: STRINGARRAY [ +CHECK-NEXT: Table Offset: 0x38 +CHECK-NEXT: Number of String Entries: 1 +CHECK-NEXT: Number of ID Entries: 0 +CHECK-NEXT: Name: MYRESOURCE [ +CHECK-NEXT: Table Offset: 0xC8 +CHECK-NEXT: Number of String Entries: 0 +CHECK-NEXT: Number of ID Entries: 1 +CHECK-NEXT: Language: (ID 1033) [ +CHECK-NEXT: Entry Offset: 0x188 +CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +CHECK-NEXT: Major Version: 0 +CHECK-NEXT: Minor Version: 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: Type: kRT_BITMAP (ID 2) [ +CHECK-NEXT: Table Offset: 0x50 +CHECK-NEXT: Number of String Entries: 2 +CHECK-NEXT: Number of ID Entries: 0 +CHECK-NEXT: Name: CURSOR [ +CHECK-NEXT: Table Offset: 0xE0 +CHECK-NEXT: Number of String Entries: 0 +CHECK-NEXT: Number of ID Entries: 1 +CHECK-NEXT: Language: (ID 1033) [ +CHECK-NEXT: Entry Offset: 0x198 +CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +CHECK-NEXT: Major Version: 0 +CHECK-NEXT: Minor Version: 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: Name: OKAY [ +CHECK-NEXT: Table Offset: 0xF8 +CHECK-NEXT: Number of String Entries: 0 +CHECK-NEXT: Number of ID Entries: 1 +CHECK-NEXT: Language: (ID 1033) [ +CHECK-NEXT: Entry Offset: 0x1A8 +CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +CHECK-NEXT: Major Version: 0 +CHECK-NEXT: Minor Version: 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: Type: kRT_MENU (ID 4) [ +CHECK-NEXT: Table Offset: 0x70 +CHECK-NEXT: Number of String Entries: 1 +CHECK-NEXT: Number of ID Entries: 1 +CHECK-NEXT: Name: "EAT" [ +CHECK-NEXT: Table Offset: 0x110 +CHECK-NEXT: Number of String Entries: 0 +CHECK-NEXT: Number of ID Entries: 1 +CHECK-NEXT: Language: (ID 3081) [ +CHECK-NEXT: Entry Offset: 0x1B8 +CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +CHECK-NEXT: Major Version: 0 +CHECK-NEXT: Minor Version: 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: Name: (ID 14432) [ +CHECK-NEXT: Table Offset: 0x128 +CHECK-NEXT: Number of String Entries: 0 +CHECK-NEXT: Number of ID Entries: 1 +CHECK-NEXT: Language: (ID 2052) [ +CHECK-NEXT: Entry Offset: 0x1C8 +CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +CHECK-NEXT: Major Version: 0 +CHECK-NEXT: Minor Version: 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: Type: kRT_DIALOG (ID 5) [ +CHECK-NEXT: Table Offset: 0x90 +CHECK-NEXT: Number of String Entries: 1 +CHECK-NEXT: Number of ID Entries: 0 +CHECK-NEXT: Name: TESTDIALOG [ +CHECK-NEXT: Table Offset: 0x140 +CHECK-NEXT: Number of String Entries: 0 +CHECK-NEXT: Number of ID Entries: 1 +CHECK-NEXT: Language: (ID 1033) [ +CHECK-NEXT: Entry Offset: 0x1D8 +CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +CHECK-NEXT: Major Version: 0 +CHECK-NEXT: Minor Version: 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: Type: kRT_ACCELERATOR (ID 9) [ +CHECK-NEXT: Table Offset: 0xA8 +CHECK-NEXT: Number of String Entries: 1 +CHECK-NEXT: Number of ID Entries: 1 +CHECK-NEXT: Name: MYACCELERATORS [ +CHECK-NEXT: Table Offset: 0x158 +CHECK-NEXT: Number of String Entries: 0 +CHECK-NEXT: Number of ID Entries: 1 +CHECK-NEXT: Language: (ID 1033) [ +CHECK-NEXT: Entry Offset: 0x1E8 +CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +CHECK-NEXT: Major Version: 0 +CHECK-NEXT: Minor Version: 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: Name: (ID 12) [ +CHECK-NEXT: Table Offset: 0x170 +CHECK-NEXT: Number of String Entries: 0 +CHECK-NEXT: Number of ID Entries: 1 +CHECK-NEXT: Language: (ID 1033) [ +CHECK-NEXT: Entry Offset: 0x1F8 +CHECK-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +CHECK-NEXT: Major Version: 0 +CHECK-NEXT: Minor Version: 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: ] +CHECK-NEXT: ] +CHECK-NEXT: ] CHECK-DAG: .rsrc$02 Data ( CHECK-NEXT: 0000: 11000300 E7030000 0D004400 4C040000 |..........D.L...| CHECK-NEXT: 0010: 82001200 BC010000 28000000 10000000 |........(.......| diff --git a/test/tools/llvm-cvtres/parse.test b/test/tools/llvm-cvtres/parse.test index 23911ada82e8..c8b3d227f0b5 100644 --- a/test/tools/llvm-cvtres/parse.test +++ b/test/tools/llvm-cvtres/parse.test @@ -2,7 +2,7 @@ // rc.exe: // > rc /fo test_resource.res /nologo test_resource.rc -RUN: llvm-cvtres /verbose /out:%t %p/Inputs/test_resource.res | FileCheck %s +RUN: llvm-cvtres /out:%t /verbose %p/Inputs/test_resource.res | FileCheck %s CHECK: Number of resources: 8 CHECK-NEXT: Resource Tree [ diff --git a/test/tools/llvm-dwarfdump/X86/apple_names_verify_buckets.s b/test/tools/llvm-dwarfdump/X86/apple_names_verify_buckets.s new file mode 100644 index 000000000000..903153c79a48 --- /dev/null +++ b/test/tools/llvm-dwarfdump/X86/apple_names_verify_buckets.s @@ -0,0 +1,192 @@ +# RUN: llvm-mc %s -filetype obj -triple x86_64-apple-darwin -o - \ +# RUN: | not llvm-dwarfdump -verify - \ +# RUN: | FileCheck %s + +# CHECK: Verifying .apple_names... +# CHECK-NEXT: error: + +# This test is meant to verify that the -verify option +# in llvm-dwarfdump, correctly identifies +# an invalid hash index for bucket[0] in the .apple_names section. + + .section __TEXT,__text,regular,pure_instructions + .file 1 "basic.c" + .comm _i,4,2 ## @i + .section __DWARF,__debug_str,regular,debug +Linfo_string: + .asciz "basic.c" ## string offset=42 + .asciz "i" ## string offset=84 + .asciz "int" ## string offset=86 + .section __DWARF,__debug_loc,regular,debug +Lsection_debug_loc: + .section __DWARF,__debug_abbrev,regular,debug +Lsection_abbrev: + .byte 1 ## Abbreviation Code + .byte 17 ## DW_TAG_compile_unit + .byte 1 ## DW_CHILDREN_yes + .byte 37 ## DW_AT_producer + .byte 14 ## DW_FORM_strp + .byte 19 ## DW_AT_language + .byte 5 ## DW_FORM_data2 + .byte 3 ## DW_AT_name + .byte 14 ## DW_FORM_strp + .byte 16 ## DW_AT_stmt_list + .byte 23 ## DW_FORM_sec_offset + .byte 27 ## DW_AT_comp_dir + .byte 14 ## DW_FORM_strp + .byte 0 ## EOM(1) + .byte 0 ## EOM(2) + .byte 2 ## Abbreviation Code + .byte 52 ## DW_TAG_variable + .byte 0 ## DW_CHILDREN_no + .byte 3 ## DW_AT_name + .byte 14 ## DW_FORM_strp + .byte 73 ## DW_AT_type + .byte 19 ## DW_FORM_ref4 + .byte 63 ## DW_AT_external + .byte 25 ## DW_FORM_flag_present + .byte 58 ## DW_AT_decl_file + .byte 11 ## DW_FORM_data1 + .byte 59 ## DW_AT_decl_line + .byte 11 ## DW_FORM_data1 + .byte 2 ## DW_AT_location + .byte 24 ## DW_FORM_exprloc + .byte 0 ## EOM(1) + .byte 0 ## EOM(2) + .byte 3 ## Abbreviation Code + .byte 36 ## DW_TAG_base_type + .byte 0 ## DW_CHILDREN_no + .byte 3 ## DW_AT_name + .byte 14 ## DW_FORM_strp + .byte 62 ## DW_AT_encoding + .byte 11 ## DW_FORM_data1 + .byte 11 ## DW_AT_byte_size + .byte 11 ## DW_FORM_data1 + .byte 0 ## EOM(1) + .byte 0 ## EOM(2) + .byte 0 ## EOM(3) + .section __DWARF,__debug_info,regular,debug +Lsection_info: +Lcu_begin0: + .long 55 ## Length of Unit + .short 4 ## DWARF version number +Lset0 = Lsection_abbrev-Lsection_abbrev ## Offset Into Abbrev. Section + .long Lset0 + .byte 8 ## Address Size (in bytes) + .byte 1 ## Abbrev [1] 0xb:0x30 DW_TAG_compile_unit + .long 0 ## DW_AT_producer + .short 12 ## DW_AT_language + .long 42 ## DW_AT_name +Lset1 = Lline_table_start0-Lsection_line ## DW_AT_stmt_list + .long Lset1 + .long 50 ## DW_AT_comp_dir + .byte 2 ## Abbrev [2] 0x1e:0x15 DW_TAG_variable + .long 84 ## DW_AT_name + .long 51 ## DW_AT_type + ## DW_AT_external + .byte 1 ## DW_AT_decl_file + .byte 1 ## DW_AT_decl_line + .byte 9 ## DW_AT_location + .byte 3 + .quad _i + .byte 3 ## Abbrev [3] 0x33:0x7 DW_TAG_base_type + .long 86 ## DW_AT_name + .byte 5 ## DW_AT_encoding + .byte 4 ## DW_AT_byte_size + .byte 0 ## End Of Children Mark + .section __DWARF,__debug_ranges,regular,debug +Ldebug_range: + .section __DWARF,__debug_macinfo,regular,debug +Ldebug_macinfo: +Lcu_macro_begin0: + .byte 0 ## End Of Macro List Mark + .section __DWARF,__apple_names,regular,debug +Lnames_begin: + .long 1212240712 ## Header Magic + .short 1 ## Header Version + .short 0 ## Header Hash Function + .long 1 ## Header Bucket Count + .long 1 ## Header Hash Count + .long 12 ## Header Data Length + .long 0 ## HeaderData Die Offset Base + .long 1 ## HeaderData Atom Count + .short 1 ## DW_ATOM_die_offset + .short 6 ## DW_FORM_data4 + .long -2 ## Bucket 0 -- error: Bucket[0] has invalid hash index: [-2] + .long 177678 ## Hash in Bucket 0 + .long LNames0-Lnames_begin ## Offset in Bucket 0 +LNames0: + .long 84 ## i + .long 1 ## Num DIEs + .long 30 + .long 0 + .section __DWARF,__apple_objc,regular,debug +Lobjc_begin: + .long 1212240712 ## Header Magic + .short 1 ## Header Version + .short 0 ## Header Hash Function + .long 1 ## Header Bucket Count + .long 0 ## Header Hash Count + .long 12 ## Header Data Length + .long 0 ## HeaderData Die Offset Base + .long 1 ## HeaderData Atom Count + .short 1 ## DW_ATOM_die_offset + .short 6 ## DW_FORM_data4 + .long -1 ## Bucket 0 + .section __DWARF,__apple_namespac,regular,debug +Lnamespac_begin: + .long 1212240712 ## Header Magic + .short 1 ## Header Version + .short 0 ## Header Hash Function + .long 1 ## Header Bucket Count + .long 0 ## Header Hash Count + .long 12 ## Header Data Length + .long 0 ## HeaderData Die Offset Base + .long 1 ## HeaderData Atom Count + .short 1 ## DW_ATOM_die_offset + .short 6 ## DW_FORM_data4 + .long -1 ## Bucket 0 + .section __DWARF,__apple_types,regular,debug +Ltypes_begin: + .long 1212240712 ## Header Magic + .short 1 ## Header Version + .short 0 ## Header Hash Function + .long 1 ## Header Bucket Count + .long 1 ## Header Hash Count + .long 20 ## Header Data Length + .long 0 ## HeaderData Die Offset Base + .long 3 ## HeaderData Atom Count + .short 1 ## DW_ATOM_die_offset + .short 6 ## DW_FORM_data4 + .short 3 ## DW_ATOM_die_tag + .short 5 ## DW_FORM_data2 + .short 4 ## DW_ATOM_type_flags + .short 11 ## DW_FORM_data1 + .long 0 ## Bucket 0 + .long 193495088 ## Hash in Bucket 0 + .long Ltypes0-Ltypes_begin ## Offset in Bucket 0 +Ltypes0: + .long 86 ## int + .long 1 ## Num DIEs + .long 51 + .short 36 + .byte 0 + .long 0 + .section __DWARF,__apple_exttypes,regular,debug +Lexttypes_begin: + .long 1212240712 ## Header Magic + .short 1 ## Header Version + .short 0 ## Header Hash Function + .long 1 ## Header Bucket Count + .long 0 ## Header Hash Count + .long 12 ## Header Data Length + .long 0 ## HeaderData Die Offset Base + .long 1 ## HeaderData Atom Count + .short 7 ## DW_ATOM_ext_types + .short 6 ## DW_FORM_data4 + .long -1 ## Bucket 0 + +.subsections_via_symbols + .section __DWARF,__debug_line,regular,debug +Lsection_line: +Lline_table_start0: diff --git a/test/tools/llvm-pdbdump/raw-stream-data.test b/test/tools/llvm-pdbdump/raw-stream-data.test deleted file mode 100644 index 1d7c23fe3672..000000000000 --- a/test/tools/llvm-pdbdump/raw-stream-data.test +++ /dev/null @@ -1,47 +0,0 @@ -; RUN: llvm-pdbutil raw -stream-data=8 %p/Inputs/LoadAddressTest.pdb \
-; RUN: | FileCheck %s -check-prefix=FULL_STREAM
-; RUN: llvm-pdbutil raw -stream-data=8:4 %p/Inputs/LoadAddressTest.pdb \
-; RUN: | FileCheck %s -check-prefix=OFFSET_STREAM
-; RUN: llvm-pdbutil raw -stream-data=8:4@24 %p/Inputs/LoadAddressTest.pdb \
-; RUN: | FileCheck %s -check-prefix=OFFSET_AND_LENGTH
-
-FULL_STREAM: Stream Data {
-FULL_STREAM-NEXT: Stream {
-FULL_STREAM-NEXT: Index: 8
-FULL_STREAM-NEXT: Type: Public Symbol Records
-FULL_STREAM-NEXT: Size: 40
-FULL_STREAM-NEXT: Blocks:
-FULL_STREAM-NEXT: Data (
-FULL_STREAM-NEXT: 0000: 12000E11 02000000 10000000 01005F6D |.............._m|
-FULL_STREAM-NEXT: 0010: 61696E00 12002511 00000000 88000000 |ain...%.........|
-FULL_STREAM-NEXT: 0020: 01006D61 696E0000 |..main..|
-FULL_STREAM-NEXT: )
-FULL_STREAM-NEXT: }
-FULL_STREAM-NEXT: }
-
-OFFSET_STREAM: Stream Data {
-OFFSET_STREAM-NEXT: Stream {
-OFFSET_STREAM-NEXT: Index: 8
-OFFSET_STREAM-NEXT: Type: Public Symbol Records
-OFFSET_STREAM-NEXT: Size: 40
-OFFSET_STREAM-NEXT: Blocks:
-OFFSET_STREAM-NEXT: Data (
-OFFSET_STREAM-NEXT: 0004: 02000000 10000000 01005F6D 61696E00 |.........._main.|
-OFFSET_STREAM-NEXT: 0014: 12002511 00000000 88000000 01006D61 |..%...........ma|
-OFFSET_STREAM-NEXT: 0024: 696E0000 |in..|
-OFFSET_STREAM-NEXT: )
-OFFSET_STREAM-NEXT: }
-OFFSET_STREAM-NEXT:}
-
-OFFSET_AND_LENGTH: Stream Data {
-OFFSET_AND_LENGTH-NEXT: Stream {
-OFFSET_AND_LENGTH-NEXT: Index: 8
-OFFSET_AND_LENGTH-NEXT: Type: Public Symbol Records
-OFFSET_AND_LENGTH-NEXT: Size: 40
-OFFSET_AND_LENGTH-NEXT: Blocks:
-OFFSET_AND_LENGTH-NEXT: Data (
-OFFSET_AND_LENGTH-NEXT: 0004: 02000000 10000000 01005F6D 61696E00 |.........._main.|
-OFFSET_AND_LENGTH-NEXT: 0014: 12002511 00000000 |..%.....|
-OFFSET_AND_LENGTH-NEXT: )
-OFFSET_AND_LENGTH-NEXT: }
-OFFSET_AND_LENGTH-NEXT:}
\ No newline at end of file diff --git a/test/tools/llvm-readobj/resources.test b/test/tools/llvm-readobj/resources.test index 855ce5393b84..589a9c968aae 100644 --- a/test/tools/llvm-readobj/resources.test +++ b/test/tools/llvm-readobj/resources.test @@ -9,103 +9,135 @@ RUN: | FileCheck %s -check-prefix ZERO RUN: llvm-readobj -coff-resources %p/Inputs/resources/test_resource.obj.coff \ RUN: | FileCheck %s -check-prefix TEST_RES -ZERO: Resources [ -ZERO-NEXT: String Name Entries: 0 -ZERO-NEXT: ID Entries: 1 -ZERO-NEXT: Type: kRT_STRING (ID 6) [ -ZERO-NEXT: String Name Entries: 0 -ZERO-NEXT: ID Entries: 1 -ZERO-NEXT: Name: (ID 1) [ -ZERO-NEXT: String Name Entries: 0 -ZERO-NEXT: ID Entries: 1 -ZERO-NEXT: Language: (ID 1033) [ -ZERO-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) -ZERO-NEXT: Major Version: 0 -ZERO-NEXT: Minor Version: 0 -ZERO-NEXT: ] -ZERO-NEXT: ] -ZERO-NEXT: ] +ZERO: Resources [ +ZERO-NEXT: Total Number of Resources: 1 +ZERO-NEXT: Base Table Address: 0x188 +ZERO-DAG: Number of String Entries: 0 +ZERO-NEXT: Number of ID Entries: 1 +ZERO-NEXT: Type: kRT_STRING (ID 6) [ +ZERO-NEXT: Table Offset: 0x18 +ZERO-NEXT: Number of String Entries: 0 +ZERO-NEXT: Number of ID Entries: 1 +ZERO-NEXT: Name: (ID 1) [ +ZERO-NEXT: Table Offset: 0x30 +ZERO-NEXT: Number of String Entries: 0 +ZERO-NEXT: Number of ID Entries: 1 +ZERO-NEXT: Language: (ID 1033) [ +ZERO-NEXT: Entry Offset: 0x48 +ZERO-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +ZERO-NEXT: Major Version: 0 +ZERO-NEXT: Minor Version: 0 +ZERO-NEXT: Characteristics: 0 +ZERO-NEXT: ] +ZERO-NEXT: ] +ZERO-NEXT: ] - -TEST_RES: Resources [ -TEST_RES-NEXT: String Name Entries: 0 -TEST_RES-NEXT: ID Entries: 4 -TEST_RES-NEXT: Type: kRT_BITMAP (ID 2) [ -TEST_RES-NEXT: String Name Entries: 2 -TEST_RES-NEXT: ID Entries: 0 -TEST_RES-NEXT: Name: CURSOR [ -TEST_RES-NEXT: String Name Entries: 0 -TEST_RES-NEXT: ID Entries: 1 -TEST_RES-NEXT: Language: (ID 1033) [ -TEST_RES-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) -TEST_RES-NEXT: Major Version: 0 -TEST_RES-NEXT: Minor Version: 0 -TEST_RES-NEXT: ] -TEST_RES-NEXT: ] -TEST_RES-NEXT: Name: OKAY [ -TEST_RES-NEXT: String Name Entries: 0 -TEST_RES-NEXT: ID Entries: 1 -TEST_RES-NEXT: Language: (ID 1033) [ -TEST_RES-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) -TEST_RES-NEXT: Major Version: 0 -TEST_RES-NEXT: Minor Version: 0 -TEST_RES-NEXT: ] -TEST_RES-NEXT: ] -TEST_RES-NEXT: ] -TEST_RES-NEXT: Type: kRT_MENU (ID 4) [ -TEST_RES-NEXT: String Name Entries: 1 -TEST_RES-NEXT: ID Entries: 1 -TEST_RES-NEXT: Name: "EAT" [ -TEST_RES-NEXT: String Name Entries: 0 -TEST_RES-NEXT: ID Entries: 1 -TEST_RES-NEXT: Language: (ID 3081) [ -TEST_RES-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) -TEST_RES-NEXT: Major Version: 0 -TEST_RES-NEXT: Minor Version: 0 -TEST_RES-NEXT: ] -TEST_RES-NEXT: ] -TEST_RES-NEXT: Name: (ID 14432) [ -TEST_RES-NEXT: String Name Entries: 0 -TEST_RES-NEXT: ID Entries: 1 -TEST_RES-NEXT: Language: (ID 2052) [ -TEST_RES-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) -TEST_RES-NEXT: Major Version: 0 -TEST_RES-NEXT: Minor Version: 0 -TEST_RES-NEXT: ] -TEST_RES-NEXT: ] -TEST_RES-NEXT: ] -TEST_RES-NEXT: Type: kRT_DIALOG (ID 5) [ -TEST_RES-NEXT: String Name Entries: 1 -TEST_RES-NEXT: ID Entries: 0 -TEST_RES-NEXT: Name: TESTDIALOG [ -TEST_RES-NEXT: String Name Entries: 0 -TEST_RES-NEXT: ID Entries: 1 -TEST_RES-NEXT: Language: (ID 1033) [ -TEST_RES-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) -TEST_RES-NEXT: Major Version: 0 -TEST_RES-NEXT: Minor Version: 0 -TEST_RES-NEXT: ] -TEST_RES-NEXT: ] -TEST_RES-NEXT: ] -TEST_RES-NEXT: Type: kRT_ACCELERATOR (ID 9) [ -TEST_RES-NEXT: String Name Entries: 1 -TEST_RES-NEXT: ID Entries: 1 -TEST_RES-NEXT: Name: MYACCELERATORS [ -TEST_RES-NEXT: String Name Entries: 0 -TEST_RES-NEXT: ID Entries: 1 -TEST_RES-NEXT: Language: (ID 1033) [ -TEST_RES-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) -TEST_RES-NEXT: Major Version: 0 -TEST_RES-NEXT: Minor Version: 0 -TEST_RES-NEXT: ] -TEST_RES-NEXT: ] -TEST_RES-NEXT: Name: (ID 12) [ -TEST_RES-NEXT: String Name Entries: 0 -TEST_RES-NEXT: ID Entries: 1 -TEST_RES-NEXT: Language: (ID 1033) [ -TEST_RES-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) -TEST_RES-NEXT: Major Version: 0 -TEST_RES-NEXT: Minor Version: 0 -TEST_RES-NEXT: ] -TEST_RES-NEXT: ] -TEST_RES-NEXT: ] +TEST_RES: Resources [ +TEST_RES-NEXT: Total Number of Resources: 7 +TEST_RES-NEXT: Base Table Address: 0x1C0 +TEST_RES-DAG: Number of String Entries: 0 +TEST_RES-NEXT: Number of ID Entries: 4 +TEST_RES-NEXT: Type: kRT_BITMAP (ID 2) [ +TEST_RES-NEXT: Table Offset: 0x30 +TEST_RES-NEXT: Number of String Entries: 2 +TEST_RES-NEXT: Number of ID Entries: 0 +TEST_RES-NEXT: Name: CURSOR [ +TEST_RES-NEXT: Table Offset: 0xA8 +TEST_RES-NEXT: Number of String Entries: 0 +TEST_RES-NEXT: Number of ID Entries: 1 +TEST_RES-NEXT: Language: (ID 1033) [ +TEST_RES-NEXT: Entry Offset: 0x150 +TEST_RES-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +TEST_RES-NEXT: Major Version: 0 +TEST_RES-NEXT: Minor Version: 0 +TEST_RES-NEXT: Characteristics: 0 +TEST_RES-NEXT: ] +TEST_RES-NEXT: ] +TEST_RES-NEXT: Name: OKAY [ +TEST_RES-NEXT: Table Offset: 0xC0 +TEST_RES-NEXT: Number of String Entries: 0 +TEST_RES-NEXT: Number of ID Entries: 1 +TEST_RES-NEXT: Language: (ID 1033) [ +TEST_RES-NEXT: Entry Offset: 0x160 +TEST_RES-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +TEST_RES-NEXT: Major Version: 0 +TEST_RES-NEXT: Minor Version: 0 +TEST_RES-NEXT: Characteristics: 0 +TEST_RES-NEXT: ] +TEST_RES-NEXT: ] +TEST_RES-NEXT: ] +TEST_RES-NEXT: Type: kRT_MENU (ID 4) [ +TEST_RES-NEXT: Table Offset: 0x50 +TEST_RES-NEXT: Number of String Entries: 1 +TEST_RES-NEXT: Number of ID Entries: 1 +TEST_RES-NEXT: Name: "EAT" [ +TEST_RES-NEXT: Table Offset: 0xD8 +TEST_RES-NEXT: Number of String Entries: 0 +TEST_RES-NEXT: Number of ID Entries: 1 +TEST_RES-NEXT: Language: (ID 3081) [ +TEST_RES-NEXT: Entry Offset: 0x170 +TEST_RES-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +TEST_RES-NEXT: Major Version: 0 +TEST_RES-NEXT: Minor Version: 0 +TEST_RES-NEXT: Characteristics: 0 +TEST_RES-NEXT: ] +TEST_RES-NEXT: ] +TEST_RES-NEXT: Name: (ID 14432) [ +TEST_RES-NEXT: Table Offset: 0xF0 +TEST_RES-NEXT: Number of String Entries: 0 +TEST_RES-NEXT: Number of ID Entries: 1 +TEST_RES-NEXT: Language: (ID 2052) [ +TEST_RES-NEXT: Entry Offset: 0x180 +TEST_RES-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +TEST_RES-NEXT: Major Version: 0 +TEST_RES-NEXT: Minor Version: 0 +TEST_RES-NEXT: Characteristics: 0 +TEST_RES-NEXT: ] +TEST_RES-NEXT: ] +TEST_RES-NEXT: ] +TEST_RES-NEXT: Type: kRT_DIALOG (ID 5) [ +TEST_RES-NEXT: Table Offset: 0x70 +TEST_RES-NEXT: Number of String Entries: 1 +TEST_RES-NEXT: Number of ID Entries: 0 +TEST_RES-NEXT: Name: TESTDIALOG [ +TEST_RES-NEXT: Table Offset: 0x108 +TEST_RES-NEXT: Number of String Entries: 0 +TEST_RES-NEXT: Number of ID Entries: 1 +TEST_RES-NEXT: Language: (ID 1033) [ +TEST_RES-NEXT: Entry Offset: 0x190 +TEST_RES-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +TEST_RES-NEXT: Major Version: 0 +TEST_RES-NEXT: Minor Version: 0 +TEST_RES-NEXT: Characteristics: 0 +TEST_RES-NEXT: ] +TEST_RES-NEXT: ] +TEST_RES-NEXT: ] +TEST_RES-NEXT: Type: kRT_ACCELERATOR (ID 9) [ +TEST_RES-NEXT: Table Offset: 0x88 +TEST_RES-NEXT: Number of String Entries: 1 +TEST_RES-NEXT: Number of ID Entries: 1 +TEST_RES-NEXT: Name: MYACCELERATORS [ +TEST_RES-NEXT: Table Offset: 0x120 +TEST_RES-NEXT: Number of String Entries: 0 +TEST_RES-NEXT: Number of ID Entries: 1 +TEST_RES-NEXT: Language: (ID 1033) [ +TEST_RES-NEXT: Entry Offset: 0x1A0 +TEST_RES-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +TEST_RES-NEXT: Major Version: 0 +TEST_RES-NEXT: Minor Version: 0 +TEST_RES-NEXT: Characteristics: 0 +TEST_RES-NEXT: ] +TEST_RES-NEXT: ] +TEST_RES-NEXT: Name: (ID 12) [ +TEST_RES-NEXT: Table Offset: 0x138 +TEST_RES-NEXT: Number of String Entries: 0 +TEST_RES-NEXT: Number of ID Entries: 1 +TEST_RES-NEXT: Language: (ID 1033) [ +TEST_RES-NEXT: Entry Offset: 0x1B0 +TEST_RES-NEXT: Time/Date Stamp: 1970-01-01 00:00:00 (0x0) +TEST_RES-NEXT: Major Version: 0 +TEST_RES-NEXT: Minor Version: 0 +TEST_RES-NEXT: Characteristics: 0 +TEST_RES-NEXT: ] +TEST_RES-NEXT: ] +TEST_RES-NEXT: ] |