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| author | Dimitry Andric <dim@FreeBSD.org> | 2011-05-02 19:34:44 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2011-05-02 19:34:44 +0000 |
| commit | 6b943ff3a3f8617113ecbf611cf0f8957e4e19d2 (patch) | |
| tree | fc5f365fb9035b2d0c622bbf06c9bbe8627d7279 /test | |
| parent | d0e4e96dc17a6c1c6de3340842c80f0e187ba349 (diff) | |
| download | src-6b943ff3a3f8617113ecbf611cf0f8957e4e19d2.tar.gz src-6b943ff3a3f8617113ecbf611cf0f8957e4e19d2.zip | |
Vendor import of llvm trunk r130700:vendor/llvm/llvm-r130700
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=221337
svn path=/vendor/llvm/llvm-r130700/; revision=221338; tag=vendor/llvm/llvm-r130700
Diffstat (limited to 'test')
618 files changed, 15984 insertions, 5992 deletions
diff --git a/test/Analysis/BasicAA/intrinsics.ll b/test/Analysis/BasicAA/intrinsics.ll new file mode 100644 index 000000000000..59725cfded05 --- /dev/null +++ b/test/Analysis/BasicAA/intrinsics.ll @@ -0,0 +1,39 @@ +; RUN: opt -basicaa -gvn -S < %s | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" + +; BasicAA should prove that these calls don't interfere, since they are +; IntrArgReadMem and have noalias pointers. + +; CHECK: define <8 x i16> @test0(i8* noalias %p, i8* noalias %q, <8 x i16> %y) { +; CHECK-NEXT: entry: +; CHECK-NEXT: %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind +; CHECK-NEXT: call void @llvm.arm.neon.vst1.v8i16(i8* %q, <8 x i16> %y, i32 16) +; CHECK-NEXT: %c = add <8 x i16> %a, %a +define <8 x i16> @test0(i8* noalias %p, i8* noalias %q, <8 x i16> %y) { +entry: + %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind + call void @llvm.arm.neon.vst1.v8i16(i8* %q, <8 x i16> %y, i32 16) + %b = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind + %c = add <8 x i16> %a, %b + ret <8 x i16> %c +} + +; CHECK: define <8 x i16> @test1(i8* %p, <8 x i16> %y) { +; CHECK-NEXT: entry: +; CHECK-NEXT: %q = getelementptr i8* %p, i64 16 +; CHECK-NEXT: %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind +; CHECK-NEXT: call void @llvm.arm.neon.vst1.v8i16(i8* %q, <8 x i16> %y, i32 16) +; CHECK-NEXT: %c = add <8 x i16> %a, %a +define <8 x i16> @test1(i8* %p, <8 x i16> %y) { +entry: + %q = getelementptr i8* %p, i64 16 + %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind + call void @llvm.arm.neon.vst1.v8i16(i8* %q, <8 x i16> %y, i32 16) + %b = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind + %c = add <8 x i16> %a, %b + ret <8 x i16> %c +} + +declare <8 x i16> @llvm.arm.neon.vld1.v8i16(i8*, i32) nounwind readonly +declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>, i32) nounwind diff --git a/test/Analysis/BasicAA/store-promote.ll b/test/Analysis/BasicAA/store-promote.ll index 33d0f3a5449b..0db805c3e21e 100644 --- a/test/Analysis/BasicAA/store-promote.ll +++ b/test/Analysis/BasicAA/store-promote.ll @@ -24,7 +24,7 @@ Out: ; preds = %Loop ; The Loop block should be empty after the load/store are promoted. ; CHECK: @test1 -; CHECK: load i32* @B +; CHECK: load i32* @A ; CHECK: Loop: ; CHECK-NEXT: br i1 %c, label %Out, label %Loop ; CHECK: Out: diff --git a/test/Analysis/PostDominators/2006-09-26-PostDominanceFrontier.ll b/test/Analysis/PostDominators/2006-09-26-PostDominanceFrontier.ll deleted file mode 100644 index b73b7f03f7e7..000000000000 --- a/test/Analysis/PostDominators/2006-09-26-PostDominanceFrontier.ll +++ /dev/null @@ -1,97 +0,0 @@ -; RUN: opt < %s -analyze -postdomfrontier \ -; RUN: -disable-verify -; ModuleID = '2006-09-26-PostDominanceFrontier.bc' -target datalayout = "e-p:64:64" -target triple = "alphaev67-unknown-linux-gnu" - %struct.FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct.FILE*, i32, i32, i64, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i32, [44 x i8] } - %struct._IO_marker = type { %struct._IO_marker*, %struct.FILE*, i32 } -@TOP = external global i64* ; <i64**> [#uses=1] -@BOT = external global i64* ; <i64**> [#uses=1] -@str = external global [2 x i8] ; <[2 x i8]*> [#uses=0] - -declare void @fopen() - -define void @main(i8** %argv) { -entry: - %netSelect.i507 = alloca i64, align 8 ; <i64*> [#uses=0] - %topStart.i = alloca i64, align 8 ; <i64*> [#uses=0] - %topEnd.i = alloca i64, align 8 ; <i64*> [#uses=0] - %botStart.i = alloca i64, align 8 ; <i64*> [#uses=0] - %botEnd.i = alloca i64, align 8 ; <i64*> [#uses=0] - %c1.i154 = alloca i32, align 4 ; <i32*> [#uses=0] - %b1.i155 = alloca i32, align 4 ; <i32*> [#uses=0] - %t1.i156 = alloca i32, align 4 ; <i32*> [#uses=0] - %c1.i = alloca i32, align 4 ; <i32*> [#uses=0] - %b1.i = alloca i32, align 4 ; <i32*> [#uses=0] - %t1.i = alloca i32, align 4 ; <i32*> [#uses=0] - %netSelect.i5 = alloca i64, align 8 ; <i64*> [#uses=0] - %netSelect.i = alloca i64, align 8 ; <i64*> [#uses=0] - %tmp2.i = getelementptr i8** %argv, i32 1 ; <i8**> [#uses=1] - %tmp3.i4 = load i8** %tmp2.i ; <i8*> [#uses=0] - call void @fopen( ) - br i1 false, label %DimensionChannel.exit, label %bb.backedge.i - -bb.backedge.i: ; preds = %entry - ret void - -DimensionChannel.exit: ; preds = %entry - %tmp13.i137 = malloc i64, i32 0 ; <i64*> [#uses=1] - %tmp610.i = malloc i64, i32 0 ; <i64*> [#uses=1] - br label %cond_true.i143 - -cond_true.i143: ; preds = %cond_true.i143, %DimensionChannel.exit - %tmp9.i140 = getelementptr i64* %tmp13.i137, i64 0 ; <i64*> [#uses=0] - %tmp12.i = getelementptr i64* %tmp610.i, i64 0 ; <i64*> [#uses=0] - br i1 false, label %bb18.i144, label %cond_true.i143 - -bb18.i144: ; preds = %cond_true.i143 - call void @fopen( ) - %tmp76.i105 = malloc i64, i32 0 ; <i64*> [#uses=3] - %tmp674.i = malloc i64, i32 0 ; <i64*> [#uses=2] - %tmp1072.i = malloc i64, i32 0 ; <i64*> [#uses=2] - %tmp1470.i = malloc i64, i32 0 ; <i64*> [#uses=1] - br label %cond_true.i114 - -cond_true.i114: ; preds = %cond_true.i114, %bb18.i144 - %tmp17.i108 = getelementptr i64* %tmp76.i105, i64 0 ; <i64*> [#uses=0] - %tmp20.i = getelementptr i64* %tmp674.i, i64 0 ; <i64*> [#uses=0] - %tmp23.i111 = getelementptr i64* %tmp1470.i, i64 0 ; <i64*> [#uses=0] - br i1 false, label %cond_true40.i, label %cond_true.i114 - -cond_true40.i: ; preds = %cond_true40.i, %cond_true.i114 - %tmp33.i115 = getelementptr i64* %tmp1072.i, i64 0 ; <i64*> [#uses=0] - br i1 false, label %bb142.i, label %cond_true40.i - -cond_next54.i: ; preds = %cond_true76.i - %tmp57.i = getelementptr i64* %tmp55.i, i64 0 ; <i64*> [#uses=0] - br i1 false, label %bb64.i, label %bb69.i - -bb64.i: ; preds = %cond_true76.i, %cond_next54.i - %tmp67.i117 = getelementptr i64* %tmp76.i105, i64 0 ; <i64*> [#uses=0] - br i1 false, label %bb114.i, label %cond_true111.i - -bb69.i: ; preds = %cond_next54.i - br i1 false, label %bb79.i, label %cond_true76.i - -cond_true76.i: ; preds = %bb142.i, %bb69.i - %tmp48.i = getelementptr i64* %tmp46.i, i64 0 ; <i64*> [#uses=0] - br i1 false, label %bb64.i, label %cond_next54.i - -bb79.i: ; preds = %bb69.i - br i1 false, label %bb114.i, label %cond_true111.i - -cond_true111.i: ; preds = %bb79.i, %bb64.i - %tmp84.i127 = getelementptr i64* %tmp46.i, i64 0 ; <i64*> [#uses=0] - ret void - -bb114.i: ; preds = %bb142.i, %bb79.i, %bb64.i - %tmp117.i = getelementptr i64* %tmp76.i105, i64 0 ; <i64*> [#uses=0] - %tmp132.i131 = getelementptr i64* %tmp674.i, i64 0 ; <i64*> [#uses=0] - %tmp122.i = getelementptr i64* %tmp1072.i, i64 0 ; <i64*> [#uses=0] - ret void - -bb142.i: ; preds = %cond_true40.i - %tmp46.i = load i64** @BOT ; <i64*> [#uses=2] - %tmp55.i = load i64** @TOP ; <i64*> [#uses=1] - br i1 false, label %bb114.i, label %cond_true76.i -} diff --git a/test/Analysis/PostDominators/2007-04-17-PostDominanceFrontier.ll b/test/Analysis/PostDominators/2007-04-17-PostDominanceFrontier.ll deleted file mode 100644 index 1ec056bc34e0..000000000000 --- a/test/Analysis/PostDominators/2007-04-17-PostDominanceFrontier.ll +++ /dev/null @@ -1,692 +0,0 @@ -; RUN: opt < %s -postdomfrontier -disable-output - -define void @SManager() { -entry: - br label %bb.outer - -bb.outer: ; preds = %bb193, %entry - br label %bb.outer156 - -bb.loopexit: ; preds = %bb442 - br label %bb.outer156 - -bb.outer156: ; preds = %bb.loopexit, %bb.outer - br label %bb - -bb: ; preds = %bb.backedge, %bb.outer156 - br i1 false, label %cond_true, label %bb.cond_next_crit_edge - -bb.cond_next_crit_edge: ; preds = %bb - br label %cond_next - -cond_true: ; preds = %bb - br label %cond_next - -cond_next: ; preds = %cond_true, %bb.cond_next_crit_edge - br i1 false, label %cond_next.bb.backedge_crit_edge, label %cond_next107 - -cond_next.bb.backedge_crit_edge: ; preds = %cond_next - br label %bb.backedge - -bb.backedge: ; preds = %cond_true112.bb.backedge_crit_edge, %cond_next.bb.backedge_crit_edge - br label %bb - -cond_next107: ; preds = %cond_next - br i1 false, label %cond_true112, label %cond_next197 - -cond_true112: ; preds = %cond_next107 - br i1 false, label %cond_true118, label %cond_true112.bb.backedge_crit_edge - -cond_true112.bb.backedge_crit_edge: ; preds = %cond_true112 - br label %bb.backedge - -cond_true118: ; preds = %cond_true112 - br i1 false, label %bb123.preheader, label %cond_true118.bb148_crit_edge - -cond_true118.bb148_crit_edge: ; preds = %cond_true118 - br label %bb148 - -bb123.preheader: ; preds = %cond_true118 - br label %bb123 - -bb123: ; preds = %bb142.bb123_crit_edge, %bb123.preheader - br i1 false, label %bb123.bb142_crit_edge, label %cond_next.i57 - -bb123.bb142_crit_edge: ; preds = %bb123 - br label %bb142 - -cond_next.i57: ; preds = %bb123 - br i1 false, label %cond_true135, label %cond_next.i57.bb142_crit_edge - -cond_next.i57.bb142_crit_edge: ; preds = %cond_next.i57 - br label %bb142 - -cond_true135: ; preds = %cond_next.i57 - br label %bb142 - -bb142: ; preds = %cond_true135, %cond_next.i57.bb142_crit_edge, %bb123.bb142_crit_edge - br i1 false, label %bb148.loopexit, label %bb142.bb123_crit_edge - -bb142.bb123_crit_edge: ; preds = %bb142 - br label %bb123 - -bb148.loopexit: ; preds = %bb142 - br label %bb148 - -bb148: ; preds = %bb148.loopexit, %cond_true118.bb148_crit_edge - br i1 false, label %bb151.preheader, label %bb148.bb177_crit_edge - -bb148.bb177_crit_edge: ; preds = %bb148 - br label %bb177 - -bb151.preheader: ; preds = %bb148 - br label %bb151 - -bb151: ; preds = %bb171.bb151_crit_edge, %bb151.preheader - br i1 false, label %bb151.bb171_crit_edge, label %cond_next.i49 - -bb151.bb171_crit_edge: ; preds = %bb151 - br label %bb171 - -cond_next.i49: ; preds = %bb151 - br i1 false, label %cond_true164, label %cond_next.i49.bb171_crit_edge - -cond_next.i49.bb171_crit_edge: ; preds = %cond_next.i49 - br label %bb171 - -cond_true164: ; preds = %cond_next.i49 - br label %bb171 - -bb171: ; preds = %cond_true164, %cond_next.i49.bb171_crit_edge, %bb151.bb171_crit_edge - br i1 false, label %bb177.loopexit, label %bb171.bb151_crit_edge - -bb171.bb151_crit_edge: ; preds = %bb171 - br label %bb151 - -bb177.loopexit: ; preds = %bb171 - br label %bb177 - -bb177: ; preds = %bb177.loopexit, %bb148.bb177_crit_edge - br i1 false, label %bb180.preheader, label %bb177.bb193_crit_edge - -bb177.bb193_crit_edge: ; preds = %bb177 - br label %bb193 - -bb180.preheader: ; preds = %bb177 - br label %bb180 - -bb180: ; preds = %bb180.bb180_crit_edge, %bb180.preheader - br i1 false, label %bb193.loopexit, label %bb180.bb180_crit_edge - -bb180.bb180_crit_edge: ; preds = %bb180 - br label %bb180 - -bb193.loopexit: ; preds = %bb180 - br label %bb193 - -bb193: ; preds = %bb193.loopexit, %bb177.bb193_crit_edge - br label %bb.outer - -cond_next197: ; preds = %cond_next107 - br i1 false, label %cond_next210, label %cond_true205 - -cond_true205: ; preds = %cond_next197 - br i1 false, label %cond_true205.bb213_crit_edge, label %cond_true205.bb299_crit_edge - -cond_true205.bb299_crit_edge: ; preds = %cond_true205 - br label %bb299 - -cond_true205.bb213_crit_edge: ; preds = %cond_true205 - br label %bb213 - -cond_next210: ; preds = %cond_next197 - br label %bb293 - -bb213: ; preds = %bb293.bb213_crit_edge, %cond_true205.bb213_crit_edge - br i1 false, label %bb213.cond_next290_crit_edge, label %cond_true248 - -bb213.cond_next290_crit_edge: ; preds = %bb213 - br label %cond_next290 - -cond_true248: ; preds = %bb213 - br i1 false, label %cond_true248.cond_next290_crit_edge, label %cond_true255 - -cond_true248.cond_next290_crit_edge: ; preds = %cond_true248 - br label %cond_next290 - -cond_true255: ; preds = %cond_true248 - br i1 false, label %cond_true266, label %cond_true255.cond_next271_crit_edge - -cond_true255.cond_next271_crit_edge: ; preds = %cond_true255 - br label %cond_next271 - -cond_true266: ; preds = %cond_true255 - br label %cond_next271 - -cond_next271: ; preds = %cond_true266, %cond_true255.cond_next271_crit_edge - br label %cond_next290 - -cond_next290: ; preds = %cond_next271, %cond_true248.cond_next290_crit_edge, %bb213.cond_next290_crit_edge - br label %bb293 - -bb293: ; preds = %cond_next290, %cond_next210 - br i1 false, label %bb293.bb213_crit_edge, label %bb293.bb299_crit_edge - -bb293.bb299_crit_edge: ; preds = %bb293 - br label %bb299 - -bb293.bb213_crit_edge: ; preds = %bb293 - br label %bb213 - -bb299: ; preds = %bb293.bb299_crit_edge, %cond_true205.bb299_crit_edge - br i1 false, label %bb302.preheader, label %bb299.bb390_crit_edge - -bb299.bb390_crit_edge: ; preds = %bb299 - br label %bb390 - -bb302.preheader: ; preds = %bb299 - br label %bb302 - -bb302: ; preds = %bb384.bb302_crit_edge, %bb302.preheader - br i1 false, label %bb302.bb384_crit_edge, label %cond_true339 - -bb302.bb384_crit_edge: ; preds = %bb302 - br label %bb384 - -cond_true339: ; preds = %bb302 - br i1 false, label %cond_true339.bb384_crit_edge, label %cond_true346 - -cond_true339.bb384_crit_edge: ; preds = %cond_true339 - br label %bb384 - -cond_true346: ; preds = %cond_true339 - br i1 false, label %cond_true357, label %cond_true346.cond_next361_crit_edge - -cond_true346.cond_next361_crit_edge: ; preds = %cond_true346 - br label %cond_next361 - -cond_true357: ; preds = %cond_true346 - br label %cond_next361 - -cond_next361: ; preds = %cond_true357, %cond_true346.cond_next361_crit_edge - br label %bb384 - -bb384: ; preds = %cond_next361, %cond_true339.bb384_crit_edge, %bb302.bb384_crit_edge - br i1 false, label %bb390.loopexit, label %bb384.bb302_crit_edge - -bb384.bb302_crit_edge: ; preds = %bb384 - br label %bb302 - -bb390.loopexit: ; preds = %bb384 - br label %bb390 - -bb390: ; preds = %bb390.loopexit, %bb299.bb390_crit_edge - br i1 false, label %bb391.preheader, label %bb390.bb442.preheader_crit_edge - -bb390.bb442.preheader_crit_edge: ; preds = %bb390 - br label %bb442.preheader - -bb391.preheader: ; preds = %bb390 - br label %bb391 - -bb391: ; preds = %bb413.bb391_crit_edge, %bb391.preheader - br i1 false, label %bb391.bb413_crit_edge, label %cond_next404 - -bb391.bb413_crit_edge: ; preds = %bb391 - br label %bb413 - -cond_next404: ; preds = %bb391 - br i1 false, label %cond_next404.HWrite.exit_crit_edge, label %cond_next.i13 - -cond_next404.HWrite.exit_crit_edge: ; preds = %cond_next404 - br label %HWrite.exit - -cond_next.i13: ; preds = %cond_next404 - br i1 false, label %cond_next.i13.cond_next13.i_crit_edge, label %cond_true12.i - -cond_next.i13.cond_next13.i_crit_edge: ; preds = %cond_next.i13 - br label %cond_next13.i - -cond_true12.i: ; preds = %cond_next.i13 - br label %cond_next13.i - -cond_next13.i: ; preds = %cond_true12.i, %cond_next.i13.cond_next13.i_crit_edge - br i1 false, label %cond_next13.i.bb.i22_crit_edge, label %cond_next43.i - -cond_next13.i.bb.i22_crit_edge: ; preds = %cond_next13.i - br label %bb.i22 - -cond_next43.i: ; preds = %cond_next13.i - br i1 false, label %cond_next43.i.bb.i22_crit_edge, label %bb60.i - -cond_next43.i.bb.i22_crit_edge: ; preds = %cond_next43.i - br label %bb.i22 - -bb.i22: ; preds = %cond_next43.i.bb.i22_crit_edge, %cond_next13.i.bb.i22_crit_edge - br label %bb413 - -bb60.i: ; preds = %cond_next43.i - br i1 false, label %bb60.i.HWrite.exit_crit_edge, label %cond_true81.i - -bb60.i.HWrite.exit_crit_edge: ; preds = %bb60.i - br label %HWrite.exit - -cond_true81.i: ; preds = %bb60.i - br label %bb413 - -HWrite.exit: ; preds = %bb60.i.HWrite.exit_crit_edge, %cond_next404.HWrite.exit_crit_edge - br label %bb413 - -bb413: ; preds = %HWrite.exit, %cond_true81.i, %bb.i22, %bb391.bb413_crit_edge - br i1 false, label %bb442.preheader.loopexit, label %bb413.bb391_crit_edge - -bb413.bb391_crit_edge: ; preds = %bb413 - br label %bb391 - -bb442.preheader.loopexit: ; preds = %bb413 - br label %bb442.preheader - -bb442.preheader: ; preds = %bb442.preheader.loopexit, %bb390.bb442.preheader_crit_edge - br label %bb442.outer - -bb420: ; preds = %bb442 - br i1 false, label %bb439.loopexit, label %cond_next433 - -cond_next433: ; preds = %bb420 - br i1 false, label %cond_next433.HRead.exit.loopexit_crit_edge, label %cond_next.i - -cond_next433.HRead.exit.loopexit_crit_edge: ; preds = %cond_next433 - br label %HRead.exit.loopexit - -cond_next.i: ; preds = %cond_next433 - br i1 false, label %cond_true9.i, label %cond_false223.i - -cond_true9.i: ; preds = %cond_next.i - switch i32 0, label %cond_false.i [ - i32 1, label %cond_true9.i.cond_true15.i_crit_edge - i32 5, label %cond_true9.i.cond_true15.i_crit_edge9 - ] - -cond_true9.i.cond_true15.i_crit_edge9: ; preds = %cond_true9.i - br label %cond_true15.i - -cond_true9.i.cond_true15.i_crit_edge: ; preds = %cond_true9.i - br label %cond_true15.i - -cond_true15.i: ; preds = %cond_true9.i.cond_true15.i_crit_edge, %cond_true9.i.cond_true15.i_crit_edge9 - br i1 false, label %cond_true15.i.cond_true44.i_crit_edge, label %cond_true15.i.cond_false49.i_crit_edge - -cond_true15.i.cond_false49.i_crit_edge: ; preds = %cond_true15.i - br label %cond_false49.i - -cond_true15.i.cond_true44.i_crit_edge: ; preds = %cond_true15.i - br label %cond_true44.i - -cond_false.i: ; preds = %cond_true9.i - br i1 false, label %cond_false.i.cond_next39.i_crit_edge, label %cond_true30.i - -cond_false.i.cond_next39.i_crit_edge: ; preds = %cond_false.i - br label %cond_next39.i - -cond_true30.i: ; preds = %cond_false.i - br label %cond_next39.i - -cond_next39.i: ; preds = %cond_true30.i, %cond_false.i.cond_next39.i_crit_edge - br i1 false, label %cond_next39.i.cond_true44.i_crit_edge, label %cond_next39.i.cond_false49.i_crit_edge - -cond_next39.i.cond_false49.i_crit_edge: ; preds = %cond_next39.i - br label %cond_false49.i - -cond_next39.i.cond_true44.i_crit_edge: ; preds = %cond_next39.i - br label %cond_true44.i - -cond_true44.i: ; preds = %cond_next39.i.cond_true44.i_crit_edge, %cond_true15.i.cond_true44.i_crit_edge - br i1 false, label %cond_true44.i.cond_next70.i_crit_edge, label %cond_true44.i.cond_true61.i_crit_edge - -cond_true44.i.cond_true61.i_crit_edge: ; preds = %cond_true44.i - br label %cond_true61.i - -cond_true44.i.cond_next70.i_crit_edge: ; preds = %cond_true44.i - br label %cond_next70.i - -cond_false49.i: ; preds = %cond_next39.i.cond_false49.i_crit_edge, %cond_true15.i.cond_false49.i_crit_edge - br i1 false, label %cond_false49.i.cond_next70.i_crit_edge, label %cond_false49.i.cond_true61.i_crit_edge - -cond_false49.i.cond_true61.i_crit_edge: ; preds = %cond_false49.i - br label %cond_true61.i - -cond_false49.i.cond_next70.i_crit_edge: ; preds = %cond_false49.i - br label %cond_next70.i - -cond_true61.i: ; preds = %cond_false49.i.cond_true61.i_crit_edge, %cond_true44.i.cond_true61.i_crit_edge - br i1 false, label %cond_true61.i.cond_next70.i_crit_edge, label %cond_true67.i - -cond_true61.i.cond_next70.i_crit_edge: ; preds = %cond_true61.i - br label %cond_next70.i - -cond_true67.i: ; preds = %cond_true61.i - br label %cond_next70.i - -cond_next70.i: ; preds = %cond_true67.i, %cond_true61.i.cond_next70.i_crit_edge, %cond_false49.i.cond_next70.i_crit_edge, %cond_true44.i.cond_next70.i_crit_edge - br i1 false, label %cond_true77.i, label %cond_next81.i - -cond_true77.i: ; preds = %cond_next70.i - br label %bb442.outer.backedge - -cond_next81.i: ; preds = %cond_next70.i - br i1 false, label %cond_true87.i, label %cond_false94.i - -cond_true87.i: ; preds = %cond_next81.i - br i1 false, label %cond_true87.i.cond_true130.i_crit_edge, label %cond_true87.i.cond_next135.i_crit_edge - -cond_true87.i.cond_next135.i_crit_edge: ; preds = %cond_true87.i - br label %cond_next135.i - -cond_true87.i.cond_true130.i_crit_edge: ; preds = %cond_true87.i - br label %cond_true130.i - -cond_false94.i: ; preds = %cond_next81.i - switch i32 0, label %cond_false94.i.cond_next125.i_crit_edge [ - i32 1, label %cond_false94.i.cond_true100.i_crit_edge - i32 5, label %cond_false94.i.cond_true100.i_crit_edge10 - ] - -cond_false94.i.cond_true100.i_crit_edge10: ; preds = %cond_false94.i - br label %cond_true100.i - -cond_false94.i.cond_true100.i_crit_edge: ; preds = %cond_false94.i - br label %cond_true100.i - -cond_false94.i.cond_next125.i_crit_edge: ; preds = %cond_false94.i - br label %cond_next125.i - -cond_true100.i: ; preds = %cond_false94.i.cond_true100.i_crit_edge, %cond_false94.i.cond_true100.i_crit_edge10 - br i1 false, label %cond_true107.i, label %cond_true100.i.cond_next109.i_crit_edge - -cond_true100.i.cond_next109.i_crit_edge: ; preds = %cond_true100.i - br label %cond_next109.i - -cond_true107.i: ; preds = %cond_true100.i - br label %cond_next109.i - -cond_next109.i: ; preds = %cond_true107.i, %cond_true100.i.cond_next109.i_crit_edge - br i1 false, label %cond_next109.i.cond_next125.i_crit_edge, label %cond_true116.i - -cond_next109.i.cond_next125.i_crit_edge: ; preds = %cond_next109.i - br label %cond_next125.i - -cond_true116.i: ; preds = %cond_next109.i - br label %cond_next125.i - -cond_next125.i: ; preds = %cond_true116.i, %cond_next109.i.cond_next125.i_crit_edge, %cond_false94.i.cond_next125.i_crit_edge - br i1 false, label %cond_next125.i.cond_true130.i_crit_edge, label %cond_next125.i.cond_next135.i_crit_edge - -cond_next125.i.cond_next135.i_crit_edge: ; preds = %cond_next125.i - br label %cond_next135.i - -cond_next125.i.cond_true130.i_crit_edge: ; preds = %cond_next125.i - br label %cond_true130.i - -cond_true130.i: ; preds = %cond_next125.i.cond_true130.i_crit_edge, %cond_true87.i.cond_true130.i_crit_edge - br label %cond_next135.i - -cond_next135.i: ; preds = %cond_true130.i, %cond_next125.i.cond_next135.i_crit_edge, %cond_true87.i.cond_next135.i_crit_edge - br i1 false, label %cond_true142.i, label %cond_next135.i.cond_next149.i_crit_edge - -cond_next135.i.cond_next149.i_crit_edge: ; preds = %cond_next135.i - br label %cond_next149.i - -cond_true142.i: ; preds = %cond_next135.i - br label %cond_next149.i - -cond_next149.i: ; preds = %cond_true142.i, %cond_next135.i.cond_next149.i_crit_edge - br i1 false, label %cond_true156.i, label %cond_next149.i.cond_next163.i_crit_edge - -cond_next149.i.cond_next163.i_crit_edge: ; preds = %cond_next149.i - br label %cond_next163.i - -cond_true156.i: ; preds = %cond_next149.i - br label %cond_next163.i - -cond_next163.i: ; preds = %cond_true156.i, %cond_next149.i.cond_next163.i_crit_edge - br i1 false, label %cond_true182.i, label %cond_next163.i.cond_next380.i_crit_edge - -cond_next163.i.cond_next380.i_crit_edge: ; preds = %cond_next163.i - br label %cond_next380.i - -cond_true182.i: ; preds = %cond_next163.i - br i1 false, label %cond_true182.i.cond_next380.i_crit_edge, label %cond_true196.i - -cond_true182.i.cond_next380.i_crit_edge: ; preds = %cond_true182.i - br label %cond_next380.i - -cond_true196.i: ; preds = %cond_true182.i - br i1 false, label %cond_true210.i, label %cond_true196.i.cond_next380.i_crit_edge - -cond_true196.i.cond_next380.i_crit_edge: ; preds = %cond_true196.i - br label %cond_next380.i - -cond_true210.i: ; preds = %cond_true196.i - br i1 false, label %cond_true216.i, label %cond_true210.i.cond_next380.i_crit_edge - -cond_true210.i.cond_next380.i_crit_edge: ; preds = %cond_true210.i - br label %cond_next380.i - -cond_true216.i: ; preds = %cond_true210.i - br label %cond_next380.i - -cond_false223.i: ; preds = %cond_next.i - br i1 false, label %cond_true229.i, label %cond_false355.i - -cond_true229.i: ; preds = %cond_false223.i - br i1 false, label %cond_true229.i.HRead.exit.loopexit_crit_edge, label %cond_next243.i - -cond_true229.i.HRead.exit.loopexit_crit_edge: ; preds = %cond_true229.i - br label %HRead.exit.loopexit - -cond_next243.i: ; preds = %cond_true229.i - br i1 false, label %cond_true248.i, label %cond_false255.i - -cond_true248.i: ; preds = %cond_next243.i - br label %cond_next260.i - -cond_false255.i: ; preds = %cond_next243.i - br label %cond_next260.i - -cond_next260.i: ; preds = %cond_false255.i, %cond_true248.i - br i1 false, label %cond_true267.i, label %cond_next273.i - -cond_true267.i: ; preds = %cond_next260.i - br label %bb442.backedge - -bb442.backedge: ; preds = %bb.i, %cond_true267.i - br label %bb442 - -cond_next273.i: ; preds = %cond_next260.i - br i1 false, label %cond_true281.i, label %cond_next273.i.cond_next288.i_crit_edge - -cond_next273.i.cond_next288.i_crit_edge: ; preds = %cond_next273.i - br label %cond_next288.i - -cond_true281.i: ; preds = %cond_next273.i - br label %cond_next288.i - -cond_next288.i: ; preds = %cond_true281.i, %cond_next273.i.cond_next288.i_crit_edge - br i1 false, label %cond_true295.i, label %cond_next288.i.cond_next302.i_crit_edge - -cond_next288.i.cond_next302.i_crit_edge: ; preds = %cond_next288.i - br label %cond_next302.i - -cond_true295.i: ; preds = %cond_next288.i - br label %cond_next302.i - -cond_next302.i: ; preds = %cond_true295.i, %cond_next288.i.cond_next302.i_crit_edge - br i1 false, label %cond_next302.i.cond_next380.i_crit_edge, label %cond_true328.i - -cond_next302.i.cond_next380.i_crit_edge: ; preds = %cond_next302.i - br label %cond_next380.i - -cond_true328.i: ; preds = %cond_next302.i - br i1 false, label %cond_true343.i, label %cond_true328.i.cond_next380.i_crit_edge - -cond_true328.i.cond_next380.i_crit_edge: ; preds = %cond_true328.i - br label %cond_next380.i - -cond_true343.i: ; preds = %cond_true328.i - br i1 false, label %cond_true349.i, label %cond_true343.i.cond_next380.i_crit_edge - -cond_true343.i.cond_next380.i_crit_edge: ; preds = %cond_true343.i - br label %cond_next380.i - -cond_true349.i: ; preds = %cond_true343.i - br label %cond_next380.i - -cond_false355.i: ; preds = %cond_false223.i - br i1 false, label %cond_false355.i.bb.i_crit_edge, label %cond_next363.i - -cond_false355.i.bb.i_crit_edge: ; preds = %cond_false355.i - br label %bb.i - -cond_next363.i: ; preds = %cond_false355.i - br i1 false, label %bb377.i, label %cond_next363.i.bb.i_crit_edge - -cond_next363.i.bb.i_crit_edge: ; preds = %cond_next363.i - br label %bb.i - -bb.i: ; preds = %cond_next363.i.bb.i_crit_edge, %cond_false355.i.bb.i_crit_edge - br label %bb442.backedge - -bb377.i: ; preds = %cond_next363.i - br label %cond_next380.i - -cond_next380.i: ; preds = %bb377.i, %cond_true349.i, %cond_true343.i.cond_next380.i_crit_edge, %cond_true328.i.cond_next380.i_crit_edge, %cond_next302.i.cond_next380.i_crit_edge, %cond_true216.i, %cond_true210.i.cond_next380.i_crit_edge, %cond_true196.i.cond_next380.i_crit_edge, %cond_true182.i.cond_next380.i_crit_edge, %cond_next163.i.cond_next380.i_crit_edge - br i1 false, label %cond_next380.i.HRead.exit_crit_edge, label %cond_true391.i - -cond_next380.i.HRead.exit_crit_edge: ; preds = %cond_next380.i - br label %HRead.exit - -cond_true391.i: ; preds = %cond_next380.i - br label %bb442.outer.backedge - -bb442.outer.backedge: ; preds = %bb439, %cond_true391.i, %cond_true77.i - br label %bb442.outer - -HRead.exit.loopexit: ; preds = %cond_true229.i.HRead.exit.loopexit_crit_edge, %cond_next433.HRead.exit.loopexit_crit_edge - br label %HRead.exit - -HRead.exit: ; preds = %HRead.exit.loopexit, %cond_next380.i.HRead.exit_crit_edge - br label %bb439 - -bb439.loopexit: ; preds = %bb420 - br label %bb439 - -bb439: ; preds = %bb439.loopexit, %HRead.exit - br label %bb442.outer.backedge - -bb442.outer: ; preds = %bb442.outer.backedge, %bb442.preheader - br label %bb442 - -bb442: ; preds = %bb442.outer, %bb442.backedge - br i1 false, label %bb420, label %bb.loopexit -} - -define void @Invalidate() { -entry: - br i1 false, label %cond_false, label %cond_true - -cond_true: ; preds = %entry - br i1 false, label %cond_true40, label %cond_true.cond_next_crit_edge - -cond_true.cond_next_crit_edge: ; preds = %cond_true - br label %cond_next - -cond_true40: ; preds = %cond_true - br label %cond_next - -cond_next: ; preds = %cond_true40, %cond_true.cond_next_crit_edge - br i1 false, label %cond_true68, label %cond_next.cond_next73_crit_edge - -cond_next.cond_next73_crit_edge: ; preds = %cond_next - br label %cond_next73 - -cond_true68: ; preds = %cond_next - br label %cond_next73 - -cond_next73: ; preds = %cond_true68, %cond_next.cond_next73_crit_edge - br i1 false, label %cond_true91, label %cond_next73.cond_next96_crit_edge - -cond_next73.cond_next96_crit_edge: ; preds = %cond_next73 - br label %cond_next96 - -cond_true91: ; preds = %cond_next73 - br label %cond_next96 - -cond_next96: ; preds = %cond_true91, %cond_next73.cond_next96_crit_edge - br i1 false, label %cond_next96.cond_next112_crit_edge, label %cond_true105 - -cond_next96.cond_next112_crit_edge: ; preds = %cond_next96 - br label %cond_next112 - -cond_true105: ; preds = %cond_next96 - br label %cond_next112 - -cond_next112: ; preds = %cond_true105, %cond_next96.cond_next112_crit_edge - br i1 false, label %cond_next112.cond_next127_crit_edge, label %cond_true119 - -cond_next112.cond_next127_crit_edge: ; preds = %cond_next112 - br label %cond_next127 - -cond_true119: ; preds = %cond_next112 - br label %cond_next127 - -cond_next127: ; preds = %cond_true119, %cond_next112.cond_next127_crit_edge - br i1 false, label %cond_next141, label %cond_true134 - -cond_true134: ; preds = %cond_next127 - br i1 false, label %cond_true134.bb161_crit_edge, label %cond_true134.bb_crit_edge - -cond_true134.bb_crit_edge: ; preds = %cond_true134 - br label %bb - -cond_true134.bb161_crit_edge: ; preds = %cond_true134 - br label %bb161 - -cond_next141: ; preds = %cond_next127 - br label %bb154 - -bb: ; preds = %bb154.bb_crit_edge, %cond_true134.bb_crit_edge - br label %bb154 - -bb154: ; preds = %bb, %cond_next141 - br i1 false, label %bb154.bb161_crit_edge, label %bb154.bb_crit_edge - -bb154.bb_crit_edge: ; preds = %bb154 - br label %bb - -bb154.bb161_crit_edge: ; preds = %bb154 - br label %bb161 - -bb161: ; preds = %bb154.bb161_crit_edge, %cond_true134.bb161_crit_edge - br i1 false, label %bb161.cond_next201_crit_edge, label %cond_true198 - -bb161.cond_next201_crit_edge: ; preds = %bb161 - br label %cond_next201 - -cond_true198: ; preds = %bb161 - br label %cond_next201 - -cond_next201: ; preds = %cond_true198, %bb161.cond_next201_crit_edge - br i1 false, label %cond_next212, label %cond_true206 - -cond_true206: ; preds = %cond_next201 - br label %UnifiedReturnBlock - -cond_false: ; preds = %entry - br label %UnifiedReturnBlock - -cond_next212: ; preds = %cond_next201 - br label %UnifiedReturnBlock - -UnifiedReturnBlock: ; preds = %cond_next212, %cond_false, %cond_true206 - ret void -} diff --git a/test/Analysis/PostDominators/2007-04-20-PostDom-Reset.ll b/test/Analysis/PostDominators/2007-04-20-PostDom-Reset.ll deleted file mode 100644 index 767e5db94ce8..000000000000 --- a/test/Analysis/PostDominators/2007-04-20-PostDom-Reset.ll +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: opt < %s -postdomfrontier -disable-output - -define void @args_out_of_range() { -entry: - br label %bb - -bb: ; preds = %bb, %entry - br label %bb -} - -define void @args_out_of_range_3() { -entry: - br label %bb - -bb: ; preds = %bb, %entry - br label %bb -} - -define void @Feq() { -entry: - br i1 false, label %cond_true, label %cond_next - -cond_true: ; preds = %entry - unreachable - -cond_next: ; preds = %entry - unreachable -} diff --git a/test/Analysis/RegionInfo/next.ll b/test/Analysis/RegionInfo/next.ll index d986387099c3..377a84d389c1 100644 --- a/test/Analysis/RegionInfo/next.ll +++ b/test/Analysis/RegionInfo/next.ll @@ -32,8 +32,8 @@ __label_000020: ; preds = %__label_002001, %bb ; CHECK-NOT: => ; CHECK: [0] entry => <Function Return> ; CHECK-NEXT: [1] __label_002001.outer => __label_000020 -; CHECK-NEXT; [2] bb197 => bb229 -; CHECK-NEXT; [3] bb224 => bb229 +; CHECK-NEXT: [2] bb197 => bb229 +; CHECK-NEXT: [3] bb224 => bb229 ; STAT: 4 region - The # of regions ; STAT: 1 region - The # of simple regions diff --git a/test/Analysis/ScalarEvolution/2011-03-09-ExactNoMaxBECount.ll b/test/Analysis/ScalarEvolution/2011-03-09-ExactNoMaxBECount.ll new file mode 100644 index 000000000000..9f17e27577c2 --- /dev/null +++ b/test/Analysis/ScalarEvolution/2011-03-09-ExactNoMaxBECount.ll @@ -0,0 +1,34 @@ +; RUN: opt -indvars %s +; PR9424: Attempt to use a SCEVCouldNotCompute object! +; The inner loop computes the Step and Start of the outer loop. +; Call that Vexit. The outer End value is max(2,Vexit), because +; the condition "icmp %4 < 2" does not guard the outer loop. +; SCEV knows that Vexit has range [2,4], so End == Vexit == Start. +; Now we have ExactBECount == 0. However, MinStart == 2 and MaxEnd == 4. +; Since the stride is variable and may wrap, we cannot compute +; MaxBECount. SCEV should override MaxBECount with ExactBECount. + +define void @bar() nounwind { +entry: + %. = select i1 undef, i32 2, i32 1 + br label %"5.preheader" + +"4": ; preds = %"5.preheader", %"4" + %0 = phi i32 [ 0, %"5.preheader" ], [ %1, %"4" ] + %1 = add nsw i32 %0, 1 + %2 = icmp sgt i32 %., %1 + br i1 %2, label %"4", label %"9" + +"9": ; preds = %"4" + %3 = add i32 %6, 1 + %4 = add i32 %3, %1 + %5 = icmp slt i32 %4, 2 + br i1 %5, label %"5.preheader", label %return + +"5.preheader": ; preds = %"9", %entry + %6 = phi i32 [ 0, %entry ], [ %4, %"9" ] + br label %"4" + +return: ; preds = %"9" + ret void +} diff --git a/test/Analysis/ScalarEvolution/2011-04-26-FoldAddRec.ll b/test/Analysis/ScalarEvolution/2011-04-26-FoldAddRec.ll new file mode 100644 index 000000000000..1600d5f05a18 --- /dev/null +++ b/test/Analysis/ScalarEvolution/2011-04-26-FoldAddRec.ll @@ -0,0 +1,33 @@ +; RUN: opt < %s -analyze -iv-users +; PR9633: Tests that SCEV handles the mul.i2 recurrence being folded to +; constant zero. + +define signext i8 @func_14(i8 signext %p_18) nounwind readnone ssp { +entry: + br label %for.inc + +for.inc: + %p_17.addr.012 = phi i32 [ 0, %entry ], [ %add, %for.inc ] + %add = add nsw i32 %p_17.addr.012, 1 + br i1 false, label %for.inc, label %for.cond + +for.cond: + %tobool.i = icmp ult i32 %add, 8192 + %shl.i = select i1 %tobool.i, i32 13, i32 0 + %shl.left.i = shl i32 %add, %shl.i + %conv.i4 = trunc i32 %shl.left.i to i8 + br i1 undef, label %for.inc9, label %if.then + +for.inc9: + %p_18.addr.011 = phi i8 [ %add12, %for.inc9 ], [ %p_18, %for.cond ] + %add12 = add i8 %p_18.addr.011, 1 + %mul.i2 = mul i8 %add12, %conv.i4 + %mul.i2.lobit = lshr i8 %mul.i2, 7 + %lor.ext.shr.i = select i1 undef, i8 %mul.i2.lobit, i8 %mul.i2 + %tobool = icmp eq i8 %lor.ext.shr.i, 0 + br i1 %tobool, label %for.inc9, label %if.then + +if.then: + ret i8 0 + +}
\ No newline at end of file diff --git a/test/Analysis/ScalarEvolution/nsw-offset.ll b/test/Analysis/ScalarEvolution/nsw-offset.ll index 4cd9a6de48c5..8969a5ad4ceb 100644 --- a/test/Analysis/ScalarEvolution/nsw-offset.ll +++ b/test/Analysis/ScalarEvolution/nsw-offset.ll @@ -19,11 +19,11 @@ bb: ; preds = %bb.nph, %bb1 %i.01 = phi i32 [ %16, %bb1 ], [ 0, %bb.nph ] ; <i32> [#uses=5] ; CHECK: %1 = sext i32 %i.01 to i64 -; CHECK: --> {0,+,2}<%bb> +; CHECK: --> {0,+,2}<nuw><nsw><%bb> %1 = sext i32 %i.01 to i64 ; <i64> [#uses=1] ; CHECK: %2 = getelementptr inbounds double* %d, i64 %1 -; CHECK: --> {%d,+,16}<%bb> +; CHECK: --> {%d,+,16}<nsw><%bb> %2 = getelementptr inbounds double* %d, i64 %1 ; <double*> [#uses=1] %3 = load double* %2, align 8 ; <double> [#uses=1] @@ -33,11 +33,11 @@ bb: ; preds = %bb.nph, %bb1 %7 = or i32 %i.01, 1 ; <i32> [#uses=1] ; CHECK: %8 = sext i32 %7 to i64 -; CHECK: --> {1,+,2}<%bb> +; CHECK: --> {1,+,2}<nuw><nsw><%bb> %8 = sext i32 %7 to i64 ; <i64> [#uses=1] ; CHECK: %9 = getelementptr inbounds double* %q, i64 %8 -; CHECK: {(8 + %q),+,16}<%bb> +; CHECK: {(8 + %q),+,16}<nsw><%bb> %9 = getelementptr inbounds double* %q, i64 %8 ; <double*> [#uses=1] ; Artificially repeat the above three instructions, this time using @@ -45,11 +45,11 @@ bb: ; preds = %bb.nph, %bb1 %t7 = add nsw i32 %i.01, 1 ; <i32> [#uses=1] ; CHECK: %t8 = sext i32 %t7 to i64 -; CHECK: --> {1,+,2}<%bb> +; CHECK: --> {1,+,2}<nuw><nsw><%bb> %t8 = sext i32 %t7 to i64 ; <i64> [#uses=1] ; CHECK: %t9 = getelementptr inbounds double* %q, i64 %t8 -; CHECK: {(8 + %q),+,16}<%bb> +; CHECK: {(8 + %q),+,16}<nsw><%bb> %t9 = getelementptr inbounds double* %q, i64 %t8 ; <double*> [#uses=1] %10 = load double* %9, align 8 ; <double> [#uses=1] diff --git a/test/Analysis/ScalarEvolution/nsw.ll b/test/Analysis/ScalarEvolution/nsw.ll index 9d8e2b62a9d2..da35a6cf7ae2 100644 --- a/test/Analysis/ScalarEvolution/nsw.ll +++ b/test/Analysis/ScalarEvolution/nsw.ll @@ -35,7 +35,7 @@ bb: ; preds = %bb1, %bb.nph bb1: ; preds = %bb %phitmp = sext i32 %tmp8 to i64 ; <i64> [#uses=1] ; CHECK: %phitmp -; CHECK-NEXT: --> {1,+,1}<%bb> +; CHECK-NEXT: --> {1,+,1}<nuw><nsw><%bb> %tmp9 = getelementptr double* %p, i64 %phitmp ; <double*> [#uses=1] ; CHECK: %tmp9 ; CHECK-NEXT: --> {(8 + %p),+,8}<%bb> @@ -62,11 +62,11 @@ for.body.lr.ph.i.i: ; preds = %entry for.body.i.i: ; preds = %for.body.i.i, %for.body.lr.ph.i.i %__first.addr.02.i.i = phi i32* [ %begin, %for.body.lr.ph.i.i ], [ %ptrincdec.i.i, %for.body.i.i ] ; CHECK: %__first.addr.02.i.i -; CHECK-NEXT: --> {%begin,+,4}<nsw><%for.body.i.i> +; CHECK-NEXT: --> {%begin,+,4}<nw><%for.body.i.i> store i32 0, i32* %__first.addr.02.i.i, align 4 %ptrincdec.i.i = getelementptr inbounds i32* %__first.addr.02.i.i, i64 1 ; CHECK: %ptrincdec.i.i -; CHECK-NEXT: --> {(4 + %begin),+,4}<nsw><%for.body.i.i> +; CHECK-NEXT: --> {(4 + %begin),+,4}<nw><%for.body.i.i> %cmp.i.i = icmp eq i32* %ptrincdec.i.i, %end br i1 %cmp.i.i, label %for.cond.for.end_crit_edge.i.i, label %for.body.i.i @@ -88,7 +88,7 @@ for.body.i.i: ; preds = %entry, %for.body.i. ; CHECK: %indvar.i.i ; CHECK: {0,+,1}<nuw><nsw><%for.body.i.i> %tmp = add nsw i64 %indvar.i.i, 1 -; CHECK: %tmp = +; CHECK: %tmp = ; CHECK: {1,+,1}<nuw><nsw><%for.body.i.i> %ptrincdec.i.i = getelementptr inbounds i32* %begin, i64 %tmp ; CHECK: %ptrincdec.i.i = @@ -99,8 +99,8 @@ for.body.i.i: ; preds = %entry, %for.body.i. store i32 0, i32* %__first.addr.08.i.i, align 4 %cmp.i.i = icmp eq i32* %ptrincdec.i.i, %end br i1 %cmp.i.i, label %_ZSt4fillIPiiEvT_S1_RKT0_.exit, label %for.body.i.i -; CHECK: Loop %for.body.i.i: Unpredictable backedge-taken count. -; CHECK: Loop %for.body.i.i: Unpredictable max backedge-taken count. +; CHECK: Loop %for.body.i.i: backedge-taken count is ((-4 + (-1 * %begin) + %end) /u 4) +; CHECK: Loop %for.body.i.i: max backedge-taken count is ((-4 + (-1 * %begin) + %end) /u 4) _ZSt4fillIPiiEvT_S1_RKT0_.exit: ; preds = %for.body.i.i, %entry ret void }
\ No newline at end of file diff --git a/test/Analysis/ScalarEvolution/sext-iv-0.ll b/test/Analysis/ScalarEvolution/sext-iv-0.ll index 2af794fbbc3e..d5d32689e17c 100644 --- a/test/Analysis/ScalarEvolution/sext-iv-0.ll +++ b/test/Analysis/ScalarEvolution/sext-iv-0.ll @@ -1,5 +1,4 @@ -; RUN: opt < %s -scalar-evolution -analyze \ -; RUN: | grep { --> \{-128,+,1\}<%bb1> Exits: 127} | count 5 +; RUN: opt < %s -scalar-evolution -analyze | FileCheck %s ; Convert (sext {-128,+,1}) to {sext(-128),+,sext(1)}, since the ; trip count is within range where this is safe. @@ -13,9 +12,17 @@ bb1.thread: bb1: ; preds = %bb1, %bb1.thread %i.0.reg2mem.0 = phi i64 [ -128, %bb1.thread ], [ %8, %bb1 ] ; <i64> [#uses=3] +; CHECK: %i.0.reg2mem.0 +; CHECK-NEXT: --> {-128,+,1}<%bb1> Exits: 127 %0 = trunc i64 %i.0.reg2mem.0 to i8 ; <i8> [#uses=1] +; CHECK: %0 +; CHECK-NEXT: --> {-128,+,1}<%bb1> Exits: 127 %1 = trunc i64 %i.0.reg2mem.0 to i9 ; <i8> [#uses=1] +; CHECK: %1 +; CHECK-NEXT: --> {-128,+,1}<%bb1> Exits: 127 %2 = sext i9 %1 to i64 ; <i64> [#uses=1] +; CHECK: %2 +; CHECK-NEXT: --> {-128,+,1}<nsw><%bb1> Exits: 127 %3 = getelementptr double* %x, i64 %2 ; <double*> [#uses=1] %4 = load double* %3, align 8 ; <double> [#uses=1] %5 = fmul double %4, 3.900000e+00 ; <double> [#uses=1] diff --git a/test/Analysis/TypeBasedAliasAnalysis/intrinsics.ll b/test/Analysis/TypeBasedAliasAnalysis/intrinsics.ll new file mode 100644 index 000000000000..8f080e2108bd --- /dev/null +++ b/test/Analysis/TypeBasedAliasAnalysis/intrinsics.ll @@ -0,0 +1,27 @@ +; RUN: opt -tbaa -basicaa -gvn -S < %s | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" + +; TBAA should prove that these calls don't interfere, since they are +; IntrArgReadMem and have TBAA metadata. + +; CHECK: define <8 x i16> @test0(i8* %p, i8* %q, <8 x i16> %y) { +; CHECK-NEXT: entry: +; CHECK-NEXT: %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind +; CHECK-NEXT: call void @llvm.arm.neon.vst1.v8i16(i8* %q, <8 x i16> %y, i32 16) +; CHECK-NEXT: %c = add <8 x i16> %a, %a +define <8 x i16> @test0(i8* %p, i8* %q, <8 x i16> %y) { +entry: + %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind, !tbaa !2 + call void @llvm.arm.neon.vst1.v8i16(i8* %q, <8 x i16> %y, i32 16), !tbaa !1 + %b = call <8 x i16> @llvm.arm.neon.vld1.v8i16(i8* %p, i32 16) nounwind, !tbaa !2 + %c = add <8 x i16> %a, %b + ret <8 x i16> %c +} + +declare <8 x i16> @llvm.arm.neon.vld1.v8i16(i8*, i32) nounwind readonly +declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>, i32) nounwind + +!0 = metadata !{metadata !"tbaa root", null} +!1 = metadata !{metadata !"A", metadata !0} +!2 = metadata !{metadata !"B", metadata !0} diff --git a/test/Assembler/AutoUpgradeIntrinsics.ll b/test/Assembler/AutoUpgradeIntrinsics.ll index 6752bd8281bd..e4e2d3a56e04 100644 --- a/test/Assembler/AutoUpgradeIntrinsics.ll +++ b/test/Assembler/AutoUpgradeIntrinsics.ll @@ -7,6 +7,8 @@ ; RUN: llvm-as < %s | llvm-dis | \ ; RUN: not grep {llvm\\.bswap\\.i\[0-9\]*\\.i\[0-9\]*} ; RUN: llvm-as < %s | llvm-dis | \ +; RUN: not grep {llvm\\.x86\\.sse2\\.loadu} +; RUN: llvm-as < %s | llvm-dis | \ ; RUN: grep {llvm\\.x86\\.mmx\\.ps} | grep {x86_mmx} | count 16 declare i32 @llvm.ctpop.i28(i28 %val) @@ -79,3 +81,13 @@ define void @sh64(<1 x i64> %A, <2 x i32> %B) { %r2 = call <1 x i64> @llvm.x86.mmx.psrl.q( <1 x i64> %A, <2 x i32> %B ) ; <<1 x i64>> [#uses=0] ret void } + +declare <4 x float> @llvm.x86.sse.loadu.ps(i8*) nounwind readnone +declare <16 x i8> @llvm.x86.sse2.loadu.dq(i8*) nounwind readnone +declare <2 x double> @llvm.x86.sse2.loadu.pd(double*) nounwind readnone +define void @test_loadu(i8* %a, double* %b) { + %v0 = call <4 x float> @llvm.x86.sse.loadu.ps(i8* %a) + %v1 = call <16 x i8> @llvm.x86.sse2.loadu.dq(i8* %a) + %v2 = call <2 x double> @llvm.x86.sse2.loadu.pd(double* %b) + ret void +} diff --git a/test/Assembler/aggregate-return-single-value.ll b/test/Assembler/aggregate-return-single-value.ll index 02fb59f8a0a4..04540b54af1f 100644 --- a/test/Assembler/aggregate-return-single-value.ll +++ b/test/Assembler/aggregate-return-single-value.ll @@ -1,14 +1,8 @@ ; RUN: llvm-as < %s | llvm-dis -define { i32 } @fooa() nounwind { - ret i32 0 -} define { i32 } @foob() nounwind { ret {i32}{ i32 0 } } -define [1 x i32] @fooc() nounwind { - ret i32 0 -} define [1 x i32] @food() nounwind { ret [1 x i32][ i32 0 ] } diff --git a/test/Assembler/comment.ll b/test/Assembler/comment.ll index fe23d26fbeb4..16362abc716f 100644 --- a/test/Assembler/comment.ll +++ b/test/Assembler/comment.ll @@ -7,7 +7,7 @@ ; BARE: } @B = external global i32 -; ANNOT: @B = external global i32 ; [#uses=0] +; ANNOT: @B = external global i32 ; [#uses=0 type=i32*] define <4 x i1> @foo(<4 x float> %a, <4 x float> %b) nounwind { entry: @@ -15,6 +15,5 @@ entry: ret <4 x i1> %cmp } -; ANNOT: %cmp = fcmp olt <4 x float> %a, %b ; [#uses=1] - +; ANNOT: %cmp = fcmp olt <4 x float> %a, %b ; [#uses=1 type=<4 x i1>] diff --git a/test/Bitcode/neon-intrinsics.ll b/test/Bitcode/neon-intrinsics.ll index 272cd424e2a2..feb2d74138d0 100644 --- a/test/Bitcode/neon-intrinsics.ll +++ b/test/Bitcode/neon-intrinsics.ll @@ -76,20 +76,13 @@ ; CHECK: zext <4 x i16> ; CHECK-NEXT: sub <4 x i32> -; vmull should be auto-upgraded to multiply with sext/zext -; (but vmullp should remain an intrinsic) +; vmull* intrinsics will remain intrinsics ; CHECK: vmulls8 -; CHECK-NOT: arm.neon.vmulls.v8i16 -; CHECK: sext <8 x i8> -; CHECK-NEXT: sext <8 x i8> -; CHECK-NEXT: mul <8 x i16> +; CHECK: arm.neon.vmulls.v8i16 ; CHECK: vmullu16 -; CHECK-NOT: arm.neon.vmullu.v4i32 -; CHECK: zext <4 x i16> -; CHECK-NEXT: zext <4 x i16> -; CHECK-NEXT: mul <4 x i32> +; CHECK: arm.neon.vmullu.v4i32 ; CHECK: vmullp8 ; CHECK: arm.neon.vmullp.v8i16 diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt index b696682c13fa..993b6e274443 100644 --- a/test/CMakeLists.txt +++ b/test/CMakeLists.txt @@ -37,14 +37,32 @@ if(PYTHONINTERP_FOUND) foreach(INC_DIR ${INC_DIRS}) set(IDIRS "${IDIRS} -I${INC_DIR}") endforeach() - string(REPLACE "<CMAKE_CXX_COMPILER>" "${CMAKE_CXX_COMPILER}" TEST_COMPILE_CXX_CMD ${CMAKE_CXX_COMPILE_OBJECT}) + + if( MSVC ) + # The compiler's path may contain white space. Wrap it: + string(REPLACE "<CMAKE_CXX_COMPILER>" "\\\"${CMAKE_CXX_COMPILER}\\\"" TEST_COMPILE_CXX_CMD ${CMAKE_CXX_COMPILE_OBJECT}) + # Eliminate continuation lines from NMake flow. PR9680 + string(REPLACE "@<<\n" " " TEST_COMPILE_CXX_CMD ${TEST_COMPILE_CXX_CMD}) + string(REPLACE "\n<<" " " TEST_COMPILE_CXX_CMD ${TEST_COMPILE_CXX_CMD}) + else() + string(REPLACE "<CMAKE_CXX_COMPILER>" "${CMAKE_CXX_COMPILER}" TEST_COMPILE_CXX_CMD ${CMAKE_CXX_COMPILE_OBJECT}) + endif() + string(REPLACE "<DEFINES>" "${DEFS}" TEST_COMPILE_CXX_CMD ${TEST_COMPILE_CXX_CMD}) string(REPLACE "<FLAGS>" "${CMAKE_CXX_FLAGS}" TEST_COMPILE_CXX_CMD ${TEST_COMPILE_CXX_CMD}) - string(REPLACE "-o" "" TEST_COMPILE_CXX_CMD ${TEST_COMPILE_CXX_CMD}) + if (MSVC) # PR9680 + # Eliminate MSVC equivalent of -o + string(REPLACE "/Fo<OBJECT>" "" TEST_COMPILE_CXX_CMD ${TEST_COMPILE_CXX_CMD}) + # Eliminate "how to rename program database" argument + string(REPLACE "/Fd<TARGET_PDB>" "" TEST_COMPILE_CXX_CMD ${TEST_COMPILE_CXX_CMD}) + else() + string(REPLACE "-o" "" TEST_COMPILE_CXX_CMD ${TEST_COMPILE_CXX_CMD}) + endif(MSVC) string(REGEX REPLACE "<[^>]+>" "" TEST_COMPILE_CXX_CMD ${TEST_COMPILE_CXX_CMD}) set(TEST_COMPILE_CXX_CMD "${TEST_COMPILE_CXX_CMD} ${IDIRS}") if(NOT MSVC) set(TEST_COMPILE_CXX_CMD "${TEST_COMPILE_CXX_CMD} -x c++") + # MSVC already has /TP to indicate a C++ source file endif() configure_file( ${CMAKE_CURRENT_SOURCE_DIR}/site.exp.in diff --git a/test/CodeGen/ARM/2009-10-27-double-align.ll b/test/CodeGen/ARM/2009-10-27-double-align.ll index c31b116c55b2..b37de9dbbdfd 100644 --- a/test/CodeGen/ARM/2009-10-27-double-align.ll +++ b/test/CodeGen/ARM/2009-10-27-double-align.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s +; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s +; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=basic | FileCheck %s @.str = private constant [1 x i8] zeroinitializer, align 1 diff --git a/test/CodeGen/ARM/2010-03-18-ldm-rtrn.ll b/test/CodeGen/ARM/2010-03-18-ldm-rtrn.ll index d9e1a1486a3c..fee86008ad71 100644 --- a/test/CodeGen/ARM/2010-03-18-ldm-rtrn.ll +++ b/test/CodeGen/ARM/2010-03-18-ldm-rtrn.ll @@ -6,7 +6,7 @@ define i32 @bar(i32 %a) nounwind { entry: %0 = tail call i32 @foo(i32 %a) nounwind ; <i32> [#uses=1] %1 = add nsw i32 %0, 3 ; <i32> [#uses=1] -; CHECK: ldmia sp!, {r11, pc} +; CHECK: pop {r11, pc} ; V4: pop ; V4-NEXT: mov pc, lr ret i32 %1 diff --git a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll index 5ad1c09eda4a..df9dbca313f2 100644 --- a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll +++ b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll @@ -7,13 +7,13 @@ define zeroext i8 @t(%struct.foo* %this) noreturn optsize { entry: ; ARM: t: -; ARM: str r0, [r1], r0 +; ARM: str r2, [r1], r0 ; THUMB: t: ; THUMB-NOT: str r0, [r1], r0 -; THUMB: str r0, [r1] +; THUMB: str r2, [r1] %0 = getelementptr inbounds %struct.foo* %this, i32 0, i32 1 ; <i64*> [#uses=1] - store i32 undef, i32* inttoptr (i32 8 to i32*), align 8 + store i32 0, i32* inttoptr (i32 8 to i32*), align 8 br i1 undef, label %bb.nph96, label %bb3 bb3: ; preds = %entry diff --git a/test/CodeGen/ARM/2010-08-04-StackVariable.ll b/test/CodeGen/ARM/2010-08-04-StackVariable.ll index f077d04803bd..25d38ed77425 100644 --- a/test/CodeGen/ARM/2010-08-04-StackVariable.ll +++ b/test/CodeGen/ARM/2010-08-04-StackVariable.ll @@ -1,5 +1,5 @@ -; RUN: llc -O0 -mtriple=arm-apple-darwin < %s | grep DW_OP_fbreg -; Use DW_OP_fbreg in variable's location expression if the variable is in a stack slot. +; RUN: llc -O0 -mtriple=arm-apple-darwin < %s | grep DW_OP_breg +; Use DW_OP_breg in variable's location expression if the variable is in a stack slot. %struct.SVal = type { i8*, i32 } diff --git a/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll b/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll index 163c9b030ec8..32d350e9c8b1 100644 --- a/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll +++ b/test/CodeGen/ARM/2010-10-25-ifcvt-ldm.ll @@ -4,9 +4,9 @@ ; was being treated as an instruction count. ; CHECK: push -; CHECK: ldmia -; CHECK: ldmia -; CHECK: ldmia +; CHECK: pop +; CHECK: pop +; CHECK: pop define i32 @test(i32 %x) { entry: diff --git a/test/CodeGen/ARM/2010-11-29-PrologueBug.ll b/test/CodeGen/ARM/2010-11-29-PrologueBug.ll index 8d7541feae94..e3c18cefd51d 100644 --- a/test/CodeGen/ARM/2010-11-29-PrologueBug.ll +++ b/test/CodeGen/ARM/2010-11-29-PrologueBug.ll @@ -10,7 +10,7 @@ entry: ; ARM: bl _foo ; ARM: bl _foo ; ARM: bl _foo -; ARM: ldmia sp!, {r7, pc} +; ARM: pop {r7, pc} ; THUMB2: t: ; THUMB2: push diff --git a/test/CodeGen/ARM/2010-12-13-reloc-pic.ll b/test/CodeGen/ARM/2010-12-13-reloc-pic.ll deleted file mode 100644 index d5aefbee197c..000000000000 --- a/test/CodeGen/ARM/2010-12-13-reloc-pic.ll +++ /dev/null @@ -1,100 +0,0 @@ -; RUN: llc %s -mtriple=armv7-linux-gnueabi -relocation-model=pic -filetype=obj -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=PIC01 %s - -;; FIXME: Reduce this test further, or even better, -;; redo as .s -> .o test once ARM AsmParser is working better - -; ModuleID = 'large2.pnacl.bc' -target triple = "armv7-none-linux-gnueabi" - -%struct._Bigint = type { %struct._Bigint*, i32, i32, i32, i32, [1 x i32] } -%struct.__FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, %struct._reent*, i8*, i32 (%struct._reent*, i8*, i8*, i32)*, i32 (%struct._reent*, i8*, i8*, i32)*, i32 (%struct._reent*, i8*, i32, i32)*, i32 (%struct._reent*, i8*)*, %struct.__sbuf, i8*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i32, %struct._flock_t, %struct._mbstate_t, i32 } -%struct.__sbuf = type { i8*, i32 } -%struct.__tm = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 } -%struct._atexit = type { %struct._atexit*, i32, [32 x void ()*], %struct._on_exit_args* } -%struct._flock_t = type { i32, i32, i32, i32, i32 } -%struct._glue = type { %struct._glue*, i32, %struct.__FILE* } -%struct._mbstate_t = type { i32, %union.anon } -%struct._misc_reent = type { i8*, %struct._mbstate_t, %struct._mbstate_t, %struct._mbstate_t, [8 x i8], i32, %struct._mbstate_t, %struct._mbstate_t, %struct._mbstate_t, %struct._mbstate_t, %struct._mbstate_t } -%struct._mprec = type { %struct._Bigint*, i32, %struct._Bigint*, %struct._Bigint** } -%struct._on_exit_args = type { [32 x i8*], [32 x i8*], i32, i32 } -%struct._rand48 = type { [3 x i16], [3 x i16], i16, i64 } -%struct._reent = type { %struct.__FILE*, %struct.__FILE*, %struct.__FILE*, i32, i32, i8*, i32, i32, i8*, %struct._mprec*, void (%struct._reent*)*, i32, i32, i8*, %struct._rand48*, %struct.__tm*, i8*, void (i32)**, %struct._atexit*, %struct._atexit, %struct._glue, %struct.__FILE*, %struct._misc_reent*, i8* } -%union.anon = type { i32 } - -@buf = constant [2 x i8] c"x\00", align 4 -@_impure_ptr = external thread_local global %struct._reent* -@.str = private constant [22 x i8] c"This should fault...\0A\00", align 4 -@.str1 = private constant [40 x i8] c"We're still running. This is not good.\0A\00", align 4 - -define i32 @main() nounwind { -entry: - %0 = load %struct._reent** @_impure_ptr, align 4 - %1 = getelementptr inbounds %struct._reent* %0, i32 0, i32 1 - %2 = load %struct.__FILE** %1, align 4 - %3 = bitcast %struct.__FILE* %2 to i8* - %4 = tail call i32 @fwrite(i8* getelementptr inbounds ([22 x i8]* @.str, i32 0, i32 0), i32 1, i32 21, i8* %3) nounwind - %5 = load %struct._reent** @_impure_ptr, align 4 - %6 = getelementptr inbounds %struct._reent* %5, i32 0, i32 1 - %7 = load %struct.__FILE** %6, align 4 - %8 = tail call i32 @fflush(%struct.__FILE* %7) nounwind - store i8 121, i8* getelementptr inbounds ([2 x i8]* @buf, i32 0, i32 0), align 4 - %9 = load %struct._reent** @_impure_ptr, align 4 - %10 = getelementptr inbounds %struct._reent* %9, i32 0, i32 1 - %11 = load %struct.__FILE** %10, align 4 - %12 = bitcast %struct.__FILE* %11 to i8* - %13 = tail call i32 @fwrite(i8* getelementptr inbounds ([40 x i8]* @.str1, i32 0, i32 0), i32 1, i32 39, i8* %12) nounwind - ret i32 1 -} - - -; PIC01: Relocation 0x00000000 -; PIC01-NEXT: 'r_offset', 0x0000001c -; PIC01-NEXT: 'r_sym' -; PIC01-NEXT: 'r_type', 0x0000001b - - -; PIC01: Relocation 0x00000001 -; PIC01-NEXT: 'r_offset', 0x00000038 -; PIC01-NEXT: 'r_sym' -; PIC01-NEXT: 'r_type', 0x0000001b - -; PIC01: Relocation 0x00000002 -; PIC01-NEXT: 'r_offset', 0x00000044 -; PIC01-NEXT: 'r_sym' -; PIC01-NEXT: 'r_type', 0x0000001b - -; PIC01: Relocation 0x00000003 -; PIC01-NEXT: 'r_offset', 0x00000070 -; PIC01-NEXT: 'r_sym' -; PIC01-NEXT: 'r_type', 0x0000001b - -; PIC01: Relocation 0x00000004 -; PIC01-NEXT: 'r_offset', 0x0000007c -; PIC01-NEXT: 'r_sym' -; PIC01-NEXT: 'r_type', 0x00000019 - - -; PIC01: Relocation 0x00000005 -; PIC01-NEXT: 'r_offset', 0x00000080 -; PIC01-NEXT: 'r_sym' -; PIC01-NEXT: 'r_type', 0x00000018 - -; PIC01: Relocation 0x00000006 -; PIC01-NEXT: 'r_offset', 0x00000084 -; PIC01-NEXT: 'r_sym' -; PIC01-NEXT: 'r_type', 0x00000068 - -; PIC01: Relocation 0x00000007 -; PIC01-NEXT: 'r_offset', 0x00000088 -; PIC01-NEXT: 'r_sym' -; PIC01-NEXT: 'r_type', 0x0000001a - -; PIC01: Relocation 0x00000008 -; PIC01-NEXT: 'r_offset', 0x0000008c -; PIC01-NEXT: 'r_sym' -; PIC01-NEXT: 'r_type', 0x00000018 - -declare i32 @fwrite(i8* nocapture, i32, i32, i8* nocapture) nounwind - -declare i32 @fflush(%struct.__FILE* nocapture) nounwind diff --git a/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll b/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll index eaa34e7960fb..69d4a1482299 100644 --- a/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll +++ b/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll @@ -10,12 +10,12 @@ @STRIDE = internal global i32 8 ; ASM: .type array00,%object @ @array00 -; ASM-NEXT: .lcomm array00,80 @ @array00 +; ASM-NEXT: .lcomm array00,80 ; ASM-NEXT: .type _MergedGlobals,%object @ @_MergedGlobals -; OBJ: Section 0x00000003 +; OBJ: Section 0x00000004 ; OBJ-NEXT: '.bss' ; OBJ: 'array00' @@ -24,7 +24,7 @@ ; OBJ-NEXT: 'st_bind', 0x00000000 ; OBJ-NEXT: 'st_type', 0x00000001 ; OBJ-NEXT: 'st_other', 0x00000000 -; OBJ-NEXT: 'st_shndx', 0x00000003 +; OBJ-NEXT: 'st_shndx', 0x00000004 define i32 @main(i32 %argc) nounwind { %1 = load i32* @sum, align 4 diff --git a/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll b/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll new file mode 100644 index 000000000000..81babe0b4b19 --- /dev/null +++ b/test/CodeGen/ARM/2011-03-10-DAGCombineCrash.ll @@ -0,0 +1,47 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 + +; rdar://9117613 + +%struct.mo = type { i32, %struct.mo_pops* } +%struct.mo_pops = type { void (%struct.mo*)*, void (%struct.mo*)*, i32 (%struct.mo*, i32*, i32)*, i32 (%struct.mo*)*, i32 (%struct.mo*, i64, i32, i32, i32*, i64, i32)*, i32 (%struct.mo*, i64, i32, i64*, i32*, i32, i32, i32)*, i32 (%struct.mo*, i64, i32)*, i32 (%struct.mo*, i64, i64, i32)*, i32 (%struct.mo*, i64, i64, i32)*, i32 (%struct.mo*, i32)*, i32 (%struct.mo*)*, i32 (%struct.mo*, i32)*, i8* } +%struct.ui = type { %struct.mo*, i32*, i32, i32*, i32*, i64, i32*, i32*, i32* } + + +define internal fastcc i32 @t(i32* %vp, i32 %withfsize, i64 %filesize) nounwind { +entry: + br i1 undef, label %bb1, label %bb + +bb: ; preds = %entry + unreachable + +bb1: ; preds = %entry + %0 = call %struct.ui* @vn_pp_to_ui(i32* undef) nounwind + call void @llvm.memset.p0i8.i32(i8* undef, i8 0, i32 40, i32 4, i1 false) + %1 = getelementptr inbounds %struct.ui* %0, i32 0, i32 0 + store %struct.mo* undef, %struct.mo** %1, align 4 + %2 = getelementptr inbounds %struct.ui* %0, i32 0, i32 5 + %3 = load i64* %2, align 4 + %4 = call i32 @mo_create_nnm(%struct.mo* undef, i64 %3, i32** undef) nounwind + br i1 undef, label %bb3, label %bb2 + +bb2: ; preds = %bb1 + unreachable + +bb3: ; preds = %bb1 + br i1 undef, label %bb4, label %bb6 + +bb4: ; preds = %bb3 + %5 = call i32 @vn_size(i32* %vp, i64* %2, i32* undef) nounwind + unreachable + +bb6: ; preds = %bb3 + ret i32 0 +} + +declare %struct.ui* @vn_pp_to_ui(i32*) + +declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind + +declare i32 @mo_create_nnm(%struct.mo*, i64, i32**) + +declare i32 @vn_size(i32*, i64*, i32*) diff --git a/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll b/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll new file mode 100644 index 000000000000..ccda281e901e --- /dev/null +++ b/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll @@ -0,0 +1,55 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 | FileCheck %s + +; Do not form Thumb2 ldrd / strd if the offset is not multiple of 4. +; rdar://9133587 + +%struct.Outer = type { i32, [2 x %"struct.Outer::Inner"] } +%"struct.Outer::Inner" = type { i32, i32, i8, i8 } + +@oStruct = external global %struct.Outer, align 4 + +define void @main() nounwind { +; CHECK: main: +; CHECK-NOT: ldrd +; CHECK: mul +for.body.lr.ph: + br label %for.body + +for.body: ; preds = %_Z14printIsNotZeroi.exit17.for.body_crit_edge, %for.body.lr.ph + %tmp3 = phi i1 [ false, %for.body.lr.ph ], [ %phitmp27, %_Z14printIsNotZeroi.exit17.for.body_crit_edge ] + %i.022 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %_Z14printIsNotZeroi.exit17.for.body_crit_edge ] + %x = getelementptr %struct.Outer* @oStruct, i32 0, i32 1, i32 %i.022, i32 0 + %y = getelementptr %struct.Outer* @oStruct, i32 0, i32 1, i32 %i.022, i32 1 + %inc = add i32 %i.022, 1 + br i1 %tmp3, label %_Z14printIsNotZeroi.exit, label %if.then.i + +if.then.i: ; preds = %for.body + unreachable + +_Z14printIsNotZeroi.exit: ; preds = %for.body + %tmp8 = load i32* %x, align 4, !tbaa !0 + %tmp11 = load i32* %y, align 4, !tbaa !0 + %mul = mul nsw i32 %tmp11, %tmp8 + %tobool.i14 = icmp eq i32 %mul, 0 + br i1 %tobool.i14, label %_Z14printIsNotZeroi.exit17, label %if.then.i16 + +if.then.i16: ; preds = %_Z14printIsNotZeroi.exit + unreachable + +_Z14printIsNotZeroi.exit17: ; preds = %_Z14printIsNotZeroi.exit + br i1 undef, label %_Z14printIsNotZeroi.exit17.for.body_crit_edge, label %for.end + +_Z14printIsNotZeroi.exit17.for.body_crit_edge: ; preds = %_Z14printIsNotZeroi.exit17 + %b.phi.trans.insert = getelementptr %struct.Outer* @oStruct, i32 0, i32 1, i32 %inc, i32 3 + %tmp3.pre = load i8* %b.phi.trans.insert, align 1, !tbaa !3 + %phitmp27 = icmp eq i8 undef, 0 + br label %for.body + +for.end: ; preds = %_Z14printIsNotZeroi.exit17 + ret void +} + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} +!3 = metadata !{metadata !"bool", metadata !1} diff --git a/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll b/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll new file mode 100644 index 000000000000..7c9af6f5e590 --- /dev/null +++ b/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -relocation-model=pic -disable-fp-elim -mcpu=cortex-a8 | FileCheck %s + +; subs r4, #1 +; cmp r4, 0 +; bgt +; cmp cannot be optimized away since it will clear the overflow bit. +; gt / ge, lt, le conditions all depend on V bit. +; rdar://9172742 + +define i32 @t() nounwind { +; CHECK: t: +entry: + br label %bb2 + +bb: ; preds = %bb2 + %0 = tail call i32 @rand() nounwind + %1 = icmp eq i32 %0, 50 + br i1 %1, label %bb3, label %bb1 + +bb1: ; preds = %bb + %tmp = tail call i32 @puts() nounwind + %indvar.next = add i32 %indvar, 1 + br label %bb2 + +bb2: ; preds = %bb1, %entry +; CHECK: bb2 +; CHECK: subs [[REG:r[0-9]+]], #1 +; CHECK: cmp [[REG]], #0 +; CHECK: bgt + %indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %entry ] + %tries.0 = sub i32 2147483647, %indvar + %tmp1 = icmp sgt i32 %tries.0, 0 + br i1 %tmp1, label %bb, label %bb3 + +bb3: ; preds = %bb2, %bb + ret i32 0 +} + +declare i32 @rand() + +declare i32 @puts() nounwind diff --git a/test/CodeGen/ARM/2011-04-07-schediv.ll b/test/CodeGen/ARM/2011-04-07-schediv.ll new file mode 100644 index 000000000000..a61908fd7c45 --- /dev/null +++ b/test/CodeGen/ARM/2011-04-07-schediv.ll @@ -0,0 +1,31 @@ +; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s +; Tests preRAsched support for VRegCycle interference. + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +define void @t(i32 %src_width, float* nocapture %src_copy_start, float* nocapture %dst_copy_start, i32 %src_copy_start_index) nounwind optsize { +entry: + %src_copy_start6 = bitcast float* %src_copy_start to i8* + %0 = icmp eq i32 %src_width, 0 + br i1 %0, label %return, label %bb + +; Make sure the scheduler schedules all uses of the preincrement +; induction variable before defining the postincrement value. +; CHECK: t: +; CHECK-NOT: mov +bb: ; preds = %entry, %bb + %j.05 = phi i32 [ %2, %bb ], [ 0, %entry ] + %tmp = mul i32 %j.05, %src_copy_start_index + %uglygep = getelementptr i8* %src_copy_start6, i32 %tmp + %src_copy_start_addr.04 = bitcast i8* %uglygep to float* + %dst_copy_start_addr.03 = getelementptr float* %dst_copy_start, i32 %j.05 + %1 = load float* %src_copy_start_addr.04, align 4 + store float %1, float* %dst_copy_start_addr.03, align 4 + %2 = add i32 %j.05, 1 + %exitcond = icmp eq i32 %2, %src_width + br i1 %exitcond, label %return, label %bb + +return: ; preds = %bb, %entry + ret void +} diff --git a/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll b/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll new file mode 100644 index 000000000000..a9dd97182a4c --- /dev/null +++ b/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll @@ -0,0 +1,34 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s + +; Overly aggressive LICM simply adds copies of constants +; rdar://9266679 + +define zeroext i1 @t(i32* nocapture %A, i32 %size, i32 %value) nounwind readonly ssp { +; CHECK: t: +entry: + br label %for.cond + +for.cond: + %0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] + %cmp = icmp ult i32 %0, %size + br i1 %cmp, label %for.body, label %return + +for.body: +; CHECK: %for.body +; CHECK: movs r{{[0-9]+}}, #1 + %arrayidx = getelementptr i32* %A, i32 %0 + %tmp4 = load i32* %arrayidx, align 4 + %cmp6 = icmp eq i32 %tmp4, %value + br i1 %cmp6, label %return, label %for.inc + +; CHECK: %for.cond +; CHECK: movs r{{[0-9]+}}, #0 + +for.inc: + %inc = add i32 %0, 1 + br label %for.cond + +return: + %retval.0 = phi i1 [ true, %for.body ], [ false, %for.cond ] + ret i1 %retval.0 +} diff --git a/test/CodeGen/ARM/2011-04-12-AlignBug.ll b/test/CodeGen/ARM/2011-04-12-AlignBug.ll new file mode 100644 index 000000000000..317be94e86b0 --- /dev/null +++ b/test/CodeGen/ARM/2011-04-12-AlignBug.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10.0.0" + +; CHECK: align 3 +@.v = linker_private unnamed_addr constant <4 x i32> <i32 1, i32 2, i32 3, i32 4>, align 8 +; CHECK: align 2 +@.strA = linker_private unnamed_addr constant [4 x i8] c"bar\00" +; CHECK-NOT: align +@.strB = linker_private unnamed_addr constant [4 x i8] c"foo\00", align 1 +@.strC = linker_private unnamed_addr constant [4 x i8] c"baz\00", section "__TEXT,__cstring,cstring_literals", align 1 diff --git a/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll b/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll new file mode 100644 index 000000000000..eb23de0b9716 --- /dev/null +++ b/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=fast +; Previously we'd crash as out of registers on this input by clobbering all of +; the aliases. +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10.0.0" + +define void @_Z8TestCasev() nounwind ssp { +entry: + %a = alloca float, align 4 + %tmp = load float* %a, align 4 + call void asm sideeffect "", "w,~{s0},~{s16}"(float %tmp) nounwind, !srcloc !0 + ret void +} + +!0 = metadata !{i32 109} diff --git a/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll b/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll new file mode 100644 index 000000000000..e712e08ddb6a --- /dev/null +++ b/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s + +; CHECK: _f +; CHECK-NOT: ands +; CHECK: cmp +; CHECK: blxle _g + +define i32 @f(i32 %a, i32 %b) nounwind ssp { +entry: + %and = and i32 %b, %a + %cmp = icmp slt i32 %and, 1 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void (...)* @g(i32 %a, i32 %b) nounwind + br label %if.end + +if.end: ; preds = %if.then, %entry + ret i32 %and +} + +declare void @g(...) diff --git a/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll b/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll new file mode 100644 index 000000000000..5404cf57a59f --- /dev/null +++ b/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s + +; CHECK: _f +; CHECK: adds +; CHECK-NOT: cmp +; CHECK: blxeq _h + +define i32 @f(i32 %a, i32 %b) nounwind ssp { +entry: + %add = add nsw i32 %b, %a + %cmp = icmp eq i32 %add, 0 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void (...)* @h(i32 %a, i32 %b) nounwind + br label %if.end + +if.end: ; preds = %if.then, %entry + ret i32 %add +} + +; CHECK: _g +; CHECK: orrs +; CHECK-NOT: cmp +; CHECK: blxeq _h + +define i32 @g(i32 %a, i32 %b) nounwind ssp { +entry: + %add = or i32 %b, %a + %cmp = icmp eq i32 %add, 0 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void (...)* @h(i32 %a, i32 %b) nounwind + br label %if.end + +if.end: ; preds = %if.then, %entry + ret i32 %add +} + +declare void @h(...) diff --git a/test/CodeGen/ARM/2011-04-26-SchedTweak.ll b/test/CodeGen/ARM/2011-04-26-SchedTweak.ll new file mode 100644 index 000000000000..ed7dd0332046 --- /dev/null +++ b/test/CodeGen/ARM/2011-04-26-SchedTweak.ll @@ -0,0 +1,70 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-ios -relocation-model=pic -mcpu=cortex-a8 | FileCheck %s + +; Do not move the umull above previous call which would require use of +; more callee-saved registers and introduce copies. +; rdar://9329627 + +%struct.FF = type { i32 (i32*)*, i32 (i32*, i32*, i32, i32, i32, i32)*, i32 (i32, i32, i8*)*, void ()*, i32 (i32, i8*, i32*)*, i32 ()* } +%struct.BD = type { %struct.BD*, i32, i32, i32, i32, i64, i32 (%struct.BD*, i8*, i64, i32)*, i32 (%struct.BD*, i8*, i32, i32)*, i32 (%struct.BD*, i8*, i64, i32)*, i32 (%struct.BD*, i8*, i32, i32)*, i32 (%struct.BD*, i64, i32)*, [16 x i8], i64, i64 } + +@FuncPtr = external hidden unnamed_addr global %struct.FF* +@.str1 = external hidden unnamed_addr constant [6 x i8], align 4 +@G = external unnamed_addr global i32 +@.str2 = external hidden unnamed_addr constant [58 x i8], align 4 +@.str3 = external hidden unnamed_addr constant [58 x i8], align 4 + +define i32 @test() nounwind optsize ssp { +entry: +; CHECK: test: +; CHECK: push +; CHECK-NOT: push + %block_size = alloca i32, align 4 + %block_count = alloca i32, align 4 + %index_cache = alloca i32, align 4 + store i32 0, i32* %index_cache, align 4 + %tmp = load i32* @G, align 4 + %tmp1 = call i32 @bar(i32 0, i32 0, i32 %tmp) nounwind + switch i32 %tmp1, label %bb8 [ + i32 0, label %bb + i32 536870913, label %bb4 + i32 536870914, label %bb6 + ] + +bb: + %tmp2 = load i32* @G, align 4 + %tmp4 = icmp eq i32 %tmp2, 0 + br i1 %tmp4, label %bb1, label %bb8 + +bb1: +; CHECK: %bb1 +; CHECK-NOT: umull +; CHECK: blx _Get +; CHECK: umull +; CHECK: blx _foo + %tmp5 = load i32* %block_size, align 4 + %tmp6 = load i32* %block_count, align 4 + %tmp7 = call %struct.FF* @Get() nounwind + store %struct.FF* %tmp7, %struct.FF** @FuncPtr, align 4 + %tmp10 = zext i32 %tmp6 to i64 + %tmp11 = zext i32 %tmp5 to i64 + %tmp12 = mul nsw i64 %tmp10, %tmp11 + %tmp13 = call i32 @foo(i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0), i64 %tmp12, i32 %tmp5) nounwind + br label %bb8 + +bb4: + ret i32 0 + +bb6: + ret i32 1 + +bb8: + ret i32 -1 +} + +declare i32 @printf(i8*, ...) + +declare %struct.FF* @Get() + +declare i32 @foo(i8*, i64, i32) + +declare i32 @bar(i32, i32, i32) diff --git a/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll b/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll new file mode 100644 index 000000000000..0741049cffdd --- /dev/null +++ b/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll @@ -0,0 +1,59 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-ios + +; If converter was being too cute. It look for root BBs (which don't have +; successors) and use inverse depth first search to traverse the BBs. However +; that doesn't work when the CFG has infinite loops. Simply do a linear +; traversal of all BBs work just fine. + +; rdar://9344645 + +%struct.hc = type { i32, i32, i32, i32 } + +define i32 @t(i32 %type) optsize { +entry: + br i1 undef, label %if.then, label %if.else + +if.then: + unreachable + +if.else: + br i1 undef, label %if.then15, label %if.else18 + +if.then15: + unreachable + +if.else18: + switch i32 %type, label %if.else173 [ + i32 3, label %if.then115 + i32 1, label %if.then102 + ] + +if.then102: + br i1 undef, label %cond.true10.i, label %t.exit + +cond.true10.i: + br label %t.exit + +t.exit: + unreachable + +if.then115: + br i1 undef, label %if.else163, label %if.else145 + +if.else145: + %call150 = call fastcc %struct.hc* @foo(%struct.hc* undef, i32 34865152) optsize + br label %while.body172 + +if.else163: + %call168 = call fastcc %struct.hc* @foo(%struct.hc* undef, i32 34078720) optsize + br label %while.body172 + +while.body172: + br label %while.body172 + +if.else173: + ret i32 -1 +} + +declare hidden fastcc %struct.hc* @foo(%struct.hc* nocapture, i32) nounwind optsize + diff --git a/test/CodeGen/ARM/align.ll b/test/CodeGen/ARM/align.ll index d57c159b85cb..9589e72df2f5 100644 --- a/test/CodeGen/ARM/align.ll +++ b/test/CodeGen/ARM/align.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=ELF -; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN +; RUN: llc < %s -mtriple=arm-apple-darwin10 | FileCheck %s -check-prefix=DARWIN @a = global i1 true ; no alignment diff --git a/test/CodeGen/ARM/arguments.ll b/test/CodeGen/ARM/arguments.ll index c7fcb9755d9e..a8b42e63b71f 100644 --- a/test/CodeGen/ARM/arguments.ll +++ b/test/CodeGen/ARM/arguments.ll @@ -14,7 +14,7 @@ define i32 @f1(i32 %a, i64 %b) { define i32 @f2() nounwind optsize { ; ELF: f2: ; ELF: mov [[REGISTER:(r[0-9]+)]], #128 -; ELF: str [[REGISTER]], [sp] +; ELF: str [[REGISTER]], [ ; DARWIN: f2: ; DARWIN: mov r3, #128 entry: diff --git a/test/CodeGen/ARM/arm-and-tst-peephole.ll b/test/CodeGen/ARM/arm-and-tst-peephole.ll index 50c638b73931..07620700aedb 100644 --- a/test/CodeGen/ARM/arm-and-tst-peephole.ll +++ b/test/CodeGen/ARM/arm-and-tst-peephole.ll @@ -23,15 +23,15 @@ tailrecurse: ; preds = %sw.bb, %entry %tmp2 = load i8** %scevgep5 %0 = ptrtoint i8* %tmp2 to i32 -; ARM: ands r12, r12, #3 +; ARM: ands {{r[0-9]+}}, {{r[0-9]+}}, #3 ; ARM-NEXT: beq -; THUMB: movs r5, #3 -; THUMB-NEXT: ands r5, r4 -; THUMB-NEXT: cmp r5, #0 +; THUMB: movs r[[R0:[0-9]+]], #3 +; THUMB-NEXT: ands r[[R0]], r +; THUMB-NEXT: cmp r[[R0]], #0 ; THUMB-NEXT: beq -; T2: ands r12, r12, #3 +; T2: ands {{r[0-9]+}}, {{r[0-9]+}}, #3 ; T2-NEXT: beq %and = and i32 %0, 3 diff --git a/test/CodeGen/ARM/arm-returnaddr.ll b/test/CodeGen/ARM/arm-returnaddr.ll index 382a18334600..95edaad47e5f 100644 --- a/test/CodeGen/ARM/arm-returnaddr.ll +++ b/test/CodeGen/ARM/arm-returnaddr.ll @@ -1,5 +1,7 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s ; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=basic | FileCheck %s +; RUN: llc < %s -mtriple=thumbv6-apple-darwin -regalloc=basic | FileCheck %s ; rdar://8015977 ; rdar://8020118 @@ -16,7 +18,7 @@ define i8* @rt2() nounwind readnone { entry: ; CHECK: rt2: ; CHECK: {r7, lr} -; CHECK: ldr r0, [r7] +; CHECK: ldr r[[R0:[0-9]+]], [r7] ; CHECK: ldr r0, [r0] ; CHECK: ldr r0, [r0, #4] %0 = tail call i8* @llvm.returnaddress(i32 2) diff --git a/test/CodeGen/ARM/avoid-cpsr-rmw.ll b/test/CodeGen/ARM/avoid-cpsr-rmw.ll new file mode 100644 index 000000000000..d0c4f3ae9d67 --- /dev/null +++ b/test/CodeGen/ARM/avoid-cpsr-rmw.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s +; Avoid some 's' 16-bit instruction which partially update CPSR (and add false +; dependency) when it isn't dependent on last CPSR defining instruction. +; rdar://8928208 + +define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { + entry: +; CHECK: t: +; CHECK: muls r2, r3, r2 +; CHECK-NEXT: mul r0, r0, r1 +; CHECK-NEXT: muls r0, r2, r0 + %0 = mul nsw i32 %a, %b + %1 = mul nsw i32 %c, %d + %2 = mul nsw i32 %0, %1 + ret i32 %2 +} diff --git a/test/CodeGen/ARM/bx_fold.ll b/test/CodeGen/ARM/bx_fold.ll index 09f1aae0a9f0..5533038fb828 100644 --- a/test/CodeGen/ARM/bx_fold.ll +++ b/test/CodeGen/ARM/bx_fold.ll @@ -24,7 +24,7 @@ bb1: ; preds = %bb, %entry bb18: ; preds = %bb1 ; CHECK-NOT: bx -; CHECK: ldmia sp! +; CHECK: pop ret void } diff --git a/test/CodeGen/ARM/call-tc.ll b/test/CodeGen/ARM/call-tc.ll index a77aba037be5..4dc37aa27558 100644 --- a/test/CodeGen/ARM/call-tc.ll +++ b/test/CodeGen/ARM/call-tc.ll @@ -74,7 +74,7 @@ entry: ; CHECKT2: t7: ; CHECKT2: blxeq _foo ; CHECKT2-NEXT: pop.w -; CHECKT2-NEXT: b.w _foo +; CHECKT2-NEXT: b _foo br i1 undef, label %bb, label %bb1.lr.ph bb1.lr.ph: diff --git a/test/CodeGen/ARM/carry.ll b/test/CodeGen/ARM/carry.ll index a6a7ed6af184..9b90408cc4db 100644 --- a/test/CodeGen/ARM/carry.ll +++ b/test/CodeGen/ARM/carry.ll @@ -19,3 +19,20 @@ entry: %tmp2 = sub i64 %tmp1, %b ret i64 %tmp2 } + +; add with live carry +define i64 @f3(i32 %al, i32 %bl) { +; CHECK: f3: +; CHECK: adds r +; CHECK: adcs r +; CHECK: adc r +entry: + ; unsigned wide add + %aw = zext i32 %al to i64 + %bw = zext i32 %bl to i64 + %cw = add i64 %aw, %bw + ; ch == carry bit + %ch = lshr i64 %cw, 32 + %dw = add i64 %ch, %bw + ret i64 %dw +} diff --git a/test/CodeGen/ARM/code-placement.ll b/test/CodeGen/ARM/code-placement.ll index 845be8c20ea5..91ef65925221 100644 --- a/test/CodeGen/ARM/code-placement.ll +++ b/test/CodeGen/ARM/code-placement.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=armv7-apple-darwin -cgp-critical-edge-splitting=0 | FileCheck %s +; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s ; PHI elimination shouldn't break backedge. ; rdar://8263994 @@ -72,7 +72,7 @@ bb2.preheader: ; preds = %bb3, %bb.nph15 br i1 %4, label %bb1, label %bb3 ; CHECK: LBB1_[[RET]]: @ %bb5 -; CHECK: ldmia sp! +; CHECK: pop bb5: ; preds = %bb3, %entry %sum.1.lcssa = phi i32 [ 0, %entry ], [ %sum.0.lcssa, %bb3 ] ; <i32> [#uses=1] ret i32 %sum.1.lcssa diff --git a/test/CodeGen/ARM/constants.ll b/test/CodeGen/ARM/constants.ll index 542cf02f2a90..7893df782054 100644 --- a/test/CodeGen/ARM/constants.ll +++ b/test/CodeGen/ARM/constants.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc < %s -march=arm -disable-cgp-branch-opts | FileCheck %s define i32 @f1() { ; CHECK: f1 @@ -14,31 +14,31 @@ define i32 @f2() { define i32 @f3() { ; CHECK: f3 -; CHECK: mov r0, #1, 24 +; CHECK: mov r0, #1, #24 ret i32 256 } define i32 @f4() { ; CHECK: f4 -; CHECK: orr{{.*}}#1, 24 +; CHECK: orr{{.*}}#1, #24 ret i32 257 } define i32 @f5() { ; CHECK: f5 -; CHECK: mov r0, #255, 2 +; CHECK: mov r0, #255, #2 ret i32 -1073741761 } define i32 @f6() { ; CHECK: f6 -; CHECK: mov r0, #63, 28 +; CHECK: mov r0, #63, #28 ret i32 1008 } define void @f7(i32 %a) { ; CHECK: f7 -; CHECK: cmp r0, #1, 16 +; CHECK: cmp r0, #1, #16 %b = icmp ugt i32 %a, 65536 br i1 %b, label %r, label %r r: diff --git a/test/CodeGen/ARM/crash-greedy.ll b/test/CodeGen/ARM/crash-greedy.ll new file mode 100644 index 000000000000..8a865e23d0a4 --- /dev/null +++ b/test/CodeGen/ARM/crash-greedy.ll @@ -0,0 +1,84 @@ +; RUN: llc < %s -regalloc=greedy -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim -verify-machineinstrs | FileCheck %s +; +; ARM tests that crash or fail with the greedy register allocator. + +target triple = "thumbv7-apple-darwin" + +declare double @exp(double) + +; CHECK: remat_subreg +define void @remat_subreg(float* nocapture %x, i32* %y, i32 %n, i32 %z, float %c, float %lambda, float* nocapture %ret_f, float* nocapture %ret_df) nounwind { +entry: + %conv16 = fpext float %lambda to double + %mul17 = fmul double %conv16, -1.000000e+00 + br i1 undef, label %cond.end.us, label %cond.end + +cond.end.us: ; preds = %entry + unreachable + +cond.end: ; preds = %cond.end, %entry + %mul = fmul double undef, 0.000000e+00 + %add = fadd double undef, %mul + %add46 = fadd double undef, undef + %add75 = fadd double 0.000000e+00, undef + br i1 undef, label %for.end, label %cond.end + +for.end: ; preds = %cond.end + %conv78 = sitofp i32 %z to double + %conv83 = fpext float %c to double + %mul84 = fmul double %mul17, %conv83 + %call85 = tail call double @exp(double %mul84) nounwind + %mul86 = fmul double %conv78, %call85 + %add88 = fadd double 0.000000e+00, %mul86 +; CHECK: blx _exp + %call100 = tail call double @exp(double %mul84) nounwind + %mul101 = fmul double undef, %call100 + %add103 = fadd double %add46, %mul101 + %mul111 = fmul double undef, %conv83 + %mul119 = fmul double %mul111, undef + %add121 = fadd double undef, %mul119 + %div = fdiv double 1.000000e+00, %conv16 + %div126 = fdiv double %add, %add75 + %sub = fsub double %div, %div126 + %div129 = fdiv double %add103, %add88 + %add130 = fadd double %sub, %div129 + %conv131 = fptrunc double %add130 to float + store float %conv131, float* %ret_f, align 4 + %mul139 = fmul double %div129, %div129 + %div142 = fdiv double %add121, %add88 + %sub143 = fsub double %mul139, %div142 +; %lambda is passed on the stack, and the stack slot load is rematerialized. +; The rematted load of a float constrains the D register used for the mul. +; CHECK: vldr + %mul146 = fmul float %lambda, %lambda + %conv147 = fpext float %mul146 to double + %div148 = fdiv double 1.000000e+00, %conv147 + %sub149 = fsub double %sub143, %div148 + %conv150 = fptrunc double %sub149 to float + store float %conv150, float* %ret_df, align 4 + ret void +} + +; CHECK: insert_elem +; This test has a sub-register copy with a kill flag: +; %vreg6:ssub_3<def> = COPY %vreg6:ssub_2<kill>; QPR_VFP2:%vreg6 +; The rewriter must do something sensible with that, or the scavenger crashes. +define void @insert_elem() nounwind { +entry: + br i1 undef, label %if.end251, label %if.then84 + +if.then84: ; preds = %entry + br i1 undef, label %if.end251, label %if.then195 + +if.then195: ; preds = %if.then84 + %div = fdiv float 1.000000e+00, undef + %vecinit207 = insertelement <4 x float> undef, float %div, i32 1 + %vecinit208 = insertelement <4 x float> %vecinit207, float 1.000000e+00, i32 2 + %vecinit209 = insertelement <4 x float> %vecinit208, float 1.000000e+00, i32 3 + %mul216 = fmul <4 x float> zeroinitializer, %vecinit209 + store <4 x float> %mul216, <4 x float>* undef, align 16 + br label %if.end251 + +if.end251: ; preds = %if.then195, %if.then84, %entry + ret void +} diff --git a/test/CodeGen/ARM/debug-info-d16-reg.ll b/test/CodeGen/ARM/debug-info-d16-reg.ll new file mode 100644 index 000000000000..8c9095e3a9ea --- /dev/null +++ b/test/CodeGen/ARM/debug-info-d16-reg.ll @@ -0,0 +1,105 @@ +; RUN: llc < %s - | FileCheck %s +; Radar 9309221 +; Test dwarf reg no for d16 +;CHECK: DW_OP_regx +;CHECK-NEXT: 272 + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +@.str = private unnamed_addr constant [11 x i8] c"%p %lf %c\0A\00", align 4 +@.str1 = private unnamed_addr constant [6 x i8] c"point\00", align 4 + +define i32 @inlineprinter(i8* %ptr, double %val, i8 zeroext %c) nounwind optsize { +entry: + tail call void @llvm.dbg.value(metadata !{i8* %ptr}, i64 0, metadata !19), !dbg !26 + tail call void @llvm.dbg.value(metadata !{double %val}, i64 0, metadata !20), !dbg !26 + tail call void @llvm.dbg.value(metadata !{i8 %c}, i64 0, metadata !21), !dbg !26 + %0 = zext i8 %c to i32, !dbg !27 + %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %val, i32 %0) nounwind, !dbg !27 + ret i32 0, !dbg !29 +} + +define i32 @printer(i8* %ptr, double %val, i8 zeroext %c) nounwind optsize noinline { +entry: + tail call void @llvm.dbg.value(metadata !{i8* %ptr}, i64 0, metadata !16), !dbg !30 + tail call void @llvm.dbg.value(metadata !{double %val}, i64 0, metadata !17), !dbg !30 + tail call void @llvm.dbg.value(metadata !{i8 %c}, i64 0, metadata !18), !dbg !30 + %0 = zext i8 %c to i32, !dbg !31 + %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %val, i32 %0) nounwind, !dbg !31 + ret i32 0, !dbg !33 +} + +declare i32 @printf(i8* nocapture, ...) nounwind + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind optsize { +entry: + tail call void @llvm.dbg.value(metadata !{i32 %argc}, i64 0, metadata !22), !dbg !34 + tail call void @llvm.dbg.value(metadata !{i8** %argv}, i64 0, metadata !23), !dbg !34 + %0 = sitofp i32 %argc to double, !dbg !35 + %1 = fadd double %0, 5.555552e+05, !dbg !35 + tail call void @llvm.dbg.value(metadata !{double %1}, i64 0, metadata !24), !dbg !35 + %2 = tail call i32 @puts(i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0)) nounwind, !dbg !36 + %3 = getelementptr inbounds i8* bitcast (i32 (i32, i8**)* @main to i8*), i32 %argc, !dbg !37 + %4 = trunc i32 %argc to i8, !dbg !37 + %5 = add i8 %4, 97, !dbg !37 + tail call void @llvm.dbg.value(metadata !{i8* %3}, i64 0, metadata !19) nounwind, !dbg !38 + tail call void @llvm.dbg.value(metadata !{double %1}, i64 0, metadata !20) nounwind, !dbg !38 + tail call void @llvm.dbg.value(metadata !{i8 %5}, i64 0, metadata !21) nounwind, !dbg !38 + %6 = zext i8 %5 to i32, !dbg !39 + %7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %3, double %1, i32 %6) nounwind, !dbg !39 + %8 = tail call i32 @printer(i8* %3, double %1, i8 zeroext %5) nounwind, !dbg !40 + ret i32 0, !dbg !41 +} + +declare i32 @puts(i8* nocapture) nounwind + +!llvm.dbg.sp = !{!0, !9, !10} +!llvm.dbg.lv.printer = !{!16, !17, !18} +!llvm.dbg.lv.inlineprinter = !{!19, !20, !21} +!llvm.dbg.lv.main = !{!22, !23, !24} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"printer", metadata !"printer", metadata !"printer", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i8*, double, i8)* @printer} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"a.c", metadata !"/tmp/", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 1, metadata !"/tmp/a.c", metadata !"/tmp", metadata !"(LLVM build 00)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5, metadata !6, metadata !7, metadata !8} +!5 = metadata !{i32 589860, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 589839, metadata !1, metadata !"", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] +!7 = metadata !{i32 589860, metadata !1, metadata !"double", metadata !1, i32 0, i64 64, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!8 = metadata !{i32 589860, metadata !1, metadata !"unsigned char", metadata !1, i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ] +!9 = metadata !{i32 589870, i32 0, metadata !1, metadata !"inlineprinter", metadata !"inlineprinter", metadata !"inlineprinter", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i8*, double, i8)* @inlineprinter} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 18, metadata !11, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**)* @main} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !5, metadata !5, metadata !13} +!13 = metadata !{i32 589839, metadata !1, metadata !"", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !14} ; [ DW_TAG_pointer_type ] +!14 = metadata !{i32 589839, metadata !1, metadata !"", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !15} ; [ DW_TAG_pointer_type ] +!15 = metadata !{i32 589860, metadata !1, metadata !"char", metadata !1, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] +!16 = metadata !{i32 590081, metadata !0, metadata !"ptr", metadata !1, i32 11, metadata !6, i32 0} ; [ DW_TAG_arg_variable ] +!17 = metadata !{i32 590081, metadata !0, metadata !"val", metadata !1, i32 11, metadata !7, i32 0} ; [ DW_TAG_arg_variable ] +!18 = metadata !{i32 590081, metadata !0, metadata !"c", metadata !1, i32 11, metadata !8, i32 0} ; [ DW_TAG_arg_variable ] +!19 = metadata !{i32 590081, metadata !9, metadata !"ptr", metadata !1, i32 4, metadata !6, i32 0} ; [ DW_TAG_arg_variable ] +!20 = metadata !{i32 590081, metadata !9, metadata !"val", metadata !1, i32 4, metadata !7, i32 0} ; [ DW_TAG_arg_variable ] +!21 = metadata !{i32 590081, metadata !9, metadata !"c", metadata !1, i32 4, metadata !8, i32 0} ; [ DW_TAG_arg_variable ] +!22 = metadata !{i32 590081, metadata !10, metadata !"argc", metadata !1, i32 17, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!23 = metadata !{i32 590081, metadata !10, metadata !"argv", metadata !1, i32 17, metadata !13, i32 0} ; [ DW_TAG_arg_variable ] +!24 = metadata !{i32 590080, metadata !25, metadata !"dval", metadata !1, i32 19, metadata !7, i32 0} ; [ DW_TAG_auto_variable ] +!25 = metadata !{i32 589835, metadata !10, i32 18, i32 0, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] +!26 = metadata !{i32 4, i32 0, metadata !9, null} +!27 = metadata !{i32 6, i32 0, metadata !28, null} +!28 = metadata !{i32 589835, metadata !9, i32 5, i32 0, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] +!29 = metadata !{i32 7, i32 0, metadata !28, null} +!30 = metadata !{i32 11, i32 0, metadata !0, null} +!31 = metadata !{i32 13, i32 0, metadata !32, null} +!32 = metadata !{i32 589835, metadata !0, i32 12, i32 0, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!33 = metadata !{i32 14, i32 0, metadata !32, null} +!34 = metadata !{i32 17, i32 0, metadata !10, null} +!35 = metadata !{i32 19, i32 0, metadata !25, null} +!36 = metadata !{i32 20, i32 0, metadata !25, null} +!37 = metadata !{i32 21, i32 0, metadata !25, null} +!38 = metadata !{i32 4, i32 0, metadata !9, metadata !37} +!39 = metadata !{i32 6, i32 0, metadata !28, metadata !37} +!40 = metadata !{i32 22, i32 0, metadata !25, null} +!41 = metadata !{i32 23, i32 0, metadata !25, null} diff --git a/test/CodeGen/ARM/debug-info-qreg.ll b/test/CodeGen/ARM/debug-info-qreg.ll new file mode 100644 index 000000000000..e83a83d1f10a --- /dev/null +++ b/test/CodeGen/ARM/debug-info-qreg.ll @@ -0,0 +1,94 @@ +; RUN: llc < %s - | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-macosx10.6.7" + +;CHECK: DW_OP_regx for Q register: D1 +;CHECK-NEXT: byte +;CHECK-NEXT: byte +;CHECK-NEXT: DW_OP_piece 8 +;CHECK-NEXT: byte 8 +;CHECK-NEXT: DW_OP_regx for Q register: D2 +;CHECK-NEXT: byte +;CHECK-NEXT: byte +;CHECK-NEXT: DW_OP_piece 8 +;CHECK-NEXT: byte 8 + +@.str = external constant [13 x i8] + +declare <4 x float> @test0001(float) nounwind readnone ssp + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind ssp { +entry: + br label %for.body9 + +for.body9: ; preds = %for.body9, %entry + %add19 = fadd <4 x float> undef, <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, !dbg !39 + br i1 undef, label %for.end54, label %for.body9, !dbg !44 + +for.end54: ; preds = %for.body9 + tail call void @llvm.dbg.value(metadata !{<4 x float> %add19}, i64 0, metadata !27), !dbg !39 + %tmp115 = extractelement <4 x float> %add19, i32 1 + %conv6.i75 = fpext float %tmp115 to double, !dbg !45 + %call.i82 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45 + ret i32 0, !dbg !49 +} + +declare i32 @printf(i8* nocapture, ...) nounwind + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.sp = !{!0, !10, !14} +!llvm.dbg.lv.test0001 = !{!18} +!llvm.dbg.lv.main = !{!19, !20, !24, !26, !27, !28, !29} +!llvm.dbg.lv.printFV = !{!30} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"test0001", metadata !"test0001", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, <4 x float> (float)* @test0001, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"build2.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"build2.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 129915)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589846, metadata !2, metadata !"v4f32", metadata !1, i32 14, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ] +!6 = metadata !{i32 590083, metadata !2, metadata !"", metadata !2, i32 0, i64 128, i64 128, i32 0, i32 0, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_vector_type ] +!7 = metadata !{i32 589860, metadata !2, metadata !"float", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!8 = metadata !{metadata !9} +!9 = metadata !{i32 589857, i64 0, i64 3} ; [ DW_TAG_subrange_type ] +!10 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 59, metadata !11, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**)* @main, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{i32 589870, i32 0, metadata !15, metadata !"printFV", metadata !"printFV", metadata !"", metadata !15, i32 41, metadata !16, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, null, null} ; [ DW_TAG_subprogram ] +!15 = metadata !{i32 589865, metadata !"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!16 = metadata !{i32 589845, metadata !15, metadata !"", metadata !15, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !17, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!17 = metadata !{null} +!18 = metadata !{i32 590081, metadata !0, metadata !"a", metadata !1, i32 16777219, metadata !7, i32 0} ; [ DW_TAG_arg_variable ] +!19 = metadata !{i32 590081, metadata !10, metadata !"argc", metadata !1, i32 16777275, metadata !13, i32 0} ; [ DW_TAG_arg_variable ] +!20 = metadata !{i32 590081, metadata !10, metadata !"argv", metadata !1, i32 33554491, metadata !21, i32 0} ; [ DW_TAG_arg_variable ] +!21 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !22} ; [ DW_TAG_pointer_type ] +!22 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !23} ; [ DW_TAG_pointer_type ] +!23 = metadata !{i32 589860, metadata !2, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] +!24 = metadata !{i32 590080, metadata !25, metadata !"i", metadata !1, i32 60, metadata !13, i32 0} ; [ DW_TAG_auto_variable ] +!25 = metadata !{i32 589835, metadata !10, i32 59, i32 33, metadata !1, i32 14} ; [ DW_TAG_lexical_block ] +!26 = metadata !{i32 590080, metadata !25, metadata !"j", metadata !1, i32 60, metadata !13, i32 0} ; [ DW_TAG_auto_variable ] +!27 = metadata !{i32 590080, metadata !25, metadata !"x", metadata !1, i32 61, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!28 = metadata !{i32 590080, metadata !25, metadata !"y", metadata !1, i32 62, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!29 = metadata !{i32 590080, metadata !25, metadata !"z", metadata !1, i32 63, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!30 = metadata !{i32 590081, metadata !14, metadata !"F", metadata !15, i32 16777257, metadata !31, i32 0} ; [ DW_TAG_arg_variable ] +!31 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !32} ; [ DW_TAG_pointer_type ] +!32 = metadata !{i32 589846, metadata !2, metadata !"FV", metadata !15, i32 25, i64 0, i64 0, i64 0, i32 0, metadata !33} ; [ DW_TAG_typedef ] +!33 = metadata !{i32 589847, metadata !2, metadata !"", metadata !15, i32 22, i64 128, i64 128, i64 0, i32 0, i32 0, metadata !34, i32 0, i32 0} ; [ DW_TAG_union_type ] +!34 = metadata !{metadata !35, metadata !37} +!35 = metadata !{i32 589837, metadata !15, metadata !"V", metadata !15, i32 23, i64 128, i64 128, i64 0, i32 0, metadata !36} ; [ DW_TAG_member ] +!36 = metadata !{i32 589846, metadata !2, metadata !"v4sf", metadata !15, i32 3, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ] +!37 = metadata !{i32 589837, metadata !15, metadata !"A", metadata !15, i32 24, i64 128, i64 32, i64 0, i32 0, metadata !38} ; [ DW_TAG_member ] +!38 = metadata !{i32 589825, metadata !2, metadata !"", metadata !2, i32 0, i64 128, i64 32, i32 0, i32 0, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_array_type ] +!39 = metadata !{i32 79, i32 7, metadata !40, null} +!40 = metadata !{i32 589835, metadata !41, i32 75, i32 35, metadata !1, i32 18} ; [ DW_TAG_lexical_block ] +!41 = metadata !{i32 589835, metadata !42, i32 75, i32 5, metadata !1, i32 17} ; [ DW_TAG_lexical_block ] +!42 = metadata !{i32 589835, metadata !43, i32 71, i32 32, metadata !1, i32 16} ; [ DW_TAG_lexical_block ] +!43 = metadata !{i32 589835, metadata !25, i32 71, i32 3, metadata !1, i32 15} ; [ DW_TAG_lexical_block ] +!44 = metadata !{i32 75, i32 5, metadata !42, null} +!45 = metadata !{i32 42, i32 2, metadata !46, metadata !48} +!46 = metadata !{i32 589835, metadata !47, i32 42, i32 2, metadata !15, i32 20} ; [ DW_TAG_lexical_block ] +!47 = metadata !{i32 589835, metadata !14, i32 41, i32 28, metadata !15, i32 19} ; [ DW_TAG_lexical_block ] +!48 = metadata !{i32 95, i32 3, metadata !25, null} +!49 = metadata !{i32 99, i32 3, metadata !25, null} diff --git a/test/CodeGen/ARM/debug-info-s16-reg.ll b/test/CodeGen/ARM/debug-info-s16-reg.ll new file mode 100644 index 000000000000..548c9bdebf02 --- /dev/null +++ b/test/CodeGen/ARM/debug-info-s16-reg.ll @@ -0,0 +1,116 @@ +; RUN: llc < %s - | FileCheck %s +; Radar 9309221 +; Test dwarf reg no for s16 +;CHECK: DW_OP_regx for S register +;CHECK-NEXT: byte +;CHECK-NEXT: byte +;CHECK-NEXT: DW_OP_bit_piece 32 0 + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-macosx10.6.7" + +@.str = private unnamed_addr constant [11 x i8] c"%p %lf %c\0A\00" +@.str1 = private unnamed_addr constant [6 x i8] c"point\00" + +define i32 @inlineprinter(i8* %ptr, float %val, i8 zeroext %c) nounwind optsize ssp { +entry: + tail call void @llvm.dbg.value(metadata !{i8* %ptr}, i64 0, metadata !8), !dbg !24 + tail call void @llvm.dbg.value(metadata !{float %val}, i64 0, metadata !10), !dbg !25 + tail call void @llvm.dbg.value(metadata !{i8 %c}, i64 0, metadata !12), !dbg !26 + %conv = fpext float %val to double, !dbg !27 + %conv3 = zext i8 %c to i32, !dbg !27 + %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %conv, i32 %conv3) nounwind optsize, !dbg !27 + ret i32 0, !dbg !29 +} + +declare i32 @printf(i8* nocapture, ...) nounwind optsize + +define i32 @printer(i8* %ptr, float %val, i8 zeroext %c) nounwind optsize noinline ssp { +entry: + tail call void @llvm.dbg.value(metadata !{i8* %ptr}, i64 0, metadata !14), !dbg !30 + tail call void @llvm.dbg.value(metadata !{float %val}, i64 0, metadata !15), !dbg !31 + tail call void @llvm.dbg.value(metadata !{i8 %c}, i64 0, metadata !16), !dbg !32 + %conv = fpext float %val to double, !dbg !33 + %conv3 = zext i8 %c to i32, !dbg !33 + %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %conv, i32 %conv3) nounwind optsize, !dbg !33 + ret i32 0, !dbg !35 +} + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind optsize ssp { +entry: + tail call void @llvm.dbg.value(metadata !{i32 %argc}, i64 0, metadata !17), !dbg !36 + tail call void @llvm.dbg.value(metadata !{i8** %argv}, i64 0, metadata !18), !dbg !37 + %conv = sitofp i32 %argc to double, !dbg !38 + %add = fadd double %conv, 5.555552e+05, !dbg !38 + %conv1 = fptrunc double %add to float, !dbg !38 + tail call void @llvm.dbg.value(metadata !{float %conv1}, i64 0, metadata !22), !dbg !38 + %call = tail call i32 @puts(i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0)) nounwind optsize, !dbg !39 + %add.ptr = getelementptr i8* bitcast (i32 (i32, i8**)* @main to i8*), i32 %argc, !dbg !40 + %add5 = add nsw i32 %argc, 97, !dbg !40 + %conv6 = trunc i32 %add5 to i8, !dbg !40 + tail call void @llvm.dbg.value(metadata !{i8* %add.ptr}, i64 0, metadata !8) nounwind, !dbg !41 + tail call void @llvm.dbg.value(metadata !{float %conv1}, i64 0, metadata !10) nounwind, !dbg !42 + tail call void @llvm.dbg.value(metadata !{i8 %conv6}, i64 0, metadata !12) nounwind, !dbg !43 + %conv.i = fpext float %conv1 to double, !dbg !44 + %conv3.i = and i32 %add5, 255, !dbg !44 + %call.i = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %add.ptr, double %conv.i, i32 %conv3.i) nounwind optsize, !dbg !44 + %call14 = tail call i32 @printer(i8* %add.ptr, float %conv1, i8 zeroext %conv6) optsize, !dbg !45 + ret i32 0, !dbg !46 +} + +declare i32 @puts(i8* nocapture) nounwind optsize + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.sp = !{!0, !6, !7} +!llvm.dbg.lv.inlineprinter = !{!8, !10, !12} +!llvm.dbg.lv.printer = !{!14, !15, !16} +!llvm.dbg.lv.main = !{!17, !18, !22} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"inlineprinter", metadata !"inlineprinter", metadata !"", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i8*, float, i8)* @inlineprinter, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"a.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"a.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 129915)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 589870, i32 0, metadata !1, metadata !"printer", metadata !"printer", metadata !"", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i8*, float, i8)* @printer, null} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 18, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**)* @main, null} ; [ DW_TAG_subprogram ] +!8 = metadata !{i32 590081, metadata !0, metadata !"ptr", metadata !1, i32 16777220, metadata !9, i32 0} ; [ DW_TAG_arg_variable ] +!9 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] +!10 = metadata !{i32 590081, metadata !0, metadata !"val", metadata !1, i32 33554436, metadata !11, i32 0} ; [ DW_TAG_arg_variable ] +!11 = metadata !{i32 589860, metadata !2, metadata !"float", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!12 = metadata !{i32 590081, metadata !0, metadata !"c", metadata !1, i32 50331652, metadata !13, i32 0} ; [ DW_TAG_arg_variable ] +!13 = metadata !{i32 589860, metadata !2, metadata !"unsigned char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ] +!14 = metadata !{i32 590081, metadata !6, metadata !"ptr", metadata !1, i32 16777227, metadata !9, i32 0} ; [ DW_TAG_arg_variable ] +!15 = metadata !{i32 590081, metadata !6, metadata !"val", metadata !1, i32 33554443, metadata !11, i32 0} ; [ DW_TAG_arg_variable ] +!16 = metadata !{i32 590081, metadata !6, metadata !"c", metadata !1, i32 50331659, metadata !13, i32 0} ; [ DW_TAG_arg_variable ] +!17 = metadata !{i32 590081, metadata !7, metadata !"argc", metadata !1, i32 16777233, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!18 = metadata !{i32 590081, metadata !7, metadata !"argv", metadata !1, i32 33554449, metadata !19, i32 0} ; [ DW_TAG_arg_variable ] +!19 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !20} ; [ DW_TAG_pointer_type ] +!20 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !21} ; [ DW_TAG_pointer_type ] +!21 = metadata !{i32 589860, metadata !2, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] +!22 = metadata !{i32 590080, metadata !23, metadata !"dval", metadata !1, i32 19, metadata !11, i32 0} ; [ DW_TAG_auto_variable ] +!23 = metadata !{i32 589835, metadata !7, i32 18, i32 1, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] +!24 = metadata !{i32 4, i32 22, metadata !0, null} +!25 = metadata !{i32 4, i32 33, metadata !0, null} +!26 = metadata !{i32 4, i32 52, metadata !0, null} +!27 = metadata !{i32 6, i32 3, metadata !28, null} +!28 = metadata !{i32 589835, metadata !0, i32 5, i32 1, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!29 = metadata !{i32 7, i32 3, metadata !28, null} +!30 = metadata !{i32 11, i32 42, metadata !6, null} +!31 = metadata !{i32 11, i32 53, metadata !6, null} +!32 = metadata !{i32 11, i32 72, metadata !6, null} +!33 = metadata !{i32 13, i32 3, metadata !34, null} +!34 = metadata !{i32 589835, metadata !6, i32 12, i32 1, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] +!35 = metadata !{i32 14, i32 3, metadata !34, null} +!36 = metadata !{i32 17, i32 15, metadata !7, null} +!37 = metadata !{i32 17, i32 28, metadata !7, null} +!38 = metadata !{i32 19, i32 31, metadata !23, null} +!39 = metadata !{i32 20, i32 3, metadata !23, null} +!40 = metadata !{i32 21, i32 3, metadata !23, null} +!41 = metadata !{i32 4, i32 22, metadata !0, metadata !40} +!42 = metadata !{i32 4, i32 33, metadata !0, metadata !40} +!43 = metadata !{i32 4, i32 52, metadata !0, metadata !40} +!44 = metadata !{i32 6, i32 3, metadata !28, metadata !40} +!45 = metadata !{i32 22, i32 3, metadata !23, null} +!46 = metadata !{i32 23, i32 1, metadata !23, null} diff --git a/test/CodeGen/ARM/divmod.ll b/test/CodeGen/ARM/divmod.ll new file mode 100644 index 000000000000..34313aa89aae --- /dev/null +++ b/test/CodeGen/ARM/divmod.ll @@ -0,0 +1,58 @@ +; RUN: llc < %s -mtriple=arm-apple-ios | FileCheck %s + +define void @foo(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp { +entry: +; CHECK: foo: +; CHECK: bl ___divmodsi4 +; CHECK-NOT: bl ___divmodsi4 + %div = sdiv i32 %x, %y + store i32 %div, i32* %P, align 4 + %rem = srem i32 %x, %y + %arrayidx6 = getelementptr inbounds i32* %P, i32 1 + store i32 %rem, i32* %arrayidx6, align 4 + ret void +} + +define void @bar(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp { +entry: +; CHECK: bar: +; CHECK: bl ___udivmodsi4 +; CHECK-NOT: bl ___udivmodsi4 + %div = udiv i32 %x, %y + store i32 %div, i32* %P, align 4 + %rem = urem i32 %x, %y + %arrayidx6 = getelementptr inbounds i32* %P, i32 1 + store i32 %rem, i32* %arrayidx6, align 4 + ret void +} + +; rdar://9280991 +@flags = external unnamed_addr global i32 +@tabsize = external unnamed_addr global i32 + +define void @do_indent(i32 %cols) nounwind { +entry: +; CHECK: do_indent: + %0 = load i32* @flags, align 4 + %1 = and i32 %0, 67108864 + %2 = icmp eq i32 %1, 0 + br i1 %2, label %bb1, label %bb + +bb: +; CHECK: bl ___divmodsi4 + %3 = load i32* @tabsize, align 4 + %4 = srem i32 %cols, %3 + %5 = sdiv i32 %cols, %3 + %6 = tail call i32 @llvm.objectsize.i32(i8* null, i1 false) + %7 = tail call i8* @__memset_chk(i8* null, i32 9, i32 %5, i32 %6) nounwind + br label %bb1 + +bb1: + %line_indent_len.0 = phi i32 [ %4, %bb ], [ 0, %entry ] + %8 = getelementptr inbounds i8* null, i32 %line_indent_len.0 + store i8 0, i8* %8, align 1 + ret void +} + +declare i32 @llvm.objectsize.i32(i8*, i1) nounwind readnone +declare i8* @__memset_chk(i8*, i32, i32, i32) nounwind diff --git a/test/CodeGen/ARM/fabss.ll b/test/CodeGen/ARM/fabss.ll index f03282bdab7f..51efe51bf152 100644 --- a/test/CodeGen/ARM/fabss.ll +++ b/test/CodeGen/ARM/fabss.ll @@ -24,4 +24,4 @@ declare float @fabsf(float) ; CORTEXA8: test: ; CORTEXA8: vabs.f32 d1, d1 ; CORTEXA9: test: -; CORTEXA9: vabs.f32 s1, s1 +; CORTEXA9: vabs.f32 s{{.}}, s{{.}} diff --git a/test/CodeGen/ARM/fadds.ll b/test/CodeGen/ARM/fadds.ll index 749690e98d0f..e35103c045eb 100644 --- a/test/CodeGen/ARM/fadds.ll +++ b/test/CodeGen/ARM/fadds.ll @@ -20,4 +20,4 @@ entry: ; CORTEXA8: test: ; CORTEXA8: vadd.f32 d0, d1, d0 ; CORTEXA9: test: -; CORTEXA9: vadd.f32 s0, s1, s0 +; CORTEXA9: vadd.f32 s{{.}}, s{{.}}, s{{.}} diff --git a/test/CodeGen/ARM/fast-isel-pred.ll b/test/CodeGen/ARM/fast-isel-pred.ll new file mode 100644 index 000000000000..8de54ad5332b --- /dev/null +++ b/test/CodeGen/ARM/fast-isel-pred.ll @@ -0,0 +1,58 @@ +; RUN: llc -O0 -mtriple=armv7-apple-darwin < %s + +define i32 @main() nounwind ssp { +entry: + %retval = alloca i32, align 4 + %X = alloca <4 x i32>, align 16 + %Y = alloca <4 x float>, align 16 + store i32 0, i32* %retval + %tmp = load <4 x i32>* %X, align 16 + call void @__aa(<4 x i32> %tmp, i8* null, i32 3, <4 x float>* %Y) + %0 = load i32* %retval + ret i32 %0 +} + +define internal void @__aa(<4 x i32> %v, i8* %p, i32 %offset, <4 x float>* %constants) nounwind inlinehint ssp { +entry: + %__a.addr.i = alloca <4 x i32>, align 16 + %v.addr = alloca <4 x i32>, align 16 + %p.addr = alloca i8*, align 4 + %offset.addr = alloca i32, align 4 + %constants.addr = alloca <4 x float>*, align 4 + store <4 x i32> %v, <4 x i32>* %v.addr, align 16 + store i8* %p, i8** %p.addr, align 4 + store i32 %offset, i32* %offset.addr, align 4 + store <4 x float>* %constants, <4 x float>** %constants.addr, align 4 + %tmp = load <4 x i32>* %v.addr, align 16 + store <4 x i32> %tmp, <4 x i32>* %__a.addr.i, align 16 + %tmp.i = load <4 x i32>* %__a.addr.i, align 16 + %0 = bitcast <4 x i32> %tmp.i to <16 x i8> + %1 = bitcast <16 x i8> %0 to <4 x i32> + %vcvt.i = sitofp <4 x i32> %1 to <4 x float> + %tmp1 = load i8** %p.addr, align 4 + %tmp2 = load i32* %offset.addr, align 4 + %tmp3 = load <4 x float>** %constants.addr, align 4 + call void @__bb(<4 x float> %vcvt.i, i8* %tmp1, i32 %tmp2, <4 x float>* %tmp3) + ret void +} + +define internal void @__bb(<4 x float> %v, i8* %p, i32 %offset, <4 x float>* %constants) nounwind inlinehint ssp { +entry: + %v.addr = alloca <4 x float>, align 16 + %p.addr = alloca i8*, align 4 + %offset.addr = alloca i32, align 4 + %constants.addr = alloca <4 x float>*, align 4 + %data = alloca i64, align 4 + store <4 x float> %v, <4 x float>* %v.addr, align 16 + store i8* %p, i8** %p.addr, align 4 + store i32 %offset, i32* %offset.addr, align 4 + store <4 x float>* %constants, <4 x float>** %constants.addr, align 4 + %tmp = load i64* %data, align 4 + %tmp1 = load i8** %p.addr, align 4 + %tmp2 = load i32* %offset.addr, align 4 + %add.ptr = getelementptr i8* %tmp1, i32 %tmp2 + %0 = bitcast i8* %add.ptr to i64* + %arrayidx = getelementptr inbounds i64* %0, i32 0 + store i64 %tmp, i64* %arrayidx + ret void +} diff --git a/test/CodeGen/ARM/fast-isel-redefinition.ll b/test/CodeGen/ARM/fast-isel-redefinition.ll new file mode 100644 index 000000000000..08dcc64c9c84 --- /dev/null +++ b/test/CodeGen/ARM/fast-isel-redefinition.ll @@ -0,0 +1,11 @@ +; RUN: llc -O0 -regalloc=linearscan < %s +; This isn't exactly a useful set of command-line options, but check that it +; doesn't crash. (It was crashing because a register was getting redefined.) + +target triple = "thumbv7-apple-macosx10.6.7" + +define i32 @f(i32* %x) nounwind ssp { + %y = getelementptr inbounds i32* %x, i32 5000 + %tmp103 = load i32* %y, align 4 + ret i32 %tmp103 +} diff --git a/test/CodeGen/ARM/fast-isel-static.ll b/test/CodeGen/ARM/fast-isel-static.ll index 8f58480be164..2d79674028ca 100644 --- a/test/CodeGen/ARM/fast-isel-static.ll +++ b/test/CodeGen/ARM/fast-isel-static.ll @@ -24,7 +24,7 @@ entry: store float 0.000000e+00, float* %ztot, align 4 store float 1.000000e+00, float* %z, align 4 ; CHECK-LONG: blx r2 -; CHECK-NORM: blx _myadd +; CHECK-NORM: bl _myadd call void @myadd(float* %ztot, float* %z) ret i32 0 } diff --git a/test/CodeGen/ARM/fast-isel.ll b/test/CodeGen/ARM/fast-isel.ll index dd806ec6f1ae..6aad92fbc6a4 100644 --- a/test/CodeGen/ARM/fast-isel.ll +++ b/test/CodeGen/ARM/fast-isel.ll @@ -1,8 +1,7 @@ -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-apple-darwin -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=thumbv7-apple-darwin +; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB ; Very basic fast-isel functionality. - define i32 @add(i32 %a, i32 %b) nounwind { entry: %a.addr = alloca i32, align 4 @@ -13,4 +12,52 @@ entry: %tmp1 = load i32* %b.addr %add = add nsw i32 %tmp, %tmp1 ret i32 %add -}
\ No newline at end of file +} + +; Check truncate to bool +define void @test1(i32 %tmp) nounwind { +entry: +%tobool = trunc i32 %tmp to i1 +br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry +call void @test1(i32 0) +br label %if.end + +if.end: ; preds = %if.then, %entry +ret void +; ARM: test1: +; ARM: tst r0, #1 +; THUMB: test1: +; THUMB: tst.w r0, #1 +} + +; Check some simple operations with immediates +define void @test2(i32 %tmp, i32* %ptr) nounwind { +; THUMB: test2: +; ARM: test2: + +b1: + %a = add i32 %tmp, 4096 + store i32 %a, i32* %ptr + br label %b2 + +; THUMB: add.w {{.*}} #4096 +; ARM: add {{.*}} #1, #20 + +b2: + %b = add i32 %tmp, 4095 + store i32 %b, i32* %ptr + br label %b3 +; THUMB: addw {{.*}} #4095 +; ARM: movw {{.*}} #4095 +; ARM: add + +b3: + %c = or i32 %tmp, 4 + store i32 %c, i32* %ptr + ret void + +; THUMB: orr {{.*}} #4 +; ARM: orr {{.*}} #4 +} diff --git a/test/CodeGen/ARM/fcopysign.ll b/test/CodeGen/ARM/fcopysign.ll index d30e3ebf50a5..f241c2681cbf 100644 --- a/test/CodeGen/ARM/fcopysign.ll +++ b/test/CodeGen/ARM/fcopysign.ll @@ -40,5 +40,37 @@ entry: ret double %1 } +; rdar://9059537 +define i32 @test4() ssp { +entry: +; SOFT: test4: +; SOFT: vmov.f64 [[REG4:(d[0-9]+)]], #1.000000e+00 +; This S-reg must be the first sub-reg of the last D-reg on vbsl. +; SOFT: vcvt.f32.f64 {{s1?[02468]}}, [[REG4]] +; SOFT: vshr.u64 [[REG4]], [[REG4]], #32 +; SOFT: vmov.i32 [[REG5:(d[0-9]+)]], #0x80000000 +; SOFT: vbsl [[REG5]], [[REG4]], {{d[0-9]+}} + %call80 = tail call double @copysign(double 1.000000e+00, double undef) + %conv81 = fptrunc double %call80 to float + %tmp88 = bitcast float %conv81 to i32 + ret i32 %tmp88 +} + +; rdar://9287902 +define float @test5() nounwind { +entry: +; SOFT: test5: +; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000 +; SOFT: vmov [[REG7:(d[0-9]+)]], r0, r1 +; SOFT: vshr.u64 [[REG7]], [[REG7]], #32 +; SOFT: vbsl [[REG6]], [[REG7]], + %0 = tail call double (...)* @bar() nounwind + %1 = fptrunc double %0 to float + %2 = tail call float @copysignf(float 5.000000e-01, float %1) nounwind readnone + %3 = fadd float %1, %2 + ret float %3 +} + +declare double @bar(...) declare double @copysign(double, double) nounwind declare float @copysignf(float, float) nounwind diff --git a/test/CodeGen/ARM/fdivs.ll b/test/CodeGen/ARM/fdivs.ll index 0c3149579297..31c1ca940502 100644 --- a/test/CodeGen/ARM/fdivs.ll +++ b/test/CodeGen/ARM/fdivs.ll @@ -20,4 +20,4 @@ entry: ; CORTEXA8: test: ; CORTEXA8: vdiv.f32 s0, s1, s0 ; CORTEXA9: test: -; CORTEXA9: vdiv.f32 s0, s1, s0 +; CORTEXA9: vdiv.f32 s{{.}}, s{{.}}, s{{.}} diff --git a/test/CodeGen/ARM/fmacs.ll b/test/CodeGen/ARM/fmacs.ll index fb83ef626af6..b63f609e755a 100644 --- a/test/CodeGen/ARM/fmacs.ll +++ b/test/CodeGen/ARM/fmacs.ll @@ -1,6 +1,8 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8 +; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=A9 +; RUN: llc < %s -mtriple=arm-linux-gnueabi -mcpu=cortex-a9 -float-abi=hard | FileCheck %s -check-prefix=HARD define float @t1(float %acc, float %a, float %b) { entry: @@ -49,3 +51,54 @@ entry: %1 = fadd float %0, %acc ret float %1 } + +; It's possible to make use of fp vmla / vmls on Cortex-A9. +; rdar://8659675 +define void @t4(float %acc1, float %a, float %b, float %acc2, float %c, float* %P1, float* %P2) { +entry: +; A8: t4: +; A8: vmul.f32 +; A8: vmul.f32 +; A8: vadd.f32 +; A8: vadd.f32 + +; Two vmla with now RAW hazard +; A9: t4: +; A9: vmla.f32 +; A9: vmla.f32 + +; HARD: t4: +; HARD: vmla.f32 s0, s1, s2 +; HARD: vmla.f32 s3, s1, s4 + %0 = fmul float %a, %b + %1 = fadd float %acc1, %0 + %2 = fmul float %a, %c + %3 = fadd float %acc2, %2 + store float %1, float* %P1 + store float %3, float* %P2 + ret void +} + +define float @t5(float %a, float %b, float %c, float %d, float %e) { +entry: +; A8: t5: +; A8: vmul.f32 +; A8: vmul.f32 +; A8: vadd.f32 +; A8: vadd.f32 + +; A9: t5: +; A9: vmla.f32 +; A9: vmul.f32 +; A9: vadd.f32 + +; HARD: t5: +; HARD: vmla.f32 s4, s0, s1 +; HARD: vmul.f32 s0, s2, s3 +; HARD: vadd.f32 s0, s4, s0 + %0 = fmul float %a, %b + %1 = fadd float %e, %0 + %2 = fmul float %c, %d + %3 = fadd float %1, %2 + ret float %3 +} diff --git a/test/CodeGen/ARM/fmuls.ll b/test/CodeGen/ARM/fmuls.ll index ef4e3e52818e..bc118b8cb226 100644 --- a/test/CodeGen/ARM/fmuls.ll +++ b/test/CodeGen/ARM/fmuls.ll @@ -20,4 +20,4 @@ entry: ; CORTEXA8: test: ; CORTEXA8: vmul.f32 d0, d1, d0 ; CORTEXA9: test: -; CORTEXA9: vmul.f32 s0, s1, s0 +; CORTEXA9: vmul.f32 s{{.}}, s{{.}}, s{{.}} diff --git a/test/CodeGen/ARM/fnmscs.ll b/test/CodeGen/ARM/fnmscs.ll index 76c806761f75..9facf20fee7e 100644 --- a/test/CodeGen/ARM/fnmscs.ll +++ b/test/CodeGen/ARM/fnmscs.ll @@ -1,6 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8 +; RUN: llc < %s -march=arm -mcpu=cortex-a8 -regalloc=basic | FileCheck %s -check-prefix=A8 define float @t1(float %acc, float %a, float %b) nounwind { entry: @@ -11,8 +12,8 @@ entry: ; NEON: vnmla.f32 ; A8: t1: -; A8: vnmul.f32 s0, s{{[01]}}, s{{[01]}} -; A8: vsub.f32 d0, d0, d1 +; A8: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}} +; A8: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}} %0 = fmul float %a, %b %1 = fsub float -0.0, %0 %2 = fsub float %1, %acc @@ -28,8 +29,8 @@ entry: ; NEON: vnmla.f32 ; A8: t2: -; A8: vnmul.f32 s0, s{{[01]}}, s{{[01]}} -; A8: vsub.f32 d0, d0, d1 +; A8: vnmul.f32 s{{[0123]}}, s{{[0123]}}, s{{[0123]}} +; A8: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}} %0 = fmul float %a, %b %1 = fmul float -1.0, %0 %2 = fsub float %1, %acc @@ -45,8 +46,8 @@ entry: ; NEON: vnmla.f64 ; A8: t3: -; A8: vnmul.f64 d16, d1{{[67]}}, d1{{[67]}} -; A8: vsub.f64 d16, d16, d17 +; A8: vnmul.f64 d1{{[67]}}, d1{{[67]}}, d1{{[67]}} +; A8: vsub.f64 d1{{[67]}}, d1{{[67]}}, d1{{[67]}} %0 = fmul double %a, %b %1 = fsub double -0.0, %0 %2 = fsub double %1, %acc @@ -62,8 +63,8 @@ entry: ; NEON: vnmla.f64 ; A8: t4: -; A8: vnmul.f64 d16, d1{{[67]}}, d1{{[67]}} -; A8: vsub.f64 d16, d16, d17 +; A8: vnmul.f64 d1{{[67]}}, d1{{[67]}}, d1{{[67]}} +; A8: vsub.f64 d1{{[67]}}, d1{{[67]}}, d1{{[67]}} %0 = fmul double %a, %b %1 = fmul double -1.0, %0 %2 = fsub double %1, %acc diff --git a/test/CodeGen/ARM/fp-arg-shuffle.ll b/test/CodeGen/ARM/fp-arg-shuffle.ll new file mode 100644 index 000000000000..ae02b792e4d6 --- /dev/null +++ b/test/CodeGen/ARM/fp-arg-shuffle.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s -march=arm -mattr=+neon -float-abi=soft | FileCheck %s + +; CHECK: function1 +; CHECK-NOT: vmov +define double @function1(double %a, double %b, double %c, double %d, double %e, double %f) nounwind noinline ssp { +entry: + %call = tail call double @function2(double %f, double %e, double %d, double %c, double %b, double %a) nounwind + ret double %call +} + +declare double @function2(double, double, double, double, double, double) diff --git a/test/CodeGen/ARM/fp.ll b/test/CodeGen/ARM/fp.ll index b6e9c3c22e75..8ef45f2bbc97 100644 --- a/test/CodeGen/ARM/fp.ll +++ b/test/CodeGen/ARM/fp.ll @@ -51,7 +51,7 @@ entry: define float @h2() { ;CHECK: h2: -;CHECK: mov r0, #254, 10 +;CHECK: mov r0, #254, #10 entry: ret float 1.000000e+00 } diff --git a/test/CodeGen/ARM/fp_convert.ll b/test/CodeGen/ARM/fp_convert.ll index 1ef9f7f32164..86c06f1ddd9e 100644 --- a/test/CodeGen/ARM/fp_convert.ll +++ b/test/CodeGen/ARM/fp_convert.ll @@ -5,7 +5,7 @@ define i32 @test1(float %a, float %b) { ; VFP2: test1: -; VFP2: vcvt.s32.f32 s0, s0 +; VFP2: vcvt.s32.f32 s{{.}}, s{{.}} ; NEON: test1: ; NEON: vcvt.s32.f32 d0, d0 entry: @@ -16,7 +16,7 @@ entry: define i32 @test2(float %a, float %b) { ; VFP2: test2: -; VFP2: vcvt.u32.f32 s0, s0 +; VFP2: vcvt.u32.f32 s{{.}}, s{{.}} ; NEON: test2: ; NEON: vcvt.u32.f32 d0, d0 entry: @@ -27,7 +27,7 @@ entry: define float @test3(i32 %a, i32 %b) { ; VFP2: test3: -; VFP2: vcvt.f32.u32 s0, s0 +; VFP2: vcvt.f32.u32 s{{.}}, s{{.}} ; NEON: test3: ; NEON: vcvt.f32.u32 d0, d0 entry: @@ -38,7 +38,7 @@ entry: define float @test4(i32 %a, i32 %b) { ; VFP2: test4: -; VFP2: vcvt.f32.s32 s0, s0 +; VFP2: vcvt.f32.s32 s{{.}}, s{{.}} ; NEON: test4: ; NEON: vcvt.f32.s32 d0, d0 entry: diff --git a/test/CodeGen/ARM/fpcmp-opt.ll b/test/CodeGen/ARM/fpcmp-opt.ll index 65b921bdf655..7c0dd0e12a79 100644 --- a/test/CodeGen/ARM/fpcmp-opt.ll +++ b/test/CodeGen/ARM/fpcmp-opt.ll @@ -37,7 +37,7 @@ define arm_apcscc i32 @t2(double* %a, double* %b) nounwind { entry: ; FINITE: t2: ; FINITE-NOT: vldr -; FINITE: ldrd r0, [r0] +; FINITE: ldrd r0, r1, [r0] ; FINITE-NOT: b LBB ; FINITE: cmp r0, #0 ; FINITE: cmpeq r1, #0 diff --git a/test/CodeGen/ARM/ifcvt10.ll b/test/CodeGen/ARM/ifcvt10.ll index 75428ac21655..18f87bfc2e71 100644 --- a/test/CodeGen/ARM/ifcvt10.ll +++ b/test/CodeGen/ARM/ifcvt10.ll @@ -9,9 +9,9 @@ entry: ; CHECK: t: ; CHECK: vpop {d8} ; CHECK-NOT: vpopne -; CHECK: ldmia sp!, {r7, pc} +; CHECK: pop {r7, pc} ; CHECK: vpop {d8} -; CHECK: ldmia sp!, {r7, pc} +; CHECK: pop {r7, pc} br i1 undef, label %if.else, label %if.then if.then: ; preds = %entry diff --git a/test/CodeGen/ARM/ifcvt5.ll b/test/CodeGen/ARM/ifcvt5.ll index bca2ae346a6f..3615055f8b29 100644 --- a/test/CodeGen/ARM/ifcvt5.ll +++ b/test/CodeGen/ARM/ifcvt5.ll @@ -11,7 +11,7 @@ entry: define i32 @t1(i32 %a, i32 %b) { ; CHECK: t1: -; CHECK: ldmialt sp!, {r7, pc} +; CHECK: poplt {r7, pc} entry: %tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1] br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock diff --git a/test/CodeGen/ARM/ifcvt6.ll b/test/CodeGen/ARM/ifcvt6.ll index 5edf32fd1af6..232765768550 100644 --- a/test/CodeGen/ARM/ifcvt6.ll +++ b/test/CodeGen/ARM/ifcvt6.ll @@ -3,7 +3,7 @@ define void @foo(i32 %X, i32 %Y) { entry: ; CHECK: cmpne -; CHECK: ldmiahi sp! +; CHECK: pophi %tmp1 = icmp ult i32 %X, 4 ; <i1> [#uses=1] %tmp4 = icmp eq i32 %Y, 0 ; <i1> [#uses=1] %tmp7 = or i1 %tmp4, %tmp1 ; <i1> [#uses=1] diff --git a/test/CodeGen/ARM/ifcvt7.ll b/test/CodeGen/ARM/ifcvt7.ll index 62e13557cfdc..476ed4d47c64 100644 --- a/test/CodeGen/ARM/ifcvt7.ll +++ b/test/CodeGen/ARM/ifcvt7.ll @@ -6,7 +6,7 @@ define fastcc i32 @CountTree(%struct.quad_struct* %tree) { ; CHECK: cmpeq ; CHECK: moveq -; CHECK: ldmiaeq sp! +; CHECK: popeq entry: br label %tailrecurse diff --git a/test/CodeGen/ARM/ifcvt8.ll b/test/CodeGen/ARM/ifcvt8.ll index 5fdfc4ea6805..ca9a5c63cda6 100644 --- a/test/CodeGen/ARM/ifcvt8.ll +++ b/test/CodeGen/ARM/ifcvt8.ll @@ -5,7 +5,7 @@ declare void @abort() define fastcc void @t(%struct.SString* %word, i8 signext %c) { -; CHECK: ldmiane sp! +; CHECK: popne entry: %tmp1 = icmp eq %struct.SString* %word, null ; <i1> [#uses=1] br i1 %tmp1, label %cond_true, label %cond_false diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll index 0aac9d16ec6c..f0ab9dd7ea00 100644 --- a/test/CodeGen/ARM/indirectbr.ll +++ b/test/CodeGen/ARM/indirectbr.ll @@ -14,15 +14,15 @@ entry: %1 = icmp eq i8* %0, null ; <i1> [#uses=1] ; indirect branch gets duplicated here ; ARM: bx -; THUMB: mov pc, r1 -; THUMB2: mov pc, r2 +; THUMB: mov pc, +; THUMB2: mov pc, br i1 %1, label %bb3, label %bb2 bb2: ; preds = %entry, %bb3 %gotovar.4.0 = phi i8* [ %gotovar.4.0.pre, %bb3 ], [ %0, %entry ] ; <i8*> [#uses=1] ; ARM: bx -; THUMB: mov pc, r1 -; THUMB2: mov pc, r2 +; THUMB: mov pc, +; THUMB2: mov pc, indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1] bb3: ; preds = %entry @@ -42,20 +42,23 @@ L3: ; preds = %L4, %bb2 br label %L2 L2: ; preds = %L3, %bb2 +; THUMB: muls %res.2 = phi i32 [ %res.1, %L3 ], [ 1, %bb2 ] ; <i32> [#uses=1] %phitmp = mul i32 %res.2, 6 ; <i32> [#uses=1] br label %L1 L1: ; preds = %L2, %bb2 %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1] -; ARM: ldr r1, LCPI -; ARM: add r1, pc, r1 -; ARM: str r1 -; THUMB: ldr.n r2, LCPI -; THUMB: add r2, pc -; THUMB: str r2 -; THUMB2: ldr.n r2, LCPI -; THUMB2-NEXT: str r2 +; ARM: ldr [[R1:r[0-9]+]], LCPI +; ARM: add [[R1b:r[0-9]+]], pc, [[R1]] +; ARM: str [[R1b]] +; THUMB: ldr.n +; THUMB: add +; THUMB: ldr.n [[R2:r[0-9]+]], LCPI +; THUMB: add [[R2]], pc +; THUMB: str [[R2]] +; THUMB2: ldr.n [[R2:r[0-9]+]], LCPI +; THUMB2-NEXT: str{{(.w)?}} [[R2]] store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4 ret i32 %res.3 } diff --git a/test/CodeGen/ARM/inlineasm3.ll b/test/CodeGen/ARM/inlineasm3.ll index 9f77ad1f794c..9d6eba85301e 100644 --- a/test/CodeGen/ARM/inlineasm3.ll +++ b/test/CodeGen/ARM/inlineasm3.ll @@ -6,7 +6,7 @@ define void @t() nounwind { entry: ; CHECK: vmov.I64 q15, #0 -; CHECK: vmov.32 d30[0], r0 +; CHECK: vmov.32 d30[0], ; CHECK: vmov q8, q15 %tmp = alloca %struct.int32x4_t, align 16 call void asm sideeffect "vmov.I64 q15, #0\0Avmov.32 d30[0], $1\0Avmov ${0:q}, q15\0A", "=*w,r,~{d31},~{d30}"(%struct.int32x4_t* %tmp, i32 8192) nounwind diff --git a/test/CodeGen/ARM/int-to-fp.ll b/test/CodeGen/ARM/int-to-fp.ll new file mode 100644 index 000000000000..889b14919840 --- /dev/null +++ b/test/CodeGen/ARM/int-to-fp.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10.0.0" + +; CHECK: sint_to_fp +; CHECK: vmovl.s16 +; CHECK: vcvt.f32.s32 +define <4 x float> @sint_to_fp(<4 x i16> %x) nounwind ssp { + %a = sitofp <4 x i16> %x to <4 x float> + ret <4 x float> %a +} + +; CHECK: uint_to_fp +; CHECK: vmovl.u16 +; CHECK: vcvt.f32.u32 +define <4 x float> @uint_to_fp(<4 x i16> %x) nounwind ssp { + %a = uitofp <4 x i16> %x to <4 x float> + ret <4 x float> %a +} diff --git a/test/CodeGen/ARM/ldm.ll b/test/CodeGen/ARM/ldm.ll index 2f1b85ebbb04..db78fd06ab2d 100644 --- a/test/CodeGen/ARM/ldm.ll +++ b/test/CodeGen/ARM/ldm.ll @@ -5,9 +5,9 @@ define i32 @t1() { ; CHECK: t1: -; CHECK: ldmia +; CHECK: pop ; V4T: t1: -; V4T: ldmia +; V4T: pop %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0) ; <i32> [#uses=1] %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1] %tmp4 = tail call i32 @f1( i32 %tmp, i32 %tmp3 ) ; <i32> [#uses=1] @@ -16,9 +16,9 @@ define i32 @t1() { define i32 @t2() { ; CHECK: t2: -; CHECK: ldmia +; CHECK: pop ; V4T: t2: -; V4T: ldmia +; V4T: pop %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1] %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1] %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 4) ; <i32> [#uses=1] @@ -29,7 +29,7 @@ define i32 @t2() { define i32 @t3() { ; CHECK: t3: ; CHECK: ldmib -; CHECK: ldmia sp! +; CHECK: pop ; V4T: t3: ; V4T: ldmib ; V4T: pop diff --git a/test/CodeGen/ARM/ldrd.ll b/test/CodeGen/ARM/ldrd.ll index 895562a1d31e..8010f20689be 100644 --- a/test/CodeGen/ARM/ldrd.ll +++ b/test/CodeGen/ARM/ldrd.ll @@ -1,19 +1,21 @@ -; RUN: llc < %s -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=V6 -; RUN: llc < %s -mtriple=armv5-apple-darwin | FileCheck %s -check-prefix=V5 -; RUN: llc < %s -mtriple=armv6-eabi | FileCheck %s -check-prefix=EABI +; RUN: llc < %s -mtriple=armv6-apple-darwin -regalloc=linearscan | FileCheck %s -check-prefix=V6 +; RUN: llc < %s -mtriple=armv5-apple-darwin -regalloc=linearscan | FileCheck %s -check-prefix=V5 +; RUN: llc < %s -mtriple=armv6-eabi -regalloc=linearscan | FileCheck %s -check-prefix=EABI ; rdar://r6949835 +; Magic ARM pair hints works best with linearscan. + @b = external global i64* define i64 @t(i64 %a) nounwind readonly { entry: -;V6: ldrd r2, [r2] +;V6: ldrd r2, r3, [r2] -;V5: ldr r3, [r2] -;V5: ldr r2, [r2, #4] +;V5: ldr r{{[0-9]+}}, [r2] +;V5: ldr r{{[0-9]+}}, [r2, #4] -;EABI: ldr r3, [r2] -;EABI: ldr r2, [r2, #4] +;EABI: ldr r{{[0-9]+}}, [r2] +;EABI: ldr r{{[0-9]+}}, [r2, #4] %0 = load i64** @b, align 4 %1 = load i64* %0, align 4 diff --git a/test/CodeGen/ARM/long.ll b/test/CodeGen/ARM/long.ll index 74f8d783377d..e401dca1ca80 100644 --- a/test/CodeGen/ARM/long.ll +++ b/test/CodeGen/ARM/long.ll @@ -14,14 +14,14 @@ entry: define i64 @f3() { ; CHECK: f3: -; CHECK: mvn r0, #2, 2 +; CHECK: mvn r0, #2, #2 entry: ret i64 2147483647 } define i64 @f4() { ; CHECK: f4: -; CHECK: mov r0, #2, 2 +; CHECK: mov r0, #2, #2 entry: ret i64 2147483648 } @@ -29,7 +29,7 @@ entry: define i64 @f5() { ; CHECK: f5: ; CHECK: mvn r0, #0 -; CHECK: mvn r1, #2, 2 +; CHECK: mvn r1, #2, #2 entry: ret i64 9223372036854775807 } diff --git a/test/CodeGen/ARM/long_shift.ll b/test/CodeGen/ARM/long_shift.ll index 5e4f5730f8d2..d5aac2e3ddaf 100644 --- a/test/CodeGen/ARM/long_shift.ll +++ b/test/CodeGen/ARM/long_shift.ll @@ -24,9 +24,10 @@ define i32 @f2(i64 %x, i64 %y) { ; CHECK: f2 ; CHECK: lsr{{.*}}r2 ; CHECK-NEXT: rsb r3, r2, #32 -; CHECK-NEXT: subs r2, r2, #32 +; CHECK-NEXT: sub r2, r2, #32 +; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: orr r0, r0, r1, lsl r3 -; CHECK-NEXT: movge r0, r1, asr r2 +; CHECK-NEXT: asrge r0, r1, r2 %a = ashr i64 %x, %y %b = trunc i64 %a to i32 ret i32 %b @@ -36,9 +37,10 @@ define i32 @f3(i64 %x, i64 %y) { ; CHECK: f3 ; CHECK: lsr{{.*}}r2 ; CHECK-NEXT: rsb r3, r2, #32 -; CHECK-NEXT: subs r2, r2, #32 +; CHECK-NEXT: sub r2, r2, #32 +; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: orr r0, r0, r1, lsl r3 -; CHECK-NEXT: movge r0, r1, lsr r2 +; CHECK-NEXT: lsrge r0, r1, r2 %a = lshr i64 %x, %y %b = trunc i64 %a to i32 ret i32 %b diff --git a/test/CodeGen/ARM/lsr-code-insertion.ll b/test/CodeGen/ARM/lsr-code-insertion.ll index 1bbb96deeefe..153fd8fe34e4 100644 --- a/test/CodeGen/ARM/lsr-code-insertion.ll +++ b/test/CodeGen/ARM/lsr-code-insertion.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -stats |& grep {39.*Number of machine instrs printed} -; RUN: llc < %s -stats |& not grep {.*Number of re-materialization} +; RUN: llc < %s | FileCheck %s ; This test really wants to check that the resultant "cond_true" block only ; has a single store in it, and that cond_true55 only has code to materialize ; the constant and do a store. We do *not* want something like this: @@ -8,6 +7,11 @@ ; add r8, r0, r6 ; str r10, [r8, #+4] ; +; CHECK: ldr [[R6:r[0-9*]+]], LCP +; CHECK: cmp {{.*}}, [[R6]] +; CHECK: ldrle +; CHECK-NEXT: strle + target triple = "arm-apple-darwin8" define void @foo(i32* %mc, i32* %mpp, i32* %ip, i32* %dpp, i32* %tpmm, i32 %M, i32* %tpim, i32* %tpdm, i32* %bp, i32* %ms, i32 %xmb) { diff --git a/test/CodeGen/ARM/lsr-on-unrolled-loops.ll b/test/CodeGen/ARM/lsr-on-unrolled-loops.ll index 9882690da268..c1318ec31f58 100644 --- a/test/CodeGen/ARM/lsr-on-unrolled-loops.ll +++ b/test/CodeGen/ARM/lsr-on-unrolled-loops.ll @@ -4,11 +4,6 @@ ; constant offset addressing, so that each of the following stores ; uses the same register. -; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-128] -; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-96] -; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-64] -; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-32] -; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}] ; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #32] ; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #64] ; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #96] diff --git a/test/CodeGen/ARM/memcpy-inline.ll b/test/CodeGen/ARM/memcpy-inline.ll index ed20c32dc0d5..5bae037cafb3 100644 --- a/test/CodeGen/ARM/memcpy-inline.ll +++ b/test/CodeGen/ARM/memcpy-inline.ll @@ -1,9 +1,11 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin | grep ldmia -; RUN: llc < %s -mtriple=arm-apple-darwin | grep stmia -; RUN: llc < %s -mtriple=arm-apple-darwin | grep ldrb -; RUN: llc < %s -mtriple=arm-apple-darwin | grep ldrh +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -regalloc=linearscan -disable-post-ra | FileCheck %s - %struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } +; The ARM magic hinting works best with linear scan. +; CHECK: ldrd +; CHECK: strd +; CHECK: ldrb + +%struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } @src = external global %struct.x @dst = external global %struct.x diff --git a/test/CodeGen/ARM/neon_div.ll b/test/CodeGen/ARM/neon_div.ll index e33797079093..de48feeb9ec2 100644 --- a/test/CodeGen/ARM/neon_div.ll +++ b/test/CodeGen/ARM/neon_div.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+neon -pre-RA-sched=source | FileCheck %s define <8 x i8> @sdivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: vrecpe.f32 diff --git a/test/CodeGen/ARM/neon_shift.ll b/test/CodeGen/ARM/neon_shift.ll new file mode 100644 index 000000000000..340f220fb362 --- /dev/null +++ b/test/CodeGen/ARM/neon_shift.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s + +; <rdar://problem/9055897> +define <4 x i16> @t1(<4 x i32> %a) nounwind { +entry: +; CHECK: vqrshrn.s32 d{{[0-9]+}}, q{{[0-9]*}}, #13 + %x = tail call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %a, <4 x i32> <i32 -13, i32 -13, i32 -13, i32 -13>) + ret <4 x i16> %x +} + +declare <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone diff --git a/test/CodeGen/ARM/peephole-bitcast.ll b/test/CodeGen/ARM/peephole-bitcast.ll new file mode 100644 index 000000000000..e670a5be3bca --- /dev/null +++ b/test/CodeGen/ARM/peephole-bitcast.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s -march=arm -mcpu=cortex-a8 -regalloc=linearscan | FileCheck %s + +; vmov s0, r0 + vmov r0, s0 should have been optimized away. +; rdar://9104514 + +; Peephole leaves a dead vmovsr instruction behind, and depends on linear scan +; to remove it. + +define void @t(float %x) nounwind ssp { +entry: +; CHECK: t: +; CHECK-NOT: vmov +; CHECK: bl + %0 = bitcast float %x to i32 + %cmp = icmp ult i32 %0, 2139095039 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @doSomething(float %x) nounwind + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +declare void @doSomething(float) diff --git a/test/CodeGen/ARM/prefetch.ll b/test/CodeGen/ARM/prefetch.ll index 895b27b749db..95f082aa9385 100644 --- a/test/CodeGen/ARM/prefetch.ll +++ b/test/CodeGen/ARM/prefetch.ll @@ -1,10 +1,15 @@ ; RUN: llc < %s -march=thumb -mattr=-thumb2 | not grep pld -; RUN: llc < %s -march=thumb -mattr=+v7a | FileCheck %s -check-prefix=THUMB2 -; RUN: llc < %s -march=arm -mattr=+v7a,+mp | FileCheck %s -check-prefix=ARM-MP +; RUN: llc < %s -march=thumb -mattr=+v7a | FileCheck %s -check-prefix=THUMB2 +; RUN: llc < %s -march=arm -mattr=+v7a | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -march=arm -mcpu=cortex-a9-mp | FileCheck %s -check-prefix=ARM-MP ; rdar://8601536 define void @t1(i8* %ptr) nounwind { entry: +; ARM: t1: +; ARM-NOT: pldw [r0] +; ARM: pld [r0] + ; ARM-MP: t1: ; ARM-MP: pldw [r0] ; ARM-MP: pld [r0] @@ -19,8 +24,8 @@ entry: define void @t2(i8* %ptr) nounwind { entry: -; ARM-MP: t2: -; ARM-MP: pld [r0, #1023] +; ARM: t2: +; ARM: pld [r0, #1023] ; THUMB2: t2: ; THUMB2: pld [r0, #1023] @@ -31,8 +36,8 @@ entry: define void @t3(i32 %base, i32 %offset) nounwind { entry: -; ARM-MP: t3: -; ARM-MP: pld [r0, r1, lsr #2] +; ARM: t3: +; ARM: pld [r0, r1, lsr #2] ; THUMB2: t3: ; THUMB2: lsrs r1, r1, #2 @@ -46,8 +51,8 @@ entry: define void @t4(i32 %base, i32 %offset) nounwind { entry: -; ARM-MP: t4: -; ARM-MP: pld [r0, r1, lsl #2] +; ARM: t4: +; ARM: pld [r0, r1, lsl #2] ; THUMB2: t4: ; THUMB2: pld [r0, r1, lsl #2] diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll index 53214fd4c302..d350937c683e 100644 --- a/test/CodeGen/ARM/reg_sequence.ll +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -march=arm -mcpu=cortex-a8 -regalloc=basic | FileCheck %s ; Implementing vld / vst as REG_SEQUENCE eliminates the extra vmov's. %struct.int16x8_t = type { <8 x i16> } @@ -123,9 +124,9 @@ return1: return2: ; CHECK: %return2 ; CHECK: vadd.i32 -; CHECK: vmov q9, q11 +; CHECK: vmov {{q[0-9]+}}, {{q[0-9]+}} ; CHECK-NOT: vmov -; CHECK: vst2.32 {d16, d17, d18, d19} +; CHECK: vst2.32 {d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}} %tmp100 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1] %tmp101 = extractvalue %struct.__neon_int32x4x2_t %tmp5, 1 ; <<4 x i32>> [#uses=1] %tmp102 = add <4 x i32> %tmp100, %tmp101 ; <<4 x i32>> [#uses=1] @@ -137,9 +138,10 @@ return2: define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind { ; CHECK: t5: ; CHECK: vldmia -; CHECK: vmov q9, q8 +; How can FileCheck match Q and D registers? We need a lisp interpreter. +; CHECK: vmov {{q[0-9]+}}, {{q[0-9]+}} ; CHECK-NOT: vmov -; CHECK: vld2.16 {d16[1], d18[1]}, [r0] +; CHECK: vld2.16 {d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0] ; CHECK-NOT: vmov ; CHECK: vadd.i16 %tmp0 = bitcast i16* %A to i8* ; <i8*> [#uses=1] @@ -154,8 +156,8 @@ define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind { define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind { ; CHECK: t6: ; CHECK: vldr.64 -; CHECK: vmov d17, d16 -; CHECK-NEXT: vld2.8 {d16[1], d17[1]} +; CHECK: vmov d[[D0:[0-9]+]], d[[D1:[0-9]+]] +; CHECK-NEXT: vld2.8 {d[[D1]][1], d[[D0]][1]} %tmp1 = load <8 x i8>* %B ; <<8 x i8>> [#uses=2] %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) ; <%struct.__neon_int8x8x2_t> [#uses=2] %tmp3 = extractvalue %struct.__neon_int8x8x2_t %tmp2, 0 ; <<8 x i8>> [#uses=1] @@ -169,10 +171,10 @@ entry: ; CHECK: t7: ; CHECK: vld2.32 ; CHECK: vst2.32 -; CHECK: vld1.32 {d16, d17}, -; CHECK: vmov q9, q8 +; CHECK: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, +; CHECK: vmov q[[Q0:[0-9]+]], q[[Q1:[0-9]+]] ; CHECK-NOT: vmov -; CHECK: vuzp.32 q8, q9 +; CHECK: vuzp.32 q[[Q1]], q[[Q0]] ; CHECK: vst1.32 %0 = bitcast i32* %iptr to i8* ; <i8*> [#uses=2] %1 = tail call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2.v4i32(i8* %0, i32 1) ; <%struct.__neon_int32x4x2_t> [#uses=2] @@ -271,7 +273,7 @@ define arm_aapcs_vfpcc i32 @t10() nounwind { entry: ; CHECK: t10: ; CHECK: vmul.f32 q8, q8, d0[0] -; CHECK: vmov.i32 q9, #0x3F000000 +; CHECK: vmov.i32 q[[Q0:[0-9]+]], #0x3F000000 ; CHECK: vadd.f32 q8, q8, q8 %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] %1 = insertelement <4 x float> %0, float undef, i32 1 ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/ARM/rev.ll b/test/CodeGen/ARM/rev.ll index 687bf8834c9f..4170ff3071ad 100644 --- a/test/CodeGen/ARM/rev.ll +++ b/test/CodeGen/ARM/rev.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+v6 | FileCheck %s -define i32 @test1(i32 %X) { +define i32 @test1(i32 %X) nounwind { ; CHECK: test1 ; CHECK: rev16 r0, r0 %tmp1 = lshr i32 %X, 8 @@ -16,7 +16,7 @@ define i32 @test1(i32 %X) { ret i32 %tmp14 } -define i32 @test2(i32 %X) { +define i32 @test2(i32 %X) nounwind { ; CHECK: test2 ; CHECK: revsh r0, r0 %tmp1 = lshr i32 %X, 8 @@ -28,3 +28,29 @@ define i32 @test2(i32 %X) { %tmp5.upgrd.2 = sext i16 %tmp5 to i32 ret i32 %tmp5.upgrd.2 } + +; rdar://9147637 +define i32 @test3(i16 zeroext %a) nounwind { +entry: +; CHECK: test3: +; CHECK: revsh r0, r0 + %0 = tail call i16 @llvm.bswap.i16(i16 %a) + %1 = sext i16 %0 to i32 + ret i32 %1 +} + +declare i16 @llvm.bswap.i16(i16) nounwind readnone + +define i32 @test4(i16 zeroext %a) nounwind { +entry: +; CHECK: test4: +; CHECK: revsh r0, r0 + %conv = zext i16 %a to i32 + %shr9 = lshr i16 %a, 8 + %conv2 = zext i16 %shr9 to i32 + %shl = shl nuw nsw i32 %conv, 8 + %or = or i32 %conv2, %shl + %sext = shl i32 %or, 16 + %conv8 = ashr exact i32 %sext, 16 + ret i32 %conv8 +} diff --git a/test/CodeGen/ARM/select-imm.ll b/test/CodeGen/ARM/select-imm.ll index 578834ec93bc..82ed0184badd 100644 --- a/test/CodeGen/ARM/select-imm.ll +++ b/test/CodeGen/ARM/select-imm.ll @@ -6,7 +6,7 @@ define i32 @t1(i32 %c) nounwind readnone { entry: ; ARM: t1: ; ARM: mov r1, #101 -; ARM: orr r1, r1, #1, 24 +; ARM: orr r1, r1, #1, #24 ; ARM: movgt r0, #123 ; ARMT2: t1: @@ -27,7 +27,7 @@ entry: ; ARM: t2: ; ARM: mov r0, #123 ; ARM: movgt r0, #101 -; ARM: orrgt r0, r0, #1, 24 +; ARM: orrgt r0, r0, #1, #24 ; ARMT2: t2: ; ARMT2: mov r0, #123 diff --git a/test/CodeGen/ARM/select.ll b/test/CodeGen/ARM/select.ll index 1aa0d3904125..d1493ee56e4b 100644 --- a/test/CodeGen/ARM/select.ll +++ b/test/CodeGen/ARM/select.ll @@ -90,3 +90,26 @@ define arm_apcscc float @f8(i32 %a) nounwind { %tmp1 = select i1 %tmp, float 0x3FF3BE76C0000000, float 0x40030E9A20000000 ret float %tmp1 } + +; <rdar://problem/9049552> +; Glue values can only have a single use, but the following test exposed a +; case where a SELECT was lowered with 2 uses of a comparison, causing the +; scheduler to assert. +; CHECK-VFP: f9: + +declare i8* @objc_msgSend(i8*, i8*, ...) +define void @f9() optsize { +entry: + %cmp = icmp eq i8* undef, inttoptr (i32 4 to i8*) + %conv191 = select i1 %cmp, float -3.000000e+00, float 0.000000e+00 + %conv195 = select i1 %cmp, double -1.000000e+00, double 0.000000e+00 + %add = fadd double %conv195, 1.100000e+01 + %conv196 = fptrunc double %add to float + %add201 = fadd float undef, %conv191 + %tmp484 = bitcast float %conv196 to i32 + %tmp478 = bitcast float %add201 to i32 + %tmp490 = insertvalue [2 x i32] undef, i32 %tmp484, 0 + %tmp493 = insertvalue [2 x i32] %tmp490, i32 %tmp478, 1 + call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, [2 x i32], i32, float)*)(i8* undef, i8* undef, [2 x i32] %tmp493, i32 0, float 1.000000e+00) optsize + ret void +} diff --git a/test/CodeGen/ARM/select_xform.ll b/test/CodeGen/ARM/select_xform.ll index 5dabfc3a82a3..4211797ef77e 100644 --- a/test/CodeGen/ARM/select_xform.ll +++ b/test/CodeGen/ARM/select_xform.ll @@ -4,7 +4,7 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { ; ARM: t1: -; ARM: sub r0, r1, #6, 2 +; ARM: sub r0, r1, #6, #2 ; ARM: movgt r0, r1 ; T2: t1: diff --git a/test/CodeGen/ARM/shifter_operand.ll b/test/CodeGen/ARM/shifter_operand.ll index 01e3a922f656..f0e2d102610d 100644 --- a/test/CodeGen/ARM/shifter_operand.ll +++ b/test/CodeGen/ARM/shifter_operand.ll @@ -51,19 +51,19 @@ entry: declare i8* @malloc(...) -define fastcc void @test4() nounwind { +define fastcc void @test4(i16 %addr) nounwind { entry: ; A8: test4: -; A8: ldr r1, [r0, r0, lsl #2] -; A8: str r1, [r0, r0, lsl #2] +; A8: ldr r2, [r0, r1, lsl #2] +; A8: str r2, [r0, r1, lsl #2] ; A9: test4: -; A9: add r0, r0, r0, lsl #2 +; A9: add r0, r0, r{{[0-9]+}}, lsl #2 ; A9: ldr r1, [r0] ; A9: str r1, [r0] %0 = tail call i8* (...)* @malloc(i32 undef) nounwind %1 = bitcast i8* %0 to i32* - %2 = sext i16 undef to i32 + %2 = sext i16 %addr to i32 %3 = getelementptr inbounds i32* %1, i32 %2 %4 = load i32* %3, align 4 %5 = add nsw i32 %4, 1 diff --git a/test/CodeGen/ARM/shuffle.ll b/test/CodeGen/ARM/shuffle.ll new file mode 100644 index 000000000000..7d6be4f5e6c3 --- /dev/null +++ b/test/CodeGen/ARM/shuffle.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin" + +define <8 x i8> @shuf(<8 x i8> %a) nounwind readnone optsize ssp { +entry: +; CHECK: vtbl + %shuffle = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 3, i32 1, i32 2, i32 0, i32 4, i32 4, i32 5, i32 0> + ret <8 x i8> %shuffle +} + +define <8 x i8> @shuf2(<8 x i8> %a, <8 x i8> %b) nounwind readnone optsize ssp { +entry: +; CHECK: vtbl + %shuffle = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 3, i32 1, i32 2, i32 0, i32 4, i32 4, i32 5, i32 8> + ret <8 x i8> %shuffle +} diff --git a/test/CodeGen/ARM/smul.ll b/test/CodeGen/ARM/smul.ll index b7ab2e796f8a..686d791ce60d 100644 --- a/test/CodeGen/ARM/smul.ll +++ b/test/CodeGen/ARM/smul.ll @@ -1,16 +1,12 @@ -; RUN: llc < %s -march=arm -; RUN: llc < %s -march=arm -mattr=+v5TE -; RUN: llc < %s -march=arm -mattr=+v5TE | \ -; RUN: grep smulbt | count 1 -; RUN: llc < %s -march=arm -mattr=+v5TE | \ -; RUN: grep smultt | count 1 -; RUN: llc < %s -march=arm -mattr=+v5TE | \ -; RUN: grep smlabt | count 1 +; RUN: llc < %s -march=arm -mcpu=generic +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s @x = weak global i16 0 ; <i16*> [#uses=1] @y = weak global i16 0 ; <i16*> [#uses=0] define i32 @f1(i32 %y) { +; CHECK: f1 +; CHECK: smulbt %tmp = load i16* @x ; <i16> [#uses=1] %tmp1 = add i16 %tmp, 2 ; <i16> [#uses=1] %tmp2 = sext i16 %tmp1 to i32 ; <i32> [#uses=1] @@ -20,6 +16,8 @@ define i32 @f1(i32 %y) { } define i32 @f2(i32 %x, i32 %y) { +; CHECK: f2 +; CHECK: smultt %tmp1 = ashr i32 %x, 16 ; <i32> [#uses=1] %tmp3 = ashr i32 %y, 16 ; <i32> [#uses=1] %tmp4 = mul i32 %tmp3, %tmp1 ; <i32> [#uses=1] @@ -27,6 +25,8 @@ define i32 @f2(i32 %x, i32 %y) { } define i32 @f3(i32 %a, i16 %x, i32 %y) { +; CHECK: f3 +; CHECK: smlabt %tmp = sext i16 %x to i32 ; <i32> [#uses=1] %tmp2 = ashr i32 %y, 16 ; <i32> [#uses=1] %tmp3 = mul i32 %tmp2, %tmp ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/str_pre-2.ll b/test/CodeGen/ARM/str_pre-2.ll index 465c7e676c56..b24f75a6e2b8 100644 --- a/test/CodeGen/ARM/str_pre-2.ll +++ b/test/CodeGen/ARM/str_pre-2.ll @@ -1,4 +1,7 @@ -; RUN: llc < %s -mtriple=armv6-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=armv6-linux-gnu -regalloc=linearscan | FileCheck %s +; RUN: llc < %s -mtriple=armv6-linux-gnu -regalloc=basic | FileCheck %s + +; The greedy register allocator uses a single CSR here, invalidating the test. @b = external global i64* diff --git a/test/CodeGen/ARM/sub.ll b/test/CodeGen/ARM/sub.ll index 81513e23e807..555b18eb1e99 100644 --- a/test/CodeGen/ARM/sub.ll +++ b/test/CodeGen/ARM/sub.ll @@ -12,7 +12,7 @@ define i64 @f1(i64 %a) { ; 66846720 = 0x03fc0000 define i64 @f2(i64 %a) { ; CHECK: f2 -; CHECK: subs r0, r0, #255, 14 +; CHECK: subs r0, r0, #255, #14 ; CHECK: sbc r1, r1, #0 %tmp = sub i64 %a, 66846720 ret i64 %tmp @@ -27,3 +27,12 @@ define i64 @f3(i64 %a) { ret i64 %tmp } +define i32 @f4(i32 %x) { +entry: +; CHECK: f4 +; CHECK: rsbs + %sub = sub i32 1, %x + %cmp = icmp ugt i32 %sub, 0 + %sel = select i1 %cmp, i32 1, i32 %sub + ret i32 %sel +} diff --git a/test/CodeGen/ARM/thumb1-varalloc.ll b/test/CodeGen/ARM/thumb1-varalloc.ll index 25093fee225a..aa88ae0c1a86 100644 --- a/test/CodeGen/ARM/thumb1-varalloc.ll +++ b/test/CodeGen/ARM/thumb1-varalloc.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=thumbv6-apple-darwin -regalloc=basic | FileCheck %s ; rdar://8819685 @__bar = external hidden global i8* @@ -12,12 +13,13 @@ entry: %0 = load i8** @__bar, align 4 %1 = icmp eq i8* %0, null br i1 %1, label %bb1, label %bb3 +; CHECK: bne bb1: store i32 1026, i32* %size, align 4 %2 = alloca [1026 x i8], align 1 -; CHECK: mov r0, sp -; CHECK: adds r4, r0, r4 +; CHECK: mov [[R0:r[0-9]+]], sp +; CHECK: adds {{r[0-9]+}}, [[R0]], {{r[0-9]+}} %3 = getelementptr inbounds [1026 x i8]* %2, i32 0, i32 0 %4 = call i32 @_called_func(i8* %3, i32* %size) nounwind %5 = icmp eq i32 %4, 0 diff --git a/test/CodeGen/ARM/trap.ll b/test/CodeGen/ARM/trap.ll index b2f6b6e69fa5..38842a9646ff 100644 --- a/test/CodeGen/ARM/trap.ll +++ b/test/CodeGen/ARM/trap.ll @@ -1,10 +1,15 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=INSTR +; RUN: llc < %s -mtriple=arm-apple-darwin -trap-func=_trap | FileCheck %s -check-prefix=FUNC ; rdar://7961298 +; rdar://9249183 define void @t() nounwind { entry: -; CHECK: t: -; CHECK: trap +; INSTR: t: +; INSTR: trap + +; FUNC: t: +; FUNC: bl __trap call void @llvm.trap() unreachable } diff --git a/test/CodeGen/ARM/umulo-32.ll b/test/CodeGen/ARM/umulo-32.ll index aa7d28a62349..fa5c0168fefe 100644 --- a/test/CodeGen/ARM/umulo-32.ll +++ b/test/CodeGen/ARM/umulo-32.ll @@ -12,3 +12,30 @@ define i32 @func(i32 %a) nounwind { } declare %umul.ty @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone + +define i32 @f(i32 %argc, i8** %argv) ssp { +; CHECK: func +; CHECK: str r0 +; CHECK: movs r2 +; CHECK: mov r1 +; CHECK: mov r3 +; CHECK: muldi3 +%1 = alloca i32, align 4 +%2 = alloca i32, align 4 +%3 = alloca i8**, align 4 +%m_degree = alloca i32, align 4 +store i32 0, i32* %1 +store i32 %argc, i32* %2, align 4 +store i8** %argv, i8*** %3, align 4 +store i32 10, i32* %m_degree, align 4 +%4 = load i32* %m_degree, align 4 +%5 = call %umul.ty @llvm.umul.with.overflow.i32(i32 %4, i32 8) +%6 = extractvalue %umul.ty %5, 1 +%7 = extractvalue %umul.ty %5, 0 +%8 = select i1 %6, i32 -1, i32 %7 +%9 = call noalias i8* @_Znam(i32 %8) +%10 = bitcast i8* %9 to double* +ret i32 0 +} + +declare noalias i8* @_Znam(i32) diff --git a/test/CodeGen/ARM/unaligned_load_store.ll b/test/CodeGen/ARM/unaligned_load_store.ll index b42e11f2c4ab..a8237c60e4e0 100644 --- a/test/CodeGen/ARM/unaligned_load_store.ll +++ b/test/CodeGen/ARM/unaligned_load_store.ll @@ -8,14 +8,14 @@ define void @t(i8* nocapture %a, i8* nocapture %b) nounwind { entry: ; GENERIC: t: -; GENERIC: ldrb r2 -; GENERIC: ldrb r3 -; GENERIC: ldrb r12 -; GENERIC: ldrb r1 -; GENERIC: strb r1 -; GENERIC: strb r12 -; GENERIC: strb r3 -; GENERIC: strb r2 +; GENERIC: ldrb [[R2:r[0-9]+]] +; GENERIC: ldrb [[R3:r[0-9]+]] +; GENERIC: ldrb [[R12:r[0-9]+]] +; GENERIC: ldrb [[R1:r[0-9]+]] +; GENERIC: strb [[R1]] +; GENERIC: strb [[R12]] +; GENERIC: strb [[R3]] +; GENERIC: strb [[R2]] ; DARWIN_V6: t: ; DARWIN_V6: ldr r1 diff --git a/test/CodeGen/ARM/undef-sext.ll b/test/CodeGen/ARM/undef-sext.ll new file mode 100644 index 000000000000..2c28da3b6461 --- /dev/null +++ b/test/CodeGen/ARM/undef-sext.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s + +; No need to sign-extend undef. + +define i32 @t(i32* %a) nounwind { +entry: +; CHECK: t: +; CHECK: ldr r0, [r0] +; CHECK: bx lr + %0 = sext i16 undef to i32 + %1 = getelementptr inbounds i32* %a, i32 %0 + %2 = load i32* %1, align 4 + ret i32 %2 +} diff --git a/test/CodeGen/ARM/va_arg.ll b/test/CodeGen/ARM/va_arg.ll index 7cb976236dc5..bb4045311624 100644 --- a/test/CodeGen/ARM/va_arg.ll +++ b/test/CodeGen/ARM/va_arg.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s +; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -pre-RA-sched=source | FileCheck %s ; Test that we correctly align elements when using va_arg ; CHECK: test1: ; CHECK-NOT: bfc -; CHECK: add r0, r0, #7 -; CHECK: bfc r0, #0, #3 +; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7 +; CHECK: bfc [[REG]], #0, #3 ; CHECK-NOT: bfc define i64 @test1(i32 %i, ...) nounwind optsize { @@ -19,8 +19,8 @@ entry: ; CHECK: test2: ; CHECK-NOT: bfc -; CHECK: add r0, r0, #7 -; CHECK: bfc r0, #0, #3 +; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7 +; CHECK: bfc [[REG]], #0, #3 ; CHECK-NOT: bfc ; CHECK: bx lr diff --git a/test/CodeGen/ARM/vbsl-constant.ll b/test/CodeGen/ARM/vbsl-constant.ll new file mode 100644 index 000000000000..14e668efb1da --- /dev/null +++ b/test/CodeGen/ARM/vbsl-constant.ll @@ -0,0 +1,115 @@ +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s + +define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { +;CHECK: v_bsli8: +;CHECK: vldr.64 +;CHECK: vldr.64 +;CHECK: vbsl + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = load <8 x i8>* %C + %tmp4 = and <8 x i8> %tmp1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> + %tmp6 = and <8 x i8> %tmp3, <i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4> + %tmp7 = or <8 x i8> %tmp4, %tmp6 + ret <8 x i8> %tmp7 +} + +define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { +;CHECK: v_bsli16: +;CHECK: vldr.64 +;CHECK: vldr.64 +;CHECK: vbsl + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = load <4 x i16>* %C + %tmp4 = and <4 x i16> %tmp1, <i16 3, i16 3, i16 3, i16 3> + %tmp6 = and <4 x i16> %tmp3, <i16 -4, i16 -4, i16 -4, i16 -4> + %tmp7 = or <4 x i16> %tmp4, %tmp6 + ret <4 x i16> %tmp7 +} + +define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { +;CHECK: v_bsli32: +;CHECK: vldr.64 +;CHECK: vldr.64 +;CHECK: vbsl + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = load <2 x i32>* %C + %tmp4 = and <2 x i32> %tmp1, <i32 3, i32 3> + %tmp6 = and <2 x i32> %tmp3, <i32 -4, i32 -4> + %tmp7 = or <2 x i32> %tmp4, %tmp6 + ret <2 x i32> %tmp7 +} + +define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind { +;CHECK: v_bsli64: +;CHECK: vldr.64 +;CHECK: vldr.64 +;CHECK: vldr.64 +;CHECK: vbsl + %tmp1 = load <1 x i64>* %A + %tmp2 = load <1 x i64>* %B + %tmp3 = load <1 x i64>* %C + %tmp4 = and <1 x i64> %tmp1, <i64 3> + %tmp6 = and <1 x i64> %tmp3, <i64 -4> + %tmp7 = or <1 x i64> %tmp4, %tmp6 + ret <1 x i64> %tmp7 +} + +define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind { +;CHECK: v_bslQi8: +;CHECK: vldmia +;CHECK: vldmia +;CHECK: vbsl + %tmp1 = load <16 x i8>* %A + %tmp2 = load <16 x i8>* %B + %tmp3 = load <16 x i8>* %C + %tmp4 = and <16 x i8> %tmp1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> + %tmp6 = and <16 x i8> %tmp3, <i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4, i8 -4> + %tmp7 = or <16 x i8> %tmp4, %tmp6 + ret <16 x i8> %tmp7 +} + +define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { +;CHECK: v_bslQi16: +;CHECK: vldmia +;CHECK: vldmia +;CHECK: vbsl + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = load <8 x i16>* %C + %tmp4 = and <8 x i16> %tmp1, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> + %tmp6 = and <8 x i16> %tmp3, <i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4, i16 -4> + %tmp7 = or <8 x i16> %tmp4, %tmp6 + ret <8 x i16> %tmp7 +} + +define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { +;CHECK: v_bslQi32: +;CHECK: vldmia +;CHECK: vldmia +;CHECK: vbsl + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i32>* %B + %tmp3 = load <4 x i32>* %C + %tmp4 = and <4 x i32> %tmp1, <i32 3, i32 3, i32 3, i32 3> + %tmp6 = and <4 x i32> %tmp3, <i32 -4, i32 -4, i32 -4, i32 -4> + %tmp7 = or <4 x i32> %tmp4, %tmp6 + ret <4 x i32> %tmp7 +} + +define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind { +;CHECK: v_bslQi64: +;CHECK: vldmia +;CHECK: vldmia +;CHECK: vldmia +;CHECK: vbsl + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i64>* %B + %tmp3 = load <2 x i64>* %C + %tmp4 = and <2 x i64> %tmp1, <i64 3, i64 3> + %tmp6 = and <2 x i64> %tmp3, <i64 -4, i64 -4> + %tmp7 = or <2 x i64> %tmp4, %tmp6 + ret <2 x i64> %tmp7 +} diff --git a/test/CodeGen/ARM/vcgt.ll b/test/CodeGen/ARM/vcgt.ll index c3c4cb356307..2243bac91fb1 100644 --- a/test/CodeGen/ARM/vcgt.ll +++ b/test/CodeGen/ARM/vcgt.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: vcgts8: @@ -161,9 +162,9 @@ define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ; rdar://7923010 define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind { ;CHECK: vcgt_zext: -;CHECK: vmov.i32 q10, #0x1 -;CHECK: vcgt.f32 q8 -;CHECK: vand q8, q8, q10 +;CHECK: vmov.i32 [[Q0:q[0-9]+]], #0x1 +;CHECK: vcgt.f32 [[Q1:q[0-9]+]] +;CHECK: vand [[Q2:q[0-9]+]], [[Q1]], [[Q0]] %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B %tmp3 = fcmp ogt <4 x float> %tmp1, %tmp2 diff --git a/test/CodeGen/ARM/vector-DAGCombine.ll b/test/CodeGen/ARM/vector-DAGCombine.ll index 3ab0cfcbbc77..81bdc44863b7 100644 --- a/test/CodeGen/ARM/vector-DAGCombine.ll +++ b/test/CodeGen/ARM/vector-DAGCombine.ll @@ -105,3 +105,21 @@ define void @i64_extractelement(i64* %ptr, <2 x i64>* %vp) nounwind { store i64 %t1, i64* %ptr ret void } + +; Test trying to do a AND Combine on illegal types. +define void @andVec(<3 x i8>* %A) nounwind { + %tmp = load <3 x i8>* %A, align 4 + %and = and <3 x i8> %tmp, <i8 7, i8 7, i8 7> + store <3 x i8> %and, <3 x i8>* %A + ret void +} + + +; Test trying to do an OR Combine on illegal types. +define void @orVec(<3 x i8>* %A) nounwind { + %tmp = load <3 x i8>* %A, align 4 + %or = or <3 x i8> %tmp, <i8 7, i8 7, i8 7> + store <3 x i8> %or, <3 x i8>* %A + ret void +} + diff --git a/test/CodeGen/ARM/vext.ll b/test/CodeGen/ARM/vext.ll index 55abefef0fa7..49a042b7e1f5 100644 --- a/test/CodeGen/ARM/vext.ll +++ b/test/CodeGen/ARM/vext.ll @@ -125,11 +125,11 @@ define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind { ; The actual shuffle code only handles some cases, make sure we check ; this rather than blindly emitting a VECTOR_SHUFFLE (infinite ; lowering loop can result otherwise). -define <8 x i8> @test_illegal(<16 x i8>* %A, <16 x i8>* %B) nounwind { +define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK: test_illegal: -;CHECK: vst1.8 - %tmp1 = load <16 x i8>* %A - %tmp2 = load <16 x i8>* %B - %tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <8 x i32> <i32 0, i32 7, i32 5, i32 25, i32 3, i32 2, i32 2, i32 26> - ret <8 x i8> %tmp3 +;CHECK: vst1.16 + %tmp1 = load <8 x i16>* %A + %tmp2 = load <8 x i16>* %B + %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 7, i32 5, i32 13, i32 3, i32 2, i32 2, i32 9> + ret <8 x i16> %tmp3 } diff --git a/test/CodeGen/ARM/vfp.ll b/test/CodeGen/ARM/vfp.ll index 44a44afe9af4..49a69827bc05 100644 --- a/test/CodeGen/ARM/vfp.ll +++ b/test/CodeGen/ARM/vfp.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+vfp2 -disable-post-ra | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+vfp2 -disable-post-ra -regalloc=basic | FileCheck %s define void @test(float* %P, double* %D) { %A = load float* %P ; <float> [#uses=1] @@ -40,9 +41,9 @@ define void @test_ext_round(float* %P, double* %D) { ;CHECK: test_ext_round: %a = load float* %P ; <float> [#uses=1] ;CHECK: vcvt.f64.f32 +;CHECK: vcvt.f32.f64 %b = fpext float %a to double ; <double> [#uses=1] %A = load double* %D ; <double> [#uses=1] -;CHECK: vcvt.f32.f64 %B = fptrunc double %A to float ; <float> [#uses=1] store double %b, double* %D store float %B, float* %P diff --git a/test/CodeGen/ARM/vld1.ll b/test/CodeGen/ARM/vld1.ll index c886125a2fb0..e524395c501a 100644 --- a/test/CodeGen/ARM/vld1.ll +++ b/test/CodeGen/ARM/vld1.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s define <8 x i8> @vld1i8(i8* %A) nounwind { ;CHECK: vld1i8: @@ -19,7 +20,7 @@ define <4 x i16> @vld1i16(i16* %A) nounwind { ;Check for a post-increment updating load. define <4 x i16> @vld1i16_update(i16** %ptr) nounwind { ;CHECK: vld1i16_update: -;CHECK: vld1.16 {d16}, [r1]! +;CHECK: vld1.16 {d16}, [{{r[0-9]+}}]! %A = load i16** %ptr %tmp0 = bitcast i16* %A to i8* %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1) @@ -39,7 +40,7 @@ define <2 x i32> @vld1i32(i32* %A) nounwind { ;Check for a post-increment updating load with register increment. define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind { ;CHECK: vld1i32_update: -;CHECK: vld1.32 {d16}, [r2], r1 +;CHECK: vld1.32 {d16}, [{{r[0-9]+}}], {{r[0-9]+}} %A = load i32** %ptr %tmp0 = bitcast i32* %A to i8* %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1) @@ -75,7 +76,7 @@ define <16 x i8> @vld1Qi8(i8* %A) nounwind { ;Check for a post-increment updating load. define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind { ;CHECK: vld1Qi8_update: -;CHECK: vld1.8 {d16, d17}, [r1, :64]! +;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+}}, :64]! %A = load i8** %ptr %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8) %tmp2 = getelementptr i8* %A, i32 16 @@ -132,8 +133,6 @@ declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*, i32) nounwind readonly ; Do not crash if the vld1 result is not used. define void @unused_vld1_result() { entry: -;CHECK: unused_vld1_result -;CHECK: vld1.32 %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) call void @llvm.trap() unreachable diff --git a/test/CodeGen/ARM/vld3.ll b/test/CodeGen/ARM/vld3.ll index dde530f6df1f..b495319830b0 100644 --- a/test/CodeGen/ARM/vld3.ll +++ b/test/CodeGen/ARM/vld3.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s %struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> } %struct.__neon_int16x4x3_t = type { <4 x i16>, <4 x i16>, <4 x i16> } @@ -36,7 +37,7 @@ define <4 x i16> @vld3i16(i16* %A) nounwind { ;Check for a post-increment updating load with register increment. define <4 x i16> @vld3i16_update(i16** %ptr, i32 %inc) nounwind { ;CHECK: vld3i16_update: -;CHECK: vld3.16 {d16, d17, d18}, [r2], r1 +;CHECK: vld3.16 {d16, d17, d18}, [{{r[0-9]+}}], {{r[0-9]+}} %A = load i16** %ptr %tmp0 = bitcast i16* %A to i8* %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1) @@ -121,8 +122,8 @@ define <4 x i32> @vld3Qi32(i32* %A) nounwind { ;Check for a post-increment updating load. define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind { ;CHECK: vld3Qi32_update: -;CHECK: vld3.32 {d16, d18, d20}, [r1]! -;CHECK: vld3.32 {d17, d19, d21}, [r1]! +;CHECK: vld3.32 {d16, d18, d20}, [r[[R:[0-9]+]]]! +;CHECK: vld3.32 {d17, d19, d21}, [r[[R]]]! %A = load i32** %ptr %tmp0 = bitcast i32* %A to i8* %tmp1 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3.v4i32(i8* %tmp0, i32 1) diff --git a/test/CodeGen/ARM/vldlane.ll b/test/CodeGen/ARM/vldlane.ll index 770ed071ac12..805aad51d4fd 100644 --- a/test/CodeGen/ARM/vldlane.ll +++ b/test/CodeGen/ARM/vldlane.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vld1lanei8: @@ -279,7 +280,7 @@ define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;Check for a post-increment updating load with register increment. define <8 x i16> @vld3laneQi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind { ;CHECK: vld3laneQi16_update: -;CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [r2], r1 +;CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [{{r[0-9]+}}], {{r[0-9]+}} %A = load i16** %ptr %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B @@ -490,7 +491,7 @@ declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8*, <4 x flo ; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because ; we don't currently have a QQQQ_VFP2 super-regclass. (The "0" for the low ; part of %ins67 is supposed to be loaded by a VLDRS instruction in this test.) -define void @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind { +define <8 x i16> @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind { ;CHECK: test_qqqq_regsequence_subreg ;CHECK: vld3.16 %tmp63 = extractvalue [6 x i64] %b, 5 @@ -499,8 +500,12 @@ define void @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind { %ins67 = or i128 %tmp65, 0 %tmp78 = bitcast i128 %ins67 to <8 x i16> %vld3_lane = tail call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> %tmp78, i32 1, i32 2) - call void @llvm.trap() - unreachable + %tmp3 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 0 + %tmp4 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 1 + %tmp5 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 2 + %tmp6 = add <8 x i16> %tmp3, %tmp4 + %tmp7 = add <8 x i16> %tmp5, %tmp6 + ret <8 x i16> %tmp7 } declare void @llvm.trap() nounwind diff --git a/test/CodeGen/ARM/vmul.ll b/test/CodeGen/ARM/vmul.ll index ee033caa00d0..1fd6581ae081 100644 --- a/test/CodeGen/ARM/vmul.ll +++ b/test/CodeGen/ARM/vmul.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: vmuli8: @@ -158,6 +158,15 @@ define <8 x i16> @vmulls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ret <8 x i16> %tmp5 } +define <8 x i16> @vmulls8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind { +;CHECK: vmulls8_int: +;CHECK: vmull.s8 + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i16> %tmp3 +} + define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK: vmulls16: ;CHECK: vmull.s16 @@ -169,6 +178,15 @@ define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ret <4 x i32> %tmp5 } +define <4 x i32> @vmulls16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind { +;CHECK: vmulls16_int: +;CHECK: vmull.s16 + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i32> %tmp3 +} + define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK: vmulls32: ;CHECK: vmull.s32 @@ -180,6 +198,15 @@ define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ret <2 x i64> %tmp5 } +define <2 x i64> @vmulls32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind { +;CHECK: vmulls32_int: +;CHECK: vmull.s32 + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i64> %tmp3 +} + define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: vmullu8: ;CHECK: vmull.u8 @@ -191,6 +218,15 @@ define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ret <8 x i16> %tmp5 } +define <8 x i16> @vmullu8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind { +;CHECK: vmullu8_int: +;CHECK: vmull.u8 + %tmp1 = load <8 x i8>* %A + %tmp2 = load <8 x i8>* %B + %tmp3 = call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2) + ret <8 x i16> %tmp3 +} + define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK: vmullu16: ;CHECK: vmull.u16 @@ -202,6 +238,15 @@ define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ret <4 x i32> %tmp5 } +define <4 x i32> @vmullu16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind { +;CHECK: vmullu16_int: +;CHECK: vmull.u16 + %tmp1 = load <4 x i16>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2) + ret <4 x i32> %tmp3 +} + define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ;CHECK: vmullu32: ;CHECK: vmull.u32 @@ -213,6 +258,15 @@ define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { ret <2 x i64> %tmp5 } +define <2 x i64> @vmullu32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind { +;CHECK: vmullu32_int: +;CHECK: vmull.u32 + %tmp1 = load <2 x i32>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2) + ret <2 x i64> %tmp3 +} + define <8 x i16> @vmullp8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: vmullp8: ;CHECK: vmull.p8 @@ -233,6 +287,15 @@ entry: ret <4 x i32> %3 } +define arm_aapcs_vfpcc <4 x i32> @test_vmull_lanes16_int(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone { +entry: +; CHECK: test_vmull_lanes16_int +; CHECK: vmull.s16 q0, d0, d1[1] + %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1] + %1 = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1] + ret <4 x i32> %1 +} + define arm_aapcs_vfpcc <2 x i64> @test_vmull_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone { entry: ; CHECK: test_vmull_lanes32 @@ -244,6 +307,15 @@ entry: ret <2 x i64> %3 } +define arm_aapcs_vfpcc <2 x i64> @test_vmull_lanes32_int(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone { +entry: +; CHECK: test_vmull_lanes32_int +; CHECK: vmull.s32 q0, d0, d1[1] + %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1] + %1 = tail call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1] + ret <2 x i64> %1 +} + define arm_aapcs_vfpcc <4 x i32> @test_vmull_laneu16(<4 x i16> %arg0_uint16x4_t, <4 x i16> %arg1_uint16x4_t) nounwind readnone { entry: ; CHECK: test_vmull_laneu16 @@ -255,6 +327,15 @@ entry: ret <4 x i32> %3 } +define arm_aapcs_vfpcc <4 x i32> @test_vmull_laneu16_int(<4 x i16> %arg0_uint16x4_t, <4 x i16> %arg1_uint16x4_t) nounwind readnone { +entry: +; CHECK: test_vmull_laneu16_int +; CHECK: vmull.u16 q0, d0, d1[1] + %0 = shufflevector <4 x i16> %arg1_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1] + %1 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %arg0_uint16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1] + ret <4 x i32> %1 +} + define arm_aapcs_vfpcc <2 x i64> @test_vmull_laneu32(<2 x i32> %arg0_uint32x2_t, <2 x i32> %arg1_uint32x2_t) nounwind readnone { entry: ; CHECK: test_vmull_laneu32 @@ -266,6 +347,23 @@ entry: ret <2 x i64> %3 } +define arm_aapcs_vfpcc <2 x i64> @test_vmull_laneu32_int(<2 x i32> %arg0_uint32x2_t, <2 x i32> %arg1_uint32x2_t) nounwind readnone { +entry: +; CHECK: test_vmull_laneu32_int +; CHECK: vmull.u32 q0, d0, d1[1] + %0 = shufflevector <2 x i32> %arg1_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1] + %1 = tail call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %arg0_uint32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1] + ret <2 x i64> %1 +} + +declare <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone + +declare <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8>, <8 x i8>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32>, <2 x i32>) nounwind readnone + declare <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8>, <8 x i8>) nounwind readnone @@ -339,3 +437,58 @@ define <2 x i64> @vmull_extvec_u32(<2 x i32> %arg) nounwind { %tmp4 = mul <2 x i64> %tmp3, <i64 1234, i64 1234> ret <2 x i64> %tmp4 } + +; rdar://9197392 +define void @distribue(i16* %dst, i8* %src, i32 %mul) nounwind { +entry: +; CHECK: distribue: +; CHECK: vmull.u8 [[REG1:(q[0-9]+)]], d{{.*}}, [[REG2:(d[0-9]+)]] +; CHECK: vmlal.u8 [[REG1]], d{{.*}}, [[REG2]] + %0 = trunc i32 %mul to i8 + %1 = insertelement <8 x i8> undef, i8 %0, i32 0 + %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer + %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %src, i32 1) + %4 = bitcast <16 x i8> %3 to <2 x double> + %5 = extractelement <2 x double> %4, i32 1 + %6 = bitcast double %5 to <8 x i8> + %7 = zext <8 x i8> %6 to <8 x i16> + %8 = zext <8 x i8> %2 to <8 x i16> + %9 = extractelement <2 x double> %4, i32 0 + %10 = bitcast double %9 to <8 x i8> + %11 = zext <8 x i8> %10 to <8 x i16> + %12 = add <8 x i16> %7, %11 + %13 = mul <8 x i16> %12, %8 + %14 = bitcast i16* %dst to i8* + tail call void @llvm.arm.neon.vst1.v8i16(i8* %14, <8 x i16> %13, i32 2) + ret void +} + +declare <16 x i8> @llvm.arm.neon.vld1.v16i8(i8*, i32) nounwind readonly + +declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>, i32) nounwind + +; Take advantage of the Cortex-A8 multiplier accumulator forward. + +%struct.uint8x8_t = type { <8 x i8> } + +define void @distribue2(%struct.uint8x8_t* nocapture %dst, i8* %src, i32 %mul) nounwind { +entry: +; CHECK: distribue2 +; CHECK-NOT: vadd.i8 +; CHECK: vmul.i8 +; CHECK: vmla.i8 + %0 = trunc i32 %mul to i8 + %1 = insertelement <8 x i8> undef, i8 %0, i32 0 + %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer + %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %src, i32 1) + %4 = bitcast <16 x i8> %3 to <2 x double> + %5 = extractelement <2 x double> %4, i32 1 + %6 = bitcast double %5 to <8 x i8> + %7 = extractelement <2 x double> %4, i32 0 + %8 = bitcast double %7 to <8 x i8> + %9 = add <8 x i8> %6, %8 + %10 = mul <8 x i8> %9, %2 + %11 = getelementptr inbounds %struct.uint8x8_t* %dst, i32 0, i32 0 + store <8 x i8> %10, <8 x i8>* %11, align 8 + ret void +} diff --git a/test/CodeGen/ARM/vst3.ll b/test/CodeGen/ARM/vst3.ll index d262303bc60e..e3372a03793d 100644 --- a/test/CodeGen/ARM/vst3.ll +++ b/test/CodeGen/ARM/vst3.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon -O0 | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+neon -disable-arm-fast-isel -O0 | FileCheck %s define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vst3i8: diff --git a/test/CodeGen/Blackfin/2009-08-04-LowerExtract-Live.ll b/test/CodeGen/Blackfin/2009-08-04-LowerExtract-Live.ll index 3ee5e8df9972..50fccb440990 100644 --- a/test/CodeGen/Blackfin/2009-08-04-LowerExtract-Live.ll +++ b/test/CodeGen/Blackfin/2009-08-04-LowerExtract-Live.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=bfin -join-liveintervals=0 -verify-machineinstrs +; RUN: llc < %s -march=bfin -join-liveintervals=0 -verify-machineinstrs -regalloc=greedy ; Provoke an error in LowerSubregsPass::LowerExtract where the live range of a ; super-register is illegally extended. diff --git a/test/CodeGen/CellSPU/jumptable.ll b/test/CodeGen/CellSPU/jumptable.ll index 42b41b3bf29b..87376ef6ed53 100644 --- a/test/CodeGen/CellSPU/jumptable.ll +++ b/test/CodeGen/CellSPU/jumptable.ll @@ -1,4 +1,4 @@ -;RUN: llc --march=cellspu %s -o - | FileCheck %s +;RUN: llc --march=cellspu -disable-cgp-branch-opts %s -o - | FileCheck %s ; This is to check that emitting jumptables doesn't crash llc define i32 @test(i32 %param) { entry: diff --git a/test/CodeGen/CellSPU/loads.ll b/test/CodeGen/CellSPU/loads.ll index 03d7ad1153a1..4771752f5f4c 100644 --- a/test/CodeGen/CellSPU/loads.ll +++ b/test/CodeGen/CellSPU/loads.ll @@ -50,3 +50,10 @@ define i32 @load_misaligned( i32* %ptr ){ %rv = load i32* %ptr, align 2 ret i32 %rv } + +define <4 x i32> @load_null_vec( ) { +;CHECK: lqa +;CHECK: bi $lr + %rv = load <4 x i32>* null + ret <4 x i32> %rv +} diff --git a/test/CodeGen/CellSPU/rotate_ops.ll b/test/CodeGen/CellSPU/rotate_ops.ll index e1172089c703..b1219e6f56e5 100644 --- a/test/CodeGen/CellSPU/rotate_ops.ll +++ b/test/CodeGen/CellSPU/rotate_ops.ll @@ -3,9 +3,9 @@ ; RUN: grep roth %t1.s | count 8 ; RUN: grep roti.*5 %t1.s | count 1 ; RUN: grep roti.*27 %t1.s | count 1 -; RUN grep rothi.*5 %t1.s | count 2 -; RUN grep rothi.*11 %t1.s | count 1 -; RUN grep rothi.*,.3 %t1.s | count 1 +; RUN: grep rothi.*5 %t1.s | count 2 +; RUN: grep rothi.*11 %t1.s | count 1 +; RUN: grep rothi.*,.3 %t1.s | count 1 ; RUN: grep andhi %t1.s | count 4 ; RUN: grep shlhi %t1.s | count 4 ; RUN: cat %t1.s | FileCheck %s diff --git a/test/CodeGen/CellSPU/shift_ops.ll b/test/CodeGen/CellSPU/shift_ops.ll index 92390abf9465..c4a5abd29042 100644 --- a/test/CodeGen/CellSPU/shift_ops.ll +++ b/test/CodeGen/CellSPU/shift_ops.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=cellspu > %t1.s -; RUN: grep {shlh } %t1.s | count 9 +; RUN: grep {shlh } %t1.s | count 10 ; RUN: grep {shlhi } %t1.s | count 3 -; RUN: grep {shl } %t1.s | count 9 +; RUN: grep {shl } %t1.s | count 11 ; RUN: grep {shli } %t1.s | count 3 ; RUN: grep {xshw } %t1.s | count 5 ; RUN: grep {and } %t1.s | count 14 @@ -14,15 +14,12 @@ ; RUN: grep {rotqbyi } %t1.s | count 1 ; RUN: grep {rotqbii } %t1.s | count 2 ; RUN: grep {rotqbybi } %t1.s | count 1 -; RUN: grep {sfi } %t1.s | count 4 +; RUN: grep {sfi } %t1.s | count 6 ; RUN: cat %t1.s | FileCheck %s target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" -; Vector shifts are not currently supported in gcc or llvm assembly. These are -; not tested. - ; Shift left i16 via register, note that the second operand to shl is promoted ; to a 32-bit type: @@ -293,3 +290,55 @@ define i128 @test_lshr_i128( i128 %val ) { %rv = lshr i128 %val, 64 ret i128 %rv } + +;Vector shifts +define <2 x i32> @shl_v2i32(<2 x i32> %val, <2 x i32> %sh) { +;CHECK: shl +;CHECK: bi $lr + %rv = shl <2 x i32> %val, %sh + ret <2 x i32> %rv +} + +define <4 x i32> @shl_v4i32(<4 x i32> %val, <4 x i32> %sh) { +;CHECK: shl +;CHECK: bi $lr + %rv = shl <4 x i32> %val, %sh + ret <4 x i32> %rv +} + +define <8 x i16> @shl_v8i16(<8 x i16> %val, <8 x i16> %sh) { +;CHECK: shlh +;CHECK: bi $lr + %rv = shl <8 x i16> %val, %sh + ret <8 x i16> %rv +} + +define <4 x i32> @lshr_v4i32(<4 x i32> %val, <4 x i32> %sh) { +;CHECK: rotm +;CHECK: bi $lr + %rv = lshr <4 x i32> %val, %sh + ret <4 x i32> %rv +} + +define <8 x i16> @lshr_v8i16(<8 x i16> %val, <8 x i16> %sh) { +;CHECK: sfhi +;CHECK: rothm +;CHECK: bi $lr + %rv = lshr <8 x i16> %val, %sh + ret <8 x i16> %rv +} + +define <4 x i32> @ashr_v4i32(<4 x i32> %val, <4 x i32> %sh) { +;CHECK: rotma +;CHECK: bi $lr + %rv = ashr <4 x i32> %val, %sh + ret <4 x i32> %rv +} + +define <8 x i16> @ashr_v8i16(<8 x i16> %val, <8 x i16> %sh) { +;CHECK: sfhi +;CHECK: rotmah +;CHECK: bi $lr + %rv = ashr <8 x i16> %val, %sh + ret <8 x i16> %rv +} diff --git a/test/CodeGen/CellSPU/stores.ll b/test/CodeGen/CellSPU/stores.ll index 7e0bf06b4e45..6ca5b0892304 100644 --- a/test/CodeGen/CellSPU/stores.ll +++ b/test/CodeGen/CellSPU/stores.ll @@ -171,3 +171,11 @@ define void @store_v8( <8 x float> %val, <8 x float>* %ptr ) store <8 x float> %val, <8 x float>* %ptr ret void } + +define void @store_null_vec( <4 x i32> %val ) { +; FIXME - this is for some reason compiled into a il+stqd, not a sta. +;CHECK: stqd +;CHECK: bi $lr + store <4 x i32> %val, <4 x i32>* null + ret void +} diff --git a/test/CodeGen/CellSPU/v2f32.ll b/test/CodeGen/CellSPU/v2f32.ll index efd032031002..09e15ffbc75d 100644 --- a/test/CodeGen/CellSPU/v2f32.ll +++ b/test/CodeGen/CellSPU/v2f32.ll @@ -33,6 +33,7 @@ define %vec @test_mul(%vec %param) ret %vec %1 } +; CHECK: test_splat: define %vec @test_splat(float %param ) { ;CHECK: lqa ;CHECK: shufb @@ -43,16 +44,17 @@ define %vec @test_splat(float %param ) { } define void @test_store(%vec %val, %vec* %ptr){ - +; CHECK: test_store: ;CHECK: stqd - store %vec undef, %vec* null + store %vec zeroinitializer, %vec* null -;CHECK: stqd $3, 0(${{.}}) +;CHECK: stqd $3, 0(${{.*}}) ;CHECK: bi $lr store %vec %val, %vec* %ptr ret void } +; CHECK: test_insert: define %vec @test_insert(){ ;CHECK: cwd ;CHECK: shufb $3 @@ -61,6 +63,8 @@ define %vec @test_insert(){ ret %vec %rv } +; CHECK: test_unaligned_store: + define void @test_unaligned_store() { ;CHECK: cdd ;CHECK: shufb @@ -68,7 +72,7 @@ define void @test_unaligned_store() { %data = alloca [4 x float], align 16 ; <[4 x float]*> [#uses=1] %ptr = getelementptr [4 x float]* %data, i32 0, i32 2 ; <float*> [#uses=1] %vptr = bitcast float* %ptr to <2 x float>* ; <[1 x <2 x float>]*> [#uses=1] - store <2 x float> undef, <2 x float>* %vptr + store <2 x float> zeroinitializer, <2 x float>* %vptr ret void } diff --git a/test/CodeGen/Generic/crash.ll b/test/CodeGen/Generic/crash.ll index 042739884df7..e7cc7e339406 100644 --- a/test/CodeGen/Generic/crash.ll +++ b/test/CodeGen/Generic/crash.ll @@ -38,3 +38,31 @@ unreachable declare void @Parse_Vector(double*) declare i32 @llvm.objectsize.i32(i8*, i1) + +; PR9578 +%struct.S0 = type { i32, i8, i32 } + +define void @func_82() nounwind optsize { +entry: + br label %for.body.i + +for.body.i: ; preds = %for.body.i, %entry + br i1 undef, label %func_74.exit.for.cond29.thread_crit_edge, label %for.body.i + +func_74.exit.for.cond29.thread_crit_edge: ; preds = %for.body.i + %f13576.pre = getelementptr inbounds %struct.S0* undef, i64 0, i32 1 + store i8 0, i8* %f13576.pre, align 4, !tbaa !0 + br label %lbl_468 + +lbl_468: ; preds = %lbl_468, %func_74.exit.for.cond29.thread_crit_edge + %f13577.ph = phi i8* [ %f13576.pre, %func_74.exit.for.cond29.thread_crit_edge ], [ %f135.pre, %lbl_468 ] + store i8 1, i8* %f13577.ph, align 1 + %f135.pre = getelementptr inbounds %struct.S0* undef, i64 0, i32 1 + br i1 undef, label %lbl_468, label %for.end74 + +for.end74: ; preds = %lbl_468 + ret void +} + +!0 = metadata !{metadata !"omnipotent char", metadata !1} +!1 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/MBlaze/fsl.ll b/test/CodeGen/MBlaze/fsl.ll index f9c6205bc19f..5444f82dd63c 100644 --- a/test/CodeGen/MBlaze/fsl.ll +++ b/test/CodeGen/MBlaze/fsl.ll @@ -3,7 +3,7 @@ ; dynamic version of the instructions and that constant values use the ; constant version of the instructions. ; -; RUN: llc < %s -march=mblaze | FileCheck %s +; RUN: llc -O3 < %s -march=mblaze | FileCheck %s declare i32 @llvm.mblaze.fsl.get(i32 %port) declare i32 @llvm.mblaze.fsl.aget(i32 %port) @@ -55,8 +55,7 @@ declare void @llvm.mblaze.fsl.tnaput(i32 %port) declare void @llvm.mblaze.fsl.tncput(i32 %port) declare void @llvm.mblaze.fsl.tncaput(i32 %port) -define i32 @fsl_get(i32 %port) -{ +define void @fsl_get(i32 %port) { ; CHECK: fsl_get: %v0 = call i32 @llvm.mblaze.fsl.get(i32 %port) ; CHECK: getd @@ -122,12 +121,11 @@ define i32 @fsl_get(i32 %port) ; CHECK-NEXT: tnecgetd %v31 = call i32 @llvm.mblaze.fsl.tnecaget(i32 %port) ; CHECK-NEXT: tnecagetd - ret i32 1 + ret void ; CHECK: rtsd } -define i32 @fslc_get() -{ +define void @fslc_get() { ; CHECK: fslc_get: %v0 = call i32 @llvm.mblaze.fsl.get(i32 1) ; CHECK: get @@ -224,12 +222,11 @@ define i32 @fslc_get() %v31 = call i32 @llvm.mblaze.fsl.tnecaget(i32 1) ; CHECK-NOT: tnecagetd ; CHECK: tnecaget - ret i32 1 + ret void ; CHECK: rtsd } -define void @putfsl(i32 %value, i32 %port) -{ +define void @putfsl(i32 %value, i32 %port) { ; CHECK: putfsl: call void @llvm.mblaze.fsl.put(i32 %value, i32 %port) ; CHECK: putd @@ -267,8 +264,7 @@ define void @putfsl(i32 %value, i32 %port) ; CHECK: rtsd } -define void @putfsl_const(i32 %value) -{ +define void @putfsl_const(i32 %value) { ; CHECK: putfsl_const: call void @llvm.mblaze.fsl.put(i32 %value, i32 1) ; CHECK-NOT: putd diff --git a/test/CodeGen/MBlaze/loop.ll b/test/CodeGen/MBlaze/loop.ll index 8973f75aa1dc..7439d0b6fe22 100644 --- a/test/CodeGen/MBlaze/loop.ll +++ b/test/CodeGen/MBlaze/loop.ll @@ -29,14 +29,12 @@ loop_inner_finish: %inner.5 = add i32 %inner.2, 1 call i32 (i8*,...)* @printf( i8* getelementptr([19 x i8]* @MSG,i32 0,i32 0), i32 %inner.0, i32 %inner.1, i32 %inner.2 ) - ; CHECK: brlid - ; CHECK: addik {{.*, 1}} %inner.6 = icmp eq i32 %inner.5, 100 - ; CHECK: cmp + ; CHECK: cmp [[REG:r[0-9]*]] br i1 %inner.6, label %loop_inner, label %loop_outer_finish - ; CHECK: {{beq|bne}} + ; CHECK: {{beqid|bneid}} [[REG]] loop_outer_finish: %outer.1 = add i32 %outer.0, 1 diff --git a/test/CodeGen/Mips/2008-07-22-Cstpool.ll b/test/CodeGen/Mips/2008-07-22-Cstpool.ll index 20bd88889061..94dfe35faba1 100644 --- a/test/CodeGen/Mips/2008-07-22-Cstpool.ll +++ b/test/CodeGen/Mips/2008-07-22-Cstpool.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=mips -o %t ; RUN: grep {CPI\[01\]_\[01\]:} %t | count 2 -; RUN: grep {rodata.cst4,"aM",@progbits} %t | count 1 +; RUN: grep {.rodata.cst4,"aM",@progbits} %t | count 1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "mipsallegrexel-unknown-psp-elf" diff --git a/test/CodeGen/Mips/2008-07-23-fpcmp.ll b/test/CodeGen/Mips/2008-07-23-fpcmp.ll index ca837ffd2a50..519e4b93a72b 100644 --- a/test/CodeGen/Mips/2008-07-23-fpcmp.ll +++ b/test/CodeGen/Mips/2008-07-23-fpcmp.ll @@ -2,6 +2,10 @@ ; RUN: grep {c\\..*\\.s} %t | count 3 ; RUN: grep {bc1\[tf\]} %t | count 3 +; FIXME: Disabled because branch instructions are generated where +; conditional move instructions are expected. +; REQUIRES: disabled + target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "mipsallegrexel-unknown-psp-elf" diff --git a/test/CodeGen/Mips/2008-07-29-icmp.ll b/test/CodeGen/Mips/2008-07-29-icmp.ll index 52a4b081ddb3..e85a749f7dcd 100644 --- a/test/CodeGen/Mips/2008-07-29-icmp.ll +++ b/test/CodeGen/Mips/2008-07-29-icmp.ll @@ -1,5 +1,9 @@ ; RUN: llc < %s -march=mips | grep {b\[ne\]\[eq\]} | count 1 +; FIXME: Disabled because branch instructions are generated where +; conditional move instructions are expected. +; REQUIRES: disabled + target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "mipsallegrexel-unknown-psp-elf" diff --git a/test/CodeGen/Mips/2008-08-06-Alloca.ll b/test/CodeGen/Mips/2008-08-06-Alloca.ll index 7be7974e0ffe..6dd4af111cd9 100644 --- a/test/CodeGen/Mips/2008-08-06-Alloca.ll +++ b/test/CodeGen/Mips/2008-08-06-Alloca.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=mips | grep {subu.*sp} | count 2 +; RUN: llc < %s -march=mips -regalloc=basic | grep {subu.*sp} | count 2 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "mipsallegrexel-unknown-psp-elf" diff --git a/test/CodeGen/Mips/2010-07-20-Select.ll b/test/CodeGen/Mips/2010-07-20-Select.ll index 891b5d9e1884..e5e2c5473770 100644 --- a/test/CodeGen/Mips/2010-07-20-Select.ll +++ b/test/CodeGen/Mips/2010-07-20-Select.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=mips -relocation-model=static | FileCheck %s +; RUN: llc < %s -march=mips -relocation-model=static -regalloc=basic | FileCheck %s ; Fix PR7473 define i32 @main() nounwind readnone { @@ -9,12 +10,12 @@ entry: volatile store i32 0, i32* %c, align 4 %0 = volatile load i32* %a, align 4 ; <i32> [#uses=1] %1 = icmp eq i32 %0, 0 ; <i1> [#uses=1] -; CHECK: addiu $3, $zero, 0 +; CHECK: addiu $[[R1:[0-9]+]], $zero, 0 %iftmp.0.0 = select i1 %1, i32 3, i32 0 ; <i32> [#uses=1] %2 = volatile load i32* %c, align 4 ; <i32> [#uses=1] %3 = icmp eq i32 %2, 0 ; <i1> [#uses=1] -; CHECK: addiu $3, $zero, 3 -; CHECK: addu $2, $5, $3 +; CHECK: addiu $[[R1]], $zero, 3 +; CHECK: addu $2, ${{.}}, $[[R1]] %iftmp.2.0 = select i1 %3, i32 0, i32 5 ; <i32> [#uses=1] %4 = add nsw i32 %iftmp.2.0, %iftmp.0.0 ; <i32> [#uses=1] ret i32 %4 diff --git a/test/CodeGen/Mips/addc.ll b/test/CodeGen/Mips/addc.ll new file mode 100644 index 000000000000..e5d05b1d6dbb --- /dev/null +++ b/test/CodeGen/Mips/addc.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=mipsel | FileCheck %s +; RUN: llc < %s -march=mips | FileCheck %s + +define void @f(i64 %l, i64* nocapture %p) nounwind { +entry: +; CHECK: lui +; CHECK: ori +; CHECK: addu + %add = add i64 %l, 1311768467294899695 + store i64 %add, i64* %p, align 4 + ret void +} + diff --git a/test/CodeGen/Mips/analyzebranch.ll b/test/CodeGen/Mips/analyzebranch.ll new file mode 100644 index 000000000000..8f0bdf286c52 --- /dev/null +++ b/test/CodeGen/Mips/analyzebranch.ll @@ -0,0 +1,46 @@ +; RUN: llc -march=mips < %s | FileCheck %s + +define double @foo(double %a, double %b) nounwind readnone { +entry: +; CHECK: bc1f $BB0_2 +; CHECK: nop +; CHECK: # BB#1: + + %cmp = fcmp ogt double %a, 0.000000e+00 + br i1 %cmp, label %if.end6, label %if.else + +if.else: ; preds = %entry + %cmp3 = fcmp ogt double %b, 0.000000e+00 + br i1 %cmp3, label %if.end6, label %return + +if.end6: ; preds = %if.else, %entry + %c.0 = phi double [ %a, %entry ], [ 0.000000e+00, %if.else ] + %sub = fsub double %b, %c.0 + %mul = fmul double %sub, 2.000000e+00 + br label %return + +return: ; preds = %if.else, %if.end6 + %retval.0 = phi double [ %mul, %if.end6 ], [ 0.000000e+00, %if.else ] + ret double %retval.0 +} + +define void @f1(float %f) nounwind { +entry: +; CHECK: bc1t $BB1_2 +; CHECK: nop +; CHECK: # BB#1: + %cmp = fcmp une float %f, 0.000000e+00 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @abort() noreturn + unreachable + +if.end: ; preds = %entry + tail call void (...)* @f2() nounwind + ret void +} + +declare void @abort() noreturn nounwind + +declare void @f2(...) diff --git a/test/CodeGen/Mips/blockaddr.ll b/test/CodeGen/Mips/blockaddr.ll new file mode 100644 index 000000000000..e9af3045e15f --- /dev/null +++ b/test/CodeGen/Mips/blockaddr.ll @@ -0,0 +1,31 @@ +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=CHECK-PIC +; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC + +@reg = common global i8* null, align 4 + +define i8* @dummy(i8* %x) nounwind readnone noinline { +entry: + ret i8* %x +} + +; CHECK-PIC: lw $[[R0:[0-9]+]], %got($tmp1)($gp) +; CHECK-PIC: addiu ${{[0-9]+}}, $[[R0]], %lo($tmp1) +; CHECK-PIC: lw $[[R1:[0-9]+]], %got($tmp2)($gp) +; CHECK-PIC: addiu ${{[0-9]+}}, $[[R1]], %lo($tmp2) +; CHECK-STATIC: lui $[[R2:[0-9]+]], %hi($tmp1) +; CHECK-STATIC: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp1) +; CHECK-STATIC: lui $[[R3:[0-9]+]], %hi($tmp2) +; CHECK-STATIC: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp2) +define void @f() nounwind { +entry: + %call = tail call i8* @dummy(i8* blockaddress(@f, %baz)) + indirectbr i8* %call, [label %baz, label %foo] + +foo: ; preds = %foo, %entry + store i8* blockaddress(@f, %foo), i8** @reg, align 4 + br label %foo + +baz: ; preds = %entry + store i8* null, i8** @reg, align 4 + ret void +} diff --git a/test/CodeGen/Mips/buildpairextractelementf64.ll b/test/CodeGen/Mips/buildpairextractelementf64.ll new file mode 100644 index 000000000000..585bc250fb8c --- /dev/null +++ b/test/CodeGen/Mips/buildpairextractelementf64.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -march=mipsel | FileCheck %s +; RUN: llc < %s -march=mips | FileCheck %s +@a = external global i32 + +define double @f(i32 %a1, double %d) nounwind { +entry: +; CHECK: mtc1 +; CHECK: mtc1 + store i32 %a1, i32* @a, align 4 + %add = fadd double %d, 2.000000e+00 + ret double %add +} + +define void @f3(double %d, i32 %a1) nounwind { +entry: +; CHECK: mfc1 +; CHECK: mfc1 + tail call void @f2(i32 %a1, double %d) nounwind + ret void +} + +declare void @f2(i32, double) + diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll index 7d3e0252e3c9..8329c891f0c2 100755 --- a/test/CodeGen/Mips/cmov.ll +++ b/test/CodeGen/Mips/cmov.ll @@ -1,10 +1,11 @@ ; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s +; RUN: llc -march=mips -mcpu=4ke -regalloc=basic < %s | FileCheck %s @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4 @i3 = common global i32* null, align 4 -; CHECK: lw $3, %got(i3)($gp) -; CHECK: addiu $5, $gp, %got(i1) +; CHECK: lw ${{[0-9]+}}, %got(i3)($gp) +; CHECK: addiu ${{[0-9]+}}, $gp, %got(i1) define i32* @cmov1(i32 %s) nounwind readonly { entry: %tobool = icmp ne i32 %s, 0 diff --git a/test/CodeGen/Mips/divrem.ll b/test/CodeGen/Mips/divrem.ll new file mode 100644 index 000000000000..398d1b78bd43 --- /dev/null +++ b/test/CodeGen/Mips/divrem.ll @@ -0,0 +1,51 @@ +; RUN: llc -march=mips < %s | FileCheck %s + +; CHECK: div $zero, +define i32 @sdiv1(i32 %a0, i32 %a1) nounwind readnone { +entry: + %div = sdiv i32 %a0, %a1 + ret i32 %div +} + +; CHECK: div $zero, +define i32 @srem1(i32 %a0, i32 %a1) nounwind readnone { +entry: + %rem = srem i32 %a0, %a1 + ret i32 %rem +} + +; CHECK: divu $zero, +define i32 @udiv1(i32 %a0, i32 %a1) nounwind readnone { +entry: + %div = udiv i32 %a0, %a1 + ret i32 %div +} + +; CHECK: divu $zero, +define i32 @urem1(i32 %a0, i32 %a1) nounwind readnone { +entry: + %rem = urem i32 %a0, %a1 + ret i32 %rem +} + +; CHECK: div $zero, +define i32 @sdivrem1(i32 %a0, i32 %a1, i32* nocapture %r) nounwind { +entry: + %rem = srem i32 %a0, %a1 + store i32 %rem, i32* %r, align 4, !tbaa !0 + %div = sdiv i32 %a0, %a1 + ret i32 %div +} + +; CHECK: divu $zero, +define i32 @udivrem1(i32 %a0, i32 %a1, i32* nocapture %r) nounwind { +entry: + %rem = urem i32 %a0, %a1 + store i32 %rem, i32* %r, align 4, !tbaa !0 + %div = udiv i32 %a0, %a1 + ret i32 %div +} + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/Mips/fpbr.ll b/test/CodeGen/Mips/fpbr.ll new file mode 100644 index 000000000000..0a6478b0f8f0 --- /dev/null +++ b/test/CodeGen/Mips/fpbr.ll @@ -0,0 +1,119 @@ +; RUN: llc < %s -march=mipsel | FileCheck %s + +define void @func0(float %f2, float %f3) nounwind { +entry: +; CHECK: c.eq.s +; CHECK: bc1f + %cmp = fcmp oeq float %f2, %f3 + br i1 %cmp, label %if.then, label %if.else + +if.then: ; preds = %entry + tail call void (...)* @g0() nounwind + br label %if.end + +if.else: ; preds = %entry + tail call void (...)* @g1() nounwind + br label %if.end + +if.end: ; preds = %if.else, %if.then + ret void +} + +declare void @g0(...) + +declare void @g1(...) + +define void @func1(float %f2, float %f3) nounwind { +entry: +; CHECK: c.olt.s +; CHECK: bc1f + %cmp = fcmp olt float %f2, %f3 + br i1 %cmp, label %if.then, label %if.else + +if.then: ; preds = %entry + tail call void (...)* @g0() nounwind + br label %if.end + +if.else: ; preds = %entry + tail call void (...)* @g1() nounwind + br label %if.end + +if.end: ; preds = %if.else, %if.then + ret void +} + +define void @func2(float %f2, float %f3) nounwind { +entry: +; CHECK: c.ole.s +; CHECK: bc1f + %cmp = fcmp ugt float %f2, %f3 + br i1 %cmp, label %if.else, label %if.then + +if.then: ; preds = %entry + tail call void (...)* @g0() nounwind + br label %if.end + +if.else: ; preds = %entry + tail call void (...)* @g1() nounwind + br label %if.end + +if.end: ; preds = %if.else, %if.then + ret void +} + +define void @func3(double %f2, double %f3) nounwind { +entry: +; CHECK: c.eq.d +; CHECK: bc1f + %cmp = fcmp oeq double %f2, %f3 + br i1 %cmp, label %if.then, label %if.else + +if.then: ; preds = %entry + tail call void (...)* @g0() nounwind + br label %if.end + +if.else: ; preds = %entry + tail call void (...)* @g1() nounwind + br label %if.end + +if.end: ; preds = %if.else, %if.then + ret void +} + +define void @func4(double %f2, double %f3) nounwind { +entry: +; CHECK: c.olt.d +; CHECK: bc1f + %cmp = fcmp olt double %f2, %f3 + br i1 %cmp, label %if.then, label %if.else + +if.then: ; preds = %entry + tail call void (...)* @g0() nounwind + br label %if.end + +if.else: ; preds = %entry + tail call void (...)* @g1() nounwind + br label %if.end + +if.end: ; preds = %if.else, %if.then + ret void +} + +define void @func5(double %f2, double %f3) nounwind { +entry: +; CHECK: c.ole.d +; CHECK: bc1f + %cmp = fcmp ugt double %f2, %f3 + br i1 %cmp, label %if.else, label %if.then + +if.then: ; preds = %entry + tail call void (...)* @g0() nounwind + br label %if.end + +if.else: ; preds = %entry + tail call void (...)* @g1() nounwind + br label %if.end + +if.end: ; preds = %if.else, %if.then + ret void +} diff --git a/test/CodeGen/Mips/fpcmp.ll b/test/CodeGen/Mips/fpcmp.ll new file mode 100644 index 000000000000..c89ffe67f1b9 --- /dev/null +++ b/test/CodeGen/Mips/fpcmp.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2 +; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-MIPS1 + +@g1 = external global i32 + +define i32 @f(float %f0, float %f1) nounwind { +entry: +; CHECK-MIPS32R2: c.olt.s +; CHECK-MIPS32R2: movt +; CHECK-MIPS32R2: c.olt.s +; CHECK-MIPS32R2: movt +; CHECK-MIPS1: c.olt.s +; CHECK-MIPS1: bc1t +; CHECK-MIPS1: c.olt.s +; CHECK-MIPS1: bc1t + %cmp = fcmp olt float %f0, %f1 + %conv = zext i1 %cmp to i32 + %tmp2 = load i32* @g1, align 4 + %add = add nsw i32 %tmp2, %conv + store i32 %add, i32* @g1, align 4 + %cond = select i1 %cmp, i32 10, i32 20 + ret i32 %cond +} diff --git a/test/CodeGen/Mips/internalfunc.ll b/test/CodeGen/Mips/internalfunc.ll new file mode 100644 index 000000000000..fdfa01a9e0f7 --- /dev/null +++ b/test/CodeGen/Mips/internalfunc.ll @@ -0,0 +1,52 @@ +; RUN: llc < %s -march=mips | FileCheck %s + +@caller.sf1 = internal unnamed_addr global void (...)* null, align 4 +@gf1 = external global void (...)* +@.str = private unnamed_addr constant [3 x i8] c"f2\00" + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind { +entry: +; CHECK: lw $[[R0:[0-9]+]], %got(f2)($gp) +; CHECK: addiu $25, $[[R0]], %lo(f2) + tail call fastcc void @f2() + ret i32 0 +} + +define void @caller(i32 %a0, i32 %a1) nounwind { +entry: +; CHECK: lw $[[R1:[0-9]+]], %got(caller.sf1)($gp) +; CHECK: addiu ${{[0-9]+}}, $[[R1]], %lo(caller.sf1) + %tobool = icmp eq i32 %a1, 0 + br i1 %tobool, label %if.end, label %if.then + +if.then: ; preds = %entry + %tmp1 = load void (...)** @caller.sf1, align 4 + tail call void (...)* %tmp1() nounwind + br label %if.end + +if.end: ; preds = %entry, %if.then +; CHECK: lw $[[R2:[0-9]+]], %got(sf2)($gp) +; CHECK: lw $[[R3:[0-9]+]], %got(caller.sf1)($gp) +; CHECK: addiu ${{[0-9]+}}, $[[R2]], %lo(sf2) +; CHECK: addiu ${{[0-9]+}}, $[[R3]], %lo(caller.sf1) + %tobool3 = icmp ne i32 %a0, 0 + %tmp4 = load void (...)** @gf1, align 4 + %cond = select i1 %tobool3, void (...)* %tmp4, void (...)* bitcast (void ()* @sf2 to void (...)*) + store void (...)* %cond, void (...)** @caller.sf1, align 4 + ret void +} + +define internal void @sf2() nounwind { +entry: + %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0)) nounwind + ret void +} + +declare i32 @printf(i8* nocapture, ...) nounwind + +define internal fastcc void @f2() nounwind noinline { +entry: + %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0)) nounwind + ret void +} + diff --git a/test/CodeGen/Mips/largeimm1.ll b/test/CodeGen/Mips/largeimm1.ll new file mode 100644 index 000000000000..d65cc025d085 --- /dev/null +++ b/test/CodeGen/Mips/largeimm1.ll @@ -0,0 +1,13 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s + +; CHECK: lui $at, 49152 +; CHECK: lui $at, 16384 +define void @f() nounwind { +entry: + %a1 = alloca [1073741824 x i8], align 1 + %arrayidx = getelementptr inbounds [1073741824 x i8]* %a1, i32 0, i32 1048676 + call void @f2(i8* %arrayidx) nounwind + ret void +} + +declare void @f2(i8*) diff --git a/test/CodeGen/Mips/o32_cc.ll b/test/CodeGen/Mips/o32_cc.ll index b6df62be6603..3974cd4a6a76 100644 --- a/test/CodeGen/Mips/o32_cc.ll +++ b/test/CodeGen/Mips/o32_cc.ll @@ -61,8 +61,8 @@ entry: declare void @f4(i32, i32, i32, i32) ; $f12, $6, stack -; CHECK: sw $2, 16($sp) -; CHECK: sw $zero, 20($sp) +; CHECK: sw +; CHECK: sw ; CHECK: ldc1 $f12, %lo ; CHECK: addiu $6, $zero, 23 define void @testlowercall5() nounwind { @@ -98,8 +98,8 @@ entry: declare void @f7(float, i32, i32) ; $4, $5, $6, stack -; CHECK: sw $2, 16($sp) -; CHECK: sw $zero, 20($sp) +; CHECK: sw +; CHECK: sw ; CHECK: addiu $4, $zero, 22 ; CHECK: addiu $5, $zero, 53 ; CHECK: addiu $6, $zero, 44 @@ -115,7 +115,7 @@ declare void @f8(i32, i32, i32, double) ; CHECK: addiu $4, $zero, 32 ; CHECK: addiu $5, $zero, 63 ; CHECK: addiu $6, $zero, 54 -; CHECK: ori $7, $2, 0 +; CHECK: ori $7 define void @testlowercall9() nounwind { entry: tail call void @f9(i32 32, i32 63, i32 54, float 1.100000e+01) nounwind @@ -128,7 +128,7 @@ declare void @f9(i32, i32, i32, float) ; CHECK: addiu $4, $zero, 42 ; CHECK: addiu $5, $zero, 73 ; CHECK: addiu $6, $zero, 0 -; CHECK: ori $7, $2, 0 +; CHECK: ori $7 define void @testlowercall10() nounwind { entry: tail call void @f10(i32 42, i32 73, double 2.700000e+01) nounwind @@ -140,7 +140,7 @@ declare void @f10(i32, i32, double) ; $4, ($6, $7) ; CHECK: addiu $4, $zero, 52 ; CHECK: addiu $6, $zero, 0 -; CHECK: ori $7, $2, 0 +; CHECK: ori $7 define void @testlowercall11() nounwind { entry: tail call void @f11(i32 52, double 1.600000e+01) nounwind @@ -152,8 +152,8 @@ declare void @f11(i32, double) ; $f12, $f14, $6, $7 ; CHECK: lwc1 $f12, %lo ; CHECK: lwc1 $f14, %lo -; CHECK: ori $6, $4, 0 -; CHECK: ori $7, $5, 0 +; CHECK: ori $6 +; CHECK: ori $7 define void @testlowercall12() nounwind { entry: tail call void @f12(float 2.800000e+01, float 1.900000e+01, float 1.000000e+01, float 2.100000e+01) nounwind @@ -165,7 +165,7 @@ declare void @f12(float, float, float, float) ; $f12, $5, $6, $7 ; CHECK: lwc1 $f12, %lo ; CHECK: addiu $5, $zero, 83 -; CHECK: ori $6, $3, 0 +; CHECK: ori $6 ; CHECK: addiu $7, $zero, 25 define void @testlowercall13() nounwind { entry: @@ -179,7 +179,7 @@ declare void @f13(float, i32, float, i32) ; $f12, $f14, $7 ; CHECK: ldc1 $f12, %lo ; CHECK: lwc1 $f14, %lo -; CHECK: ori $7, $4, 0 +; CHECK: ori $7 define void @testlowercall14() nounwind { entry: tail call void @f14(double 3.500000e+01, float 2.900000e+01, float 3.000000e+01) nounwind @@ -192,7 +192,7 @@ declare void @f14(double, float, float) ; CHECK: lwc1 $f12, %lo ; CHECK: lwc1 $f14, %lo ; CHECK: addiu $6, $zero, 0 -; CHECK: ori $7, $4, 32768 +; CHECK: ori $7 define void @testlowercall15() nounwind { entry: tail call void @f15(float 4.800000e+01, float 3.900000e+01, double 3.700000e+01) nounwind @@ -203,9 +203,9 @@ declare void @f15(float, float, double) ; $4, $5, $6, $7 ; CHECK: addiu $4, $zero, 62 -; CHECK: ori $5, $2, 0 +; CHECK: ori $5 ; CHECK: addiu $6, $zero, 64 -; CHECK: ori $7, $3, 0 +; CHECK: ori $7 define void @testlowercall16() nounwind { entry: tail call void @f16(i32 62, float 4.900000e+01, i32 64, float 3.100000e+01) nounwind @@ -216,7 +216,7 @@ declare void @f16(i32, float, i32, float) ; $4, $5, $6, $7 ; CHECK: addiu $4, $zero, 72 -; CHECK: ori $5, $2, 0 +; CHECK: ori $5 ; CHECK: addiu $6, $zero, 74 ; CHECK: addiu $7, $zero, 35 define void @testlowercall17() nounwind { @@ -230,7 +230,7 @@ declare void @f17(i32, float, i32, i32) ; $4, $5, $6, $7 ; CHECK: addiu $4, $zero, 82 ; CHECK: addiu $5, $zero, 93 -; CHECK: ori $6, $2, 0 +; CHECK: ori $6 ; CHECK: addiu $7, $zero, 45 define void @testlowercall18() nounwind { entry: @@ -242,11 +242,11 @@ declare void @f18(i32, i32, float, i32) ; $4, ($6, $7), stack -; CHECK: sw $2, 16($sp) -; CHECK: sw $zero, 20($sp) +; CHECK: sw +; CHECK: sw ; CHECK: addiu $4, $zero, 92 ; CHECK: addiu $6, $zero, 0 -; CHECK: ori $7, $3, 0 +; CHECK: ori $7 define void @testlowercall20() nounwind { entry: tail call void @f20(i32 92, double 2.600000e+01, double 4.700000e+01) nounwind @@ -270,7 +270,7 @@ declare void @f21(float, i32) ; CHECK: lwc1 $f12, %lo ; CHECK: addiu $5, $zero, 113 ; CHECK: addiu $6, $zero, 0 -; CHECK: ori $7, $3, 32768 +; CHECK: ori $7 define void @testlowercall22() nounwind { entry: tail call void @f22(float 6.800000e+01, i32 113, double 5.700000e+01) nounwind @@ -291,8 +291,8 @@ entry: declare void @f23(double, i32) ; $f12,$6, stack -; CHECK: sw $2, 16($sp) -; CHECK: sw $zero, 20($sp) +; CHECK: sw +; CHECK: sw ; CHECK: ldc1 $f12, %lo ; CHECK: addiu $6, $zero, 133 define void @testlowercall24() nounwind { @@ -306,15 +306,15 @@ declare void @f24(double, i32, double) ; CHECK: lwc1 $f12, %lo ; lwc1 $f12, %lo ; CHECK: lwc1 $f14, %lo -; CHECK: ori $6, $4, 0 -; CHECK: ori $7, $5, 0 +; CHECK: ori $6 +; CHECK: ori $7 ; CHECK: lwc1 $f12, %lo ; CHECK: addiu $5, $zero, 83 -; CHECK: ori $6, $3, 0 +; CHECK: ori $6 ; CHECK: addiu $7, $zero, 25 ; CHECK: addiu $4, $zero, 82 ; CHECK: addiu $5, $zero, 93 -; CHECK: ori $6, $2, 0 +; CHECK: ori $6 ; CHECK: addiu $7, $zero, 45 define void @testlowercall25() nounwind { entry: diff --git a/test/CodeGen/Mips/o32_cc_vararg.ll b/test/CodeGen/Mips/o32_cc_vararg.ll new file mode 100644 index 000000000000..1f71ed2640eb --- /dev/null +++ b/test/CodeGen/Mips/o32_cc_vararg.ll @@ -0,0 +1,278 @@ +; RUN: llc -march=mipsel -mcpu=mips2 -pre-RA-sched=source < %s | FileCheck %s +; RUN: llc -march=mipsel -mcpu=mips2 -pre-RA-sched=source < %s -regalloc=basic | FileCheck %s + + +; All test functions do the same thing - they return the first variable +; argument. + +; All CHECK's do the same thing - they check whether variable arguments from +; registers are placed on correct stack locations, and whether the first +; variable argument is returned from the correct stack location. + + +declare void @llvm.va_start(i8*) nounwind +declare void @llvm.va_end(i8*) nounwind + +; return int +define i32 @va1(i32 %a, ...) nounwind { +entry: + %a.addr = alloca i32, align 4 + %ap = alloca i8*, align 4 + %b = alloca i32, align 4 + store i32 %a, i32* %a.addr, align 4 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + %0 = va_arg i8** %ap, i32 + store i32 %0, i32* %b, align 4 + %ap2 = bitcast i8** %ap to i8* + call void @llvm.va_end(i8* %ap2) + %tmp = load i32* %b, align 4 + ret i32 %tmp + +; CHECK: va1: +; CHECK: addiu $sp, $sp, -32 +; CHECK: sw $7, 44($sp) +; CHECK: sw $6, 40($sp) +; CHECK: sw $5, 36($sp) +; CHECK: lw $2, 36($sp) +} + +; check whether the variable double argument will be accessed from the 8-byte +; aligned location (i.e. whether the address is computed by adding 7 and +; clearing lower 3 bits) +define double @va2(i32 %a, ...) nounwind { +entry: + %a.addr = alloca i32, align 4 + %ap = alloca i8*, align 4 + %b = alloca double, align 8 + store i32 %a, i32* %a.addr, align 4 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + %0 = va_arg i8** %ap, double + store double %0, double* %b, align 8 + %ap2 = bitcast i8** %ap to i8* + call void @llvm.va_end(i8* %ap2) + %tmp = load double* %b, align 8 + ret double %tmp + +; CHECK: va2: +; CHECK: addiu $sp, $sp, -40 +; CHECK: sw $7, 52($sp) +; CHECK: sw $6, 48($sp) +; CHECK: sw $5, 44($sp) +; CHECK: addiu $[[R0:[0-9]+]], $sp, 44 +; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7 +; CHECK: addiu $[[R2:[0-9]+]], $zero, -8 +; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]] +; CHECK: ldc1 $f0, 0($[[R3]]) +} + +; int +define i32 @va3(double %a, ...) nounwind { +entry: + %a.addr = alloca double, align 8 + %ap = alloca i8*, align 4 + %b = alloca i32, align 4 + store double %a, double* %a.addr, align 8 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + %0 = va_arg i8** %ap, i32 + store i32 %0, i32* %b, align 4 + %ap2 = bitcast i8** %ap to i8* + call void @llvm.va_end(i8* %ap2) + %tmp = load i32* %b, align 4 + ret i32 %tmp + +; CHECK: va3: +; CHECK: addiu $sp, $sp, -40 +; CHECK: sw $7, 52($sp) +; CHECK: sw $6, 48($sp) +; CHECK: lw $2, 48($sp) +} + +; double +define double @va4(double %a, ...) nounwind { +entry: + %a.addr = alloca double, align 8 + %ap = alloca i8*, align 4 + %b = alloca double, align 8 + store double %a, double* %a.addr, align 8 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + %0 = va_arg i8** %ap, double + store double %0, double* %b, align 8 + %ap2 = bitcast i8** %ap to i8* + call void @llvm.va_end(i8* %ap2) + %tmp = load double* %b, align 8 + ret double %tmp + +; CHECK: va4: +; CHECK: addiu $sp, $sp, -48 +; CHECK: sw $7, 60($sp) +; CHECK: sw $6, 56($sp) +; CHECK: addiu $[[R0:[0-9]+]], $sp, 56 +; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7 +; CHECK: addiu $[[R2:[0-9]+]], $zero, -8 +; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]] +; CHECK: ldc1 $f0, 0($[[R3]]) +} + +; int +define i32 @va5(i32 %a, i32 %b, i32 %c, ...) nounwind { +entry: + %a.addr = alloca i32, align 4 + %b.addr = alloca i32, align 4 + %c.addr = alloca i32, align 4 + %ap = alloca i8*, align 4 + %d = alloca i32, align 4 + store i32 %a, i32* %a.addr, align 4 + store i32 %b, i32* %b.addr, align 4 + store i32 %c, i32* %c.addr, align 4 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + %0 = va_arg i8** %ap, i32 + store i32 %0, i32* %d, align 4 + %ap2 = bitcast i8** %ap to i8* + call void @llvm.va_end(i8* %ap2) + %tmp = load i32* %d, align 4 + ret i32 %tmp + +; CHECK: va5: +; CHECK: addiu $sp, $sp, -40 +; CHECK: sw $7, 52($sp) +; CHECK: lw $2, 52($sp) +} + +; double +define double @va6(i32 %a, i32 %b, i32 %c, ...) nounwind { +entry: + %a.addr = alloca i32, align 4 + %b.addr = alloca i32, align 4 + %c.addr = alloca i32, align 4 + %ap = alloca i8*, align 4 + %d = alloca double, align 8 + store i32 %a, i32* %a.addr, align 4 + store i32 %b, i32* %b.addr, align 4 + store i32 %c, i32* %c.addr, align 4 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + %0 = va_arg i8** %ap, double + store double %0, double* %d, align 8 + %ap2 = bitcast i8** %ap to i8* + call void @llvm.va_end(i8* %ap2) + %tmp = load double* %d, align 8 + ret double %tmp + +; CHECK: va6: +; CHECK: addiu $sp, $sp, -48 +; CHECK: sw $7, 60($sp) +; CHECK: addiu $[[R0:[0-9]+]], $sp, 60 +; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7 +; CHECK: addiu $[[R2:[0-9]+]], $zero, -8 +; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]] +; CHECK: ldc1 $f0, 0($[[R3]]) +} + +; int +define i32 @va7(i32 %a, double %b, ...) nounwind { +entry: + %a.addr = alloca i32, align 4 + %b.addr = alloca double, align 8 + %ap = alloca i8*, align 4 + %c = alloca i32, align 4 + store i32 %a, i32* %a.addr, align 4 + store double %b, double* %b.addr, align 8 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + %0 = va_arg i8** %ap, i32 + store i32 %0, i32* %c, align 4 + %ap2 = bitcast i8** %ap to i8* + call void @llvm.va_end(i8* %ap2) + %tmp = load i32* %c, align 4 + ret i32 %tmp + +; CHECK: va7: +; CHECK: addiu $sp, $sp, -40 +; CHECK: lw $2, 56($sp) +} + +; double +define double @va8(i32 %a, double %b, ...) nounwind { +entry: + %a.addr = alloca i32, align 4 + %b.addr = alloca double, align 8 + %ap = alloca i8*, align 4 + %c = alloca double, align 8 + store i32 %a, i32* %a.addr, align 4 + store double %b, double* %b.addr, align 8 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + %0 = va_arg i8** %ap, double + store double %0, double* %c, align 8 + %ap2 = bitcast i8** %ap to i8* + call void @llvm.va_end(i8* %ap2) + %tmp = load double* %c, align 8 + ret double %tmp + +; CHECK: va8: +; CHECK: addiu $sp, $sp, -48 +; CHECK: addiu $[[R0:[0-9]+]], $sp, 64 +; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7 +; CHECK: addiu $[[R2:[0-9]+]], $zero, -8 +; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]] +; CHECK: ldc1 $f0, 0($[[R3]]) +} + +; int +define i32 @va9(double %a, double %b, i32 %c, ...) nounwind { +entry: + %a.addr = alloca double, align 8 + %b.addr = alloca double, align 8 + %c.addr = alloca i32, align 4 + %ap = alloca i8*, align 4 + %d = alloca i32, align 4 + store double %a, double* %a.addr, align 8 + store double %b, double* %b.addr, align 8 + store i32 %c, i32* %c.addr, align 4 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + %0 = va_arg i8** %ap, i32 + store i32 %0, i32* %d, align 4 + %ap2 = bitcast i8** %ap to i8* + call void @llvm.va_end(i8* %ap2) + %tmp = load i32* %d, align 4 + ret i32 %tmp + +; CHECK: va9: +; CHECK: addiu $sp, $sp, -56 +; CHECK: lw $2, 76($sp) +} + +; double +define double @va10(double %a, double %b, i32 %c, ...) nounwind { +entry: + %a.addr = alloca double, align 8 + %b.addr = alloca double, align 8 + %c.addr = alloca i32, align 4 + %ap = alloca i8*, align 4 + %d = alloca double, align 8 + store double %a, double* %a.addr, align 8 + store double %b, double* %b.addr, align 8 + store i32 %c, i32* %c.addr, align 4 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + %0 = va_arg i8** %ap, double + store double %0, double* %d, align 8 + %ap2 = bitcast i8** %ap to i8* + call void @llvm.va_end(i8* %ap2) + %tmp = load double* %d, align 8 + ret double %tmp + +; CHECK: va10: +; CHECK: addiu $sp, $sp, -56 +; CHECK: addiu $[[R0:[0-9]+]], $sp, 76 +; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7 +; CHECK: addiu $[[R2:[0-9]+]], $zero, -8 +; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]] +; CHECK: ldc1 $f0, 0($[[R3]]) +} diff --git a/test/CodeGen/Mips/select.ll b/test/CodeGen/Mips/select.ll new file mode 100644 index 000000000000..c83fa3ece026 --- /dev/null +++ b/test/CodeGen/Mips/select.ll @@ -0,0 +1,196 @@ +; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2 +; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=CHECK-MIPS1 + +@d2 = external global double +@d3 = external global double + +define i32 @sel1(i32 %s, i32 %f0, i32 %f1) nounwind readnone { +entry: +; CHECK-MIPS32R2: movn +; CHECK-MIPS1: beq + %tobool = icmp ne i32 %s, 0 + %cond = select i1 %tobool, i32 %f1, i32 %f0 + ret i32 %cond +} + +define float @sel2(i32 %s, float %f0, float %f1) nounwind readnone { +entry: +; CHECK-MIPS32R2: movn.s +; CHECK-MIPS1: beq + %tobool = icmp ne i32 %s, 0 + %cond = select i1 %tobool, float %f0, float %f1 + ret float %cond +} + +define double @sel2_1(i32 %s, double %f0, double %f1) nounwind readnone { +entry: +; CHECK-MIPS32R2: movn.d +; CHECK-MIPS1: beq + %tobool = icmp ne i32 %s, 0 + %cond = select i1 %tobool, double %f0, double %f1 + ret double %cond +} + +define float @sel3(float %f0, float %f1, float %f2, float %f3) nounwind readnone { +entry: +; CHECK-MIPS32R2: c.eq.s +; CHECK-MIPS32R2: movt.s +; CHECK-MIPS1: c.eq.s +; CHECK-MIPS1: bc1f + %cmp = fcmp oeq float %f2, %f3 + %cond = select i1 %cmp, float %f0, float %f1 + ret float %cond +} + +define float @sel4(float %f0, float %f1, float %f2, float %f3) nounwind readnone { +entry: +; CHECK-MIPS32R2: c.olt.s +; CHECK-MIPS32R2: movt.s +; CHECK-MIPS1: c.olt.s +; CHECK-MIPS1: bc1f + %cmp = fcmp olt float %f2, %f3 + %cond = select i1 %cmp, float %f0, float %f1 + ret float %cond +} + +define float @sel5(float %f0, float %f1, float %f2, float %f3) nounwind readnone { +entry: +; CHECK-MIPS32R2: c.ule.s +; CHECK-MIPS32R2: movf.s +; CHECK-MIPS1: c.ule.s +; CHECK-MIPS1: bc1t + %cmp = fcmp ogt float %f2, %f3 + %cond = select i1 %cmp, float %f0, float %f1 + ret float %cond +} + +define double @sel5_1(double %f0, double %f1, float %f2, float %f3) nounwind readnone { +entry: +; CHECK-MIPS32R2: c.ule.s +; CHECK-MIPS32R2: movf.d +; CHECK-MIPS1: c.ule.s +; CHECK-MIPS1: bc1t + %cmp = fcmp ogt float %f2, %f3 + %cond = select i1 %cmp, double %f0, double %f1 + ret double %cond +} + +define double @sel6(double %f0, double %f1, double %f2, double %f3) nounwind readnone { +entry: +; CHECK-MIPS32R2: c.eq.d +; CHECK-MIPS32R2: movt.d +; CHECK-MIPS1: c.eq.d +; CHECK-MIPS1: bc1f + %cmp = fcmp oeq double %f2, %f3 + %cond = select i1 %cmp, double %f0, double %f1 + ret double %cond +} + +define double @sel7(double %f0, double %f1, double %f2, double %f3) nounwind readnone { +entry: +; CHECK-MIPS32R2: c.olt.d +; CHECK-MIPS32R2: movt.d +; CHECK-MIPS1: c.olt.d +; CHECK-MIPS1: bc1f + %cmp = fcmp olt double %f2, %f3 + %cond = select i1 %cmp, double %f0, double %f1 + ret double %cond +} + +define double @sel8(double %f0, double %f1, double %f2, double %f3) nounwind readnone { +entry: +; CHECK-MIPS32R2: c.ule.d +; CHECK-MIPS32R2: movf.d +; CHECK-MIPS1: c.ule.d +; CHECK-MIPS1: bc1t + %cmp = fcmp ogt double %f2, %f3 + %cond = select i1 %cmp, double %f0, double %f1 + ret double %cond +} + +define float @sel8_1(float %f0, float %f1, double %f2, double %f3) nounwind readnone { +entry: +; CHECK-MIPS32R2: c.ule.d +; CHECK-MIPS32R2: movf.s +; CHECK-MIPS1: c.ule.d +; CHECK-MIPS1: bc1t + %cmp = fcmp ogt double %f2, %f3 + %cond = select i1 %cmp, float %f0, float %f1 + ret float %cond +} + +define i32 @sel9(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone { +entry: +; CHECK-MIPS32R2: c.eq.s +; CHECK-MIPS32R2: movt +; CHECK-MIPS1: c.eq.s +; CHECK-MIPS1: bc1f + %cmp = fcmp oeq float %f2, %f3 + %cond = select i1 %cmp, i32 %f0, i32 %f1 + ret i32 %cond +} + +define i32 @sel10(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone { +entry: +; CHECK-MIPS32R2: c.olt.s +; CHECK-MIPS32R2: movt +; CHECK-MIPS1: c.olt.s +; CHECK-MIPS1: bc1f + %cmp = fcmp olt float %f2, %f3 + %cond = select i1 %cmp, i32 %f0, i32 %f1 + ret i32 %cond +} + +define i32 @sel11(i32 %f0, i32 %f1, float %f2, float %f3) nounwind readnone { +entry: +; CHECK-MIPS32R2: c.ule.s +; CHECK-MIPS32R2: movf +; CHECK-MIPS1: c.ule.s +; CHECK-MIPS1: bc1t + %cmp = fcmp ogt float %f2, %f3 + %cond = select i1 %cmp, i32 %f0, i32 %f1 + ret i32 %cond +} + +define i32 @sel12(i32 %f0, i32 %f1) nounwind readonly { +entry: +; CHECK-MIPS32R2: c.eq.d +; CHECK-MIPS32R2: movt +; CHECK-MIPS1: c.eq.d +; CHECK-MIPS1: bc1f + %tmp = load double* @d2, align 8, !tbaa !0 + %tmp1 = load double* @d3, align 8, !tbaa !0 + %cmp = fcmp oeq double %tmp, %tmp1 + %cond = select i1 %cmp, i32 %f0, i32 %f1 + ret i32 %cond +} + +define i32 @sel13(i32 %f0, i32 %f1) nounwind readonly { +entry: +; CHECK-MIPS32R2: c.olt.d +; CHECK-MIPS32R2: movt +; CHECK-MIPS1: c.olt.d +; CHECK-MIPS1: bc1f + %tmp = load double* @d2, align 8, !tbaa !0 + %tmp1 = load double* @d3, align 8, !tbaa !0 + %cmp = fcmp olt double %tmp, %tmp1 + %cond = select i1 %cmp, i32 %f0, i32 %f1 + ret i32 %cond +} + +define i32 @sel14(i32 %f0, i32 %f1) nounwind readonly { +entry: +; CHECK-MIPS32R2: c.ule.d +; CHECK-MIPS32R2: movf +; CHECK-MIPS1: c.ule.d +; CHECK-MIPS1: bc1t + %tmp = load double* @d2, align 8, !tbaa !0 + %tmp1 = load double* @d3, align 8, !tbaa !0 + %cmp = fcmp ogt double %tmp, %tmp1 + %cond = select i1 %cmp, i32 %f0, i32 %f1 + ret i32 %cond +} + +!0 = metadata !{metadata !"double", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/PTX/add.ll b/test/CodeGen/PTX/add.ll index 1259d03e96c9..235b00e8782f 100644 --- a/test/CodeGen/PTX/add.ll +++ b/test/CodeGen/PTX/add.ll @@ -1,15 +1,71 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s -define ptx_device i32 @t1(i32 %x, i32 %y) { -; CHECK: add.s32 r0, r1, r2; +define ptx_device i16 @t1_u16(i16 %x, i16 %y) { +; CHECK: add.u16 rh0, rh1, rh2; +; CHECK-NEXT: ret; + %z = add i16 %x, %y + ret i16 %z +} + +define ptx_device i32 @t1_u32(i32 %x, i32 %y) { +; CHECK: add.u32 r0, r1, r2; +; CHECK-NEXT: ret; %z = add i32 %x, %y -; CHECK: ret; ret i32 %z } -define ptx_device i32 @t2(i32 %x) { -; CHECK: add.s32 r0, r1, 1; +define ptx_device i64 @t1_u64(i64 %x, i64 %y) { +; CHECK: add.u64 rd0, rd1, rd2; +; CHECK-NEXT: ret; + %z = add i64 %x, %y + ret i64 %z +} + +define ptx_device float @t1_f32(float %x, float %y) { +; CHECK: add.f32 f0, f1, f2 +; CHECK-NEXT: ret; + %z = fadd float %x, %y + ret float %z +} + +define ptx_device double @t1_f64(double %x, double %y) { +; CHECK: add.f64 fd0, fd1, fd2 +; CHECK-NEXT: ret; + %z = fadd double %x, %y + ret double %z +} + +define ptx_device i16 @t2_u16(i16 %x) { +; CHECK: add.u16 rh0, rh1, 1; +; CHECK-NEXT: ret; + %z = add i16 %x, 1 + ret i16 %z +} + +define ptx_device i32 @t2_u32(i32 %x) { +; CHECK: add.u32 r0, r1, 1; +; CHECK-NEXT: ret; %z = add i32 %x, 1 -; CHECK: ret; ret i32 %z } + +define ptx_device i64 @t2_u64(i64 %x) { +; CHECK: add.u64 rd0, rd1, 1; +; CHECK-NEXT: ret; + %z = add i64 %x, 1 + ret i64 %z +} + +define ptx_device float @t2_f32(float %x) { +; CHECK: add.f32 f0, f1, 0F3F800000; +; CHECK-NEXT: ret; + %z = fadd float %x, 1.0 + ret float %z +} + +define ptx_device double @t2_f64(double %x) { +; CHECK: add.f64 fd0, fd1, 0D3FF0000000000000; +; CHECK-NEXT: ret; + %z = fadd double %x, 1.0 + ret double %z +} diff --git a/test/CodeGen/PTX/bitwise.ll b/test/CodeGen/PTX/bitwise.ll new file mode 100644 index 000000000000..dbc77e53330b --- /dev/null +++ b/test/CodeGen/PTX/bitwise.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -march=ptx32 | FileCheck %s + +; preds + +define ptx_device i32 @t1_and_preds(i1 %x, i1 %y) { +; CHECK: and.pred p0, p1, p2 + %c = and i1 %x, %y + %d = zext i1 %c to i32 + ret i32 %d +} + +define ptx_device i32 @t1_or_preds(i1 %x, i1 %y) { +; CHECK: or.pred p0, p1, p2 + %a = or i1 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +define ptx_device i32 @t1_xor_preds(i1 %x, i1 %y) { +; CHECK: xor.pred p0, p1, p2 + %a = xor i1 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} diff --git a/test/CodeGen/PTX/bra.ll b/test/CodeGen/PTX/bra.ll new file mode 100644 index 000000000000..49383eb3cf96 --- /dev/null +++ b/test/CodeGen/PTX/bra.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -march=ptx32 | FileCheck %s + +define ptx_device void @test_bra_direct() { +; CHECK: bra $L__BB0_1; +entry: + br label %loop +loop: + br label %loop +} + +define ptx_device i32 @test_bra_cond_direct(i32 %x, i32 %y) { +entry: +; CHECK: setp.le.u32 p0, r1, r2 + %p = icmp ugt i32 %x, %y +; CHECK-NEXT: @p0 bra +; CHECK-NOT: bra + br i1 %p, label %clause.if, label %clause.else +clause.if: +; CHECK: mov.u32 r0, r1 + ret i32 %x +clause.else: +; CHECK: mov.u32 r0, r2 + ret i32 %y +} diff --git a/test/CodeGen/PTX/exit.ll b/test/CodeGen/PTX/exit.ll index 4071babb80ce..7816c801728f 100644 --- a/test/CodeGen/PTX/exit.ll +++ b/test/CodeGen/PTX/exit.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s define ptx_kernel void @t1() { ; CHECK: exit; diff --git a/test/CodeGen/PTX/fdiv-sm10.ll b/test/CodeGen/PTX/fdiv-sm10.ll new file mode 100644 index 000000000000..121360ce9be3 --- /dev/null +++ b/test/CodeGen/PTX/fdiv-sm10.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=ptx32 -mattr=+sm10 | FileCheck %s + +define ptx_device float @t1_f32(float %x, float %y) { +; CHECK: div.approx.f32 f0, f1, f2; +; CHECK-NEXT: ret; + %a = fdiv float %x, %y + ret float %a +} + +define ptx_device double @t1_f64(double %x, double %y) { +; CHECK: div.f64 fd0, fd1, fd2; +; CHECK-NEXT: ret; + %a = fdiv double %x, %y + ret double %a +} diff --git a/test/CodeGen/PTX/fdiv-sm13.ll b/test/CodeGen/PTX/fdiv-sm13.ll new file mode 100644 index 000000000000..0ec7bae8030e --- /dev/null +++ b/test/CodeGen/PTX/fdiv-sm13.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=ptx32 -mattr=+sm13 | FileCheck %s + +define ptx_device float @t1_f32(float %x, float %y) { +; CHECK: div.approx.f32 f0, f1, f2; +; CHECK-NEXT: ret; + %a = fdiv float %x, %y + ret float %a +} + +define ptx_device double @t1_f64(double %x, double %y) { +; CHECK: div.rn.f64 fd0, fd1, fd2; +; CHECK-NEXT: ret; + %a = fdiv double %x, %y + ret double %a +} diff --git a/test/CodeGen/PTX/intrinsic.ll b/test/CodeGen/PTX/intrinsic.ll new file mode 100644 index 000000000000..cea41827ca47 --- /dev/null +++ b/test/CodeGen/PTX/intrinsic.ll @@ -0,0 +1,281 @@ +; RUN: llc < %s -march=ptx32 -mattr=+ptx20,+sm20 | FileCheck %s + +define ptx_device i32 @test_tid_x() { +; CHECK: mov.u32 r0, %tid.x; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.tid.x() + ret i32 %x +} + +define ptx_device i32 @test_tid_y() { +; CHECK: mov.u32 r0, %tid.y; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.tid.y() + ret i32 %x +} + +define ptx_device i32 @test_tid_z() { +; CHECK: mov.u32 r0, %tid.z; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.tid.z() + ret i32 %x +} + +define ptx_device i32 @test_tid_w() { +; CHECK: mov.u32 r0, %tid.w; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.tid.w() + ret i32 %x +} + +define ptx_device i32 @test_ntid_x() { +; CHECK: mov.u32 r0, %ntid.x; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.ntid.x() + ret i32 %x +} + +define ptx_device i32 @test_ntid_y() { +; CHECK: mov.u32 r0, %ntid.y; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.ntid.y() + ret i32 %x +} + +define ptx_device i32 @test_ntid_z() { +; CHECK: mov.u32 r0, %ntid.z; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.ntid.z() + ret i32 %x +} + +define ptx_device i32 @test_ntid_w() { +; CHECK: mov.u32 r0, %ntid.w; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.ntid.w() + ret i32 %x +} + +define ptx_device i32 @test_laneid() { +; CHECK: mov.u32 r0, %laneid; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.laneid() + ret i32 %x +} + +define ptx_device i32 @test_warpid() { +; CHECK: mov.u32 r0, %warpid; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.warpid() + ret i32 %x +} + +define ptx_device i32 @test_nwarpid() { +; CHECK: mov.u32 r0, %nwarpid; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.nwarpid() + ret i32 %x +} + +define ptx_device i32 @test_ctaid_x() { +; CHECK: mov.u32 r0, %ctaid.x; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.ctaid.x() + ret i32 %x +} + +define ptx_device i32 @test_ctaid_y() { +; CHECK: mov.u32 r0, %ctaid.y; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.ctaid.y() + ret i32 %x +} + +define ptx_device i32 @test_ctaid_z() { +; CHECK: mov.u32 r0, %ctaid.z; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.ctaid.z() + ret i32 %x +} + +define ptx_device i32 @test_ctaid_w() { +; CHECK: mov.u32 r0, %ctaid.w; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.ctaid.w() + ret i32 %x +} + +define ptx_device i32 @test_nctaid_x() { +; CHECK: mov.u32 r0, %nctaid.x; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.nctaid.x() + ret i32 %x +} + +define ptx_device i32 @test_nctaid_y() { +; CHECK: mov.u32 r0, %nctaid.y; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.nctaid.y() + ret i32 %x +} + +define ptx_device i32 @test_nctaid_z() { +; CHECK: mov.u32 r0, %nctaid.z; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.nctaid.z() + ret i32 %x +} + +define ptx_device i32 @test_nctaid_w() { +; CHECK: mov.u32 r0, %nctaid.w; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.nctaid.w() + ret i32 %x +} + +define ptx_device i32 @test_smid() { +; CHECK: mov.u32 r0, %smid; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.smid() + ret i32 %x +} + +define ptx_device i32 @test_nsmid() { +; CHECK: mov.u32 r0, %nsmid; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.nsmid() + ret i32 %x +} + +define ptx_device i32 @test_gridid() { +; CHECK: mov.u32 r0, %gridid; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.gridid() + ret i32 %x +} + +define ptx_device i32 @test_lanemask_eq() { +; CHECK: mov.u32 r0, %lanemask_eq; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.lanemask.eq() + ret i32 %x +} + +define ptx_device i32 @test_lanemask_le() { +; CHECK: mov.u32 r0, %lanemask_le; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.lanemask.le() + ret i32 %x +} + +define ptx_device i32 @test_lanemask_lt() { +; CHECK: mov.u32 r0, %lanemask_lt; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.lanemask.lt() + ret i32 %x +} + +define ptx_device i32 @test_lanemask_ge() { +; CHECK: mov.u32 r0, %lanemask_ge; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.lanemask.ge() + ret i32 %x +} + +define ptx_device i32 @test_lanemask_gt() { +; CHECK: mov.u32 r0, %lanemask_gt; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.lanemask.gt() + ret i32 %x +} + +define ptx_device i32 @test_clock() { +; CHECK: mov.u32 r0, %clock; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.clock() + ret i32 %x +} + +define ptx_device i64 @test_clock64() { +; CHECK: mov.u64 rd0, %clock64; +; CHECK-NEXT: ret; + %x = call i64 @llvm.ptx.read.clock64() + ret i64 %x +} + +define ptx_device i32 @test_pm0() { +; CHECK: mov.u32 r0, %pm0; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.pm0() + ret i32 %x +} + +define ptx_device i32 @test_pm1() { +; CHECK: mov.u32 r0, %pm1; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.pm1() + ret i32 %x +} + +define ptx_device i32 @test_pm2() { +; CHECK: mov.u32 r0, %pm2; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.pm2() + ret i32 %x +} + +define ptx_device i32 @test_pm3() { +; CHECK: mov.u32 r0, %pm3; +; CHECK-NEXT: ret; + %x = call i32 @llvm.ptx.read.pm3() + ret i32 %x +} + +define ptx_device void @test_bar_sync() { +; CHECK: bar.sync 0 +; CHECK-NEXT: ret; + call void @llvm.ptx.bar.sync(i32 0) + ret void +} + +declare i32 @llvm.ptx.read.tid.x() +declare i32 @llvm.ptx.read.tid.y() +declare i32 @llvm.ptx.read.tid.z() +declare i32 @llvm.ptx.read.tid.w() +declare i32 @llvm.ptx.read.ntid.x() +declare i32 @llvm.ptx.read.ntid.y() +declare i32 @llvm.ptx.read.ntid.z() +declare i32 @llvm.ptx.read.ntid.w() + +declare i32 @llvm.ptx.read.laneid() +declare i32 @llvm.ptx.read.warpid() +declare i32 @llvm.ptx.read.nwarpid() + +declare i32 @llvm.ptx.read.ctaid.x() +declare i32 @llvm.ptx.read.ctaid.y() +declare i32 @llvm.ptx.read.ctaid.z() +declare i32 @llvm.ptx.read.ctaid.w() +declare i32 @llvm.ptx.read.nctaid.x() +declare i32 @llvm.ptx.read.nctaid.y() +declare i32 @llvm.ptx.read.nctaid.z() +declare i32 @llvm.ptx.read.nctaid.w() + +declare i32 @llvm.ptx.read.smid() +declare i32 @llvm.ptx.read.nsmid() +declare i32 @llvm.ptx.read.gridid() + +declare i32 @llvm.ptx.read.lanemask.eq() +declare i32 @llvm.ptx.read.lanemask.le() +declare i32 @llvm.ptx.read.lanemask.lt() +declare i32 @llvm.ptx.read.lanemask.ge() +declare i32 @llvm.ptx.read.lanemask.gt() + +declare i32 @llvm.ptx.read.clock() +declare i64 @llvm.ptx.read.clock64() + +declare i32 @llvm.ptx.read.pm0() +declare i32 @llvm.ptx.read.pm1() +declare i32 @llvm.ptx.read.pm2() +declare i32 @llvm.ptx.read.pm3() + +declare void @llvm.ptx.bar.sync(i32 %i) diff --git a/test/CodeGen/PTX/ld.ll b/test/CodeGen/PTX/ld.ll index 836c4d41045a..377a95abe3db 100644 --- a/test/CodeGen/PTX/ld.ll +++ b/test/CodeGen/PTX/ld.ll @@ -1,78 +1,447 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s -;CHECK: .extern .global .s32 array[]; -@array = external global [10 x i32] +;CHECK: .extern .global .b8 array_i16[20]; +@array_i16 = external global [10 x i16] -;CHECK: .extern .const .s32 array_constant[]; -@array_constant = external addrspace(1) constant [10 x i32] +;CHECK: .extern .const .b8 array_constant_i16[20]; +@array_constant_i16 = external addrspace(1) constant [10 x i16] -;CHECK: .extern .local .s32 array_local[]; -@array_local = external addrspace(2) global [10 x i32] +;CHECK: .extern .local .b8 array_local_i16[20]; +@array_local_i16 = external addrspace(2) global [10 x i16] -;CHECK: .extern .shared .s32 array_shared[]; -@array_shared = external addrspace(4) global [10 x i32] +;CHECK: .extern .shared .b8 array_shared_i16[20]; +@array_shared_i16 = external addrspace(4) global [10 x i16] -define ptx_device i32 @t1(i32* %p) { +;CHECK: .extern .global .b8 array_i32[40]; +@array_i32 = external global [10 x i32] + +;CHECK: .extern .const .b8 array_constant_i32[40]; +@array_constant_i32 = external addrspace(1) constant [10 x i32] + +;CHECK: .extern .local .b8 array_local_i32[40]; +@array_local_i32 = external addrspace(2) global [10 x i32] + +;CHECK: .extern .shared .b8 array_shared_i32[40]; +@array_shared_i32 = external addrspace(4) global [10 x i32] + +;CHECK: .extern .global .b8 array_i64[80]; +@array_i64 = external global [10 x i64] + +;CHECK: .extern .const .b8 array_constant_i64[80]; +@array_constant_i64 = external addrspace(1) constant [10 x i64] + +;CHECK: .extern .local .b8 array_local_i64[80]; +@array_local_i64 = external addrspace(2) global [10 x i64] + +;CHECK: .extern .shared .b8 array_shared_i64[80]; +@array_shared_i64 = external addrspace(4) global [10 x i64] + +;CHECK: .extern .global .b8 array_float[40]; +@array_float = external global [10 x float] + +;CHECK: .extern .const .b8 array_constant_float[40]; +@array_constant_float = external addrspace(1) constant [10 x float] + +;CHECK: .extern .local .b8 array_local_float[40]; +@array_local_float = external addrspace(2) global [10 x float] + +;CHECK: .extern .shared .b8 array_shared_float[40]; +@array_shared_float = external addrspace(4) global [10 x float] + +;CHECK: .extern .global .b8 array_double[80]; +@array_double = external global [10 x double] + +;CHECK: .extern .const .b8 array_constant_double[80]; +@array_constant_double = external addrspace(1) constant [10 x double] + +;CHECK: .extern .local .b8 array_local_double[80]; +@array_local_double = external addrspace(2) global [10 x double] + +;CHECK: .extern .shared .b8 array_shared_double[80]; +@array_shared_double = external addrspace(4) global [10 x double] + + +define ptx_device i16 @t1_u16(i16* %p) { entry: -;CHECK: ld.global.s32 r0, [r1]; +;CHECK: ld.global.u16 rh0, [r1]; +;CHECK-NEXT: ret; + %x = load i16* %p + ret i16 %x +} + +define ptx_device i32 @t1_u32(i32* %p) { +entry: +;CHECK: ld.global.u32 r0, [r1]; +;CHECK-NEXT: ret; %x = load i32* %p ret i32 %x } -define ptx_device i32 @t2(i32* %p) { +define ptx_device i64 @t1_u64(i64* %p) { +entry: +;CHECK: ld.global.u64 rd0, [r1]; +;CHECK-NEXT: ret; + %x = load i64* %p + ret i64 %x +} + +define ptx_device float @t1_f32(float* %p) { +entry: +;CHECK: ld.global.f32 f0, [r1]; +;CHECK-NEXT: ret; + %x = load float* %p + ret float %x +} + +define ptx_device double @t1_f64(double* %p) { +entry: +;CHECK: ld.global.f64 fd0, [r1]; +;CHECK-NEXT: ret; + %x = load double* %p + ret double %x +} + +define ptx_device i16 @t2_u16(i16* %p) { entry: -;CHECK: ld.global.s32 r0, [r1+4]; +;CHECK: ld.global.u16 rh0, [r1+2]; +;CHECK-NEXT: ret; + %i = getelementptr i16* %p, i32 1 + %x = load i16* %i + ret i16 %x +} + +define ptx_device i32 @t2_u32(i32* %p) { +entry: +;CHECK: ld.global.u32 r0, [r1+4]; +;CHECK-NEXT: ret; %i = getelementptr i32* %p, i32 1 %x = load i32* %i ret i32 %x } -define ptx_device i32 @t3(i32* %p, i32 %q) { +define ptx_device i64 @t2_u64(i64* %p) { +entry: +;CHECK: ld.global.u64 rd0, [r1+8]; +;CHECK-NEXT: ret; + %i = getelementptr i64* %p, i32 1 + %x = load i64* %i + ret i64 %x +} + +define ptx_device float @t2_f32(float* %p) { +entry: +;CHECK: ld.global.f32 f0, [r1+4]; +;CHECK-NEXT: ret; + %i = getelementptr float* %p, i32 1 + %x = load float* %i + ret float %x +} + +define ptx_device double @t2_f64(double* %p) { +entry: +;CHECK: ld.global.f64 fd0, [r1+8]; +;CHECK-NEXT: ret; + %i = getelementptr double* %p, i32 1 + %x = load double* %i + ret double %x +} + +define ptx_device i16 @t3_u16(i16* %p, i32 %q) { +entry: +;CHECK: shl.b32 r0, r2, 1; +;CHECK-NEXT: add.u32 r0, r1, r0; +;CHECK-NEXT: ld.global.u16 rh0, [r0]; + %i = getelementptr i16* %p, i32 %q + %x = load i16* %i + ret i16 %x +} + +define ptx_device i32 @t3_u32(i32* %p, i32 %q) { entry: ;CHECK: shl.b32 r0, r2, 2; -;CHECK: add.s32 r0, r1, r0; -;CHECK: ld.global.s32 r0, [r0]; +;CHECK-NEXT: add.u32 r0, r1, r0; +;CHECK-NEXT: ld.global.u32 r0, [r0]; %i = getelementptr i32* %p, i32 %q %x = load i32* %i ret i32 %x } -define ptx_device i32 @t4_global() { +define ptx_device i64 @t3_u64(i64* %p, i32 %q) { +entry: +;CHECK: shl.b32 r0, r2, 3; +;CHECK-NEXT: add.u32 r0, r1, r0; +;CHECK-NEXT: ld.global.u64 rd0, [r0]; + %i = getelementptr i64* %p, i32 %q + %x = load i64* %i + ret i64 %x +} + +define ptx_device float @t3_f32(float* %p, i32 %q) { +entry: +;CHECK: shl.b32 r0, r2, 2; +;CHECK-NEXT: add.u32 r0, r1, r0; +;CHECK-NEXT: ld.global.f32 f0, [r0]; + %i = getelementptr float* %p, i32 %q + %x = load float* %i + ret float %x +} + +define ptx_device double @t3_f64(double* %p, i32 %q) { +entry: +;CHECK: shl.b32 r0, r2, 3; +;CHECK-NEXT: add.u32 r0, r1, r0; +;CHECK-NEXT: ld.global.f64 fd0, [r0]; + %i = getelementptr double* %p, i32 %q + %x = load double* %i + ret double %x +} + +define ptx_device i16 @t4_global_u16() { +entry: +;CHECK: mov.u32 r0, array_i16; +;CHECK-NEXT: ld.global.u16 rh0, [r0]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i16]* @array_i16, i32 0, i32 0 + %x = load i16* %i + ret i16 %x +} + +define ptx_device i32 @t4_global_u32() { entry: -;CHECK: ld.global.s32 r0, [array]; - %i = getelementptr [10 x i32]* @array, i32 0, i32 0 +;CHECK: mov.u32 r0, array_i32; +;CHECK-NEXT: ld.global.u32 r0, [r0]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i32]* @array_i32, i32 0, i32 0 %x = load i32* %i ret i32 %x } -define ptx_device i32 @t4_const() { +define ptx_device i64 @t4_global_u64() { entry: -;CHECK: ld.const.s32 r0, [array_constant]; - %i = getelementptr [10 x i32] addrspace(1)* @array_constant, i32 0, i32 0 +;CHECK: mov.u32 r0, array_i64; +;CHECK-NEXT: ld.global.u64 rd0, [r0]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i64]* @array_i64, i32 0, i32 0 + %x = load i64* %i + ret i64 %x +} + +define ptx_device float @t4_global_f32() { +entry: +;CHECK: mov.u32 r0, array_float; +;CHECK-NEXT: ld.global.f32 f0, [r0]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x float]* @array_float, i32 0, i32 0 + %x = load float* %i + ret float %x +} + +define ptx_device double @t4_global_f64() { +entry: +;CHECK: mov.u32 r0, array_double; +;CHECK-NEXT: ld.global.f64 fd0, [r0]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x double]* @array_double, i32 0, i32 0 + %x = load double* %i + ret double %x +} + +define ptx_device i16 @t4_const_u16() { +entry: +;CHECK: mov.u32 r0, array_constant_i16; +;CHECK-NEXT: ld.const.u16 rh0, [r0]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i16] addrspace(1)* @array_constant_i16, i32 0, i32 0 + %x = load i16 addrspace(1)* %i + ret i16 %x +} + +define ptx_device i32 @t4_const_u32() { +entry: +;CHECK: mov.u32 r0, array_constant_i32; +;CHECK-NEXT: ld.const.u32 r0, [r0]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i32] addrspace(1)* @array_constant_i32, i32 0, i32 0 %x = load i32 addrspace(1)* %i ret i32 %x } -define ptx_device i32 @t4_local() { +define ptx_device i64 @t4_const_u64() { +entry: +;CHECK: mov.u32 r0, array_constant_i64; +;CHECK-NEXT: ld.const.u64 rd0, [r0]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i64] addrspace(1)* @array_constant_i64, i32 0, i32 0 + %x = load i64 addrspace(1)* %i + ret i64 %x +} + +define ptx_device float @t4_const_f32() { entry: -;CHECK: ld.local.s32 r0, [array_local]; - %i = getelementptr [10 x i32] addrspace(2)* @array_local, i32 0, i32 0 +;CHECK: mov.u32 r0, array_constant_float; +;CHECK-NEXT: ld.const.f32 f0, [r0]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x float] addrspace(1)* @array_constant_float, i32 0, i32 0 + %x = load float addrspace(1)* %i + ret float %x +} + +define ptx_device double @t4_const_f64() { +entry: +;CHECK: mov.u32 r0, array_constant_double; +;CHECK-NEXT: ld.const.f64 fd0, [r0]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x double] addrspace(1)* @array_constant_double, i32 0, i32 0 + %x = load double addrspace(1)* %i + ret double %x +} + +define ptx_device i16 @t4_local_u16() { +entry: +;CHECK: mov.u32 r0, array_local_i16; +;CHECK-NEXT: ld.local.u16 rh0, [r0]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i16] addrspace(2)* @array_local_i16, i32 0, i32 0 + %x = load i16 addrspace(2)* %i + ret i16 %x +} + +define ptx_device i32 @t4_local_u32() { +entry: +;CHECK: mov.u32 r0, array_local_i32; +;CHECK-NEXT: ld.local.u32 r0, [r0]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i32] addrspace(2)* @array_local_i32, i32 0, i32 0 %x = load i32 addrspace(2)* %i ret i32 %x } -define ptx_device i32 @t4_shared() { +define ptx_device i64 @t4_local_u64() { entry: -;CHECK: ld.shared.s32 r0, [array_shared]; - %i = getelementptr [10 x i32] addrspace(4)* @array_shared, i32 0, i32 0 +;CHECK: mov.u32 r0, array_local_i64; +;CHECK-NEXT: ld.local.u64 rd0, [r0]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i64] addrspace(2)* @array_local_i64, i32 0, i32 0 + %x = load i64 addrspace(2)* %i + ret i64 %x +} + +define ptx_device float @t4_local_f32() { +entry: +;CHECK: mov.u32 r0, array_local_float; +;CHECK-NEXT: ld.local.f32 f0, [r0]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x float] addrspace(2)* @array_local_float, i32 0, i32 0 + %x = load float addrspace(2)* %i + ret float %x +} + +define ptx_device double @t4_local_f64() { +entry: +;CHECK: mov.u32 r0, array_local_double; +;CHECK-NEXT: ld.local.f64 fd0, [r0]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x double] addrspace(2)* @array_local_double, i32 0, i32 0 + %x = load double addrspace(2)* %i + ret double %x +} + +define ptx_device i16 @t4_shared_u16() { +entry: +;CHECK: mov.u32 r0, array_shared_i16; +;CHECK-NEXT: ld.shared.u16 rh0, [r0]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i16] addrspace(4)* @array_shared_i16, i32 0, i32 0 + %x = load i16 addrspace(4)* %i + ret i16 %x +} + +define ptx_device i32 @t4_shared_u32() { +entry: +;CHECK: mov.u32 r0, array_shared_i32; +;CHECK-NEXT: ld.shared.u32 r0, [r0]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i32] addrspace(4)* @array_shared_i32, i32 0, i32 0 %x = load i32 addrspace(4)* %i ret i32 %x } -define ptx_device i32 @t5() { +define ptx_device i64 @t4_shared_u64() { +entry: +;CHECK: mov.u32 r0, array_shared_i64; +;CHECK-NEXT: ld.shared.u64 rd0, [r0]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i64] addrspace(4)* @array_shared_i64, i32 0, i32 0 + %x = load i64 addrspace(4)* %i + ret i64 %x +} + +define ptx_device float @t4_shared_f32() { +entry: +;CHECK: mov.u32 r0, array_shared_float; +;CHECK-NEXT: ld.shared.f32 f0, [r0]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x float] addrspace(4)* @array_shared_float, i32 0, i32 0 + %x = load float addrspace(4)* %i + ret float %x +} + +define ptx_device double @t4_shared_f64() { +entry: +;CHECK: mov.u32 r0, array_shared_double; +;CHECK-NEXT: ld.shared.f64 fd0, [r0]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x double] addrspace(4)* @array_shared_double, i32 0, i32 0 + %x = load double addrspace(4)* %i + ret double %x +} + +define ptx_device i16 @t5_u16() { entry: -;CHECK: ld.global.s32 r0, [array+4]; - %i = getelementptr [10 x i32]* @array, i32 0, i32 1 +;CHECK: mov.u32 r0, array_i16; +;CHECK-NEXT: ld.global.u16 rh0, [r0+2]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i16]* @array_i16, i32 0, i32 1 + %x = load i16* %i + ret i16 %x +} + +define ptx_device i32 @t5_u32() { +entry: +;CHECK: mov.u32 r0, array_i32; +;CHECK-NEXT: ld.global.u32 r0, [r0+4]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i32]* @array_i32, i32 0, i32 1 %x = load i32* %i ret i32 %x } + +define ptx_device i64 @t5_u64() { +entry: +;CHECK: mov.u32 r0, array_i64; +;CHECK-NEXT: ld.global.u64 rd0, [r0+8]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i64]* @array_i64, i32 0, i32 1 + %x = load i64* %i + ret i64 %x +} + +define ptx_device float @t5_f32() { +entry: +;CHECK: mov.u32 r0, array_float; +;CHECK-NEXT: ld.global.f32 f0, [r0+4]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x float]* @array_float, i32 0, i32 1 + %x = load float* %i + ret float %x +} + +define ptx_device double @t5_f64() { +entry: +;CHECK: mov.u32 r0, array_double; +;CHECK-NEXT: ld.global.f64 fd0, [r0+8]; +;CHECK-NEXT: ret; + %i = getelementptr [10 x double]* @array_double, i32 0, i32 1 + %x = load double* %i + ret double %x +} diff --git a/test/CodeGen/PTX/llvm-intrinsic.ll b/test/CodeGen/PTX/llvm-intrinsic.ll new file mode 100644 index 000000000000..1e265f5b7b3a --- /dev/null +++ b/test/CodeGen/PTX/llvm-intrinsic.ll @@ -0,0 +1,56 @@ +; RUN: llc < %s -march=ptx32 -mattr=+ptx20,+sm20 | FileCheck %s + +define ptx_device float @test_sqrt_f32(float %x) { +entry: +; CHECK: sqrt.rn.f32 f0, f1; +; CHECK-NEXT: ret; + %y = call float @llvm.sqrt.f32(float %x) + ret float %y +} + +define ptx_device double @test_sqrt_f64(double %x) { +entry: +; CHECK: sqrt.rn.f64 fd0, fd1; +; CHECK-NEXT: ret; + %y = call double @llvm.sqrt.f64(double %x) + ret double %y +} + +define ptx_device float @test_sin_f32(float %x) { +entry: +; CHECK: sin.approx.f32 f0, f1; +; CHECK-NEXT: ret; + %y = call float @llvm.sin.f32(float %x) + ret float %y +} + +define ptx_device double @test_sin_f64(double %x) { +entry: +; CHECK: sin.approx.f64 fd0, fd1; +; CHECK-NEXT: ret; + %y = call double @llvm.sin.f64(double %x) + ret double %y +} + +define ptx_device float @test_cos_f32(float %x) { +entry: +; CHECK: cos.approx.f32 f0, f1; +; CHECK-NEXT: ret; + %y = call float @llvm.cos.f32(float %x) + ret float %y +} + +define ptx_device double @test_cos_f64(double %x) { +entry: +; CHECK: cos.approx.f64 fd0, fd1; +; CHECK-NEXT: ret; + %y = call double @llvm.cos.f64(double %x) + ret double %y +} + +declare float @llvm.sqrt.f32(float) +declare double @llvm.sqrt.f64(double) +declare float @llvm.sin.f32(float) +declare double @llvm.sin.f64(double) +declare float @llvm.cos.f32(float) +declare double @llvm.cos.f64(double) diff --git a/test/CodeGen/PTX/mad.ll b/test/CodeGen/PTX/mad.ll new file mode 100644 index 000000000000..0c25f2c0030a --- /dev/null +++ b/test/CodeGen/PTX/mad.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -march=ptx32 -mattr=+sm13 | FileCheck %s + +define ptx_device float @t1_f32(float %x, float %y, float %z) { +; CHECK: mad.rn.f32 f0, f1, f2, f3; +; CHECK-NEXT: ret; + %a = fmul float %x, %y + %b = fadd float %a, %z + ret float %b +} + +define ptx_device double @t1_f64(double %x, double %y, double %z) { +; CHECK: mad.rn.f64 fd0, fd1, fd2, fd3; +; CHECK-NEXT: ret; + %a = fmul double %x, %y + %b = fadd double %a, %z + ret double %b +} diff --git a/test/CodeGen/PTX/mov.ll b/test/CodeGen/PTX/mov.ll index c365e9beb897..120572a0e868 100644 --- a/test/CodeGen/PTX/mov.ll +++ b/test/CodeGen/PTX/mov.ll @@ -1,13 +1,62 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s -define ptx_device i32 @t1() { -; CHECK: mov.s32 r0, 0; +define ptx_device i16 @t1_u16() { +; CHECK: mov.u16 rh0, 0; +; CHECK: ret; + ret i16 0 +} + +define ptx_device i32 @t1_u32() { +; CHECK: mov.u32 r0, 0; ; CHECK: ret; ret i32 0 } -define ptx_device i32 @t2(i32 %x) { -; CHECK: mov.s32 r0, r1; +define ptx_device i64 @t1_u64() { +; CHECK: mov.u64 rd0, 0; +; CHECK: ret; + ret i64 0 +} + +define ptx_device float @t1_f32() { +; CHECK: mov.f32 f0, 0F00000000; +; CHECK: ret; + ret float 0.0 +} + +define ptx_device double @t1_f64() { +; CHECK: mov.f64 fd0, 0D0000000000000000; +; CHECK: ret; + ret double 0.0 +} + +define ptx_device i16 @t2_u16(i16 %x) { +; CHECK: mov.u16 rh0, rh1; +; CHECK: ret; + ret i16 %x +} + +define ptx_device i32 @t2_u32(i32 %x) { +; CHECK: mov.u32 r0, r1; ; CHECK: ret; ret i32 %x } + +define ptx_device i64 @t2_u64(i64 %x) { +; CHECK: mov.u64 rd0, rd1; +; CHECK: ret; + ret i64 %x +} + +define ptx_device float @t3_f32(float %x) { +; CHECK: mov.f32 f0, f1; +; CHECK-NEXT: ret; + ret float %x +} + +define ptx_device double @t3_f64(double %x) { +; CHECK: mov.f64 fd0, fd1; +; CHECK-NEXT: ret; + ret double %x +} + diff --git a/test/CodeGen/PTX/mul.ll b/test/CodeGen/PTX/mul.ll new file mode 100644 index 000000000000..5ce042675dc8 --- /dev/null +++ b/test/CodeGen/PTX/mul.ll @@ -0,0 +1,39 @@ +; RUN: llc < %s -march=ptx32 | FileCheck %s + +;define ptx_device i32 @t1(i32 %x, i32 %y) { +; %z = mul i32 %x, %y +; ret i32 %z +;} + +;define ptx_device i32 @t2(i32 %x) { +; %z = mul i32 %x, 1 +; ret i32 %z +;} + +define ptx_device float @t1_f32(float %x, float %y) { +; CHECK: mul.f32 f0, f1, f2 +; CHECK-NEXT: ret; + %z = fmul float %x, %y + ret float %z +} + +define ptx_device double @t1_f64(double %x, double %y) { +; CHECK: mul.f64 fd0, fd1, fd2 +; CHECK-NEXT: ret; + %z = fmul double %x, %y + ret double %z +} + +define ptx_device float @t2_f32(float %x) { +; CHECK: mul.f32 f0, f1, 0F40A00000; +; CHECK-NEXT: ret; + %z = fmul float %x, 5.0 + ret float %z +} + +define ptx_device double @t2_f64(double %x) { +; CHECK: mul.f64 fd0, fd1, 0D4014000000000000; +; CHECK-NEXT: ret; + %z = fmul double %x, 5.0 + ret double %z +} diff --git a/test/CodeGen/PTX/options.ll b/test/CodeGen/PTX/options.ll index a14d5c9c27ba..ac33fef0d6e3 100644 --- a/test/CodeGen/PTX/options.ll +++ b/test/CodeGen/PTX/options.ll @@ -1,5 +1,9 @@ -; RUN: llc < %s -march=ptx -ptx-version=2.0 | grep ".version 2.0" -; RUN: llc < %s -march=ptx -ptx-target=sm_20 | grep ".target sm_20" +; RUN: llc < %s -march=ptx32 -mattr=ptx20 | grep ".version 2.0" +; RUN: llc < %s -march=ptx32 -mattr=ptx21 | grep ".version 2.1" +; RUN: llc < %s -march=ptx32 -mattr=ptx22 | grep ".version 2.2" +; RUN: llc < %s -march=ptx32 -mattr=sm10 | grep ".target sm_10" +; RUN: llc < %s -march=ptx32 -mattr=sm13 | grep ".target sm_13" +; RUN: llc < %s -march=ptx32 -mattr=sm20 | grep ".target sm_20" define ptx_device void @t1() { ret void diff --git a/test/CodeGen/PTX/parameter-order.ll b/test/CodeGen/PTX/parameter-order.ll new file mode 100644 index 000000000000..95d4a328149c --- /dev/null +++ b/test/CodeGen/PTX/parameter-order.ll @@ -0,0 +1,8 @@ +; RUN: llc < %s -march=ptx32 | FileCheck %s + +; CHECK: .func (.reg .u32 r0) test_parameter_order (.reg .f32 f1, .reg .u32 r1, .reg .u32 r2, .reg .f32 f2) +define ptx_device i32 @test_parameter_order(float %a, i32 %b, i32 %c, float %d) { +; CHECK: sub.u32 r0, r1, r2 + %result = sub i32 %b, %c + ret i32 %result +} diff --git a/test/CodeGen/PTX/ret.ll b/test/CodeGen/PTX/ret.ll index d5037f25fd36..ba0523f6424a 100644 --- a/test/CodeGen/PTX/ret.ll +++ b/test/CodeGen/PTX/ret.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s define ptx_device void @t1() { ; CHECK: ret; diff --git a/test/CodeGen/PTX/setp.ll b/test/CodeGen/PTX/setp.ll new file mode 100644 index 000000000000..5836122049e6 --- /dev/null +++ b/test/CodeGen/PTX/setp.ll @@ -0,0 +1,134 @@ +; RUN: llc < %s -march=ptx32 | FileCheck %s + +define ptx_device i32 @test_setp_eq_u32_rr(i32 %x, i32 %y) { +; CHECK: setp.eq.u32 p0, r1, r2; +; CHECK-NEXT: cvt.u32.pred r0, p0; +; CHECK-NEXT: ret; + %p = icmp eq i32 %x, %y + %z = zext i1 %p to i32 + ret i32 %z +} + +define ptx_device i32 @test_setp_ne_u32_rr(i32 %x, i32 %y) { +; CHECK: setp.ne.u32 p0, r1, r2; +; CHECK-NEXT: cvt.u32.pred r0, p0; +; CHECK-NEXT: ret; + %p = icmp ne i32 %x, %y + %z = zext i1 %p to i32 + ret i32 %z +} + +define ptx_device i32 @test_setp_lt_u32_rr(i32 %x, i32 %y) { +; CHECK: setp.lt.u32 p0, r1, r2; +; CHECK-NEXT: cvt.u32.pred r0, p0; +; CHECK-NEXT: ret; + %p = icmp ult i32 %x, %y + %z = zext i1 %p to i32 + ret i32 %z +} + +define ptx_device i32 @test_setp_le_u32_rr(i32 %x, i32 %y) { +; CHECK: setp.le.u32 p0, r1, r2; +; CHECK-NEXT: cvt.u32.pred r0, p0; +; CHECK-NEXT: ret; + %p = icmp ule i32 %x, %y + %z = zext i1 %p to i32 + ret i32 %z +} + +define ptx_device i32 @test_setp_gt_u32_rr(i32 %x, i32 %y) { +; CHECK: setp.gt.u32 p0, r1, r2; +; CHECK-NEXT: cvt.u32.pred r0, p0; +; CHECK-NEXT: ret; + %p = icmp ugt i32 %x, %y + %z = zext i1 %p to i32 + ret i32 %z +} + +define ptx_device i32 @test_setp_ge_u32_rr(i32 %x, i32 %y) { +; CHECK: setp.ge.u32 p0, r1, r2; +; CHECK-NEXT: cvt.u32.pred r0, p0; +; CHECK-NEXT: ret; + %p = icmp uge i32 %x, %y + %z = zext i1 %p to i32 + ret i32 %z +} + +define ptx_device i32 @test_setp_eq_u32_ri(i32 %x) { +; CHECK: setp.eq.u32 p0, r1, 1; +; CHECK-NEXT: cvt.u32.pred r0, p0; +; CHECK-NEXT: ret; + %p = icmp eq i32 %x, 1 + %z = zext i1 %p to i32 + ret i32 %z +} + +define ptx_device i32 @test_setp_ne_u32_ri(i32 %x) { +; CHECK: setp.ne.u32 p0, r1, 1; +; CHECK-NEXT: cvt.u32.pred r0, p0; +; CHECK-NEXT: ret; + %p = icmp ne i32 %x, 1 + %z = zext i1 %p to i32 + ret i32 %z +} + +define ptx_device i32 @test_setp_lt_u32_ri(i32 %x) { +; CHECK: setp.eq.u32 p0, r1, 0; +; CHECK-NEXT: cvt.u32.pred r0, p0; +; CHECK-NEXT: ret; + %p = icmp ult i32 %x, 1 + %z = zext i1 %p to i32 + ret i32 %z +} + +define ptx_device i32 @test_setp_le_u32_ri(i32 %x) { +; CHECK: setp.lt.u32 p0, r1, 2; +; CHECK-NEXT: cvt.u32.pred r0, p0; +; CHECK-NEXT: ret; + %p = icmp ule i32 %x, 1 + %z = zext i1 %p to i32 + ret i32 %z +} + +define ptx_device i32 @test_setp_gt_u32_ri(i32 %x) { +; CHECK: setp.gt.u32 p0, r1, 1; +; CHECK-NEXT: cvt.u32.pred r0, p0; +; CHECK-NEXT: ret; + %p = icmp ugt i32 %x, 1 + %z = zext i1 %p to i32 + ret i32 %z +} + +define ptx_device i32 @test_setp_ge_u32_ri(i32 %x) { +; CHECK: setp.ne.u32 p0, r1, 0; +; CHECK-NEXT: cvt.u32.pred r0, p0; +; CHECK-NEXT: ret; + %p = icmp uge i32 %x, 1 + %z = zext i1 %p to i32 + ret i32 %z +} + +define ptx_device i32 @test_setp_4_op_format_1(i32 %x, i32 %y, i32 %u, i32 %v) { +; CHECK: setp.gt.u32 p0, r3, r4; +; CHECK-NEXT: setp.eq.and.u32 p0, r1, r2, p0; +; CHECK-NEXT: cvt.u32.pred r0, p0; +; CHECK-NEXT: ret; + %c = icmp eq i32 %x, %y + %d = icmp ugt i32 %u, %v + %e = and i1 %c, %d + %z = zext i1 %e to i32 + ret i32 %z +} + +define ptx_device i32 @test_setp_4_op_format_2(i32 %x, i32 %y, i32 %w) { +; CHECK: cvt.pred.u32 p0, r3; +; CHECK-NEXT: setp.eq.and.u32 p0, r1, r2, !p0; +; CHECK-NEXT: cvt.u32.pred r0, p0; +; CHECK-NEXT: ret; + %c = trunc i32 %w to i1 + %d = icmp eq i32 %x, %y + %e = xor i1 %c, 1 + %f = and i1 %d, %e + %z = zext i1 %f to i32 + ret i32 %z +} diff --git a/test/CodeGen/PTX/shl.ll b/test/CodeGen/PTX/shl.ll index b564b43ab932..6e72c9221325 100644 --- a/test/CodeGen/PTX/shl.ll +++ b/test/CodeGen/PTX/shl.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s define ptx_device i32 @t1(i32 %x, i32 %y) { ; CHECK: shl.b32 r0, r1, r2 diff --git a/test/CodeGen/PTX/shr.ll b/test/CodeGen/PTX/shr.ll index 3f8ade862b75..8693e0ecf49a 100644 --- a/test/CodeGen/PTX/shr.ll +++ b/test/CodeGen/PTX/shr.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s define ptx_device i32 @t1(i32 %x, i32 %y) { ; CHECK: shr.u32 r0, r1, r2 diff --git a/test/CodeGen/PTX/st.ll b/test/CodeGen/PTX/st.ll index 2cbacb9ee59c..dee5c61abe66 100644 --- a/test/CodeGen/PTX/st.ll +++ b/test/CodeGen/PTX/st.ll @@ -1,71 +1,402 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s -;CHECK: .extern .global .s32 array[]; -@array = external global [10 x i32] +;CHECK: .extern .global .b8 array_i16[20]; +@array_i16 = external global [10 x i16] -;CHECK: .extern .const .s32 array_constant[]; -@array_constant = external addrspace(1) constant [10 x i32] +;CHECK: .extern .const .b8 array_constant_i16[20]; +@array_constant_i16 = external addrspace(1) constant [10 x i16] -;CHECK: .extern .local .s32 array_local[]; -@array_local = external addrspace(2) global [10 x i32] +;CHECK: .extern .local .b8 array_local_i16[20]; +@array_local_i16 = external addrspace(2) global [10 x i16] -;CHECK: .extern .shared .s32 array_shared[]; -@array_shared = external addrspace(4) global [10 x i32] +;CHECK: .extern .shared .b8 array_shared_i16[20]; +@array_shared_i16 = external addrspace(4) global [10 x i16] -define ptx_device void @t1(i32* %p, i32 %x) { +;CHECK: .extern .global .b8 array_i32[40]; +@array_i32 = external global [10 x i32] + +;CHECK: .extern .const .b8 array_constant_i32[40]; +@array_constant_i32 = external addrspace(1) constant [10 x i32] + +;CHECK: .extern .local .b8 array_local_i32[40]; +@array_local_i32 = external addrspace(2) global [10 x i32] + +;CHECK: .extern .shared .b8 array_shared_i32[40]; +@array_shared_i32 = external addrspace(4) global [10 x i32] + +;CHECK: .extern .global .b8 array_i64[80]; +@array_i64 = external global [10 x i64] + +;CHECK: .extern .const .b8 array_constant_i64[80]; +@array_constant_i64 = external addrspace(1) constant [10 x i64] + +;CHECK: .extern .local .b8 array_local_i64[80]; +@array_local_i64 = external addrspace(2) global [10 x i64] + +;CHECK: .extern .shared .b8 array_shared_i64[80]; +@array_shared_i64 = external addrspace(4) global [10 x i64] + +;CHECK: .extern .global .b8 array_float[40]; +@array_float = external global [10 x float] + +;CHECK: .extern .const .b8 array_constant_float[40]; +@array_constant_float = external addrspace(1) constant [10 x float] + +;CHECK: .extern .local .b8 array_local_float[40]; +@array_local_float = external addrspace(2) global [10 x float] + +;CHECK: .extern .shared .b8 array_shared_float[40]; +@array_shared_float = external addrspace(4) global [10 x float] + +;CHECK: .extern .global .b8 array_double[80]; +@array_double = external global [10 x double] + +;CHECK: .extern .const .b8 array_constant_double[80]; +@array_constant_double = external addrspace(1) constant [10 x double] + +;CHECK: .extern .local .b8 array_local_double[80]; +@array_local_double = external addrspace(2) global [10 x double] + +;CHECK: .extern .shared .b8 array_shared_double[80]; +@array_shared_double = external addrspace(4) global [10 x double] + + +define ptx_device void @t1_u16(i16* %p, i16 %x) { entry: -;CHECK: st.global.s32 [r1], r2; +;CHECK: st.global.u16 [r1], rh1; +;CHECK-NEXT: ret; + store i16 %x, i16* %p + ret void +} + +define ptx_device void @t1_u32(i32* %p, i32 %x) { +entry: +;CHECK: st.global.u32 [r1], r2; +;CHECK-NEXT: ret; store i32 %x, i32* %p ret void } -define ptx_device void @t2(i32* %p, i32 %x) { +define ptx_device void @t1_u64(i64* %p, i64 %x) { +entry: +;CHECK: st.global.u64 [r1], rd1; +;CHECK-NEXT: ret; + store i64 %x, i64* %p + ret void +} + +define ptx_device void @t1_f32(float* %p, float %x) { +entry: +;CHECK: st.global.f32 [r1], f1; +;CHECK-NEXT: ret; + store float %x, float* %p + ret void +} + +define ptx_device void @t1_f64(double* %p, double %x) { +entry: +;CHECK: st.global.f64 [r1], fd1; +;CHECK-NEXT: ret; + store double %x, double* %p + ret void +} + +define ptx_device void @t2_u16(i16* %p, i16 %x) { entry: -;CHECK: st.global.s32 [r1+4], r2; +;CHECK: st.global.u16 [r1+2], rh1; +;CHECK-NEXT: ret; + %i = getelementptr i16* %p, i32 1 + store i16 %x, i16* %i + ret void +} + +define ptx_device void @t2_u32(i32* %p, i32 %x) { +entry: +;CHECK: st.global.u32 [r1+4], r2; +;CHECK-NEXT: ret; %i = getelementptr i32* %p, i32 1 store i32 %x, i32* %i ret void } -define ptx_device void @t3(i32* %p, i32 %q, i32 %x) { -;CHECK: .reg .s32 r0; +define ptx_device void @t2_u64(i64* %p, i64 %x) { +entry: +;CHECK: st.global.u64 [r1+8], rd1; +;CHECK-NEXT: ret; + %i = getelementptr i64* %p, i32 1 + store i64 %x, i64* %i + ret void +} + +define ptx_device void @t2_f32(float* %p, float %x) { +entry: +;CHECK: st.global.f32 [r1+4], f1; +;CHECK-NEXT: ret; + %i = getelementptr float* %p, i32 1 + store float %x, float* %i + ret void +} + +define ptx_device void @t2_f64(double* %p, double %x) { +entry: +;CHECK: st.global.f64 [r1+8], fd1; +;CHECK-NEXT: ret; + %i = getelementptr double* %p, i32 1 + store double %x, double* %i + ret void +} + +define ptx_device void @t3_u16(i16* %p, i32 %q, i16 %x) { +entry: +;CHECK: shl.b32 r0, r2, 1; +;CHECK-NEXT: add.u32 r0, r1, r0; +;CHECK-NEXT: st.global.u16 [r0], rh1; +;CHECK-NEXT: ret; + %i = getelementptr i16* %p, i32 %q + store i16 %x, i16* %i + ret void +} + +define ptx_device void @t3_u32(i32* %p, i32 %q, i32 %x) { entry: ;CHECK: shl.b32 r0, r2, 2; -;CHECK: add.s32 r0, r1, r0; -;CHECK: st.global.s32 [r0], r3; +;CHECK-NEXT: add.u32 r0, r1, r0; +;CHECK-NEXT: st.global.u32 [r0], r3; +;CHECK-NEXT: ret; %i = getelementptr i32* %p, i32 %q store i32 %x, i32* %i ret void } -define ptx_device void @t4_global(i32 %x) { +define ptx_device void @t3_u64(i64* %p, i32 %q, i64 %x) { +entry: +;CHECK: shl.b32 r0, r2, 3; +;CHECK-NEXT: add.u32 r0, r1, r0; +;CHECK-NEXT: st.global.u64 [r0], rd1; +;CHECK-NEXT: ret; + %i = getelementptr i64* %p, i32 %q + store i64 %x, i64* %i + ret void +} + +define ptx_device void @t3_f32(float* %p, i32 %q, float %x) { +entry: +;CHECK: shl.b32 r0, r2, 2; +;CHECK-NEXT: add.u32 r0, r1, r0; +;CHECK-NEXT: st.global.f32 [r0], f1; +;CHECK-NEXT: ret; + %i = getelementptr float* %p, i32 %q + store float %x, float* %i + ret void +} + +define ptx_device void @t3_f64(double* %p, i32 %q, double %x) { +entry: +;CHECK: shl.b32 r0, r2, 3; +;CHECK-NEXT: add.u32 r0, r1, r0; +;CHECK-NEXT: st.global.f64 [r0], fd1; +;CHECK-NEXT: ret; + %i = getelementptr double* %p, i32 %q + store double %x, double* %i + ret void +} + +define ptx_device void @t4_global_u16(i16 %x) { +entry: +;CHECK: mov.u32 r0, array_i16; +;CHECK-NEXT: st.global.u16 [r0], rh1; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i16]* @array_i16, i16 0, i16 0 + store i16 %x, i16* %i + ret void +} + +define ptx_device void @t4_global_u32(i32 %x) { entry: -;CHECK: st.global.s32 [array], r1; - %i = getelementptr [10 x i32]* @array, i32 0, i32 0 +;CHECK: mov.u32 r0, array_i32; +;CHECK-NEXT: st.global.u32 [r0], r1; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i32]* @array_i32, i32 0, i32 0 store i32 %x, i32* %i ret void } -define ptx_device void @t4_local(i32 %x) { +define ptx_device void @t4_global_u64(i64 %x) { +entry: +;CHECK: mov.u32 r0, array_i64; +;CHECK-NEXT: st.global.u64 [r0], rd1; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i64]* @array_i64, i32 0, i32 0 + store i64 %x, i64* %i + ret void +} + +define ptx_device void @t4_global_f32(float %x) { +entry: +;CHECK: mov.u32 r0, array_float; +;CHECK-NEXT: st.global.f32 [r0], f1; +;CHECK-NEXT: ret; + %i = getelementptr [10 x float]* @array_float, i32 0, i32 0 + store float %x, float* %i + ret void +} + +define ptx_device void @t4_global_f64(double %x) { +entry: +;CHECK: mov.u32 r0, array_double; +;CHECK-NEXT: st.global.f64 [r0], fd1; +;CHECK-NEXT: ret; + %i = getelementptr [10 x double]* @array_double, i32 0, i32 0 + store double %x, double* %i + ret void +} + +define ptx_device void @t4_local_u16(i16 %x) { entry: -;CHECK: st.local.s32 [array_local], r1; - %i = getelementptr [10 x i32] addrspace(2)* @array_local, i32 0, i32 0 +;CHECK: mov.u32 r0, array_local_i16; +;CHECK-NEXT: st.local.u16 [r0], rh1; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i16] addrspace(2)* @array_local_i16, i32 0, i32 0 + store i16 %x, i16 addrspace(2)* %i + ret void +} + +define ptx_device void @t4_local_u32(i32 %x) { +entry: +;CHECK: mov.u32 r0, array_local_i32; +;CHECK-NEXT: st.local.u32 [r0], r1; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i32] addrspace(2)* @array_local_i32, i32 0, i32 0 store i32 %x, i32 addrspace(2)* %i ret void } -define ptx_device void @t4_shared(i32 %x) { +define ptx_device void @t4_local_u64(i64 %x) { +entry: +;CHECK: mov.u32 r0, array_local_i64; +;CHECK-NEXT: st.local.u64 [r0], rd1; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i64] addrspace(2)* @array_local_i64, i32 0, i32 0 + store i64 %x, i64 addrspace(2)* %i + ret void +} + +define ptx_device void @t4_local_f32(float %x) { +entry: +;CHECK: mov.u32 r0, array_local_float; +;CHECK-NEXT: st.local.f32 [r0], f1; +;CHECK-NEXT: ret; + %i = getelementptr [10 x float] addrspace(2)* @array_local_float, i32 0, i32 0 + store float %x, float addrspace(2)* %i + ret void +} + +define ptx_device void @t4_local_f64(double %x) { +entry: +;CHECK: mov.u32 r0, array_local_double; +;CHECK-NEXT: st.local.f64 [r0], fd1; +;CHECK-NEXT: ret; + %i = getelementptr [10 x double] addrspace(2)* @array_local_double, i32 0, i32 0 + store double %x, double addrspace(2)* %i + ret void +} + +define ptx_device void @t4_shared_u16(i16 %x) { entry: -;CHECK: st.shared.s32 [array_shared], r1; - %i = getelementptr [10 x i32] addrspace(4)* @array_shared, i32 0, i32 0 +;CHECK: mov.u32 r0, array_shared_i16; +;CHECK-NEXT: st.shared.u16 [r0], rh1; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i16] addrspace(4)* @array_shared_i16, i32 0, i32 0 + store i16 %x, i16 addrspace(4)* %i + ret void +} + +define ptx_device void @t4_shared_u32(i32 %x) { +entry: +;CHECK: mov.u32 r0, array_shared_i32; +;CHECK-NEXT: st.shared.u32 [r0], r1; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i32] addrspace(4)* @array_shared_i32, i32 0, i32 0 store i32 %x, i32 addrspace(4)* %i ret void } -define ptx_device void @t5(i32 %x) { +define ptx_device void @t4_shared_u64(i64 %x) { +entry: +;CHECK: mov.u32 r0, array_shared_i64; +;CHECK-NEXT: st.shared.u64 [r0], rd1; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i64] addrspace(4)* @array_shared_i64, i32 0, i32 0 + store i64 %x, i64 addrspace(4)* %i + ret void +} + +define ptx_device void @t4_shared_f32(float %x) { +entry: +;CHECK: mov.u32 r0, array_shared_float; +;CHECK-NEXT: st.shared.f32 [r0], f1; +;CHECK-NEXT: ret; + %i = getelementptr [10 x float] addrspace(4)* @array_shared_float, i32 0, i32 0 + store float %x, float addrspace(4)* %i + ret void +} + +define ptx_device void @t4_shared_f64(double %x) { +entry: +;CHECK: mov.u32 r0, array_shared_double; +;CHECK-NEXT: st.shared.f64 [r0], fd1; +;CHECK-NEXT: ret; + %i = getelementptr [10 x double] addrspace(4)* @array_shared_double, i32 0, i32 0 + store double %x, double addrspace(4)* %i + ret void +} + +define ptx_device void @t5_u16(i16 %x) { entry: -;CHECK: st.global.s32 [array+4], r1; - %i = getelementptr [10 x i32]* @array, i32 0, i32 1 +;CHECK: mov.u32 r0, array_i16; +;CHECK-NEXT: st.global.u16 [r0+2], rh1; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i16]* @array_i16, i32 0, i32 1 + store i16 %x, i16* %i + ret void +} + +define ptx_device void @t5_u32(i32 %x) { +entry: +;CHECK: mov.u32 r0, array_i32; +;CHECK-NEXT: st.global.u32 [r0+4], r1; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i32]* @array_i32, i32 0, i32 1 store i32 %x, i32* %i ret void } + +define ptx_device void @t5_u64(i64 %x) { +entry: +;CHECK: mov.u32 r0, array_i64; +;CHECK-NEXT: st.global.u64 [r0+8], rd1; +;CHECK-NEXT: ret; + %i = getelementptr [10 x i64]* @array_i64, i32 0, i32 1 + store i64 %x, i64* %i + ret void +} + +define ptx_device void @t5_f32(float %x) { +entry: +;CHECK: mov.u32 r0, array_float; +;CHECK-NEXT: st.global.f32 [r0+4], f1; +;CHECK-NEXT: ret; + %i = getelementptr [10 x float]* @array_float, i32 0, i32 1 + store float %x, float* %i + ret void +} + +define ptx_device void @t5_f64(double %x) { +entry: +;CHECK: mov.u32 r0, array_double; +;CHECK-NEXT: st.global.f64 [r0+8], fd1; +;CHECK-NEXT: ret; + %i = getelementptr [10 x double]* @array_double, i32 0, i32 1 + store double %x, double* %i + ret void +} diff --git a/test/CodeGen/PTX/sub.ll b/test/CodeGen/PTX/sub.ll index aab3fdadad13..7dd2c6f6ac79 100644 --- a/test/CodeGen/PTX/sub.ll +++ b/test/CodeGen/PTX/sub.ll @@ -1,15 +1,71 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s -define ptx_device i32 @t1(i32 %x, i32 %y) { -;CHECK: sub.s32 r0, r1, r2; +define ptx_device i16 @t1_u16(i16 %x, i16 %y) { +; CHECK: sub.u16 rh0, rh1, rh2; +; CHECK-NEXT: ret; + %z = sub i16 %x, %y + ret i16 %z +} + +define ptx_device i32 @t1_u32(i32 %x, i32 %y) { +; CHECK: sub.u32 r0, r1, r2; +; CHECK-NEXT: ret; %z = sub i32 %x, %y -;CHECK: ret; ret i32 %z } -define ptx_device i32 @t2(i32 %x) { -;CHECK: add.s32 r0, r1, -1; +define ptx_device i64 @t1_u64(i64 %x, i64 %y) { +; CHECK: sub.u64 rd0, rd1, rd2; +; CHECK-NEXT: ret; + %z = sub i64 %x, %y + ret i64 %z +} + +define ptx_device float @t1_f32(float %x, float %y) { +; CHECK: sub.f32 f0, f1, f2 +; CHECK-NEXT: ret; + %z = fsub float %x, %y + ret float %z +} + +define ptx_device double @t1_f64(double %x, double %y) { +; CHECK: sub.f64 fd0, fd1, fd2 +; CHECK-NEXT: ret; + %z = fsub double %x, %y + ret double %z +} + +define ptx_device i16 @t2_u16(i16 %x) { +; CHECK: add.u16 rh0, rh1, -1; +; CHECK-NEXT: ret; + %z = sub i16 %x, 1 + ret i16 %z +} + +define ptx_device i32 @t2_u32(i32 %x) { +; CHECK: add.u32 r0, r1, -1; +; CHECK-NEXT: ret; %z = sub i32 %x, 1 -;CHECK: ret; ret i32 %z } + +define ptx_device i64 @t2_u64(i64 %x) { +; CHECK: add.u64 rd0, rd1, -1; +; CHECK-NEXT: ret; + %z = sub i64 %x, 1 + ret i64 %z +} + +define ptx_device float @t2_f32(float %x) { +; CHECK: add.f32 f0, f1, 0FBF800000; +; CHECK-NEXT: ret; + %z = fsub float %x, 1.0 + ret float %z +} + +define ptx_device double @t2_f64(double %x) { +; CHECK: add.f64 fd0, fd1, 0DBFF0000000000000; +; CHECK-NEXT: ret; + %z = fsub double %x, 1.0 + ret double %z +} diff --git a/test/CodeGen/PowerPC/2008-12-12-EH.ll b/test/CodeGen/PowerPC/2008-12-12-EH.ll index 2315e36ff465..a2a5e9e39641 100644 --- a/test/CodeGen/PowerPC/2008-12-12-EH.ll +++ b/test/CodeGen/PowerPC/2008-12-12-EH.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin9 | grep ^__Z1fv.eh +; RUN: llc < %s -disable-cfi -march=ppc32 -mtriple=powerpc-apple-darwin9 | grep ^__Z1fv.eh define void @_Z1fv() { entry: diff --git a/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll b/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll index b10920a6c10d..72ae9d6c73b3 100644 --- a/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll +++ b/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mcpu=g5 | FileCheck %s +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mcpu=g5 -regalloc=basic | FileCheck %s declare i8* @llvm.frameaddress(i32) nounwind readnone diff --git a/test/CodeGen/PowerPC/Atomics-64.ll b/test/CodeGen/PowerPC/Atomics-64.ll index 1dc4310761c3..cfc1eb98e064 100644 --- a/test/CodeGen/PowerPC/Atomics-64.ll +++ b/test/CodeGen/PowerPC/Atomics-64.ll @@ -1,5 +1,11 @@ -; RUN: llc < %s -march=ppc64 -; ModuleID = 'Atomics.c' +; RUN: llc < %s -march=ppc64 -verify-machineinstrs +; +; This test is disabled until PPCISelLowering learns to insert proper 64-bit +; code for ATOMIC_CMP_SWAP. Currently, it is inserting 32-bit instructions with +; 64-bit operands which causes the machine code verifier to throw a tantrum. +; +; XFAIL: * + target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc64-apple-darwin9" @sc = common global i8 0 ; <i8*> [#uses=52] diff --git a/test/CodeGen/PowerPC/Frames-small.ll b/test/CodeGen/PowerPC/Frames-small.ll index 404fdd01966c..ecd5ecd2eca1 100644 --- a/test/CodeGen/PowerPC/Frames-small.ll +++ b/test/CodeGen/PowerPC/Frames-small.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -o %t1 -; RUN not grep {stw r31, -4(r1)} %t1 +; RUN: not grep {stw r31, -4(r1)} %t1 ; RUN: grep {stwu r1, -16448(r1)} %t1 ; RUN: grep {addi r1, r1, 16448} %t1 ; RUN: llc < %s -march=ppc32 | \ diff --git a/test/CodeGen/PowerPC/indirectbr.ll b/test/CodeGen/PowerPC/indirectbr.ll index 5122ab39d232..ac5662534d0b 100644 --- a/test/CodeGen/PowerPC/indirectbr.ll +++ b/test/CodeGen/PowerPC/indirectbr.ll @@ -43,13 +43,13 @@ L2: ; preds = %L3, %bb2 L1: ; preds = %L2, %bb2 %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1] -; PIC: addis r4, r4, ha16(Ltmp0-L0$pb) -; PIC: li r6, lo16(Ltmp0-L0$pb) -; PIC: add r4, r4, r6 -; PIC: stw r4 -; STATIC: li r5, lo16(Ltmp0) -; STATIC: addis r5, r5, ha16(Ltmp0) -; STATIC: stw r5 +; PIC: addis r[[R0:[0-9]+]], r{{[0-9]+}}, ha16(Ltmp0-L0$pb) +; PIC: li r[[R1:[0-9]+]], lo16(Ltmp0-L0$pb) +; PIC: add r[[R2:[0-9]+]], r[[R0]], r[[R1]] +; PIC: stw r[[R2]] +; STATIC: li r[[R0:[0-9]+]], lo16(Ltmp0) +; STATIC: addis r[[R0]], r[[R0]], ha16(Ltmp0) +; STATIC: stw r[[R0]] store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4 ret i32 %res.3 } diff --git a/test/CodeGen/PowerPC/mulhs.ll b/test/CodeGen/PowerPC/mulhs.ll index 9ab8d997c0d0..5b02e187ae88 100644 --- a/test/CodeGen/PowerPC/mulhs.ll +++ b/test/CodeGen/PowerPC/mulhs.ll @@ -5,7 +5,7 @@ ; RUN: not grep add %t ; RUN: grep mulhw %t | count 1 -define i32 @mulhs(i32 %a, i32 %b) { +define i32 @mulhs(i32 %a, i32 %b) nounwind { entry: %tmp.1 = sext i32 %a to i64 ; <i64> [#uses=1] %tmp.3 = sext i32 %b to i64 ; <i64> [#uses=1] diff --git a/test/CodeGen/PowerPC/ppc-prologue.ll b/test/CodeGen/PowerPC/ppc-prologue.ll index 2ebfd3c319fc..553837121a36 100644 --- a/test/CodeGen/PowerPC/ppc-prologue.ll +++ b/test/CodeGen/PowerPC/ppc-prologue.ll @@ -5,9 +5,7 @@ define i32 @_Z4funci(i32 %a) ssp { ; CHECK-NEXT: stw r31, -4(r1) ; CHECK-NEXT: stw r0, 8(r1) ; CHECK-NEXT: stwu r1, -80(r1) -; CHECK-NEXT: Ltmp0: -; CHECK-NEXT: mr r31, r1 -; CHECK-NEXT: Ltmp1: +; CHECK: mr r31, r1 entry: %a_addr = alloca i32 ; <i32*> [#uses=2] %retval = alloca i32 ; <i32*> [#uses=2] diff --git a/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll b/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll index fbf724270566..9e6583ca2ce1 100644 --- a/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll +++ b/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll @@ -1,5 +1,7 @@ ;RUN: llc -march=sparc < %s | FileCheck %s -check-prefix=V8 ;RUN: llc -march=sparc -mattr=v9 < %s | FileCheck %s -check-prefix=V9 +;RUN: llc -march=sparc -regalloc=basic < %s | FileCheck %s -check-prefix=V8 +;RUN: llc -march=sparc -regalloc=basic -mattr=v9 < %s | FileCheck %s -check-prefix=V9 define i8* @frameaddr() nounwind readnone { entry: diff --git a/test/CodeGen/SystemZ/2009-07-10-BadIncomingArgOffset.ll b/test/CodeGen/SystemZ/2009-07-10-BadIncomingArgOffset.ll index 98feb83231dc..92f54675b72b 100644 --- a/test/CodeGen/SystemZ/2009-07-10-BadIncomingArgOffset.ll +++ b/test/CodeGen/SystemZ/2009-07-10-BadIncomingArgOffset.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s | FileCheck %s +; RUN: llc < %s -regalloc=basic | FileCheck %s target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16" target triple = "s390x-ibm-linux" @@ -8,7 +9,7 @@ declare void @rdft(i32 signext, i32 signext, double*, i32* nocapture, double*) n declare double @mp_mul_d2i_test(i32 signext, i32 signext, double* nocapture) nounwind define void @mp_mul_radix_test_bb3(i32 %radix, i32 %nfft, double* %tmpfft, i32* %ip, double* %w, double* %arrayidx44.reload, double* %call.out) nounwind { -; CHECK: lg %r11, 328(%r15) +; CHECK: lg %r{{[0-9]+}}, 328(%r15) newFuncRoot: br label %bb3 diff --git a/test/CodeGen/Thumb/2009-08-20-ISelBug.ll b/test/CodeGen/Thumb/2009-08-20-ISelBug.ll index 39612c00e4f6..d6ca0d793351 100644 --- a/test/CodeGen/Thumb/2009-08-20-ISelBug.ll +++ b/test/CodeGen/Thumb/2009-08-20-ISelBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv6-apple-darwin -relocation-model=pic -disable-fp-elim -mattr=+v6 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv6-apple-darwin -relocation-model=pic -disable-fp-elim -mattr=+v6 -verify-machineinstrs | FileCheck %s ; rdar://7157006 %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } diff --git a/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll b/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll deleted file mode 100644 index fad26693e768..000000000000 --- a/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll +++ /dev/null @@ -1,20 +0,0 @@ -; RUN: llc < %s -regalloc=fast -relocation-model=pic | FileCheck %s - -target triple = "thumbv6-apple-darwin10" - -@fred = internal global i32 0 ; <i32*> [#uses=1] - -define void @foo() nounwind { -entry: -; CHECK: str r0, [sp - %0 = call i32 (...)* @bar() nounwind ; <i32> [#uses=1] -; CHECK: blx _bar -; CHECK: ldr r1, [sp - store i32 %0, i32* @fred, align 4 - br label %return - -return: ; preds = %entry - ret void -} - -declare i32 @bar(...) diff --git a/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll b/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll index 06c0dfec5bab..9f5a677ed356 100644 --- a/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll +++ b/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll @@ -10,7 +10,7 @@ define void @_Z19getClosestDiagonal3ii(%0* noalias sret, i32, i32) nounwind { ; CHECK: blx ___muldf3 ; CHECK: blx ___muldf3 -; CHECK: beq LBB0_7 +; CHECK: beq LBB0 ; CHECK: blx ___muldf3 ; <label>:3 switch i32 %1, label %4 [ diff --git a/test/CodeGen/Thumb/dyn-stackalloc.ll b/test/CodeGen/Thumb/dyn-stackalloc.ll index 1f31dca0524d..cd35be69f5ca 100644 --- a/test/CodeGen/Thumb/dyn-stackalloc.ll +++ b/test/CodeGen/Thumb/dyn-stackalloc.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-cgp-branch-opts -disable-post-ra | FileCheck %s +; RUN: llc < %s -mtriple=thumb-apple-darwin -disable-cgp-branch-opts -disable-post-ra -regalloc=basic | FileCheck %s %struct.state = type { i32, %struct.info*, float**, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i64, i64, i64, i64, i64, i8* } %struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* } @@ -7,9 +8,10 @@ define void @t1(%struct.state* %v) { ; CHECK: t1: ; CHECK: push ; CHECK: add r7, sp, #12 -; CHECK: mov r2, sp -; CHECK: subs r4, r2, r1 -; CHECK: mov sp, r4 +; CHECK: lsls r[[R0:[0-9]+]] +; CHECK: mov r[[R1:[0-9]+]], sp +; CHECK: subs r[[R2:[0-9]+]], r[[R1]], r[[R0]] +; CHECK: mov sp, r[[R2]] %tmp6 = load i32* null %tmp8 = alloca float, i32 %tmp6 store i32 1, i32* null @@ -40,15 +42,16 @@ define void @t2(%struct.comment* %vc, i8* %tag, i8* %contents) { ; CHECK: t2: ; CHECK: push ; CHECK: add r7, sp, #12 -; CHECK: sub sp, #8 -; CHECK: mov r6, sp -; CHECK: str r2, [r6, #4] -; CHECK: str r0, [r6] +; CHECK: sub sp, # +; CHECK: mov r[[R0:[0-9]+]], sp +; CHECK: str r{{[0-9+]}}, [r[[R0]] +; CHECK: str r{{[0-9+]}}, [r[[R0]] ; CHECK-NOT: ldr r0, [sp -; CHECK: ldr r0, [r6, #4] -; CHECK: mov r0, sp -; CHECK: subs r5, r0, r1 -; CHECK: mov sp, r5 +; CHECK: mov r[[R1:[0-9]+]], sp +; CHECK: subs r[[R2:[0-9]+]], r[[R1]], r{{[0-9]+}} +; CHECK: mov sp, r[[R2]] +; CHECK-NOT: ldr r0, [sp +; CHECK: bx %tmp1 = call i32 @strlen( i8* %tag ) %tmp3 = call i32 @strlen( i8* %contents ) %tmp4 = add i32 %tmp1, 2 diff --git a/test/CodeGen/Thumb/rev.ll b/test/CodeGen/Thumb/rev.ll new file mode 100644 index 000000000000..5e163f8f96bc --- /dev/null +++ b/test/CodeGen/Thumb/rev.ll @@ -0,0 +1,56 @@ +; RUN: llc < %s -march=thumb -mattr=+v6 | FileCheck %s + +define i32 @test1(i32 %X) nounwind { +; CHECK: test1 +; CHECK: rev16 r0, r0 + %tmp1 = lshr i32 %X, 8 + %X15 = bitcast i32 %X to i32 + %tmp4 = shl i32 %X15, 8 + %tmp2 = and i32 %tmp1, 16711680 + %tmp5 = and i32 %tmp4, -16777216 + %tmp9 = and i32 %tmp1, 255 + %tmp13 = and i32 %tmp4, 65280 + %tmp6 = or i32 %tmp5, %tmp2 + %tmp10 = or i32 %tmp6, %tmp13 + %tmp14 = or i32 %tmp10, %tmp9 + ret i32 %tmp14 +} + +define i32 @test2(i32 %X) nounwind { +; CHECK: test2 +; CHECK: revsh r0, r0 + %tmp1 = lshr i32 %X, 8 + %tmp1.upgrd.1 = trunc i32 %tmp1 to i16 + %tmp3 = trunc i32 %X to i16 + %tmp2 = and i16 %tmp1.upgrd.1, 255 + %tmp4 = shl i16 %tmp3, 8 + %tmp5 = or i16 %tmp2, %tmp4 + %tmp5.upgrd.2 = sext i16 %tmp5 to i32 + ret i32 %tmp5.upgrd.2 +} + +; rdar://9147637 +define i32 @test3(i16 zeroext %a) nounwind { +entry: +; CHECK: test3: +; CHECK: revsh r0, r0 + %0 = tail call i16 @llvm.bswap.i16(i16 %a) + %1 = sext i16 %0 to i32 + ret i32 %1 +} + +declare i16 @llvm.bswap.i16(i16) nounwind readnone + +define i32 @test4(i16 zeroext %a) nounwind { +entry: +; CHECK: test4: +; CHECK: revsh r0, r0 + %conv = zext i16 %a to i32 + %shr9 = lshr i16 %a, 8 + %conv2 = zext i16 %shr9 to i32 + %shl = shl nuw nsw i32 %conv, 8 + %or = or i32 %conv2, %shl + %sext = shl i32 %or, 16 + %conv8 = ashr exact i32 %sext, 16 + ret i32 %conv8 +} diff --git a/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll b/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll index 550b3efae998..ff68e665078a 100644 --- a/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll +++ b/test/CodeGen/Thumb2/2009-08-06-SpDecBug.ll @@ -8,7 +8,7 @@ entry: ; CHECK: sub sp, #8 ; CHECK: push ; CHECK: add r7, sp, #4 -; CHECK: subs r4, r7, #4 +; CHECK: sub.w r4, r7, #4 ; CHECK: mov sp, r4 ; CHECK-NOT: mov sp, r7 ; CHECK: add sp, #8 diff --git a/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll b/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll index b2ed8fc7a67c..ac3e80a7c113 100644 --- a/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll +++ b/test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-cgp-branch-opts | FileCheck %s %struct.pix_pos = type { i32, i32, i32, i32, i32, i32 } diff --git a/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll b/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll index 45d356c3dc67..3594424e290b 100644 --- a/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll +++ b/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=thumbv7-eabi -mcpu=cortex-a8 -float-abi=hard | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-eabi -mcpu=cortex-a8 -float-abi=hard -regalloc=basic | FileCheck %s ; PR5204 %"struct.__gnu_cxx::__normal_iterator<char*,std::basic_string<char, std::char_traits<char>, std::allocator<char> > >" = type { i8* } @@ -11,8 +12,8 @@ define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this, %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) { ; CHECK: _ZNKSs7compareERKSs: ; CHECK: it eq -; CHECK-NEXT: subeq r0, r6, r7 -; CHECK-NEXT: ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +; CHECK-NEXT: subeq r0, r{{[0-9]+}}, r{{[0-9]+}} +; CHECK-NEXT: ldmia.w sp!, entry: %0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i32> [#uses=3] %1 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) ; <i32> [#uses=3] diff --git a/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll b/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll index 458569ec93b5..bb734aca4e68 100644 --- a/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll +++ b/test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll @@ -1,10 +1,11 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 \ -; RUN: -pre-RA-sched=source | FileCheck -check-prefix=SOURCE %s +; RUN: -pre-RA-sched=source | FileCheck %s ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 \ -; RUN: -pre-RA-sched=list-hybrid | FileCheck -check-prefix=HYBRID %s +; RUN: -pre-RA-sched=list-hybrid | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -regalloc=basic | FileCheck %s ; Radar 7459078 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" - + %0 = type { i32, i32 } %s1 = type { %s3, i32, %s4, i8*, void (i8*, i8*)*, i8*, i32*, i32*, i32*, i32, i64, [1 x i32] } %s2 = type { i32 (...)**, %s4 } @@ -13,11 +14,10 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32- %s5 = type { i32 } ; Make sure the cmp is not scheduled before the InlineAsm that clobbers cc. -; SOURCE: InlineAsm End -; SOURCE: cmp -; SOURCE: beq -; HYBRID: InlineAsm End -; HYBRID: cbz +; CHECK: blx _f2 +; CHECK: cmp r0, #0 +; CHECK-NOT: cmp +; CHECK: InlineAsm Start define void @test(%s1* %this, i32 %format, i32 %w, i32 %h, i32 %levels, i32* %s, i8* %data, i32* nocapture %rowbytes, void (i8*, i8*)* %release, i8* %info) nounwind { entry: %tmp1 = getelementptr inbounds %s1* %this, i32 0, i32 0, i32 0, i32 1, i32 0, i32 0 diff --git a/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll b/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll index 313728c1b56a..d2140a10048d 100644 --- a/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll +++ b/test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll @@ -8,7 +8,7 @@ declare void @bar() nounwind optsize define void @foo() nounwind optsize { ; CHECK: foo: ; CHECK: push -; CHECK: add r7, sp, #4 +; CHECK: mov r7, sp ; CHECK: sub sp, #4 entry: %m.i = alloca %struct.buf*, align 4 diff --git a/test/CodeGen/Thumb2/2011-04-21-FILoweringBug.ll b/test/CodeGen/Thumb2/2011-04-21-FILoweringBug.ll new file mode 100644 index 000000000000..604a352baa11 --- /dev/null +++ b/test/CodeGen/Thumb2/2011-04-21-FILoweringBug.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s + +; Use sp, #imm to lower frame indices when the offset is multiple of 4 +; and in the range of 0-1020. This saves code size by utilizing +; 16-bit instructions. +; rdar://9321541 + +define i32 @t() nounwind { +entry: +; CHECK: t: +; CHECK: sub sp, #12 +; CHECK-NOT: sub +; CHECK: add r0, sp, #4 +; CHECK: add r1, sp, #8 +; CHECK: mov r2, sp + %size = alloca i32, align 4 + %count = alloca i32, align 4 + %index = alloca i32, align 4 + %0 = call i32 @foo(i32* %count, i32* %size, i32* %index) nounwind + ret i32 %0 +} + +declare i32 @foo(i32*, i32*, i32*) diff --git a/test/CodeGen/Thumb2/bfi.ll b/test/CodeGen/Thumb2/bfi.ll index 6fb2fc888d9f..0e767707b6cf 100644 --- a/test/CodeGen/Thumb2/bfi.ll +++ b/test/CodeGen/Thumb2/bfi.ll @@ -49,3 +49,14 @@ define i32 @f4(i32 %a) nounwind { %ins12 = or i32 %ins7, 3137 ret i32 %ins12 } + +; rdar://9177502 +define i32 @f5(i32 %a, i32 %b) nounwind readnone { +entry: +; CHECK: f5 +; CHECK-NOT: bfi r0, r2, #0, #1 +%and = and i32 %a, 2 +%b.masked = and i32 %b, -2 +%and3 = or i32 %b.masked, %and +ret i32 %and3 +} diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll index b8c8cb122a19..edbf83405be7 100644 --- a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll +++ b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll @@ -6,8 +6,6 @@ entry: br label %bb5 bb5: ; preds = %bb5, %entry -; CHECK: %bb5 -; CHECK: bne br i1 undef, label %bb5, label %bb.nph bb.nph: ; preds = %bb5 diff --git a/test/CodeGen/Thumb2/ldr-str-imm12.ll b/test/CodeGen/Thumb2/ldr-str-imm12.ll index 650d788cb4d2..e1932bd2748a 100644 --- a/test/CodeGen/Thumb2/ldr-str-imm12.ll +++ b/test/CodeGen/Thumb2/ldr-str-imm12.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim -regalloc=linearscan | FileCheck %s ; rdar://7352504 ; Make sure we use "str r9, [sp, #+28]" instead of "sub.w r4, r7, #256" followed by "str r9, [r4, #-32]". @@ -22,7 +22,7 @@ define %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind { entry: -; CHECK: ldr.w {{(r[0-9])|(lr)}}, [r7, #28] +; CHECK: ldr.w {{(r[0-9]+)|(lr)}}, [r7, #28] %xgaps.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] %ycomp.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] br label %bb20 diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll index 5e776dd8937c..ee054a165a01 100644 --- a/test/CodeGen/Thumb2/machine-licm.ll +++ b/test/CodeGen/Thumb2/machine-licm.ll @@ -14,19 +14,19 @@ entry: bb.nph: ; preds = %entry ; CHECK: BB#1 -; CHECK: movw r2, :lower16:L_GV$non_lazy_ptr -; CHECK: movt r2, :upper16:L_GV$non_lazy_ptr -; CHECK: ldr r2, [r2] -; CHECK: ldr r3, [r2] +; CHECK: movw r[[R2:[0-9]+]], :lower16:L_GV$non_lazy_ptr +; CHECK: movt r[[R2]], :upper16:L_GV$non_lazy_ptr +; CHECK: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]] +; CHECK: ldr{{.*}}, [r[[R2b]] ; CHECK: LBB0_2 ; CHECK-NOT: LCPI0_0: ; PIC: BB#1 -; PIC: movw r2, :lower16:(L_GV$non_lazy_ptr-(LPC0_0+4)) -; PIC: movt r2, :upper16:(L_GV$non_lazy_ptr-(LPC0_0+4)) -; PIC: add r2, pc -; PIC: ldr r2, [r2] -; PIC: ldr r3, [r2] +; PIC: movw r[[R2:[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+4)) +; PIC: movt r[[R2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+4)) +; PIC: add r[[R2]], pc +; PIC: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]] +; PIC: ldr{{.*}}, [r[[R2b]] ; PIC: LBB0_2 ; PIC-NOT: LCPI0_0: ; PIC: .section @@ -88,10 +88,10 @@ define zeroext i16 @t3(i8 zeroext %data, i16 zeroext %crc) nounwind readnone { bb.nph: ; CHECK: bb.nph ; CHECK: movw {{(r[0-9])|(lr)}}, #32768 -; CHECK: movs {{(r[0-9])|(lr)}}, #8 -; CHECK: movw [[REGISTER:(r[0-9])|(lr)]], #16386 -; CHECK: movw {{(r[0-9])|(lr)}}, #65534 -; CHECK: movt {{(r[0-9])|(lr)}}, #65535 +; CHECK: movs {{(r[0-9]+)|(lr)}}, #0 +; CHECK: movw [[REGISTER:(r[0-9]+)|(lr)]], #16386 +; CHECK: movw {{(r[0-9]+)|(lr)}}, #65534 +; CHECK: movt {{(r[0-9]+)|(lr)}}, #65535 br label %bb bb: ; preds = %bb, %bb.nph diff --git a/test/CodeGen/Thumb2/thumb2-ldrd.ll b/test/CodeGen/Thumb2/thumb2-ldrd.ll index a747d5f75697..d3b781dbc0d4 100644 --- a/test/CodeGen/Thumb2/thumb2-ldrd.ll +++ b/test/CodeGen/Thumb2/thumb2-ldrd.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 -regalloc=linearscan | FileCheck %s @b = external global i64* diff --git a/test/CodeGen/Thumb2/thumb2-lsr3.ll b/test/CodeGen/Thumb2/thumb2-lsr3.ll index 5cfd3f5198b7..e7ba782afe6a 100644 --- a/test/CodeGen/Thumb2/thumb2-lsr3.ll +++ b/test/CodeGen/Thumb2/thumb2-lsr3.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i1 @test1(i64 %poscnt, i32 %work) { entry: -; CHECK: rrx r0, r0 ; CHECK: lsrs.w r1, r1, #1 +; CHECK: rrx r0, r0 %0 = lshr i64 %poscnt, 1 %1 = icmp eq i64 %0, 0 ret i1 %1 @@ -11,8 +11,8 @@ entry: define i1 @test2(i64 %poscnt, i32 %work) { entry: -; CHECK: rrx r0, r0 ; CHECK: asrs.w r1, r1, #1 +; CHECK: rrx r0, r0 %0 = ashr i64 %poscnt, 1 %1 = icmp eq i64 %0, 0 ret i1 %1 diff --git a/test/CodeGen/Thumb2/thumb2-ror.ll b/test/CodeGen/Thumb2/thumb2-ror.ll index 0200116fc31a..590c333b3d1a 100644 --- a/test/CodeGen/Thumb2/thumb2-ror.ll +++ b/test/CodeGen/Thumb2/thumb2-ror.ll @@ -1,11 +1,24 @@ ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; CHECK: f1: +; CHECK: ror.w r0, r0, #22 define i32 @f1(i32 %a) { %l8 = shl i32 %a, 10 %r8 = lshr i32 %a, 22 %tmp = or i32 %l8, %r8 ret i32 %tmp } -; CHECK: f1: -; CHECK: ror.w r0, r0, #22 + +; CHECK: f2: +; CHECK-NOT: and +; CHECK: ror +define i32 @f2(i32 %v, i32 %nbits) { +entry: + %and = and i32 %nbits, 31 + %shr = lshr i32 %v, %and + %sub = sub i32 32, %and + %shl = shl i32 %v, %sub + %or = or i32 %shl, %shr + ret i32 %or +}
\ No newline at end of file diff --git a/test/CodeGen/Thumb2/thumb2-ror2.ll b/test/CodeGen/Thumb2/thumb2-ror2.ll deleted file mode 100644 index ffd1dd7dc613..000000000000 --- a/test/CodeGen/Thumb2/thumb2-ror2.ll +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s - -define i32 @f1(i32 %a, i32 %b) { -; CHECK: f1: -; CHECK: rors r0, r1 - %db = sub i32 32, %b - %l8 = shl i32 %a, %b - %r8 = lshr i32 %a, %db - %tmp = or i32 %l8, %r8 - ret i32 %tmp -} diff --git a/test/CodeGen/Thumb2/thumb2-sbc.ll b/test/CodeGen/Thumb2/thumb2-sbc.ll index de6502d2e63e..53f45ea951f5 100644 --- a/test/CodeGen/Thumb2/thumb2-sbc.ll +++ b/test/CodeGen/Thumb2/thumb2-sbc.ll @@ -39,7 +39,7 @@ define i64 @f5(i64 %a) { ; CHECK: f5 ; CHECK: subs r0, #2 ; CHECK: adc r1, r1, #-1448498775 - %tmp = sub i64 %a, 6221254862626095106 + %tmp = sub i64 %a, 6221254862626095106 ret i64 %tmp } @@ -48,7 +48,22 @@ define i64 @f6(i64 %a) { ; CHECK: f6 ; CHECK: subs r0, #2 ; CHECK: sbc r1, r1, #66846720 - %tmp = sub i64 %a, 287104476244869122 + %tmp = sub i64 %a, 287104476244869122 ret i64 %tmp } +; Example from numerics code that manually computes wider-than-64 values. +; +; CHECK: livecarry: +; CHECK: adds +; CHECK: adcs +; CHECK: adc +define i64 @livecarry(i64 %carry, i32 %digit) nounwind { + %ch = lshr i64 %carry, 32 + %cl = and i64 %carry, 4294967295 + %truncdigit = zext i32 %digit to i64 + %prod = add i64 %cl, %truncdigit + %ph = lshr i64 %prod, 32 + %carryresult = add i64 %ch, %ph + ret i64 %carryresult +} diff --git a/test/CodeGen/Thumb2/thumb2-sub3.ll b/test/CodeGen/Thumb2/thumb2-sub3.ll index 855ad06a63f1..1dbda57f2369 100644 --- a/test/CodeGen/Thumb2/thumb2-sub3.ll +++ b/test/CodeGen/Thumb2/thumb2-sub3.ll @@ -4,7 +4,7 @@ define i64 @f1(i64 %a) { ; CHECK: f1 ; CHECK: subs r0, #171 -; CHECK: adc r1, r1, #-1 +; CHECK: sbc r1, r1, #0 %tmp = sub i64 %a, 171 ret i64 %tmp } @@ -13,7 +13,7 @@ define i64 @f1(i64 %a) { define i64 @f2(i64 %a) { ; CHECK: f2 ; CHECK: subs.w r0, r0, #1179666 -; CHECK: adc r1, r1, #-1 +; CHECK: sbc r1, r1, #0 %tmp = sub i64 %a, 1179666 ret i64 %tmp } @@ -22,7 +22,7 @@ define i64 @f2(i64 %a) { define i64 @f3(i64 %a) { ; CHECK: f3 ; CHECK: subs.w r0, r0, #872428544 -; CHECK: adc r1, r1, #-1 +; CHECK: sbc r1, r1, #0 %tmp = sub i64 %a, 872428544 ret i64 %tmp } @@ -31,7 +31,7 @@ define i64 @f3(i64 %a) { define i64 @f4(i64 %a) { ; CHECK: f4 ; CHECK: subs.w r0, r0, #1448498774 -; CHECK: adc r1, r1, #-1 +; CHECK: sbc r1, r1, #0 %tmp = sub i64 %a, 1448498774 ret i64 %tmp } @@ -40,7 +40,7 @@ define i64 @f4(i64 %a) { define i64 @f5(i64 %a) { ; CHECK: f5 ; CHECK: subs.w r0, r0, #66846720 -; CHECK: adc r1, r1, #-1 +; CHECK: sbc r1, r1, #0 %tmp = sub i64 %a, 66846720 ret i64 %tmp } diff --git a/test/CodeGen/Thumb2/thumb2-sub5.ll b/test/CodeGen/Thumb2/thumb2-sub5.ll index c3b56bc09c85..6edd789beec5 100644 --- a/test/CodeGen/Thumb2/thumb2-sub5.ll +++ b/test/CodeGen/Thumb2/thumb2-sub5.ll @@ -1,9 +1,10 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2 -mattr=+32bit | FileCheck %s define i64 @f1(i64 %a, i64 %b) { ; CHECK: f1: -; CHECK: subs r0, r0, r2 -; CHECK: sbcs r1, r3 +; CHECK: subs.w r0, r0, r2 +; To test dead_carry, +32bit prevents sbc conveting to 16-bit sbcs +; CHECK: sbc.w r1, r1, r3 %tmp = sub i64 %a, %b ret i64 %tmp } diff --git a/test/CodeGen/Thumb2/thumb2-uxtb.ll b/test/CodeGen/Thumb2/thumb2-uxtb.ll index 2074f98cb608..35914b16790a 100644 --- a/test/CodeGen/Thumb2/thumb2-uxtb.ll +++ b/test/CodeGen/Thumb2/thumb2-uxtb.ll @@ -128,9 +128,9 @@ define i32 @test10(i32 %p0) { ; ARMv7M: test10 ; ARMv7M: mov.w r1, #16253176 +; ARMv7M: mov.w r2, #458759 ; ARMv7M: and.w r0, r1, r0, lsr #7 -; ARMv7M: mov.w r1, #458759 -; ARMv7M: and.w r1, r1, r0, lsr #5 +; ARMv7M: and.w r1, r2, r0, lsr #5 ; ARMv7M: orrs r0, r1 %tmp1 = lshr i32 %p0, 7 ; <i32> [#uses=1] %tmp2 = and i32 %tmp1, 16253176 ; <i32> [#uses=2] diff --git a/test/CodeGen/X86/2007-01-08-X86-64-Pointer.ll b/test/CodeGen/X86/2007-01-08-X86-64-Pointer.ll index de226a140ad1..3458550aa103 100644 --- a/test/CodeGen/X86/2007-01-08-X86-64-Pointer.ll +++ b/test/CodeGen/X86/2007-01-08-X86-64-Pointer.ll @@ -1,5 +1,8 @@ -; RUN: llc %s -o - -march=x86-64 | grep {(%rdi,%rax,8)} -; RUN: llc %s -o - -march=x86-64 | not grep {addq.*8} +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s +; CHECK-NOT: {{addq.*8}} +; CHECK: ({{%rdi|%rcx}},%rax,8) +; CHECK-NOT: {{addq.*8}} define void @foo(double* %y) nounwind { entry: diff --git a/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll b/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll index a662dd58df57..11c0bf957983 100644 --- a/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll +++ b/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll @@ -8,8 +8,8 @@ entry: bb26: ; preds = %bb26, %entry -; CHECK: addl %e -; CHECK: adcl %e +; CHECK: addl +; CHECK: adcl %i.037.0 = phi i32 [ 0, %entry ], [ %tmp25, %bb26 ] ; <i32> [#uses=3] %sum.035.0 = phi <1 x i64> [ zeroinitializer, %entry ], [ %tmp22, %bb26 ] ; <<1 x i64>> [#uses=1] diff --git a/test/CodeGen/X86/2007-05-05-Personality.ll b/test/CodeGen/X86/2007-05-05-Personality.ll index a9b17d3b8f36..0f49d2e10cb9 100644 --- a/test/CodeGen/X86/2007-05-05-Personality.ll +++ b/test/CodeGen/X86/2007-05-05-Personality.ll @@ -1,4 +1,7 @@ -; RUN: llc < %s -mtriple=i686-pc-linux-gnu -o - | grep zPL +; RUN: llc < %s -mtriple=i686-pc-linux-gnu -o - | FileCheck %s + +; CHECK: .cfi_personality 0, __gnat_eh_personality +; CHECK: .cfi_lsda 0, .Lexception0 @error = external global i8 ; <i8*> [#uses=2] diff --git a/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll b/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll index 1c5e6766fd6e..187c3e4221b5 100644 --- a/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll +++ b/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll @@ -1,6 +1,8 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx | grep {movd %rsi, %mm0} -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx | grep {movd %rdi, %mm1} -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx | grep {paddusw %mm0, %mm1} +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx | FileCheck %s + +; CHECK: movd %rsi, [[MM0:%mm[0-9]+]] +; CHECK: movd %rdi, [[MM1:%mm[0-9]+]] +; CHECK: paddusw [[MM0]], [[MM1]] @R = external global x86_mmx ; <x86_mmx*> [#uses=1] diff --git a/test/CodeGen/X86/2007-07-18-Vector-Extract.ll b/test/CodeGen/X86/2007-07-18-Vector-Extract.ll index 8625b2771738..6288c4a892c3 100644 --- a/test/CodeGen/X86/2007-07-18-Vector-Extract.ll +++ b/test/CodeGen/X86/2007-07-18-Vector-Extract.ll @@ -1,5 +1,7 @@ -; RUN: llc < %s -march=x86-64 -mattr=+sse | grep {movq (%rdi), %rax} -; RUN: llc < %s -march=x86-64 -mattr=+sse | grep {movq 8(%rdi), %rax} +; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse | FileCheck %s +; CHECK: movq ([[A0:%rdi|%rcx]]), %rax +; CHECK: movq 8([[A0]]), %rax define i64 @foo_0(<2 x i64>* %val) { entry: %val12 = getelementptr <2 x i64>* %val, i32 0, i32 0 ; <i64*> [#uses=1] diff --git a/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll b/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll index c3403a0b4eeb..1e43272a84e8 100644 --- a/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll +++ b/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin | grep {isNullOrNil].eh"} | count 2 +; RUN: llc < %s -disable-cfi -march=x86 -mtriple=i686-apple-darwin | grep {isNullOrNil].eh"} | FileCheck %s + +; CHECK: "_-[NSString(local) isNullOrNil].eh": %struct.NSString = type { } %struct._objc__method_prototype_list = type opaque diff --git a/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll b/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll index 4d6971586c2a..b4a986ff77f9 100644 --- a/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll +++ b/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll @@ -22,8 +22,8 @@ entry: ; CHECK: bar: ; CHECK: fldt 4(%esp) ; CHECK-NEXT: fld %st(0) -; CHECK-NEXT: fmul %st(1) -; CHECK-NEXT: fmulp %st(1) +; CHECK-NEXT: fmul %st(1), %st(0) +; CHECK-NEXT: fmulp ; CHECK-NEXT: ret } diff --git a/test/CodeGen/X86/2008-02-22-ReMatBug.ll b/test/CodeGen/X86/2008-02-22-ReMatBug.ll index a91ac27f98dd..8f4d353f28d3 100644 --- a/test/CodeGen/X86/2008-02-22-ReMatBug.ll +++ b/test/CodeGen/X86/2008-02-22-ReMatBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -stats |& grep {Number of re-materialization} | grep 2 +; RUN: llc < %s -march=x86 -stats -regalloc=linearscan |& grep {Number of re-materialization} | grep 2 ; rdar://5761454 %struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* } diff --git a/test/CodeGen/X86/2008-03-18-CoalescerBug.ll b/test/CodeGen/X86/2008-03-18-CoalescerBug.ll index 3ae502619725..33d658ca01f9 100644 --- a/test/CodeGen/X86/2008-03-18-CoalescerBug.ll +++ b/test/CodeGen/X86/2008-03-18-CoalescerBug.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim | grep movss | count 1 -; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim -stats |& grep {Number of re-materialization} | grep 1 +; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim -regalloc=linearscan | grep movss | count 1 +; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim -regalloc=linearscan -stats |& grep {Number of re-materialization} | grep 1 %struct..0objc_object = type opaque %struct.OhBoy = type { } diff --git a/test/CodeGen/X86/2008-04-02-unnamedEH.ll b/test/CodeGen/X86/2008-04-02-unnamedEH.ll index 27bbbaa2962d..ab8ec801b049 100644 --- a/test/CodeGen/X86/2008-04-02-unnamedEH.ll +++ b/test/CodeGen/X86/2008-04-02-unnamedEH.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | FileCheck %s +; RUN: llc < %s -disable-cfi | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin8" diff --git a/test/CodeGen/X86/2008-04-16-ReMatBug.ll b/test/CodeGen/X86/2008-04-16-ReMatBug.ll index 6e8891bfd5b8..bfe8ef53f565 100644 --- a/test/CodeGen/X86/2008-04-16-ReMatBug.ll +++ b/test/CodeGen/X86/2008-04-16-ReMatBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin | grep movw | not grep {, %e} +; RUN: llc < %s -mtriple=i386-apple-darwin -disable-cgp-branch-opts | grep movw | not grep {, %e} %struct.DBC_t = type { i32, i8*, i16, %struct.DBC_t*, i8*, i8*, i8*, i8*, i8*, %struct.DBC_t*, i32, i32, i32, i32, i8*, i8*, i8*, i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i16, i16, i32*, i8, i16, %struct.DRVOPT*, i16 } %struct.DRVOPT = type { i16, i32, i8, %struct.DRVOPT* } diff --git a/test/CodeGen/X86/2008-07-11-SpillerBug.ll b/test/CodeGen/X86/2008-07-11-SpillerBug.ll index d0023b28c6dd..dee7415b0836 100644 --- a/test/CodeGen/X86/2008-07-11-SpillerBug.ll +++ b/test/CodeGen/X86/2008-07-11-SpillerBug.ll @@ -4,7 +4,6 @@ ; CHECK: andl $65534, % ; CHECK-NEXT: movl % ; CHECK-NEXT: movzwl -; CHECK-NEXT: movl $17 @g_5 = external global i16 ; <i16*> [#uses=2] @g_107 = external global i16 ; <i16*> [#uses=1] diff --git a/test/CodeGen/X86/2008-07-19-movups-spills.ll b/test/CodeGen/X86/2008-07-19-movups-spills.ll index cf04dcf0f18c..368af6d8abde 100644 --- a/test/CodeGen/X86/2008-07-19-movups-spills.ll +++ b/test/CodeGen/X86/2008-07-19-movups-spills.ll @@ -1,7 +1,9 @@ -; RUN: llc < %s -mtriple=i686-pc-linux -realign-stack=1 -mattr=sse2 | grep movaps | count 75 -; RUN: llc < %s -mtriple=i686-pc-linux -realign-stack=0 -mattr=sse2 | grep movaps | count 75 +; RUN: llc < %s -mtriple=i686-pc-linux -realign-stack=1 -mattr=sse2 | grep movups | count 33 +; RUN: llc < %s -mtriple=i686-pc-linux -realign-stack=0 -mattr=sse2 | grep movups | count 33 ; PR2539 ; PR8969 - make 32-bit linux have a 16-byte aligned stack +; Verify that movups is still generated with an aligned stack for the globals +; that must be accessed unaligned external global <4 x float>, align 1 ; <<4 x float>*>:0 [#uses=2] external global <4 x float>, align 1 ; <<4 x float>*>:1 [#uses=1] diff --git a/test/CodeGen/X86/2008-08-05-SpillerBug.ll b/test/CodeGen/X86/2008-08-05-SpillerBug.ll deleted file mode 100644 index d9d95b595bee..000000000000 --- a/test/CodeGen/X86/2008-08-05-SpillerBug.ll +++ /dev/null @@ -1,44 +0,0 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah -disable-fp-elim -stats |& grep asm-printer | grep 55 -; PR2568 - -@g_3 = external global i16 ; <i16*> [#uses=1] -@g_5 = external global i32 ; <i32*> [#uses=3] - -declare i32 @func_15(i16 signext , i16 signext , i32) nounwind - -define void @func_9_entry_2E_ce(i8 %p_11) nounwind { -newFuncRoot: - br label %entry.ce - -entry.ce.ret.exitStub: ; preds = %entry.ce - ret void - -entry.ce: ; preds = %newFuncRoot - load i16* @g_3, align 2 ; <i16>:0 [#uses=1] - icmp sgt i16 %0, 0 ; <i1>:1 [#uses=1] - zext i1 %1 to i32 ; <i32>:2 [#uses=1] - load i32* @g_5, align 4 ; <i32>:3 [#uses=4] - icmp ugt i32 %2, %3 ; <i1>:4 [#uses=1] - zext i1 %4 to i32 ; <i32>:5 [#uses=1] - icmp eq i32 %3, 0 ; <i1>:6 [#uses=1] - %.0 = select i1 %6, i32 1, i32 %3 ; <i32> [#uses=1] - urem i32 1, %.0 ; <i32>:7 [#uses=2] - sext i8 %p_11 to i16 ; <i16>:8 [#uses=1] - trunc i32 %3 to i16 ; <i16>:9 [#uses=1] - tail call i32 @func_15( i16 signext %8, i16 signext %9, i32 1 ) nounwind ; <i32>:10 [#uses=0] - load i32* @g_5, align 4 ; <i32>:11 [#uses=1] - trunc i32 %11 to i16 ; <i16>:12 [#uses=1] - tail call i32 @func_15( i16 signext %12, i16 signext 1, i32 %7 ) nounwind ; <i32>:13 [#uses=0] - sext i8 %p_11 to i32 ; <i32>:14 [#uses=1] - %p_11.lobit = lshr i8 %p_11, 7 ; <i8> [#uses=1] - %tmp = zext i8 %p_11.lobit to i32 ; <i32> [#uses=1] - %tmp.not = xor i32 %tmp, 1 ; <i32> [#uses=1] - %.015 = ashr i32 %14, %tmp.not ; <i32> [#uses=2] - icmp eq i32 %.015, 0 ; <i1>:15 [#uses=1] - %.016 = select i1 %15, i32 1, i32 %.015 ; <i32> [#uses=1] - udiv i32 %7, %.016 ; <i32>:16 [#uses=1] - icmp ult i32 %5, %16 ; <i1>:17 [#uses=1] - zext i1 %17 to i32 ; <i32>:18 [#uses=1] - store i32 %18, i32* @g_5, align 4 - br label %entry.ce.ret.exitStub -} diff --git a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll index eadfda0394dd..947a1f17172c 100644 --- a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll +++ b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll @@ -1,5 +1,7 @@ -; RUN: llc < %s -march=x86 | grep "#%ebp %edi %ebx 8(%esi) %eax %dl" -; RUN: llc < %s -march=x86 -regalloc=fast | grep "#%ebx %esi %edi 8(%ebp) %eax %dl" +; RUN: llc < %s -march=x86 -regalloc=linearscan | grep "#%ebp %edi %ebx 8(%esi) %eax %dl" +; RUN: llc < %s -march=x86 -regalloc=fast | grep "#%ebx %esi %edi 8(%ebp) %eax %dl" +; RUN: llc < %s -march=x86 -regalloc=basic | grep "#%ebp %esi %edx 8(%edi) %eax %bl" +; RUN: llc < %s -march=x86 -regalloc=greedy | grep "#%edx %edi %ebp 8(%esi) %eax %bl" ; The 1st, 2nd, 3rd and 5th registers above must all be different. The registers ; referenced in the 4th and 6th operands must not be the same as the 1st or 5th diff --git a/test/CodeGen/X86/2008-12-12-PrivateEHSymbol.ll b/test/CodeGen/X86/2008-12-12-PrivateEHSymbol.ll index e97b63db14d9..2e278118b7ad 100644 --- a/test/CodeGen/X86/2008-12-12-PrivateEHSymbol.ll +++ b/test/CodeGen/X86/2008-12-12-PrivateEHSymbol.ll @@ -1,7 +1,5 @@ -; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu | grep ^.L_Z1fv.eh -; RUN: llc < %s -march=x86 -mtriple=i686-unknown-linux-gnu | grep ^.L_Z1fv.eh -; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin9 | grep ^__Z1fv.eh -; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 | grep ^__Z1fv.eh +; RUN: llc < %s -disable-cfi -march=x86-64 -mtriple=x86_64-apple-darwin9 | grep ^__Z1fv.eh +; RUN: llc < %s -disable-cfi -march=x86 -mtriple=i386-apple-darwin9 | grep ^__Z1fv.eh define void @_Z1fv() { entry: diff --git a/test/CodeGen/X86/2009-02-20-PreAllocSplit-Crash.ll b/test/CodeGen/X86/2009-02-20-PreAllocSplit-Crash.ll index 58a7f9fb7593..aba4bfcbf52f 100644 --- a/test/CodeGen/X86/2009-02-20-PreAllocSplit-Crash.ll +++ b/test/CodeGen/X86/2009-02-20-PreAllocSplit-Crash.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin8 -pre-alloc-split +; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin8 -pre-alloc-split -regalloc=linearscan define i32 @main() nounwind { bb4.i.thread: diff --git a/test/CodeGen/X86/2009-03-11-CoalescerBug.ll b/test/CodeGen/X86/2009-03-11-CoalescerBug.ll deleted file mode 100644 index d5ba93e10495..000000000000 --- a/test/CodeGen/X86/2009-03-11-CoalescerBug.ll +++ /dev/null @@ -1,85 +0,0 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin9 -stats |& grep regcoalescing | grep commuting - -@lookupTable5B = external global [64 x i32], align 32 ; <[64 x i32]*> [#uses=1] -@lookupTable3B = external global [16 x i32], align 32 ; <[16 x i32]*> [#uses=1] -@disparity0 = external global i32 ; <i32*> [#uses=5] -@disparity1 = external global i32 ; <i32*> [#uses=3] - -define i32 @calc(i32 %theWord, i32 %k) nounwind { -entry: - %0 = lshr i32 %theWord, 3 ; <i32> [#uses=1] - %1 = and i32 %0, 31 ; <i32> [#uses=1] - %2 = shl i32 %k, 5 ; <i32> [#uses=1] - %3 = or i32 %1, %2 ; <i32> [#uses=1] - %4 = and i32 %theWord, 7 ; <i32> [#uses=1] - %5 = shl i32 %k, 3 ; <i32> [#uses=1] - %6 = or i32 %5, %4 ; <i32> [#uses=1] - %7 = getelementptr [64 x i32]* @lookupTable5B, i32 0, i32 %3 ; <i32*> [#uses=1] - %8 = load i32* %7, align 4 ; <i32> [#uses=5] - %9 = getelementptr [16 x i32]* @lookupTable3B, i32 0, i32 %6 ; <i32*> [#uses=1] - %10 = load i32* %9, align 4 ; <i32> [#uses=5] - %11 = and i32 %8, 65536 ; <i32> [#uses=1] - %12 = icmp eq i32 %11, 0 ; <i1> [#uses=1] - br i1 %12, label %bb1, label %bb - -bb: ; preds = %entry - %13 = and i32 %8, 994 ; <i32> [#uses=1] - %14 = load i32* @disparity0, align 4 ; <i32> [#uses=2] - store i32 %14, i32* @disparity1, align 4 - br label %bb8 - -bb1: ; preds = %entry - %15 = lshr i32 %8, 18 ; <i32> [#uses=1] - %16 = and i32 %15, 1 ; <i32> [#uses=1] - %17 = load i32* @disparity0, align 4 ; <i32> [#uses=4] - %18 = icmp eq i32 %16, %17 ; <i1> [#uses=1] - %not = select i1 %18, i32 0, i32 994 ; <i32> [#uses=1] - %.masked = and i32 %8, 994 ; <i32> [#uses=1] - %result.1 = xor i32 %not, %.masked ; <i32> [#uses=2] - %19 = and i32 %8, 524288 ; <i32> [#uses=1] - %20 = icmp eq i32 %19, 0 ; <i1> [#uses=1] - br i1 %20, label %bb7, label %bb6 - -bb6: ; preds = %bb1 - %21 = xor i32 %17, 1 ; <i32> [#uses=2] - store i32 %21, i32* @disparity1, align 4 - br label %bb8 - -bb7: ; preds = %bb1 - store i32 %17, i32* @disparity1, align 4 - br label %bb8 - -bb8: ; preds = %bb7, %bb6, %bb - %22 = phi i32 [ %17, %bb7 ], [ %21, %bb6 ], [ %14, %bb ] ; <i32> [#uses=4] - %result.0 = phi i32 [ %result.1, %bb7 ], [ %result.1, %bb6 ], [ %13, %bb ] ; <i32> [#uses=2] - %23 = and i32 %10, 65536 ; <i32> [#uses=1] - %24 = icmp eq i32 %23, 0 ; <i1> [#uses=1] - br i1 %24, label %bb10, label %bb9 - -bb9: ; preds = %bb8 - %25 = and i32 %10, 29 ; <i32> [#uses=1] - %26 = or i32 %result.0, %25 ; <i32> [#uses=1] - store i32 %22, i32* @disparity0, align 4 - ret i32 %26 - -bb10: ; preds = %bb8 - %27 = lshr i32 %10, 18 ; <i32> [#uses=1] - %28 = and i32 %27, 1 ; <i32> [#uses=1] - %29 = icmp eq i32 %28, %22 ; <i1> [#uses=1] - %not13 = select i1 %29, i32 0, i32 29 ; <i32> [#uses=1] - %.masked20 = and i32 %10, 29 ; <i32> [#uses=1] - %.pn = xor i32 %not13, %.masked20 ; <i32> [#uses=1] - %result.3 = or i32 %.pn, %result.0 ; <i32> [#uses=2] - %30 = and i32 %10, 524288 ; <i32> [#uses=1] - %31 = icmp eq i32 %30, 0 ; <i1> [#uses=1] - br i1 %31, label %bb17, label %bb16 - -bb16: ; preds = %bb10 - %32 = xor i32 %22, 1 ; <i32> [#uses=1] - store i32 %32, i32* @disparity0, align 4 - ret i32 %result.3 - -bb17: ; preds = %bb10 - store i32 %22, i32* @disparity0, align 4 - ret i32 %result.3 -} diff --git a/test/CodeGen/X86/2009-03-16-SpillerBug.ll b/test/CodeGen/X86/2009-03-16-SpillerBug.ll index 80e7639e7c29..951e191cd293 100644 --- a/test/CodeGen/X86/2009-03-16-SpillerBug.ll +++ b/test/CodeGen/X86/2009-03-16-SpillerBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -stats |& grep virtregrewriter | not grep {stores unfolded} +; RUN: llc < %s -mtriple=i386-apple-darwin -regalloc=linearscan -stats |& grep virtregrewriter | not grep {stores unfolded} ; rdar://6682365 ; Do not clobber a register if another spill slot is available in it and it's marked "do not clobber". diff --git a/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll b/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll index fcb2ed07dc13..f739216f825a 100644 --- a/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll +++ b/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep asm-printer | grep 82 +; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep asm-printer | grep 77 ; rdar://6802189 ; Test if linearscan is unfavoring registers for allocation to allow more reuse diff --git a/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll b/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll index 69f644f5834b..620e0f366740 100644 --- a/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll +++ b/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=i386-apple-darwin10.0 -relocation-model=pic -asm-verbose=false \ -; RUN: -disable-fp-elim -mattr=-sse41,-sse3,+sse2 -post-RA-scheduler=false < %s | \ +; RUN: -disable-fp-elim -mattr=-sse41,-sse3,+sse2 -post-RA-scheduler=false -regalloc=linearscan < %s | \ ; RUN: FileCheck %s ; rdar://6808032 diff --git a/test/CodeGen/X86/2009-04-24.ll b/test/CodeGen/X86/2009-04-24.ll index dd8823574cde..d6ed0c42230d 100644 --- a/test/CodeGen/X86/2009-04-24.ll +++ b/test/CodeGen/X86/2009-04-24.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu -regalloc=fast -relocation-model=pic > %t2 ; RUN: grep {leaq.*TLSGD} %t2 -; RUN; grep {__tls_get_addr} %t2 +; RUN: grep {__tls_get_addr} %t2 ; PR4004 @i = thread_local global i32 15 diff --git a/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll b/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll index 7325f4ae1251..f6ac2ba60647 100644 --- a/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll +++ b/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll @@ -11,7 +11,7 @@ ; Move return address (76(%esp)) to a temporary register (%ebp) ; CHECK: movl 76(%esp), [[REGISTER:%[a-z]+]] ; Overwrite return addresss -; CHECK: movl %ebx, 76(%esp) +; CHECK: movl [[EBX:%[a-z]+]], 76(%esp) ; Move return address from temporary register (%ebp) to new stack location (60(%esp)) ; CHECK: movl [[REGISTER]], 60(%esp) diff --git a/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll b/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll index fa3d5fbcdc48..69787c78cfd6 100644 --- a/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll +++ b/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll @@ -31,18 +31,19 @@ entry: ret void } +; CHECK: ti64 define void @ti64(double %a, double %b) nounwind { entry: %tmp1 = bitcast double %a to <1 x i64> %tmp2 = bitcast double %b to <1 x i64> %tmp3 = add <1 x i64> %tmp1, %tmp2 -; CHECK: addq %rax, %rcx +; CHECK: addq store <1 x i64> %tmp3, <1 x i64>* null ret void } ; MMX intrinsics calls get us MMX instructions. - +; CHECK: ti8a define void @ti8a(double %a, double %b) nounwind { entry: %tmp1 = bitcast double %a to x86_mmx diff --git a/test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll b/test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll index 323925c7ff68..5accfd74c0a9 100644 --- a/test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll +++ b/test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll @@ -22,8 +22,8 @@ while.end: ; preds = %while.cond, %entry %conv = zext i32 %v to i64 ; <i64> [#uses=1] %conv14 = zext i32 %div11 to i64 ; <i64> [#uses=1] ; Verify that we don't clobber %eax after putting the imulq result in %rax -; CHECK: imulq %r{{.}}x, %r[[RES:.]]x -; CHECK-NOT: movl {{.*}}, %e[[RES]]x +; CHECK: imulq %r{{.}}x, %r[[RES:..]] +; CHECK-NOT: movl {{.*}}, %e[[RES]] ; CHECK: div %mul = mul i64 %conv14, %conv ; <i64> [#uses=1] %conv16 = zext i32 %div to i64 ; <i64> [#uses=1] diff --git a/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll b/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll index f9bda7f1007e..848af82da820 100644 --- a/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll +++ b/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=x86-64 -O2 < %s | FileCheck %s +; RUN: llc -march=x86-64 -O2 -regalloc=basic < %s | FileCheck %s ; Test to check .debug_loc support. This test case emits many debug_loc entries. ; CHECK: Loc expr size diff --git a/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll b/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll index 60171eb62973..6600cc3cae4f 100644 --- a/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll +++ b/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll @@ -1,6 +1,7 @@ ; RUN: llc -O2 < %s | FileCheck %s +; RUN: llc -O2 -regalloc=basic < %s | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" -target triple = "x86_64-apple-darwin" +target triple = "x86_64-apple-darwin10" %struct.a = type { i32, %struct.a* } @@ -55,12 +56,21 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !29 = metadata !{i32 524299, metadata !9, i32 17, i32 0} ; [ DW_TAG_lexical_block ] !30 = metadata !{i32 19, i32 0, metadata !29, null} +; The variable bar:myvar changes registers after the first movq. +; It is cobbered by popq %rbx +; CHECK: movq +; CHECK-NEXT: [[LABEL:Ltmp[0-9]*]] +; CHECK: .loc 1 19 0 +; CHECK: popq +; CHECK-NEXT: [[CLOBBER:Ltmp[0-9]*]] + + ; CHECK: Ldebug_loc0: ; CHECK-NEXT: .quad Lfunc_begin0 -; CHECK-NEXT: .quad Ltmp3 +; CHECK-NEXT: .quad [[LABEL]] ; CHECK-NEXT: .short 1 ; CHECK-NEXT: .byte 85 -; CHECK-NEXT: .quad Ltmp3 -; CHECK-NEXT: .quad Ltmp6 +; CHECK-NEXT: .quad [[LABEL]] +; CHECK-NEXT: .quad [[CLOBBER]] ; CHECK-NEXT: .short 1 ; CHECK-NEXT: .byte 83 diff --git a/test/CodeGen/X86/2010-05-28-Crash.ll b/test/CodeGen/X86/2010-05-28-Crash.ll index ad8546ef8ce8..1a0da3177a22 100644 --- a/test/CodeGen/X86/2010-05-28-Crash.ll +++ b/test/CodeGen/X86/2010-05-28-Crash.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-apple-darwin -regalloc=basic < %s | FileCheck %s ; Test to check separate label for inlined function argument. define i32 @foo(i32 %y) nounwind optsize ssp { diff --git a/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll b/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll index 812d3720d6f5..a9c03ee563d8 100644 --- a/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll +++ b/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll @@ -1,4 +1,5 @@ -; RUN: llc -O2 < %s | FileCheck %s +; RUN: llc -O2 < %s | FileCheck %s +; RUN: llc -O2 -regalloc=basic < %s | FileCheck %s ; Test to check that unused argument 'this' is not undefined in debug info. target triple = "x86_64-apple-darwin10.2" diff --git a/test/CodeGen/X86/2010-08-04-StackVariable.ll b/test/CodeGen/X86/2010-08-04-StackVariable.ll index edfd1b868737..ba36fe7c12fd 100644 --- a/test/CodeGen/X86/2010-08-04-StackVariable.ll +++ b/test/CodeGen/X86/2010-08-04-StackVariable.ll @@ -1,5 +1,5 @@ -; RUN: llc -O0 -mtriple=x86_64-apple-darwin < %s | grep DW_OP_fbreg -; Use DW_OP_fbreg in variable's location expression if the variable is in a stack slot. +; RUN: llc -O0 -mtriple=x86_64-apple-darwin < %s | grep DW_OP_breg7 +; Use DW_OP_breg7 in variable's location expression if the variable is in a stack slot. %struct.SVal = type { i8*, i32 } diff --git a/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll b/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll index 8fe0309421e5..eaede30f9b55 100644 --- a/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll +++ b/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll @@ -18,9 +18,9 @@ entry: ret i32 0 } -; CHECK: movq ___stack_chk_guard@GOTPCREL(%rip), %rax -; CHECK: movb 30(%rsp), %dl -; CHECK: movb (%rsp), %sil -; CHECK: movb %sil, (%rsp) -; CHECK: movb %dl, 30(%rsp) +; CHECK: movq ___stack_chk_guard@GOTPCREL(%rip) +; CHECK: movb 38(%rsp), [[R0:%.+]] +; CHECK: movb 8(%rsp), [[R1:%.+]] +; CHECK: movb [[R1]], 8(%rsp) +; CHECK: movb [[R0]], 38(%rsp) ; CHECK: callq ___stack_chk_fail diff --git a/test/CodeGen/X86/2010-09-30-CMOV-JumpTable-PHI.ll b/test/CodeGen/X86/2010-09-30-CMOV-JumpTable-PHI.ll index cae81d086ea1..73e996c5d553 100644 --- a/test/CodeGen/X86/2010-09-30-CMOV-JumpTable-PHI.ll +++ b/test/CodeGen/X86/2010-09-30-CMOV-JumpTable-PHI.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -cgp-critical-edge-splitting=0 -mcpu=i386 < %s +; RUN: llc -verify-machineinstrs -mcpu=i386 < %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" target triple = "i386-pc-linux-gnu" diff --git a/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll b/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll index 973975b658a3..7f134113b2e3 100644 --- a/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll +++ b/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s | FileCheck %s +; RUN: llc < %s -regalloc=basic | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-darwin10.0.0" diff --git a/test/CodeGen/X86/2011-02-27-Fpextend.ll b/test/CodeGen/X86/2011-02-27-Fpextend.ll new file mode 100644 index 000000000000..c12b9563b305 --- /dev/null +++ b/test/CodeGen/X86/2011-02-27-Fpextend.ll @@ -0,0 +1,7 @@ +; RUN: llc -mtriple=x86_64-pc-linux < %s +; PR9309 + +define <4 x double> @f_fu(<4 x float>) nounwind { + %float2double.i = fpext <4 x float> %0 to <4 x double> + ret <4 x double> %float2double.i +} diff --git a/test/CodeGen/X86/2011-03-02-DAGCombiner.ll b/test/CodeGen/X86/2011-03-02-DAGCombiner.ll new file mode 100644 index 000000000000..be58cedfdaa7 --- /dev/null +++ b/test/CodeGen/X86/2011-03-02-DAGCombiner.ll @@ -0,0 +1,51 @@ +; RUN: llc < %s -march=x86-64 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin11.0.0" + +%0 = type { i8, [3 x i8] } +%struct.anon = type { float, x86_fp80 } + +define i32 @main() nounwind ssp { +entry: + %retval = alloca i32, align 4 + %F = alloca %struct.anon, align 16 + %K = alloca %0, align 4 + store i32 0, i32* %retval + %0 = bitcast %0* %K to i32* + %1 = load i32* %0, align 4 + %2 = and i32 %1, -121 + %3 = or i32 %2, 32 + store i32 %3, i32* %0, align 4 + %4 = bitcast %0* %K to i32* + %5 = load i32* %4, align 4 + %6 = lshr i32 %5, 3 + %bf.clear = and i32 %6, 15 + %conv = sitofp i32 %bf.clear to float + %f = getelementptr inbounds %struct.anon* %F, i32 0, i32 0 + %tmp = load float* %f, align 4 + %sub = fsub float %tmp, %conv + store float %sub, float* %f, align 4 + %ld = getelementptr inbounds %struct.anon* %F, i32 0, i32 1 + %tmp1 = load x86_fp80* %ld, align 16 + %7 = bitcast %0* %K to i32* + %8 = load i32* %7, align 4 + %9 = lshr i32 %8, 7 + %bf.clear2 = and i32 %9, 1 + %conv3 = uitofp i32 %bf.clear2 to x86_fp80 + %sub4 = fsub x86_fp80 %conv3, %tmp1 + %conv5 = fptoui x86_fp80 %sub4 to i32 + %bf.value = and i32 %conv5, 1 + %10 = bitcast %0* %K to i32* + %11 = and i32 %bf.value, 1 + %12 = shl i32 %11, 7 + %13 = load i32* %10, align 4 + %14 = and i32 %13, -129 + %15 = or i32 %14, %12 + store i32 %15, i32* %10, align 4 + %call = call i32 (...)* @iequals(i32 1841, i32 %bf.value, i32 0) + %16 = load i32* %retval + ret i32 %16 +} + +declare i32 @iequals(...) diff --git a/test/CodeGen/X86/2011-03-08-Sched-crash.ll b/test/CodeGen/X86/2011-03-08-Sched-crash.ll new file mode 100644 index 000000000000..6329ae670e48 --- /dev/null +++ b/test/CodeGen/X86/2011-03-08-Sched-crash.ll @@ -0,0 +1,56 @@ +; RUN: llc < %s +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" +target triple = "i386-apple-darwin9.0.0" + +%0 = type { i32, i1 } + +declare %0 @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone + +define linkonce_odr hidden void @_ZN2js5QueueINS_7SlotMap8SlotInfoEE6ensureEj(i8* nocapture %this, i32 %size) nounwind align 2 { + br i1 undef, label %14, label %1 + +; <label>:1 ; preds = %0 + br i1 undef, label %2, label %3 + +; <label>:2 ; preds = %1 + br label %3 + +; <label>:3 ; preds = %2, %1 + br i1 undef, label %13, label %4 + +; <label>:4 ; preds = %3 + %5 = tail call %0 @llvm.umul.with.overflow.i32(i32 undef, i32 16) + %6 = extractvalue %0 %5, 1 + %7 = extractvalue %0 %5, 0 + %.op = add i32 %7, 7 + %.op.op = and i32 %.op, -8 + %8 = select i1 %6, i32 0, i32 %.op.op + br i1 undef, label %10, label %9 + +; <label>:9 ; preds = %4 + br label %_ZnamRN7nanojit9AllocatorE.exit + +; <label>:10 ; preds = %4 + %11 = tail call i8* @_ZN7nanojit9Allocator9allocSlowEmb(i8* undef, i32 %8, i1 zeroext false) nounwind + br label %_ZnamRN7nanojit9AllocatorE.exit + +_ZnamRN7nanojit9AllocatorE.exit: ; preds = %10, %9 + br i1 false, label %._crit_edge, label %.lr.ph + +.lr.ph: ; preds = %_ZnamRN7nanojit9AllocatorE.exit + br label %12 + +; <label>:12 ; preds = %12, %.lr.ph + br i1 undef, label %._crit_edge, label %12 + +._crit_edge: ; preds = %12, %_ZnamRN7nanojit9AllocatorE.exit + br label %14 + +; <label>:13 ; preds = %3 + br label %14 + +; <label>:14 ; preds = %13, %._crit_edge, %0 + ret void +} + +declare i8* @_ZN7nanojit9Allocator9allocSlowEmb(i8*, i32, i1 zeroext) diff --git a/test/CodeGen/X86/2011-03-09-Physreg-Coalescing.ll b/test/CodeGen/X86/2011-03-09-Physreg-Coalescing.ll new file mode 100644 index 000000000000..e48edf7e30b4 --- /dev/null +++ b/test/CodeGen/X86/2011-03-09-Physreg-Coalescing.ll @@ -0,0 +1,22 @@ +; RUN: llc -mcpu=yonah < %s +; PR9438 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" +target triple = "i386-unknown-freebsd9.0" + +; The 'call fastcc' ties down %ebx, %ecx, and %edx. +; A MUL8r ties down %al, leaving no GR32_ABCD registers available. +; The coalescer can easily overallocate physical registers, +; and register allocation fails. + +declare fastcc i8* @save_string(i8* %d, i8* nocapture %s) nounwind + +define i32 @cvtchar(i8* nocapture %sp) nounwind { + %temp.i = alloca [2 x i8], align 1 + %tmp1 = load i8* %sp, align 1 + %div = udiv i8 %tmp1, 10 + %rem = urem i8 %div, 10 + %arrayidx.i = getelementptr inbounds [2 x i8]* %temp.i, i32 0, i32 0 + store i8 %rem, i8* %arrayidx.i, align 1 + %call.i = call fastcc i8* @save_string(i8* %sp, i8* %arrayidx.i) nounwind + ret i32 undef +} diff --git a/test/CodeGen/X86/2011-03-30-CreateFixedObjCrash.ll b/test/CodeGen/X86/2011-03-30-CreateFixedObjCrash.ll new file mode 100644 index 000000000000..38a9b3d4f5cc --- /dev/null +++ b/test/CodeGen/X86/2011-03-30-CreateFixedObjCrash.ll @@ -0,0 +1,10 @@ +; RUN: llc < %s -march=x86 + +; rdar://7983260 + +%struct.T0 = type {} + +define void @fn4(%struct.T0* byval %arg0) nounwind ssp { +entry: + ret void +} diff --git a/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll b/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll new file mode 100644 index 000000000000..07b1971218c3 --- /dev/null +++ b/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll @@ -0,0 +1,65 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=yonah | FileCheck %s +; Reduced from JavaScriptCore + +%"class.JSC::CodeLocationCall" = type { [8 x i8] } +%"class.JSC::JSGlobalData" = type { [4 x i8] } +%"class.JSC::FunctionPtr" = type { i8* } +%"class.JSC::Structure" = type { [4 x i8] } +%"class.JSC::UString" = type { i8* } +%"class.JSC::JSString" = type { [16 x i8], i32, %"class.JSC::UString", i32 } + +declare hidden fastcc void @_ZN3JSCL23returnToThrowTrampolineEPNS_12JSGlobalDataENS_16ReturnAddressPtrERS2_(%"class.JSC::JSGlobalData"* nocapture, i8*, %"class.JSC::FunctionPtr"* nocapture) nounwind noinline ssp + +; Avoid hoisting the test above loads or copies +; CHECK: %entry +; CHECK: cmpq +; CHECK-NOT: mov +; CHECK: jb +define i32 @cti_op_eq(i8** nocapture %args) nounwind ssp { +entry: + %0 = load i8** null, align 8 + %tmp13 = bitcast i8* %0 to %"class.JSC::CodeLocationCall"* + %tobool.i.i.i = icmp ugt i8* undef, inttoptr (i64 281474976710655 to i8*) + %or.cond.i = and i1 %tobool.i.i.i, undef + br i1 %or.cond.i, label %if.then.i, label %if.end.i + +if.then.i: ; preds = %entry + br i1 undef, label %if.then.i.i.i, label %_ZN3JSC7JSValue19equalSlowCaseInlineEPNS_9ExecStateES0_S0_.exit + +if.then.i.i.i: ; preds = %if.then.i + %conv.i.i.i.i = trunc i64 undef to i32 + br label %_ZN3JSC7JSValue19equalSlowCaseInlineEPNS_9ExecStateES0_S0_.exit + +if.end.i: ; preds = %entry + br i1 undef, label %land.rhs.i121.i, label %_ZNK3JSC7JSValue8isStringEv.exit122.i + +land.rhs.i121.i: ; preds = %if.end.i + %tmp.i.i117.i = load %"class.JSC::Structure"** undef, align 8 + br label %_ZNK3JSC7JSValue8isStringEv.exit122.i + +_ZNK3JSC7JSValue8isStringEv.exit122.i: ; preds = %land.rhs.i121.i, %if.end.i + %brmerge.i = or i1 undef, false + %or.cond = or i1 false, %brmerge.i + br i1 %or.cond, label %_ZN3JSC7JSValue19equalSlowCaseInlineEPNS_9ExecStateES0_S0_.exit, label %if.then.i92.i + +if.then.i92.i: ; preds = %_ZNK3JSC7JSValue8isStringEv.exit122.i + tail call void @_ZNK3JSC8JSString11resolveRopeEPNS_9ExecStateE(%"class.JSC::JSString"* undef, %"class.JSC::CodeLocationCall"* %tmp13) nounwind + unreachable + +_ZN3JSC7JSValue19equalSlowCaseInlineEPNS_9ExecStateES0_S0_.exit: ; preds = %_ZNK3JSC7JSValue8isStringEv.exit122.i, %if.then.i.i.i, %if.then.i + + %1 = load i8** undef, align 8 + br i1 undef, label %do.end39, label %do.body27 + +do.body27: ; preds = %_ZN3JSC7JSValue19equalSlowCaseInlineEPNS_9ExecStateES0_S0_.exit + %tmp30 = bitcast i8* %1 to %"class.JSC::JSGlobalData"* + %2 = getelementptr inbounds i8** %args, i64 -1 + %3 = bitcast i8** %2 to %"class.JSC::FunctionPtr"* + tail call fastcc void @_ZN3JSCL23returnToThrowTrampolineEPNS_12JSGlobalDataENS_16ReturnAddressPtrERS2_(%"class.JSC::JSGlobalData"* %tmp30, i8* undef, %"class.JSC::FunctionPtr"* %3) + unreachable + +do.end39: ; preds = %_ZN3JSC7JSValue19equalSlowCaseInlineEPNS_9ExecStateES0_S0_.exit + ret i32 undef +} + +declare void @_ZNK3JSC8JSString11resolveRopeEPNS_9ExecStateE(%"class.JSC::JSString"*, %"class.JSC::CodeLocationCall"*) diff --git a/test/CodeGen/X86/3dnow-intrinsics.ll b/test/CodeGen/X86/3dnow-intrinsics.ll new file mode 100644 index 000000000000..0b27bf2d1853 --- /dev/null +++ b/test/CodeGen/X86/3dnow-intrinsics.ll @@ -0,0 +1,297 @@ +; RUN: llc < %s -march=x86 -mattr=+3dnow | FileCheck %s + +define <8 x i8> @test_pavgusb(x86_mmx %a.coerce, x86_mmx %b.coerce) nounwind readnone { +; CHECK: pavgusb +entry: + %0 = bitcast x86_mmx %a.coerce to <8 x i8> + %1 = bitcast x86_mmx %b.coerce to <8 x i8> + %2 = bitcast <8 x i8> %0 to x86_mmx + %3 = bitcast <8 x i8> %1 to x86_mmx + %4 = call x86_mmx @llvm.x86.3dnow.pavgusb(x86_mmx %2, x86_mmx %3) + %5 = bitcast x86_mmx %4 to <8 x i8> + ret <8 x i8> %5 +} + +declare x86_mmx @llvm.x86.3dnow.pavgusb(x86_mmx, x86_mmx) nounwind readnone + +define <2 x i32> @test_pf2id(<2 x float> %a) nounwind readnone { +; CHECK: pf2id +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = tail call x86_mmx @llvm.x86.3dnow.pf2id(x86_mmx %0) + %2 = bitcast x86_mmx %1 to <2 x i32> + ret <2 x i32> %2 +} + +declare x86_mmx @llvm.x86.3dnow.pf2id(x86_mmx) nounwind readnone + +define <2 x float> @test_pfacc(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfacc +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfacc(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfacc(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pfadd(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfadd +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfadd(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfadd(x86_mmx, x86_mmx) nounwind readnone + +define <2 x i32> @test_pfcmpeq(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfcmpeq +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfcmpeq(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x i32> + ret <2 x i32> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfcmpeq(x86_mmx, x86_mmx) nounwind readnone + +define <2 x i32> @test_pfcmpge(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfcmpge +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfcmpge(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x i32> + ret <2 x i32> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfcmpge(x86_mmx, x86_mmx) nounwind readnone + +define <2 x i32> @test_pfcmpgt(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfcmpgt +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfcmpgt(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x i32> + ret <2 x i32> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfcmpgt(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pfmax(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfmax +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfmax(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfmax(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pfmin(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfmin +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfmin(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfmin(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pfmul(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfmul +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfmul(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfmul(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pfrcp(<2 x float> %a) nounwind readnone { +; CHECK: pfrcp +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = tail call x86_mmx @llvm.x86.3dnow.pfrcp(x86_mmx %0) + %2 = bitcast x86_mmx %1 to <2 x float> + ret <2 x float> %2 +} + +declare x86_mmx @llvm.x86.3dnow.pfrcp(x86_mmx) nounwind readnone + +define <2 x float> @test_pfrcpit1(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfrcpit1 +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfrcpit1(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfrcpit1(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pfrcpit2(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfrcpit2 +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfrcpit2(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfrcpit2(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pfrsqrt(<2 x float> %a) nounwind readnone { +; CHECK: pfrsqrt +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = tail call x86_mmx @llvm.x86.3dnow.pfrsqrt(x86_mmx %0) + %2 = bitcast x86_mmx %1 to <2 x float> + ret <2 x float> %2 +} + +declare x86_mmx @llvm.x86.3dnow.pfrsqrt(x86_mmx) nounwind readnone + +define <2 x float> @test_pfrsqit1(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfrsqit1 +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfrsqit1(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfrsqit1(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pfsub(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfsub +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfsub(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfsub(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pfsubr(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfsubr +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfsubr(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfsubr(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pi2fd(x86_mmx %a.coerce) nounwind readnone { +; CHECK: pi2fd +entry: + %0 = bitcast x86_mmx %a.coerce to <2 x i32> + %1 = bitcast <2 x i32> %0 to x86_mmx + %2 = call x86_mmx @llvm.x86.3dnow.pi2fd(x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pi2fd(x86_mmx) nounwind readnone + +define <4 x i16> @test_pmulhrw(x86_mmx %a.coerce, x86_mmx %b.coerce) nounwind readnone { +; CHECK: pmulhrw +entry: + %0 = bitcast x86_mmx %a.coerce to <4 x i16> + %1 = bitcast x86_mmx %b.coerce to <4 x i16> + %2 = bitcast <4 x i16> %0 to x86_mmx + %3 = bitcast <4 x i16> %1 to x86_mmx + %4 = call x86_mmx @llvm.x86.3dnow.pmulhrw(x86_mmx %2, x86_mmx %3) + %5 = bitcast x86_mmx %4 to <4 x i16> + ret <4 x i16> %5 +} + +declare x86_mmx @llvm.x86.3dnow.pmulhrw(x86_mmx, x86_mmx) nounwind readnone + +define <2 x i32> @test_pf2iw(<2 x float> %a) nounwind readnone { +; CHECK: pf2iw +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = tail call x86_mmx @llvm.x86.3dnowa.pf2iw(x86_mmx %0) + %2 = bitcast x86_mmx %1 to <2 x i32> + ret <2 x i32> %2 +} + +declare x86_mmx @llvm.x86.3dnowa.pf2iw(x86_mmx) nounwind readnone + +define <2 x float> @test_pfnacc(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfnacc +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnowa.pfnacc(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnowa.pfnacc(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pfpnacc(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfpnacc +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnowa.pfpnacc(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnowa.pfpnacc(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pi2fw(x86_mmx %a.coerce) nounwind readnone { +; CHECK: pi2fw +entry: + %0 = bitcast x86_mmx %a.coerce to <2 x i32> + %1 = bitcast <2 x i32> %0 to x86_mmx + %2 = call x86_mmx @llvm.x86.3dnowa.pi2fw(x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnowa.pi2fw(x86_mmx) nounwind readnone + +define <2 x float> @test_pswapdsf(<2 x float> %a) nounwind readnone { +; CHECK: pswapd +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = tail call x86_mmx @llvm.x86.3dnowa.pswapd(x86_mmx %0) + %2 = bitcast x86_mmx %1 to <2 x float> + ret <2 x float> %2 +} + +define <2 x i32> @test_pswapdsi(<2 x i32> %a) nounwind readnone { +; CHECK: pswapd +entry: + %0 = bitcast <2 x i32> %a to x86_mmx + %1 = tail call x86_mmx @llvm.x86.3dnowa.pswapd(x86_mmx %0) + %2 = bitcast x86_mmx %1 to <2 x i32> + ret <2 x i32> %2 +} + +declare x86_mmx @llvm.x86.3dnowa.pswapd(x86_mmx) nounwind readnone diff --git a/test/CodeGen/X86/MachineSink-PHIUse.ll b/test/CodeGen/X86/MachineSink-PHIUse.ll index 728e37736018..3758fd8ce500 100644 --- a/test/CodeGen/X86/MachineSink-PHIUse.ll +++ b/test/CodeGen/X86/MachineSink-PHIUse.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-appel-darwin -stats |& grep {machine-sink} +; RUN: llc < %s -mtriple=x86_64-appel-darwin -disable-cgp-branch-opts -stats |& grep {machine-sink} define fastcc void @t() nounwind ssp { entry: diff --git a/test/CodeGen/X86/SIMD/dg.exp b/test/CodeGen/X86/SIMD/dg.exp new file mode 100644 index 000000000000..629a14773615 --- /dev/null +++ b/test/CodeGen/X86/SIMD/dg.exp @@ -0,0 +1,5 @@ +load_lib llvm.exp + +if { [llvm_supports_target X86] } { + RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] +} diff --git a/test/CodeGen/X86/SIMD/notvunpcklpd.ll b/test/CodeGen/X86/SIMD/notvunpcklpd.ll new file mode 100644 index 000000000000..3afc2f2305ab --- /dev/null +++ b/test/CodeGen/X86/SIMD/notvunpcklpd.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -mattr=+avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-unknown-linux-gnu" + +define void @try_([2 x <4 x double>]* noalias %incarray, [2 x <4 x double>]* noalias %incarrayb ) { +entry: + %incarray1 = alloca [2 x <4 x double>]*, align 8 + %incarrayb1 = alloca [2 x <4 x double>]*, align 8 + %carray = alloca [2 x <4 x double>], align 16 + %r = getelementptr [2 x <4 x double>]* %incarray, i32 0, i32 0 + %rb = getelementptr [2 x <4 x double>]* %incarrayb, i32 0, i32 0 + %r3 = load <4 x double>* %r, align 8 + %r4 = load <4 x double>* %rb, align 8 + %r11 = shufflevector <4 x double> %r3, <4 x double> %r4, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x double>> [#uses=1] +; CHECK-NOT: vunpcklpd + %r12 = getelementptr [2 x <4 x double>]* %carray, i32 0, i32 1 + store <4 x double> %r11, <4 x double>* %r12, align 4 + ret void +} diff --git a/test/CodeGen/X86/SIMD/notvunpcklps.ll b/test/CodeGen/X86/SIMD/notvunpcklps.ll new file mode 100644 index 000000000000..19daa3e7d508 --- /dev/null +++ b/test/CodeGen/X86/SIMD/notvunpcklps.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -mattr=+avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-unknown-linux-gnu" + +define void @try_([2 x <8 x float>]* noalias %incarray, [2 x <8 x float>]* noalias %incarrayb ) { +enmtry: + %incarray1 = alloca [2 x <8 x float>]*, align 8 + %incarrayb1 = alloca [2 x <8 x float>]*, align 8 + %carray = alloca [2 x <8 x float>], align 16 + %r = getelementptr [2 x <8 x float>]* %incarray, i32 0, i32 0 + %rb = getelementptr [2 x <8 x float>]* %incarrayb, i32 0, i32 0 + %r3 = load <8 x float>* %r, align 8 + %r4 = load <8 x float>* %rb, align 8 + %r8 = shufflevector <8 x float> %r3, <8 x float> %r4, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 > ; <<8 x float>> [#uses=1] +; CHECK-NOT: vunpcklps + %r9 = getelementptr [2 x <8 x float>]* %carray, i32 0, i32 0 + store <8 x float> %r8, <8 x float>* %r9, align 4 + ret void +} diff --git a/test/CodeGen/X86/SIMD/vunpcklpd.ll b/test/CodeGen/X86/SIMD/vunpcklpd.ll new file mode 100644 index 000000000000..60d23a4f6789 --- /dev/null +++ b/test/CodeGen/X86/SIMD/vunpcklpd.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -mattr=+avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-unknown-linux-gnu" + +define void @try_([2 x <4 x double>]* noalias %incarray, [2 x <4 x double>]* noalias %incarrayb ) { +entry: + %incarray1 = alloca [2 x <4 x double>]*, align 8 + %incarrayb1 = alloca [2 x <4 x double>]*, align 8 + %carray = alloca [2 x <4 x double>], align 16 + %r = getelementptr [2 x <4 x double>]* %incarray, i32 0, i32 0 + %rb = getelementptr [2 x <4 x double>]* %incarrayb, i32 0, i32 0 + %r3 = load <4 x double>* %r, align 8 + %r4 = load <4 x double>* %rb, align 8 + %r11 = shufflevector <4 x double> %r3, <4 x double> %r4, <4 x i32> < i32 0, i32 4, i32 2, i32 6 > ; <<4 x double>> [#uses=1] +; CHECK: vunpcklpd + %r12 = getelementptr [2 x <4 x double>]* %carray, i32 0, i32 1 + store <4 x double> %r11, <4 x double>* %r12, align 4 + ret void +} diff --git a/test/CodeGen/X86/SIMD/vunpcklps.ll b/test/CodeGen/X86/SIMD/vunpcklps.ll new file mode 100644 index 000000000000..a87b29965eaa --- /dev/null +++ b/test/CodeGen/X86/SIMD/vunpcklps.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -mattr=+avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target triple = "x86_64-unknown-linux-gnu" + +define void @try_([2 x <8 x float>]* noalias %incarray, [2 x <8 x float>]* noalias %incarrayb ) { +entry: + %incarray1 = alloca [2 x <8 x float>]*, align 8 + %incarrayb1 = alloca [2 x <8 x float>]*, align 8 + %carray = alloca [2 x <8 x float>], align 16 + %r = getelementptr [2 x <8 x float>]* %incarray, i32 0, i32 0 + %rb = getelementptr [2 x <8 x float>]* %incarrayb, i32 0, i32 0 + %r3 = load <8 x float>* %r, align 8 + %r4 = load <8 x float>* %rb, align 8 + %r11 = shufflevector <8 x float> %r3, <8 x float> %r4, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13 > ; <<8 x float>> [#uses=1] +; CHECK: vunpcklps + %r12 = getelementptr [2 x <8 x float>]* %carray, i32 0, i32 1 + store <8 x float> %r11, <8 x float>* %r12, align 4 + ret void +} diff --git a/test/CodeGen/X86/abi-isel.ll b/test/CodeGen/X86/abi-isel.ll index 5b4d79fa22b9..7535e07b809c 100644 --- a/test/CodeGen/X86/abi-isel.ll +++ b/test/CodeGen/X86/abi-isel.ll @@ -12,6 +12,17 @@ ; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-DYNAMIC ; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-PIC +; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-32-STATIC +; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-32-PIC +; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-64-STATIC +; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=LINUX-64-PIC +; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=i686-apple-darwin -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=DARWIN-32-STATIC +; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=i686-apple-darwin -march=x86 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-32-DYNAMIC +; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=i686-apple-darwin -march=x86 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-32-PIC +; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=DARWIN-64-STATIC +; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-DYNAMIC +; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-PIC + @src = external global [131072 x i32] @dst = external global [131072 x i32] @xsrc = external global [32 x i32] @@ -38,68 +49,68 @@ entry: ret void ; LINUX-64-STATIC: foo00: -; LINUX-64-STATIC: movl src(%rip), %eax -; LINUX-64-STATIC: movl %eax, dst +; LINUX-64-STATIC: movl src(%rip), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], dst ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: foo00: -; LINUX-32-STATIC: movl src, %eax -; LINUX-32-STATIC-NEXT: movl %eax, dst +; LINUX-32-STATIC: movl src, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], dst ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: foo00: -; LINUX-32-PIC: movl src, %eax -; LINUX-32-PIC-NEXT: movl %eax, dst +; LINUX-32-PIC: movl src, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], dst ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: foo00: -; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl (%rax), %eax -; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, (%rcx) +; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r..]] +; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e..]] +; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), [[RCX:%r..]] +; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _foo00: -; DARWIN-32-STATIC: movl _src, %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _dst +; DARWIN-32-STATIC: movl _src, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _dst ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _foo00: -; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: movl (%eax), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx) +; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, [[EAX:%e..]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[EAX]]), [[EAX:%e..]] +; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, [[ECX:%e..]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], ([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo00: ; DARWIN-32-PIC: calll L0$pb ; DARWIN-32-PIC-NEXT: L0$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L0$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L0$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e..]] +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L0$pb([[EAX]]), [[ECX:%e..]] +; DARWIN-32-PIC-NEXT: movl ([[ECX]]), [[ECX:%e..]] +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L0$pb([[EAX]]), [[EAX:%e..]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], ([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo00: -; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl (%rax), %eax -; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx) +; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), [[RAX:%r..]] +; DARWIN-64-STATIC-NEXT: movl ([[RAX]]), [[EAX:%e..]] +; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r..]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], ([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _foo00: -; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl (%rax), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx) +; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), [[RAX:%r..]] +; DARWIN-64-DYNAMIC-NEXT: movl ([[RAX]]), [[EAX:%e..]] +; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r..]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], ([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _foo00: -; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movl (%rax), %eax -; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, (%rcx) +; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), [[RAX:%r..]] +; DARWIN-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e..]] +; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r..]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], ([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -110,68 +121,68 @@ entry: ret void ; LINUX-64-STATIC: fxo00: -; LINUX-64-STATIC: movl xsrc(%rip), %eax -; LINUX-64-STATIC: movl %eax, xdst +; LINUX-64-STATIC: movl xsrc(%rip), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], xdst ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: fxo00: -; LINUX-32-STATIC: movl xsrc, %eax -; LINUX-32-STATIC-NEXT: movl %eax, xdst +; LINUX-32-STATIC: movl xsrc, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], xdst ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: fxo00: -; LINUX-32-PIC: movl xsrc, %eax -; LINUX-32-PIC-NEXT: movl %eax, xdst +; LINUX-32-PIC: movl xsrc, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], xdst ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: fxo00: -; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl (%rax), %eax -; LINUX-64-PIC-NEXT: movq xdst@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, (%rcx) +; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq xdst@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _fxo00: -; DARWIN-32-STATIC: movl _xsrc, %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _xdst +; DARWIN-32-STATIC: movl _xsrc, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _xdst ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _fxo00: -; DARWIN-32-DYNAMIC: movl L_xsrc$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: movl (%eax), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx) +; DARWIN-32-DYNAMIC: movl L_xsrc$non_lazy_ptr, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], ([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _fxo00: ; DARWIN-32-PIC: calll L1$pb ; DARWIN-32-PIC-NEXT: L1$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L1$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L1$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L1$pb([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl ([[ECX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L1$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], ([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _fxo00: -; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl (%rax), %eax -; DARWIN-64-STATIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx) +; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _xdst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], ([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _fxo00: -; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl (%rax), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx) +; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _xdst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], ([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _fxo00: -; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movl (%rax), %eax -; DARWIN-64-PIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, (%rcx) +; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _xdst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], ([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -192,9 +203,9 @@ entry: ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: foo01: -; LINUX-64-PIC: movq dst@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq %rax, (%rcx) +; LINUX-64-PIC: movq dst@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _foo01: @@ -202,36 +213,36 @@ entry: ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _foo01: -; DARWIN-32-DYNAMIC: movl L_dst$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx) +; DARWIN-32-DYNAMIC: movl L_dst$non_lazy_ptr, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], ([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo01: ; DARWIN-32-PIC: calll L2$pb ; DARWIN-32-PIC-NEXT: L2$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L2$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L2$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) +; DARWIN-32-PIC-NEXT: popl +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L2$pb( +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L2$pb( +; DARWIN-32-PIC-NEXT: movl ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo01: -; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _foo01: -; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _foo01: -; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -252,9 +263,9 @@ entry: ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: fxo01: -; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq %rax, (%rcx) +; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _fxo01: @@ -262,36 +273,36 @@ entry: ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _fxo01: -; DARWIN-32-DYNAMIC: movl L_xdst$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx) +; DARWIN-32-DYNAMIC: movl L_xdst$non_lazy_ptr, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], ([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _fxo01: ; DARWIN-32-PIC: calll L3$pb ; DARWIN-32-PIC-NEXT: L3$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L3$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L3$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) +; DARWIN-32-PIC-NEXT: popl [[R0:%e..]] +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L3$pb([[R0]]), [[R1:%e..]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L3$pb([[R0]]), [[R2:%e..]] +; DARWIN-32-PIC-NEXT: movl [[R1:%e..]], ([[R2]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _fxo01: -; DARWIN-64-STATIC: movq _xdst@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-STATIC: movq _xdst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _fxo01: -; DARWIN-64-DYNAMIC: movq _xdst@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-DYNAMIC: movq _xdst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _fxo01: -; DARWIN-64-PIC: movq _xdst@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-PIC: movq _xdst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -308,72 +319,72 @@ entry: ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: foo02: -; LINUX-32-STATIC: movl src, %eax -; LINUX-32-STATIC-NEXT: movl ptr, %ecx -; LINUX-32-STATIC-NEXT: movl %eax, (%ecx) +; LINUX-32-STATIC: movl src, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl ptr, [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], ([[ECX]]) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: foo02: -; LINUX-32-PIC: movl src, %eax -; LINUX-32-PIC-NEXT: movl ptr, %ecx -; LINUX-32-PIC-NEXT: movl %eax, (%ecx) +; LINUX-32-PIC: movl src, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl ptr, [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], ([[ECX]]) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: foo02: -; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl (%rax), %eax -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq (%rcx), %rcx -; LINUX-64-PIC-NEXT: movl %eax, (%rcx) +; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _foo02: -; DARWIN-32-STATIC: movl _src, %eax -; DARWIN-32-STATIC-NEXT: movl _ptr, %ecx -; DARWIN-32-STATIC-NEXT: movl %eax, (%ecx) +; DARWIN-32-STATIC: movl _src, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _ptr, [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], ([[ECX]]) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _foo02: -; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: movl (%eax), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx) +; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[ECX]]), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], ([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo02: ; DARWIN-32-PIC: calll L4$pb ; DARWIN-32-PIC-NEXT: L4$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L4$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L4$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl (%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) +; DARWIN-32-PIC-NEXT: popl [[R0:%e..]] +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L4$pb([[R0]]), [[R1:%e..]] +; DARWIN-32-PIC-NEXT: movl ([[R1]]), [[R2:%e..]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L4$pb([[R0]]), [[R3:%e..]] +; DARWIN-32-PIC-NEXT: movl ([[R3]]), [[R4:%e..]] +; DARWIN-32-PIC-NEXT: movl [[R2]], ([[R4]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo02: -; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl (%rax), %eax -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx) +; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], ([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _foo02: -; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl (%rax), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx) +; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], ([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _foo02: -; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movl (%rax), %eax -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, (%rcx) +; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], ([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -389,73 +400,73 @@ entry: ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: fxo02: -; LINUX-32-STATIC: movl xsrc, %eax -; LINUX-32-STATIC-NEXT: movl ptr, %ecx -; LINUX-32-STATIC-NEXT: movl %eax, (%ecx) +; LINUX-32-STATIC: movl xsrc, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl ptr, [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], ([[ECX]]) ; LINUX-32-STATIC-NEXT: ret ret void ; LINUX-32-PIC: fxo02: -; LINUX-32-PIC: movl xsrc, %eax -; LINUX-32-PIC-NEXT: movl ptr, %ecx -; LINUX-32-PIC-NEXT: movl %eax, (%ecx) +; LINUX-32-PIC: movl xsrc, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl ptr, [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], ([[ECX]]) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: fxo02: -; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl (%rax), %eax -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq (%rcx), %rcx -; LINUX-64-PIC-NEXT: movl %eax, (%rcx) +; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _fxo02: -; DARWIN-32-STATIC: movl _xsrc, %eax -; DARWIN-32-STATIC-NEXT: movl _ptr, %ecx -; DARWIN-32-STATIC-NEXT: movl %eax, (%ecx) +; DARWIN-32-STATIC: movl _xsrc, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _ptr, [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], ([[ECX]]) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _fxo02: -; DARWIN-32-DYNAMIC: movl L_xsrc$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: movl (%eax), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx) +; DARWIN-32-DYNAMIC: movl L_xsrc$non_lazy_ptr, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[ECX]]), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], ([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _fxo02: ; DARWIN-32-PIC: calll L5$pb ; DARWIN-32-PIC-NEXT: L5$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L5$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L5$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl (%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L5$pb([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl ([[ECX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L5$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl ([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], ([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _fxo02: -; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl (%rax), %eax -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx) +; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], ([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _fxo02: -; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl (%rax), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx) +; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], ([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _fxo02: -; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movl (%rax), %eax -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, (%rcx) +; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], ([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -465,58 +476,58 @@ entry: store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 0), align 32 ret void ; LINUX-64-STATIC: foo03: -; LINUX-64-STATIC: movl dsrc(%rip), %eax -; LINUX-64-STATIC: movl %eax, ddst +; LINUX-64-STATIC: movl dsrc(%rip), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], ddst ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: foo03: -; LINUX-32-STATIC: movl dsrc, %eax -; LINUX-32-STATIC-NEXT: movl %eax, ddst +; LINUX-32-STATIC: movl dsrc, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], ddst ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: foo03: -; LINUX-32-PIC: movl dsrc, %eax -; LINUX-32-PIC-NEXT: movl %eax, ddst +; LINUX-32-PIC: movl dsrc, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], ddst ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: foo03: -; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl (%rax), %eax -; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, (%rcx) +; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _foo03: -; DARWIN-32-STATIC: movl _dsrc, %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _ddst +; DARWIN-32-STATIC: movl _dsrc, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _ddst ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _foo03: -; DARWIN-32-DYNAMIC: movl _dsrc, %eax -; DARWIN-32-DYNAMIC-NEXT: movl %eax, _ddst +; DARWIN-32-DYNAMIC: movl _dsrc, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], _ddst ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo03: ; DARWIN-32-PIC: calll L6$pb ; DARWIN-32-PIC-NEXT: L6$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _dsrc-L6$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _ddst-L6$pb(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _dsrc-L6$pb([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], _ddst-L6$pb([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo03: -; DARWIN-64-STATIC: movl _dsrc(%rip), %eax -; DARWIN-64-STATIC-NEXT: movl %eax, _ddst(%rip) +; DARWIN-64-STATIC: movl _dsrc(%rip), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], _ddst(%rip) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _foo03: -; DARWIN-64-DYNAMIC: movl _dsrc(%rip), %eax -; DARWIN-64-DYNAMIC-NEXT: movl %eax, _ddst(%rip) +; DARWIN-64-DYNAMIC: movl _dsrc(%rip), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], _ddst(%rip) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _foo03: -; DARWIN-64-PIC: movl _dsrc(%rip), %eax -; DARWIN-64-PIC-NEXT: movl %eax, _ddst(%rip) +; DARWIN-64-PIC: movl _dsrc(%rip), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], _ddst(%rip) ; DARWIN-64-PIC-NEXT: ret } @@ -537,9 +548,9 @@ entry: ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: foo04: -; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq %rax, (%rcx) +; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _foo04: @@ -553,24 +564,24 @@ entry: ; DARWIN-32-PIC: _foo04: ; DARWIN-32-PIC: calll L7$pb ; DARWIN-32-PIC-NEXT: L7$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ddst-L7$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L7$pb(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal _ddst-L7$pb([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], _dptr-L7$pb([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo04: -; DARWIN-64-STATIC: leaq _ddst(%rip), %rax -; DARWIN-64-STATIC-NEXT: movq %rax, _dptr(%rip) +; DARWIN-64-STATIC: leaq _ddst(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq [[RAX]], _dptr(%rip) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _foo04: -; DARWIN-64-DYNAMIC: leaq _ddst(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movq %rax, _dptr(%rip) +; DARWIN-64-DYNAMIC: leaq _ddst(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq [[RAX]], _dptr(%rip) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _foo04: -; DARWIN-64-PIC: leaq _ddst(%rip), %rax -; DARWIN-64-PIC-NEXT: movq %rax, _dptr(%rip) +; DARWIN-64-PIC: leaq _ddst(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq [[RAX]], _dptr(%rip) ; DARWIN-64-PIC-NEXT: ret } @@ -587,62 +598,62 @@ entry: ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: foo05: -; LINUX-32-STATIC: movl dsrc, %eax -; LINUX-32-STATIC-NEXT: movl dptr, %ecx -; LINUX-32-STATIC-NEXT: movl %eax, (%ecx) +; LINUX-32-STATIC: movl dsrc, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl dptr, [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], ([[ECX]]) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: foo05: -; LINUX-32-PIC: movl dsrc, %eax -; LINUX-32-PIC-NEXT: movl dptr, %ecx -; LINUX-32-PIC-NEXT: movl %eax, (%ecx) +; LINUX-32-PIC: movl dsrc, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl dptr, [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], ([[ECX]]) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: foo05: -; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl (%rax), %eax -; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq (%rcx), %rcx -; LINUX-64-PIC-NEXT: movl %eax, (%rcx) +; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _foo05: -; DARWIN-32-STATIC: movl _dsrc, %eax -; DARWIN-32-STATIC-NEXT: movl _dptr, %ecx -; DARWIN-32-STATIC-NEXT: movl %eax, (%ecx) +; DARWIN-32-STATIC: movl _dsrc, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _dptr, [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], ([[ECX]]) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _foo05: -; DARWIN-32-DYNAMIC: movl _dsrc, %eax -; DARWIN-32-DYNAMIC-NEXT: movl _dptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx) +; DARWIN-32-DYNAMIC: movl _dsrc, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _dptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], ([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo05: ; DARWIN-32-PIC: calll L8$pb ; DARWIN-32-PIC-NEXT: L8$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _dsrc-L8$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _dptr-L8$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _dsrc-L8$pb([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _dptr-L8$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], ([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo05: -; DARWIN-64-STATIC: movl _dsrc(%rip), %eax -; DARWIN-64-STATIC-NEXT: movq _dptr(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx) +; DARWIN-64-STATIC: movl _dsrc(%rip), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _dptr(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], ([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _foo05: -; DARWIN-64-DYNAMIC: movl _dsrc(%rip), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _dptr(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx) +; DARWIN-64-DYNAMIC: movl _dsrc(%rip), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _dptr(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], ([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _foo05: -; DARWIN-64-PIC: movl _dsrc(%rip), %eax -; DARWIN-64-PIC-NEXT: movq _dptr(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, (%rcx) +; DARWIN-64-PIC: movl _dsrc(%rip), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _dptr(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], ([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -652,56 +663,56 @@ entry: store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 0), align 4 ret void ; LINUX-64-STATIC: foo06: -; LINUX-64-STATIC: movl lsrc(%rip), %eax -; LINUX-64-STATIC: movl %eax, ldst(%rip) +; LINUX-64-STATIC: movl lsrc(%rip), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], ldst(%rip) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: foo06: -; LINUX-32-STATIC: movl lsrc, %eax -; LINUX-32-STATIC-NEXT: movl %eax, ldst +; LINUX-32-STATIC: movl lsrc, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], ldst ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: foo06: -; LINUX-32-PIC: movl lsrc, %eax -; LINUX-32-PIC-NEXT: movl %eax, ldst +; LINUX-32-PIC: movl lsrc, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], ldst ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: foo06: -; LINUX-64-PIC: movl lsrc(%rip), %eax -; LINUX-64-PIC-NEXT: movl %eax, ldst(%rip) +; LINUX-64-PIC: movl lsrc(%rip), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], ldst(%rip) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _foo06: -; DARWIN-32-STATIC: movl _lsrc, %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _ldst +; DARWIN-32-STATIC: movl _lsrc, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _ldst ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _foo06: -; DARWIN-32-DYNAMIC: movl _lsrc, %eax -; DARWIN-32-DYNAMIC-NEXT: movl %eax, _ldst +; DARWIN-32-DYNAMIC: movl _lsrc, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], _ldst ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo06: ; DARWIN-32-PIC: calll L9$pb ; DARWIN-32-PIC-NEXT: L9$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _lsrc-L9$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _ldst-L9$pb(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _lsrc-L9$pb([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], _ldst-L9$pb([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo06: -; DARWIN-64-STATIC: movl _lsrc(%rip), %eax -; DARWIN-64-STATIC-NEXT: movl %eax, _ldst(%rip) +; DARWIN-64-STATIC: movl _lsrc(%rip), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], _ldst(%rip) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _foo06: -; DARWIN-64-DYNAMIC: movl _lsrc(%rip), %eax -; DARWIN-64-DYNAMIC-NEXT: movl %eax, _ldst(%rip) +; DARWIN-64-DYNAMIC: movl _lsrc(%rip), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], _ldst(%rip) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _foo06: -; DARWIN-64-PIC: movl _lsrc(%rip), %eax -; DARWIN-64-PIC-NEXT: movl %eax, _ldst(%rip) +; DARWIN-64-PIC: movl _lsrc(%rip), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], _ldst(%rip) ; DARWIN-64-PIC-NEXT: ret } @@ -722,8 +733,8 @@ entry: ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: foo07: -; LINUX-64-PIC: leaq ldst(%rip), %rax -; LINUX-64-PIC-NEXT: movq %rax, lptr(%rip) +; LINUX-64-PIC: leaq ldst(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq [[RAX]], lptr(%rip) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _foo07: @@ -737,24 +748,24 @@ entry: ; DARWIN-32-PIC: _foo07: ; DARWIN-32-PIC: calll L10$pb ; DARWIN-32-PIC-NEXT: L10$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ldst-L10$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L10$pb(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal _ldst-L10$pb([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], _lptr-L10$pb([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo07: -; DARWIN-64-STATIC: leaq _ldst(%rip), %rax -; DARWIN-64-STATIC-NEXT: movq %rax, _lptr(%rip) +; DARWIN-64-STATIC: leaq _ldst(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq [[RAX]], _lptr(%rip) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _foo07: -; DARWIN-64-DYNAMIC: leaq _ldst(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movq %rax, _lptr(%rip) +; DARWIN-64-DYNAMIC: leaq _ldst(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq [[RAX]], _lptr(%rip) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _foo07: -; DARWIN-64-PIC: leaq _ldst(%rip), %rax -; DARWIN-64-PIC-NEXT: movq %rax, _lptr(%rip) +; DARWIN-64-PIC: leaq _ldst(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq [[RAX]], _lptr(%rip) ; DARWIN-64-PIC-NEXT: ret } @@ -771,60 +782,60 @@ entry: ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: foo08: -; LINUX-32-STATIC: movl lsrc, %eax -; LINUX-32-STATIC-NEXT: movl lptr, %ecx -; LINUX-32-STATIC-NEXT: movl %eax, (%ecx) +; LINUX-32-STATIC: movl lsrc, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl lptr, [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], ([[ECX]]) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: foo08: -; LINUX-32-PIC: movl lsrc, %eax -; LINUX-32-PIC-NEXT: movl lptr, %ecx -; LINUX-32-PIC-NEXT: movl %eax, (%ecx) +; LINUX-32-PIC: movl lsrc, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl lptr, [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], ([[ECX]]) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: foo08: -; LINUX-64-PIC: movl lsrc(%rip), %eax -; LINUX-64-PIC-NEXT: movq lptr(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, (%rcx) +; LINUX-64-PIC: movl lsrc(%rip), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq lptr(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _foo08: -; DARWIN-32-STATIC: movl _lsrc, %eax -; DARWIN-32-STATIC-NEXT: movl _lptr, %ecx -; DARWIN-32-STATIC-NEXT: movl %eax, (%ecx) +; DARWIN-32-STATIC: movl _lsrc, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _lptr, [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], ([[ECX]]) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _foo08: -; DARWIN-32-DYNAMIC: movl _lsrc, %eax -; DARWIN-32-DYNAMIC-NEXT: movl _lptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx) +; DARWIN-32-DYNAMIC: movl _lsrc, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _lptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], ([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _foo08: ; DARWIN-32-PIC: calll L11$pb ; DARWIN-32-PIC-NEXT: L11$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _lsrc-L11$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _lptr-L11$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _lsrc-L11$pb([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _lptr-L11$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], ([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _foo08: -; DARWIN-64-STATIC: movl _lsrc(%rip), %eax -; DARWIN-64-STATIC-NEXT: movq _lptr(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx) +; DARWIN-64-STATIC: movl _lsrc(%rip), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _lptr(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], ([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _foo08: -; DARWIN-64-DYNAMIC: movl _lsrc(%rip), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _lptr(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx) +; DARWIN-64-DYNAMIC: movl _lsrc(%rip), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _lptr(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], ([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _foo08: -; DARWIN-64-PIC: movl _lsrc(%rip), %eax -; DARWIN-64-PIC-NEXT: movq _lptr(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, (%rcx) +; DARWIN-64-PIC: movl _lsrc(%rip), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _lptr(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], ([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -834,68 +845,68 @@ entry: store i32 %0, i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 16), align 4 ret void ; LINUX-64-STATIC: qux00: -; LINUX-64-STATIC: movl src+64(%rip), %eax -; LINUX-64-STATIC: movl %eax, dst+64(%rip) +; LINUX-64-STATIC: movl src+64(%rip), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], dst+64(%rip) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: qux00: -; LINUX-32-STATIC: movl src+64, %eax -; LINUX-32-STATIC-NEXT: movl %eax, dst+64 +; LINUX-32-STATIC: movl src+64, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], dst+64 ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: qux00: -; LINUX-32-PIC: movl src+64, %eax -; LINUX-32-PIC-NEXT: movl %eax, dst+64 +; LINUX-32-PIC: movl src+64, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], dst+64 ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: qux00: -; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl 64(%rax), %eax -; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx) +; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 64([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _qux00: -; DARWIN-32-STATIC: movl _src+64, %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _dst+64 +; DARWIN-32-STATIC: movl _src+64, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _dst+64 ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _qux00: -; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: movl 64(%eax), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, 64(%ecx) +; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl 64([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], 64([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux00: ; DARWIN-32-PIC: calll L12$pb ; DARWIN-32-PIC-NEXT: L12$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L12$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L12$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L12$pb([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 64([[ECX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L12$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], 64([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux00: -; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl 64(%rax), %eax -; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx) +; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 64([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _qux00: -; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx) +; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 64([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _qux00: -; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movl 64(%rax), %eax -; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx) +; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 64([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -905,68 +916,68 @@ entry: store i32 %0, i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 16), align 4 ret void ; LINUX-64-STATIC: qxx00: -; LINUX-64-STATIC: movl xsrc+64(%rip), %eax -; LINUX-64-STATIC: movl %eax, xdst+64(%rip) +; LINUX-64-STATIC: movl xsrc+64(%rip), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], xdst+64(%rip) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: qxx00: -; LINUX-32-STATIC: movl xsrc+64, %eax -; LINUX-32-STATIC-NEXT: movl %eax, xdst+64 +; LINUX-32-STATIC: movl xsrc+64, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], xdst+64 ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: qxx00: -; LINUX-32-PIC: movl xsrc+64, %eax -; LINUX-32-PIC-NEXT: movl %eax, xdst+64 +; LINUX-32-PIC: movl xsrc+64, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], xdst+64 ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: qxx00: -; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl 64(%rax), %eax -; LINUX-64-PIC-NEXT: movq xdst@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx) +; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq xdst@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 64([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _qxx00: -; DARWIN-32-STATIC: movl _xsrc+64, %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _xdst+64 +; DARWIN-32-STATIC: movl _xsrc+64, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _xdst+64 ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _qxx00: -; DARWIN-32-DYNAMIC: movl L_xsrc$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: movl 64(%eax), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, 64(%ecx) +; DARWIN-32-DYNAMIC: movl L_xsrc$non_lazy_ptr, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl 64([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], 64([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qxx00: ; DARWIN-32-PIC: calll L13$pb ; DARWIN-32-PIC-NEXT: L13$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L13$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L13$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L13$pb([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 64([[ECX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L13$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], 64([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qxx00: -; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl 64(%rax), %eax -; DARWIN-64-STATIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx) +; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _xdst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 64([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _qxx00: -; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx) +; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _xdst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 64([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _qxx00: -; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movl 64(%rax), %eax -; DARWIN-64-PIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx) +; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _xdst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 64([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -987,10 +998,10 @@ entry: ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: qux01: -; LINUX-64-PIC: movq dst@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: addq $64, %rax -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq %rax, (%rcx) +; LINUX-64-PIC: movq dst@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: addq $64, [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _qux01: @@ -998,41 +1009,41 @@ entry: ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _qux01: -; DARWIN-32-DYNAMIC: movl L_dst$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: addl $64, %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx) +; DARWIN-32-DYNAMIC: movl L_dst$non_lazy_ptr, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: addl $64, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], ([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux01: ; DARWIN-32-PIC: calll L14$pb ; DARWIN-32-PIC-NEXT: L14$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L14$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: addl $64, %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L14$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L14$pb([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: addl $64, [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L14$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], ([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux01: -; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: addq $64, %rax -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: addq $64, [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _qux01: -; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: addq $64, %rax -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: addq $64, [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _qux01: -; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: addq $64, %rax -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: addq $64, [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -1053,10 +1064,10 @@ entry: ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: qxx01: -; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: addq $64, %rax -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq %rax, (%rcx) +; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: addq $64, [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _qxx01: @@ -1064,41 +1075,41 @@ entry: ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _qxx01: -; DARWIN-32-DYNAMIC: movl L_xdst$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: addl $64, %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx) +; DARWIN-32-DYNAMIC: movl L_xdst$non_lazy_ptr, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: addl $64, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], ([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qxx01: ; DARWIN-32-PIC: calll L15$pb ; DARWIN-32-PIC-NEXT: L15$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L15$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: addl $64, %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L15$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L15$pb([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: addl $64, [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L15$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], ([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qxx01: -; DARWIN-64-STATIC: movq _xdst@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: addq $64, %rax -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-STATIC: movq _xdst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: addq $64, [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _qxx01: -; DARWIN-64-DYNAMIC: movq _xdst@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: addq $64, %rax -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-DYNAMIC: movq _xdst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: addq $64, [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _qxx01: -; DARWIN-64-PIC: movq _xdst@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: addq $64, %rax -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-PIC: movq _xdst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: addq $64, [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -1109,79 +1120,79 @@ entry: %2 = getelementptr i32* %0, i64 16 store i32 %1, i32* %2, align 4 ; LINUX-64-STATIC: qux02: -; LINUX-64-STATIC: movl src+64(%rip), %eax -; LINUX-64-STATIC: movq ptr(%rip), %rcx -; LINUX-64-STATIC: movl %eax, 64(%rcx) +; LINUX-64-STATIC: movl src+64(%rip), [[EAX:%e.x]] +; LINUX-64-STATIC: movq ptr(%rip), [[RCX:%r.x]] +; LINUX-64-STATIC: movl [[EAX]], 64([[RCX]]) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: qux02: -; LINUX-32-STATIC: movl src+64, %eax -; LINUX-32-STATIC-NEXT: movl ptr, %ecx -; LINUX-32-STATIC-NEXT: movl %eax, 64(%ecx) +; LINUX-32-STATIC: movl src+64, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl ptr, [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], 64([[ECX]]) ; LINUX-32-STATIC-NEXT: ret ret void ; LINUX-32-PIC: qux02: -; LINUX-32-PIC: movl src+64, %eax -; LINUX-32-PIC-NEXT: movl ptr, %ecx -; LINUX-32-PIC-NEXT: movl %eax, 64(%ecx) +; LINUX-32-PIC: movl src+64, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl ptr, [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], 64([[ECX]]) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: qux02: -; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl 64(%rax), %eax -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq (%rcx), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx) +; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 64([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _qux02: -; DARWIN-32-STATIC: movl _src+64, %eax -; DARWIN-32-STATIC-NEXT: movl _ptr, %ecx -; DARWIN-32-STATIC-NEXT: movl %eax, 64(%ecx) +; DARWIN-32-STATIC: movl _src+64, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _ptr, [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], 64([[ECX]]) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _qux02: -; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: movl 64(%eax), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, 64(%ecx) +; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl 64([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[ECX]]), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], 64([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux02: ; DARWIN-32-PIC: calll L16$pb ; DARWIN-32-PIC-NEXT: L16$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L16$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L16$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl (%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L16$pb([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 64([[ECX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L16$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl ([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], 64([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux02: -; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl 64(%rax), %eax -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx) +; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 64([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _qux02: -; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx) +; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 64([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _qux02: -; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movl 64(%rax), %eax -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx) +; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 64([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -1192,79 +1203,79 @@ entry: %2 = getelementptr i32* %0, i64 16 store i32 %1, i32* %2, align 4 ; LINUX-64-STATIC: qxx02: -; LINUX-64-STATIC: movl xsrc+64(%rip), %eax -; LINUX-64-STATIC: movq ptr(%rip), %rcx -; LINUX-64-STATIC: movl %eax, 64(%rcx) +; LINUX-64-STATIC: movl xsrc+64(%rip), [[EAX:%e.x]] +; LINUX-64-STATIC: movq ptr(%rip), [[RCX:%r.x]] +; LINUX-64-STATIC: movl [[EAX]], 64([[RCX]]) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: qxx02: -; LINUX-32-STATIC: movl xsrc+64, %eax -; LINUX-32-STATIC-NEXT: movl ptr, %ecx -; LINUX-32-STATIC-NEXT: movl %eax, 64(%ecx) +; LINUX-32-STATIC: movl xsrc+64, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl ptr, [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], 64([[ECX]]) ; LINUX-32-STATIC-NEXT: ret ret void ; LINUX-32-PIC: qxx02: -; LINUX-32-PIC: movl xsrc+64, %eax -; LINUX-32-PIC-NEXT: movl ptr, %ecx -; LINUX-32-PIC-NEXT: movl %eax, 64(%ecx) +; LINUX-32-PIC: movl xsrc+64, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl ptr, [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], 64([[ECX]]) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: qxx02: -; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl 64(%rax), %eax -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq (%rcx), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx) +; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 64([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _qxx02: -; DARWIN-32-STATIC: movl _xsrc+64, %eax -; DARWIN-32-STATIC-NEXT: movl _ptr, %ecx -; DARWIN-32-STATIC-NEXT: movl %eax, 64(%ecx) +; DARWIN-32-STATIC: movl _xsrc+64, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _ptr, [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], 64([[ECX]]) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _qxx02: -; DARWIN-32-DYNAMIC: movl L_xsrc$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: movl 64(%eax), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, 64(%ecx) +; DARWIN-32-DYNAMIC: movl L_xsrc$non_lazy_ptr, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl 64([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[ECX]]), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], 64([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qxx02: ; DARWIN-32-PIC: calll L17$pb ; DARWIN-32-PIC-NEXT: L17$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L17$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl 64(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L17$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl (%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L17$pb([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 64([[ECX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L17$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl ([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], 64([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qxx02: -; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl 64(%rax), %eax -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx) +; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 64([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _qxx02: -; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx) +; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 64([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _qxx02: -; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movl 64(%rax), %eax -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx) +; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 64([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -1274,58 +1285,58 @@ entry: store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 16), align 32 ret void ; LINUX-64-STATIC: qux03: -; LINUX-64-STATIC: movl dsrc+64(%rip), %eax -; LINUX-64-STATIC: movl %eax, ddst+64(%rip) +; LINUX-64-STATIC: movl dsrc+64(%rip), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], ddst+64(%rip) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: qux03: -; LINUX-32-STATIC: movl dsrc+64, %eax -; LINUX-32-STATIC-NEXT: movl %eax, ddst+64 +; LINUX-32-STATIC: movl dsrc+64, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], ddst+64 ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: qux03: -; LINUX-32-PIC: movl dsrc+64, %eax -; LINUX-32-PIC-NEXT: movl %eax, ddst+64 +; LINUX-32-PIC: movl dsrc+64, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], ddst+64 ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: qux03: -; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl 64(%rax), %eax -; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx) +; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 64([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _qux03: -; DARWIN-32-STATIC: movl _dsrc+64, %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _ddst+64 +; DARWIN-32-STATIC: movl _dsrc+64, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _ddst+64 ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _qux03: -; DARWIN-32-DYNAMIC: movl _dsrc+64, %eax -; DARWIN-32-DYNAMIC-NEXT: movl %eax, _ddst+64 +; DARWIN-32-DYNAMIC: movl _dsrc+64, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], _ddst+64 ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux03: ; DARWIN-32-PIC: calll L18$pb ; DARWIN-32-PIC-NEXT: L18$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_dsrc-L18$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, (_ddst-L18$pb)+64(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl (_dsrc-L18$pb)+64([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], (_ddst-L18$pb)+64([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux03: -; DARWIN-64-STATIC: movl _dsrc+64(%rip), %eax -; DARWIN-64-STATIC-NEXT: movl %eax, _ddst+64(%rip) +; DARWIN-64-STATIC: movl _dsrc+64(%rip), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], _ddst+64(%rip) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _qux03: -; DARWIN-64-DYNAMIC: movl _dsrc+64(%rip), %eax -; DARWIN-64-DYNAMIC-NEXT: movl %eax, _ddst+64(%rip) +; DARWIN-64-DYNAMIC: movl _dsrc+64(%rip), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], _ddst+64(%rip) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _qux03: -; DARWIN-64-PIC: movl _dsrc+64(%rip), %eax -; DARWIN-64-PIC-NEXT: movl %eax, _ddst+64(%rip) +; DARWIN-64-PIC: movl _dsrc+64(%rip), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], _ddst+64(%rip) ; DARWIN-64-PIC-NEXT: ret } @@ -1346,10 +1357,10 @@ entry: ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: qux04: -; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: addq $64, %rax -; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq %rax, (%rcx) +; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: addq $64, [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _qux04: @@ -1363,24 +1374,24 @@ entry: ; DARWIN-32-PIC: _qux04: ; DARWIN-32-PIC: calll L19$pb ; DARWIN-32-PIC-NEXT: L19$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ddst-L19$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L19$pb(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_ddst-L19$pb)+64([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], _dptr-L19$pb([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux04: -; DARWIN-64-STATIC: leaq _ddst+64(%rip), %rax -; DARWIN-64-STATIC-NEXT: movq %rax, _dptr(%rip) +; DARWIN-64-STATIC: leaq _ddst+64(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq [[RAX]], _dptr(%rip) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _qux04: -; DARWIN-64-DYNAMIC: leaq _ddst+64(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movq %rax, _dptr(%rip) +; DARWIN-64-DYNAMIC: leaq _ddst+64(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq [[RAX]], _dptr(%rip) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _qux04: -; DARWIN-64-PIC: leaq _ddst+64(%rip), %rax -; DARWIN-64-PIC-NEXT: movq %rax, _dptr(%rip) +; DARWIN-64-PIC: leaq _ddst+64(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq [[RAX]], _dptr(%rip) ; DARWIN-64-PIC-NEXT: ret } @@ -1391,69 +1402,69 @@ entry: %2 = getelementptr i32* %0, i64 16 store i32 %1, i32* %2, align 4 ; LINUX-64-STATIC: qux05: -; LINUX-64-STATIC: movl dsrc+64(%rip), %eax -; LINUX-64-STATIC: movq dptr(%rip), %rcx -; LINUX-64-STATIC: movl %eax, 64(%rcx) +; LINUX-64-STATIC: movl dsrc+64(%rip), [[EAX:%e.x]] +; LINUX-64-STATIC: movq dptr(%rip), [[RCX:%r.x]] +; LINUX-64-STATIC: movl [[EAX]], 64([[RCX]]) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: qux05: -; LINUX-32-STATIC: movl dsrc+64, %eax -; LINUX-32-STATIC-NEXT: movl dptr, %ecx -; LINUX-32-STATIC-NEXT: movl %eax, 64(%ecx) +; LINUX-32-STATIC: movl dsrc+64, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl dptr, [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], 64([[ECX]]) ; LINUX-32-STATIC-NEXT: ret ret void ; LINUX-32-PIC: qux05: -; LINUX-32-PIC: movl dsrc+64, %eax -; LINUX-32-PIC-NEXT: movl dptr, %ecx -; LINUX-32-PIC-NEXT: movl %eax, 64(%ecx) +; LINUX-32-PIC: movl dsrc+64, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl dptr, [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], 64([[ECX]]) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: qux05: -; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl 64(%rax), %eax -; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq (%rcx), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx) +; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 64([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _qux05: -; DARWIN-32-STATIC: movl _dsrc+64, %eax -; DARWIN-32-STATIC-NEXT: movl _dptr, %ecx -; DARWIN-32-STATIC-NEXT: movl %eax, 64(%ecx) +; DARWIN-32-STATIC: movl _dsrc+64, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _dptr, [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], 64([[ECX]]) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _qux05: -; DARWIN-32-DYNAMIC: movl _dsrc+64, %eax -; DARWIN-32-DYNAMIC-NEXT: movl _dptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, 64(%ecx) +; DARWIN-32-DYNAMIC: movl _dsrc+64, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _dptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], 64([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux05: ; DARWIN-32-PIC: calll L20$pb ; DARWIN-32-PIC-NEXT: L20$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_dsrc-L20$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _dptr-L20$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl (_dsrc-L20$pb)+64([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _dptr-L20$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], 64([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux05: -; DARWIN-64-STATIC: movl _dsrc+64(%rip), %eax -; DARWIN-64-STATIC-NEXT: movq _dptr(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx) +; DARWIN-64-STATIC: movl _dsrc+64(%rip), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _dptr(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 64([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _qux05: -; DARWIN-64-DYNAMIC: movl _dsrc+64(%rip), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _dptr(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx) +; DARWIN-64-DYNAMIC: movl _dsrc+64(%rip), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _dptr(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 64([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _qux05: -; DARWIN-64-PIC: movl _dsrc+64(%rip), %eax -; DARWIN-64-PIC-NEXT: movq _dptr(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx) +; DARWIN-64-PIC: movl _dsrc+64(%rip), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _dptr(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 64([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -1463,56 +1474,56 @@ entry: store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 16), align 4 ret void ; LINUX-64-STATIC: qux06: -; LINUX-64-STATIC: movl lsrc+64(%rip), %eax -; LINUX-64-STATIC: movl %eax, ldst+64 +; LINUX-64-STATIC: movl lsrc+64(%rip), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], ldst+64 ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: qux06: -; LINUX-32-STATIC: movl lsrc+64, %eax -; LINUX-32-STATIC-NEXT: movl %eax, ldst+64 +; LINUX-32-STATIC: movl lsrc+64, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], ldst+64 ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: qux06: -; LINUX-32-PIC: movl lsrc+64, %eax -; LINUX-32-PIC-NEXT: movl %eax, ldst+64 +; LINUX-32-PIC: movl lsrc+64, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], ldst+64 ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: qux06: -; LINUX-64-PIC: movl lsrc+64(%rip), %eax -; LINUX-64-PIC-NEXT: movl %eax, ldst+64(%rip) +; LINUX-64-PIC: movl lsrc+64(%rip), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], ldst+64(%rip) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _qux06: -; DARWIN-32-STATIC: movl _lsrc+64, %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _ldst+64 +; DARWIN-32-STATIC: movl _lsrc+64, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _ldst+64 ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _qux06: -; DARWIN-32-DYNAMIC: movl _lsrc+64, %eax -; DARWIN-32-DYNAMIC-NEXT: movl %eax, _ldst+64 +; DARWIN-32-DYNAMIC: movl _lsrc+64, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], _ldst+64 ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux06: ; DARWIN-32-PIC: calll L21$pb ; DARWIN-32-PIC-NEXT: L21$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_lsrc-L21$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, (_ldst-L21$pb)+64(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl (_lsrc-L21$pb)+64([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], (_ldst-L21$pb)+64([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux06: -; DARWIN-64-STATIC: movl _lsrc+64(%rip), %eax -; DARWIN-64-STATIC-NEXT: movl %eax, _ldst+64(%rip) +; DARWIN-64-STATIC: movl _lsrc+64(%rip), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], _ldst+64(%rip) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _qux06: -; DARWIN-64-DYNAMIC: movl _lsrc+64(%rip), %eax -; DARWIN-64-DYNAMIC-NEXT: movl %eax, _ldst+64(%rip) +; DARWIN-64-DYNAMIC: movl _lsrc+64(%rip), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], _ldst+64(%rip) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _qux06: -; DARWIN-64-PIC: movl _lsrc+64(%rip), %eax -; DARWIN-64-PIC-NEXT: movl %eax, _ldst+64(%rip) +; DARWIN-64-PIC: movl _lsrc+64(%rip), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], _ldst+64(%rip) ; DARWIN-64-PIC-NEXT: ret } @@ -1533,8 +1544,8 @@ entry: ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: qux07: -; LINUX-64-PIC: leaq ldst+64(%rip), %rax -; LINUX-64-PIC-NEXT: movq %rax, lptr(%rip) +; LINUX-64-PIC: leaq ldst+64(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq [[RAX]], lptr(%rip) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _qux07: @@ -1548,24 +1559,24 @@ entry: ; DARWIN-32-PIC: _qux07: ; DARWIN-32-PIC: calll L22$pb ; DARWIN-32-PIC-NEXT: L22$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ldst-L22$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L22$pb(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_ldst-L22$pb)+64([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], _lptr-L22$pb([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux07: -; DARWIN-64-STATIC: leaq _ldst+64(%rip), %rax -; DARWIN-64-STATIC-NEXT: movq %rax, _lptr(%rip) +; DARWIN-64-STATIC: leaq _ldst+64(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq [[RAX]], _lptr(%rip) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _qux07: -; DARWIN-64-DYNAMIC: leaq _ldst+64(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movq %rax, _lptr(%rip) +; DARWIN-64-DYNAMIC: leaq _ldst+64(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq [[RAX]], _lptr(%rip) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _qux07: -; DARWIN-64-PIC: leaq _ldst+64(%rip), %rax -; DARWIN-64-PIC-NEXT: movq %rax, _lptr(%rip) +; DARWIN-64-PIC: leaq _ldst+64(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq [[RAX]], _lptr(%rip) ; DARWIN-64-PIC-NEXT: ret } @@ -1576,67 +1587,67 @@ entry: %2 = getelementptr i32* %0, i64 16 store i32 %1, i32* %2, align 4 ; LINUX-64-STATIC: qux08: -; LINUX-64-STATIC: movl lsrc+64(%rip), %eax -; LINUX-64-STATIC: movq lptr(%rip), %rcx -; LINUX-64-STATIC: movl %eax, 64(%rcx) +; LINUX-64-STATIC: movl lsrc+64(%rip), [[EAX:%e.x]] +; LINUX-64-STATIC: movq lptr(%rip), [[RCX:%r.x]] +; LINUX-64-STATIC: movl [[EAX]], 64([[RCX]]) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: qux08: -; LINUX-32-STATIC: movl lsrc+64, %eax -; LINUX-32-STATIC-NEXT: movl lptr, %ecx -; LINUX-32-STATIC-NEXT: movl %eax, 64(%ecx) +; LINUX-32-STATIC: movl lsrc+64, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl lptr, [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], 64([[ECX]]) ; LINUX-32-STATIC-NEXT: ret ret void ; LINUX-32-PIC: qux08: -; LINUX-32-PIC: movl lsrc+64, %eax -; LINUX-32-PIC-NEXT: movl lptr, %ecx -; LINUX-32-PIC-NEXT: movl %eax, 64(%ecx) +; LINUX-32-PIC: movl lsrc+64, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl lptr, [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], 64([[ECX]]) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: qux08: -; LINUX-64-PIC: movl lsrc+64(%rip), %eax -; LINUX-64-PIC-NEXT: movq lptr(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx) +; LINUX-64-PIC: movl lsrc+64(%rip), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq lptr(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 64([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _qux08: -; DARWIN-32-STATIC: movl _lsrc+64, %eax -; DARWIN-32-STATIC-NEXT: movl _lptr, %ecx -; DARWIN-32-STATIC-NEXT: movl %eax, 64(%ecx) +; DARWIN-32-STATIC: movl _lsrc+64, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _lptr, [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], 64([[ECX]]) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _qux08: -; DARWIN-32-DYNAMIC: movl _lsrc+64, %eax -; DARWIN-32-DYNAMIC-NEXT: movl _lptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, 64(%ecx) +; DARWIN-32-DYNAMIC: movl _lsrc+64, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _lptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], 64([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _qux08: ; DARWIN-32-PIC: calll L23$pb ; DARWIN-32-PIC-NEXT: L23$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_lsrc-L23$pb)+64(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _lptr-L23$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, 64(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl (_lsrc-L23$pb)+64([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _lptr-L23$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], 64([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _qux08: -; DARWIN-64-STATIC: movl _lsrc+64(%rip), %eax -; DARWIN-64-STATIC-NEXT: movq _lptr(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx) +; DARWIN-64-STATIC: movl _lsrc+64(%rip), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _lptr(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 64([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _qux08: -; DARWIN-64-DYNAMIC: movl _lsrc+64(%rip), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _lptr(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx) +; DARWIN-64-DYNAMIC: movl _lsrc+64(%rip), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _lptr(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 64([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _qux08: -; DARWIN-64-PIC: movl _lsrc+64(%rip), %eax -; DARWIN-64-PIC-NEXT: movq _lptr(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx) +; DARWIN-64-PIC: movl _lsrc+64(%rip), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _lptr(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 64([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -1648,73 +1659,73 @@ entry: store i32 %1, i32* %2, align 4 ret void ; LINUX-64-STATIC: ind00: -; LINUX-64-STATIC: movl src(,%rdi,4), %eax -; LINUX-64-STATIC: movl %eax, dst(,%rdi,4) +; LINUX-64-STATIC: movl src(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], dst(,%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: ind00: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl src(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl %ecx, dst(,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl src(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], dst(,[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: ind00: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl src(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl %ecx, dst(,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl src(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], dst(,[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: ind00: -; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl (%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4) +; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _ind00: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _src(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl %ecx, _dst(,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _src(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], _dst(,[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _ind00: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl (%ecx,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, %edx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, (%edx,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[ECX]],[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind00: ; DARWIN-32-PIC: calll L24$pb ; DARWIN-32-PIC-NEXT: L24$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L24$pb(%eax), %edx -; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L24$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L24$pb([[EAX]]), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl ([[EDX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L24$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], ([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind00: -; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _ind00: -; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _ind00: -; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -1726,73 +1737,73 @@ entry: store i32 %1, i32* %2, align 4 ret void ; LINUX-64-STATIC: ixd00: -; LINUX-64-STATIC: movl xsrc(,%rdi,4), %eax -; LINUX-64-STATIC: movl %eax, xdst(,%rdi,4) +; LINUX-64-STATIC: movl xsrc(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], xdst(,%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: ixd00: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl xsrc(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl %ecx, xdst(,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl xsrc(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], xdst(,[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: ixd00: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl xsrc(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl %ecx, xdst(,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl xsrc(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], xdst(,[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: ixd00: -; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl (%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: movq xdst@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4) +; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq xdst@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _ixd00: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _xsrc(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl %ecx, _xdst(,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _xsrc(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], _xdst(,[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _ixd00: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_xsrc$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl (%ecx,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, %edx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, (%edx,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_xsrc$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[ECX]],[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ixd00: ; DARWIN-32-PIC: calll L25$pb ; DARWIN-32-PIC-NEXT: L25$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L25$pb(%eax), %edx -; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L25$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L25$pb([[EAX]]), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl ([[EDX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L25$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], ([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ixd00: -; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _xdst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _ixd00: -; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _xdst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _ixd00: -; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _xdst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -1802,73 +1813,73 @@ entry: store i32* %0, i32** @ptr, align 8 ret void ; LINUX-64-STATIC: ind01: -; LINUX-64-STATIC: leaq dst(,%rdi,4), %rax -; LINUX-64-STATIC: movq %rax, ptr +; LINUX-64-STATIC: leaq dst(,%rdi,4), [[RAX:%r.x]] +; LINUX-64-STATIC: movq [[RAX]], ptr ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: ind01: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal dst(,%eax,4), %eax -; LINUX-32-STATIC-NEXT: movl %eax, ptr +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal dst(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], ptr ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: ind01: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal dst(,%eax,4), %eax -; LINUX-32-PIC-NEXT: movl %eax, ptr +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal dst(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], ptr ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: ind01: ; LINUX-64-PIC: shlq $2, %rdi ; LINUX-64-PIC-NEXT: addq dst@GOTPCREL(%rip), %rdi -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movq %rdi, (%rax) +; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq %rdi, ([[RAX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _ind01: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _dst(,%eax,4), %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _ptr +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _dst(,[[EAX]],4), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _ptr ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _ind01: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: shll $2, %eax -; DARWIN-32-DYNAMIC-NEXT: addl L_dst$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: shll $2, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: addl L_dst$non_lazy_ptr, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], ([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind01: ; DARWIN-32-PIC: calll L26$pb ; DARWIN-32-PIC-NEXT: L26$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: shll $2, %ecx -; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L26$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L26$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: shll $2, [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L26$pb([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L26$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], ([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind01: ; DARWIN-64-STATIC: shlq $2, %rdi ; DARWIN-64-STATIC-NEXT: addq _dst@GOTPCREL(%rip), %rdi -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movq %rdi, (%rax) +; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq %rdi, ([[RAX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _ind01: ; DARWIN-64-DYNAMIC: shlq $2, %rdi ; DARWIN-64-DYNAMIC-NEXT: addq _dst@GOTPCREL(%rip), %rdi -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movq %rdi, (%rax) +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq %rdi, ([[RAX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _ind01: ; DARWIN-64-PIC: shlq $2, %rdi ; DARWIN-64-PIC-NEXT: addq _dst@GOTPCREL(%rip), %rdi -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movq %rdi, (%rax) +; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq %rdi, ([[RAX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -1878,73 +1889,73 @@ entry: store i32* %0, i32** @ptr, align 8 ret void ; LINUX-64-STATIC: ixd01: -; LINUX-64-STATIC: leaq xdst(,%rdi,4), %rax -; LINUX-64-STATIC: movq %rax, ptr +; LINUX-64-STATIC: leaq xdst(,%rdi,4), [[RAX:%r.x]] +; LINUX-64-STATIC: movq [[RAX]], ptr ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: ixd01: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal xdst(,%eax,4), %eax -; LINUX-32-STATIC-NEXT: movl %eax, ptr +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal xdst(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], ptr ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: ixd01: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal xdst(,%eax,4), %eax -; LINUX-32-PIC-NEXT: movl %eax, ptr +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal xdst(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], ptr ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: ixd01: ; LINUX-64-PIC: shlq $2, %rdi ; LINUX-64-PIC-NEXT: addq xdst@GOTPCREL(%rip), %rdi -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movq %rdi, (%rax) +; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq %rdi, ([[RAX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _ixd01: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _xdst(,%eax,4), %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _ptr +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _xdst(,[[EAX]],4), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _ptr ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _ixd01: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: shll $2, %eax -; DARWIN-32-DYNAMIC-NEXT: addl L_xdst$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: shll $2, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: addl L_xdst$non_lazy_ptr, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], ([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ixd01: ; DARWIN-32-PIC: calll L27$pb ; DARWIN-32-PIC-NEXT: L27$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: shll $2, %ecx -; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-L27$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L27$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: shll $2, [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-L27$pb([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L27$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], ([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ixd01: ; DARWIN-64-STATIC: shlq $2, %rdi ; DARWIN-64-STATIC-NEXT: addq _xdst@GOTPCREL(%rip), %rdi -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movq %rdi, (%rax) +; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq %rdi, ([[RAX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _ixd01: ; DARWIN-64-DYNAMIC: shlq $2, %rdi ; DARWIN-64-DYNAMIC-NEXT: addq _xdst@GOTPCREL(%rip), %rdi -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movq %rdi, (%rax) +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq %rdi, ([[RAX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _ixd01: ; DARWIN-64-PIC: shlq $2, %rdi ; DARWIN-64-PIC-NEXT: addq _xdst@GOTPCREL(%rip), %rdi -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movq %rdi, (%rax) +; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq %rdi, ([[RAX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -1957,83 +1968,83 @@ entry: store i32 %2, i32* %3, align 4 ret void ; LINUX-64-STATIC: ind02: -; LINUX-64-STATIC: movl src(,%rdi,4), %eax -; LINUX-64-STATIC: movq ptr(%rip), %rcx -; LINUX-64-STATIC: movl %eax, (%rcx,%rdi,4) +; LINUX-64-STATIC: movl src(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movq ptr(%rip), [[RCX:%r.x]] +; LINUX-64-STATIC: movl [[EAX]], ([[RCX]],%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: ind02: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl src(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl ptr, %edx -; LINUX-32-STATIC-NEXT: movl %ecx, (%edx,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl src(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl ptr, [[EDX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: ind02: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl src(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl ptr, %edx -; LINUX-32-PIC-NEXT: movl %ecx, (%edx,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl src(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl ptr, [[EDX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: ind02: -; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl (%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq (%rcx), %rcx -; LINUX-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4) +; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _ind02: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _src(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl _ptr, %edx -; DARWIN-32-STATIC-NEXT: movl %ecx, (%edx,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _src(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _ptr, [[EDX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _ind02: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl (%ecx,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %edx -; DARWIN-32-DYNAMIC-NEXT: movl (%edx), %edx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, (%edx,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[ECX]],[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[EDX]]), [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind02: ; DARWIN-32-PIC: calll L28$pb ; DARWIN-32-PIC-NEXT: L28$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L28$pb(%eax), %edx -; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L28$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl (%eax), %eax -; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L28$pb([[EAX]]), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl ([[EDX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L28$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl ([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], ([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind02: -; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _ind02: -; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _ind02: -; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -2046,83 +2057,83 @@ entry: store i32 %2, i32* %3, align 4 ret void ; LINUX-64-STATIC: ixd02: -; LINUX-64-STATIC: movl xsrc(,%rdi,4), %eax -; LINUX-64-STATIC: movq ptr(%rip), %rcx -; LINUX-64-STATIC: movl %eax, (%rcx,%rdi,4) +; LINUX-64-STATIC: movl xsrc(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movq ptr(%rip), [[RCX:%r.x]] +; LINUX-64-STATIC: movl [[EAX]], ([[RCX]],%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: ixd02: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl xsrc(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl ptr, %edx -; LINUX-32-STATIC-NEXT: movl %ecx, (%edx,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl xsrc(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl ptr, [[EDX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: ixd02: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl xsrc(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl ptr, %edx -; LINUX-32-PIC-NEXT: movl %ecx, (%edx,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl xsrc(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl ptr, [[EDX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: ixd02: -; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl (%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq (%rcx), %rcx -; LINUX-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4) +; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _ixd02: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _xsrc(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl _ptr, %edx -; DARWIN-32-STATIC-NEXT: movl %ecx, (%edx,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _xsrc(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _ptr, [[EDX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _ixd02: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_xsrc$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl (%ecx,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %edx -; DARWIN-32-DYNAMIC-NEXT: movl (%edx), %edx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, (%edx,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_xsrc$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[ECX]],[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[EDX]]), [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ixd02: ; DARWIN-32-PIC: calll L29$pb ; DARWIN-32-PIC-NEXT: L29$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L29$pb(%eax), %edx -; DARWIN-32-PIC-NEXT: movl (%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L29$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl (%eax), %eax -; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L29$pb([[EAX]]), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl ([[EDX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L29$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl ([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], ([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ixd02: -; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _ixd02: -; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _ixd02: -; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -2134,69 +2145,69 @@ entry: store i32 %1, i32* %2, align 4 ret void ; LINUX-64-STATIC: ind03: -; LINUX-64-STATIC: movl dsrc(,%rdi,4), %eax -; LINUX-64-STATIC: movl %eax, ddst(,%rdi,4) +; LINUX-64-STATIC: movl dsrc(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], ddst(,%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: ind03: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl dsrc(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl %ecx, ddst(,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl dsrc(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], ddst(,[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: ind03: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl dsrc(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl %ecx, ddst(,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl dsrc(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], ddst(,[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: ind03: -; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl (%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4) +; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _ind03: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _dsrc(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl %ecx, _ddst(,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _dsrc(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], _ddst(,[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _ind03: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl _dsrc(,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, _ddst(,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _dsrc(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], _ddst(,[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind03: ; DARWIN-32-PIC: calll L30$pb ; DARWIN-32-PIC-NEXT: L30$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _dsrc-L30$pb(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, _ddst-L30$pb(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _dsrc-L30$pb([[EAX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], _ddst-L30$pb([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind03: -; DARWIN-64-STATIC: leaq _dsrc(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: leaq _ddst(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-STATIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: leaq _ddst(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _ind03: -; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: leaq _ddst(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq _ddst(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _ind03: -; DARWIN-64-PIC: leaq _dsrc(%rip), %rax -; DARWIN-64-PIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: leaq _ddst(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-PIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: leaq _ddst(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -2206,66 +2217,66 @@ entry: store i32* %0, i32** @dptr, align 8 ret void ; LINUX-64-STATIC: ind04: -; LINUX-64-STATIC: leaq ddst(,%rdi,4), %rax -; LINUX-64-STATIC: movq %rax, dptr +; LINUX-64-STATIC: leaq ddst(,%rdi,4), [[RAX:%r.x]] +; LINUX-64-STATIC: movq [[RAX]], dptr ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: ind04: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal ddst(,%eax,4), %eax -; LINUX-32-STATIC-NEXT: movl %eax, dptr +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal ddst(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], dptr ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: ind04: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal ddst(,%eax,4), %eax -; LINUX-32-PIC-NEXT: movl %eax, dptr +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal ddst(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], dptr ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: ind04: ; LINUX-64-PIC: shlq $2, %rdi ; LINUX-64-PIC-NEXT: addq ddst@GOTPCREL(%rip), %rdi -; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movq %rdi, (%rax) +; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq %rdi, ([[RAX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _ind04: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _ddst(,%eax,4), %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _dptr +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _ddst(,[[EAX]],4), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _dptr ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _ind04: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: leal _ddst(,%eax,4), %eax -; DARWIN-32-DYNAMIC-NEXT: movl %eax, _dptr +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal _ddst(,[[EAX]],4), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], _dptr ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind04: ; DARWIN-32-PIC: calll L31$pb ; DARWIN-32-PIC-NEXT: L31$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal _ddst-L31$pb(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L31$pb(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: leal _ddst-L31$pb([[EAX]],[[ECX]],4), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], _dptr-L31$pb([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind04: -; DARWIN-64-STATIC: leaq _ddst(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq (%rax,%rdi,4), %rax -; DARWIN-64-STATIC-NEXT: movq %rax, _dptr(%rip) +; DARWIN-64-STATIC: leaq _ddst(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq ([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq [[RAX]], _dptr(%rip) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _ind04: -; DARWIN-64-DYNAMIC: leaq _ddst(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq (%rax,%rdi,4), %rax -; DARWIN-64-DYNAMIC-NEXT: movq %rax, _dptr(%rip) +; DARWIN-64-DYNAMIC: leaq _ddst(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq ([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq [[RAX]], _dptr(%rip) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _ind04: -; DARWIN-64-PIC: leaq _ddst(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq (%rax,%rdi,4), %rax -; DARWIN-64-PIC-NEXT: movq %rax, _dptr(%rip) +; DARWIN-64-PIC: leaq _ddst(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq ([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq [[RAX]], _dptr(%rip) ; DARWIN-64-PIC-NEXT: ret } @@ -2278,76 +2289,76 @@ entry: store i32 %2, i32* %3, align 4 ret void ; LINUX-64-STATIC: ind05: -; LINUX-64-STATIC: movl dsrc(,%rdi,4), %eax -; LINUX-64-STATIC: movq dptr(%rip), %rcx -; LINUX-64-STATIC: movl %eax, (%rcx,%rdi,4) +; LINUX-64-STATIC: movl dsrc(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movq dptr(%rip), [[RCX:%r.x]] +; LINUX-64-STATIC: movl [[EAX]], ([[RCX]],%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: ind05: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl dsrc(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl dptr, %edx -; LINUX-32-STATIC-NEXT: movl %ecx, (%edx,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl dsrc(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl dptr, [[EDX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: ind05: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl dsrc(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl dptr, %edx -; LINUX-32-PIC-NEXT: movl %ecx, (%edx,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl dsrc(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl dptr, [[EDX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: ind05: -; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl (%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq (%rcx), %rcx -; LINUX-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4) +; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _ind05: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _dsrc(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl _dptr, %edx -; DARWIN-32-STATIC-NEXT: movl %ecx, (%edx,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _dsrc(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _dptr, [[EDX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _ind05: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl _dsrc(,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl _dptr, %edx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, (%edx,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _dsrc(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _dptr, [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind05: ; DARWIN-32-PIC: calll L32$pb ; DARWIN-32-PIC-NEXT: L32$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _dsrc-L32$pb(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _dptr-L32$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _dsrc-L32$pb([[EAX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _dptr-L32$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], ([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind05: -; DARWIN-64-STATIC: leaq _dsrc(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: movq _dptr(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-STATIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _dptr(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _ind05: -; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _dptr(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _dptr(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _ind05: -; DARWIN-64-PIC: leaq _dsrc(%rip), %rax -; DARWIN-64-PIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: movq _dptr(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-PIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _dptr(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -2359,69 +2370,69 @@ entry: store i32 %1, i32* %2, align 4 ret void ; LINUX-64-STATIC: ind06: -; LINUX-64-STATIC: movl lsrc(,%rdi,4), %eax -; LINUX-64-STATIC: movl %eax, ldst(,%rdi,4) +; LINUX-64-STATIC: movl lsrc(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], ldst(,%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: ind06: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl lsrc(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl %ecx, ldst(,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl lsrc(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], ldst(,[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: ind06: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl lsrc(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl %ecx, ldst(,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl lsrc(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], ldst(,[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: ind06: -; LINUX-64-PIC: leaq lsrc(%rip), %rax -; LINUX-64-PIC-NEXT: movl (%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: leaq ldst(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4) +; LINUX-64-PIC: leaq lsrc(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: leaq ldst(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _ind06: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _lsrc(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl %ecx, _ldst(,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _lsrc(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], _ldst(,[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _ind06: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl _lsrc(,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, _ldst(,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _lsrc(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], _ldst(,[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind06: ; DARWIN-32-PIC: calll L33$pb ; DARWIN-32-PIC-NEXT: L33$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _lsrc-L33$pb(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, _ldst-L33$pb(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _lsrc-L33$pb([[EAX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], _ldst-L33$pb([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind06: -; DARWIN-64-STATIC: leaq _lsrc(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: leaq _ldst(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-STATIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: leaq _ldst(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _ind06: -; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: leaq _ldst(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq _ldst(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _ind06: -; DARWIN-64-PIC: leaq _lsrc(%rip), %rax -; DARWIN-64-PIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: leaq _ldst(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-PIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: leaq _ldst(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -2431,65 +2442,65 @@ entry: store i32* %0, i32** @lptr, align 8 ret void ; LINUX-64-STATIC: ind07: -; LINUX-64-STATIC: leaq ldst(,%rdi,4), %rax -; LINUX-64-STATIC: movq %rax, lptr +; LINUX-64-STATIC: leaq ldst(,%rdi,4), [[RAX:%r.x]] +; LINUX-64-STATIC: movq [[RAX]], lptr ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: ind07: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal ldst(,%eax,4), %eax -; LINUX-32-STATIC-NEXT: movl %eax, lptr +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal ldst(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], lptr ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: ind07: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal ldst(,%eax,4), %eax -; LINUX-32-PIC-NEXT: movl %eax, lptr +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal ldst(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], lptr ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: ind07: -; LINUX-64-PIC: leaq ldst(%rip), %rax -; LINUX-64-PIC-NEXT: leaq (%rax,%rdi,4), %rax -; LINUX-64-PIC-NEXT: movq %rax, lptr(%rip) +; LINUX-64-PIC: leaq ldst(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq ([[RAX]],%rdi,4), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq [[RAX]], lptr(%rip) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _ind07: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _ldst(,%eax,4), %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _lptr +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _ldst(,[[EAX]],4), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _lptr ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _ind07: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: leal _ldst(,%eax,4), %eax -; DARWIN-32-DYNAMIC-NEXT: movl %eax, _lptr +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal _ldst(,[[EAX]],4), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], _lptr ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind07: ; DARWIN-32-PIC: calll L34$pb ; DARWIN-32-PIC-NEXT: L34$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal _ldst-L34$pb(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L34$pb(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: leal _ldst-L34$pb([[EAX]],[[ECX]],4), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], _lptr-L34$pb([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind07: -; DARWIN-64-STATIC: leaq _ldst(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq (%rax,%rdi,4), %rax -; DARWIN-64-STATIC-NEXT: movq %rax, _lptr(%rip) +; DARWIN-64-STATIC: leaq _ldst(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq ([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq [[RAX]], _lptr(%rip) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _ind07: -; DARWIN-64-DYNAMIC: leaq _ldst(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq (%rax,%rdi,4), %rax -; DARWIN-64-DYNAMIC-NEXT: movq %rax, _lptr(%rip) +; DARWIN-64-DYNAMIC: leaq _ldst(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq ([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq [[RAX]], _lptr(%rip) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _ind07: -; DARWIN-64-PIC: leaq _ldst(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq (%rax,%rdi,4), %rax -; DARWIN-64-PIC-NEXT: movq %rax, _lptr(%rip) +; DARWIN-64-PIC: leaq _ldst(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq ([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq [[RAX]], _lptr(%rip) ; DARWIN-64-PIC-NEXT: ret } @@ -2502,75 +2513,75 @@ entry: store i32 %2, i32* %3, align 4 ret void ; LINUX-64-STATIC: ind08: -; LINUX-64-STATIC: movl lsrc(,%rdi,4), %eax -; LINUX-64-STATIC: movq lptr(%rip), %rcx -; LINUX-64-STATIC: movl %eax, (%rcx,%rdi,4) +; LINUX-64-STATIC: movl lsrc(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movq lptr(%rip), [[RCX:%r.x]] +; LINUX-64-STATIC: movl [[EAX]], ([[RCX]],%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: ind08: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl lsrc(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl lptr, %edx -; LINUX-32-STATIC-NEXT: movl %ecx, (%edx,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl lsrc(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl lptr, [[EDX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: ind08: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl lsrc(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl lptr, %edx -; LINUX-32-PIC-NEXT: movl %ecx, (%edx,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl lsrc(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl lptr, [[EDX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: ind08: -; LINUX-64-PIC: leaq lsrc(%rip), %rax -; LINUX-64-PIC-NEXT: movl (%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: movq lptr(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4) +; LINUX-64-PIC: leaq lsrc(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq lptr(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _ind08: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _lsrc(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl _lptr, %edx -; DARWIN-32-STATIC-NEXT: movl %ecx, (%edx,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _lsrc(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _lptr, [[EDX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _ind08: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl _lsrc(,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl _lptr, %edx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, (%edx,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _lsrc(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _lptr, [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _ind08: ; DARWIN-32-PIC: calll L35$pb ; DARWIN-32-PIC-NEXT: L35$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _lsrc-L35$pb(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _lptr-L35$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %edx, (%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _lsrc-L35$pb([[EAX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _lptr-L35$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], ([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _ind08: -; DARWIN-64-STATIC: leaq _lsrc(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: movq _lptr(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-STATIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _lptr(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _ind08: -; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _lptr(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _lptr(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _ind08: -; DARWIN-64-PIC: leaq _lsrc(%rip), %rax -; DARWIN-64-PIC-NEXT: movl (%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: movq _lptr(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, (%rcx,%rdi,4) +; DARWIN-64-PIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _lptr(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], ([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -2583,73 +2594,73 @@ entry: store i32 %2, i32* %3, align 4 ret void ; LINUX-64-STATIC: off00: -; LINUX-64-STATIC: movl src+64(,%rdi,4), %eax -; LINUX-64-STATIC: movl %eax, dst+64(,%rdi,4) +; LINUX-64-STATIC: movl src+64(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], dst+64(,%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: off00: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl src+64(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl %ecx, dst+64(,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl src+64(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], dst+64(,[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: off00: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl src+64(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl %ecx, dst+64(,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl src+64(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], dst+64(,[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: off00: -; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _off00: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _src+64(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl %ecx, _dst+64(,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _src+64(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], _dst+64(,[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _off00: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl 64(%ecx,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, %edx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, 64(%edx,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl 64([[ECX]],[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off00: ; DARWIN-32-PIC: calll L36$pb ; DARWIN-32-PIC-NEXT: L36$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L36$pb(%eax), %edx -; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L36$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L36$pb([[EAX]]), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 64([[EDX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L36$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], 64([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off00: -; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _off00: -; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _off00: -; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -2662,73 +2673,73 @@ entry: store i32 %2, i32* %3, align 4 ret void ; LINUX-64-STATIC: oxf00: -; LINUX-64-STATIC: movl xsrc+64(,%rdi,4), %eax -; LINUX-64-STATIC: movl %eax, xdst+64(,%rdi,4) +; LINUX-64-STATIC: movl xsrc+64(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], xdst+64(,%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: oxf00: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl xsrc+64(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl %ecx, xdst+64(,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl xsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], xdst+64(,[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: oxf00: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl xsrc+64(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl %ecx, xdst+64(,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl xsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], xdst+64(,[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: oxf00: -; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: movq xdst@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq xdst@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _oxf00: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _xsrc+64(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl %ecx, _xdst+64(,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _xsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], _xdst+64(,[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _oxf00: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_xsrc$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl 64(%ecx,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, %edx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, 64(%edx,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_xsrc$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl 64([[ECX]],[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _oxf00: ; DARWIN-32-PIC: calll L37$pb ; DARWIN-32-PIC-NEXT: L37$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L37$pb(%eax), %edx -; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L37$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L37$pb([[EAX]]), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 64([[EDX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L37$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], 64([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _oxf00: -; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _xdst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _oxf00: -; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _xdst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _oxf00: -; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: movq _xdst@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _xdst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -2739,73 +2750,73 @@ entry: store i32* %0, i32** @ptr, align 8 ret void ; LINUX-64-STATIC: off01: -; LINUX-64-STATIC: leaq dst+64(,%rdi,4), %rax -; LINUX-64-STATIC: movq %rax, ptr +; LINUX-64-STATIC: leaq dst+64(,%rdi,4), [[RAX:%r.x]] +; LINUX-64-STATIC: movq [[RAX]], ptr ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: off01: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal dst+64(,%eax,4), %eax -; LINUX-32-STATIC-NEXT: movl %eax, ptr +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal dst+64(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], ptr ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: off01: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal dst+64(,%eax,4), %eax -; LINUX-32-PIC-NEXT: movl %eax, ptr +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal dst+64(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], ptr ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: off01: -; LINUX-64-PIC: movq dst@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq %rax, (%rcx) +; LINUX-64-PIC: movq dst@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _off01: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _dst+64(,%eax,4), %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _ptr +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _dst+64(,[[EAX]],4), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _ptr ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _off01: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: leal 64(%ecx,%eax,4), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal 64([[ECX]],[[EAX]],4), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], ([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off01: ; DARWIN-32-PIC: calll L38$pb ; DARWIN-32-PIC-NEXT: L38$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L38$pb(%eax), %edx -; DARWIN-32-PIC-NEXT: leal 64(%edx,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L38$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L38$pb([[EAX]]), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: leal 64([[EDX]],[[ECX]],4), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L38$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], ([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off01: -; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 64([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _off01: -; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 64([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _off01: -; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -2816,73 +2827,73 @@ entry: store i32* %0, i32** @ptr, align 8 ret void ; LINUX-64-STATIC: oxf01: -; LINUX-64-STATIC: leaq xdst+64(,%rdi,4), %rax -; LINUX-64-STATIC: movq %rax, ptr +; LINUX-64-STATIC: leaq xdst+64(,%rdi,4), [[RAX:%r.x]] +; LINUX-64-STATIC: movq [[RAX]], ptr ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: oxf01: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal xdst+64(,%eax,4), %eax -; LINUX-32-STATIC-NEXT: movl %eax, ptr +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal xdst+64(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], ptr ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: oxf01: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal xdst+64(,%eax,4), %eax -; LINUX-32-PIC-NEXT: movl %eax, ptr +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal xdst+64(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], ptr ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: oxf01: -; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq %rax, (%rcx) +; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _oxf01: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _xdst+64(,%eax,4), %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _ptr +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _xdst+64(,[[EAX]],4), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _ptr ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _oxf01: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: leal 64(%ecx,%eax,4), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal 64([[ECX]],[[EAX]],4), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], ([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _oxf01: ; DARWIN-32-PIC: calll L39$pb ; DARWIN-32-PIC-NEXT: L39$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L39$pb(%eax), %edx -; DARWIN-32-PIC-NEXT: leal 64(%edx,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L39$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L39$pb([[EAX]]), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: leal 64([[EDX]],[[ECX]],4), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L39$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], ([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _oxf01: -; DARWIN-64-STATIC: movq _xdst@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-STATIC: movq _xdst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 64([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _oxf01: -; DARWIN-64-DYNAMIC: movq _xdst@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-DYNAMIC: movq _xdst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 64([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _oxf01: -; DARWIN-64-PIC: movq _xdst@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-PIC: movq _xdst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -2896,83 +2907,83 @@ entry: store i32 %3, i32* %4, align 4 ret void ; LINUX-64-STATIC: off02: -; LINUX-64-STATIC: movl src+64(,%rdi,4), %eax -; LINUX-64-STATIC: movq ptr(%rip), %rcx -; LINUX-64-STATIC: movl %eax, 64(%rcx,%rdi,4) +; LINUX-64-STATIC: movl src+64(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movq ptr(%rip), [[RCX:%r.x]] +; LINUX-64-STATIC: movl [[EAX]], 64([[RCX]],%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: off02: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl src+64(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl ptr, %edx -; LINUX-32-STATIC-NEXT: movl %ecx, 64(%edx,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl src+64(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl ptr, [[EDX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: off02: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl src+64(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl ptr, %edx -; LINUX-32-PIC-NEXT: movl %ecx, 64(%edx,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl src+64(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl ptr, [[EDX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: off02: -; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq (%rcx), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _off02: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _src+64(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl _ptr, %edx -; DARWIN-32-STATIC-NEXT: movl %ecx, 64(%edx,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _src+64(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _ptr, [[EDX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _off02: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl 64(%ecx,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %edx -; DARWIN-32-DYNAMIC-NEXT: movl (%edx), %edx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, 64(%edx,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl 64([[ECX]],[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[EDX]]), [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off02: ; DARWIN-32-PIC: calll L40$pb ; DARWIN-32-PIC-NEXT: L40$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L40$pb(%eax), %edx -; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L40$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl (%eax), %eax -; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L40$pb([[EAX]]), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 64([[EDX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L40$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl ([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], 64([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off02: -; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _off02: -; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _off02: -; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -2986,83 +2997,83 @@ entry: store i32 %3, i32* %4, align 4 ret void ; LINUX-64-STATIC: oxf02: -; LINUX-64-STATIC: movl xsrc+64(,%rdi,4), %eax -; LINUX-64-STATIC: movq ptr(%rip), %rcx -; LINUX-64-STATIC: movl %eax, 64(%rcx,%rdi,4) +; LINUX-64-STATIC: movl xsrc+64(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movq ptr(%rip), [[RCX:%r.x]] +; LINUX-64-STATIC: movl [[EAX]], 64([[RCX]],%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: oxf02: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl xsrc+64(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl ptr, %edx -; LINUX-32-STATIC-NEXT: movl %ecx, 64(%edx,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl xsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl ptr, [[EDX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: oxf02: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl xsrc+64(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl ptr, %edx -; LINUX-32-PIC-NEXT: movl %ecx, 64(%edx,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl xsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl ptr, [[EDX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: oxf02: -; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq (%rcx), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _oxf02: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _xsrc+64(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl _ptr, %edx -; DARWIN-32-STATIC-NEXT: movl %ecx, 64(%edx,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _xsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _ptr, [[EDX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _oxf02: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_xsrc$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl 64(%ecx,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %edx -; DARWIN-32-DYNAMIC-NEXT: movl (%edx), %edx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, 64(%edx,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_xsrc$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl 64([[ECX]],[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[EDX]]), [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _oxf02: ; DARWIN-32-PIC: calll L41$pb ; DARWIN-32-PIC-NEXT: L41$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L41$pb(%eax), %edx -; DARWIN-32-PIC-NEXT: movl 64(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L41$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl (%eax), %eax -; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L41$pb([[EAX]]), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 64([[EDX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L41$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl ([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], 64([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _oxf02: -; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _oxf02: -; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _oxf02: -; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -3075,69 +3086,69 @@ entry: store i32 %2, i32* %3, align 4 ret void ; LINUX-64-STATIC: off03: -; LINUX-64-STATIC: movl dsrc+64(,%rdi,4), %eax -; LINUX-64-STATIC: movl %eax, ddst+64(,%rdi,4) +; LINUX-64-STATIC: movl dsrc+64(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], ddst+64(,%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: off03: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl dsrc+64(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl %ecx, ddst+64(,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl dsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], ddst+64(,[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: off03: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl dsrc+64(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl %ecx, ddst+64(,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl dsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], ddst+64(,[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: off03: -; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _off03: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _dsrc+64(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl %ecx, _ddst+64(,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _dsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], _ddst+64(,[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _off03: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl _dsrc+64(,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, _ddst+64(,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _dsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], _ddst+64(,[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off03: ; DARWIN-32-PIC: calll L42$pb ; DARWIN-32-PIC-NEXT: L42$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_dsrc-L42$pb)+64(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, (_ddst-L42$pb)+64(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl (_dsrc-L42$pb)+64([[EAX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], (_ddst-L42$pb)+64([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off03: -; DARWIN-64-STATIC: leaq _dsrc(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: leaq _ddst(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-STATIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: leaq _ddst(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _off03: -; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: leaq _ddst(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq _ddst(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _off03: -; DARWIN-64-PIC: leaq _dsrc(%rip), %rax -; DARWIN-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: leaq _ddst(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-PIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: leaq _ddst(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -3148,66 +3159,66 @@ entry: store i32* %0, i32** @dptr, align 8 ret void ; LINUX-64-STATIC: off04: -; LINUX-64-STATIC: leaq ddst+64(,%rdi,4), %rax -; LINUX-64-STATIC: movq %rax, dptr +; LINUX-64-STATIC: leaq ddst+64(,%rdi,4), [[RAX:%r.x]] +; LINUX-64-STATIC: movq [[RAX]], dptr ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: off04: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal ddst+64(,%eax,4), %eax -; LINUX-32-STATIC-NEXT: movl %eax, dptr +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal ddst+64(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], dptr ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: off04: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal ddst+64(,%eax,4), %eax -; LINUX-32-PIC-NEXT: movl %eax, dptr +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal ddst+64(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], dptr ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: off04: -; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax -; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq %rax, (%rcx) +; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _off04: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _ddst+64(,%eax,4), %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _dptr +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _ddst+64(,[[EAX]],4), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _dptr ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _off04: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: leal _ddst+64(,%eax,4), %eax -; DARWIN-32-DYNAMIC-NEXT: movl %eax, _dptr +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal _ddst+64(,[[EAX]],4), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], _dptr ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off04: ; DARWIN-32-PIC: calll L43$pb ; DARWIN-32-PIC-NEXT: L43$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ddst-L43$pb)+64(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L43$pb(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_ddst-L43$pb)+64([[EAX]],[[ECX]],4), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], _dptr-L43$pb([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off04: -; DARWIN-64-STATIC: leaq _ddst(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax -; DARWIN-64-STATIC-NEXT: movq %rax, _dptr(%rip) +; DARWIN-64-STATIC: leaq _ddst(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 64([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq [[RAX]], _dptr(%rip) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _off04: -; DARWIN-64-DYNAMIC: leaq _ddst(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax -; DARWIN-64-DYNAMIC-NEXT: movq %rax, _dptr(%rip) +; DARWIN-64-DYNAMIC: leaq _ddst(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 64([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq [[RAX]], _dptr(%rip) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _off04: -; DARWIN-64-PIC: leaq _ddst(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax -; DARWIN-64-PIC-NEXT: movq %rax, _dptr(%rip) +; DARWIN-64-PIC: leaq _ddst(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq [[RAX]], _dptr(%rip) ; DARWIN-64-PIC-NEXT: ret } @@ -3221,76 +3232,76 @@ entry: store i32 %3, i32* %4, align 4 ret void ; LINUX-64-STATIC: off05: -; LINUX-64-STATIC: movl dsrc+64(,%rdi,4), %eax -; LINUX-64-STATIC: movq dptr(%rip), %rcx -; LINUX-64-STATIC: movl %eax, 64(%rcx,%rdi,4) +; LINUX-64-STATIC: movl dsrc+64(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movq dptr(%rip), [[RCX:%r.x]] +; LINUX-64-STATIC: movl [[EAX]], 64([[RCX]],%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: off05: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl dsrc+64(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl dptr, %edx -; LINUX-32-STATIC-NEXT: movl %ecx, 64(%edx,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl dsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl dptr, [[EDX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: off05: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl dsrc+64(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl dptr, %edx -; LINUX-32-PIC-NEXT: movl %ecx, 64(%edx,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl dsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl dptr, [[EDX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: off05: -; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq (%rcx), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _off05: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _dsrc+64(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl _dptr, %edx -; DARWIN-32-STATIC-NEXT: movl %ecx, 64(%edx,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _dsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _dptr, [[EDX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _off05: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl _dsrc+64(,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl _dptr, %edx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, 64(%edx,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _dsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _dptr, [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off05: ; DARWIN-32-PIC: calll L44$pb ; DARWIN-32-PIC-NEXT: L44$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_dsrc-L44$pb)+64(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _dptr-L44$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl (_dsrc-L44$pb)+64([[EAX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _dptr-L44$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], 64([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off05: -; DARWIN-64-STATIC: leaq _dsrc(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: movq _dptr(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-STATIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _dptr(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _off05: -; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _dptr(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _dptr(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _off05: -; DARWIN-64-PIC: leaq _dsrc(%rip), %rax -; DARWIN-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: movq _dptr(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-PIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _dptr(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -3303,69 +3314,69 @@ entry: store i32 %2, i32* %3, align 4 ret void ; LINUX-64-STATIC: off06: -; LINUX-64-STATIC: movl lsrc+64(,%rdi,4), %eax -; LINUX-64-STATIC: movl %eax, ldst+64(,%rdi,4) +; LINUX-64-STATIC: movl lsrc+64(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], ldst+64(,%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: off06: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl lsrc+64(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl %ecx, ldst+64(,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl lsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], ldst+64(,[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: off06: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl lsrc+64(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl %ecx, ldst+64(,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl lsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], ldst+64(,[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: off06: -; LINUX-64-PIC: leaq lsrc(%rip), %rax -; LINUX-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: leaq ldst(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; LINUX-64-PIC: leaq lsrc(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: leaq ldst(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _off06: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _lsrc+64(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl %ecx, _ldst+64(,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _lsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], _ldst+64(,[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _off06: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl _lsrc+64(,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, _ldst+64(,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _lsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], _ldst+64(,[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off06: ; DARWIN-32-PIC: calll L45$pb ; DARWIN-32-PIC-NEXT: L45$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_lsrc-L45$pb)+64(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, (_ldst-L45$pb)+64(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl (_lsrc-L45$pb)+64([[EAX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], (_ldst-L45$pb)+64([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off06: -; DARWIN-64-STATIC: leaq _lsrc(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: leaq _ldst(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-STATIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: leaq _ldst(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _off06: -; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: leaq _ldst(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq _ldst(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _off06: -; DARWIN-64-PIC: leaq _lsrc(%rip), %rax -; DARWIN-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: leaq _ldst(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-PIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: leaq _ldst(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -3376,65 +3387,65 @@ entry: store i32* %0, i32** @lptr, align 8 ret void ; LINUX-64-STATIC: off07: -; LINUX-64-STATIC: leaq ldst+64(,%rdi,4), %rax -; LINUX-64-STATIC: movq %rax, lptr +; LINUX-64-STATIC: leaq ldst+64(,%rdi,4), [[RAX:%r.x]] +; LINUX-64-STATIC: movq [[RAX]], lptr ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: off07: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal ldst+64(,%eax,4), %eax -; LINUX-32-STATIC-NEXT: movl %eax, lptr +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal ldst+64(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], lptr ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: off07: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal ldst+64(,%eax,4), %eax -; LINUX-32-PIC-NEXT: movl %eax, lptr +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal ldst+64(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], lptr ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: off07: -; LINUX-64-PIC: leaq ldst(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax -; LINUX-64-PIC-NEXT: movq %rax, lptr(%rip) +; LINUX-64-PIC: leaq ldst(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq [[RAX]], lptr(%rip) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _off07: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _ldst+64(,%eax,4), %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _lptr +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _ldst+64(,[[EAX]],4), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _lptr ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _off07: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: leal _ldst+64(,%eax,4), %eax -; DARWIN-32-DYNAMIC-NEXT: movl %eax, _lptr +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal _ldst+64(,[[EAX]],4), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], _lptr ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off07: ; DARWIN-32-PIC: calll L46$pb ; DARWIN-32-PIC-NEXT: L46$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ldst-L46$pb)+64(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L46$pb(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_ldst-L46$pb)+64([[EAX]],[[ECX]],4), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], _lptr-L46$pb([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off07: -; DARWIN-64-STATIC: leaq _ldst(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax -; DARWIN-64-STATIC-NEXT: movq %rax, _lptr(%rip) +; DARWIN-64-STATIC: leaq _ldst(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 64([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq [[RAX]], _lptr(%rip) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _off07: -; DARWIN-64-DYNAMIC: leaq _ldst(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax -; DARWIN-64-DYNAMIC-NEXT: movq %rax, _lptr(%rip) +; DARWIN-64-DYNAMIC: leaq _ldst(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 64([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq [[RAX]], _lptr(%rip) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _off07: -; DARWIN-64-PIC: leaq _ldst(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax -; DARWIN-64-PIC-NEXT: movq %rax, _lptr(%rip) +; DARWIN-64-PIC: leaq _ldst(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq [[RAX]], _lptr(%rip) ; DARWIN-64-PIC-NEXT: ret } @@ -3448,75 +3459,75 @@ entry: store i32 %3, i32* %4, align 4 ret void ; LINUX-64-STATIC: off08: -; LINUX-64-STATIC: movl lsrc+64(,%rdi,4), %eax -; LINUX-64-STATIC: movq lptr(%rip), %rcx -; LINUX-64-STATIC: movl %eax, 64(%rcx,%rdi,4) +; LINUX-64-STATIC: movl lsrc+64(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movq lptr(%rip), [[RCX:%r.x]] +; LINUX-64-STATIC: movl [[EAX]], 64([[RCX]],%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: off08: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl lsrc+64(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl lptr, %edx -; LINUX-32-STATIC-NEXT: movl %ecx, 64(%edx,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl lsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl lptr, [[EDX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: off08: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl lsrc+64(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl lptr, %edx -; LINUX-32-PIC-NEXT: movl %ecx, 64(%edx,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl lsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl lptr, [[EDX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: off08: -; LINUX-64-PIC: leaq lsrc(%rip), %rax -; LINUX-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: movq lptr(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; LINUX-64-PIC: leaq lsrc(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq lptr(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _off08: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _lsrc+64(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl _lptr, %edx -; DARWIN-32-STATIC-NEXT: movl %ecx, 64(%edx,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _lsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _lptr, [[EDX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _off08: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl _lsrc+64(,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl _lptr, %edx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, 64(%edx,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _lsrc+64(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _lptr, [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _off08: ; DARWIN-32-PIC: calll L47$pb ; DARWIN-32-PIC-NEXT: L47$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_lsrc-L47$pb)+64(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _lptr-L47$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %edx, 64(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl (_lsrc-L47$pb)+64([[EAX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _lptr-L47$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], 64([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _off08: -; DARWIN-64-STATIC: leaq _lsrc(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: movq _lptr(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-STATIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _lptr(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _off08: -; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _lptr(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _lptr(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _off08: -; DARWIN-64-PIC: leaq _lsrc(%rip), %rax -; DARWIN-64-PIC-NEXT: movl 64(%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: movq _lptr(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 64(%rcx,%rdi,4) +; DARWIN-64-PIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _lptr(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 64([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -3526,68 +3537,68 @@ entry: store i32 %0, i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 65536), align 4 ret void ; LINUX-64-STATIC: moo00: -; LINUX-64-STATIC: movl src+262144(%rip), %eax -; LINUX-64-STATIC: movl %eax, dst+262144(%rip) +; LINUX-64-STATIC: movl src+262144(%rip), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], dst+262144(%rip) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: moo00: -; LINUX-32-STATIC: movl src+262144, %eax -; LINUX-32-STATIC-NEXT: movl %eax, dst+262144 +; LINUX-32-STATIC: movl src+262144, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], dst+262144 ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: moo00: -; LINUX-32-PIC: movl src+262144, %eax -; LINUX-32-PIC-NEXT: movl %eax, dst+262144 +; LINUX-32-PIC: movl src+262144, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], dst+262144 ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: moo00: -; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl 262144(%rax), %eax -; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx) +; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 262144([[RAX]]), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _moo00: -; DARWIN-32-STATIC: movl _src+262144, %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _dst+262144 +; DARWIN-32-STATIC: movl _src+262144, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _dst+262144 ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _moo00: -; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: movl 262144(%eax), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, 262144(%ecx) +; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl 262144([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], 262144([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo00: ; DARWIN-32-PIC: calll L48$pb ; DARWIN-32-PIC-NEXT: L48$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L48$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl 262144(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L48$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L48$pb([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 262144([[ECX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L48$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], 262144([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo00: -; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl 262144(%rax), %eax -; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 262144(%rcx) +; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl 262144([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 262144([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _moo00: -; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl 262144(%rax), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 262144(%rcx) +; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl 262144([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 262144([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _moo00: -; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movl 262144(%rax), %eax -; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 262144(%rcx) +; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl 262144([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -3608,10 +3619,10 @@ entry: ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: moo01: -; LINUX-64-PIC: movl $262144, %eax -; LINUX-64-PIC-NEXT: addq dst@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq %rax, (%rcx) +; LINUX-64-PIC: movl $262144, [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: addq dst@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _moo01: @@ -3619,41 +3630,41 @@ entry: ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _moo01: -; DARWIN-32-DYNAMIC: movl $262144, %eax -; DARWIN-32-DYNAMIC-NEXT: addl L_dst$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx) +; DARWIN-32-DYNAMIC: movl $262144, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: addl L_dst$non_lazy_ptr, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], ([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo01: ; DARWIN-32-PIC: calll L49$pb ; DARWIN-32-PIC-NEXT: L49$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl $262144, %ecx -; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L49$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L49$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl $262144, [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L49$pb([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L49$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], ([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo01: -; DARWIN-64-STATIC: movl $262144, %eax -; DARWIN-64-STATIC-NEXT: addq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-STATIC: movl $262144, [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: addq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _moo01: -; DARWIN-64-DYNAMIC: movl $262144, %eax -; DARWIN-64-DYNAMIC-NEXT: addq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-DYNAMIC: movl $262144, [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: addq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _moo01: -; DARWIN-64-PIC: movl $262144, %eax -; DARWIN-64-PIC-NEXT: addq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-PIC: movl $262144, [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: addq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -3665,78 +3676,78 @@ entry: store i32 %1, i32* %2, align 4 ret void ; LINUX-64-STATIC: moo02: -; LINUX-64-STATIC: movl src+262144(%rip), %eax -; LINUX-64-STATIC: movq ptr(%rip), %rcx -; LINUX-64-STATIC: movl %eax, 262144(%rcx) +; LINUX-64-STATIC: movl src+262144(%rip), [[EAX:%e.x]] +; LINUX-64-STATIC: movq ptr(%rip), [[RCX:%r.x]] +; LINUX-64-STATIC: movl [[EAX]], 262144([[RCX]]) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: moo02: -; LINUX-32-STATIC: movl src+262144, %eax -; LINUX-32-STATIC-NEXT: movl ptr, %ecx -; LINUX-32-STATIC-NEXT: movl %eax, 262144(%ecx) +; LINUX-32-STATIC: movl src+262144, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl ptr, [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], 262144([[ECX]]) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: moo02: -; LINUX-32-PIC: movl src+262144, %eax -; LINUX-32-PIC-NEXT: movl ptr, %ecx -; LINUX-32-PIC-NEXT: movl %eax, 262144(%ecx) +; LINUX-32-PIC: movl src+262144, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl ptr, [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], 262144([[ECX]]) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: moo02: -; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl 262144(%rax), %eax -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq (%rcx), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx) +; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 262144([[RAX]]), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _moo02: -; DARWIN-32-STATIC: movl _src+262144, %eax -; DARWIN-32-STATIC-NEXT: movl _ptr, %ecx -; DARWIN-32-STATIC-NEXT: movl %eax, 262144(%ecx) +; DARWIN-32-STATIC: movl _src+262144, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _ptr, [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], 262144([[ECX]]) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _moo02: -; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: movl 262144(%eax), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl (%ecx), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, 262144(%ecx) +; DARWIN-32-DYNAMIC: movl L_src$non_lazy_ptr, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl 262144([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[ECX]]), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], 262144([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo02: ; DARWIN-32-PIC: calll L50$pb ; DARWIN-32-PIC-NEXT: L50$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L50$pb(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl 262144(%ecx), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L50$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl (%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L50$pb([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 262144([[ECX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L50$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl ([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], 262144([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo02: -; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl 262144(%rax), %eax -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 262144(%rcx) +; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl 262144([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 262144([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _moo02: -; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl 262144(%rax), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 262144(%rcx) +; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl 262144([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 262144([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _moo02: -; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movl 262144(%rax), %eax -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 262144(%rcx) +; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl 262144([[RAX]]), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -3746,58 +3757,58 @@ entry: store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 65536), align 32 ret void ; LINUX-64-STATIC: moo03: -; LINUX-64-STATIC: movl dsrc+262144(%rip), %eax -; LINUX-64-STATIC: movl %eax, ddst+262144(%rip) +; LINUX-64-STATIC: movl dsrc+262144(%rip), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], ddst+262144(%rip) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: moo03: -; LINUX-32-STATIC: movl dsrc+262144, %eax -; LINUX-32-STATIC-NEXT: movl %eax, ddst+262144 +; LINUX-32-STATIC: movl dsrc+262144, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], ddst+262144 ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: moo03: -; LINUX-32-PIC: movl dsrc+262144, %eax -; LINUX-32-PIC-NEXT: movl %eax, ddst+262144 +; LINUX-32-PIC: movl dsrc+262144, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], ddst+262144 ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: moo03: -; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl 262144(%rax), %eax -; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx) +; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 262144([[RAX]]), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _moo03: -; DARWIN-32-STATIC: movl _dsrc+262144, %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _ddst+262144 +; DARWIN-32-STATIC: movl _dsrc+262144, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _ddst+262144 ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _moo03: -; DARWIN-32-DYNAMIC: movl _dsrc+262144, %eax -; DARWIN-32-DYNAMIC-NEXT: movl %eax, _ddst+262144 +; DARWIN-32-DYNAMIC: movl _dsrc+262144, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], _ddst+262144 ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo03: ; DARWIN-32-PIC: calll L51$pb ; DARWIN-32-PIC-NEXT: L51$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_dsrc-L51$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, (_ddst-L51$pb)+262144(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl (_dsrc-L51$pb)+262144([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], (_ddst-L51$pb)+262144([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo03: -; DARWIN-64-STATIC: movl _dsrc+262144(%rip), %eax -; DARWIN-64-STATIC-NEXT: movl %eax, _ddst+262144(%rip) +; DARWIN-64-STATIC: movl _dsrc+262144(%rip), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], _ddst+262144(%rip) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _moo03: -; DARWIN-64-DYNAMIC: movl _dsrc+262144(%rip), %eax -; DARWIN-64-DYNAMIC-NEXT: movl %eax, _ddst+262144(%rip) +; DARWIN-64-DYNAMIC: movl _dsrc+262144(%rip), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], _ddst+262144(%rip) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _moo03: -; DARWIN-64-PIC: movl _dsrc+262144(%rip), %eax -; DARWIN-64-PIC-NEXT: movl %eax, _ddst+262144(%rip) +; DARWIN-64-PIC: movl _dsrc+262144(%rip), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], _ddst+262144(%rip) ; DARWIN-64-PIC-NEXT: ret } @@ -3818,10 +3829,10 @@ entry: ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: moo04: -; LINUX-64-PIC: movl $262144, %eax -; LINUX-64-PIC-NEXT: addq ddst@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq %rax, (%rcx) +; LINUX-64-PIC: movl $262144, [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: addq ddst@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _moo04: @@ -3835,24 +3846,24 @@ entry: ; DARWIN-32-PIC: _moo04: ; DARWIN-32-PIC: calll L52$pb ; DARWIN-32-PIC-NEXT: L52$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ddst-L52$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L52$pb(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_ddst-L52$pb)+262144([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], _dptr-L52$pb([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo04: -; DARWIN-64-STATIC: leaq _ddst+262144(%rip), %rax -; DARWIN-64-STATIC-NEXT: movq %rax, _dptr(%rip) +; DARWIN-64-STATIC: leaq _ddst+262144(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq [[RAX]], _dptr(%rip) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _moo04: -; DARWIN-64-DYNAMIC: leaq _ddst+262144(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movq %rax, _dptr(%rip) +; DARWIN-64-DYNAMIC: leaq _ddst+262144(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq [[RAX]], _dptr(%rip) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _moo04: -; DARWIN-64-PIC: leaq _ddst+262144(%rip), %rax -; DARWIN-64-PIC-NEXT: movq %rax, _dptr(%rip) +; DARWIN-64-PIC: leaq _ddst+262144(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq [[RAX]], _dptr(%rip) ; DARWIN-64-PIC-NEXT: ret } @@ -3864,68 +3875,68 @@ entry: store i32 %1, i32* %2, align 4 ret void ; LINUX-64-STATIC: moo05: -; LINUX-64-STATIC: movl dsrc+262144(%rip), %eax -; LINUX-64-STATIC: movq dptr(%rip), %rcx -; LINUX-64-STATIC: movl %eax, 262144(%rcx) +; LINUX-64-STATIC: movl dsrc+262144(%rip), [[EAX:%e.x]] +; LINUX-64-STATIC: movq dptr(%rip), [[RCX:%r.x]] +; LINUX-64-STATIC: movl [[EAX]], 262144([[RCX]]) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: moo05: -; LINUX-32-STATIC: movl dsrc+262144, %eax -; LINUX-32-STATIC-NEXT: movl dptr, %ecx -; LINUX-32-STATIC-NEXT: movl %eax, 262144(%ecx) +; LINUX-32-STATIC: movl dsrc+262144, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl dptr, [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], 262144([[ECX]]) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: moo05: -; LINUX-32-PIC: movl dsrc+262144, %eax -; LINUX-32-PIC-NEXT: movl dptr, %ecx -; LINUX-32-PIC-NEXT: movl %eax, 262144(%ecx) +; LINUX-32-PIC: movl dsrc+262144, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl dptr, [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], 262144([[ECX]]) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: moo05: -; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl 262144(%rax), %eax -; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq (%rcx), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx) +; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 262144([[RAX]]), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _moo05: -; DARWIN-32-STATIC: movl _dsrc+262144, %eax -; DARWIN-32-STATIC-NEXT: movl _dptr, %ecx -; DARWIN-32-STATIC-NEXT: movl %eax, 262144(%ecx) +; DARWIN-32-STATIC: movl _dsrc+262144, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _dptr, [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], 262144([[ECX]]) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _moo05: -; DARWIN-32-DYNAMIC: movl _dsrc+262144, %eax -; DARWIN-32-DYNAMIC-NEXT: movl _dptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, 262144(%ecx) +; DARWIN-32-DYNAMIC: movl _dsrc+262144, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _dptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], 262144([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo05: ; DARWIN-32-PIC: calll L53$pb ; DARWIN-32-PIC-NEXT: L53$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_dsrc-L53$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _dptr-L53$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl (_dsrc-L53$pb)+262144([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _dptr-L53$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], 262144([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo05: -; DARWIN-64-STATIC: movl _dsrc+262144(%rip), %eax -; DARWIN-64-STATIC-NEXT: movq _dptr(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 262144(%rcx) +; DARWIN-64-STATIC: movl _dsrc+262144(%rip), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _dptr(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 262144([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _moo05: -; DARWIN-64-DYNAMIC: movl _dsrc+262144(%rip), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _dptr(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 262144(%rcx) +; DARWIN-64-DYNAMIC: movl _dsrc+262144(%rip), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _dptr(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 262144([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _moo05: -; DARWIN-64-PIC: movl _dsrc+262144(%rip), %eax -; DARWIN-64-PIC-NEXT: movq _dptr(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 262144(%rcx) +; DARWIN-64-PIC: movl _dsrc+262144(%rip), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _dptr(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -3935,56 +3946,56 @@ entry: store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 65536), align 4 ret void ; LINUX-64-STATIC: moo06: -; LINUX-64-STATIC: movl lsrc+262144(%rip), %eax -; LINUX-64-STATIC: movl %eax, ldst+262144(%rip) +; LINUX-64-STATIC: movl lsrc+262144(%rip), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], ldst+262144(%rip) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: moo06: -; LINUX-32-STATIC: movl lsrc+262144, %eax -; LINUX-32-STATIC-NEXT: movl %eax, ldst+262144 +; LINUX-32-STATIC: movl lsrc+262144, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], ldst+262144 ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: moo06: -; LINUX-32-PIC: movl lsrc+262144, %eax -; LINUX-32-PIC-NEXT: movl %eax, ldst+262144 +; LINUX-32-PIC: movl lsrc+262144, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], ldst+262144 ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: moo06: -; LINUX-64-PIC: movl lsrc+262144(%rip), %eax -; LINUX-64-PIC-NEXT: movl %eax, ldst+262144(%rip) +; LINUX-64-PIC: movl lsrc+262144(%rip), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], ldst+262144(%rip) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _moo06: -; DARWIN-32-STATIC: movl _lsrc+262144, %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _ldst+262144 +; DARWIN-32-STATIC: movl _lsrc+262144, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _ldst+262144 ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _moo06: -; DARWIN-32-DYNAMIC: movl _lsrc+262144, %eax -; DARWIN-32-DYNAMIC-NEXT: movl %eax, _ldst+262144 +; DARWIN-32-DYNAMIC: movl _lsrc+262144, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], _ldst+262144 ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo06: ; DARWIN-32-PIC: calll L54$pb ; DARWIN-32-PIC-NEXT: L54$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_lsrc-L54$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, (_ldst-L54$pb)+262144(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl (_lsrc-L54$pb)+262144([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], (_ldst-L54$pb)+262144([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo06: -; DARWIN-64-STATIC: movl _lsrc+262144(%rip), %eax -; DARWIN-64-STATIC-NEXT: movl %eax, _ldst+262144(%rip) +; DARWIN-64-STATIC: movl _lsrc+262144(%rip), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], _ldst+262144(%rip) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _moo06: -; DARWIN-64-DYNAMIC: movl _lsrc+262144(%rip), %eax -; DARWIN-64-DYNAMIC-NEXT: movl %eax, _ldst+262144(%rip) +; DARWIN-64-DYNAMIC: movl _lsrc+262144(%rip), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], _ldst+262144(%rip) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _moo06: -; DARWIN-64-PIC: movl _lsrc+262144(%rip), %eax -; DARWIN-64-PIC-NEXT: movl %eax, _ldst+262144(%rip) +; DARWIN-64-PIC: movl _lsrc+262144(%rip), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], _ldst+262144(%rip) ; DARWIN-64-PIC-NEXT: ret } @@ -4005,8 +4016,8 @@ entry: ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: moo07: -; LINUX-64-PIC: leaq ldst+262144(%rip), %rax -; LINUX-64-PIC-NEXT: movq %rax, lptr(%rip) +; LINUX-64-PIC: leaq ldst+262144(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq [[RAX]], lptr(%rip) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _moo07: @@ -4020,24 +4031,24 @@ entry: ; DARWIN-32-PIC: _moo07: ; DARWIN-32-PIC: calll L55$pb ; DARWIN-32-PIC-NEXT: L55$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ldst-L55$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L55$pb(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_ldst-L55$pb)+262144([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], _lptr-L55$pb([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo07: -; DARWIN-64-STATIC: leaq _ldst+262144(%rip), %rax -; DARWIN-64-STATIC-NEXT: movq %rax, _lptr(%rip) +; DARWIN-64-STATIC: leaq _ldst+262144(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq [[RAX]], _lptr(%rip) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _moo07: -; DARWIN-64-DYNAMIC: leaq _ldst+262144(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movq %rax, _lptr(%rip) +; DARWIN-64-DYNAMIC: leaq _ldst+262144(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq [[RAX]], _lptr(%rip) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _moo07: -; DARWIN-64-PIC: leaq _ldst+262144(%rip), %rax -; DARWIN-64-PIC-NEXT: movq %rax, _lptr(%rip) +; DARWIN-64-PIC: leaq _ldst+262144(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq [[RAX]], _lptr(%rip) ; DARWIN-64-PIC-NEXT: ret } @@ -4049,66 +4060,66 @@ entry: store i32 %1, i32* %2, align 4 ret void ; LINUX-64-STATIC: moo08: -; LINUX-64-STATIC: movl lsrc+262144(%rip), %eax -; LINUX-64-STATIC: movq lptr(%rip), %rcx -; LINUX-64-STATIC: movl %eax, 262144(%rcx) +; LINUX-64-STATIC: movl lsrc+262144(%rip), [[EAX:%e.x]] +; LINUX-64-STATIC: movq lptr(%rip), [[RCX:%r.x]] +; LINUX-64-STATIC: movl [[EAX]], 262144([[RCX]]) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: moo08: -; LINUX-32-STATIC: movl lsrc+262144, %eax -; LINUX-32-STATIC-NEXT: movl lptr, %ecx -; LINUX-32-STATIC-NEXT: movl %eax, 262144(%ecx) +; LINUX-32-STATIC: movl lsrc+262144, [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl lptr, [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], 262144([[ECX]]) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: moo08: -; LINUX-32-PIC: movl lsrc+262144, %eax -; LINUX-32-PIC-NEXT: movl lptr, %ecx -; LINUX-32-PIC-NEXT: movl %eax, 262144(%ecx) +; LINUX-32-PIC: movl lsrc+262144, [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl lptr, [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], 262144([[ECX]]) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: moo08: -; LINUX-64-PIC: movl lsrc+262144(%rip), %eax -; LINUX-64-PIC-NEXT: movq lptr(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx) +; LINUX-64-PIC: movl lsrc+262144(%rip), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq lptr(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _moo08: -; DARWIN-32-STATIC: movl _lsrc+262144, %eax -; DARWIN-32-STATIC-NEXT: movl _lptr, %ecx -; DARWIN-32-STATIC-NEXT: movl %eax, 262144(%ecx) +; DARWIN-32-STATIC: movl _lsrc+262144, [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _lptr, [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], 262144([[ECX]]) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _moo08: -; DARWIN-32-DYNAMIC: movl _lsrc+262144, %eax -; DARWIN-32-DYNAMIC-NEXT: movl _lptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, 262144(%ecx) +; DARWIN-32-DYNAMIC: movl _lsrc+262144, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _lptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], 262144([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _moo08: ; DARWIN-32-PIC: calll L56$pb ; DARWIN-32-PIC-NEXT: L56$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl (_lsrc-L56$pb)+262144(%eax), %ecx -; DARWIN-32-PIC-NEXT: movl _lptr-L56$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, 262144(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl (_lsrc-L56$pb)+262144([[EAX]]), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _lptr-L56$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], 262144([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _moo08: -; DARWIN-64-STATIC: movl _lsrc+262144(%rip), %eax -; DARWIN-64-STATIC-NEXT: movq _lptr(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 262144(%rcx) +; DARWIN-64-STATIC: movl _lsrc+262144(%rip), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _lptr(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 262144([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _moo08: -; DARWIN-64-DYNAMIC: movl _lsrc+262144(%rip), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _lptr(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 262144(%rcx) +; DARWIN-64-DYNAMIC: movl _lsrc+262144(%rip), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _lptr(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 262144([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _moo08: -; DARWIN-64-PIC: movl _lsrc+262144(%rip), %eax -; DARWIN-64-PIC-NEXT: movq _lptr(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 262144(%rcx) +; DARWIN-64-PIC: movl _lsrc+262144(%rip), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _lptr(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -4121,73 +4132,73 @@ entry: store i32 %2, i32* %3, align 4 ret void ; LINUX-64-STATIC: big00: -; LINUX-64-STATIC: movl src+262144(,%rdi,4), %eax -; LINUX-64-STATIC: movl %eax, dst+262144(,%rdi,4) +; LINUX-64-STATIC: movl src+262144(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], dst+262144(,%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: big00: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl src+262144(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl %ecx, dst+262144(,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl src+262144(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], dst+262144(,[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: big00: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl src+262144(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl %ecx, dst+262144(,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl src+262144(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], dst+262144(,[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: big00: -; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _big00: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _src+262144(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl %ecx, _dst+262144(,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _src+262144(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], _dst+262144(,[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _big00: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl 262144(%ecx,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, %edx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, 262144(%edx,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl 262144([[ECX]],[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], 262144([[EDX]],[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big00: ; DARWIN-32-PIC: calll L57$pb ; DARWIN-32-PIC-NEXT: L57$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L57$pb(%eax), %edx -; DARWIN-32-PIC-NEXT: movl 262144(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L57$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L57$pb([[EAX]]), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 262144([[EDX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L57$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], 262144([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big00: -; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _big00: -; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _big00: -; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _dst@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -4198,73 +4209,73 @@ entry: store i32* %0, i32** @ptr, align 8 ret void ; LINUX-64-STATIC: big01: -; LINUX-64-STATIC: leaq dst+262144(,%rdi,4), %rax -; LINUX-64-STATIC: movq %rax, ptr(%rip) +; LINUX-64-STATIC: leaq dst+262144(,%rdi,4), [[RAX:%r.x]] +; LINUX-64-STATIC: movq [[RAX]], ptr(%rip) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: big01: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal dst+262144(,%eax,4), %eax -; LINUX-32-STATIC-NEXT: movl %eax, ptr +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal dst+262144(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], ptr ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: big01: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal dst+262144(,%eax,4), %eax -; LINUX-32-PIC-NEXT: movl %eax, ptr +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal dst+262144(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], ptr ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: big01: -; LINUX-64-PIC: movq dst@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq %rax, (%rcx) +; LINUX-64-PIC: movq dst@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _big01: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _dst+262144(,%eax,4), %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _ptr +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _dst+262144(,[[EAX]],4), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _ptr ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _big01: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: leal 262144(%ecx,%eax,4), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %eax, (%ecx) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal 262144([[ECX]],[[EAX]],4), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], ([[ECX]]) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big01: ; DARWIN-32-PIC: calll L58$pb ; DARWIN-32-PIC-NEXT: L58$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L58$pb(%eax), %edx -; DARWIN-32-PIC-NEXT: leal 262144(%edx,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L58$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %ecx, (%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L58$pb([[EAX]]), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: leal 262144([[EDX]],[[ECX]],4), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L58$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], ([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big01: -; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 262144([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _big01: -; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 262144([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _big01: -; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movq %rax, (%rcx) +; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; DARWIN-64-PIC-NEXT: ret } @@ -4278,83 +4289,83 @@ entry: store i32 %3, i32* %4, align 4 ret void ; LINUX-64-STATIC: big02: -; LINUX-64-STATIC: movl src+262144(,%rdi,4), %eax -; LINUX-64-STATIC: movq ptr(%rip), %rcx -; LINUX-64-STATIC: movl %eax, 262144(%rcx,%rdi,4) +; LINUX-64-STATIC: movl src+262144(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movq ptr(%rip), [[RCX:%r.x]] +; LINUX-64-STATIC: movl [[EAX]], 262144([[RCX]],%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: big02: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl src+262144(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl ptr, %edx -; LINUX-32-STATIC-NEXT: movl %ecx, 262144(%edx,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl src+262144(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl ptr, [[EDX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], 262144([[EDX]],[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: big02: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl src+262144(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl ptr, %edx -; LINUX-32-PIC-NEXT: movl %ecx, 262144(%edx,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl src+262144(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl ptr, [[EDX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], 262144([[EDX]],[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: big02: -; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq (%rcx), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _big02: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _src+262144(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl _ptr, %edx -; DARWIN-32-STATIC-NEXT: movl %ecx, 262144(%edx,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _src+262144(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _ptr, [[EDX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], 262144([[EDX]],[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _big02: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: movl 262144(%ecx,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, %edx -; DARWIN-32-DYNAMIC-NEXT: movl (%edx), %edx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, 262144(%edx,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl 262144([[ECX]],[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_ptr$non_lazy_ptr, [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[EDX]]), [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], 262144([[EDX]],[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big02: ; DARWIN-32-PIC: calll L59$pb ; DARWIN-32-PIC-NEXT: L59$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L59$pb(%eax), %edx -; DARWIN-32-PIC-NEXT: movl 262144(%edx,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L59$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl (%eax), %eax -; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L59$pb([[EAX]]), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 262144([[EDX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L59$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl ([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], 262144([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big02: -; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _big02: -; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _big02: -; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), %rcx -; DARWIN-64-PIC-NEXT: movq (%rcx), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -4367,69 +4378,69 @@ entry: store i32 %2, i32* %3, align 4 ret void ; LINUX-64-STATIC: big03: -; LINUX-64-STATIC: movl dsrc+262144(,%rdi,4), %eax -; LINUX-64-STATIC: movl %eax, ddst+262144(,%rdi,4) +; LINUX-64-STATIC: movl dsrc+262144(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], ddst+262144(,%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: big03: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl dsrc+262144(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl %ecx, ddst+262144(,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl dsrc+262144(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], ddst+262144(,[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: big03: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl dsrc+262144(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl %ecx, ddst+262144(,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl dsrc+262144(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], ddst+262144(,[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: big03: -; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _big03: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _dsrc+262144(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl %ecx, _ddst+262144(,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _dsrc+262144(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], _ddst+262144(,[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _big03: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl _dsrc+262144(,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, _ddst+262144(,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _dsrc+262144(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], _ddst+262144(,[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big03: ; DARWIN-32-PIC: calll L60$pb ; DARWIN-32-PIC-NEXT: L60$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_dsrc-L60$pb)+262144(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, (_ddst-L60$pb)+262144(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl (_dsrc-L60$pb)+262144([[EAX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], (_ddst-L60$pb)+262144([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big03: -; DARWIN-64-STATIC: leaq _dsrc(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: leaq _ddst(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; DARWIN-64-STATIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: leaq _ddst(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _big03: -; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: leaq _ddst(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq _ddst(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _big03: -; DARWIN-64-PIC: leaq _dsrc(%rip), %rax -; DARWIN-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: leaq _ddst(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; DARWIN-64-PIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: leaq _ddst(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -4440,66 +4451,66 @@ entry: store i32* %0, i32** @dptr, align 8 ret void ; LINUX-64-STATIC: big04: -; LINUX-64-STATIC: leaq ddst+262144(,%rdi,4), %rax -; LINUX-64-STATIC: movq %rax, dptr +; LINUX-64-STATIC: leaq ddst+262144(,%rdi,4), [[RAX:%r.x]] +; LINUX-64-STATIC: movq [[RAX]], dptr ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: big04: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal ddst+262144(,%eax,4), %eax -; LINUX-32-STATIC-NEXT: movl %eax, dptr +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal ddst+262144(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], dptr ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: big04: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal ddst+262144(,%eax,4), %eax -; LINUX-32-PIC-NEXT: movl %eax, dptr +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal ddst+262144(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], dptr ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: big04: -; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax -; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq %rax, (%rcx) +; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq [[RAX]], ([[RCX]]) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _big04: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _ddst+262144(,%eax,4), %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _dptr +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _ddst+262144(,[[EAX]],4), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _dptr ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _big04: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: leal _ddst+262144(,%eax,4), %eax -; DARWIN-32-DYNAMIC-NEXT: movl %eax, _dptr +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal _ddst+262144(,[[EAX]],4), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], _dptr ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big04: ; DARWIN-32-PIC: calll L61$pb ; DARWIN-32-PIC-NEXT: L61$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ddst-L61$pb)+262144(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _dptr-L61$pb(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_ddst-L61$pb)+262144([[EAX]],[[ECX]],4), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], _dptr-L61$pb([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big04: -; DARWIN-64-STATIC: leaq _ddst(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax -; DARWIN-64-STATIC-NEXT: movq %rax, _dptr(%rip) +; DARWIN-64-STATIC: leaq _ddst(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 262144([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq [[RAX]], _dptr(%rip) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _big04: -; DARWIN-64-DYNAMIC: leaq _ddst(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax -; DARWIN-64-DYNAMIC-NEXT: movq %rax, _dptr(%rip) +; DARWIN-64-DYNAMIC: leaq _ddst(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 262144([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq [[RAX]], _dptr(%rip) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _big04: -; DARWIN-64-PIC: leaq _ddst(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax -; DARWIN-64-PIC-NEXT: movq %rax, _dptr(%rip) +; DARWIN-64-PIC: leaq _ddst(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq [[RAX]], _dptr(%rip) ; DARWIN-64-PIC-NEXT: ret } @@ -4513,76 +4524,76 @@ entry: store i32 %3, i32* %4, align 4 ret void ; LINUX-64-STATIC: big05: -; LINUX-64-STATIC: movl dsrc+262144(,%rdi,4), %eax -; LINUX-64-STATIC: movq dptr(%rip), %rcx -; LINUX-64-STATIC: movl %eax, 262144(%rcx,%rdi,4) +; LINUX-64-STATIC: movl dsrc+262144(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movq dptr(%rip), [[RCX:%r.x]] +; LINUX-64-STATIC: movl [[EAX]], 262144([[RCX]],%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: big05: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl dsrc+262144(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl dptr, %edx -; LINUX-32-STATIC-NEXT: movl %ecx, 262144(%edx,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl dsrc+262144(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl dptr, [[EDX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], 262144([[EDX]],[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: big05: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl dsrc+262144(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl dptr, %edx -; LINUX-32-PIC-NEXT: movl %ecx, 262144(%edx,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl dsrc+262144(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl dptr, [[EDX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], 262144([[EDX]],[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: big05: -; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), %rcx -; LINUX-64-PIC-NEXT: movq (%rcx), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RCX]]), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _big05: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _dsrc+262144(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl _dptr, %edx -; DARWIN-32-STATIC-NEXT: movl %ecx, 262144(%edx,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _dsrc+262144(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _dptr, [[EDX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], 262144([[EDX]],[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _big05: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl _dsrc+262144(,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl _dptr, %edx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, 262144(%edx,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _dsrc+262144(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _dptr, [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], 262144([[EDX]],[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big05: ; DARWIN-32-PIC: calll L62$pb ; DARWIN-32-PIC-NEXT: L62$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_dsrc-L62$pb)+262144(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _dptr-L62$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl (_dsrc-L62$pb)+262144([[EAX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _dptr-L62$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], 262144([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big05: -; DARWIN-64-STATIC: leaq _dsrc(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: movq _dptr(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; DARWIN-64-STATIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _dptr(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _big05: -; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _dptr(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _dptr(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _big05: -; DARWIN-64-PIC: leaq _dsrc(%rip), %rax -; DARWIN-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: movq _dptr(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; DARWIN-64-PIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _dptr(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -4595,69 +4606,69 @@ entry: store i32 %2, i32* %3, align 4 ret void ; LINUX-64-STATIC: big06: -; LINUX-64-STATIC: movl lsrc+262144(,%rdi,4), %eax -; LINUX-64-STATIC: movl %eax, ldst+262144(,%rdi,4) +; LINUX-64-STATIC: movl lsrc+262144(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movl [[EAX]], ldst+262144(,%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: big06: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl lsrc+262144(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl %ecx, ldst+262144(,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl lsrc+262144(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], ldst+262144(,[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: big06: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl lsrc+262144(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl %ecx, ldst+262144(,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl lsrc+262144(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], ldst+262144(,[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: big06: -; LINUX-64-PIC: leaq lsrc(%rip), %rax -; LINUX-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: leaq ldst(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; LINUX-64-PIC: leaq lsrc(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: leaq ldst(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _big06: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _lsrc+262144(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl %ecx, _ldst+262144(,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _lsrc+262144(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], _ldst+262144(,[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _big06: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl _lsrc+262144(,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, _ldst+262144(,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _lsrc+262144(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], _ldst+262144(,[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big06: ; DARWIN-32-PIC: calll L63$pb ; DARWIN-32-PIC-NEXT: L63$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_lsrc-L63$pb)+262144(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl %edx, (_ldst-L63$pb)+262144(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl (_lsrc-L63$pb)+262144([[EAX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], (_ldst-L63$pb)+262144([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big06: -; DARWIN-64-STATIC: leaq _lsrc(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: leaq _ldst(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; DARWIN-64-STATIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: leaq _ldst(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _big06: -; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: leaq _ldst(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq _ldst(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _big06: -; DARWIN-64-PIC: leaq _lsrc(%rip), %rax -; DARWIN-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: leaq _ldst(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; DARWIN-64-PIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: leaq _ldst(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -4668,65 +4679,65 @@ entry: store i32* %0, i32** @lptr, align 8 ret void ; LINUX-64-STATIC: big07: -; LINUX-64-STATIC: leaq ldst+262144(,%rdi,4), %rax -; LINUX-64-STATIC: movq %rax, lptr +; LINUX-64-STATIC: leaq ldst+262144(,%rdi,4), [[RAX:%r.x]] +; LINUX-64-STATIC: movq [[RAX]], lptr ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: big07: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal ldst+262144(,%eax,4), %eax -; LINUX-32-STATIC-NEXT: movl %eax, lptr +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal ldst+262144(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[EAX]], lptr ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: big07: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal ldst+262144(,%eax,4), %eax -; LINUX-32-PIC-NEXT: movl %eax, lptr +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal ldst+262144(,[[EAX]],4), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[EAX]], lptr ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: big07: -; LINUX-64-PIC: leaq ldst(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax -; LINUX-64-PIC-NEXT: movq %rax, lptr(%rip) +; LINUX-64-PIC: leaq ldst(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq [[RAX]], lptr(%rip) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _big07: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _ldst+262144(,%eax,4), %eax -; DARWIN-32-STATIC-NEXT: movl %eax, _lptr +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _ldst+262144(,[[EAX]],4), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[EAX]], _lptr ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _big07: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: leal _ldst+262144(,%eax,4), %eax -; DARWIN-32-DYNAMIC-NEXT: movl %eax, _lptr +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal _ldst+262144(,[[EAX]],4), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[EAX]], _lptr ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big07: ; DARWIN-32-PIC: calll L64$pb ; DARWIN-32-PIC-NEXT: L64$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ldst-L64$pb)+262144(%eax,%ecx,4), %ecx -; DARWIN-32-PIC-NEXT: movl %ecx, _lptr-L64$pb(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_ldst-L64$pb)+262144([[EAX]],[[ECX]],4), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[ECX]], _lptr-L64$pb([[EAX]]) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big07: -; DARWIN-64-STATIC: leaq _ldst(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax -; DARWIN-64-STATIC-NEXT: movq %rax, _lptr(%rip) +; DARWIN-64-STATIC: leaq _ldst(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 262144([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq [[RAX]], _lptr(%rip) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _big07: -; DARWIN-64-DYNAMIC: leaq _ldst(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax -; DARWIN-64-DYNAMIC-NEXT: movq %rax, _lptr(%rip) +; DARWIN-64-DYNAMIC: leaq _ldst(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 262144([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq [[RAX]], _lptr(%rip) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _big07: -; DARWIN-64-PIC: leaq _ldst(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax -; DARWIN-64-PIC-NEXT: movq %rax, _lptr(%rip) +; DARWIN-64-PIC: leaq _ldst(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq [[RAX]], _lptr(%rip) ; DARWIN-64-PIC-NEXT: ret } @@ -4740,75 +4751,75 @@ entry: store i32 %3, i32* %4, align 4 ret void ; LINUX-64-STATIC: big08: -; LINUX-64-STATIC: movl lsrc+262144(,%rdi,4), %eax -; LINUX-64-STATIC: movq lptr(%rip), %rcx -; LINUX-64-STATIC: movl %eax, 262144(%rcx,%rdi,4) +; LINUX-64-STATIC: movl lsrc+262144(,%rdi,4), [[EAX:%e.x]] +; LINUX-64-STATIC: movq lptr(%rip), [[RCX:%r.x]] +; LINUX-64-STATIC: movl [[EAX]], 262144([[RCX]],%rdi,4) ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: big08: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl lsrc+262144(,%eax,4), %ecx -; LINUX-32-STATIC-NEXT: movl lptr, %edx -; LINUX-32-STATIC-NEXT: movl %ecx, 262144(%edx,%eax,4) +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl lsrc+262144(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: movl lptr, [[EDX:%e.x]] +; LINUX-32-STATIC-NEXT: movl [[ECX]], 262144([[EDX]],[[EAX]],4) ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: big08: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl lsrc+262144(,%eax,4), %ecx -; LINUX-32-PIC-NEXT: movl lptr, %edx -; LINUX-32-PIC-NEXT: movl %ecx, 262144(%edx,%eax,4) +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl lsrc+262144(,[[EAX]],4), [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: movl lptr, [[EDX:%e.x]] +; LINUX-32-PIC-NEXT: movl [[ECX]], 262144([[EDX]],[[EAX]],4) ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: big08: -; LINUX-64-PIC: leaq lsrc(%rip), %rax -; LINUX-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; LINUX-64-PIC-NEXT: movq lptr(%rip), %rcx -; LINUX-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; LINUX-64-PIC: leaq lsrc(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; LINUX-64-PIC-NEXT: movq lptr(%rip), [[RCX:%r.x]] +; LINUX-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _big08: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _lsrc+262144(,%eax,4), %ecx -; DARWIN-32-STATIC-NEXT: movl _lptr, %edx -; DARWIN-32-STATIC-NEXT: movl %ecx, 262144(%edx,%eax,4) +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _lsrc+262144(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _lptr, [[EDX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl [[ECX]], 262144([[EDX]],[[EAX]],4) ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _big08: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl _lsrc+262144(,%eax,4), %ecx -; DARWIN-32-DYNAMIC-NEXT: movl _lptr, %edx -; DARWIN-32-DYNAMIC-NEXT: movl %ecx, 262144(%edx,%eax,4) +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _lsrc+262144(,[[EAX]],4), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _lptr, [[EDX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], 262144([[EDX]],[[EAX]],4) ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _big08: ; DARWIN-32-PIC: calll L65$pb ; DARWIN-32-PIC-NEXT: L65$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl (_lsrc-L65$pb)+262144(%eax,%ecx,4), %edx -; DARWIN-32-PIC-NEXT: movl _lptr-L65$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl %edx, 262144(%eax,%ecx,4) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl (_lsrc-L65$pb)+262144([[EAX]],[[ECX]],4), [[EDX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _lptr-L65$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl [[EDX]], 262144([[EAX]],[[ECX]],4) ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _big08: -; DARWIN-64-STATIC: leaq _lsrc(%rip), %rax -; DARWIN-64-STATIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; DARWIN-64-STATIC-NEXT: movq _lptr(%rip), %rcx -; DARWIN-64-STATIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; DARWIN-64-STATIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-STATIC-NEXT: movq _lptr(%rip), [[RCX:%r.x]] +; DARWIN-64-STATIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _big08: -; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; DARWIN-64-DYNAMIC-NEXT: movq _lptr(%rip), %rcx -; DARWIN-64-DYNAMIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _lptr(%rip), [[RCX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _big08: -; DARWIN-64-PIC: leaq _lsrc(%rip), %rax -; DARWIN-64-PIC-NEXT: movl 262144(%rax,%rdi,4), %eax -; DARWIN-64-PIC-NEXT: movq _lptr(%rip), %rcx -; DARWIN-64-PIC-NEXT: movl %eax, 262144(%rcx,%rdi,4) +; DARWIN-64-PIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]] +; DARWIN-64-PIC-NEXT: movq _lptr(%rip), [[RCX:%r.x]] +; DARWIN-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]],%rdi,4) ; DARWIN-64-PIC-NEXT: ret } @@ -4842,8 +4853,8 @@ entry: ; DARWIN-32-PIC: _bar00: ; DARWIN-32-PIC: calll L66$pb ; DARWIN-32-PIC-NEXT: L66$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L66$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L66$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar00: @@ -4889,8 +4900,8 @@ entry: ; DARWIN-32-PIC: _bxr00: ; DARWIN-32-PIC: calll L67$pb ; DARWIN-32-PIC-NEXT: L67$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L67$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L67$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bxr00: @@ -4936,8 +4947,8 @@ entry: ; DARWIN-32-PIC: _bar01: ; DARWIN-32-PIC: calll L68$pb ; DARWIN-32-PIC-NEXT: L68$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L68$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L68$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar01: @@ -4983,8 +4994,8 @@ entry: ; DARWIN-32-PIC: _bxr01: ; DARWIN-32-PIC: calll L69$pb ; DARWIN-32-PIC-NEXT: L69$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L69$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L69$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bxr01: @@ -5030,8 +5041,8 @@ entry: ; DARWIN-32-PIC: _bar02: ; DARWIN-32-PIC: calll L70$pb ; DARWIN-32-PIC-NEXT: L70$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L70$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L70$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar02: @@ -5077,8 +5088,8 @@ entry: ; DARWIN-32-PIC: _bar03: ; DARWIN-32-PIC: calll L71$pb ; DARWIN-32-PIC-NEXT: L71$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _dsrc-L71$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal _dsrc-L71$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar03: @@ -5124,8 +5135,8 @@ entry: ; DARWIN-32-PIC: _bar04: ; DARWIN-32-PIC: calll L72$pb ; DARWIN-32-PIC-NEXT: L72$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ddst-L72$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal _ddst-L72$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar04: @@ -5171,8 +5182,8 @@ entry: ; DARWIN-32-PIC: _bar05: ; DARWIN-32-PIC: calll L73$pb ; DARWIN-32-PIC-NEXT: L73$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _dptr-L73$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal _dptr-L73$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar05: @@ -5218,8 +5229,8 @@ entry: ; DARWIN-32-PIC: _bar06: ; DARWIN-32-PIC: calll L74$pb ; DARWIN-32-PIC-NEXT: L74$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _lsrc-L74$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal _lsrc-L74$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar06: @@ -5265,8 +5276,8 @@ entry: ; DARWIN-32-PIC: _bar07: ; DARWIN-32-PIC: calll L75$pb ; DARWIN-32-PIC-NEXT: L75$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ldst-L75$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal _ldst-L75$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar07: @@ -5312,8 +5323,8 @@ entry: ; DARWIN-32-PIC: _bar08: ; DARWIN-32-PIC: calll L76$pb ; DARWIN-32-PIC-NEXT: L76$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _lptr-L76$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal _lptr-L76$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bar08: @@ -5359,8 +5370,8 @@ entry: ; DARWIN-32-PIC: _har00: ; DARWIN-32-PIC: calll L77$pb ; DARWIN-32-PIC-NEXT: L77$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L77$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L77$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har00: @@ -5406,8 +5417,8 @@ entry: ; DARWIN-32-PIC: _hxr00: ; DARWIN-32-PIC: calll L78$pb ; DARWIN-32-PIC-NEXT: L78$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L78$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L78$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _hxr00: @@ -5453,8 +5464,8 @@ entry: ; DARWIN-32-PIC: _har01: ; DARWIN-32-PIC: calll L79$pb ; DARWIN-32-PIC-NEXT: L79$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L79$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L79$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har01: @@ -5500,8 +5511,8 @@ entry: ; DARWIN-32-PIC: _hxr01: ; DARWIN-32-PIC: calll L80$pb ; DARWIN-32-PIC-NEXT: L80$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L80$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L80$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _hxr01: @@ -5535,8 +5546,8 @@ entry: ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: har02: -; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movq (%rax), %rax +; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RAX]]), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _har02: @@ -5544,31 +5555,31 @@ entry: ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _har02: -; DARWIN-32-DYNAMIC: movl L_ptr$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: movl (%eax), %eax +; DARWIN-32-DYNAMIC: movl L_ptr$non_lazy_ptr, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[EAX]]), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _har02: ; DARWIN-32-PIC: calll L81$pb ; DARWIN-32-PIC-NEXT: L81$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L81$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl (%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L81$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl ([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har02: -; DARWIN-64-STATIC: movq _ptr@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movq (%rax), %rax +; DARWIN-64-STATIC: movq _ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq ([[RAX]]), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _har02: -; DARWIN-64-DYNAMIC: movq _ptr@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movq (%rax), %rax +; DARWIN-64-DYNAMIC: movq _ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq ([[RAX]]), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _har02: -; DARWIN-64-PIC: movq _ptr@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movq (%rax), %rax +; DARWIN-64-PIC: movq _ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq ([[RAX]]), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -5602,8 +5613,8 @@ entry: ; DARWIN-32-PIC: _har03: ; DARWIN-32-PIC: calll L82$pb ; DARWIN-32-PIC-NEXT: L82$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _dsrc-L82$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal _dsrc-L82$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har03: @@ -5649,8 +5660,8 @@ entry: ; DARWIN-32-PIC: _har04: ; DARWIN-32-PIC: calll L83$pb ; DARWIN-32-PIC-NEXT: L83$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ddst-L83$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal _ddst-L83$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har04: @@ -5684,8 +5695,8 @@ entry: ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: har05: -; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movq (%rax), %rax +; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RAX]]), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _har05: @@ -5699,8 +5710,8 @@ entry: ; DARWIN-32-PIC: _har05: ; DARWIN-32-PIC: calll L84$pb ; DARWIN-32-PIC-NEXT: L84$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _dptr-L84$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _dptr-L84$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har05: @@ -5746,8 +5757,8 @@ entry: ; DARWIN-32-PIC: _har06: ; DARWIN-32-PIC: calll L85$pb ; DARWIN-32-PIC-NEXT: L85$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _lsrc-L85$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal _lsrc-L85$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har06: @@ -5793,8 +5804,8 @@ entry: ; DARWIN-32-PIC: _har07: ; DARWIN-32-PIC: calll L86$pb ; DARWIN-32-PIC-NEXT: L86$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _ldst-L86$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal _ldst-L86$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har07: @@ -5842,8 +5853,8 @@ entry: ; DARWIN-32-PIC: _har08: ; DARWIN-32-PIC: calll L87$pb ; DARWIN-32-PIC-NEXT: L87$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _lptr-L87$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _lptr-L87$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _har08: @@ -5891,8 +5902,8 @@ entry: ; DARWIN-32-PIC: _bat00: ; DARWIN-32-PIC: calll L88$pb ; DARWIN-32-PIC-NEXT: L88$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L88$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L88$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -5944,8 +5955,8 @@ entry: ; DARWIN-32-PIC: _bxt00: ; DARWIN-32-PIC: calll L89$pb ; DARWIN-32-PIC-NEXT: L89$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L89$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L89$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -5997,8 +6008,8 @@ entry: ; DARWIN-32-PIC: _bat01: ; DARWIN-32-PIC: calll L90$pb ; DARWIN-32-PIC-NEXT: L90$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L90$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L90$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -6050,8 +6061,8 @@ entry: ; DARWIN-32-PIC: _bxt01: ; DARWIN-32-PIC: calll L91$pb ; DARWIN-32-PIC-NEXT: L91$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L91$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L91$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -6093,8 +6104,8 @@ entry: ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: bat02: -; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movq (%rax), %rax +; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RAX]]), %rax ; LINUX-64-PIC-NEXT: addq $64, %rax ; LINUX-64-PIC-NEXT: ret @@ -6104,35 +6115,35 @@ entry: ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _bat02: -; DARWIN-32-DYNAMIC: movl L_ptr$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: movl (%eax), %eax +; DARWIN-32-DYNAMIC: movl L_ptr$non_lazy_ptr, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[EAX]]), [[EAX:%e.x]] ; DARWIN-32-DYNAMIC-NEXT: addl $64, %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bat02: ; DARWIN-32-PIC: calll L92$pb ; DARWIN-32-PIC-NEXT: L92$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L92$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl (%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L92$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl ([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bat02: -; DARWIN-64-STATIC: movq _ptr@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movq (%rax), %rax +; DARWIN-64-STATIC: movq _ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq ([[RAX]]), %rax ; DARWIN-64-STATIC-NEXT: addq $64, %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _bat02: -; DARWIN-64-DYNAMIC: movq _ptr@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movq (%rax), %rax +; DARWIN-64-DYNAMIC: movq _ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq ([[RAX]]), [[RAX:%r.x]] ; DARWIN-64-DYNAMIC-NEXT: addq $64, %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _bat02: -; DARWIN-64-PIC: movq _ptr@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movq (%rax), %rax +; DARWIN-64-PIC: movq _ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq ([[RAX]]), %rax ; DARWIN-64-PIC-NEXT: addq $64, %rax ; DARWIN-64-PIC-NEXT: ret } @@ -6168,8 +6179,8 @@ entry: ; DARWIN-32-PIC: _bat03: ; DARWIN-32-PIC: calll L93$pb ; DARWIN-32-PIC-NEXT: L93$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_dsrc-L93$pb)+64(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_dsrc-L93$pb)+64([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bat03: @@ -6216,8 +6227,8 @@ entry: ; DARWIN-32-PIC: _bat04: ; DARWIN-32-PIC: calll L94$pb ; DARWIN-32-PIC-NEXT: L94$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ddst-L94$pb)+64(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_ddst-L94$pb)+64([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bat04: @@ -6255,8 +6266,8 @@ entry: ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: bat05: -; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movq (%rax), %rax +; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RAX]]), %rax ; LINUX-64-PIC-NEXT: addq $64, %rax ; LINUX-64-PIC-NEXT: ret @@ -6273,8 +6284,8 @@ entry: ; DARWIN-32-PIC: _bat05: ; DARWIN-32-PIC: calll L95$pb ; DARWIN-32-PIC-NEXT: L95$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _dptr-L95$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _dptr-L95$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -6324,8 +6335,8 @@ entry: ; DARWIN-32-PIC: _bat06: ; DARWIN-32-PIC: calll L96$pb ; DARWIN-32-PIC-NEXT: L96$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_lsrc-L96$pb)+64(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_lsrc-L96$pb)+64([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bat06: @@ -6371,8 +6382,8 @@ entry: ; DARWIN-32-PIC: _bat07: ; DARWIN-32-PIC: calll L97$pb ; DARWIN-32-PIC-NEXT: L97$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ldst-L97$pb)+64(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_ldst-L97$pb)+64([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bat07: @@ -6427,8 +6438,8 @@ entry: ; DARWIN-32-PIC: _bat08: ; DARWIN-32-PIC: calll L98$pb ; DARWIN-32-PIC-NEXT: L98$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl _lptr-L98$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _lptr-L98$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: addl $64, %eax ; DARWIN-32-PIC-NEXT: ret @@ -6480,9 +6491,9 @@ entry: ; DARWIN-32-PIC: _bam00: ; DARWIN-32-PIC: calll L99$pb ; DARWIN-32-PIC-NEXT: L99$pb: -; DARWIN-32-PIC-NEXT: popl %ecx +; DARWIN-32-PIC-NEXT: popl [[ECX:%e.x]] ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl L_src$non_lazy_ptr-L99$pb(%ecx), %eax +; DARWIN-32-PIC-NEXT: addl L_src$non_lazy_ptr-L99$pb([[ECX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam00: @@ -6533,9 +6544,9 @@ entry: ; DARWIN-32-PIC: _bam01: ; DARWIN-32-PIC: calll L100$pb ; DARWIN-32-PIC-NEXT: L100$pb: -; DARWIN-32-PIC-NEXT: popl %ecx +; DARWIN-32-PIC-NEXT: popl [[ECX:%e.x]] ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L100$pb(%ecx), %eax +; DARWIN-32-PIC-NEXT: addl L_dst$non_lazy_ptr-L100$pb([[ECX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam01: @@ -6586,9 +6597,9 @@ entry: ; DARWIN-32-PIC: _bxm01: ; DARWIN-32-PIC: calll L101$pb ; DARWIN-32-PIC-NEXT: L101$pb: -; DARWIN-32-PIC-NEXT: popl %ecx +; DARWIN-32-PIC-NEXT: popl [[ECX:%e.x]] ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-L101$pb(%ecx), %eax +; DARWIN-32-PIC-NEXT: addl L_xdst$non_lazy_ptr-L101$pb([[ECX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bxm01: @@ -6629,9 +6640,9 @@ entry: ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: bam02: -; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), %rcx +; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]] ; LINUX-64-PIC-NEXT: movl $262144, %eax -; LINUX-64-PIC-NEXT: addq (%rcx), %rax +; LINUX-64-PIC-NEXT: addq ([[RCX]]), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _bam02: @@ -6640,36 +6651,36 @@ entry: ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _bam02: -; DARWIN-32-DYNAMIC: movl L_ptr$non_lazy_ptr, %ecx +; DARWIN-32-DYNAMIC: movl L_ptr$non_lazy_ptr, [[ECX:%e.x]] ; DARWIN-32-DYNAMIC-NEXT: movl $262144, %eax -; DARWIN-32-DYNAMIC-NEXT: addl (%ecx), %eax +; DARWIN-32-DYNAMIC-NEXT: addl ([[ECX]]), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _bam02: ; DARWIN-32-PIC: calll L102$pb ; DARWIN-32-PIC-NEXT: L102$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L102$pb(%eax), %ecx +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L102$pb([[EAX]]), [[ECX:%e.x]] ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl (%ecx), %eax +; DARWIN-32-PIC-NEXT: addl ([[ECX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam02: -; DARWIN-64-STATIC: movq _ptr@GOTPCREL(%rip), %rcx +; DARWIN-64-STATIC: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] ; DARWIN-64-STATIC-NEXT: movl $262144, %eax -; DARWIN-64-STATIC-NEXT: addq (%rcx), %rax +; DARWIN-64-STATIC-NEXT: addq ([[RCX]]), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _bam02: -; DARWIN-64-DYNAMIC: movq _ptr@GOTPCREL(%rip), %rcx +; DARWIN-64-DYNAMIC: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] ; DARWIN-64-DYNAMIC-NEXT: movl $262144, %eax -; DARWIN-64-DYNAMIC-NEXT: addq (%rcx), %rax +; DARWIN-64-DYNAMIC-NEXT: addq ([[RCX]]), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _bam02: -; DARWIN-64-PIC: movq _ptr@GOTPCREL(%rip), %rcx +; DARWIN-64-PIC: movq _ptr@GOTPCREL(%rip), [[RCX:%r.x]] ; DARWIN-64-PIC-NEXT: movl $262144, %eax -; DARWIN-64-PIC-NEXT: addq (%rcx), %rax +; DARWIN-64-PIC-NEXT: addq ([[RCX]]), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -6704,8 +6715,8 @@ entry: ; DARWIN-32-PIC: _bam03: ; DARWIN-32-PIC: calll L103$pb ; DARWIN-32-PIC-NEXT: L103$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_dsrc-L103$pb)+262144(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_dsrc-L103$pb)+262144([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam03: @@ -6752,8 +6763,8 @@ entry: ; DARWIN-32-PIC: _bam04: ; DARWIN-32-PIC: calll L104$pb ; DARWIN-32-PIC-NEXT: L104$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ddst-L104$pb)+262144(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_ddst-L104$pb)+262144([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam04: @@ -6791,9 +6802,9 @@ entry: ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: bam05: -; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), %rcx +; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]] ; LINUX-64-PIC-NEXT: movl $262144, %eax -; LINUX-64-PIC-NEXT: addq (%rcx), %rax +; LINUX-64-PIC-NEXT: addq ([[RCX]]), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _bam05: @@ -6809,9 +6820,9 @@ entry: ; DARWIN-32-PIC: _bam05: ; DARWIN-32-PIC: calll L105$pb ; DARWIN-32-PIC-NEXT: L105$pb: -; DARWIN-32-PIC-NEXT: popl %ecx +; DARWIN-32-PIC-NEXT: popl [[ECX:%e.x]] ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl _dptr-L105$pb(%ecx), %eax +; DARWIN-32-PIC-NEXT: addl _dptr-L105$pb([[ECX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam05: @@ -6860,8 +6871,8 @@ entry: ; DARWIN-32-PIC: _bam06: ; DARWIN-32-PIC: calll L106$pb ; DARWIN-32-PIC-NEXT: L106$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_lsrc-L106$pb)+262144(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_lsrc-L106$pb)+262144([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam06: @@ -6908,7 +6919,7 @@ entry: ; DARWIN-32-PIC: calll L107$pb ; DARWIN-32-PIC-NEXT: L107$pb: ; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal (_ldst-L107$pb)+262144(%eax), %eax +; DARWIN-32-PIC-NEXT: leal (_ldst-L107$pb)+262144([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam07: @@ -6963,9 +6974,9 @@ entry: ; DARWIN-32-PIC: _bam08: ; DARWIN-32-PIC: calll L108$pb ; DARWIN-32-PIC-NEXT: L108$pb: -; DARWIN-32-PIC-NEXT: popl %ecx +; DARWIN-32-PIC-NEXT: popl [[ECX:%e.x]] ; DARWIN-32-PIC-NEXT: movl $262144, %eax -; DARWIN-32-PIC-NEXT: addl _lptr-L108$pb(%ecx), %eax +; DARWIN-32-PIC-NEXT: addl _lptr-L108$pb([[ECX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _bam08: @@ -6995,53 +7006,53 @@ entry: ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cat00: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal src+64(,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal src+64(,[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cat00: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal src+64(,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal src+64(,[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cat00: -; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cat00: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _src+64(,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _src+64(,[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cat00: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: leal 64(%ecx,%eax,4), %eax +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat00: ; DARWIN-32-PIC: calll L109$pb ; DARWIN-32-PIC-NEXT: L109$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L109$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L109$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal 64([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat00: -; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cat00: -; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cat00: -; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -7056,53 +7067,53 @@ entry: ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cxt00: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal xsrc+64(,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal xsrc+64(,[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cxt00: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal xsrc+64(,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal xsrc+64(,[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cxt00: -; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cxt00: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _xsrc+64(,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _xsrc+64(,[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cxt00: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_xsrc$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: leal 64(%ecx,%eax,4), %eax +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_xsrc$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cxt00: ; DARWIN-32-PIC: calll L110$pb ; DARWIN-32-PIC-NEXT: L110$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L110$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L110$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal 64([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cxt00: -; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cxt00: -; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cxt00: -; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -7117,53 +7128,53 @@ entry: ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cat01: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal dst+64(,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal dst+64(,[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cat01: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal dst+64(,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal dst+64(,[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cat01: -; LINUX-64-PIC: movq dst@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; LINUX-64-PIC: movq dst@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cat01: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _dst+64(,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _dst+64(,[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cat01: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: leal 64(%ecx,%eax,4), %eax +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat01: ; DARWIN-32-PIC: calll L111$pb ; DARWIN-32-PIC-NEXT: L111$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L111$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L111$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal 64([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat01: -; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cat01: -; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cat01: -; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -7178,53 +7189,53 @@ entry: ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cxt01: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal xdst+64(,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal xdst+64(,[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cxt01: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal xdst+64(,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal xdst+64(,[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cxt01: -; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cxt01: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _xdst+64(,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _xdst+64(,[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cxt01: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: leal 64(%ecx,%eax,4), %eax +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cxt01: ; DARWIN-32-PIC: calll L112$pb ; DARWIN-32-PIC-NEXT: L112$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L112$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L112$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal 64([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cxt01: -; DARWIN-64-STATIC: movq _xdst@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: movq _xdst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cxt01: -; DARWIN-64-DYNAMIC: movq _xdst@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: movq _xdst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cxt01: -; DARWIN-64-PIC: movq _xdst@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-PIC: movq _xdst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -7236,67 +7247,67 @@ entry: %3 = bitcast i32* %2 to i8* ret i8* %3 ; LINUX-64-STATIC: cat02: -; LINUX-64-STATIC: movq ptr(%rip), %rax -; LINUX-64-STATIC: leaq 64(%rax,%rdi,4), %rax +; LINUX-64-STATIC: movq ptr(%rip), [[RAX:%r.x]] +; LINUX-64-STATIC: leaq 64([[RAX]],%rdi,4), %rax ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cat02: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl ptr, %ecx -; LINUX-32-STATIC-NEXT: leal 64(%ecx,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl ptr, [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cat02: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl ptr, %ecx -; LINUX-32-PIC-NEXT: leal 64(%ecx,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl ptr, [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cat02: -; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movq (%rax), %rax -; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RAX]]), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cat02: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _ptr, %ecx -; DARWIN-32-STATIC-NEXT: leal 64(%ecx,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _ptr, [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cat02: -; DARWIN-32-DYNAMIC: movl L_ptr$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: movl (%eax), %eax -; DARWIN-32-DYNAMIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-DYNAMIC-NEXT: leal 64(%eax,%ecx,4), %eax +; DARWIN-32-DYNAMIC: movl L_ptr$non_lazy_ptr, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal 64([[EAX]],[[ECX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat02: ; DARWIN-32-PIC: calll L113$pb ; DARWIN-32-PIC-NEXT: L113$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L113$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl (%eax), %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L113$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl ([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: leal 64([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat02: -; DARWIN-64-STATIC: movq _ptr@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movq (%rax), %rax -; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: movq _ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq ([[RAX]]), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cat02: -; DARWIN-64-DYNAMIC: movq _ptr@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movq (%rax), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: movq _ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq ([[RAX]]), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cat02: -; DARWIN-64-PIC: movq _ptr@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movq (%rax), %rax -; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-PIC: movq _ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq ([[RAX]]), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -7311,51 +7322,51 @@ entry: ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cat03: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal dsrc+64(,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal dsrc+64(,[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cat03: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal dsrc+64(,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal dsrc+64(,[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cat03: -; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cat03: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _dsrc+64(,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _dsrc+64(,[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cat03: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: leal _dsrc+64(,%eax,4), %eax +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal _dsrc+64(,[[EAX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat03: ; DARWIN-32-PIC: calll L114$pb ; DARWIN-32-PIC-NEXT: L114$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_dsrc-L114$pb)+64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_dsrc-L114$pb)+64([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat03: -; DARWIN-64-STATIC: leaq _dsrc(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cat03: -; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cat03: -; DARWIN-64-PIC: leaq _dsrc(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-PIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -7370,51 +7381,51 @@ entry: ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cat04: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal ddst+64(,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal ddst+64(,[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cat04: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal ddst+64(,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal ddst+64(,[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cat04: -; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cat04: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _ddst+64(,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _ddst+64(,[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cat04: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: leal _ddst+64(,%eax,4), %eax +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal _ddst+64(,[[EAX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat04: ; DARWIN-32-PIC: calll L115$pb ; DARWIN-32-PIC-NEXT: L115$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ddst-L115$pb)+64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_ddst-L115$pb)+64([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat04: -; DARWIN-64-STATIC: leaq _ddst(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: leaq _ddst(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cat04: -; DARWIN-64-DYNAMIC: leaq _ddst(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: leaq _ddst(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cat04: -; DARWIN-64-PIC: leaq _ddst(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-PIC: leaq _ddst(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -7426,62 +7437,62 @@ entry: %3 = bitcast i32* %2 to i8* ret i8* %3 ; LINUX-64-STATIC: cat05: -; LINUX-64-STATIC: movq dptr(%rip), %rax -; LINUX-64-STATIC: leaq 64(%rax,%rdi,4), %rax +; LINUX-64-STATIC: movq dptr(%rip), [[RAX:%r.x]] +; LINUX-64-STATIC: leaq 64([[RAX]],%rdi,4), %rax ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cat05: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl dptr, %ecx -; LINUX-32-STATIC-NEXT: leal 64(%ecx,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl dptr, [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cat05: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl dptr, %ecx -; LINUX-32-PIC-NEXT: leal 64(%ecx,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl dptr, [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cat05: -; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movq (%rax), %rax -; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RAX]]), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cat05: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _dptr, %ecx -; DARWIN-32-STATIC-NEXT: leal 64(%ecx,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _dptr, [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cat05: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl _dptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: leal 64(%ecx,%eax,4), %eax +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _dptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat05: ; DARWIN-32-PIC: calll L116$pb ; DARWIN-32-PIC-NEXT: L116$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _dptr-L116$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _dptr-L116$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal 64([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat05: -; DARWIN-64-STATIC: movq _dptr(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: movq _dptr(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cat05: -; DARWIN-64-DYNAMIC: movq _dptr(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: movq _dptr(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cat05: -; DARWIN-64-PIC: movq _dptr(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-PIC: movq _dptr(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -7496,51 +7507,51 @@ entry: ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cat06: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal lsrc+64(,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal lsrc+64(,[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cat06: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal lsrc+64(,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal lsrc+64(,[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cat06: -; LINUX-64-PIC: leaq lsrc(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; LINUX-64-PIC: leaq lsrc(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cat06: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _lsrc+64(,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _lsrc+64(,[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cat06: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: leal _lsrc+64(,%eax,4), %eax +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal _lsrc+64(,[[EAX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat06: ; DARWIN-32-PIC: calll L117$pb ; DARWIN-32-PIC-NEXT: L117$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_lsrc-L117$pb)+64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_lsrc-L117$pb)+64([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat06: -; DARWIN-64-STATIC: leaq _lsrc(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cat06: -; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cat06: -; DARWIN-64-PIC: leaq _lsrc(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-PIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -7555,51 +7566,51 @@ entry: ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cat07: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal ldst+64(,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal ldst+64(,[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cat07: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal ldst+64(,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal ldst+64(,[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cat07: -; LINUX-64-PIC: leaq ldst(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; LINUX-64-PIC: leaq ldst(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cat07: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _ldst+64(,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _ldst+64(,[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cat07: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: leal _ldst+64(,%eax,4), %eax +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal _ldst+64(,[[EAX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat07: ; DARWIN-32-PIC: calll L118$pb ; DARWIN-32-PIC-NEXT: L118$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ldst-L118$pb)+64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_ldst-L118$pb)+64([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat07: -; DARWIN-64-STATIC: leaq _ldst(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: leaq _ldst(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cat07: -; DARWIN-64-DYNAMIC: leaq _ldst(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: leaq _ldst(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cat07: -; DARWIN-64-PIC: leaq _ldst(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-PIC: leaq _ldst(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -7611,61 +7622,61 @@ entry: %3 = bitcast i32* %2 to i8* ret i8* %3 ; LINUX-64-STATIC: cat08: -; LINUX-64-STATIC: movq lptr(%rip), %rax -; LINUX-64-STATIC: leaq 64(%rax,%rdi,4), %rax +; LINUX-64-STATIC: movq lptr(%rip), [[RAX:%r.x]] +; LINUX-64-STATIC: leaq 64([[RAX]],%rdi,4), %rax ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cat08: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl lptr, %ecx -; LINUX-32-STATIC-NEXT: leal 64(%ecx,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl lptr, [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cat08: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl lptr, %ecx -; LINUX-32-PIC-NEXT: leal 64(%ecx,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl lptr, [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cat08: -; LINUX-64-PIC: movq lptr(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; LINUX-64-PIC: movq lptr(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cat08: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _lptr, %ecx -; DARWIN-32-STATIC-NEXT: leal 64(%ecx,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _lptr, [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cat08: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl _lptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: leal 64(%ecx,%eax,4), %eax +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _lptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cat08: ; DARWIN-32-PIC: calll L119$pb ; DARWIN-32-PIC-NEXT: L119$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _lptr-L119$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: leal 64(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _lptr-L119$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal 64([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cat08: -; DARWIN-64-STATIC: movq _lptr(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: movq _lptr(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cat08: -; DARWIN-64-DYNAMIC: movq _lptr(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: movq _lptr(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cat08: -; DARWIN-64-PIC: movq _lptr(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 64(%rax,%rdi,4), %rax +; DARWIN-64-PIC: movq _lptr(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -7680,53 +7691,53 @@ entry: ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cam00: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal src+262144(,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal src+262144(,[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cam00: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal src+262144(,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal src+262144(,[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cam00: -; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cam00: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _src+262144(,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _src+262144(,[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cam00: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: leal 262144(%ecx,%eax,4), %eax +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_src$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam00: ; DARWIN-32-PIC: calll L120$pb ; DARWIN-32-PIC-NEXT: L120$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L120$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L120$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal 262144([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam00: -; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cam00: -; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cam00: -; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-PIC: movq _src@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -7741,53 +7752,53 @@ entry: ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cxm00: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal xsrc+262144(,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal xsrc+262144(,[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cxm00: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal xsrc+262144(,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal xsrc+262144(,[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cxm00: -; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cxm00: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _xsrc+262144(,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _xsrc+262144(,[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cxm00: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_xsrc$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: leal 262144(%ecx,%eax,4), %eax +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_xsrc$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cxm00: ; DARWIN-32-PIC: calll L121$pb ; DARWIN-32-PIC-NEXT: L121$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L121$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L121$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal 262144([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cxm00: -; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cxm00: -; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cxm00: -; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-PIC: movq _xsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -7802,53 +7813,53 @@ entry: ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cam01: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal dst+262144(,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal dst+262144(,[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cam01: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal dst+262144(,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal dst+262144(,[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cam01: -; LINUX-64-PIC: movq dst@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; LINUX-64-PIC: movq dst@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cam01: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _dst+262144(,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _dst+262144(,[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cam01: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: leal 262144(%ecx,%eax,4), %eax +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam01: ; DARWIN-32-PIC: calll L122$pb ; DARWIN-32-PIC-NEXT: L122$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L122$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_dst$non_lazy_ptr-L122$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal 262144([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam01: -; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: movq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cam01: -; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: movq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cam01: -; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-PIC: movq _dst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -7864,52 +7875,52 @@ entry: ; LINUX-32-STATIC: cxm01: ; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal xdst+262144(,%eax,4), %eax +; LINUX-32-STATIC-NEXT: leal xdst+262144(,[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cxm01: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal xdst+262144(,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal xdst+262144(,[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cxm01: -; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cxm01: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _xdst+262144(,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _xdst+262144(,[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cxm01: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: leal 262144(%ecx,%eax,4), %eax +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cxm01: ; DARWIN-32-PIC: calll L123$pb ; DARWIN-32-PIC-NEXT: L123$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L123$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_xdst$non_lazy_ptr-L123$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal 262144([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cxm01: -; DARWIN-64-STATIC: movq _xdst@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: movq _xdst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cxm01: -; DARWIN-64-DYNAMIC: movq _xdst@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: movq _xdst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cxm01: -; DARWIN-64-PIC: movq _xdst@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-PIC: movq _xdst@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -7921,67 +7932,67 @@ entry: %3 = bitcast i32* %2 to i8* ret i8* %3 ; LINUX-64-STATIC: cam02: -; LINUX-64-STATIC: movq ptr(%rip), %rax -; LINUX-64-STATIC: leaq 262144(%rax,%rdi,4), %rax +; LINUX-64-STATIC: movq ptr(%rip), [[RAX:%r.x]] +; LINUX-64-STATIC: leaq 262144([[RAX]],%rdi,4), %rax ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cam02: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl ptr, %ecx -; LINUX-32-STATIC-NEXT: leal 262144(%ecx,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl ptr, [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cam02: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl ptr, %ecx -; LINUX-32-PIC-NEXT: leal 262144(%ecx,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl ptr, [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cam02: -; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movq (%rax), %rax -; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RAX]]), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cam02: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _ptr, %ecx -; DARWIN-32-STATIC-NEXT: leal 262144(%ecx,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _ptr, [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cam02: -; DARWIN-32-DYNAMIC: movl L_ptr$non_lazy_ptr, %eax -; DARWIN-32-DYNAMIC-NEXT: movl (%eax), %eax -; DARWIN-32-DYNAMIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-DYNAMIC-NEXT: leal 262144(%eax,%ecx,4), %eax +; DARWIN-32-DYNAMIC: movl L_ptr$non_lazy_ptr, [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl ([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal 262144([[EAX]],[[ECX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam02: ; DARWIN-32-PIC: calll L124$pb ; DARWIN-32-PIC-NEXT: L124$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L124$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: movl (%eax), %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ptr$non_lazy_ptr-L124$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl ([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: leal 262144([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam02: -; DARWIN-64-STATIC: movq _ptr@GOTPCREL(%rip), %rax -; DARWIN-64-STATIC-NEXT: movq (%rax), %rax -; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: movq _ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq ([[RAX]]), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cam02: -; DARWIN-64-DYNAMIC: movq _ptr@GOTPCREL(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: movq (%rax), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: movq _ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq ([[RAX]]), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cam02: -; DARWIN-64-PIC: movq _ptr@GOTPCREL(%rip), %rax -; DARWIN-64-PIC-NEXT: movq (%rax), %rax -; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-PIC: movq _ptr@GOTPCREL(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: movq ([[RAX]]), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -7996,51 +8007,51 @@ entry: ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cam03: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal dsrc+262144(,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal dsrc+262144(,[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cam03: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal dsrc+262144(,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal dsrc+262144(,[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cam03: -; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cam03: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _dsrc+262144(,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _dsrc+262144(,[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cam03: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: leal _dsrc+262144(,%eax,4), %eax +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal _dsrc+262144(,[[EAX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam03: ; DARWIN-32-PIC: calll L125$pb ; DARWIN-32-PIC-NEXT: L125$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_dsrc-L125$pb)+262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_dsrc-L125$pb)+262144([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam03: -; DARWIN-64-STATIC: leaq _dsrc(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cam03: -; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cam03: -; DARWIN-64-PIC: leaq _dsrc(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-PIC: leaq _dsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -8055,51 +8066,51 @@ entry: ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cam04: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal ddst+262144(,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal ddst+262144(,[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cam04: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal ddst+262144(,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal ddst+262144(,[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cam04: -; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cam04: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _ddst+262144(,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _ddst+262144(,[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cam04: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: leal _ddst+262144(,%eax,4), %eax +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal _ddst+262144(,[[EAX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam04: ; DARWIN-32-PIC: calll L126$pb ; DARWIN-32-PIC-NEXT: L126$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ddst-L126$pb)+262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_ddst-L126$pb)+262144([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam04: -; DARWIN-64-STATIC: leaq _ddst(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: leaq _ddst(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cam04: -; DARWIN-64-DYNAMIC: leaq _ddst(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: leaq _ddst(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cam04: -; DARWIN-64-PIC: leaq _ddst(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-PIC: leaq _ddst(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -8111,62 +8122,62 @@ entry: %3 = bitcast i32* %2 to i8* ret i8* %3 ; LINUX-64-STATIC: cam05: -; LINUX-64-STATIC: movq dptr(%rip), %rax -; LINUX-64-STATIC: leaq 262144(%rax,%rdi,4), %rax +; LINUX-64-STATIC: movq dptr(%rip), [[RAX:%r.x]] +; LINUX-64-STATIC: leaq 262144([[RAX]],%rdi,4), %rax ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cam05: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl dptr, %ecx -; LINUX-32-STATIC-NEXT: leal 262144(%ecx,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl dptr, [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cam05: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl dptr, %ecx -; LINUX-32-PIC-NEXT: leal 262144(%ecx,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl dptr, [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cam05: -; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: movq (%rax), %rax -; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: movq ([[RAX]]), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cam05: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _dptr, %ecx -; DARWIN-32-STATIC-NEXT: leal 262144(%ecx,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _dptr, [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cam05: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl _dptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: leal 262144(%ecx,%eax,4), %eax +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _dptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam05: ; DARWIN-32-PIC: calll L127$pb ; DARWIN-32-PIC-NEXT: L127$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _dptr-L127$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _dptr-L127$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal 262144([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam05: -; DARWIN-64-STATIC: movq _dptr(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: movq _dptr(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cam05: -; DARWIN-64-DYNAMIC: movq _dptr(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: movq _dptr(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cam05: -; DARWIN-64-PIC: movq _dptr(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-PIC: movq _dptr(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -8181,51 +8192,51 @@ entry: ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cam06: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal lsrc+262144(,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal lsrc+262144(,[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cam06: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal lsrc+262144(,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal lsrc+262144(,[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cam06: -; LINUX-64-PIC: leaq lsrc(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; LINUX-64-PIC: leaq lsrc(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cam06: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _lsrc+262144(,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _lsrc+262144(,[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cam06: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: leal _lsrc+262144(,%eax,4), %eax +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal _lsrc+262144(,[[EAX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam06: ; DARWIN-32-PIC: calll L128$pb ; DARWIN-32-PIC-NEXT: L128$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_lsrc-L128$pb)+262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_lsrc-L128$pb)+262144([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam06: -; DARWIN-64-STATIC: leaq _lsrc(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cam06: -; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cam06: -; DARWIN-64-PIC: leaq _lsrc(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-PIC: leaq _lsrc(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -8240,51 +8251,51 @@ entry: ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cam07: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: leal ldst+262144(,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: leal ldst+262144(,[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cam07: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: leal ldst+262144(,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: leal ldst+262144(,[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cam07: -; LINUX-64-PIC: leaq ldst(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; LINUX-64-PIC: leaq ldst(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cam07: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: leal _ldst+262144(,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal _ldst+262144(,[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cam07: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: leal _ldst+262144(,%eax,4), %eax +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal _ldst+262144(,[[EAX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam07: ; DARWIN-32-PIC: calll L129$pb ; DARWIN-32-PIC-NEXT: L129$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: leal (_ldst-L129$pb)+262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: leal (_ldst-L129$pb)+262144([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam07: -; DARWIN-64-STATIC: leaq _ldst(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: leaq _ldst(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cam07: -; DARWIN-64-DYNAMIC: leaq _ldst(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: leaq _ldst(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cam07: -; DARWIN-64-PIC: leaq _ldst(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-PIC: leaq _ldst(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -8296,61 +8307,61 @@ entry: %3 = bitcast i32* %2 to i8* ret i8* %3 ; LINUX-64-STATIC: cam08: -; LINUX-64-STATIC: movq lptr(%rip), %rax -; LINUX-64-STATIC: leaq 262144(%rax,%rdi,4), %rax +; LINUX-64-STATIC: movq lptr(%rip), [[RAX:%r.x]] +; LINUX-64-STATIC: leaq 262144([[RAX]],%rdi,4), %rax ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: cam08: -; LINUX-32-STATIC: movl 4(%esp), %eax -; LINUX-32-STATIC-NEXT: movl lptr, %ecx -; LINUX-32-STATIC-NEXT: leal 262144(%ecx,%eax,4), %eax +; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-STATIC-NEXT: movl lptr, [[ECX:%e.x]] +; LINUX-32-STATIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: cam08: -; LINUX-32-PIC: movl 4(%esp), %eax -; LINUX-32-PIC-NEXT: movl lptr, %ecx -; LINUX-32-PIC-NEXT: leal 262144(%ecx,%eax,4), %eax +; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]] +; LINUX-32-PIC-NEXT: movl lptr, [[ECX:%e.x]] +; LINUX-32-PIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: cam08: -; LINUX-64-PIC: movq lptr(%rip), %rax -; LINUX-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; LINUX-64-PIC: movq lptr(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _cam08: -; DARWIN-32-STATIC: movl 4(%esp), %eax -; DARWIN-32-STATIC-NEXT: movl _lptr, %ecx -; DARWIN-32-STATIC-NEXT: leal 262144(%ecx,%eax,4), %eax +; DARWIN-32-STATIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-STATIC-NEXT: movl _lptr, [[ECX:%e.x]] +; DARWIN-32-STATIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax ; DARWIN-32-STATIC-NEXT: ret ; DARWIN-32-DYNAMIC: _cam08: -; DARWIN-32-DYNAMIC: movl 4(%esp), %eax -; DARWIN-32-DYNAMIC-NEXT: movl _lptr, %ecx -; DARWIN-32-DYNAMIC-NEXT: leal 262144(%ecx,%eax,4), %eax +; DARWIN-32-DYNAMIC: movl 4(%esp), [[EAX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: movl _lptr, [[ECX:%e.x]] +; DARWIN-32-DYNAMIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax ; DARWIN-32-DYNAMIC-NEXT: ret ; DARWIN-32-PIC: _cam08: ; DARWIN-32-PIC: calll L130$pb ; DARWIN-32-PIC-NEXT: L130$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl 4(%esp), %ecx -; DARWIN-32-PIC-NEXT: movl _lptr-L130$pb(%eax), %eax -; DARWIN-32-PIC-NEXT: leal 262144(%eax,%ecx,4), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl 4(%esp), [[ECX:%e.x]] +; DARWIN-32-PIC-NEXT: movl _lptr-L130$pb([[EAX]]), [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal 262144([[EAX]],[[ECX]],4), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _cam08: -; DARWIN-64-STATIC: movq _lptr(%rip), %rax -; DARWIN-64-STATIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-STATIC: movq _lptr(%rip), [[RAX:%r.x]] +; DARWIN-64-STATIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _cam08: -; DARWIN-64-DYNAMIC: movq _lptr(%rip), %rax -; DARWIN-64-DYNAMIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-DYNAMIC: movq _lptr(%rip), [[RAX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _cam08: -; DARWIN-64-PIC: movq _lptr(%rip), %rax -; DARWIN-64-PIC-NEXT: leaq 262144(%rax,%rdi,4), %rax +; DARWIN-64-PIC: movq _lptr(%rip), [[RAX:%r.x]] +; DARWIN-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax ; DARWIN-64-PIC-NEXT: ret } @@ -8648,8 +8659,8 @@ entry: ; DARWIN-32-PIC: _address: ; DARWIN-32-PIC: calll L133$pb ; DARWIN-32-PIC-NEXT: L133$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_callee$non_lazy_ptr-L133$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_callee$non_lazy_ptr-L133$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _address: @@ -8697,8 +8708,8 @@ entry: ; DARWIN-32-PIC: _laddress: ; DARWIN-32-PIC: calll L134$pb ; DARWIN-32-PIC-NEXT: L134$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _lcallee-L134$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal _lcallee-L134$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _laddress: @@ -8744,8 +8755,8 @@ entry: ; DARWIN-32-PIC: _daddress: ; DARWIN-32-PIC: calll L135$pb ; DARWIN-32-PIC-NEXT: L135$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: leal _dcallee-L135$pb(%eax), %eax +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: leal _dcallee-L135$pb([[EAX]]), %eax ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _daddress: @@ -9206,11 +9217,11 @@ entry: ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: icaller: -; LINUX-64-PIC: pushq %rbx -; LINUX-64-PIC-NEXT: movq ifunc@GOTPCREL(%rip), %rbx -; LINUX-64-PIC-NEXT: callq *(%rbx) -; LINUX-64-PIC-NEXT: callq *(%rbx) -; LINUX-64-PIC-NEXT: popq %rbx +; LINUX-64-PIC: pushq [[RBX:%r.x]] +; LINUX-64-PIC-NEXT: movq ifunc@GOTPCREL(%rip), [[RBX:%r.x]] +; LINUX-64-PIC-NEXT: callq *([[RBX]]) +; LINUX-64-PIC-NEXT: callq *([[RBX]]) +; LINUX-64-PIC-NEXT: popq [[RBX:%r.x]] ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _icaller: @@ -9235,8 +9246,8 @@ entry: ; DARWIN-32-PIC-NEXT: subl $8, %esp ; DARWIN-32-PIC-NEXT: calll L142$pb ; DARWIN-32-PIC-NEXT: L142$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-L142$pb(%eax), %esi +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-L142$pb([[EAX]]), %esi ; DARWIN-32-PIC-NEXT: calll *(%esi) ; DARWIN-32-PIC-NEXT: calll *(%esi) ; DARWIN-32-PIC-NEXT: addl $8, %esp @@ -9244,27 +9255,27 @@ entry: ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _icaller: -; DARWIN-64-STATIC: pushq %rbx -; DARWIN-64-STATIC-NEXT: movq _ifunc@GOTPCREL(%rip), %rbx -; DARWIN-64-STATIC-NEXT: callq *(%rbx) -; DARWIN-64-STATIC-NEXT: callq *(%rbx) -; DARWIN-64-STATIC-NEXT: popq %rbx +; DARWIN-64-STATIC: pushq [[RBX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq _ifunc@GOTPCREL(%rip), [[RBX:%r.x]] +; DARWIN-64-STATIC-NEXT: callq *([[RBX]]) +; DARWIN-64-STATIC-NEXT: callq *([[RBX]]) +; DARWIN-64-STATIC-NEXT: popq [[RBX:%r.x]] ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _icaller: -; DARWIN-64-DYNAMIC: pushq %rbx -; DARWIN-64-DYNAMIC-NEXT: movq _ifunc@GOTPCREL(%rip), %rbx -; DARWIN-64-DYNAMIC-NEXT: callq *(%rbx) -; DARWIN-64-DYNAMIC-NEXT: callq *(%rbx) -; DARWIN-64-DYNAMIC-NEXT: popq %rbx +; DARWIN-64-DYNAMIC: pushq [[RBX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _ifunc@GOTPCREL(%rip), [[RBX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: callq *([[RBX]]) +; DARWIN-64-DYNAMIC-NEXT: callq *([[RBX]]) +; DARWIN-64-DYNAMIC-NEXT: popq [[RBX:%r.x]] ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _icaller: -; DARWIN-64-PIC: pushq %rbx -; DARWIN-64-PIC-NEXT: movq _ifunc@GOTPCREL(%rip), %rbx -; DARWIN-64-PIC-NEXT: callq *(%rbx) -; DARWIN-64-PIC-NEXT: callq *(%rbx) -; DARWIN-64-PIC-NEXT: popq %rbx +; DARWIN-64-PIC: pushq [[RBX:%r.x]] +; DARWIN-64-PIC-NEXT: movq _ifunc@GOTPCREL(%rip), [[RBX:%r.x]] +; DARWIN-64-PIC-NEXT: callq *([[RBX]]) +; DARWIN-64-PIC-NEXT: callq *([[RBX]]) +; DARWIN-64-PIC-NEXT: popq [[RBX:%r.x]] ; DARWIN-64-PIC-NEXT: ret } @@ -9296,11 +9307,11 @@ entry: ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: dicaller: -; LINUX-64-PIC: pushq %rbx -; LINUX-64-PIC-NEXT: movq difunc@GOTPCREL(%rip), %rbx -; LINUX-64-PIC-NEXT: callq *(%rbx) -; LINUX-64-PIC-NEXT: callq *(%rbx) -; LINUX-64-PIC-NEXT: popq %rbx +; LINUX-64-PIC: pushq [[RBX:%r.x]] +; LINUX-64-PIC-NEXT: movq difunc@GOTPCREL(%rip), [[RBX:%r.x]] +; LINUX-64-PIC-NEXT: callq *([[RBX]]) +; LINUX-64-PIC-NEXT: callq *([[RBX]]) +; LINUX-64-PIC-NEXT: popq [[RBX:%r.x]] ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _dicaller: @@ -9461,11 +9472,11 @@ entry: ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: itailcaller: -; LINUX-64-PIC: pushq %rbx -; LINUX-64-PIC-NEXT: movq ifunc@GOTPCREL(%rip), %rbx -; LINUX-64-PIC-NEXT: callq *(%rbx) -; LINUX-64-PIC-NEXT: callq *(%rbx) -; LINUX-64-PIC-NEXT: popq %rbx +; LINUX-64-PIC: pushq [[RBX:%r.x]] +; LINUX-64-PIC-NEXT: movq ifunc@GOTPCREL(%rip), [[RBX:%r.x]] +; LINUX-64-PIC-NEXT: callq *([[RBX]]) +; LINUX-64-PIC-NEXT: callq *([[RBX]]) +; LINUX-64-PIC-NEXT: popq [[RBX:%r.x]] ; LINUX-64-PIC-NEXT: ret ; DARWIN-32-STATIC: _itailcaller: @@ -9490,8 +9501,8 @@ entry: ; DARWIN-32-PIC-NEXT: subl $8, %esp ; DARWIN-32-PIC-NEXT: calll L145$pb ; DARWIN-32-PIC-NEXT: L145$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-L145$pb(%eax), %esi +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: movl L_ifunc$non_lazy_ptr-L145$pb([[EAX]]), %esi ; DARWIN-32-PIC-NEXT: calll *(%esi) ; DARWIN-32-PIC-NEXT: calll *(%esi) ; DARWIN-32-PIC-NEXT: addl $8, %esp @@ -9499,27 +9510,27 @@ entry: ; DARWIN-32-PIC-NEXT: ret ; DARWIN-64-STATIC: _itailcaller: -; DARWIN-64-STATIC: pushq %rbx -; DARWIN-64-STATIC-NEXT: movq _ifunc@GOTPCREL(%rip), %rbx -; DARWIN-64-STATIC-NEXT: callq *(%rbx) -; DARWIN-64-STATIC-NEXT: callq *(%rbx) -; DARWIN-64-STATIC-NEXT: popq %rbx +; DARWIN-64-STATIC: pushq [[RBX:%r.x]] +; DARWIN-64-STATIC-NEXT: movq _ifunc@GOTPCREL(%rip), [[RBX:%r.x]] +; DARWIN-64-STATIC-NEXT: callq *([[RBX]]) +; DARWIN-64-STATIC-NEXT: callq *([[RBX]]) +; DARWIN-64-STATIC-NEXT: popq [[RBX:%r.x]] ; DARWIN-64-STATIC-NEXT: ret ; DARWIN-64-DYNAMIC: _itailcaller: -; DARWIN-64-DYNAMIC: pushq %rbx -; DARWIN-64-DYNAMIC-NEXT: movq _ifunc@GOTPCREL(%rip), %rbx -; DARWIN-64-DYNAMIC-NEXT: callq *(%rbx) -; DARWIN-64-DYNAMIC-NEXT: callq *(%rbx) -; DARWIN-64-DYNAMIC-NEXT: popq %rbx +; DARWIN-64-DYNAMIC: pushq [[RBX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: movq _ifunc@GOTPCREL(%rip), [[RBX:%r.x]] +; DARWIN-64-DYNAMIC-NEXT: callq *([[RBX]]) +; DARWIN-64-DYNAMIC-NEXT: callq *([[RBX]]) +; DARWIN-64-DYNAMIC-NEXT: popq [[RBX:%r.x]] ; DARWIN-64-DYNAMIC-NEXT: ret ; DARWIN-64-PIC: _itailcaller: -; DARWIN-64-PIC: pushq %rbx -; DARWIN-64-PIC-NEXT: movq _ifunc@GOTPCREL(%rip), %rbx -; DARWIN-64-PIC-NEXT: callq *(%rbx) -; DARWIN-64-PIC-NEXT: callq *(%rbx) -; DARWIN-64-PIC-NEXT: popq %rbx +; DARWIN-64-PIC: pushq [[RBX:%r.x]] +; DARWIN-64-PIC-NEXT: movq _ifunc@GOTPCREL(%rip), [[RBX:%r.x]] +; DARWIN-64-PIC-NEXT: callq *([[RBX]]) +; DARWIN-64-PIC-NEXT: callq *([[RBX]]) +; DARWIN-64-PIC-NEXT: popq [[RBX:%r.x]] ; DARWIN-64-PIC-NEXT: ret } @@ -9547,8 +9558,8 @@ entry: ; LINUX-64-PIC: ditailcaller: ; LINUX-64-PIC: pushq -; LINUX-64-PIC-NEXT: movq difunc@GOTPCREL(%rip), %rax -; LINUX-64-PIC-NEXT: callq *(%rax) +; LINUX-64-PIC-NEXT: movq difunc@GOTPCREL(%rip), [[RAX:%r.x]] +; LINUX-64-PIC-NEXT: callq *([[RAX]]) ; LINUX-64-PIC-NEXT: popq ; LINUX-64-PIC-NEXT: ret @@ -9568,8 +9579,8 @@ entry: ; DARWIN-32-PIC: subl $12, %esp ; DARWIN-32-PIC-NEXT: calll L146$pb ; DARWIN-32-PIC-NEXT: L146$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: calll *_difunc-L146$pb(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: calll *_difunc-L146$pb([[EAX]]) ; DARWIN-32-PIC-NEXT: addl $12, %esp ; DARWIN-32-PIC-NEXT: ret @@ -9635,8 +9646,8 @@ entry: ; DARWIN-32-PIC: subl $12, %esp ; DARWIN-32-PIC-NEXT: calll L147$pb ; DARWIN-32-PIC-NEXT: L147$pb: -; DARWIN-32-PIC-NEXT: popl %eax -; DARWIN-32-PIC-NEXT: calll *_lifunc-L147$pb(%eax) +; DARWIN-32-PIC-NEXT: popl [[EAX:%e.x]] +; DARWIN-32-PIC-NEXT: calll *_lifunc-L147$pb([[EAX]]) ; DARWIN-32-PIC-NEXT: addl $12, %esp ; DARWIN-32-PIC-NEXT: ret diff --git a/test/CodeGen/X86/add.ll b/test/CodeGen/X86/add.ll index 62c898025c80..b95e5b53c2dc 100644 --- a/test/CodeGen/X86/add.ll +++ b/test/CodeGen/X86/add.ll @@ -133,3 +133,18 @@ define i32 @test9(i32 %x, i32 %y) nounwind readnone { ; X64: subl ; X64: ret } + +define i1 @test10(i32 %x) nounwind { +entry: + %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %x, i32 1) + %obit = extractvalue {i32, i1} %t, 1 + ret i1 %obit + +; X32: test10: +; X32: incl +; X32-NEXT: seto + +; X64: test10: +; X64: incl +; X64-NEXT: seto +} diff --git a/test/CodeGen/X86/adde-carry.ll b/test/CodeGen/X86/adde-carry.ll new file mode 100644 index 000000000000..98c4f9934318 --- /dev/null +++ b/test/CodeGen/X86/adde-carry.ll @@ -0,0 +1,26 @@ +; RUN: llc -march=x86-64 < %s | FileCheck %s -check-prefix=CHECK-64 +; RUN: llc -march=x86 < %s | FileCheck %s -check-prefix=CHECK-32 + +define void @a(i64* nocapture %s, i64* nocapture %t, i64 %a, i64 %b, i64 %c) nounwind { +entry: + %0 = zext i64 %a to i128 + %1 = zext i64 %b to i128 + %2 = add i128 %1, %0 + %3 = zext i64 %c to i128 + %4 = shl i128 %3, 64 + %5 = add i128 %4, %2 + %6 = lshr i128 %5, 64 + %7 = trunc i128 %6 to i64 + store i64 %7, i64* %s, align 8 + %8 = trunc i128 %2 to i64 + store i64 %8, i64* %t, align 8 + ret void + +; CHECK-32: addl +; CHECK-32: adcl +; CHECK-32: adcl $0 +; CHECK-32: adcl $0 + +; CHECK-64: addq +; CHECK-64: adcq $0 +} diff --git a/test/CodeGen/X86/aliases.ll b/test/CodeGen/X86/aliases.ll index 3ed3bd67cef1..f92027998a40 100644 --- a/test/CodeGen/X86/aliases.ll +++ b/test/CodeGen/X86/aliases.ll @@ -1,6 +1,4 @@ ; RUN: llc < %s -mtriple=i686-pc-linux-gnu -asm-verbose=false -o %t -; RUN: grep { = } %t | count 16 -; RUN: grep set %t | count 18 ; RUN: grep globl %t | count 6 ; RUN: grep weak %t | count 1 ; RUN: grep hidden %t | count 1 diff --git a/test/CodeGen/X86/alignment.ll b/test/CodeGen/X86/alignment.ll index 9678e6df740e..7e911159790b 100644 --- a/test/CodeGen/X86/alignment.ll +++ b/test/CodeGen/X86/alignment.ll @@ -6,7 +6,7 @@ ; CHECK: .bss ; CHECK: .globl GlobalA -; CHECK: .align 16 +; CHECK: .align 8 ; CHECK: GlobalA: ; CHECK: .zero 384 @@ -15,12 +15,12 @@ ; PR6921 @GlobalB = common global { [384 x i8] } zeroinitializer, align 8 -; CHECK: .comm GlobalB,384,16 +; CHECK: .comm GlobalB,384,8 @GlobalC = common global { [384 x i8] } zeroinitializer, align 2 -; CHECK: .comm GlobalC,384,16 +; CHECK: .comm GlobalC,384,2 diff --git a/test/CodeGen/X86/apm.ll b/test/CodeGen/X86/apm.ll index d0c64f243386..b514cf6427d5 100644 --- a/test/CodeGen/X86/apm.ll +++ b/test/CodeGen/X86/apm.ll @@ -1,10 +1,16 @@ -; RUN: llc < %s -o - -march=x86-64 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=WIN64 ; PR8573 ; CHECK: foo: ; CHECK: leaq (%rdi), %rax ; CHECK-NEXT: movl %esi, %ecx ; CHECK-NEXT: monitor +; WIN64: foo: +; WIN64: leaq (%rcx), %rax +; WIN64-NEXT: movl %edx, %ecx +; WIN64-NEXT: movl %r8d, %edx +; WIN64-NEXT: monitor define void @foo(i8* %P, i32 %E, i32 %H) nounwind { entry: tail call void @llvm.x86.sse3.monitor(i8* %P, i32 %E, i32 %H) @@ -17,6 +23,9 @@ declare void @llvm.x86.sse3.monitor(i8*, i32, i32) nounwind ; CHECK: movl %edi, %ecx ; CHECK-NEXT: movl %esi, %eax ; CHECK-NEXT: mwait +; WIN64: bar: +; WIN64: movl %edx, %eax +; WIN64-NEXT: mwait define void @bar(i32 %E, i32 %H) nounwind { entry: tail call void @llvm.x86.sse3.mwait(i32 %E, i32 %H) diff --git a/test/CodeGen/X86/avoid-lea-scale2.ll b/test/CodeGen/X86/avoid-lea-scale2.ll index 8003de262d2c..cee2ee4e0399 100644 --- a/test/CodeGen/X86/avoid-lea-scale2.ll +++ b/test/CodeGen/X86/avoid-lea-scale2.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=x86-64 | grep {leal.*-2(\[%\]rdi,\[%\]rdi)} +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s +; CHECK: leal -2({{%rdi,%rdi|%rcx,%rcx}}) define i32 @foo(i32 %x) nounwind readnone { %t0 = shl i32 %x, 1 diff --git a/test/CodeGen/X86/avx-intrinsics-x86.ll b/test/CodeGen/X86/avx-intrinsics-x86.ll index 6c32396a4177..5201688686d3 100644 --- a/test/CodeGen/X86/avx-intrinsics-x86.ll +++ b/test/CodeGen/X86/avx-intrinsics-x86.ll @@ -247,7 +247,7 @@ declare <2 x double> @llvm.x86.sse2.div.sd(<2 x double>, <2 x double>) nounwind define <16 x i8> @test_x86_sse2_loadu_dq(i8* %a0) { ; CHECK: movl - ; CHECK: vmovdqu + ; CHECK: vmovups %res = call <16 x i8> @llvm.x86.sse2.loadu.dq(i8* %a0) ; <<16 x i8>> [#uses=1] ret <16 x i8> %res } @@ -256,7 +256,7 @@ declare <16 x i8> @llvm.x86.sse2.loadu.dq(i8*) nounwind readonly define <2 x double> @test_x86_sse2_loadu_pd(i8* %a0) { ; CHECK: movl - ; CHECK: vmovupd + ; CHECK: vmovups %res = call <2 x double> @llvm.x86.sse2.loadu.pd(i8* %a0) ; <<2 x double>> [#uses=1] ret <2 x double> %res } diff --git a/test/CodeGen/X86/bool-zext.ll b/test/CodeGen/X86/bool-zext.ll new file mode 100644 index 000000000000..d2c30c64f237 --- /dev/null +++ b/test/CodeGen/X86/bool-zext.ll @@ -0,0 +1,35 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s + +; CHECK: @bar1 +; CHECK: movzbl +; CHECK: callq +define void @bar1(i1 zeroext %v1) nounwind ssp { +entry: + %conv = zext i1 %v1 to i32 + %call = tail call i32 (...)* @foo1(i32 %conv) nounwind + ret void +} + +; CHECK: @bar2 +; CHECK-NOT: movzbl +; CHECK: callq +define void @bar2(i8 zeroext %v1) nounwind ssp { +entry: + %conv = zext i8 %v1 to i32 + %call = tail call i32 (...)* @foo1(i32 %conv) nounwind + ret void +} + +; CHECK: @bar3 +; CHECK: callq +; CHECK-NOT: movzbl +; CHECK-NOT: and +; CHECK: ret +define zeroext i1 @bar3() nounwind ssp { +entry: + %call = call i1 @foo2() nounwind + ret i1 %call +} + +declare i32 @foo1(...) +declare zeroext i1 @foo2() diff --git a/test/CodeGen/X86/break-anti-dependencies.ll b/test/CodeGen/X86/break-anti-dependencies.ll index 972b3cd43cf6..93b20437e1e8 100644 --- a/test/CodeGen/X86/break-anti-dependencies.ll +++ b/test/CodeGen/X86/break-anti-dependencies.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=x86-64 -post-RA-scheduler -break-anti-dependencies=none > %t +; Without list-burr scheduling we may not see the difference in codegen here. +; RUN: llc < %s -march=x86-64 -post-RA-scheduler -pre-RA-sched=list-burr -break-anti-dependencies=none > %t ; RUN: grep {%xmm0} %t | count 14 ; RUN: not grep {%xmm1} %t ; RUN: llc < %s -march=x86-64 -post-RA-scheduler -break-anti-dependencies=critical > %t diff --git a/test/CodeGen/X86/byval.ll b/test/CodeGen/X86/byval.ll index ac0bc094e56e..185eda1566d4 100644 --- a/test/CodeGen/X86/byval.ll +++ b/test/CodeGen/X86/byval.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=x86-64 | FileCheck -check-prefix=X86-64 %s +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck -check-prefix=X86-64 %s +; Win64 has not supported byval yet. ; RUN: llc < %s -march=x86 | FileCheck -check-prefix=X86 %s ; X86: movl 4(%esp), %eax diff --git a/test/CodeGen/X86/byval2.ll b/test/CodeGen/X86/byval2.ll index 71129f5f6c9b..03a9f0fb742a 100644 --- a/test/CodeGen/X86/byval2.ll +++ b/test/CodeGen/X86/byval2.ll @@ -1,5 +1,28 @@ -; RUN: llc < %s -march=x86-64 | grep rep.movsq | count 2 -; RUN: llc < %s -march=x86 | grep rep.movsl | count 2 +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64 +; X64-NOT: movsq +; X64: rep +; X64-NOT: rep +; X64: movsq +; X64-NOT: movsq +; X64: rep +; X64-NOT: rep +; X64: movsq +; X64-NOT: rep +; X64-NOT: movsq + +; Win64 has not supported byval yet. + +; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X32 +; X32-NOT: movsl +; X32: rep +; X32-NOT: rep +; X32: movsl +; X32-NOT: movsl +; X32: rep +; X32-NOT: rep +; X32: movsl +; X32-NOT: rep +; X32-NOT: movsl %struct.s = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, diff --git a/test/CodeGen/X86/byval3.ll b/test/CodeGen/X86/byval3.ll index 504e0bed7916..8d5bb6d972d7 100644 --- a/test/CodeGen/X86/byval3.ll +++ b/test/CodeGen/X86/byval3.ll @@ -1,5 +1,28 @@ -; RUN: llc < %s -march=x86-64 | grep rep.movsq | count 2 -; RUN: llc < %s -march=x86 | grep rep.movsl | count 2 +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64 +; X64-NOT: movsq +; X64: rep +; X64-NOT: rep +; X64: movsq +; X64-NOT: movsq +; X64: rep +; X64-NOT: rep +; X64: movsq +; X64-NOT: rep +; X64-NOT: movsq + +; Win64 has not supported byval yet. + +; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X32 +; X32-NOT: movsl +; X32: rep +; X32-NOT: rep +; X32: movsl +; X32-NOT: movsl +; X32: rep +; X32-NOT: rep +; X32: movsl +; X32-NOT: rep +; X32-NOT: movsl %struct.s = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, diff --git a/test/CodeGen/X86/byval4.ll b/test/CodeGen/X86/byval4.ll index 4db9d650b439..ae1a79a1e103 100644 --- a/test/CodeGen/X86/byval4.ll +++ b/test/CodeGen/X86/byval4.ll @@ -1,5 +1,28 @@ -; RUN: llc < %s -march=x86-64 | grep rep.movsq | count 2 -; RUN: llc < %s -march=x86 | grep rep.movsl | count 2 +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64 +; X64-NOT: movsq +; X64: rep +; X64-NOT: rep +; X64: movsq +; X64-NOT: movsq +; X64: rep +; X64-NOT: rep +; X64: movsq +; X64-NOT: rep +; X64-NOT: movsq + +; Win64 has not supported byval yet. + +; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X32 +; X32-NOT: movsl +; X32: rep +; X32-NOT: rep +; X32: movsl +; X32-NOT: movsl +; X32: rep +; X32-NOT: rep +; X32: movsl +; X32-NOT: rep +; X32-NOT: movsl %struct.s = type { i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, diff --git a/test/CodeGen/X86/byval5.ll b/test/CodeGen/X86/byval5.ll index 69c115b97326..a376709d7346 100644 --- a/test/CodeGen/X86/byval5.ll +++ b/test/CodeGen/X86/byval5.ll @@ -1,5 +1,28 @@ -; RUN: llc < %s -march=x86-64 | grep rep.movsq | count 2 -; RUN: llc < %s -march=x86 | grep rep.movsl | count 2 +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64 +; X64-NOT: movsq +; X64: rep +; X64-NOT: rep +; X64: movsq +; X64-NOT: movsq +; X64: rep +; X64-NOT: rep +; X64: movsq +; X64-NOT: rep +; X64-NOT: movsq + +; Win64 has not supported byval yet. + +; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X32 +; X32-NOT: movsl +; X32: rep +; X32-NOT: rep +; X32: movsl +; X32-NOT: movsl +; X32: rep +; X32-NOT: rep +; X32: movsl +; X32-NOT: rep +; X32-NOT: movsl %struct.s = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, diff --git a/test/CodeGen/X86/call-push.ll b/test/CodeGen/X86/call-push.ll index 02cbccc1a492..8cca10c83073 100644 --- a/test/CodeGen/X86/call-push.ll +++ b/test/CodeGen/X86/call-push.ll @@ -27,3 +27,19 @@ UnifiedReturnBlock: ; preds = %entry } declare i32 @f(%struct.decode_t*) + + +; There should be no store for the undef operand. + +; CHECK: _test2: +; CHECK-NOT: 8(%esp) +; CHECK: 4(%esp) +; CHECK-NOT: 8(%esp) +; CHECK: calll +declare i32 @foo(i32, i32, i32) + +define void @test2() nounwind { +entry: + %call = call i32 @foo(i32 8, i32 6, i32 undef) + ret void +} diff --git a/test/CodeGen/X86/coalesce-esp.ll b/test/CodeGen/X86/coalesce-esp.ll index e0f2796f9dce..a5848763c98d 100644 --- a/test/CodeGen/X86/coalesce-esp.ll +++ b/test/CodeGen/X86/coalesce-esp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | grep {movl %esp, %ecx} +; RUN: llc < %s | grep {movl %esp, %ebp} ; PR4572 ; Don't coalesce with %esp if it would end up putting %esp in diff --git a/test/CodeGen/X86/coalescer-commute2.ll b/test/CodeGen/X86/coalescer-commute2.ll index 5d10bbad09ef..730692093de0 100644 --- a/test/CodeGen/X86/coalescer-commute2.ll +++ b/test/CodeGen/X86/coalescer-commute2.ll @@ -1,5 +1,10 @@ -; RUN: llc < %s -march=x86-64 | grep paddw | count 2 -; RUN: llc < %s -march=x86-64 | not grep mov +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; CHECK-NOT: mov +; CHECK: paddw +; CHECK-NOT: mov +; CHECK: paddw +; CHECK-NOT: paddw +; CHECK-NOT: mov ; The 2-addr pass should ensure that identical code is produced for these functions ; no extra copy should be generated. diff --git a/test/CodeGen/X86/coalescer-cross.ll b/test/CodeGen/X86/coalescer-cross.ll index 7d6f399930fd..976db6479e09 100644 --- a/test/CodeGen/X86/coalescer-cross.ll +++ b/test/CodeGen/X86/coalescer-cross.ll @@ -1,6 +1,10 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin10 | not grep movaps +; RUN: llc < %s -mtriple=i386-apple-darwin10 | FileCheck %s +; RUN: llc < %s -mtriple=i386-apple-darwin10 -regalloc=basic | FileCheck %s ; rdar://6509240 +; CHECK: os_clock +; CHECK-NOT: movaps + type { %struct.TValue } ; type %0 type { %struct.L_Umaxalign, i32, %struct.Node* } ; type %1 %struct.CallInfo = type { %struct.TValue*, %struct.TValue*, %struct.TValue*, i32*, i32, i32 } diff --git a/test/CodeGen/X86/commute-two-addr.ll b/test/CodeGen/X86/commute-two-addr.ll index 89b436e75c9e..ef44a3d119b8 100644 --- a/test/CodeGen/X86/commute-two-addr.ll +++ b/test/CodeGen/X86/commute-two-addr.ll @@ -38,11 +38,10 @@ define i32 @t2(i32 %X, i32 %Y) nounwind { define %0 @t3(i32 %lb, i8 zeroext %has_lb, i8 zeroext %lb_inclusive, i32 %ub, i8 zeroext %has_ub, i8 zeroext %ub_inclusive) nounwind { entry: ; DARWIN: t3: +; DARWIN: shll $16 ; DARWIN: shlq $32, %rcx ; DARWIN-NOT: leaq ; DARWIN: orq %rcx, %rax -; DARWIN-NOT: mov -; DARWIN: shll $16 %tmp21 = zext i32 %lb to i64 %tmp23 = zext i32 %ub to i64 %tmp24 = shl i64 %tmp23, 32 diff --git a/test/CodeGen/X86/constant-pool-remat-0.ll b/test/CodeGen/X86/constant-pool-remat-0.ll index 2a44463e5d32..4be14d2128ef 100644 --- a/test/CodeGen/X86/constant-pool-remat-0.ll +++ b/test/CodeGen/X86/constant-pool-remat-0.ll @@ -1,7 +1,16 @@ -; RUN: llc < %s -march=x86-64 | grep LCPI | count 3 -; RUN: llc < %s -march=x86-64 -o /dev/null -stats -info-output-file - | grep asm-printer | grep 6 -; RUN: llc < %s -march=x86 -mattr=+sse2 | grep LCPI | count 3 -; RUN: llc < %s -march=x86 -mattr=+sse2 -o /dev/null -stats -info-output-file - | grep asm-printer | grep 12 +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux -regalloc=greedy | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s +; CHECK: LCPI +; CHECK: LCPI +; CHECK: LCPI +; CHECK-NOT: LCPI + +; RUN: llc < %s -mtriple=x86_64-linux -o /dev/null -stats -info-output-file - | FileCheck %s -check-prefix=X64stat +; X64stat: 6 asm-printer + +; RUN: llc < %s -march=x86 -mattr=+sse2 -o /dev/null -stats -info-output-file - | FileCheck %s -check-prefix=X32stat +; X32stat: 12 asm-printer declare float @qux(float %y) diff --git a/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll b/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll index 17cb2b305721..b82348b32e43 100644 --- a/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll +++ b/test/CodeGen/X86/convert-2-addr-3-addr-inc64.ll @@ -1,6 +1,10 @@ -; RUN: llc < %s -march=x86-64 -o %t -stats -info-output-file - | \ -; RUN: grep {asm-printer} | grep {Number of machine instrs printed} | grep 9 -; RUN: grep {leal 1(\%rsi),} %t +; RUN: llc < %s -mtriple=x86_64-linux -o /dev/null -stats |& FileCheck %s -check-prefix=STATS +; RUN: llc < %s -mtriple=x86_64-win32 -o /dev/null -stats |& FileCheck %s -check-prefix=STATS +; STATS: 9 asm-printer + +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s +; CHECK: leal 1({{%rsi|%rdx}}), define fastcc zeroext i8 @fullGtU(i32 %i1, i32 %i2, i8* %ptr) nounwind optsize { entry: diff --git a/test/CodeGen/X86/crash.ll b/test/CodeGen/X86/crash.ll index 2d8e63e31342..7c4e64cdf6f2 100644 --- a/test/CodeGen/X86/crash.ll +++ b/test/CodeGen/X86/crash.ll @@ -189,7 +189,7 @@ for.inc44: ; preds = %for.body } ; PR9028 -define void @f(i64 %A) nounwind { +define void @func_60(i64 %A) nounwind { entry: %0 = zext i64 %A to i160 %1 = shl i160 %0, 64 @@ -199,3 +199,19 @@ entry: store i576 %4, i576* undef, align 8 ret void } + +; <rdar://problem/9187792> +define fastcc void @func_61() nounwind sspreq { +entry: + %t1 = tail call i64 @llvm.objectsize.i64(i8* undef, i1 false) + %t2 = icmp eq i64 %t1, -1 + br i1 %t2, label %bb2, label %bb1 + +bb1: + ret void + +bb2: + ret void +} + +declare i64 @llvm.objectsize.i64(i8*, i1) nounwind readnone diff --git a/test/CodeGen/X86/dbg-declare-arg.ll b/test/CodeGen/X86/dbg-declare-arg.ll new file mode 100644 index 000000000000..367c1ef36c60 --- /dev/null +++ b/test/CodeGen/X86/dbg-declare-arg.ll @@ -0,0 +1,123 @@ +; RUN: llc -O0 -fast-isel=false < %s | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-macosx10.6.7" +;Radar 9321650 + +;CHECK: ##DEBUG_VALUE: my_a + +%class.A = type { i32, i32, i32, i32 } + +define void @_Z3fooi(%class.A* sret %agg.result, i32 %i) ssp { +entry: + %i.addr = alloca i32, align 4 + %j = alloca i32, align 4 + %nrvo = alloca i1 + %cleanup.dest.slot = alloca i32 + store i32 %i, i32* %i.addr, align 4 + call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !26), !dbg !27 + call void @llvm.dbg.declare(metadata !{i32* %j}, metadata !28), !dbg !30 + store i32 0, i32* %j, align 4, !dbg !31 + %tmp = load i32* %i.addr, align 4, !dbg !32 + %cmp = icmp eq i32 %tmp, 42, !dbg !32 + br i1 %cmp, label %if.then, label %if.end, !dbg !32 + +if.then: ; preds = %entry + %tmp1 = load i32* %i.addr, align 4, !dbg !33 + %add = add nsw i32 %tmp1, 1, !dbg !33 + store i32 %add, i32* %j, align 4, !dbg !33 + br label %if.end, !dbg !35 + +if.end: ; preds = %if.then, %entry + store i1 false, i1* %nrvo, !dbg !36 + call void @llvm.dbg.declare(metadata !{%class.A* %agg.result}, metadata !37), !dbg !39 + %tmp2 = load i32* %j, align 4, !dbg !40 + %x = getelementptr inbounds %class.A* %agg.result, i32 0, i32 0, !dbg !40 + store i32 %tmp2, i32* %x, align 4, !dbg !40 + store i1 true, i1* %nrvo, !dbg !41 + store i32 1, i32* %cleanup.dest.slot + %nrvo.val = load i1* %nrvo, !dbg !42 + br i1 %nrvo.val, label %nrvo.skipdtor, label %nrvo.unused, !dbg !42 + +nrvo.unused: ; preds = %if.end + call void @_ZN1AD1Ev(%class.A* %agg.result), !dbg !42 + br label %nrvo.skipdtor, !dbg !42 + +nrvo.skipdtor: ; preds = %nrvo.unused, %if.end + ret void, !dbg !42 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +define linkonce_odr void @_ZN1AD1Ev(%class.A* %this) unnamed_addr ssp align 2 { +entry: + %this.addr = alloca %class.A*, align 8 + store %class.A* %this, %class.A** %this.addr, align 8 + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !43), !dbg !44 + %this1 = load %class.A** %this.addr + call void @_ZN1AD2Ev(%class.A* %this1) + ret void, !dbg !45 +} + +define linkonce_odr void @_ZN1AD2Ev(%class.A* %this) unnamed_addr nounwind ssp align 2 { +entry: + %this.addr = alloca %class.A*, align 8 + store %class.A* %this, %class.A** %this.addr, align 8 + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !46), !dbg !47 + %this1 = load %class.A** %this.addr + %x = getelementptr inbounds %class.A* %this1, i32 0, i32 0, !dbg !48 + store i32 1, i32* %x, align 4, !dbg !48 + ret void, !dbg !48 +} + +!llvm.dbg.sp = !{!0, !10, !14, !19, !22, !25} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"~A", metadata !"~A", metadata !"", metadata !3, i32 2, metadata !11, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589826, metadata !2, metadata !"A", metadata !3, i32 2, i64 128, i64 32, i32 0, i32 0, null, metadata !4, i32 0, null, null} ; [ DW_TAG_class_type ] +!2 = metadata !{i32 589841, i32 0, i32 4, metadata !"a.cc", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 130127)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589865, metadata !"a.cc", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!4 = metadata !{metadata !5, metadata !7, metadata !8, metadata !9, metadata !0, metadata !10, metadata !14} +!5 = metadata !{i32 589837, metadata !3, metadata !"x", metadata !3, i32 2, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] +!6 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 589837, metadata !3, metadata !"y", metadata !3, i32 2, i64 32, i64 32, i64 32, i32 0, metadata !6} ; [ DW_TAG_member ] +!8 = metadata !{i32 589837, metadata !3, metadata !"z", metadata !3, i32 2, i64 32, i64 32, i64 64, i32 0, metadata !6} ; [ DW_TAG_member ] +!9 = metadata !{i32 589837, metadata !3, metadata !"o", metadata !3, i32 2, i64 32, i64 32, i64 96, i32 0, metadata !6} ; [ DW_TAG_member ] +!10 = metadata !{i32 589870, i32 0, metadata !1, metadata !"A", metadata !"A", metadata !"", metadata !3, i32 2, metadata !11, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 589845, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{null, metadata !13} +!13 = metadata !{i32 589839, metadata !2, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !1} ; [ DW_TAG_pointer_type ] +!14 = metadata !{i32 589870, i32 0, metadata !1, metadata !"A", metadata !"A", metadata !"", metadata !3, i32 2, metadata !15, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null} ; [ DW_TAG_subprogram ] +!15 = metadata !{i32 589845, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !16, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!16 = metadata !{null, metadata !13, metadata !17} +!17 = metadata !{i32 589840, metadata !2, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !18} ; [ DW_TAG_reference_type ] +!18 = metadata !{i32 589862, metadata !2, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !1} ; [ DW_TAG_const_type ] +!19 = metadata !{i32 589870, i32 0, metadata !3, metadata !"foo", metadata !"foo", metadata !"_Z3fooi", metadata !3, i32 4, metadata !20, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*, i32)* @_Z3fooi, null, null} ; [ DW_TAG_subprogram ] +!20 = metadata !{i32 589845, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !21, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!21 = metadata !{metadata !1} +!22 = metadata !{i32 589870, i32 0, metadata !3, metadata !"~A", metadata !"~A", metadata !"_ZN1AD1Ev", metadata !3, i32 2, metadata !23, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*)* @_ZN1AD1Ev, null, null} ; [ DW_TAG_subprogram ] +!23 = metadata !{i32 589845, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !24, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!24 = metadata !{null} +!25 = metadata !{i32 589870, i32 0, metadata !3, metadata !"~A", metadata !"~A", metadata !"_ZN1AD2Ev", metadata !3, i32 2, metadata !23, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*)* @_ZN1AD2Ev, null, null} ; [ DW_TAG_subprogram ] +!26 = metadata !{i32 590081, metadata !19, metadata !"i", metadata !3, i32 16777220, metadata !6, i32 0} ; [ DW_TAG_arg_variable ] +!27 = metadata !{i32 4, i32 11, metadata !19, null} +!28 = metadata !{i32 590080, metadata !29, metadata !"j", metadata !3, i32 5, metadata !6, i32 0} ; [ DW_TAG_auto_variable ] +!29 = metadata !{i32 589835, metadata !19, i32 4, i32 14, metadata !3, i32 0} ; [ DW_TAG_lexical_block ] +!30 = metadata !{i32 5, i32 7, metadata !29, null} +!31 = metadata !{i32 5, i32 12, metadata !29, null} +!32 = metadata !{i32 6, i32 3, metadata !29, null} +!33 = metadata !{i32 7, i32 5, metadata !34, null} +!34 = metadata !{i32 589835, metadata !29, i32 6, i32 16, metadata !3, i32 1} ; [ DW_TAG_lexical_block ] +!35 = metadata !{i32 8, i32 3, metadata !34, null} +!36 = metadata !{i32 9, i32 9, metadata !29, null} +!37 = metadata !{i32 590080, metadata !29, metadata !"my_a", metadata !3, i32 9, metadata !38, i32 0} ; [ DW_TAG_auto_variable ] +!38 = metadata !{i32 589840, metadata !2, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !1} ; [ DW_TAG_reference_type ] +!39 = metadata !{i32 9, i32 5, metadata !29, null} +!40 = metadata !{i32 10, i32 3, metadata !29, null} +!41 = metadata !{i32 11, i32 3, metadata !29, null} +!42 = metadata !{i32 12, i32 1, metadata !29, null} +!43 = metadata !{i32 590081, metadata !22, metadata !"this", metadata !3, i32 16777218, metadata !13, i32 64} ; [ DW_TAG_arg_variable ] +!44 = metadata !{i32 2, i32 47, metadata !22, null} +!45 = metadata !{i32 2, i32 61, metadata !22, null} +!46 = metadata !{i32 590081, metadata !25, metadata !"this", metadata !3, i32 16777218, metadata !13, i32 64} ; [ DW_TAG_arg_variable ] +!47 = metadata !{i32 2, i32 47, metadata !25, null} +!48 = metadata !{i32 2, i32 54, metadata !49, null} +!49 = metadata !{i32 589835, metadata !25, i32 2, i32 52, metadata !3, i32 2} ; [ DW_TAG_lexical_block ] diff --git a/test/CodeGen/X86/dbg-file-name.ll b/test/CodeGen/X86/dbg-file-name.ll new file mode 100644 index 000000000000..e7d5f924aa8a --- /dev/null +++ b/test/CodeGen/X86/dbg-file-name.ll @@ -0,0 +1,19 @@ +; RUN: llc -mtriple x86_64-apple-darwin10.0.0 < %s | FileCheck %s + +; Radar 8884898 +; CHECK: file 1 "/Users/manav/one/two/simple.c" + +declare i32 @printf(i8*, ...) nounwind + +define i32 @main() nounwind { + ret i32 0 +} + +!llvm.dbg.sp = !{ !6} + +!1 = metadata !{i32 589865, metadata !"simple.c", metadata !"/Users/manav/one/two", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 1, metadata !"simple.c", metadata !"/Users/manav/one/two", metadata !"LLVM build 00", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!5 = metadata !{i32 589860, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 9, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @main} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, null} ; [ DW_TAG_subroutine_type ] +!8 = metadata !{metadata !5} diff --git a/test/CodeGen/X86/dbg-merge-loc-entry.ll b/test/CodeGen/X86/dbg-merge-loc-entry.ll index 83df1478cf18..76b93dd42777 100644 --- a/test/CodeGen/X86/dbg-merge-loc-entry.ll +++ b/test/CodeGen/X86/dbg-merge-loc-entry.ll @@ -1,10 +1,11 @@ ; RUN: llc < %s | FileCheck %s +; RUN: llc < %s -regalloc=basic | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-darwin8" ;CHECK: Ldebug_loc0: ;CHECK-NEXT: .quad Lfunc_begin0 -;CHECK-NEXT: .quad Lfunc_end0 +;CHECK-NEXT: .quad L ;CHECK-NEXT: .short 1 ## Loc expr size ;CHECK-NEXT: .byte 85 ## DW_OP_reg5 ;CHECK-NEXT: .quad 0 diff --git a/test/CodeGen/X86/dbg-value-inlined-parameter.ll b/test/CodeGen/X86/dbg-value-inlined-parameter.ll index 89bbf34a1286..481c4ba4a49a 100644 --- a/test/CodeGen/X86/dbg-value-inlined-parameter.ll +++ b/test/CodeGen/X86/dbg-value-inlined-parameter.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-apple-darwin -regalloc=basic < %s | FileCheck %s ;CHECK: DW_TAG_inlined_subroutine ;CHECK-NEXT: DW_AT_abstract_origin diff --git a/test/CodeGen/X86/dbg-value-location.ll b/test/CodeGen/X86/dbg-value-location.ll index 87d7e910c339..a0e4d16246ff 100644 --- a/test/CodeGen/X86/dbg-value-location.ll +++ b/test/CodeGen/X86/dbg-value-location.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s | FileCheck %s +; RUN: llc < %s -regalloc=basic | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-darwin10.0.0" ;Radar 8950491 diff --git a/test/CodeGen/X86/dbg-value-range.ll b/test/CodeGen/X86/dbg-value-range.ll index 2985224d9dbd..da49f2dee1a7 100644 --- a/test/CodeGen/X86/dbg-value-range.ll +++ b/test/CodeGen/X86/dbg-value-range.ll @@ -1,4 +1,5 @@ -; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-apple-darwin10 < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-apple-darwin10 -regalloc=basic < %s | FileCheck %s %struct.a = type { i32 } @@ -41,15 +42,17 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !18 = metadata !{i32 7, i32 2, metadata !12, null} !19 = metadata !{i32 8, i32 2, metadata !12, null} -; check that variable bar:b value range is appropriately trucated in debug info. Here Ltmp5 is end of -; location range. +; Check that variable bar:b value range is appropriately trucated in debug info. +; The variable is in %rdi which is clobbered by 'movl %ebx, %edi' +; Here Ltmp7 is the end of the location range. -;CHECK:Ltmp6 -;CHECK-NEXT: DEBUG_VALUE: bar:b <- undef +;CHECK: .loc 1 7 2 +;CHECK: movl +;CHECK-NEXT: [[CLOBBER:Ltmp[0-9]*]] ;CHECK:Ldebug_loc0: -;CHECK-NEXT: .quad Ltmp -;CHECK-NEXT: .quad Ltmp6 +;CHECK-NEXT: .quad +;CHECK-NEXT: .quad [[CLOBBER]] ;CHECK-NEXT: .short 1 ;CHECK-NEXT: .byte 85 ;CHECK-NEXT: .quad 0 diff --git a/test/CodeGen/X86/divide-by-constant.ll b/test/CodeGen/X86/divide-by-constant.ll index fe335b9369cb..08e3272a3707 100644 --- a/test/CodeGen/X86/divide-by-constant.ll +++ b/test/CodeGen/X86/divide-by-constant.ll @@ -60,3 +60,14 @@ entry: ; CHECK: shrl $31, %ecx ; CHECK: sarl $18, %eax } + +define i32 @test7(i32 %x) nounwind { + %div = udiv i32 %x, 28 + ret i32 %div +; CHECK: test7: +; CHECK: shrl $2 +; CHECK: movl $613566757 +; CHECK: mull +; CHECK-NOT: shrl +; CHECK: ret +} diff --git a/test/CodeGen/X86/dyn-stackalloc.ll b/test/CodeGen/X86/dyn-stackalloc.ll index e577611ebcf1..7b0fe18f65c1 100644 --- a/test/CodeGen/X86/dyn-stackalloc.ll +++ b/test/CodeGen/X86/dyn-stackalloc.ll @@ -1,6 +1,9 @@ -; RUN: llc < %s -mtriple=i686-linux | not egrep {\\\$4294967289|-7} -; RUN: llc < %s -mtriple=i686-linux | egrep {\\\$4294967280|-16} -; RUN: llc < %s -mtriple=x86_64-linux | grep {\\-16} +; RUN: llc < %s -mtriple=i686-linux | FileCheck %s -check-prefix=X32 +; X32-NOT: {{$429496728|-7}} +; X32: {{$4294967280|-16}} +; X32-NOT: {{$429496728|-7}} +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64 +; X64: -16 define void @t() nounwind { A: diff --git a/test/CodeGen/X86/fast-isel-gep.ll b/test/CodeGen/X86/fast-isel-gep.ll index fbe0243716bd..48abfd0f26e5 100644 --- a/test/CodeGen/X86/fast-isel-gep.ll +++ b/test/CodeGen/X86/fast-isel-gep.ll @@ -87,4 +87,23 @@ define i64 @test5(i8* %A, i32 %I, i64 %B) nounwind { ; X64-NEXT: ret } +; PR9500, rdar://9156159 - Don't do non-local address mode folding, +; because it may require values which wouldn't otherwise be live out +; of their blocks. +define void @test6() { +if.end: ; preds = %if.then, %invoke.cont + %tmp15 = load i64* undef + %dec = add i64 %tmp15, 13 + store i64 %dec, i64* undef + %call17 = invoke i8* @_ZNK18G__FastAllocString4dataEv() + to label %invoke.cont16 unwind label %lpad +invoke.cont16: ; preds = %if.then14 + %arrayidx18 = getelementptr inbounds i8* %call17, i64 %dec + store i8 0, i8* %arrayidx18 + unreachable + +lpad: ; preds = %if.end19, %if.then14, %if.end, %entry + unreachable +} +declare i8* @_ZNK18G__FastAllocString4dataEv() nounwind diff --git a/test/CodeGen/X86/fast-isel-i1.ll b/test/CodeGen/X86/fast-isel-i1.ll index d0665783ce64..5d572c1de500 100644 --- a/test/CodeGen/X86/fast-isel-i1.ll +++ b/test/CodeGen/X86/fast-isel-i1.ll @@ -1,19 +1,40 @@ -; RUN: llc < %s -march=x86 -fast-isel | grep {andb \$1, %} +; RUN: llc < %s -march=x86 -fast-isel | FileCheck %s -declare i64 @bar(i64) +declare i64 @test1a(i64) -define i32 @foo(i64 %x) nounwind { - %y = add i64 %x, -3 ; <i64> [#uses=1] - %t = call i64 @bar(i64 %y) ; <i64> [#uses=1] - %s = mul i64 %t, 77 ; <i64> [#uses=1] - %z = trunc i64 %s to i1 ; <i1> [#uses=1] +define i32 @test1(i64 %x) nounwind { +; CHECK: test1: +; CHECK: andb $1, % + %y = add i64 %x, -3 + %t = call i64 @test1a(i64 %y) + %s = mul i64 %t, 77 + %z = trunc i64 %s to i1 br label %next next: ; preds = %0 - %u = zext i1 %z to i32 ; <i32> [#uses=1] - %v = add i32 %u, 1999 ; <i32> [#uses=1] + %u = zext i1 %z to i32 + %v = add i32 %u, 1999 br label %exit exit: ; preds = %next ret i32 %v } + +define void @test2(i8* %a) nounwind { +entry: +; CHECK: test2: +; CHECK: movb {{.*}} %al +; CHECK-NEXT: xorb $1, %al +; CHECK-NEXT: testb $1 + %tmp = load i8* %a, align 1 + %tobool = trunc i8 %tmp to i1 + %tobool2 = xor i1 %tobool, true + br i1 %tobool2, label %if.then, label %if.end + +if.then: + call void @test2(i8* null) + br label %if.end + +if.end: + ret void +} diff --git a/test/CodeGen/X86/fast-isel-shift-imm.ll b/test/CodeGen/X86/fast-isel-shift-imm.ll deleted file mode 100644 index 5c62c1880516..000000000000 --- a/test/CodeGen/X86/fast-isel-shift-imm.ll +++ /dev/null @@ -1,8 +0,0 @@ -; RUN: llc < %s -march=x86 -O0 | grep {sarl \$80, %e} -; PR3242 - -define void @foo(i32 %x, i32* %p) nounwind { - %y = ashr i32 %x, 50000 - store i32 %y, i32* %p - ret void -} diff --git a/test/CodeGen/X86/fast-isel-x86-64.ll b/test/CodeGen/X86/fast-isel-x86-64.ll new file mode 100644 index 000000000000..c4afc10ffab8 --- /dev/null +++ b/test/CodeGen/X86/fast-isel-x86-64.ll @@ -0,0 +1,262 @@ +; RUN: llc < %s -fast-isel -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +; Make sure that fast-isel folds the immediate into the binop even though it +; is non-canonical. +define i32 @test1(i32 %i) nounwind ssp { + %and = and i32 8, %i + ret i32 %and +} + +; CHECK: test1: +; CHECK: andl $8, + + +; rdar://9289512 - The load should fold into the compare. +define void @test2(i64 %x) nounwind ssp { +entry: + %x.addr = alloca i64, align 8 + store i64 %x, i64* %x.addr, align 8 + %tmp = load i64* %x.addr, align 8 + %cmp = icmp sgt i64 %tmp, 42 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +; CHECK: test2: +; CHECK: movq %rdi, -8(%rsp) +; CHECK: cmpq $42, -8(%rsp) +} + + + + +@G = external global i32 +define i64 @test3() nounwind { + %A = ptrtoint i32* @G to i64 + ret i64 %A +; CHECK: test3: +; CHECK: movq _G@GOTPCREL(%rip), %rax +; CHECK-NEXT: ret +} + + + +; rdar://9289558 +@rtx_length = external global [153 x i8] + +define i32 @test4(i64 %idxprom9) nounwind { + %arrayidx10 = getelementptr inbounds [153 x i8]* @rtx_length, i32 0, i64 %idxprom9 + %tmp11 = load i8* %arrayidx10, align 1 + %conv = zext i8 %tmp11 to i32 + ret i32 %conv + +; CHECK: test4: +; CHECK: movq _rtx_length@GOTPCREL(%rip), %rax +; CHECK-NEXT: movzbl (%rax,%rdi), %eax +; CHECK-NEXT: ret +} + + +; PR3242 - Out of range shifts should not be folded by fastisel. +define void @test5(i32 %x, i32* %p) nounwind { + %y = ashr i32 %x, 50000 + store i32 %y, i32* %p + ret void + +; CHECK: test5: +; CHECK: movl $50000, %ecx +; CHECK: sarl %cl, %edi +; CHECK: ret +} + +; rdar://9289501 - fast isel should fold trivial multiplies to shifts. +define i64 @test6(i64 %x) nounwind ssp { +entry: + %mul = mul nsw i64 %x, 8 + ret i64 %mul + +; CHECK: test6: +; CHECK: leaq (,%rdi,8), %rax +} + +define i32 @test7(i32 %x) nounwind ssp { +entry: + %mul = mul nsw i32 %x, 8 + ret i32 %mul +; CHECK: test7: +; CHECK: leal (,%rdi,8), %eax +} + + +; rdar://9289507 - folding of immediates into 64-bit operations. +define i64 @test8(i64 %x) nounwind ssp { +entry: + %add = add nsw i64 %x, 7 + ret i64 %add + +; CHECK: test8: +; CHECK: addq $7, %rdi +} + +define i64 @test9(i64 %x) nounwind ssp { +entry: + %add = mul nsw i64 %x, 7 + ret i64 %add +; CHECK: test9: +; CHECK: imulq $7, %rdi, %rax +} + +; rdar://9297011 - Don't reject udiv by a power of 2. +define i32 @test10(i32 %X) nounwind { + %Y = udiv i32 %X, 8 + ret i32 %Y +; CHECK: test10: +; CHECK: shrl $3, +} + +define i32 @test11(i32 %X) nounwind { + %Y = sdiv exact i32 %X, 8 + ret i32 %Y +; CHECK: test11: +; CHECK: sarl $3, +} + + +; rdar://9297006 - Trunc to bool. +define void @test12(i8 %tmp) nounwind ssp noredzone { +entry: + %tobool = trunc i8 %tmp to i1 + br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @test12(i8 0) noredzone + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +; CHECK: test12: +; CHECK: testb $1, +; CHECK-NEXT: je L +; CHECK-NEXT: movl $0, %edi +; CHECK-NEXT: callq +} + +declare void @test13f(i1 %X) + +define void @test13() nounwind { + call void @test13f(i1 0) + ret void +; CHECK: test13: +; CHECK: movl $0, %edi +; CHECK-NEXT: callq +} + + + +; rdar://9297003 - fast isel bails out on all functions taking bools +define void @test14(i8 %tmp) nounwind ssp noredzone { +entry: + %tobool = trunc i8 %tmp to i1 + call void @test13f(i1 zeroext %tobool) noredzone + ret void +; CHECK: test14: +; CHECK: andb $1, +; CHECK: callq +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32, i1) + +; rdar://9289488 - fast-isel shouldn't bail out on llvm.memcpy +define void @test15(i8* %a, i8* %b) nounwind { + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %b, i64 4, i32 4, i1 false) + ret void +; CHECK: test15: +; CHECK-NEXT: movl (%rsi), %eax +; CHECK-NEXT: movl %eax, (%rdi) +; CHECK-NEXT: ret +} + +; Handling for varargs calls +declare void @test16callee(...) nounwind +define void @test16() nounwind { +; CHECK: test16: +; CHECK: movl $1, %edi +; CHECK: movb $0, %al +; CHECK: callq _test16callee + call void (...)* @test16callee(i32 1) + br label %block2 + +block2: +; CHECK: movabsq $1 +; CHECK: cvtsi2sdq {{.*}} %xmm0 +; CHECK: movb $1, %al +; CHECK: callq _test16callee + call void (...)* @test16callee(double 1.000000e+00) + ret void +} + + +declare void @foo() unnamed_addr ssp align 2 + +; Verify that we don't fold the load into the compare here. That would move it +; w.r.t. the call. +define i32 @test17(i32 *%P) ssp nounwind { +entry: + %tmp = load i32* %P + %cmp = icmp ne i32 %tmp, 5 + call void @foo() + br i1 %cmp, label %if.then, label %if.else + +if.then: ; preds = %entry + ret i32 1 + +if.else: ; preds = %entry + ret i32 2 +; CHECK: test17: +; CHECK: movl (%rdi), %eax +; CHECK: callq _foo +; CHECK: cmpl $5, %eax +; CHECK-NEXT: je +} + +; Check that 0.0 is materialized using pxor +define void @test18(float* %p1) { + store float 0.0, float* %p1 + ret void +; CHECK: test18: +; CHECK: pxor +} +define void @test19(double* %p1) { + store double 0.0, double* %p1 + ret void +; CHECK: test19: +; CHECK: pxor +} + +; Check that we fast-isel sret +%struct.a = type { i64, i64, i64 } +define void @test20() nounwind ssp { +entry: + %tmp = alloca %struct.a, align 8 + call void @test20sret(%struct.a* sret %tmp) + ret void +; CHECK: test20: +; CHECK: leaq (%rsp), %rdi +; CHECK: callq _test20sret +} +declare void @test20sret(%struct.a* sret) + +; Check that -0.0 is not materialized using pxor +define void @test21(double* %p1) { + store double -0.0, double* %p1 + ret void +; CHECK: test21: +; CHECK-NOT: pxor +; CHECK: movsd LCPI +}
\ No newline at end of file diff --git a/test/CodeGen/X86/fast-isel-x86.ll b/test/CodeGen/X86/fast-isel-x86.ll index 56aeb3a34364..19972f74b2ba 100644 --- a/test/CodeGen/X86/fast-isel-x86.ll +++ b/test/CodeGen/X86/fast-isel-x86.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=x86 -relocation-model=pic < %s +; RUN: llc -fast-isel -O0 -mtriple=i386-apple-darwin10 -relocation-model=pic < %s | FileCheck %s ; This should use flds to set the return value. ; CHECK: test0: @@ -31,3 +31,18 @@ define i32 @test2() nounwind { %t = load i32* @HHH ret i32 %t } + +; Check that we fast-isel sret, and handle the callee-pops behavior correctly. +%struct.a = type { i64, i64, i64 } +define void @test3() nounwind ssp { +entry: + %tmp = alloca %struct.a, align 8 + call void @test3sret(%struct.a* sret %tmp) + ret void +; CHECK: test3: +; CHECK: subl $44 +; CHECK: leal 16(%esp) +; CHECK: calll _test3sret +; CHECK: addl $40 +} +declare void @test3sret(%struct.a* sret) diff --git a/test/CodeGen/X86/fast-isel.ll b/test/CodeGen/X86/fast-isel.ll index 177c06b45dcd..5a1d2136ce4a 100644 --- a/test/CodeGen/X86/fast-isel.ll +++ b/test/CodeGen/X86/fast-isel.ll @@ -20,6 +20,7 @@ fast: %t6 = add i32 %t5, 2 %t7 = getelementptr i32* %y, i32 1 %t8 = getelementptr i32* %t7, i32 %t6 + call void asm sideeffect "hello world", ""() br label %exit exit: @@ -92,3 +93,13 @@ define void @load_store_i1(i1* %p, i1* %q) nounwind { store i1 %t, i1* %q ret void } + + +@crash_test1x = external global <2 x i32>, align 8 + +define void @crash_test1() nounwind ssp { + %tmp = load <2 x i32>* @crash_test1x, align 8 + %neg = xor <2 x i32> %tmp, <i32 -1, i32 -1> + ret void +} + diff --git a/test/CodeGen/X86/fold-mul-lohi.ll b/test/CodeGen/X86/fold-mul-lohi.ll index 0351ecab117b..5614c808d0e6 100644 --- a/test/CodeGen/X86/fold-mul-lohi.ll +++ b/test/CodeGen/X86/fold-mul-lohi.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -march=x86 | not grep lea -; RUN: llc < %s -march=x86-64 | not grep lea +; RUN: llc < %s -march=x86 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; CHECK-NOT: lea @B = external global [1000 x i8], align 32 @A = external global [1000 x i8], align 32 diff --git a/test/CodeGen/X86/fold-pcmpeqd-0.ll b/test/CodeGen/X86/fold-pcmpeqd-0.ll index e5be58e1aaa3..647bbdb7f0fd 100644 --- a/test/CodeGen/X86/fold-pcmpeqd-0.ll +++ b/test/CodeGen/X86/fold-pcmpeqd-0.ll @@ -1,11 +1,21 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | not grep pcmpeqd -; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | grep orps | grep CPI0_2 | count 2 -; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep pcmpeqd | count 1 +; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah -regalloc=linearscan | FileCheck --check-prefix=I386 %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck --check-prefix=X86-64 %s ; This testcase shouldn't need to spill the -1 value, ; so it should just use pcmpeqd to materialize an all-ones vector. ; For i386, cp load of -1 are folded. +; With -regalloc=greedy, the live range is split before spilling, so the first +; pcmpeq doesn't get folded as a constant pool load. + +; I386-NOT: pcmpeqd +; I386: orps LCPI0_2, %xmm +; I386-NOT: pcmpeqd +; I386: orps LCPI0_2, %xmm + +; X86-64: pcmpeqd +; X86-64-NOT: pcmpeqd + %struct.__ImageExecInfo = type <{ <4 x i32>, <4 x float>, <2 x i64>, i8*, i8*, i8*, i32, i32, i32, i32, i32 }> %struct._cl_image_format_t = type <{ i32, i32, i32 }> %struct._image2d_t = type <{ i8*, %struct._cl_image_format_t, i32, i32, i32, i32, i32, i32 }> diff --git a/test/CodeGen/X86/fold-pcmpeqd-2.ll b/test/CodeGen/X86/fold-pcmpeqd-2.ll index 49f879504e06..9f8d9903810d 100644 --- a/test/CodeGen/X86/fold-pcmpeqd-2.ll +++ b/test/CodeGen/X86/fold-pcmpeqd-2.ll @@ -1,10 +1,20 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | not grep pcmpeqd -; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep pcmpeqd | count 1 +; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah -regalloc=linearscan | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -regalloc=linearscan | FileCheck %s -; This testcase should need to spill the -1 value on x86-32, +; This testcase should need to spill the -1 value on both x86-32 and x86-64, ; so it shouldn't use pcmpeqd to materialize an all-ones vector; it ; should use a constant-pool load instead. +; Constant pool all-ones vector: +; CHECK: .long 4294967295 +; CHECK-NEXT: .long 4294967295 +; CHECK-NEXT: .long 4294967295 +; CHECK-NEXT: .long 4294967295 + +; No pcmpeqd instructions, everybody uses the constant pool. +; CHECK: program_1: +; CHECK-NOT: pcmpeqd + %struct.__ImageExecInfo = type <{ <4 x i32>, <4 x float>, <2 x i64>, i8*, i8*, i8*, i32, i32, i32, i32, i32 }> %struct._cl_image_format_t = type <{ i32, i32, i32 }> %struct._image2d_t = type <{ i8*, %struct._cl_image_format_t, i32, i32, i32, i32, i32, i32 }> @@ -57,6 +67,7 @@ forbody: ; preds = %forcond %bitcast11.i6 = bitcast <4 x float> %tmp83 to <4 x i32> ; <<4 x i32>> [#uses=1] %not.i7 = xor <4 x i32> zeroinitializer, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1] %andnps.i8 = and <4 x i32> %bitcast11.i6, %not.i7 ; <<4 x i32>> [#uses=1] + call void null(<4 x float> %mul313, <4 x float> %cmpunord.i11, <4 x float> %tmp83, <4 x float> zeroinitializer, %struct.__ImageExecInfo* null, <4 x i32> zeroinitializer) nounwind %orps.i9 = or <4 x i32> %andnps.i8, %andps.i5 ; <<4 x i32>> [#uses=1] %bitcast17.i10 = bitcast <4 x i32> %orps.i9 to <4 x float> ; <<4 x float>> [#uses=1] %tmp84 = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %mul313, <4 x float> zeroinitializer) nounwind ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/X86/fold-zext-trunc.ll b/test/CodeGen/X86/fold-zext-trunc.ll new file mode 100644 index 000000000000..f901ad280b50 --- /dev/null +++ b/test/CodeGen/X86/fold-zext-trunc.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s | FileCheck %s +; PR9055 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" +target triple = "i686-pc-linux-gnu" + +%struct.S0 = type { i32, [2 x i8], [2 x i8], [4 x i8] } + +@g_98 = common global %struct.S0 zeroinitializer, align 4 + +define void @foo() nounwind { +; CHECK: movzbl +; CHECK-NOT: movzbl +; CHECK: calll +entry: + %tmp17 = load i8* getelementptr inbounds (%struct.S0* @g_98, i32 0, i32 1, i32 0), align 4 + %tmp54 = zext i8 %tmp17 to i32 + %foo = load i32* bitcast (i8* getelementptr inbounds (%struct.S0* @g_98, i32 0, i32 1, i32 0) to i32*), align 4 + %conv.i = trunc i32 %foo to i8 + tail call void @func_12(i32 %tmp54, i8 zeroext %conv.i) nounwind + ret void +} + +declare void @func_12(i32, i8 zeroext) diff --git a/test/CodeGen/X86/fp-stack-compare.ll b/test/CodeGen/X86/fp-stack-compare.ll index b216914d2391..f3998b67f672 100644 --- a/test/CodeGen/X86/fp-stack-compare.ll +++ b/test/CodeGen/X86/fp-stack-compare.ll @@ -1,11 +1,11 @@ -; RUN: llc < %s -march=x86 -mcpu=i386 | grep {fucompi.*st.\[12\]} +; RUN: llc < %s -march=x86 -mcpu=i386 | FileCheck %s ; PR1012 define float @foo(float* %col.2.0) { - %tmp = load float* %col.2.0 ; <float> [#uses=3] - %tmp16 = fcmp olt float %tmp, 0.000000e+00 ; <i1> [#uses=1] - %tmp20 = fsub float -0.000000e+00, %tmp ; <float> [#uses=1] - %iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp ; <float> [#uses=1] - ret float %iftmp.2.0 +; CHECK: fucompi + %tmp = load float* %col.2.0 + %tmp16 = fcmp olt float %tmp, 0.000000e+00 + %tmp20 = fsub float -0.000000e+00, %tmp + %iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp + ret float %iftmp.2.0 } - diff --git a/test/CodeGen/X86/fp-trunc.ll b/test/CodeGen/X86/fp-trunc.ll new file mode 100644 index 000000000000..170637a40ee2 --- /dev/null +++ b/test/CodeGen/X86/fp-trunc.ll @@ -0,0 +1,35 @@ +; RUN: llc < %s -march=x86 -mattr=+sse2,-avx | FileCheck %s + +define <1 x float> @test1(<1 x double> %x) nounwind { +; CHECK: cvtsd2ss +; CHECK: ret + %y = fptrunc <1 x double> %x to <1 x float> + ret <1 x float> %y +} + + +define <2 x float> @test2(<2 x double> %x) nounwind { +; FIXME: It would be nice if this compiled down to a cvtpd2ps +; CHECK: cvtsd2ss +; CHECK: cvtsd2ss +; CHECK: ret + %y = fptrunc <2 x double> %x to <2 x float> + ret <2 x float> %y +} + +define <8 x float> @test3(<8 x double> %x) nounwind { +; FIXME: It would be nice if this compiled down to a series of cvtpd2ps +; CHECK: cvtsd2ss +; CHECK: cvtsd2ss +; CHECK: cvtsd2ss +; CHECK: cvtsd2ss +; CHECK: cvtsd2ss +; CHECK: cvtsd2ss +; CHECK: cvtsd2ss +; CHECK: cvtsd2ss +; CHECK: ret + %y = fptrunc <8 x double> %x to <8 x float> + ret <8 x float> %y +} + + diff --git a/test/CodeGen/X86/global-sections-tls.ll b/test/CodeGen/X86/global-sections-tls.ll index 2c2303042bc4..d5409a579b2f 100644 --- a/test/CodeGen/X86/global-sections-tls.ll +++ b/test/CodeGen/X86/global-sections-tls.ll @@ -2,7 +2,7 @@ ; PR4639 @G1 = internal thread_local global i32 0 ; <i32*> [#uses=1] -; LINUX: .section .tbss,"awT",@nobits +; LINUX: .section .tbss,"awT",@nobits ; LINUX: G1: diff --git a/test/CodeGen/X86/global-sections.ll b/test/CodeGen/X86/global-sections.ll index 39a69e17a100..d0a1b4d281fe 100644 --- a/test/CodeGen/X86/global-sections.ll +++ b/test/CodeGen/X86/global-sections.ll @@ -99,7 +99,7 @@ ; DARWIN: _G7: ; DARWIN: .asciz "abcdefghi" -; LINUX: .section .rodata.str1.1,"aMS",@progbits,1 +; LINUX: .section .rodata.str1.1,"aMS",@progbits,1 ; LINUX: .globl G7 ; LINUX: G7: ; LINUX: .asciz "abcdefghi" @@ -114,7 +114,7 @@ ; DARWIN: .globl _G8 ; DARWIN: _G8: -; LINUX: .section .rodata.str2.2,"aMS",@progbits,2 +; LINUX: .section .rodata.str2.2,"aMS",@progbits,2 ; LINUX: .globl G8 ; LINUX:G8: @@ -123,7 +123,7 @@ ; DARWIN: .globl _G9 ; DARWIN: _G9: -; LINUX: .section .rodata.str4.4,"aMS",@progbits,4 +; LINUX: .section .rodata.str4.4,"aMS",@progbits,4 ; LINUX: .globl G9 ; LINUX:G9 diff --git a/test/CodeGen/X86/h-register-store.ll b/test/CodeGen/X86/h-register-store.ll index d30e6b334e8b..0adb2b148c39 100644 --- a/test/CodeGen/X86/h-register-store.ll +++ b/test/CodeGen/X86/h-register-store.ll @@ -1,9 +1,29 @@ -; RUN: llc < %s -march=x86-64 > %t -; RUN: grep mov %t | count 6 -; RUN: grep {movb %ah, (%rsi)} %t | count 3 -; RUN: llc < %s -march=x86 > %t -; RUN: grep mov %t | count 3 -; RUN: grep {movb %ah, (%e} %t | count 3 +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64 +; X64: mov +; X64-NEXT: movb %ah, (%rsi) +; X64: mov +; X64-NEXT: movb %ah, (%rsi) +; X64: mov +; X64-NEXT: movb %ah, (%rsi) +; X64-NOT: mov + +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=W64 +; W64-NOT: mov +; W64: movb %ch, (%rdx) +; W64-NOT: mov +; W64: movb %ch, (%rdx) +; W64-NOT: mov +; W64: movb %ch, (%rdx) +; W64-NOT: mov + +; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X32 +; X32-NOT: mov +; X32: movb %ah, (%e +; X32-NOT: mov +; X32: movb %ah, (%e +; X32-NOT: mov +; X32: movb %ah, (%e +; X32-NOT: mov ; Use h-register extract and store. diff --git a/test/CodeGen/X86/h-registers-0.ll b/test/CodeGen/X86/h-registers-0.ll index e84bb9a34a26..cdc75af92e43 100644 --- a/test/CodeGen/X86/h-registers-0.ll +++ b/test/CodeGen/X86/h-registers-0.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=X86-64 +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X86-64 +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=WIN64 ; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X86-32 ; Use h registers. On x86-64, codegen doesn't support general allocation @@ -9,6 +10,12 @@ define void @bar64(i64 inreg %x, i8* inreg %p) nounwind { ; X86-64: shrq $8, %rdi ; X86-64: incb %dil +; See FIXME: on regclass GR8. +; It could be optimally transformed like; incb %ch; movb %ch, (%rdx) +; WIN64: bar64: +; WIN64: shrq $8, %rcx +; WIN64: incb %cl + ; X86-32: bar64: ; X86-32: incb %ah %t0 = lshr i64 %x, 8 @@ -23,6 +30,10 @@ define void @bar32(i32 inreg %x, i8* inreg %p) nounwind { ; X86-64: shrl $8, %edi ; X86-64: incb %dil +; WIN64: bar32: +; WIN64: shrl $8, %ecx +; WIN64: incb %cl + ; X86-32: bar32: ; X86-32: incb %ah %t0 = lshr i32 %x, 8 @@ -37,6 +48,10 @@ define void @bar16(i16 inreg %x, i8* inreg %p) nounwind { ; X86-64: shrl $8, %edi ; X86-64: incb %dil +; WIN64: bar16: +; WIN64: shrl $8, %ecx +; WIN64: incb %cl + ; X86-32: bar16: ; X86-32: incb %ah %t0 = lshr i16 %x, 8 @@ -51,6 +66,9 @@ define i64 @qux64(i64 inreg %x) nounwind { ; X86-64: movq %rdi, %rax ; X86-64: movzbl %ah, %eax +; WIN64: qux64: +; WIN64: movzbl %ch, %eax + ; X86-32: qux64: ; X86-32: movzbl %ah, %eax %t0 = lshr i64 %x, 8 @@ -63,6 +81,9 @@ define i32 @qux32(i32 inreg %x) nounwind { ; X86-64: movl %edi, %eax ; X86-64: movzbl %ah, %eax +; WIN64: qux32: +; WIN64: movzbl %ch, %eax + ; X86-32: qux32: ; X86-32: movzbl %ah, %eax %t0 = lshr i32 %x, 8 @@ -75,6 +96,9 @@ define i16 @qux16(i16 inreg %x) nounwind { ; X86-64: movl %edi, %eax ; X86-64: movzbl %ah, %eax +; WIN64: qux16: +; WIN64: movzbl %ch, %eax + ; X86-32: qux16: ; X86-32: movzbl %ah, %eax %t0 = lshr i16 %x, 8 diff --git a/test/CodeGen/X86/h-registers-1.ll b/test/CodeGen/X86/h-registers-1.ll index e97ebab69712..402cdfe413b5 100644 --- a/test/CodeGen/X86/h-registers-1.ll +++ b/test/CodeGen/X86/h-registers-1.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 > %t +; RUN: llc < %s -mtriple=x86_64-linux > %t ; RUN: grep {movzbl %\[abcd\]h,} %t | count 8 ; RUN: grep {%\[abcd\]h} %t | not grep {%r\[\[:digit:\]\]*d} diff --git a/test/CodeGen/X86/hidden-vis-pic.ll b/test/CodeGen/X86/hidden-vis-pic.ll index ba130a2c1c86..217dba6944b4 100644 --- a/test/CodeGen/X86/hidden-vis-pic.ll +++ b/test/CodeGen/X86/hidden-vis-pic.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin9 -relocation-model=pic -disable-fp-elim -unwind-tables | FileCheck %s +; RUN: llc < %s -disable-cfi -mtriple=i386-apple-darwin9 -relocation-model=pic -disable-fp-elim -unwind-tables | FileCheck %s diff --git a/test/CodeGen/X86/i64-mem-copy.ll b/test/CodeGen/X86/i64-mem-copy.ll index 847e2095f4c5..dce12ae12485 100644 --- a/test/CodeGen/X86/i64-mem-copy.ll +++ b/test/CodeGen/X86/i64-mem-copy.ll @@ -1,5 +1,9 @@ -; RUN: llc < %s -march=x86-64 | grep {movq.*(%rsi), %rax} -; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {movsd.*(%eax),} +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=X64 +; X64: movq ({{%rsi|%rdx}}), %r + +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s -check-prefix=X32 +; X32: movsd (%eax), %xmm ; Uses movsd to load / store i64 values if sse2 is available. diff --git a/test/CodeGen/X86/iabs.ll b/test/CodeGen/X86/iabs.ll index 6a79ee879253..a8ba0155fd10 100644 --- a/test/CodeGen/X86/iabs.ll +++ b/test/CodeGen/X86/iabs.ll @@ -1,12 +1,11 @@ ; RUN: llc < %s -march=x86-64 -stats |& \ -; RUN: grep {6 .*Number of machine instrs printed} +; RUN: grep {5 .*Number of machine instrs printed} ;; Integer absolute value, should produce something at least as good as: -;; movl %edi, %eax -;; sarl $31, %eax -;; addl %eax, %edi -;; xorl %eax, %edi -;; movl %edi, %eax +;; movl %edi, %ecx +;; sarl $31, %ecx +;; leal (%rdi,%rcx), %eax +;; xorl %ecx, %eax ;; ret define i32 @test(i32 %a) nounwind { %tmp1neg = sub i32 0, %a diff --git a/test/CodeGen/X86/isel-sink3.ll b/test/CodeGen/X86/isel-sink3.ll index 8d3d97a930be..7012ccefaadb 100644 --- a/test/CodeGen/X86/isel-sink3.ll +++ b/test/CodeGen/X86/isel-sink3.ll @@ -1,9 +1,11 @@ -; RUN: llc < %s | grep {addl.\$4, %ecx} -; RUN: llc < %s | not grep leal +; RUN: llc < %s | FileCheck %s ; this should not sink %1 into bb1, that would increase reg pressure. ; rdar://6399178 +; CHECK: addl $4, +; CHECK-NOT: leal + target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin7" diff --git a/test/CodeGen/X86/lea-3.ll b/test/CodeGen/X86/lea-3.ll index 44413d60785e..c439ee1d06e3 100644 --- a/test/CodeGen/X86/lea-3.ll +++ b/test/CodeGen/X86/lea-3.ll @@ -1,17 +1,20 @@ -; RUN: llc < %s -march=x86-64 | grep {leal (%rdi,%rdi,2), %eax} -define i32 @test(i32 %a) { - %tmp2 = mul i32 %a, 3 ; <i32> [#uses=1] - ret i32 %tmp2 -} +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -; RUN: llc < %s -march=x86-64 | grep {leaq (,%rdi,4), %rax} +; CHECK: leaq (,[[A0:%rdi|%rcx]],4), %rax define i64 @test2(i64 %a) { %tmp2 = shl i64 %a, 2 %tmp3 = or i64 %tmp2, %a ret i64 %tmp3 } -;; TODO! LEA instead of shift + copy. +; CHECK: leal ([[A0]],[[A0]],2), %eax +define i32 @test(i32 %a) { + %tmp2 = mul i32 %a, 3 ; <i32> [#uses=1] + ret i32 %tmp2 +} + +; CHECK: leaq (,[[A0]],8), %rax define i64 @test3(i64 %a) { %tmp2 = shl i64 %a, 3 ret i64 %tmp2 diff --git a/test/CodeGen/X86/lock-inst-encoding.ll b/test/CodeGen/X86/lock-inst-encoding.ll index 03468e2b3f4f..2d10fbc611d0 100644 --- a/test/CodeGen/X86/lock-inst-encoding.ll +++ b/test/CodeGen/X86/lock-inst-encoding.ll @@ -4,10 +4,9 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 target triple = "x86_64-apple-darwin10.0.0" ; CHECK: f0: -; CHECK: addq %rax, (%rdi) -; CHECK: # encoding: [0xf0,0x48,0x01,0x07] +; CHECK: addq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0, ; CHECK: ret -define void @f0(i64* %a0) { +define void @f0(i64* %a0) nounwind { %t0 = and i64 1, 1 call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) nounwind %1 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %a0, i64 %t0) nounwind diff --git a/test/CodeGen/X86/loop-strength-reduce4.ll b/test/CodeGen/X86/loop-strength-reduce4.ll index 6556fdeea834..32e78790abdb 100644 --- a/test/CodeGen/X86/loop-strength-reduce4.ll +++ b/test/CodeGen/X86/loop-strength-reduce4.ll @@ -4,10 +4,10 @@ ; By starting the IV at -64 instead of 0, a cmp is eliminated, ; as the flags from the add can be used directly. -; STATIC: movl $-64, %ecx +; STATIC: movl $-64, [[ECX:%e..]] -; STATIC: movl %eax, _state+76(%ecx) -; STATIC: addl $16, %ecx +; STATIC: movl [[EAX:%e..]], _state+76([[ECX]]) +; STATIC: addl $16, [[ECX]] ; STATIC: jne ; In PIC mode the symbol can't be folded, so the change-compare-stride diff --git a/test/CodeGen/X86/lsr-interesting-step.ll b/test/CodeGen/X86/lsr-interesting-step.ll index 4b7050bd507b..d1de0510a046 100644 --- a/test/CodeGen/X86/lsr-interesting-step.ll +++ b/test/CodeGen/X86/lsr-interesting-step.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=x86-64 -relocation-model=static -mtriple=x86_64-unknown-linux-gnu +; RUN: llc < %s -march=x86-64 -relocation-model=static -mtriple=x86_64-unknown-linux-gnu -asm-verbose=0 | FileCheck %s ; The inner loop should require only one add (and no leas either). ; rdar://8100380 -; CHECK: BB0_4: +; CHECK: BB0_3: ; CHECK-NEXT: movb $0, flags(%rdx) ; CHECK-NEXT: addq %rcx, %rdx ; CHECK-NEXT: cmpq $8192, %rdx diff --git a/test/CodeGen/X86/lsr-quadratic-expand.ll b/test/CodeGen/X86/lsr-quadratic-expand.ll new file mode 100644 index 000000000000..2bbb47092904 --- /dev/null +++ b/test/CodeGen/X86/lsr-quadratic-expand.ll @@ -0,0 +1,22 @@ +; RUN: llc -march=x86-64 < %s + +define void @dw2102_i2c_transfer() nounwind { +entry: + br label %bb + +bb: ; preds = %bb, %entry + %z = phi i64 [ 0, %entry ], [ %z3, %bb ] + %z1 = phi i16 [ undef, %entry ], [ %z6, %bb ] + %z2 = phi i32 [ 0, %entry ], [ %z8, %bb ] + %z3 = add i64 %z, 1 + %z4 = zext i16 %z1 to i32 + %z5 = add nsw i32 %z4, %z2 + %z6 = trunc i32 %z5 to i16 + call fastcc void @dw210x_op_rw(i16 zeroext %z6) + %z7 = getelementptr i8* null, i64 %z + store i8 undef, i8* %z7, align 1 + %z8 = add nsw i32 %z2, 1 + br label %bb +} + +declare fastcc void @dw210x_op_rw(i16 zeroext) nounwind diff --git a/test/CodeGen/X86/lsr-redundant-addressing.ll b/test/CodeGen/X86/lsr-redundant-addressing.ll new file mode 100644 index 000000000000..aaa1426918f2 --- /dev/null +++ b/test/CodeGen/X86/lsr-redundant-addressing.ll @@ -0,0 +1,45 @@ +; RUN: llc -march=x86-64 < %s | fgrep {addq $-16,} | count 1 +; rdar://9081094 + +; LSR shouldn't create lots of redundant address computations. + +%0 = type { i32, [3 x i32] } +%1 = type { i32 (i32, i32, i32)*, i32, i32, [3 x i32], i8*, i8*, i8* } + +@pgm = external hidden unnamed_addr global [5 x %0], align 32 +@isa = external hidden unnamed_addr constant [13 x %1], align 32 + +define void @main_bb.i() nounwind { +bb: + br label %bb38 + +bb38: ; preds = %bb200, %bb + %tmp39 = phi i64 [ %tmp201, %bb200 ], [ 0, %bb ] + %tmp40 = sub i64 0, %tmp39 + %tmp47 = getelementptr [5 x %0]* @pgm, i64 0, i64 %tmp40, i32 0 + %tmp34 = load i32* %tmp47, align 16 + %tmp203 = icmp slt i32 %tmp34, 12 + br i1 %tmp203, label %bb215, label %bb200 + +bb200: ; preds = %bb38 + %tmp201 = add i64 %tmp39, 1 + br label %bb38 + +bb215: ; preds = %bb38 + %tmp50 = getelementptr [5 x %0]* @pgm, i64 0, i64 %tmp40, i32 1, i64 2 + %tmp49 = getelementptr [5 x %0]* @pgm, i64 0, i64 %tmp40, i32 1, i64 1 + %tmp48 = getelementptr [5 x %0]* @pgm, i64 0, i64 %tmp40, i32 1, i64 0 + %tmp216 = add nsw i32 %tmp34, 1 + store i32 %tmp216, i32* %tmp47, align 16 + %tmp217 = sext i32 %tmp216 to i64 + %tmp218 = getelementptr inbounds [13 x %1]* @isa, i64 0, i64 %tmp217, i32 3, i64 0 + %tmp219 = load i32* %tmp218, align 8 + store i32 %tmp219, i32* %tmp48, align 4 + %tmp220 = getelementptr inbounds [13 x %1]* @isa, i64 0, i64 %tmp217, i32 3, i64 1 + %tmp221 = load i32* %tmp220, align 4 + store i32 %tmp221, i32* %tmp49, align 4 + %tmp222 = getelementptr inbounds [13 x %1]* @isa, i64 0, i64 %tmp217, i32 3, i64 2 + %tmp223 = load i32* %tmp222, align 8 + store i32 %tmp223, i32* %tmp50, align 4 + ret void +} diff --git a/test/CodeGen/X86/lsr-reuse-trunc.ll b/test/CodeGen/X86/lsr-reuse-trunc.ll index 29f03d68dade..47705190b0f4 100644 --- a/test/CodeGen/X86/lsr-reuse-trunc.ll +++ b/test/CodeGen/X86/lsr-reuse-trunc.ll @@ -4,8 +4,9 @@ ; Full strength reduction wouldn't reduce register pressure, so LSR should ; stick with indexing here. -; CHECK: movaps (%{{rsi|rdx}},%rax,4), %xmm3 -; CHECK: movaps %xmm3, (%{{rdi|rcx}},%rax,4) +; CHECK: movaps (%{{rsi|rdx}},%rax,4), [[X3:%xmm[0-9]+]] +; CHECK: movaps +; CHECK: [[X3]], (%{{rdi|rcx}},%rax,4) ; CHECK: addq $4, %rax ; CHECK: cmpl %eax, (%{{rdx|r8}}) ; CHECK-NEXT: jg diff --git a/test/CodeGen/X86/lsr-reuse.ll b/test/CodeGen/X86/lsr-reuse.ll index 2a9762928329..527a5a60e868 100644 --- a/test/CodeGen/X86/lsr-reuse.ll +++ b/test/CodeGen/X86/lsr-reuse.ll @@ -1,3 +1,4 @@ +; XFAIL: * ; RUN: llc < %s -march=x86-64 -O3 -asm-verbose=false | FileCheck %s target datalayout = "e-p:64:64:64" target triple = "x86_64-unknown-unknown" diff --git a/test/CodeGen/X86/machine-cse.ll b/test/CodeGen/X86/machine-cse.ll index e284776ed02d..d819fc8f6ecd 100644 --- a/test/CodeGen/X86/machine-cse.ll +++ b/test/CodeGen/X86/machine-cse.ll @@ -6,11 +6,11 @@ %struct.s2 = type { i32, i8*, i8*, [256 x %struct.s1*], [8 x i32], i64, i8*, i32, i64, i64, i32, %struct.s3*, %struct.s3*, [49 x i64] } %struct.s3 = type { %struct.s3*, %struct.s3*, i32, i32, i32 } -define fastcc i8* @t(i64 %size) nounwind { +define fastcc i8* @t(i32 %base) nounwind { entry: ; CHECK: t: ; CHECK: leaq (%rax,%rax,4) - %0 = zext i32 undef to i64 + %0 = zext i32 %base to i64 %1 = getelementptr inbounds %struct.s2* null, i64 %0 br i1 undef, label %bb1, label %bb2 diff --git a/test/CodeGen/X86/mcinst-lowering-cmp0.ll b/test/CodeGen/X86/mcinst-lowering-cmp0.ll deleted file mode 100644 index 756be1fabfda..000000000000 --- a/test/CodeGen/X86/mcinst-lowering-cmp0.ll +++ /dev/null @@ -1,68 +0,0 @@ -; RUN: llc --show-mc-encoding -relocation-model=pic -disable-fp-elim -O3 < %s | FileCheck %s - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" -target triple = "i386-apple-darwin10.0.0" - -%struct.NSConstantString = type { i32*, i32, i8*, i32 } -%struct._objc_module = type { i32, i32, i8*, %struct._objc_symtab* } -%struct._objc_symtab = type { i32, i8*, i16, i16, [0 x i8*] } - -@"\01L_OBJC_IMAGE_INFO" = internal constant [2 x i32] [i32 0, i32 16], section "__OBJC, __image_info,regular" ; <[2 x i32]*> [#uses=1] -@"\01L_OBJC_METH_VAR_NAME_" = internal global [4 x i8] c"foo\00", section "__TEXT,__cstring,cstring_literals", align 1 ; <[4 x i8]*> [#uses=1] -@"\01L_OBJC_SELECTOR_REFERENCES_" = internal global i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), section "__OBJC,__message_refs,literal_pointers,no_dead_strip", align 4 ; <i8**> [#uses=3] -@__CFConstantStringClassReference = external global [0 x i32] ; <[0 x i32]*> [#uses=1] -@.str = private constant [3 x i8] c"||\00" ; <[3 x i8]*> [#uses=1] -@_unnamed_cfstring_ = private constant %struct.NSConstantString { i32* getelementptr inbounds ([0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), i32 1992, i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i32 2 }, section "__DATA,__cfstring" ; <%struct.NSConstantString*> [#uses=1] -@"\01L_OBJC_METH_VAR_NAME_1" = internal global [5 x i8] c"baz:\00", section "__TEXT,__cstring,cstring_literals", align 1 ; <[5 x i8]*> [#uses=1] -@"\01L_OBJC_SELECTOR_REFERENCES_2" = internal global i8* getelementptr inbounds ([5 x i8]* @"\01L_OBJC_METH_VAR_NAME_1", i32 0, i32 0), section "__OBJC,__message_refs,literal_pointers,no_dead_strip", align 4 ; <i8**> [#uses=2] -@"\01L_OBJC_METH_VAR_NAME_3" = internal global [4 x i8] c"bar\00", section "__TEXT,__cstring,cstring_literals", align 1 ; <[4 x i8]*> [#uses=1] -@"\01L_OBJC_SELECTOR_REFERENCES_4" = internal global i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_3", i32 0, i32 0), section "__OBJC,__message_refs,literal_pointers,no_dead_strip", align 4 ; <i8**> [#uses=2] -@"\01L_OBJC_CLASS_NAME_" = internal global [1 x i8] zeroinitializer, section "__TEXT,__cstring,cstring_literals", align 1 ; <[1 x i8]*> [#uses=1] -@"\01L_OBJC_MODULES" = internal global %struct._objc_module { i32 7, i32 16, i8* getelementptr inbounds ([1 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), %struct._objc_symtab* null }, section "__OBJC,__module_info,regular,no_dead_strip", align 4 ; <%struct._objc_module*> [#uses=1] -@llvm.used = appending global [9 x i8*] [i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*), i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_" to i8*), i8* getelementptr inbounds ([5 x i8]* @"\01L_OBJC_METH_VAR_NAME_1", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_2" to i8*), i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_3", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_4" to i8*), i8* getelementptr inbounds ([1 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), i8* bitcast (%struct._objc_module* @"\01L_OBJC_MODULES" to i8*)], section "llvm.metadata" ; <[9 x i8*]*> [#uses=0] - -define void @f0(i8* nocapture %a, i8* nocapture %b) nounwind optsize ssp { -entry: - %call = tail call i32 (...)* @get_name() nounwind optsize ; <i32> [#uses=2] - %conv = inttoptr i32 %call to i8* ; <i8*> [#uses=1] - %call1 = tail call i32 (...)* @get_dict() nounwind optsize ; <i32> [#uses=2] - %conv2 = inttoptr i32 %call1 to i8* ; <i8*> [#uses=2] - -; Check that we lower to the short form of cmpl, which has an 8-bit immediate. -; -; CHECK: cmpl $0, -16(%ebp) ## 4-byte Folded Reload -; CHECK: ## encoding: [0x83,0x7d,0xf0,0x00] -; rdar://7999130 - %cmp = icmp eq i32 %call1, 0 ; <i1> [#uses=1] - br i1 %cmp, label %if.end, label %if.then - -if.then: ; preds = %entry - %tmp5 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_" ; <i8*> [#uses=1] - %call6 = tail call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %conv2, i8* %tmp5) nounwind optsize ; <i8*> [#uses=1] - %tmp7 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_2" ; <i8*> [#uses=1] - %call820 = tail call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %call6, i8* %tmp7, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring_ to i8*)) nounwind optsize ; <i8*> [#uses=0] - br label %if.end - -if.end: ; preds = %entry, %if.then - %tmp10 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_" ; <i8*> [#uses=1] - %call11 = tail call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %conv2, i8* %tmp10) nounwind optsize ; <i8*> [#uses=1] - %tmp12 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_4" ; <i8*> [#uses=1] - %call13 = tail call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %call11, i8* %tmp12) nounwind optsize ; <i8*> [#uses=0] - %cmp15 = icmp eq i32 %call, 0 ; <i1> [#uses=1] - br i1 %cmp15, label %if.end19, label %if.then17 - -if.then17: ; preds = %if.end - tail call void (...)* @f1(i8* %conv) nounwind optsize - ret void - -if.end19: ; preds = %if.end - ret void -} - -declare i32 @get_name(...) optsize - -declare i32 @get_dict(...) optsize - -declare i8* @objc_msgSend(i8*, i8*, ...) - -declare void @f1(...) optsize diff --git a/test/CodeGen/X86/mmx-copy-gprs.ll b/test/CodeGen/X86/mmx-copy-gprs.ll index 3607043e94fc..377875565bf8 100644 --- a/test/CodeGen/X86/mmx-copy-gprs.ll +++ b/test/CodeGen/X86/mmx-copy-gprs.ll @@ -1,10 +1,12 @@ -; RUN: llc < %s -march=x86-64 | grep {movq.*(%rsi), %rax} -; RUN: llc < %s -march=x86 -mattr=-sse2 | grep {movl.*4(%eax),} -; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {movsd.(%eax),} +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=-sse2 | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s ; This test should use GPRs to copy the mmx value, not MMX regs. Using mmx regs, ; increases the places that need to use emms. - +; CHECK-NOT: %mm +; CHECK-NOT: emms ; rdar://5741668 define void @foo(<1 x i64>* %x, <1 x i64>* %y) nounwind { diff --git a/test/CodeGen/X86/narrow-shl-cst.ll b/test/CodeGen/X86/narrow-shl-cst.ll new file mode 100644 index 000000000000..a404f34b9caa --- /dev/null +++ b/test/CodeGen/X86/narrow-shl-cst.ll @@ -0,0 +1,101 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s +; PR5039 + +define i32 @test1(i32 %x) nounwind { + %and = shl i32 %x, 10 + %shl = and i32 %and, 31744 + ret i32 %shl +; CHECK: test1: +; CHECK: andl $31 +; CHECK: shll $10 +} + +define i32 @test2(i32 %x) nounwind { + %or = shl i32 %x, 10 + %shl = or i32 %or, 31744 + ret i32 %shl +; CHECK: test2: +; CHECK: orl $31 +; CHECK: shll $10 +} + +define i32 @test3(i32 %x) nounwind { + %xor = shl i32 %x, 10 + %shl = xor i32 %xor, 31744 + ret i32 %shl +; CHECK: test3: +; CHECK: xorl $31 +; CHECK: shll $10 +} + +define i64 @test4(i64 %x) nounwind { + %and = shl i64 %x, 40 + %shl = and i64 %and, 264982302294016 + ret i64 %shl +; CHECK: test4: +; CHECK: andq $241 +; CHECK: shlq $40 +} + +define i64 @test5(i64 %x) nounwind { + %and = shl i64 %x, 40 + %shl = and i64 %and, 34084860461056 + ret i64 %shl +; CHECK: test5: +; CHECK: andq $31 +; CHECK: shlq $40 +} + +define i64 @test6(i64 %x) nounwind { + %and = shl i64 %x, 32 + %shl = and i64 %and, -281474976710656 + ret i64 %shl +; CHECK: test6: +; CHECK: andq $-65536 +; CHECK: shlq $32 +} + +define i64 @test7(i64 %x) nounwind { + %or = shl i64 %x, 40 + %shl = or i64 %or, 264982302294016 + ret i64 %shl +; CHECK: test7: +; CHECK: orq $241 +; CHECK: shlq $40 +} + +define i64 @test8(i64 %x) nounwind { + %or = shl i64 %x, 40 + %shl = or i64 %or, 34084860461056 + ret i64 %shl +; CHECK: test8: +; CHECK: orq $31 +; CHECK: shlq $40 +} + +define i64 @test9(i64 %x) nounwind { + %xor = shl i64 %x, 40 + %shl = xor i64 %xor, 264982302294016 + ret i64 %shl +; CHECK: test9: +; CHECK: orq $241 +; CHECK: shlq $40 +} + +define i64 @test10(i64 %x) nounwind { + %xor = shl i64 %x, 40 + %shl = xor i64 %xor, 34084860461056 + ret i64 %shl +; CHECK: test10: +; CHECK: xorq $31 +; CHECK: shlq $40 +} + +define i64 @test11(i64 %x) nounwind { + %xor = shl i64 %x, 33 + %shl = xor i64 %xor, -562949953421312 + ret i64 %shl +; CHECK: test11: +; CHECK: xorq $-65536 +; CHECK: shlq $33 +} diff --git a/test/CodeGen/X86/no-cfi.ll b/test/CodeGen/X86/no-cfi.ll new file mode 100644 index 000000000000..f9985d458512 --- /dev/null +++ b/test/CodeGen/X86/no-cfi.ll @@ -0,0 +1,38 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -disable-cfi | FileCheck --check-prefix=STATIC %s +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -disable-cfi -relocation-model=pic | FileCheck --check-prefix=PIC %s + +; STATIC: .ascii "zPLR" +; STATIC: .byte 3 +; STATIC-NEXT: .long __gxx_personality_v0 +; STATIC-NEXT: .byte 3 +; STATIC-NEXT: .byte 3 + +; PIC: .ascii "zPLR" +; PIC: .byte 155 +; PIC-NEXT: .L +; PIC-NEXT: .long DW.ref.__gxx_personality_v0-.L +; PIC-NEXT: .byte 27 +; PIC-NEXT: .byte 27 + + +define void @bar() { +entry: + %call = invoke i32 @foo() + to label %invoke.cont unwind label %lpad + +invoke.cont: + ret void + +lpad: + %exn = call i8* @llvm.eh.exception() nounwind + %eh.selector = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* null) nounwind + ret void +} + +declare i32 @foo() + +declare i8* @llvm.eh.exception() nounwind readonly + +declare i32 @__gxx_personality_v0(...) + +declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind diff --git a/test/CodeGen/X86/optimize-max-3.ll b/test/CodeGen/X86/optimize-max-3.ll index b90413d40a0f..e35eb7036723 100644 --- a/test/CodeGen/X86/optimize-max-3.ll +++ b/test/CodeGen/X86/optimize-max-3.ll @@ -45,8 +45,8 @@ for.end: ; preds = %for.body, %entry ; CHECK-NEXT: align ; CHECK-NEXT: BB1_2: ; CHECK-NEXT: callq -; CHECK-NEXT: incl [[BX:%ebx|%esi]] -; CHECK-NEXT: cmpl [[R14:%r14d|%edi]], [[BX]] +; CHECK-NEXT: incl [[BX:%[a-z0-9]+]] +; CHECK-NEXT: cmpl [[R14:%[a-z0-9]+]], [[BX]] ; CHECK-NEXT: movq %rax, %r{{di|cx}} ; CHECK-NEXT: jl diff --git a/test/CodeGen/X86/or-address.ll b/test/CodeGen/X86/or-address.ll index 6447680e623b..b3fc62736b38 100644 --- a/test/CodeGen/X86/or-address.ll +++ b/test/CodeGen/X86/or-address.ll @@ -4,10 +4,10 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 target triple = "x86_64-apple-darwin10.3" -; CHECK: movl %{{.*}}, (%rdi,%rdx,4) -; CHECK: movl %{{.*}}, 8(%rdi,%rdx,4) -; CHECK: movl %{{.*}}, 4(%rdi,%rdx,4) -; CHECK: movl %{{.*}}, 12(%rdi,%rdx,4) +; CHECK: movl %{{.*}}, (%rdi,[[R0:.+]],4) +; CHECK: movl %{{.*}}, 8(%rdi,[[R0]],4) +; CHECK: movl %{{.*}}, 4(%rdi,[[R0]],4) +; CHECK: movl %{{.*}}, 12(%rdi,[[R0]],4) define void @test(i32* nocapture %array, i32 %r0) nounwind ssp noredzone { bb.nph: diff --git a/test/CodeGen/X86/peep-vector-extract-concat.ll b/test/CodeGen/X86/peep-vector-extract-concat.ll index e4ab2b5e05a4..606a9be68bd4 100644 --- a/test/CodeGen/X86/peep-vector-extract-concat.ll +++ b/test/CodeGen/X86/peep-vector-extract-concat.ll @@ -1,4 +1,9 @@ -; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse41 | grep {pshufd \$3, %xmm0, %xmm0} +; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse2,-sse41 | FileCheck %s +; CHECK: pshufd $3, %xmm0, %xmm0 + +; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse2,-sse41 | FileCheck %s -check-prefix=WIN64 +; %a is passed indirectly on Win64. +; WIN64: movss 12(%rcx), %xmm0 define float @foo(<8 x float> %a) nounwind { %c = extractelement <8 x float> %a, i32 3 diff --git a/test/CodeGen/X86/personality.ll b/test/CodeGen/X86/personality.ll index 6789bb0c0fbe..e952a9bb25a4 100644 --- a/test/CodeGen/X86/personality.ll +++ b/test/CodeGen/X86/personality.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin9 | FileCheck %s -check-prefix=X64 -; RUN: llc < %s -mtriple=i386-apple-darwin9 | FileCheck %s -check-prefix=X32 +; RUN: llc < %s -disable-cfi -mtriple=x86_64-apple-darwin9 -disable-cgp-branch-opts | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -disable-cfi -mtriple=i386-apple-darwin9 -disable-cgp-branch-opts | FileCheck %s -check-prefix=X32 ; PR1632 define void @_Z1fv() { @@ -38,13 +38,15 @@ declare void @__gxx_personality_v0() declare void @__cxa_end_catch() -; X64: Leh_frame_common_begin0: -; X64: .long ___gxx_personality_v0@GOTPCREL+4 +; X64: zPLR +; X64: .byte 155 +; X64-NEXT: .long ___gxx_personality_v0@GOTPCREL+4 -; X32: Leh_frame_common_begin0: -; X32: .long L___gxx_personality_v0$non_lazy_ptr- -; .... +; X32: .section __IMPORT,__pointers,non_lazy_symbol_pointers +; X32-NEXT: L___gxx_personality_v0$non_lazy_ptr: +; X32-NEXT: .indirect_symbol ___gxx_personality_v0 -; X32: .section __IMPORT,__pointers,non_lazy_symbol_pointers -; X32: L___gxx_personality_v0$non_lazy_ptr: -; X32: .indirect_symbol ___gxx_personality_v0 +; X32: zPLR +; X32: .byte 155 +; X32-NEXT: : +; X32-NEXT: .long L___gxx_personality_v0$non_lazy_ptr- diff --git a/test/CodeGen/X86/phi-constants.ll b/test/CodeGen/X86/phi-bit-propagation.ll index da9652f73404..94c97229b092 100644 --- a/test/CodeGen/X86/phi-constants.ll +++ b/test/CodeGen/X86/phi-bit-propagation.ll @@ -33,3 +33,23 @@ return: ; preds = %for.body, %for.cond %retval.0 = phi i1 [ true, %for.body ], [ false, %for.cond ] ret i1 %retval.0 } + +; This test case caused an assertion failure; see PR9324. +define void @func_37() noreturn nounwind ssp { +entry: + br i1 undef, label %lbl_919, label %entry.for.inc_crit_edge + +entry.for.inc_crit_edge: ; preds = %entry + br label %for.inc + +lbl_919: ; preds = %for.cond7.preheader, %entry + br label %for.cond7.preheader + +for.cond7.preheader: ; preds = %for.inc, %lbl_919 + %storemerge.ph = phi i8 [ 0, %lbl_919 ], [ %add, %for.inc ] + br i1 undef, label %for.inc, label %lbl_919 + +for.inc: ; preds = %for.cond7.preheader, %entry.for.inc_crit_edge + %add = add i8 undef, 1 + br label %for.cond7.preheader +} diff --git a/test/CodeGen/X86/pic.ll b/test/CodeGen/X86/pic.ll index dc5fcd78dc84..fb60ac2a60b9 100644 --- a/test/CodeGen/X86/pic.ll +++ b/test/CodeGen/X86/pic.ll @@ -79,8 +79,8 @@ entry: ; LINUX-NEXT: .L3$pb: ; LINUX: popl ; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L3$pb), %[[REG3:e..]] -; LINUX: movl pfoo@GOT(%[[REG3]]), ; LINUX: calll afoo@PLT +; LINUX: movl pfoo@GOT(%[[REG3]]), ; LINUX: calll * } diff --git a/test/CodeGen/X86/pmulld.ll b/test/CodeGen/X86/pmulld.ll index 3ef594112b45..be527aed9a98 100644 --- a/test/CodeGen/X86/pmulld.ll +++ b/test/CodeGen/X86/pmulld.ll @@ -1,8 +1,13 @@ -; RUN: llc < %s -march=x86-64 -mattr=+sse41 -asm-verbose=0 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse41 -asm-verbose=0 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse41 -asm-verbose=0 | FileCheck %s -check-prefix=WIN64 define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind { ; CHECK: test1: ; CHECK-NEXT: pmulld + +; WIN64: test1: +; WIN64-NEXT: movdqa (%rcx), %xmm0 +; WIN64-NEXT: pmulld (%rdx), %xmm0 %C = mul <4 x i32> %A, %B ret <4 x i32> %C } @@ -10,6 +15,11 @@ define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind { define <4 x i32> @test1a(<4 x i32> %A, <4 x i32> *%Bp) nounwind { ; CHECK: test1a: ; CHECK-NEXT: pmulld + +; WIN64: test1a: +; WIN64-NEXT: movdqa (%rcx), %xmm0 +; WIN64-NEXT: pmulld (%rdx), %xmm0 + %B = load <4 x i32>* %Bp %C = mul <4 x i32> %A, %B ret <4 x i32> %C diff --git a/test/CodeGen/X86/postra-licm.ll b/test/CodeGen/X86/postra-licm.ll index 902c69b471db..48c48aebe5be 100644 --- a/test/CodeGen/X86/postra-licm.ll +++ b/test/CodeGen/X86/postra-licm.ll @@ -2,6 +2,7 @@ ; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s -check-prefix=X86-64 ; MachineLICM should be able to hoist loop invariant reload out of the loop. +; Only linear scan needs this, -regalloc=greedy sinks the spill instead. ; rdar://7233099 %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } @@ -68,10 +69,12 @@ bb26.preheader: ; preds = %imix_test.exit bb23: ; preds = %imix_test.exit unreachable +; Verify that there are no loads inside the loop. ; X86-32: %bb26.preheader -; X86-32: movl -16(%ebp), -; X86-32-NEXT: .align 4 -; X86-32-NEXT: %bb28 +; X86-32: .align 4 +; X86-32-NOT: (%esp), +; X86-32-NOT: (%ebp), +; X86-32: jmp bb28: ; preds = %bb28, %bb26.preheader %counter.035 = phi i32 [ %3, %bb28 ], [ 0, %bb26.preheader ] ; <i32> [#uses=2] diff --git a/test/CodeGen/X86/pr2659.ll b/test/CodeGen/X86/pr2659.ll index 54d043d54f83..ef0f9ea8b03a 100644 --- a/test/CodeGen/X86/pr2659.ll +++ b/test/CodeGen/X86/pr2659.ll @@ -18,7 +18,8 @@ forcond.preheader: ; preds = %entry ; CHECK: movl $1 ; CHECK-NOT: xorl ; CHECK-NOT: movl -; CHECK-NEXT: je +; CHECK-NOT: LBB +; CHECK: je ifthen: ; preds = %entry ret i32 0 diff --git a/test/CodeGen/X86/pr3366.ll b/test/CodeGen/X86/pr3366.ll index f813e2e58801..1127b6093215 100644 --- a/test/CodeGen/X86/pr3366.ll +++ b/test/CodeGen/X86/pr3366.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | grep movzbl +; RUN: llc < %s -march=x86 -disable-cgp-branch-opts | grep movzbl ; PR3366 define void @_ada_c34002a() nounwind { diff --git a/test/CodeGen/X86/pr3495-2.ll b/test/CodeGen/X86/pr3495-2.ll index 98c064a07db9..a4204e528930 100644 --- a/test/CodeGen/X86/pr3495-2.ll +++ b/test/CodeGen/X86/pr3495-2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -relocation-model=pic -disable-fp-elim -stats |& grep {Number of loads added} | grep 1 +; RUN: llc < %s -march=x86 -relocation-model=pic -disable-fp-elim -stats -regalloc=linearscan |& grep {Number of loads added} | grep 1 ; PR3495 ; ; This test may not be testing what it was supposed to test. diff --git a/test/CodeGen/X86/pr3495.ll b/test/CodeGen/X86/pr3495.ll index e84a84f59bb7..c612a6ec8bbc 100644 --- a/test/CodeGen/X86/pr3495.ll +++ b/test/CodeGen/X86/pr3495.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=x86 -stats |& grep {Number of loads added} | grep 2 -; RUN: llc < %s -march=x86 -stats |& grep {Number of register spills} | grep 1 -; RUN: llc < %s -march=x86 -stats |& grep {Number of machine instrs printed} | grep 34 +; RUN: llc < %s -march=x86 -stats -regalloc=linearscan |& grep {Number of loads added} | grep 2 +; RUN: llc < %s -march=x86 -stats -regalloc=linearscan |& grep {Number of register spills} | grep 1 +; RUN: llc < %s -march=x86 -stats -regalloc=linearscan |& grep {Number of machine instrs printed} | grep 34 ; PR3495 target triple = "i386-pc-linux-gnu" diff --git a/test/CodeGen/X86/pr9743.ll b/test/CodeGen/X86/pr9743.ll new file mode 100644 index 000000000000..8feccd9ef1c2 --- /dev/null +++ b/test/CodeGen/X86/pr9743.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -disable-fp-elim -asm-verbose=0 | FileCheck %s + +define void @f() { + ret void +} + +; CHECK: .cfi_startproc +; CHECK-NEXT: pushq +; CHECK-NEXT: : +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: : +; CHECK-NEXT: .cfi_offset 6, -16 +; CHECK-NEXT: movq %rsp, %rbp +; CHECK-NEXT: : +; CHECK-NEXT: .cfi_def_cfa_register 6 +; CHECK-NEXT: popq %rbp +; CHECK-NEXT: ret diff --git a/test/CodeGen/X86/pre-split1.ll b/test/CodeGen/X86/pre-split1.ll index e89b507414eb..b55bf5710767 100644 --- a/test/CodeGen/X86/pre-split1.ll +++ b/test/CodeGen/X86/pre-split1.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \ +; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan -stats |& \ ; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 1 ; XFAIL: * diff --git a/test/CodeGen/X86/pre-split10.ll b/test/CodeGen/X86/pre-split10.ll index db039bd97acd..83c6450c0ab9 100644 --- a/test/CodeGen/X86/pre-split10.ll +++ b/test/CodeGen/X86/pre-split10.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split +; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan define i32 @main(i32 %argc, i8** %argv) nounwind { entry: diff --git a/test/CodeGen/X86/pre-split11.ll b/test/CodeGen/X86/pre-split11.ll index 0a9f4e33f34c..3d549f9111ec 100644 --- a/test/CodeGen/X86/pre-split11.ll +++ b/test/CodeGen/X86/pre-split11.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse2 -pre-alloc-split | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse2 -pre-alloc-split -regalloc=linearscan | FileCheck %s @.str = private constant [28 x i8] c"\0A\0ADOUBLE D = %f\0A\00", align 1 ; <[28 x i8]*> [#uses=1] @.str1 = private constant [37 x i8] c"double to long l1 = %ld\09\09(0x%lx)\0A\00", align 8 ; <[37 x i8]*> [#uses=1] diff --git a/test/CodeGen/X86/pre-split2.ll b/test/CodeGen/X86/pre-split2.ll index ba902f95513d..670737b72df1 100644 --- a/test/CodeGen/X86/pre-split2.ll +++ b/test/CodeGen/X86/pre-split2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \ +; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats -regalloc=linearscan |& \ ; RUN: grep {pre-alloc-split} | count 2 define i32 @t(i32 %arg) { diff --git a/test/CodeGen/X86/pre-split3.ll b/test/CodeGen/X86/pre-split3.ll index 2e314207c3e3..0c49a913353c 100644 --- a/test/CodeGen/X86/pre-split3.ll +++ b/test/CodeGen/X86/pre-split3.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \ +; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan -stats |& \ ; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 1 define i32 @t(i32 %arg) { diff --git a/test/CodeGen/X86/pre-split4.ll b/test/CodeGen/X86/pre-split4.ll index 10cef276c62f..37d1ac6301f0 100644 --- a/test/CodeGen/X86/pre-split4.ll +++ b/test/CodeGen/X86/pre-split4.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \ +; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan -stats |& \ ; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 2 define i32 @main(i32 %argc, i8** %argv) nounwind { diff --git a/test/CodeGen/X86/pre-split5.ll b/test/CodeGen/X86/pre-split5.ll index 8def460809f2..9f41f24c73e5 100644 --- a/test/CodeGen/X86/pre-split5.ll +++ b/test/CodeGen/X86/pre-split5.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split +; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan target triple = "i386-apple-darwin9.5" %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } diff --git a/test/CodeGen/X86/pre-split6.ll b/test/CodeGen/X86/pre-split6.ll index 837e238b6208..d8f274db2c9a 100644 --- a/test/CodeGen/X86/pre-split6.ll +++ b/test/CodeGen/X86/pre-split6.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -pre-alloc-split | grep {divsd 24} | count 1 +; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -pre-alloc-split -regalloc=linearscan | grep {divsd 24} | count 1 @current_surfaces.b = external global i1 ; <i1*> [#uses=1] diff --git a/test/CodeGen/X86/pre-split7.ll b/test/CodeGen/X86/pre-split7.ll index 0b81c0bc09fe..8c93faac677c 100644 --- a/test/CodeGen/X86/pre-split7.ll +++ b/test/CodeGen/X86/pre-split7.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split +; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan @object_distance = external global double, align 8 ; <double*> [#uses=1] @axis_slope_angle = external global double, align 8 ; <double*> [#uses=1] diff --git a/test/CodeGen/X86/pre-split8.ll b/test/CodeGen/X86/pre-split8.ll index 0684bd036ce2..7e6ad6e17695 100644 --- a/test/CodeGen/X86/pre-split8.ll +++ b/test/CodeGen/X86/pre-split8.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \ +; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan -stats |& \ ; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 1 @current_surfaces.b = external global i1 ; <i1*> [#uses=1] diff --git a/test/CodeGen/X86/pre-split9.ll b/test/CodeGen/X86/pre-split9.ll index 86dda33533f7..951e6fb28a11 100644 --- a/test/CodeGen/X86/pre-split9.ll +++ b/test/CodeGen/X86/pre-split9.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \ +; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan -stats |& \ ; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 1 @current_surfaces.b = external global i1 ; <i1*> [#uses=1] diff --git a/test/CodeGen/X86/remat-scalar-zero.ll b/test/CodeGen/X86/remat-scalar-zero.ll index 2da96aba5531..f6f0ed10b514 100644 --- a/test/CodeGen/X86/remat-scalar-zero.ll +++ b/test/CodeGen/X86/remat-scalar-zero.ll @@ -1,3 +1,4 @@ +; XFAIL: * ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu > %t ; RUN: not grep xor %t ; RUN: not grep movap %t diff --git a/test/CodeGen/X86/scalar-min-max-fill-operand.ll b/test/CodeGen/X86/scalar-min-max-fill-operand.ll index fe40758d8ecd..2f90932c0ed8 100644 --- a/test/CodeGen/X86/scalar-min-max-fill-operand.ll +++ b/test/CodeGen/X86/scalar-min-max-fill-operand.ll @@ -1,6 +1,13 @@ -; RUN: llc < %s -march=x86-64 | grep min | count 1 -; RUN: llc < %s -march=x86-64 | grep max | count 1 -; RUN: llc < %s -march=x86-64 | grep mov | count 2 +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; CHECK-NOT: {{(min|max|mov)}} +; CHECK: mov +; CHECK-NOT: {{(min|max|mov)}} +; CHECK: min +; CHECK-NOT: {{(min|max|mov)}} +; CHECK: mov +; CHECK-NOT: {{(min|max|mov)}} +; CHECK: max +; CHECK-NOT: {{(min|max|mov)}} declare float @bar() diff --git a/test/CodeGen/X86/sext-i1.ll b/test/CodeGen/X86/sext-i1.ll index 21c418d534e9..574769b43084 100644 --- a/test/CodeGen/X86/sext-i1.ll +++ b/test/CodeGen/X86/sext-i1.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=32 -; RUN: llc < %s -march=x86-64 | FileCheck %s -check-prefix=64 +; RUN: llc < %s -march=x86 -disable-cgp-branch-opts | FileCheck %s -check-prefix=32 +; RUN: llc < %s -march=x86-64 -disable-cgp-branch-opts | FileCheck %s -check-prefix=64 ; rdar://7573216 ; PR6146 diff --git a/test/CodeGen/X86/shrink-compare.ll b/test/CodeGen/X86/shrink-compare.ll new file mode 100644 index 000000000000..8d4b07f9d9b0 --- /dev/null +++ b/test/CodeGen/X86/shrink-compare.ll @@ -0,0 +1,36 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s + +declare void @bar() + +define void @test1(i32* nocapture %X) nounwind { +entry: + %tmp1 = load i32* %X, align 4 + %and = and i32 %tmp1, 255 + %cmp = icmp eq i32 %and, 47 + br i1 %cmp, label %if.then, label %if.end + +if.then: + tail call void @bar() nounwind + br label %if.end + +if.end: + ret void +; CHECK: test1: +; CHECK: cmpb $47, (%{{rdi|rcx}}) +} + +define void @test2(i32 %X) nounwind { +entry: + %and = and i32 %X, 255 + %cmp = icmp eq i32 %and, 47 + br i1 %cmp, label %if.then, label %if.end + +if.then: + tail call void @bar() nounwind + br label %if.end + +if.end: + ret void +; CHECK: test2: +; CHECK: cmpb $47, %{{dil|cl}} +} diff --git a/test/CodeGen/X86/sse-align-0.ll b/test/CodeGen/X86/sse-align-0.ll index b12a87d614d2..8ffd31247702 100644 --- a/test/CodeGen/X86/sse-align-0.ll +++ b/test/CodeGen/X86/sse-align-0.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=x86-64 | not grep mov +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; CHECK-NOT: mov define <4 x float> @foo(<4 x float>* %p, <4 x float> %x) nounwind { %t = load <4 x float>* %p diff --git a/test/CodeGen/X86/sse-align-3.ll b/test/CodeGen/X86/sse-align-3.ll index c42f7f0bad99..04f216176c36 100644 --- a/test/CodeGen/X86/sse-align-3.ll +++ b/test/CodeGen/X86/sse-align-3.ll @@ -1,4 +1,9 @@ -; RUN: llc < %s -march=x86-64 | grep movap | count 2 +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; CHECK-NOT: movapd +; CHECK: movaps +; CHECK-NOT: movaps +; CHECK: movapd +; CHECK-NOT: movap define void @foo(<4 x float>* %p, <4 x float> %x) nounwind { store <4 x float> %x, <4 x float>* %p diff --git a/test/CodeGen/X86/sse-align-7.ll b/test/CodeGen/X86/sse-align-7.ll index 5784481c5ae9..e55d5859560e 100644 --- a/test/CodeGen/X86/sse-align-7.ll +++ b/test/CodeGen/X86/sse-align-7.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=x86-64 | grep movaps | count 1 +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; CHECK: movaps +; CHECK-NOT: movaps define void @bar(<2 x i64>* %p, <2 x i64> %x) nounwind { store <2 x i64> %x, <2 x i64>* %p diff --git a/test/CodeGen/X86/sse-commute.ll b/test/CodeGen/X86/sse-commute.ll index 38ed644e952b..336bf06e557d 100644 --- a/test/CodeGen/X86/sse-commute.ll +++ b/test/CodeGen/X86/sse-commute.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=x86-64 < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-linux < %s | FileCheck %s ; Commute the comparison to avoid a move. ; PR7500. diff --git a/test/CodeGen/X86/sse2.ll b/test/CodeGen/X86/sse2.ll index 5c3e32f016a7..70e0a8a177e0 100644 --- a/test/CodeGen/X86/sse2.ll +++ b/test/CodeGen/X86/sse2.ll @@ -178,9 +178,9 @@ define <4 x float> @test14(<4 x float>* %x, <4 x float>* %y) nounwind { %tmp27 = shufflevector <4 x float> %tmp9, <4 x float> %tmp21, <4 x i32> < i32 0, i32 1, i32 4, i32 5 > ; <<4 x float>> [#uses=1] ret <4 x float> %tmp27 ; CHECK: test14: -; CHECK: addps %xmm1, %xmm0 -; CHECK: subps %xmm1, %xmm2 -; CHECK: movlhps %xmm2, %xmm0 +; CHECK: addps [[X1:%xmm[0-9]+]], [[X0:%xmm[0-9]+]] +; CHECK: subps [[X1]], [[X2:%xmm[0-9]+]] +; CHECK: movlhps [[X2]], [[X0]] } define <4 x float> @test15(<4 x float>* %x, <4 x float>* %y) nounwind { diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll index 9a60091a0cf0..8e72f133420a 100644 --- a/test/CodeGen/X86/sse3.ll +++ b/test/CodeGen/X86/sse3.ll @@ -168,12 +168,12 @@ define internal void @t10() nounwind { store <4 x i16> %6, <4 x i16>* @g2, align 8 ret void ; X64: t10: -; X64: pextrw $4, %xmm0, %eax -; X64: unpcklpd %xmm1, %xmm1 -; X64: pshuflw $8, %xmm1, %xmm1 -; X64: pinsrw $2, %eax, %xmm1 -; X64: pextrw $6, %xmm0, %eax -; X64: pinsrw $3, %eax, %xmm1 +; X64: pextrw $4, [[X0:%xmm[0-9]+]], %eax +; X64: unpcklpd [[X1:%xmm[0-9]+]] +; X64: pshuflw $8, [[X1]], [[X1]] +; X64: pinsrw $2, %eax, [[X1]] +; X64: pextrw $6, [[X0]], %eax +; X64: pinsrw $3, %eax, [[X1]] } diff --git a/test/CodeGen/X86/sse_reload_fold.ll b/test/CodeGen/X86/sse_reload_fold.ll index dc3d6fe6797d..02399c499556 100644 --- a/test/CodeGen/X86/sse_reload_fold.ll +++ b/test/CodeGen/X86/sse_reload_fold.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -march=x86-64 -mattr=+64bit,+sse3 -print-failed-fuse-candidates |& \ -; RUN: grep fail | count 1 +; RUN: llc < %s -mtriple=x86_64-linux -mattr=+64bit,+sse3 -print-failed-fuse-candidates |& FileCheck %s +; CHECK: fail +; CHECK-NOT: fail declare float @test_f(float %f) declare double @test_d(double %f) diff --git a/test/CodeGen/X86/stdarg.ll b/test/CodeGen/X86/stdarg.ll index 9778fa138948..5728daf1ee1c 100644 --- a/test/CodeGen/X86/stdarg.ll +++ b/test/CodeGen/X86/stdarg.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=x86-64 | grep {testb \[%\]al, \[%\]al} +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; CHECK: testb %al, %al %struct.__va_list_tag = type { i32, i32, i8*, i8* } diff --git a/test/CodeGen/X86/stride-nine-with-base-reg.ll b/test/CodeGen/X86/stride-nine-with-base-reg.ll index f4847a31c81f..ddf059c675df 100644 --- a/test/CodeGen/X86/stride-nine-with-base-reg.ll +++ b/test/CodeGen/X86/stride-nine-with-base-reg.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -march=x86 -relocation-model=static | not grep lea -; RUN: llc < %s -march=x86-64 | not grep lea +; RUN: llc < %s -march=x86 -relocation-model=static | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; CHECK-NOT: lea ; P should be sunk into the loop and folded into the address mode. There ; shouldn't be any lea instructions inside the loop. diff --git a/test/CodeGen/X86/stride-reuse.ll b/test/CodeGen/X86/stride-reuse.ll index 5cbd895250a6..1251a2400555 100644 --- a/test/CodeGen/X86/stride-reuse.ll +++ b/test/CodeGen/X86/stride-reuse.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -march=x86 | not grep lea -; RUN: llc < %s -march=x86-64 | not grep lea +; RUN: llc < %s -march=x86 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; CHECK-NOT: lea @B = external global [1000 x float], align 32 @A = external global [1000 x float], align 32 diff --git a/test/CodeGen/X86/sub-with-overflow.ll b/test/CodeGen/X86/sub-with-overflow.ll index 19f4079abb5f..4522e917d315 100644 --- a/test/CodeGen/X86/sub-with-overflow.ll +++ b/test/CodeGen/X86/sub-with-overflow.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=x86 | grep {jo} | count 1 -; RUN: llc < %s -march=x86 | grep {jb} | count 1 +; RUN: llc < %s -march=x86 | FileCheck %s @ok = internal constant [4 x i8] c"%d\0A\00" @no = internal constant [4 x i8] c"no\0A\00" @@ -18,6 +17,10 @@ normal: overflow: %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind ret i1 false + +; CHECK: func1: +; CHECK: subl 20(%esp) +; CHECK-NEXT: jo } define i1 @func2(i32 %v1, i32 %v2) nounwind { @@ -34,8 +37,23 @@ normal: carry: %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind ret i1 false + +; CHECK: func2: +; CHECK: subl 20(%esp) +; CHECK-NEXT: jb } declare i32 @printf(i8*, ...) nounwind declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32) declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) + +define i1 @func3(i32 %x) nounwind { +entry: + %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %x, i32 1) + %obit = extractvalue {i32, i1} %t, 1 + ret i1 %obit + +; CHECK: func3: +; CHECK: decl +; CHECK-NEXT: seto +} diff --git a/test/CodeGen/X86/tail-opts.ll b/test/CodeGen/X86/tail-opts.ll index 9291695f4d65..77710ad56bae 100644 --- a/test/CodeGen/X86/tail-opts.ll +++ b/test/CodeGen/X86/tail-opts.ll @@ -109,15 +109,15 @@ altret: ; CHECK: dont_merge_oddly: ; CHECK-NOT: ret -; CHECK: ucomiss %xmm1, %xmm2 +; CHECK: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}} ; CHECK-NEXT: jbe .LBB2_3 -; CHECK-NEXT: ucomiss %xmm0, %xmm1 +; CHECK-NEXT: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}} ; CHECK-NEXT: ja .LBB2_4 ; CHECK-NEXT: .LBB2_2: ; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB2_3: -; CHECK-NEXT: ucomiss %xmm0, %xmm2 +; CHECK-NEXT: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}} ; CHECK-NEXT: jbe .LBB2_2 ; CHECK-NEXT: .LBB2_4: ; CHECK-NEXT: xorb %al, %al @@ -153,16 +153,20 @@ bb30: ; an unconditional jump to complete a two-way conditional branch. ; CHECK: c_expand_expr_stmt: -; CHECK: jmp .LBB3_11 -; CHECK-NEXT: .LBB3_9: -; CHECK-NEXT: movq 8(%rax), %rax -; CHECK-NEXT: xorb %dl, %dl -; CHECK-NEXT: movb 16(%rax), %al -; CHECK-NEXT: cmpb $16, %al -; CHECK-NEXT: je .LBB3_11 -; CHECK-NEXT: cmpb $23, %al -; CHECK-NEXT: jne .LBB3_14 -; CHECK-NEXT: .LBB3_11: +; +; This test only works when register allocation happens to use %rax for both +; load addresses. +; +; CHE: jmp .LBB3_11 +; CHE-NEXT: .LBB3_9: +; CHE-NEXT: movq 8(%rax), %rax +; CHE-NEXT: xorb %dl, %dl +; CHE-NEXT: movb 16(%rax), %al +; CHE-NEXT: cmpb $16, %al +; CHE-NEXT: je .LBB3_11 +; CHE-NEXT: cmpb $23, %al +; CHE-NEXT: jne .LBB3_14 +; CHE-NEXT: .LBB3_11: %0 = type { %struct.rtx_def* } %struct.lang_decl = type opaque diff --git a/test/CodeGen/X86/tailcall-returndup-void.ll b/test/CodeGen/X86/tailcall-returndup-void.ll new file mode 100644 index 000000000000..c1d631225ec7 --- /dev/null +++ b/test/CodeGen/X86/tailcall-returndup-void.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s +; CHECK: rBM_info +; CHECK-NOT: ret + +@sES_closure = external global [0 x i64] +declare cc10 void @sEH_info(i64* noalias nocapture, i64* noalias nocapture, i64* noalias nocapture, i64, i64, i64) align 8 + +define cc10 void @rBM_info(i64* noalias nocapture %Base_Arg, i64* noalias nocapture %Sp_Arg, i64* noalias nocapture %Hp_Arg, i64 %R1_Arg, i64 %R2_Arg, i64 %R3_Arg) nounwind align 8 { +c263: + %ln265 = getelementptr inbounds i64* %Sp_Arg, i64 -2 + %ln266 = ptrtoint i64* %ln265 to i64 + %ln268 = icmp ult i64 %ln266, %R3_Arg + br i1 %ln268, label %c26a, label %n26p + +n26p: ; preds = %c263 + br i1 icmp ne (i64 and (i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 7), i64 0), label %c1ZP.i, label %n1ZQ.i + +n1ZQ.i: ; preds = %n26p + %ln1ZT.i = load i64* getelementptr inbounds ([0 x i64]* @sES_closure, i64 0, i64 0), align 8 + %ln1ZU.i = inttoptr i64 %ln1ZT.i to void (i64*, i64*, i64*, i64, i64, i64)* + tail call cc10 void %ln1ZU.i(i64* %Base_Arg, i64* %Sp_Arg, i64* %Hp_Arg, i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 %R3_Arg) nounwind + br label %rBL_info.exit + +c1ZP.i: ; preds = %n26p + tail call cc10 void @sEH_info(i64* %Base_Arg, i64* %Sp_Arg, i64* %Hp_Arg, i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 ptrtoint ([0 x i64]* @sES_closure to i64), i64 %R3_Arg) nounwind + br label %rBL_info.exit + +rBL_info.exit: ; preds = %c1ZP.i, %n1ZQ.i + ret void + +c26a: ; preds = %c263 + %ln27h = getelementptr inbounds i64* %Base_Arg, i64 -2 + %ln27j = load i64* %ln27h, align 8 + %ln27k = inttoptr i64 %ln27j to void (i64*, i64*, i64*, i64, i64, i64)* + tail call cc10 void %ln27k(i64* %Base_Arg, i64* %Sp_Arg, i64* %Hp_Arg, i64 %R1_Arg, i64 %R2_Arg, i64 %R3_Arg) nounwind + ret void +} diff --git a/test/CodeGen/X86/tailcallbyval64.ll b/test/CodeGen/X86/tailcallbyval64.ll index 7c685b85807e..1b1efe713c6e 100644 --- a/test/CodeGen/X86/tailcallbyval64.ll +++ b/test/CodeGen/X86/tailcallbyval64.ll @@ -1,15 +1,30 @@ -; RUN: llc < %s -march=x86-64 -tailcallopt | grep TAILCALL +; RUN: llc < %s -mtriple=x86_64-linux -tailcallopt | FileCheck %s + +; FIXME: Win64 does not support byval. + +; Expect the entry point. +; CHECK: tailcaller: + ; Expect 2 rep;movs because of tail call byval lowering. -; RUN: llc < %s -march=x86-64 -tailcallopt | grep rep | wc -l | grep 2 +; CHECK: rep; +; CHECK: rep; + ; A sequence of copyto/copyfrom virtual registers is used to deal with byval ; lowering appearing after moving arguments to registers. The following two ; checks verify that the register allocator changes those sequences to direct ; moves to argument register where it can (for registers that are not used in ; byval lowering - not rsi, not rdi, not rcx). ; Expect argument 4 to be moved directly to register edx. -; RUN: llc < %s -march=x86-64 -tailcallopt | grep movl | grep {7} | grep edx +; CHECK: movl $7, %edx + ; Expect argument 6 to be moved directly to register r8. -; RUN: llc < %s -march=x86-64 -tailcallopt | grep movl | grep {17} | grep r8 +; CHECK: movl $17, %r8d + +; Expect not call but jmp to @tailcallee. +; CHECK: jmp tailcallee + +; Expect the trailer. +; CHECK: .size tailcaller %struct.s = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, @@ -25,5 +40,3 @@ entry: %tmp4 = tail call fastcc i64 @tailcallee(%struct.s* %a byval, i64 %tmp3, i64 %b, i64 7, i64 13, i64 17) ret i64 %tmp4 } - - diff --git a/test/CodeGen/X86/tailcallstack64.ll b/test/CodeGen/X86/tailcallstack64.ll index 0c732d56b6ca..060ce0f7aab4 100644 --- a/test/CodeGen/X86/tailcallstack64.ll +++ b/test/CodeGen/X86/tailcallstack64.ll @@ -2,19 +2,19 @@ ; RUN: llc < %s -tailcallopt -mtriple=x86_64-win32 -post-RA-scheduler=true | FileCheck %s ; FIXME: Redundant unused stack allocation could be eliminated. -; CHECK: subq ${{24|88}}, %rsp +; CHECK: subq ${{24|72}}, %rsp ; Check that lowered arguments on the stack do not overwrite each other. ; Add %in1 %p1 to a different temporary register (%eax). -; CHECK: movl [[A1:32|144]](%rsp), %eax +; CHECK: movl [[A1:32|144]](%rsp), [[R1:%e..]] ; Move param %in1 to temp register (%r10d). -; CHECK: movl [[A2:40|152]](%rsp), %r10d +; CHECK: movl [[A2:40|152]](%rsp), [[R2:%[a-z0-9]+]] ; Add %in1 %p1 to a different temporary register (%eax). -; CHECK: addl {{%edi|%ecx}}, %eax +; CHECK: addl {{%edi|%ecx}}, [[R1]] ; Move param %in2 to stack. -; CHECK: movl %r10d, [[A1]](%rsp) +; CHECK: movl [[R2]], [[A1]](%rsp) ; Move result of addition to stack. -; CHECK: movl %eax, [[A2]](%rsp) +; CHECK: movl [[R1]], [[A2]](%rsp) ; Eventually, do a TAILCALL ; CHECK: TAILCALL diff --git a/test/CodeGen/X86/test-nofold.ll b/test/CodeGen/X86/test-nofold.ll index f1063dcabf4f..97db1b340e81 100644 --- a/test/CodeGen/X86/test-nofold.ll +++ b/test/CodeGen/X86/test-nofold.ll @@ -2,10 +2,10 @@ ; rdar://5752025 ; We want: -; CHECK: movl 4(%esp), %ecx -; CHECK-NEXT: andl $15, %ecx -; CHECK-NEXT: movl $42, %eax -; CHECK-NEXT: cmovel %ecx, %eax +; CHECK: movl $42, %ecx +; CHECK-NEXT: movl 4(%esp), %eax +; CHECK-NEXT: andl $15, %eax +; CHECK-NEXT: cmovnel %ecx, %eax ; CHECK-NEXT: ret ; ; We don't want: diff --git a/test/CodeGen/X86/twoaddr-lea.ll b/test/CodeGen/X86/twoaddr-lea.ll index ec16dfe172e3..a1d797feeac4 100644 --- a/test/CodeGen/X86/twoaddr-lea.ll +++ b/test/CodeGen/X86/twoaddr-lea.ll @@ -34,3 +34,14 @@ entry: %add5 = add i32 %add3, %d ret i32 %add5 } + +; rdar://9002648 +define i64 @test3(i64 %x) nounwind readnone ssp { +entry: +; CHECK: test3: +; CHECK: leaq (%rdi,%rdi), %rax +; CHECK-NOT: addq +; CHECK-NEXT: ret + %0 = shl i64 %x, 1 + ret i64 %0 +} diff --git a/test/CodeGen/X86/umulo-64.ll b/test/CodeGen/X86/umulo-64.ll deleted file mode 100644 index 280bd9cb066d..000000000000 --- a/test/CodeGen/X86/umulo-64.ll +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin - -%0 = type { i64, i1 } - -define i32 @f0(i64 %a, i64 %b) nounwind ssp { - %1 = alloca i64, align 4 - %2 = alloca i64, align 4 - store i64 %a, i64* %1, align 8 - store i64 %b, i64* %2, align 8 - %3 = load i64* %1, align 8 - %4 = load i64* %2, align 8 - %5 = call %0 @llvm.smul.with.overflow.i64(i64 %3, i64 %4) - %6 = extractvalue %0 %5, 0 - %7 = extractvalue %0 %5, 1 - br i1 %7, label %8, label %9 - -; <label>:8 ; preds = %0 - call void @llvm.trap() - unreachable - -; <label>:9 ; preds = %0 - %10 = trunc i64 %6 to i32 - ret i32 %10 -} - -declare %0 @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone - -declare void @llvm.trap() nounwind diff --git a/test/CodeGen/X86/unaligned-load.ll b/test/CodeGen/X86/unaligned-load.ll index 6a493c0594de..9f704898d688 100644 --- a/test/CodeGen/X86/unaligned-load.ll +++ b/test/CodeGen/X86/unaligned-load.ll @@ -29,8 +29,8 @@ return: declare void @llvm.memcpy.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind ; CORE2: .section -; CORE2: .align 4 +; CORE2: .align 3 ; CORE2-NEXT: _.str1: ; CORE2-NEXT: .asciz "DHRYSTONE PROGRAM, SOME STRING" -; CORE2: .align 4 +; CORE2: .align 3 ; CORE2-NEXT: _.str3: diff --git a/test/CodeGen/X86/unknown-location.ll b/test/CodeGen/X86/unknown-location.ll index 09431b5564ae..b89c4738af12 100644 --- a/test/CodeGen/X86/unknown-location.ll +++ b/test/CodeGen/X86/unknown-location.ll @@ -4,16 +4,11 @@ ; represent this in the debug information. This is done by setting line ; and column to 0 -; CHECK: leal (%rdi,%rsi), %eax +; CHECK: leal ; CHECK-NEXT: .loc 1 0 0 -; CHECK-NEXT: Ltmp -; CHECK-NEXT: cltd -; CHECK-NEXT: idivl %r8d -; CHECK-NEXT: .loc 1 4 3 -; CHECK-NEXT: Ltmp -; CHECK-NEXT: addl %ecx, %eax -; CHECK-NEXT: ret -; CHECK-NEXT: Ltmp +; CHECK: cltd +; CHECK-NEXT: idivl +; CHECK-NEXT: .loc 2 4 3 define i32 @foo(i32 %w, i32 %x, i32 %y, i32 %z) nounwind { entry: diff --git a/test/CodeGen/X86/unreachable-stack-protector.ll b/test/CodeGen/X86/unreachable-stack-protector.ll new file mode 100644 index 000000000000..eeebceea71d4 --- /dev/null +++ b/test/CodeGen/X86/unreachable-stack-protector.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +declare i64 @llvm.objectsize.i64(i8*, i1) nounwind readnone + +define void @test5() nounwind optsize noinline ssp { +entry: +; CHECK: movq ___stack_chk_guard@GOTPCREL(%rip) + %buf = alloca [64 x i8], align 16 + %0 = call i64 @llvm.objectsize.i64(i8* undef, i1 false) + br i1 false, label %if.end, label %if.then + +if.then: ; preds = %entry + unreachable + +if.end: ; preds = %entry + ret void +} diff --git a/test/CodeGen/X86/v2f32.ll b/test/CodeGen/X86/v2f32.ll index 76c3fdfc060c..6d14099b5c0c 100644 --- a/test/CodeGen/X86/v2f32.ll +++ b/test/CodeGen/X86/v2f32.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=x86-64 -mcpu=penryn -asm-verbose=0 -o - | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-linux -mcpu=penryn -asm-verbose=0 -o - | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-win32 -mcpu=penryn -asm-verbose=0 -o - | FileCheck %s -check-prefix=W64 ; RUN: llc < %s -mcpu=yonah -march=x86 -asm-verbose=0 -o - | FileCheck %s -check-prefix=X32 ; PR7518 @@ -15,6 +16,13 @@ define void @test1(<2 x float> %Q, float *%P2) nounwind { ; X64-NEXT: movss %xmm1, (%rdi) ; X64-NEXT: ret +; W64: test1: +; W64-NEXT: movdqa (%rcx), %xmm0 +; W64-NEXT: pshufd $1, %xmm0, %xmm1 +; W64-NEXT: addss %xmm0, %xmm1 +; W64-NEXT: movss %xmm1, (%rdx) +; W64-NEXT: ret + ; X32: test1: ; X32-NEXT: pshufd $1, %xmm0, %xmm1 ; X32-NEXT: addss %xmm0, %xmm1 @@ -31,6 +39,14 @@ define <2 x float> @test2(<2 x float> %Q, <2 x float> %R, <2 x float> *%P) nounw ; X64: test2: ; X64-NEXT: addps %xmm1, %xmm0 ; X64-NEXT: ret + +; W64: test2: +; W64-NEXT: movaps (%rcx), %xmm0 +; W64-NEXT: addps (%rdx), %xmm0 +; W64-NEXT: ret + +; X32: test2: +; X32: addps %xmm1, %xmm0 } @@ -38,17 +54,35 @@ define <2 x float> @test3(<4 x float> %A) nounwind { %B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1> %C = fadd <2 x float> %B, %B ret <2 x float> %C -; CHECK: test3: -; CHECK-NEXT: addps %xmm0, %xmm0 -; CHECK-NEXT: ret +; X64: test3: +; X64-NEXT: addps %xmm0, %xmm0 +; X64-NEXT: ret + +; W64: test3: +; W64-NEXT: movaps (%rcx), %xmm0 +; W64-NEXT: addps %xmm0, %xmm0 +; W64-NEXT: ret + +; X32: test3: +; X32-NEXT: addps %xmm0, %xmm0 +; X32-NEXT: ret } define <2 x float> @test4(<2 x float> %A) nounwind { %C = fadd <2 x float> %A, %A ret <2 x float> %C -; CHECK: test4: -; CHECK-NEXT: addps %xmm0, %xmm0 -; CHECK-NEXT: ret +; X64: test4: +; X64-NEXT: addps %xmm0, %xmm0 +; X64-NEXT: ret + +; W64: test4: +; W64-NEXT: movaps (%rcx), %xmm0 +; W64-NEXT: addps %xmm0, %xmm0 +; W64-NEXT: ret + +; X32: test4: +; X32-NEXT: addps %xmm0, %xmm0 +; X32-NEXT: ret } define <4 x float> @test5(<4 x float> %A) nounwind { @@ -61,10 +95,21 @@ BB: %E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> ret <4 x float> %E -; CHECK: _test5: -; CHECK-NEXT: addps %xmm0, %xmm0 -; CHECK-NEXT: addps %xmm0, %xmm0 -; CHECK-NEXT: ret +; X64: test5: +; X64-NEXT: addps %xmm0, %xmm0 +; X64-NEXT: addps %xmm0, %xmm0 +; X64-NEXT: ret + +; W64: test5: +; W64-NEXT: movaps (%rcx), %xmm0 +; W64-NEXT: addps %xmm0, %xmm0 +; W64-NEXT: addps %xmm0, %xmm0 +; W64-NEXT: ret + +; X32: test5: +; X32-NEXT: addps %xmm0, %xmm0 +; X32-NEXT: addps %xmm0, %xmm0 +; X32-NEXT: ret } diff --git a/test/CodeGen/X86/vec_cast.ll b/test/CodeGen/X86/vec_cast.ll index 95289c9685a1..90d39d0b46ab 100644 --- a/test/CodeGen/X86/vec_cast.ll +++ b/test/CodeGen/X86/vec_cast.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=x86-64 -mcpu=core2 - +; RUN: llc < %s -mtriple=x86_64-linux -mcpu=core2 +; RUN: llc < %s -mtriple=x86_64-win32 -mcpu=core2 define <8 x i32> @a(<8 x i16> %a) nounwind { %c = sext <8 x i16> %a to <8 x i32> diff --git a/test/CodeGen/X86/vec_set-8.ll b/test/CodeGen/X86/vec_set-8.ll index 9697f1186d45..66056d0add9c 100644 --- a/test/CodeGen/X86/vec_set-8.ll +++ b/test/CodeGen/X86/vec_set-8.ll @@ -1,5 +1,8 @@ -; RUN: llc < %s -march=x86-64 | not grep movsd -; RUN: llc < %s -march=x86-64 | grep {movd.*%rdi,.*%xmm0} +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s +; CHECK-NOT: movsd +; CHECK: movd {{%rdi|%rcx}}, %xmm0 +; CHECK-NOT: movsd define <2 x i64> @test(i64 %i) nounwind { entry: diff --git a/test/CodeGen/X86/vec_shuffle-16.ll b/test/CodeGen/X86/vec_shuffle-16.ll index 470f676d4627..2ee87fe4ff86 100644 --- a/test/CodeGen/X86/vec_shuffle-16.ll +++ b/test/CodeGen/X86/vec_shuffle-16.ll @@ -1,27 +1,36 @@ -; RUN: llc < %s -march=x86 -mattr=+sse,-sse2 -mtriple=i386-apple-darwin -o %t -; RUN: grep shufps %t | count 4 -; RUN: grep movaps %t | count 2 -; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin -o %t -; RUN: grep pshufd %t | count 4 -; RUN: not grep shufps %t -; RUN: not grep mov %t +; RUN: llc < %s -march=x86 -mattr=+sse,-sse2 -mtriple=i386-apple-darwin | FileCheck %s -check-prefix=sse +; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin | FileCheck %s -check-prefix=sse2 define <4 x float> @t1(<4 x float> %a, <4 x float> %b) nounwind { +; sse: movaps +; sse: shufps +; sse2: pshufd +; sse2-NEXT: ret %tmp1 = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer ret <4 x float> %tmp1 } define <4 x float> @t2(<4 x float> %A, <4 x float> %B) nounwind { +; sse: shufps +; sse2: pshufd +; sse2-NEXT: ret %tmp = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > ret <4 x float> %tmp } define <4 x float> @t3(<4 x float> %A, <4 x float> %B) nounwind { +; sse: movaps +; sse: shufps +; sse2: pshufd +; sse2-NEXT: ret %tmp = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> < i32 4, i32 4, i32 4, i32 4 > ret <4 x float> %tmp } define <4 x float> @t4(<4 x float> %A, <4 x float> %B) nounwind { +; sse: shufps +; sse2: pshufd +; sse2-NEXT: ret %tmp = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> < i32 1, i32 3, i32 2, i32 0 > ret <4 x float> %tmp } diff --git a/test/CodeGen/X86/vec_shuffle-17.ll b/test/CodeGen/X86/vec_shuffle-17.ll index 9c33abb4421a..ebc8c5b34a90 100644 --- a/test/CodeGen/X86/vec_shuffle-17.ll +++ b/test/CodeGen/X86/vec_shuffle-17.ll @@ -1,5 +1,8 @@ -; RUN: llc < %s -march=x86-64 | grep {movd.*%rdi, %xmm0} -; RUN: llc < %s -march=x86-64 | not grep xor +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s +; CHECK-NOT: xor +; CHECK: movd {{%rdi|%rcx}}, %xmm0 +; CHECK-NOT: xor ; PR2108 define <2 x i64> @doload64(i64 %x) nounwind { diff --git a/test/CodeGen/X86/vec_uint_to_fp.ll b/test/CodeGen/X86/vec_uint_to_fp.ll new file mode 100644 index 000000000000..39e7d715c5bb --- /dev/null +++ b/test/CodeGen/X86/vec_uint_to_fp.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s -march=x86 -mcpu=sandybridge | FileCheck %s + +; Test that we are not lowering uinttofp to scalars +define <4 x float> @test1(<4 x i32> %A) nounwind { +; CHECK: test1: +; CHECK-NOT: cvtsd2ss +; CHECK: ret + %C = uitofp <4 x i32> %A to <4 x float> + ret <4 x float> %C +} + diff --git a/test/CodeGen/X86/visibility.ll b/test/CodeGen/X86/visibility.ll index a8d287083a80..580c3dc9266d 100644 --- a/test/CodeGen/X86/visibility.ll +++ b/test/CodeGen/X86/visibility.ll @@ -1,11 +1,14 @@ ; RUN: llc -mtriple=x86_64-unknown-linux-gnu %s -o - | FileCheck %s +@zed = external hidden constant i32 + define hidden void @foo() nounwind { entry: - call void @bar() + call void @bar(i32* @zed) ret void } -declare hidden void @bar() +declare hidden void @bar(i32*) +;CHECK: .hidden zed ;CHECK: .hidden bar diff --git a/test/CodeGen/X86/widen_load-0.ll b/test/CodeGen/X86/widen_load-0.ll index f6c4af03209b..82c8252e7bbc 100644 --- a/test/CodeGen/X86/widen_load-0.ll +++ b/test/CodeGen/X86/widen_load-0.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -o - -march=x86-64 | FileCheck %s +; RUN: llc < %s -o - -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -o - -mtriple=x86_64-win32 | FileCheck %s -check-prefix=WIN64 ; PR4891 ; Both loads should happen before either store. @@ -8,6 +9,11 @@ ; CHECK: movl %ecx, (%rdi) ; CHECK: movl %eax, (%rsi) +; WIN64: movl (%rcx), %eax +; WIN64: movl (%rdx), %esi +; WIN64: movl %esi, (%rcx) +; WIN64: movl %eax, (%rdx) + define void @short2_int_swap(<2 x i16>* nocapture %b, i32* nocapture %c) nounwind { entry: %0 = load <2 x i16>* %b, align 2 ; <<2 x i16>> [#uses=1] diff --git a/test/CodeGen/X86/win64_alloca_dynalloca.ll b/test/CodeGen/X86/win64_alloca_dynalloca.ll new file mode 100644 index 000000000000..cbd38da60e96 --- /dev/null +++ b/test/CodeGen/X86/win64_alloca_dynalloca.ll @@ -0,0 +1,74 @@ +; RUN: llc < %s -mtriple=x86_64-mingw32 | FileCheck %s -check-prefix=M64 +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=W64 +; RUN: llc < %s -mtriple=x86_64-win32-macho | FileCheck %s -check-prefix=EFI +; PR8777 +; PR8778 + +define i64 @foo(i64 %n, i64 %x) nounwind { +entry: + + %buf0 = alloca i8, i64 4096, align 1 + +; ___chkstk must adjust %rsp. +; M64: movq %rsp, %rbp +; M64: $4096, %rax +; M64: callq ___chkstk +; M64-NOT: %rsp + +; __chkstk does not adjust %rsp. +; W64: movq %rsp, %rbp +; W64: $4096, %rax +; W64: callq __chkstk +; W64: subq $4096, %rsp + +; Freestanding +; EFI: movq %rsp, %rbp +; EFI: $[[B0OFS:4096|4104]], %rsp +; EFI-NOT: call + + %buf1 = alloca i8, i64 %n, align 1 + +; M64: leaq 15(%rcx), %rax +; M64: andq $-16, %rax +; M64: callq ___chkstk +; M64-NOT: %rsp +; M64: movq %rsp, %rax + +; W64: leaq 15(%rcx), %rax +; W64: andq $-16, %rax +; W64: callq __chkstk +; W64: subq %rax, %rsp +; W64: movq %rsp, %rax + +; EFI: leaq 15(%rcx), [[R1:%r..]] +; EFI: andq $-16, [[R1]] +; EFI: movq %rsp, [[R64:%r..]] +; EFI: subq [[R1]], [[R64]] +; EFI: movq [[R64]], %rsp + + %r = call i64 @bar(i64 %n, i64 %x, i64 %n, i8* %buf0, i8* %buf1) nounwind + +; M64: subq $48, %rsp +; M64: leaq -4096(%rbp), %r9 +; M64: movq %rax, 32(%rsp) +; M64: callq bar + +; W64: subq $48, %rsp +; W64: leaq -4096(%rbp), %r9 +; W64: movq %rax, 32(%rsp) +; W64: callq bar + +; EFI: subq $48, %rsp +; EFI: leaq -[[B0OFS]](%rbp), %r9 +; EFI: movq [[R64]], 32(%rsp) +; EFI: callq _bar + + ret i64 %r + +; M64: movq %rbp, %rsp + +; W64: movq %rbp, %rsp + +} + +declare i64 @bar(i64, i64, i64, i8* nocapture, i8* nocapture) nounwind diff --git a/test/CodeGen/X86/win64_vararg.ll b/test/CodeGen/X86/win64_vararg.ll index a451318f6e8c..efe8bcacbeae 100644 --- a/test/CodeGen/X86/win64_vararg.ll +++ b/test/CodeGen/X86/win64_vararg.ll @@ -18,3 +18,36 @@ entry: } declare void @llvm.va_start(i8*) nounwind + +; CHECK: f5: +; CHECK: pushq +; CHECK: leaq 56(%rsp), +define i8* @f5(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, ...) nounwind { +entry: + %ap = alloca i8*, align 8 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + ret i8* %ap1 +} + +; CHECK: f4: +; CHECK: pushq +; CHECK: leaq 48(%rsp), +define i8* @f4(i64 %a0, i64 %a1, i64 %a2, i64 %a3, ...) nounwind { +entry: + %ap = alloca i8*, align 8 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + ret i8* %ap1 +} + +; CHECK: f3: +; CHECK: pushq +; CHECK: leaq 40(%rsp), +define i8* @f3(i64 %a0, i64 %a1, i64 %a2, ...) nounwind { +entry: + %ap = alloca i8*, align 8 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + ret i8* %ap1 +} diff --git a/test/CodeGen/X86/win_chkstk.ll b/test/CodeGen/X86/win_chkstk.ll index 82ce81d4ae70..e4e4483ff949 100644 --- a/test/CodeGen/X86/win_chkstk.ll +++ b/test/CodeGen/X86/win_chkstk.ll @@ -3,6 +3,7 @@ ; RUN: llc < %s -mtriple=i686-pc-mingw32 | FileCheck %s -check-prefix=MINGW_X32 ; RUN: llc < %s -mtriple=x86_64-pc-mingw32 | FileCheck %s -check-prefix=MINGW_X64 ; RUN: llc < %s -mtriple=i386-pc-linux | FileCheck %s -check-prefix=LINUX +; RUN: llc < %s -mtriple=x86_64-pc-win32-macho | FileCheck %s -check-prefix=LINUX ; Windows and mingw require a prologue helper routine if more than 4096 bytes area ; allocated on the stack. Windows uses __chkstk and mingw uses __alloca. __alloca @@ -16,7 +17,7 @@ entry: ; WIN_X32: calll __chkstk ; WIN_X64: callq __chkstk ; MINGW_X32: calll __alloca -; MINGW_X64: callq __chkstk +; MINGW_X64: callq ___chkstk ; LINUX-NOT: call __chkstk %array4096 = alloca [4096 x i8], align 16 ; <[4096 x i8]*> [#uses=0] ret i32 0 diff --git a/test/CodeGen/X86/x86-64-malloc.ll b/test/CodeGen/X86/x86-64-malloc.ll index b4f1fa666720..4aa0ec3dc9f7 100644 --- a/test/CodeGen/X86/x86-64-malloc.ll +++ b/test/CodeGen/X86/x86-64-malloc.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=x86-64 | grep {shll.*3, %edi} +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s +; CHECK: shll $3, {{%edi|%ecx}} ; PR3829 ; The generated code should multiply by 3 (sizeof i8*) as an i32, ; not as an i64! diff --git a/test/CodeGen/X86/zext-extract_subreg.ll b/test/CodeGen/X86/zext-extract_subreg.ll index e61e8805a2fd..4f1dde3c4f0e 100644 --- a/test/CodeGen/X86/zext-extract_subreg.ll +++ b/test/CodeGen/X86/zext-extract_subreg.ll @@ -13,6 +13,7 @@ if.end: ; preds = %if.end.i ; CHECK: %if.end ; CHECK: movl (%{{.*}}), [[REG:%[a-z]+]] ; CHECK-NOT: movl [[REG]], [[REG]] +; CHECK-NEXT: testl [[REG]], [[REG]] ; CHECK-NEXT: xorb %tmp138 = select i1 undef, i32 0, i32 %tmp7.i %tmp867 = zext i32 %tmp138 to i64 diff --git a/test/CodeGen/X86/zext-sext.ll b/test/CodeGen/X86/zext-sext.ll index bd109b92d9f7..cea9e9c854db 100644 --- a/test/CodeGen/X86/zext-sext.ll +++ b/test/CodeGen/X86/zext-sext.ll @@ -1,3 +1,4 @@ +; XFAIL: * ; RUN: llc < %s -march=x86-64 | FileCheck %s ; <rdar://problem/8006248> diff --git a/test/CodeGen/XCore/events.ll b/test/CodeGen/XCore/events.ll index 4fc2f26d1b6b..30a6ec35513e 100644 --- a/test/CodeGen/XCore/events.ll +++ b/test/CodeGen/XCore/events.ll @@ -2,6 +2,7 @@ declare void @llvm.xcore.setv.p1i8(i8 addrspace(1)* %r, i8* %p) declare i8* @llvm.xcore.waitevent() +declare i8* @llvm.xcore.checkevent(i8*) declare void @llvm.xcore.clre() define i32 @f(i8 addrspace(1)* %r) nounwind { @@ -22,3 +23,22 @@ ret: %retval = phi i32 [1, %L1], [2, %L2] ret i32 %retval } + +define i32 @g(i8 addrspace(1)* %r) nounwind { +; CHECK: g: +entry: +; CHECK: clre + call void @llvm.xcore.clre() + call void @llvm.xcore.setv.p1i8(i8 addrspace(1)* %r, i8* blockaddress(@f, %L1)) + %goto_addr = call i8* @llvm.xcore.checkevent(i8 *blockaddress(@f, %L2)) +; CHECK: setsr 1 +; CHECK: clrsr 1 + indirectbr i8* %goto_addr, [label %L1, label %L2] +L1: + br label %ret +L2: + br label %ret +ret: + %retval = phi i32 [1, %L1], [2, %L2] + ret i32 %retval +} diff --git a/test/CodeGen/XCore/mul64.ll b/test/CodeGen/XCore/mul64.ll index 1dc94712507e..77c6b4268849 100644 --- a/test/CodeGen/XCore/mul64.ll +++ b/test/CodeGen/XCore/mul64.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=xcore | FileCheck %s +; RUN: llc < %s -march=xcore -regalloc=basic | FileCheck %s define i64 @umul_lohi(i32 %a, i32 %b) { entry: %0 = zext i32 %a to i64 @@ -7,8 +8,8 @@ entry: ret i64 %2 } ; CHECK: umul_lohi: -; CHECK: ldc r2, 0 -; CHECK-NEXT: lmul r1, r0, r1, r0, r2, r2 +; CHECK: ldc [[REG:r[0-9]+]], 0 +; CHECK-NEXT: lmul r1, r0, r1, r0, [[REG]], [[REG]] ; CHECK-NEXT: retsp 0 define i64 @smul_lohi(i32 %a, i32 %b) { @@ -19,11 +20,11 @@ entry: ret i64 %2 } ; CHECK: smul_lohi: -; CHECK: ldc r2, 0 -; CHECK-NEXT: mov r3, r2 -; CHECK-NEXT: maccs r2, r3, r1, r0 -; CHECK-NEXT: mov r0, r3 -; CHECK-NEXT: mov r1, r2 +; CHECK: ldc +; CHECK-NEXT: mov +; CHECK-NEXT: maccs +; CHECK-NEXT: mov r0, +; CHECK-NEXT: mov r1, ; CHECK-NEXT: retsp 0 define i64 @mul64(i64 %a, i64 %b) { @@ -32,11 +33,11 @@ entry: ret i64 %0 } ; CHECK: mul64: -; CHECK: ldc r11, 0 -; CHECK-NEXT: lmul r11, r4, r0, r2, r11, r11 -; CHECK-NEXT: mul r0, r0, r3 -; CHECK-NEXT: lmul r0, r1, r1, r2, r11, r0 -; CHECK-NEXT: mov r0, r4 +; CHECK: ldc +; CHECK-NEXT: lmul +; CHECK-NEXT: mul +; CHECK-NEXT: lmul +; CHECK-NEXT: mov r0, define i64 @mul64_2(i64 %a, i32 %b) { entry: @@ -45,8 +46,8 @@ entry: ret i64 %1 } ; CHECK: mul64_2: -; CHECK: ldc r3, 0 -; CHECK-NEXT: lmul r3, r0, r0, r2, r3, r3 -; CHECK-NEXT: mul r1, r1, r2 -; CHECK-NEXT: add r1, r3, r1 +; CHECK: ldc +; CHECK-NEXT: lmul +; CHECK-NEXT: mul +; CHECK-NEXT: add r1, ; CHECK-NEXT: retsp 0 diff --git a/test/CodeGen/XCore/ps-intrinsics.ll b/test/CodeGen/XCore/ps-intrinsics.ll new file mode 100644 index 000000000000..92b26c75e0e4 --- /dev/null +++ b/test/CodeGen/XCore/ps-intrinsics.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -march=xcore | FileCheck %s +declare i32 @llvm.xcore.getps(i32) +declare void @llvm.xcore.setps(i32, i32) + +define i32 @getps(i32 %reg) nounwind { +; CHECK: getps: +; CHECK: get r0, ps[r0] + %result = call i32 @llvm.xcore.getps(i32 %reg) + ret i32 %result +} + + +define void @setps(i32 %reg, i32 %value) nounwind { +; CHECK: setps: +; CHECK: set ps[r0], r1 + call void @llvm.xcore.setps(i32 %reg, i32 %value) + ret void +} diff --git a/test/CodeGen/XCore/resources.ll b/test/CodeGen/XCore/resources.ll index 3389912b8c0b..bd0492c88ee8 100644 --- a/test/CodeGen/XCore/resources.ll +++ b/test/CodeGen/XCore/resources.ll @@ -19,6 +19,9 @@ declare void @llvm.xcore.syncr.p1i8(i8 addrspace(1)* %r) declare void @llvm.xcore.settw.p1i8(i8 addrspace(1)* %r, i32 %value) declare void @llvm.xcore.setv.p1i8(i8 addrspace(1)* %r, i8* %p) declare void @llvm.xcore.eeu.p1i8(i8 addrspace(1)* %r) +declare void @llvm.xcore.setclk.p1i8.p1i8(i8 addrspace(1)* %a, i8 addrspace(1)* %b) +declare void @llvm.xcore.setrdy.p1i8.p1i8(i8 addrspace(1)* %a, i8 addrspace(1)* %b) +declare void @llvm.xcore.setpsc.p1i8(i8 addrspace(1)* %r, i32 %value) define i8 addrspace(1)* @getr() { ; CHECK: getr: @@ -174,3 +177,24 @@ define void @eeu(i8 addrspace(1)* %r) { call void @llvm.xcore.eeu.p1i8(i8 addrspace(1)* %r) ret void } + +define void @setclk(i8 addrspace(1)* %a, i8 addrspace(1)* %b) { +; CHECK: setclk +; CHECK: setclk res[r0], r1 + call void @llvm.xcore.setclk.p1i8.p1i8(i8 addrspace(1)* %a, i8 addrspace(1)* %b) + ret void +} + +define void @setrdy(i8 addrspace(1)* %a, i8 addrspace(1)* %b) { +; CHECK: setrdy +; CHECK: setrdy res[r0], r1 + call void @llvm.xcore.setrdy.p1i8.p1i8(i8 addrspace(1)* %a, i8 addrspace(1)* %b) + ret void +} + +define void @setpsc(i8 addrspace(1)* %r, i32 %value) { +; CHECK: setpsc +; CHECK: setpsc res[r0], r1 + call void @llvm.xcore.setpsc.p1i8(i8 addrspace(1)* %r, i32 %value) + ret void +} diff --git a/test/CodeGen/XCore/scavenging.ll b/test/CodeGen/XCore/scavenging.ll new file mode 100644 index 000000000000..3181e96116b6 --- /dev/null +++ b/test/CodeGen/XCore/scavenging.ll @@ -0,0 +1,52 @@ +; RUN: llc < %s -march=xcore +@size = global i32 0 ; <i32*> [#uses=1] +@g0 = external global i32 ; <i32*> [#uses=2] +@g1 = external global i32 ; <i32*> [#uses=2] +@g2 = external global i32 ; <i32*> [#uses=2] +@g3 = external global i32 ; <i32*> [#uses=2] +@g4 = external global i32 ; <i32*> [#uses=2] +@g5 = external global i32 ; <i32*> [#uses=2] +@g6 = external global i32 ; <i32*> [#uses=2] +@g7 = external global i32 ; <i32*> [#uses=2] +@g8 = external global i32 ; <i32*> [#uses=2] +@g9 = external global i32 ; <i32*> [#uses=2] +@g10 = external global i32 ; <i32*> [#uses=2] +@g11 = external global i32 ; <i32*> [#uses=2] + +define void @f() nounwind { +entry: + %x = alloca [100 x i32], align 4 ; <[100 x i32]*> [#uses=2] + %0 = load i32* @size, align 4 ; <i32> [#uses=1] + %1 = alloca i32, i32 %0, align 4 ; <i32*> [#uses=1] + %2 = volatile load i32* @g0, align 4 ; <i32> [#uses=1] + %3 = volatile load i32* @g1, align 4 ; <i32> [#uses=1] + %4 = volatile load i32* @g2, align 4 ; <i32> [#uses=1] + %5 = volatile load i32* @g3, align 4 ; <i32> [#uses=1] + %6 = volatile load i32* @g4, align 4 ; <i32> [#uses=1] + %7 = volatile load i32* @g5, align 4 ; <i32> [#uses=1] + %8 = volatile load i32* @g6, align 4 ; <i32> [#uses=1] + %9 = volatile load i32* @g7, align 4 ; <i32> [#uses=1] + %10 = volatile load i32* @g8, align 4 ; <i32> [#uses=1] + %11 = volatile load i32* @g9, align 4 ; <i32> [#uses=1] + %12 = volatile load i32* @g10, align 4 ; <i32> [#uses=1] + %13 = volatile load i32* @g11, align 4 ; <i32> [#uses=2] + %14 = getelementptr [100 x i32]* %x, i32 0, i32 50 ; <i32*> [#uses=1] + store i32 %13, i32* %14, align 4 + volatile store i32 %13, i32* @g11, align 4 + volatile store i32 %12, i32* @g10, align 4 + volatile store i32 %11, i32* @g9, align 4 + volatile store i32 %10, i32* @g8, align 4 + volatile store i32 %9, i32* @g7, align 4 + volatile store i32 %8, i32* @g6, align 4 + volatile store i32 %7, i32* @g5, align 4 + volatile store i32 %6, i32* @g4, align 4 + volatile store i32 %5, i32* @g3, align 4 + volatile store i32 %4, i32* @g2, align 4 + volatile store i32 %3, i32* @g1, align 4 + volatile store i32 %2, i32* @g0, align 4 + %x1 = getelementptr [100 x i32]* %x, i32 0, i32 0 ; <i32*> [#uses=1] + call void @g(i32* %x1, i32* %1) nounwind + ret void +} + +declare void @g(i32*, i32*) diff --git a/test/CodeGen/XCore/sr-intrinsics.ll b/test/CodeGen/XCore/sr-intrinsics.ll new file mode 100644 index 000000000000..e12ed0380309 --- /dev/null +++ b/test/CodeGen/XCore/sr-intrinsics.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -march=xcore | FileCheck %s +declare void @llvm.xcore.setsr(i32) +declare void @llvm.xcore.clrsr(i32) + +define void @setsr() nounwind { +; CHECK: setsr: +; CHECK: setsr 128 + call void @llvm.xcore.setsr(i32 128) + ret void +} + + +define void @clrsr() nounwind { +; CHECK: clrsr: +; CHECK: clrsr 128 + call void @llvm.xcore.clrsr(i32 128) + ret void +} diff --git a/test/CodeGen/XCore/threads.ll b/test/CodeGen/XCore/threads.ll new file mode 100644 index 000000000000..a0558e365cbb --- /dev/null +++ b/test/CodeGen/XCore/threads.ll @@ -0,0 +1,67 @@ +; RUN: llc -march=xcore < %s | FileCheck %s + +declare i8 addrspace(1)* @llvm.xcore.getst.p1i8.p1i8(i8 addrspace(1)* %r) +declare void @llvm.xcore.msync.p1i8(i8 addrspace(1)* %r) +declare void @llvm.xcore.ssync() +declare void @llvm.xcore.mjoin.p1i8(i8 addrspace(1)* %r) +declare void @llvm.xcore.initsp.p1i8(i8 addrspace(1)* %r, i8* %value) +declare void @llvm.xcore.initpc.p1i8(i8 addrspace(1)* %r, i8* %value) +declare void @llvm.xcore.initlr.p1i8(i8 addrspace(1)* %r, i8* %value) +declare void @llvm.xcore.initcp.p1i8(i8 addrspace(1)* %r, i8* %value) +declare void @llvm.xcore.initdp.p1i8(i8 addrspace(1)* %r, i8* %value) + +define i8 addrspace(1)* @getst(i8 addrspace(1)* %r) { +; CHECK: getst: +; CHECK: getst r0, res[r0] + %result = call i8 addrspace(1)* @llvm.xcore.getst.p1i8.p1i8(i8 addrspace(1)* %r) + ret i8 addrspace(1)* %result +} + +define void @ssync() { +; CHECK: ssync: +; CHECK: ssync + call void @llvm.xcore.ssync() + ret void +} + +define void @mjoin(i8 addrspace(1)* %r) { +; CHECK: mjoin: +; CHECK: mjoin res[r0] + call void @llvm.xcore.mjoin.p1i8(i8 addrspace(1)* %r) + ret void +} + +define void @initsp(i8 addrspace(1)* %t, i8* %src) { +; CHECK: initsp: +; CHECK: init t[r0]:sp, r1 + call void @llvm.xcore.initsp.p1i8(i8 addrspace(1)* %t, i8* %src) + ret void +} + +define void @initpc(i8 addrspace(1)* %t, i8* %src) { +; CHECK: initpc: +; CHECK: init t[r0]:pc, r1 + call void @llvm.xcore.initpc.p1i8(i8 addrspace(1)* %t, i8* %src) + ret void +} + +define void @initlr(i8 addrspace(1)* %t, i8* %src) { +; CHECK: initlr: +; CHECK: init t[r0]:lr, r1 + call void @llvm.xcore.initlr.p1i8(i8 addrspace(1)* %t, i8* %src) + ret void +} + +define void @initcp(i8 addrspace(1)* %t, i8* %src) { +; CHECK: initcp: +; CHECK: init t[r0]:cp, r1 + call void @llvm.xcore.initcp.p1i8(i8 addrspace(1)* %t, i8* %src) + ret void +} + +define void @initdp(i8 addrspace(1)* %t, i8* %src) { +; CHECK: initdp: +; CHECK: init t[r0]:dp, r1 + call void @llvm.xcore.initdp.p1i8(i8 addrspace(1)* %t, i8* %src) + ret void +} diff --git a/test/CodeGen/XCore/trampoline.ll b/test/CodeGen/XCore/trampoline.ll index 18cc45edbf9f..4e1aba025b2f 100644 --- a/test/CodeGen/XCore/trampoline.ll +++ b/test/CodeGen/XCore/trampoline.ll @@ -5,8 +5,8 @@ define void @f() nounwind { entry: ; CHECK: f: -; CHECK ldap r11, g.1101 -; CHECK stw r11, sp[7] +; CHECK: ldap r11, g.1101 +; CHECK: stw r11, sp[7] %TRAMP.23 = alloca [20 x i8], align 2 %FRAME.0 = alloca %struct.FRAME.f, align 4 %TRAMP.23.sub = getelementptr inbounds [20 x i8]* %TRAMP.23, i32 0, i32 0 diff --git a/test/DebugInfo/2010-04-13-PubType.ll b/test/DebugInfo/2010-04-13-PubType.ll index 371169fe1839..db7bb0ad6030 100644 --- a/test/DebugInfo/2010-04-13-PubType.ll +++ b/test/DebugInfo/2010-04-13-PubType.ll @@ -1,7 +1,7 @@ ; RUN: llc -O0 -asm-verbose < %s > %t ; RUN: grep "External Name" %t | grep -v X ; RUN: grep "External Name" %t | grep Y | count 1 -; Test to check type with no defintion is listed in pubtypes section. +; Test to check type with no definition is listed in pubtypes section. %struct.X = type opaque %struct.Y = type { i32 } diff --git a/test/DebugInfo/array.ll b/test/DebugInfo/array.ll new file mode 100644 index 000000000000..9f592a12a923 --- /dev/null +++ b/test/DebugInfo/array.ll @@ -0,0 +1,34 @@ +; RUN: llc -O0 < %s | FileCheck %s +; Do not emit AT_upper_bound for an unbounded array. +; radar 9241695 +define i32 @main() nounwind ssp { +entry: + %retval = alloca i32, align 4 + %a = alloca [0 x i32], align 4 + store i32 0, i32* %retval + call void @llvm.dbg.declare(metadata !{[0 x i32]* %a}, metadata !6), !dbg !11 + ret i32 0, !dbg !12 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +!llvm.dbg.sp = !{!0} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @main, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"array.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"array.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 129138)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 590080, metadata !7, metadata !"a", metadata !1, i32 4, metadata !8, i32 0} ; [ DW_TAG_auto_variable ] +!7 = metadata !{i32 589835, metadata !0, i32 3, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!8 = metadata !{i32 589825, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 32, i32 0, i32 0, metadata !5, metadata !9, i32 0, i32 0} ; [ DW_TAG_array_type ] +!9 = metadata !{metadata !10} +;CHECK: DW_TAG_subrange_type +;CHECK-NEXT: DW_AT_type +;CHECK-NOT: DW_AT_lower_bound +;CHECK-NOT: DW_AT_upper_bound +;CHECK-NEXT: End Of Children Mark +!10 = metadata !{i32 589857, i64 1, i64 0} ; [ DW_TAG_subrange_type ] +!11 = metadata !{i32 4, i32 7, metadata !7, null} +!12 = metadata !{i32 5, i32 3, metadata !7, null} diff --git a/test/FrontendAda/real_cst.adb b/test/FrontendAda/real_cst.adb index c9708301d62f..75143710252f 100644 --- a/test/FrontendAda/real_cst.adb +++ b/test/FrontendAda/real_cst.adb @@ -1,4 +1,4 @@ --- RUN: %llvmgcc -S -O2 -gnatn %s +-- RUN: %llvmgcc -S -O2 -gnatn %s -I%p/Support package body Real_Cst is Cst : constant Float := 0.0; procedure Write (Stream : access Ada.Streams.Root_Stream_Type'Class) is diff --git a/test/FrontendC++/2009-07-15-LineNumbers.cpp b/test/FrontendC++/2009-07-15-LineNumbers.cpp deleted file mode 100644 index e1cc81f40f79..000000000000 --- a/test/FrontendC++/2009-07-15-LineNumbers.cpp +++ /dev/null @@ -1,27 +0,0 @@ -// This is a regression test on debug info to make sure that we can -// print line numbers in asm. -// RUN: %llvmgcc -S -O0 -g %s -o - | \ -// RUN: llc --disable-fp-elim -O0 -relocation-model=pic | grep {2009-07-15-LineNumbers.cpp:25$} - -#include <stdlib.h> - -class DeepStack { - int seedVal; -public: - DeepStack(int seed) : seedVal(seed) {} - - int shallowest( int x ) { return shallower(x + 1); } - int shallower ( int x ) { return shallow(x + 2); } - int shallow ( int x ) { return deep(x + 3); } - int deep ( int x ) { return deeper(x + 4); } - int deeper ( int x ) { return deepest(x + 6); } - int deepest ( int x ) { return x + 7; } - - int runit() { return shallowest(seedVal); } -}; - -int main ( int argc, char** argv) { - - DeepStack DS9( (argc > 1 ? atoi(argv[1]) : 0) ); - return DS9.runit(); -} diff --git a/test/FrontendC/2006-05-01-AppleAlignmentPragma.c b/test/FrontendC/2006-05-01-AppleAlignmentPragma.c index c9050aa9e4e4..233968b51aa3 100644 --- a/test/FrontendC/2006-05-01-AppleAlignmentPragma.c +++ b/test/FrontendC/2006-05-01-AppleAlignmentPragma.c @@ -1,7 +1,7 @@ // RUN: %llvmgcc %s -S -o - #ifdef __APPLE__ -/* test that X is layed out correctly when this pragma is used. */ +/* test that X is laid out correctly when this pragma is used. */ #pragma options align=mac68k #endif diff --git a/test/FrontendC/2010-07-27-MinNoFoldConst.c b/test/FrontendC/2010-07-27-MinNoFoldConst.c index 7cd8b4c43764..ea711e5dddc8 100644 --- a/test/FrontendC/2010-07-27-MinNoFoldConst.c +++ b/test/FrontendC/2010-07-27-MinNoFoldConst.c @@ -10,7 +10,7 @@ static void bad(unsigned int v1, unsigned int v2) { // MIN(1631381461u * v2 - 4047041419, 1631381461u * v1 - 4047041419) // // 1631381461u * 1273463329u = 2077504466193943669, but 32-bit overflow clips -// this to 4047041419. This breaks the comparision implicit in the MIN(). +// this to 4047041419. This breaks the comparison implicit in the MIN(). // Two multiply operations suggests the bad optimization is happening; // one multiplication, after the MIN(), is correct. // CHECK: mul diff --git a/test/FrontendC/2011-03-02-UnionInitializer.c b/test/FrontendC/2011-03-02-UnionInitializer.c new file mode 100644 index 000000000000..a5ea75e08c01 --- /dev/null +++ b/test/FrontendC/2011-03-02-UnionInitializer.c @@ -0,0 +1,2 @@ +// RUN: %llvmgcc -S %s +union { int :3; double f; } u17_017 = {17.17}; diff --git a/test/FrontendC/2011-03-08-ZeroFieldUnionInitializer.c b/test/FrontendC/2011-03-08-ZeroFieldUnionInitializer.c new file mode 100644 index 000000000000..1fd8a8782464 --- /dev/null +++ b/test/FrontendC/2011-03-08-ZeroFieldUnionInitializer.c @@ -0,0 +1,7 @@ +// RUN: %llvmgcc -S %s +typedef struct { + union { + struct { } __attribute((packed)); + }; +} fenv_t; +const fenv_t _FE_DFL_ENV = {{{ 0, 0, 0, 0 }}}; diff --git a/test/FrontendC/2011-03-31-ArrayRefFolding.c b/test/FrontendC/2011-03-31-ArrayRefFolding.c new file mode 100644 index 000000000000..403927931c7f --- /dev/null +++ b/test/FrontendC/2011-03-31-ArrayRefFolding.c @@ -0,0 +1,15 @@ +// RUN: %llvmgcc -S -o - -m32 -Os %s | FileCheck %s +// PR9571 + +struct t { + int x; +}; + +extern struct t *cfun; + +int f(void) { + if (!(cfun + 0)) +// CHECK: icmp eq %struct.t* %0, null + return 0; + return cfun->x; +} diff --git a/test/FrontendC/cstring-align.c b/test/FrontendC/cstring-align.c deleted file mode 100644 index 544c9f3d3fbb..000000000000 --- a/test/FrontendC/cstring-align.c +++ /dev/null @@ -1,11 +0,0 @@ -// RUN: %llvmgcc %s -S -Os -o - | llc -march=x86 -mtriple=i386-apple-darwin10 | FileCheck %s - -extern void func(const char *, const char *); - -void long_function_name() { - func("%s: the function name", __func__); -} - -// CHECK: .align 4 -// CHECK: ___func__. -// CHECK: .asciz "long_function_name" diff --git a/test/FrontendC/mmx-inline-asm.c b/test/FrontendC/mmx-inline-asm.c new file mode 100644 index 000000000000..b66137c3c221 --- /dev/null +++ b/test/FrontendC/mmx-inline-asm.c @@ -0,0 +1,24 @@ +// RUN: %llvmgcc -mmmx -S -o - %s | FileCheck %s +// XFAIL: * +// XTARGET: x86,i386,i686 +// <rdar://problem/9091220> +#include <mmintrin.h> +#include <stdint.h> + +// CHECK: type { x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx } + +void foo(__m64 vfill) { + __m64 v1, v2, v3, v4, v5, v6, v7; + + __asm__ __volatile__ ( + "\tmovq %7, %0\n" + "\tmovq %7, %1\n" + "\tmovq %7, %2\n" + "\tmovq %7, %3\n" + "\tmovq %7, %4\n" + "\tmovq %7, %5\n" + "\tmovq %7, %6" + : "=&y" (v1), "=&y" (v2), "=&y" (v3), + "=&y" (v4), "=&y" (v5), "=&y" (v6), "=y" (v7) + : "y" (vfill)); +} diff --git a/test/FrontendC/vla-3.c b/test/FrontendC/vla-3.c new file mode 100644 index 000000000000..eca9675a419f --- /dev/null +++ b/test/FrontendC/vla-3.c @@ -0,0 +1,11 @@ +// RUN: %llvmgcc -std=gnu99 %s -S -o - | grep ".*alloca.*align 16" + +void adr(char *); + +void vlaalign(int size) +{ + char __attribute__((aligned(16))) tmp[size+32]; + char tmp2[size+16]; + + adr(tmp); +} diff --git a/test/FrontendObjC/2011-03-02-ConstCFStringLiteralAlign.m b/test/FrontendObjC/2011-03-02-ConstCFStringLiteralAlign.m new file mode 100644 index 000000000000..a5bd2b73bf09 --- /dev/null +++ b/test/FrontendObjC/2011-03-02-ConstCFStringLiteralAlign.m @@ -0,0 +1,11 @@ +// RUN: %llvmgcc -S -w -m64 -mmacosx-version-min=10.5 %s -o - | \ +// RUN: llc --disable-fp-elim -o - | FileCheck %s +// XFAIL: * +// XTARGET: darwin + +@interface Foo +@end +Foo *FooName = @"FooBar"; + +// CHECK: .section __TEXT,__cstring,cstring_literals +// CHECK-NEXT: L_.str: diff --git a/test/FrontendObjC/2011-03-08-IVarLookup.m b/test/FrontendObjC/2011-03-08-IVarLookup.m new file mode 100644 index 000000000000..939f2a7b8f36 --- /dev/null +++ b/test/FrontendObjC/2011-03-08-IVarLookup.m @@ -0,0 +1,32 @@ +// RUN: %llvmgcc -x objective-c -S -fobjc-abi-version=2 %s -o /dev/null +// XFAIL: * +// XTARGET: darwin + +typedef unsigned int UInt_t; + +@interface A +{ +@protected + UInt_t _f1; +} +@end + +@interface B : A { } +@end + +@interface A () +@property (assign) UInt_t f1; +@end + +@interface B () +@property (assign) int x; +@end + +@implementation B +@synthesize x; +- (id) init +{ + _f1 = 0; + return self; +} +@end diff --git a/test/MC/ARM/arm_addrmode2.s b/test/MC/ARM/arm_addrmode2.s new file mode 100644 index 000000000000..ca99233b9b5c --- /dev/null +++ b/test/MC/ARM/arm_addrmode2.s @@ -0,0 +1,34 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s + +@ Post-indexed +@ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6] +@ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6] +@ CHECK: ldrt r1, [r0], #4 @ encoding: [0x04,0x10,0xb0,0xe4] +@ CHECK: ldrbt r1, [r0], r2 @ encoding: [0x02,0x10,0xf0,0xe6] +@ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6] +@ CHECK: ldrbt r1, [r0], #4 @ encoding: [0x04,0x10,0xf0,0xe4] +@ CHECK: strt r1, [r0], r2 @ encoding: [0x02,0x10,0xa0,0xe6] +@ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6] +@ CHECK: strt r1, [r0], #4 @ encoding: [0x04,0x10,0xa0,0xe4] +@ CHECK: strbt r1, [r0], r2 @ encoding: [0x02,0x10,0xe0,0xe6] +@ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6] +@ CHECK: strbt r1, [r0], #4 @ encoding: [0x04,0x10,0xe0,0xe4] + ldrt r1, [r0], r2 + ldrt r1, [r0], r2, lsr #3 + ldrt r1, [r0], #4 + ldrbt r1, [r0], r2 + ldrbt r1, [r0], r2, lsr #3 + ldrbt r1, [r0], #4 + strt r1, [r0], r2 + strt r1, [r0], r2, lsr #3 + strt r1, [r0], #4 + strbt r1, [r0], r2 + strbt r1, [r0], r2, lsr #3 + strbt r1, [r0], #4 + +@ Pre-indexed +@ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7] +@ CHECK: ldrb r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xf0,0xe7] + ldr r1, [r0, r2, lsr #3]! + ldrb r1, [r0, r2, lsr #3]! + diff --git a/test/MC/ARM/arm_addrmode3.s b/test/MC/ARM/arm_addrmode3.s new file mode 100644 index 000000000000..0b9639e32307 --- /dev/null +++ b/test/MC/ARM/arm_addrmode3.s @@ -0,0 +1,18 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s + +@ CHECK: ldrsbt r1, [r0], +r2 @ encoding: [0xd2,0x10,0xb0,0xe0] +@ CHECK: ldrsbt r1, [r0], #4 @ encoding: [0xd4,0x10,0xf0,0xe0] +@ CHECK: ldrsht r1, [r0], +r2 @ encoding: [0xf2,0x10,0xb0,0xe0] +@ CHECK: ldrsht r1, [r0], #4 @ encoding: [0xf4,0x10,0xf0,0xe0] +@ CHECK: ldrht r1, [r0], +r2 @ encoding: [0xb2,0x10,0xb0,0xe0] +@ CHECK: ldrht r1, [r0], #4 @ encoding: [0xb4,0x10,0xf0,0xe0] +@ CHECK: strht r1, [r0], +r2 @ encoding: [0xb2,0x10,0xa0,0xe0] +@ CHECK: strht r1, [r0], #4 @ encoding: [0xb4,0x10,0xe0,0xe0] + ldrsbt r1, [r0], r2 + ldrsbt r1, [r0], #4 + ldrsht r1, [r0], r2 + ldrsht r1, [r0], #4 + ldrht r1, [r0], r2 + ldrht r1, [r0], #4 + strht r1, [r0], r2 + strht r1, [r0], #4 diff --git a/test/MC/ARM/arm_instructions.s b/test/MC/ARM/arm_instructions.s index fbec7891c801..50a2b704379b 100644 --- a/test/MC/ARM/arm_instructions.s +++ b/test/MC/ARM/arm_instructions.s @@ -282,3 +282,30 @@ @ CHECK: msr cpsr_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1] msr cpsr_fsxc, r0 +@ CHECK: add r1, r2, r3, lsl r4 @ encoding: [0x13,0x14,0x82,0xe0] + add r1, r2, r3, lsl r4 + +@ CHECK: strexb r0, r1, [r2] @ encoding: [0x91,0x0f,0xc2,0xe1] + strexb r0, r1, [r2] + +@ CHECK: strexh r0, r1, [r2] @ encoding: [0x91,0x0f,0xe2,0xe1] + strexh r0, r1, [r2] + +@ CHECK: strex r0, r1, [r2] @ encoding: [0x91,0x0f,0x82,0xe1] + strex r0, r1, [r2] + +@ CHECK: strexd r0, r2, r3, [r1] @ encoding: [0x92,0x0f,0xa1,0xe1] + strexd r0, r2, r3, [r1] + +@ CHECK: ldrexb r0, [r0] @ encoding: [0x9f,0x0f,0xd0,0xe1] + ldrexb r0, [r0] + +@ CHECK: ldrexh r0, [r0] @ encoding: [0x9f,0x0f,0xf0,0xe1] + ldrexh r0, [r0] + +@ CHECK: ldrex r0, [r0] @ encoding: [0x9f,0x0f,0x90,0xe1] + ldrex r0, [r0] + +@ CHECK: ldrexd r0, r1, [r0] @ encoding: [0x9f,0x0f,0xb0,0xe1] + ldrexd r0, r1, [r0] + diff --git a/test/MC/ARM/elf-reloc-01.ll b/test/MC/ARM/elf-reloc-01.ll index 6b83c95032cd..eb6e2436af33 100644 --- a/test/MC/ARM/elf-reloc-01.ll +++ b/test/MC/ARM/elf-reloc-01.ll @@ -60,12 +60,11 @@ bb3: ; preds = %bb, %entry declare void @exit(i32) noreturn nounwind - -;; OBJ: Symbol 0x00000002 -;; OBJ-NEXT: '_MergedGlobals' -;; OBJ-NEXT: 'st_value', 0x00000010 - ;; OBJ: Relocation 0x00000001 ;; OBJ-NEXT: 'r_offset', ;; OBJ-NEXT: 'r_sym', 0x00000002 ;; OBJ-NEXT: 'r_type', 0x0000002b + +;; OBJ: Symbol 0x00000002 +;; OBJ-NEXT: '_MergedGlobals' +;; OBJ-NEXT: 'st_value', 0x00000010 diff --git a/test/MC/ARM/elf-reloc-02.ll b/test/MC/ARM/elf-reloc-02.ll index 132a47758dad..091e89f57643 100644 --- a/test/MC/ARM/elf-reloc-02.ll +++ b/test/MC/ARM/elf-reloc-02.ll @@ -41,11 +41,10 @@ declare i32 @write(...) declare void @exit(i32) noreturn nounwind - -;; OBJ: Symbol 0x00000002 -;; OBJ-NEXT: '.L.str' - ;; OBJ: Relocation 0x00000000 ;; OBJ-NEXT: 'r_offset', ;; OBJ-NEXT: 'r_sym', 0x00000002 ;; OBJ-NEXT: 'r_type', 0x0000002b + +;; OBJ: Symbol 0x00000002 +;; OBJ-NEXT: '.L.str' diff --git a/test/MC/ARM/elf-reloc-03.ll b/test/MC/ARM/elf-reloc-03.ll index e052f39a615a..91dba554ab63 100644 --- a/test/MC/ARM/elf-reloc-03.ll +++ b/test/MC/ARM/elf-reloc-03.ll @@ -88,11 +88,10 @@ entry: declare void @exit(i32) noreturn nounwind - -;; OBJ: Symbol 0x0000000c -;; OBJ-NEXT: 'vtable' - ;; OBJ: Relocation 0x00000001 ;; OBJ-NEXT: 'r_offset', ;; OBJ-NEXT: 'r_sym', 0x0000000c ;; OBJ-NEXT: 'r_type', 0x0000002b + +;; OBJ: Symbol 0x0000000c +;; OBJ-NEXT: 'vtable' diff --git a/test/MC/ARM/neon-shift-encoding.s b/test/MC/ARM/neon-shift-encoding.s index 4b4fa0876ccd..a7a1b8386044 100644 --- a/test/MC/ARM/neon-shift-encoding.s +++ b/test/MC/ARM/neon-shift-encoding.s @@ -1,160 +1,237 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s -@ CHECK: vshl.u8 d16, d17, d16 @ encoding: [0xa1,0x04,0x40,0xf3] +_foo: +@ CHECK: vshl.u8 d16, d17, d16 @ encoding: [0xa1,0x04,0x40,0xf3] vshl.u8 d16, d17, d16 -@ CHECK: vshl.u16 d16, d17, d16 @ encoding: [0xa1,0x04,0x50,0xf3] +@ CHECK: vshl.u16 d16, d17, d16 @ encoding: [0xa1,0x04,0x50,0xf3] vshl.u16 d16, d17, d16 -@ CHECK: vshl.u32 d16, d17, d16 @ encoding: [0xa1,0x04,0x60,0xf3] +@ CHECK: vshl.u32 d16, d17, d16 @ encoding: [0xa1,0x04,0x60,0xf3] vshl.u32 d16, d17, d16 -@ CHECK: vshl.u64 d16, d17, d16 @ encoding: [0xa1,0x04,0x70,0xf3] +@ CHECK: vshl.u64 d16, d17, d16 @ encoding: [0xa1,0x04,0x70,0xf3] vshl.u64 d16, d17, d16 -@ CHECK: vshl.i8 d16, d16, #7 @ encoding: [0x30,0x05,0xcf,0xf2] +@ CHECK: vshl.i8 d16, d16, #7 @ encoding: [0x30,0x05,0xcf,0xf2] vshl.i8 d16, d16, #7 -@ CHECK: vshl.i16 d16, d16, #15 @ encoding: [0x30,0x05,0xdf,0xf2] +@ CHECK: vshl.i16 d16, d16, #15 @ encoding: [0x30,0x05,0xdf,0xf2] vshl.i16 d16, d16, #15 -@ CHECK: vshl.i32 d16, d16, #31 @ encoding: [0x30,0x05,0xff,0xf2] +@ CHECK: vshl.i32 d16, d16, #31 @ encoding: [0x30,0x05,0xff,0xf2] vshl.i32 d16, d16, #31 -@ CHECK: vshl.i64 d16, d16, #63 @ encoding: [0xb0,0x05,0xff,0xf2] +@ CHECK: vshl.i64 d16, d16, #63 @ encoding: [0xb0,0x05,0xff,0xf2] vshl.i64 d16, d16, #63 -@ CHECK: vshl.u8 q8, q9, q8 @ encoding: [0xe2,0x04,0x40,0xf3] +@ CHECK: vshl.u8 q8, q9, q8 @ encoding: [0xe2,0x04,0x40,0xf3] vshl.u8 q8, q9, q8 -@ CHECK: vshl.u16 q8, q9, q8 @ encoding: [0xe2,0x04,0x50,0xf3] +@ CHECK: vshl.u16 q8, q9, q8 @ encoding: [0xe2,0x04,0x50,0xf3] vshl.u16 q8, q9, q8 -@ CHECK: vshl.u32 q8, q9, q8 @ encoding: [0xe2,0x04,0x60,0xf3] +@ CHECK: vshl.u32 q8, q9, q8 @ encoding: [0xe2,0x04,0x60,0xf3] vshl.u32 q8, q9, q8 -@ CHECK: vshl.u64 q8, q9, q8 @ encoding: [0xe2,0x04,0x70,0xf3] +@ CHECK: vshl.u64 q8, q9, q8 @ encoding: [0xe2,0x04,0x70,0xf3] vshl.u64 q8, q9, q8 -@ CHECK: vshl.i8 q8, q8, #7 @ encoding: [0x70,0x05,0xcf,0xf2] +@ CHECK: vshl.i8 q8, q8, #7 @ encoding: [0x70,0x05,0xcf,0xf2] vshl.i8 q8, q8, #7 -@ CHECK: vshl.i16 q8, q8, #15 @ encoding: [0x70,0x05,0xdf,0xf2] +@ CHECK: vshl.i16 q8, q8, #15 @ encoding: [0x70,0x05,0xdf,0xf2] vshl.i16 q8, q8, #15 -@ CHECK: vshl.i32 q8, q8, #31 @ encoding: [0x70,0x05,0xff,0xf2] +@ CHECK: vshl.i32 q8, q8, #31 @ encoding: [0x70,0x05,0xff,0xf2] vshl.i32 q8, q8, #31 -@ CHECK: vshl.i64 q8, q8, #63 @ encoding: [0xf0,0x05,0xff,0xf2] +@ CHECK: vshl.i64 q8, q8, #63 @ encoding: [0xf0,0x05,0xff,0xf2] vshl.i64 q8, q8, #63 -@ CHECK: vshr.u8 d16, d16, #8 @ encoding: [0x30,0x00,0xc8,0xf3] - vshr.u8 d16, d16, #8 -@ CHECK: vshr.u16 d16, d16, #16 @ encoding: [0x30,0x00,0xd0,0xf3] - vshr.u16 d16, d16, #16 -@ CHECK: vshr.u32 d16, d16, #32 @ encoding: [0x30,0x00,0xe0,0xf3] - vshr.u32 d16, d16, #32 -@ CHECK: vshr.u64 d16, d16, #64 @ encoding: [0xb0,0x00,0xc0,0xf3] - vshr.u64 d16, d16, #64 -@ CHECK: vshr.u8 q8, q8, #8 @ encoding: [0x70,0x00,0xc8,0xf3] - vshr.u8 q8, q8, #8 -@ CHECK: vshr.u16 q8, q8, #16 @ encoding: [0x70,0x00,0xd0,0xf3] - vshr.u16 q8, q8, #16 -@ CHECK: vshr.u32 q8, q8, #32 @ encoding: [0x70,0x00,0xe0,0xf3] - vshr.u32 q8, q8, #32 -@ CHECK: vshr.u64 q8, q8, #64 @ encoding: [0xf0,0x00,0xc0,0xf3] - vshr.u64 q8, q8, #64 -@ CHECK: vshr.s8 d16, d16, #8 @ encoding: [0x30,0x00,0xc8,0xf2] - vshr.s8 d16, d16, #8 -@ CHECK: vshr.s16 d16, d16, #16 @ encoding: [0x30,0x00,0xd0,0xf2] - vshr.s16 d16, d16, #16 -@ CHECK: vshr.s32 d16, d16, #32 @ encoding: [0x30,0x00,0xe0,0xf2] - vshr.s32 d16, d16, #32 -@ CHECK: vshr.s64 d16, d16, #64 @ encoding: [0xb0,0x00,0xc0,0xf2] - vshr.s64 d16, d16, #64 -@ CHECK: vshr.s8 q8, q8, #8 @ encoding: [0x70,0x00,0xc8,0xf2] - vshr.s8 q8, q8, #8 -@ CHECK: vshr.s16 q8, q8, #16 @ encoding: [0x70,0x00,0xd0,0xf2] - vshr.s16 q8, q8, #16 -@ CHECK: vshr.s32 q8, q8, #32 @ encoding: [0x70,0x00,0xe0,0xf2 - vshr.s32 q8, q8, #32 -@ CHECK: vshr.s64 q8, q8, #64 @ encoding: [0xf0,0x00,0xc0,0xf2] - vshr.s64 q8, q8, #64 -@ CHECK: vshll.s8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf2] +@ CHECK: vshr.u8 d16, d16, #7 @ encoding: [0x30,0x00,0xc9,0xf3] + vshr.u8 d16, d16, #7 +@ CHECK: vshr.u16 d16, d16, #15 @ encoding: [0x30,0x00,0xd1,0xf3] + vshr.u16 d16, d16, #15 +@ CHECK: vshr.u32 d16, d16, #31 @ encoding: [0x30,0x00,0xe1,0xf3] + vshr.u32 d16, d16, #31 +@ CHECK: vshr.u64 d16, d16, #63 @ encoding: [0xb0,0x00,0xc1,0xf3] + vshr.u64 d16, d16, #63 +@ CHECK: vshr.u8 q8, q8, #7 @ encoding: [0x70,0x00,0xc9,0xf3] + vshr.u8 q8, q8, #7 +@ CHECK: vshr.u16 q8, q8, #15 @ encoding: [0x70,0x00,0xd1,0xf3] + vshr.u16 q8, q8, #15 +@ CHECK: vshr.u32 q8, q8, #31 @ encoding: [0x70,0x00,0xe1,0xf3] + vshr.u32 q8, q8, #31 +@ CHECK: vshr.u64 q8, q8, #63 @ encoding: [0xf0,0x00,0xc1,0xf3] + vshr.u64 q8, q8, #63 +@ CHECK: vshr.s8 d16, d16, #7 @ encoding: [0x30,0x00,0xc9,0xf2] + vshr.s8 d16, d16, #7 +@ CHECK: vshr.s16 d16, d16, #15 @ encoding: [0x30,0x00,0xd1,0xf2] + vshr.s16 d16, d16, #15 +@ CHECK: vshr.s32 d16, d16, #31 @ encoding: [0x30,0x00,0xe1,0xf2] + vshr.s32 d16, d16, #31 +@ CHECK: vshr.s64 d16, d16, #63 @ encoding: [0xb0,0x00,0xc1,0xf2] + vshr.s64 d16, d16, #63 +@ CHECK: vshr.s8 q8, q8, #7 @ encoding: [0x70,0x00,0xc9,0xf2] + vshr.s8 q8, q8, #7 +@ CHECK: vshr.s16 q8, q8, #15 @ encoding: [0x70,0x00,0xd1,0xf2] + vshr.s16 q8, q8, #15 +@ CHECK: vshr.s32 q8, q8, #31 @ encoding: [0x70,0x00,0xe1,0xf2] + vshr.s32 q8, q8, #31 +@ CHECK: vshr.s64 q8, q8, #63 @ encoding: [0xf0,0x00,0xc1,0xf2] + vshr.s64 q8, q8, #63 +@ CHECK: vsra.u8 d16, d16, #7 @ encoding: [0x30,0x01,0xc9,0xf3] + vsra.u8 d16, d16, #7 +@ CHECK: vsra.u16 d16, d16, #15 @ encoding: [0x30,0x01,0xd1,0xf3] + vsra.u16 d16, d16, #15 +@ CHECK: vsra.u32 d16, d16, #31 @ encoding: [0x30,0x01,0xe1,0xf3] + vsra.u32 d16, d16, #31 +@ CHECK: vsra.u64 d16, d16, #63 @ encoding: [0xb0,0x01,0xc1,0xf3] + vsra.u64 d16, d16, #63 +@ CHECK: vsra.u8 q8, q8, #7 @ encoding: [0x70,0x01,0xc9,0xf3] + vsra.u8 q8, q8, #7 +@ CHECK: vsra.u16 q8, q8, #15 @ encoding: [0x70,0x01,0xd1,0xf3] + vsra.u16 q8, q8, #15 +@ CHECK: vsra.u32 q8, q8, #31 @ encoding: [0x70,0x01,0xe1,0xf3] + vsra.u32 q8, q8, #31 +@ CHECK: vsra.u64 q8, q8, #63 @ encoding: [0xf0,0x01,0xc1,0xf3] + vsra.u64 q8, q8, #63 +@ CHECK: vsra.s8 d16, d16, #7 @ encoding: [0x30,0x01,0xc9,0xf2] + vsra.s8 d16, d16, #7 +@ CHECK: vsra.s16 d16, d16, #15 @ encoding: [0x30,0x01,0xd1,0xf2] + vsra.s16 d16, d16, #15 +@ CHECK: vsra.s32 d16, d16, #31 @ encoding: [0x30,0x01,0xe1,0xf2] + vsra.s32 d16, d16, #31 +@ CHECK: vsra.s64 d16, d16, #63 @ encoding: [0xb0,0x01,0xc1,0xf2] + vsra.s64 d16, d16, #63 +@ CHECK: vsra.s8 q8, q8, #7 @ encoding: [0x70,0x01,0xc9,0xf2] + vsra.s8 q8, q8, #7 +@ CHECK: vsra.s16 q8, q8, #15 @ encoding: [0x70,0x01,0xd1,0xf2] + vsra.s16 q8, q8, #15 +@ CHECK: vsra.s32 q8, q8, #31 @ encoding: [0x70,0x01,0xe1,0xf2] + vsra.s32 q8, q8, #31 +@ CHECK: vsra.s64 q8, q8, #63 @ encoding: [0xf0,0x01,0xc1,0xf2] + vsra.s64 q8, q8, #63 +@ CHECK: vsri.8 d16, d16, #7 @ encoding: [0x30,0x04,0xc9,0xf3] + vsri.8 d16, d16, #7 +@ CHECK: vsri.16 d16, d16, #15 @ encoding: [0x30,0x04,0xd1,0xf3] + vsri.16 d16, d16, #15 +@ CHECK: vsri.32 d16, d16, #31 @ encoding: [0x30,0x04,0xe1,0xf3] + vsri.32 d16, d16, #31 +@ CHECK: vsri.64 d16, d16, #63 @ encoding: [0xb0,0x04,0xc1,0xf3] + vsri.64 d16, d16, #63 +@ CHECK: vsri.8 q8, q8, #7 @ encoding: [0x70,0x04,0xc9,0xf3] + vsri.8 q8, q8, #7 +@ CHECK: vsri.16 q8, q8, #15 @ encoding: [0x70,0x04,0xd1,0xf3] + vsri.16 q8, q8, #15 +@ CHECK: vsri.32 q8, q8, #31 @ encoding: [0x70,0x04,0xe1,0xf3] + vsri.32 q8, q8, #31 +@ CHECK: vsri.64 q8, q8, #63 @ encoding: [0xf0,0x04,0xc1,0xf3] + vsri.64 q8, q8, #63 +@ CHECK: vsli.8 d16, d16, #7 @ encoding: [0x30,0x05,0xcf,0xf3] + vsli.8 d16, d16, #7 +@ CHECK: vsli.16 d16, d16, #15 @ encoding: [0x30,0x05,0xdf,0xf3] + vsli.16 d16, d16, #15 +@ CHECK: vsli.32 d16, d16, #31 @ encoding: [0x30,0x05,0xff,0xf3] + vsli.32 d16, d16, #31 +@ CHECK: vsli.64 d16, d16, #63 @ encoding: [0xb0,0x05,0xff,0xf3] + vsli.64 d16, d16, #63 +@ CHECK: vsli.8 q8, q8, #7 @ encoding: [0x70,0x05,0xcf,0xf3] + vsli.8 q8, q8, #7 +@ CHECK: vsli.16 q8, q8, #15 @ encoding: [0x70,0x05,0xdf,0xf3] + vsli.16 q8, q8, #15 +@ CHECK: vsli.32 q8, q8, #31 @ encoding: [0x70,0x05,0xff,0xf3] + vsli.32 q8, q8, #31 +@ CHECK: vsli.64 q8, q8, #63 @ encoding: [0xf0,0x05,0xff,0xf3] + vsli.64 q8, q8, #63 +@ CHECK: vshll.s8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf2] vshll.s8 q8, d16, #7 -@ CHECK: vshll.s16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf2] +@ CHECK: vshll.s16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf2] vshll.s16 q8, d16, #15 -@ CHECK: vshll.s32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf2] +@ CHECK: vshll.s32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf2] vshll.s32 q8, d16, #31 -@ CHECK: vshll.u8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf3] +@ CHECK: vshll.u8 q8, d16, #7 @ encoding: [0x30,0x0a,0xcf,0xf3] vshll.u8 q8, d16, #7 -@ CHECK: vshll.u16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf3] +@ CHECK: vshll.u16 q8, d16, #15 @ encoding: [0x30,0x0a,0xdf,0xf3] vshll.u16 q8, d16, #15 -@ CHECK: vshll.u32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf3] +@ CHECK: vshll.u32 q8, d16, #31 @ encoding: [0x30,0x0a,0xff,0xf3] vshll.u32 q8, d16, #31 -@ CHECK: vshll.i8 q8, d16, #8 @ encoding: [0x20,0x03,0xf2,0xf3] +@ CHECK: vshll.i8 q8, d16, #8 @ encoding: [0x20,0x03,0xf2,0xf3] vshll.i8 q8, d16, #8 -@ CHECK: vshll.i16 q8, d16, #16 @ encoding: [0x20,0x03,0xf6,0xf3] +@ CHECK: vshll.i16 q8, d16, #16 @ encoding: [0x20,0x03,0xf6,0xf3] vshll.i16 q8, d16, #16 -@ CHECK: vshll.i32 q8, d16, #32 @ encoding: [0x20,0x03,0xfa,0xf3] +@ CHECK: vshll.i32 q8, d16, #32 @ encoding: [0x20,0x03,0xfa,0xf3] vshll.i32 q8, d16, #32 -@ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2] +@ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2] vshrn.i16 d16, q8, #8 -@ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2] +@ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2] vshrn.i32 d16, q8, #16 -@ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2] +@ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2] vshrn.i64 d16, q8, #32 -@ CHECK: vrshl.s8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf2] +@ CHECK: vrshl.s8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf2] vrshl.s8 d16, d17, d16 -@ CHECK: vrshl.s16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf2] +@ CHECK: vrshl.s16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf2] vrshl.s16 d16, d17, d16 -@ CHECK: vrshl.s32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf2] +@ CHECK: vrshl.s32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf2] vrshl.s32 d16, d17, d16 -@ CHECK: vrshl.s64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0 +@ CHECK: vrshl.s64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0xf2] vrshl.s64 d16, d17, d16 -@ CHECK: vrshl.u8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf3] +@ CHECK: vrshl.u8 d16, d17, d16 @ encoding: [0xa1,0x05,0x40,0xf3] vrshl.u8 d16, d17, d16 -@ CHECK: vrshl.u16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf3] +@ CHECK: vrshl.u16 d16, d17, d16 @ encoding: [0xa1,0x05,0x50,0xf3] vrshl.u16 d16, d17, d16 -@ CHECK: vrshl.u32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf3] +@ CHECK: vrshl.u32 d16, d17, d16 @ encoding: [0xa1,0x05,0x60,0xf3] vrshl.u32 d16, d17, d16 -@ CHECK: vrshl.u64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0xf3] +@ CHECK: vrshl.u64 d16, d17, d16 @ encoding: [0xa1,0x05,0x70,0xf3] vrshl.u64 d16, d17, d16 -@ CHECK: vrshl.s8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf2] +@ CHECK: vrshl.s8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf2] vrshl.s8 q8, q9, q8 -@ CHECK: vrshl.s16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf2] +@ CHECK: vrshl.s16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf2] vrshl.s16 q8, q9, q8 -@ CHECK: vrshl.s32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf2] +@ CHECK: vrshl.s32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf2] vrshl.s32 q8, q9, q8 -@ CHECK: vrshl.s64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf2] +@ CHECK: vrshl.s64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf2] vrshl.s64 q8, q9, q8 -@ CHECK: vrshl.u8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf3] +@ CHECK: vrshl.u8 q8, q9, q8 @ encoding: [0xe2,0x05,0x40,0xf3] vrshl.u8 q8, q9, q8 -@ CHECK: vrshl.u16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf3] +@ CHECK: vrshl.u16 q8, q9, q8 @ encoding: [0xe2,0x05,0x50,0xf3] vrshl.u16 q8, q9, q8 -@ CHECK: vrshl.u32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf3] +@ CHECK: vrshl.u32 q8, q9, q8 @ encoding: [0xe2,0x05,0x60,0xf3] vrshl.u32 q8, q9, q8 -@ CHECK: vrshl.u64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf3] +@ CHECK: vrshl.u64 q8, q9, q8 @ encoding: [0xe2,0x05,0x70,0xf3] vrshl.u64 q8, q9, q8 -@ CHECK: vrshr.s8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf2] +@ CHECK: vrshr.s8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf2] vrshr.s8 d16, d16, #8 -@ CHECK: vrshr.s16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf2] +@ CHECK: vrshr.s16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf2] vrshr.s16 d16, d16, #16 -@ CHECK: vrshr.s32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf2] +@ CHECK: vrshr.s32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf2] vrshr.s32 d16, d16, #32 -@ CHECK: vrshr.s64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf2] +@ CHECK: vrshr.s64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf2] vrshr.s64 d16, d16, #64 -@ CHECK: vrshr.u8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf3] +@ CHECK: vrshr.u8 d16, d16, #8 @ encoding: [0x30,0x02,0xc8,0xf3] vrshr.u8 d16, d16, #8 -@ CHECK: vrshr.u16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf3] +@ CHECK: vrshr.u16 d16, d16, #16 @ encoding: [0x30,0x02,0xd0,0xf3] vrshr.u16 d16, d16, #16 -@ CHECK: vrshr.u32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf3] +@ CHECK: vrshr.u32 d16, d16, #32 @ encoding: [0x30,0x02,0xe0,0xf3] vrshr.u32 d16, d16, #32 -@ CHECK: vrshr.u64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf3] +@ CHECK: vrshr.u64 d16, d16, #64 @ encoding: [0xb0,0x02,0xc0,0xf3] vrshr.u64 d16, d16, #64 -@ CHECK: vrshr.s8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf2] +@ CHECK: vrshr.s8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf2] vrshr.s8 q8, q8, #8 -@ CHECK: vrshr.s16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf2] +@ CHECK: vrshr.s16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf2] vrshr.s16 q8, q8, #16 -@ CHECK: vrshr.s32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf2] +@ CHECK: vrshr.s32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf2] vrshr.s32 q8, q8, #32 -@ CHECK: vrshr.s64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf2] +@ CHECK: vrshr.s64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf2] vrshr.s64 q8, q8, #64 -@ CHECK: vrshr.u8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf3] +@ CHECK: vrshr.u8 q8, q8, #8 @ encoding: [0x70,0x02,0xc8,0xf3] vrshr.u8 q8, q8, #8 -@ CHECK: vrshr.u16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf3] +@ CHECK: vrshr.u16 q8, q8, #16 @ encoding: [0x70,0x02,0xd0,0xf3] vrshr.u16 q8, q8, #16 -@ CHECK: vrshr.u32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf3] +@ CHECK: vrshr.u32 q8, q8, #32 @ encoding: [0x70,0x02,0xe0,0xf3] vrshr.u32 q8, q8, #32 -@ CHECK: vrshr.u64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf3] +@ CHECK: vrshr.u64 q8, q8, #64 @ encoding: [0xf0,0x02,0xc0,0xf3] vrshr.u64 q8, q8, #64 -@ CHECK: vrshrn.i16 d16, q8, #8 @ encoding: [0x70,0x08,0xc8,0xf2] +@ CHECK: vrshrn.i16 d16, q8, #8 @ encoding: [0x70,0x08,0xc8,0xf2] vrshrn.i16 d16, q8, #8 -@ CHECK: vrshrn.i32 d16, q8, #16 @ encoding: [0x70,0x08,0xd0,0xf2] +@ CHECK: vrshrn.i32 d16, q8, #16 @ encoding: [0x70,0x08,0xd0,0xf2] vrshrn.i32 d16, q8, #16 -@ CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf2] +@ CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf2] vrshrn.i64 d16, q8, #32 +@ CHECK: vqrshrn.s16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf2] + vqrshrn.s16 d16, q8, #4 +@ CHECK: vqrshrn.s32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf2] + vqrshrn.s32 d16, q8, #13 +@ CHECK: vqrshrn.s64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf2] + vqrshrn.s64 d16, q8, #13 +@ CHECK: vqrshrn.u16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf3] + vqrshrn.u16 d16, q8, #4 +@ CHECK: vqrshrn.u32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf3] + vqrshrn.u32 d16, q8, #13 +@ CHECK: vqrshrn.u64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf3] + vqrshrn.u64 d16, q8, #13 diff --git a/test/MC/ARM/simple-encoding.ll b/test/MC/ARM/simple-encoding.ll index 0877e8e30c6f..7b581b3279fb 100644 --- a/test/MC/ARM/simple-encoding.ll +++ b/test/MC/ARM/simple-encoding.ll @@ -1,4 +1,4 @@ -;RUN: llc -mtriple=armv7-apple-darwin -show-mc-encoding < %s | FileCheck %s +;RUN: llc -mtriple=armv7-apple-darwin -show-mc-encoding -disable-cgp-branch-opts < %s | FileCheck %s ;FIXME: Once the ARM integrated assembler is up and going, these sorts of tests @@ -39,7 +39,7 @@ define i32 @f3(i32 %a, i32 %b) { define i32 @f4(i32 %a, i32 %b) { ; CHECK: f4 -; CHECK: add r0, r0, #254, 28 @ encoding: [0xfe,0x0e,0x80,0xe2] +; CHECK: add r0, r0, #254, #28 @ encoding: [0xfe,0x0e,0x80,0xe2] ; CHECK: @ 4064 ; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1] %add = add nsw i32 %a, 4064 @@ -118,7 +118,7 @@ define i32 @f12(i32 %a) { define i64 @f13() { ; CHECK: f13: ; CHECK: mvn r0, #0 @ encoding: [0x00,0x00,0xe0,0xe3] -; CHECK: mvn r1, #2, 2 @ encoding: [0x02,0x11,0xe0,0xe3] +; CHECK: mvn r1, #2, #2 @ encoding: [0x02,0x11,0xe0,0xe3] ret i64 9223372036854775807 } @@ -229,7 +229,7 @@ define i32 @f23(i32 %X, i32 %Y) { define void @f24(i32 %a) { ; CHECK: f24 -; CHECK: cmp r0, #1, 16 @ encoding: [0x01,0x08,0x50,0xe3] +; CHECK: cmp r0, #1, #16 @ encoding: [0x01,0x08,0x50,0xe3] %b = icmp ugt i32 %a, 65536 br i1 %b, label %r, label %r r: diff --git a/test/MC/ARM/thumb2.s b/test/MC/ARM/thumb2.s index cd093119e58a..5342b9001e47 100644 --- a/test/MC/ARM/thumb2.s +++ b/test/MC/ARM/thumb2.s @@ -284,3 +284,19 @@ @ CHECK: msr cpsr_fsxc, r0 @ encoding: [0x80,0xf3,0x00,0x8f] msr cpsr_fsxc, r0 +@ CHECK: strexb r0, r1, [r2] @ encoding: [0xc2,0xe8,0x40,0x1f] + strexb r0, r1, [r2] +@ CHECK: strexh r0, r1, [r2] @ encoding: [0xc2,0xe8,0x50,0x1f] + strexh r0, r1, [r2] +@ CHECK: strex r0, r1, [r2] @ encoding: [0x42,0xe8,0x00,0x10] + strex r0, r1, [r2] +@ CHECK: strexd r0, r2, r3, [r1] @ encoding: [0xc1,0xe8,0x70,0x23] + strexd r0, r2, r3, [r1] +@ CHECK: ldrexb r0, [r0] @ encoding: [0xd0,0xe8,0x4f,0x0f] + ldrexb r0, [r0] +@ CHECK: ldrexh r0, [r0] @ encoding: [0xd0,0xe8,0x5f,0x0f] + ldrexh r0, [r0] +@ CHECK: ldrex r0, [r0] @ encoding: [0x50,0xe8,0x00,0x0f] + ldrex r0, [r0] +@ CHECK: ldrexd r0, r1, [r0] @ encoding: [0xd0,0xe8,0x7f,0x01] + ldrexd r0, r1, [r0] diff --git a/test/MC/AsmParser/directive_space.s b/test/MC/AsmParser/directive_space.s index e6353a4af4de..fc5aeb4b6338 100644 --- a/test/MC/AsmParser/directive_space.s +++ b/test/MC/AsmParser/directive_space.s @@ -9,3 +9,8 @@ TEST0: # CHECK: .space 2,3 TEST1: .space 2, 3 + +# CHECK: TEST2: +# CHECK: .space 1 +TEST2: + .skip 1 diff --git a/test/MC/AsmParser/dot-symbol.s b/test/MC/AsmParser/dot-symbol.s new file mode 100644 index 000000000000..4a38a4053242 --- /dev/null +++ b/test/MC/AsmParser/dot-symbol.s @@ -0,0 +1,12 @@ +# Historically 'as' treats '.' as a reference to the current location in +# arbitrary contects. We don't support this in general. + +# RUN: not llvm-mc -triple i386-unknown-unknown %s 2> %t +# RUN: FileCheck -input-file %t %s + +# CHECK: assignment to pseudo-symbol '.' is unsupported (use '.space' or '.org'). +. = . + 8 + +# CHECK: invalid use of pseudo-symbol '.' as a label +.: + .long 0 diff --git a/test/MC/AsmParser/exprs-invalid.s b/test/MC/AsmParser/exprs-invalid.s index 5358fc5d7535..dc27d8043f5b 100644 --- a/test/MC/AsmParser/exprs-invalid.s +++ b/test/MC/AsmParser/exprs-invalid.s @@ -1,13 +1,8 @@ -// RUN: not llvm-mc -triple i386-unknown-unknown %s 2> %t -// RUN: FileCheck -input-file %t %s +// RUN: not llvm-mc -triple x86_64-apple-darwin10 %s 2> %t.err | FileCheck %s +// RUN: FileCheck --check-prefix=CHECK-ERRORS %s < %t.err +// CHECK: .section __TEXT,__text,regular,pure_instructions +// CHECK-ERRORS: error: invalid octal number +.long 80+08 -// Currently XFAIL'ed, since the front-end isn't validating this. Figure out the -// right resolution. -// -// XFAIL: * - - .text -a: - .data -// CHECK: expected relocatable expression - .long -(0 + a) +// CHECK-ERRORS: error: invalid hexadecimal number +.long 80+0xzz diff --git a/test/MC/AsmParser/floating-literals.s b/test/MC/AsmParser/floating-literals.s index bd122a8cf0e3..d44bb9830c08 100644 --- a/test/MC/AsmParser/floating-literals.s +++ b/test/MC/AsmParser/floating-literals.s @@ -6,6 +6,15 @@ # CHECK: .long 1082549862 .single 1.2455, +2.3, 3, + 4.2 +# CHECK: .long 2139095040 +.single InFinIty + +# CHECK: .long 4286578688 +.single -iNf + +# CHECK: .long 2147483647 +.single nAN + # CHECK: .long 1067928519 .float 1.307 diff --git a/test/MC/AsmParser/rename.s b/test/MC/AsmParser/rename.s index 64ca51538128..934cee808bd9 100644 --- a/test/MC/AsmParser/rename.s +++ b/test/MC/AsmParser/rename.s @@ -1,10 +1,14 @@ // RUN: llvm-mc -triple i386-unknown-unknown %s | FileCheck %s .size bar, . - bar +.Ltmp01: + .size foo, .Ltmp01 - foo .Ltmp0: - .size foo, .Ltmp0 - foo + .size qux, .Ltmp0 - qux // CHECK: .Ltmp0: // CHECK: .size bar, .Ltmp0-bar // CHECK: .Ltmp01 // CHECK: .size foo, .Ltmp01-foo +// CHECK: .Ltmp02 +// CHECK: .size qux, .Ltmp02-qux diff --git a/test/MC/AsmParser/section.s b/test/MC/AsmParser/section.s index 414fc6d5397f..5abacc701354 100644 --- a/test/MC/AsmParser/section.s +++ b/test/MC/AsmParser/section.s @@ -45,7 +45,7 @@ .previous .byte 1 .previous -# CHECK: (('sh_name', 0x00000012) # 'test1' +# CHECK: (('sh_name', 0x00000044) # 'test1' # CHECK-NEXT: ('sh_type', 0x00000001) # CHECK-NEXT: ('sh_flags', 0x00000000) # CHECK-NEXT: ('sh_addr', 0x00000000) @@ -57,7 +57,7 @@ # CHECK-NEXT: ('sh_entsize', 0x00000000) # CHECK-NEXT: ('_section_data', '01010101 010101') # CHECK-NEXT: ), -# CHECK: (('sh_name', 0x00000018) # 'test2' +# CHECK: (('sh_name', 0x0000003e) # 'test2' # CHECK-NEXT: ('sh_type', 0x00000001) # CHECK-NEXT: ('sh_flags', 0x00000000) # CHECK-NEXT: ('sh_addr', 0x00000000) @@ -69,7 +69,7 @@ # CHECK-NEXT: ('sh_entsize', 0x00000000) # CHECK-NEXT: ('_section_data', '02020202 0202') # CHECK-NEXT: ), -# CHECK: (('sh_name', 0x0000001e) # 'test3' +# CHECK: (('sh_name', 0x00000038) # 'test3' # CHECK-NEXT: ('sh_type', 0x00000001) # CHECK-NEXT: ('sh_flags', 0x00000000) # CHECK-NEXT: ('sh_addr', 0x00000000) @@ -81,7 +81,7 @@ # CHECK-NEXT: ('sh_entsize', 0x00000000) # CHECK-NEXT: ('_section_data', '03030303 03') # CHECK-NEXT: ), -# CHECK: (('sh_name', 0x00000024) # 'test4' +# CHECK: (('sh_name', 0x00000032) # 'test4' # CHECK-NEXT: ('sh_type', 0x00000001) # CHECK-NEXT: ('sh_flags', 0x00000000) # CHECK-NEXT: ('sh_addr', 0x00000000) @@ -93,7 +93,7 @@ # CHECK-NEXT: ('sh_entsize', 0x00000000) # CHECK-NEXT: ('_section_data', '040404') # CHECK-NEXT: ), -# CHECK: (('sh_name', 0x0000002a) # 'test5' +# CHECK: (('sh_name', 0x0000002c) # 'test5' # CHECK-NEXT: ('sh_type', 0x00000001) # CHECK-NEXT: ('sh_flags', 0x00000000) # CHECK-NEXT: ('sh_addr', 0x00000000) diff --git a/test/MC/COFF/basic-coff.s b/test/MC/COFF/basic-coff.s index 0c8658258ed4..23156b82d2e5 100644 --- a/test/MC/COFF/basic-coff.s +++ b/test/MC/COFF/basic-coff.s @@ -1,133 +1,133 @@ -// This test checks that the COFF object emitter works for the most basic
-// programs.
-
-// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | coff-dump.py | FileCheck %s
-// I WOULD RUN, BUT THIS FAILS: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s
-
-.def _main;
- .scl 2;
- .type 32;
- .endef
- .text
- .globl _main
- .align 16, 0x90
-_main: # @main
-# BB#0: # %entry
- subl $4, %esp
- movl $L_.str, (%esp)
- calll _printf
- xorl %eax, %eax
- addl $4, %esp
- ret
-
- .data
-L_.str: # @.str
- .asciz "Hello World"
-
-// CHECK: {
-// CHECK: MachineType = IMAGE_FILE_MACHINE_I386 (0x14C)
-// CHECK: NumberOfSections = 2
-// CHECK: TimeDateStamp = {{[0-9]+}}
-// CHECK: PointerToSymbolTable = 0x{{[0-9A-F]+}}
-// CHECK: NumberOfSymbols = 6
-// CHECK: SizeOfOptionalHeader = 0
-// CHECK: Characteristics = 0x0
-// CHECK: Sections = [
-// CHECK: 1 = {
-// CHECK: Name = .text
-// CHECK: VirtualSize = 0
-// CHECK: VirtualAddress = 0
-// CHECK: SizeOfRawData = {{[0-9]+}}
-// CHECK: PointerToRawData = 0x{{[0-9A-F]+}}
-// CHECK: PointerToRelocations = 0x{{[0-9A-F]+}}
-// CHECK: PointerToLineNumbers = 0x0
-// CHECK: NumberOfRelocations = 2
-// CHECK: NumberOfLineNumbers = 0
-// CHECK: Charateristics = 0x60500020
-// CHECK: IMAGE_SCN_CNT_CODE
-// CHECK: IMAGE_SCN_ALIGN_16BYTES
-// CHECK: IMAGE_SCN_MEM_EXECUTE
-// CHECK: IMAGE_SCN_MEM_READ
-// CHECK: SectionData =
-// CHECK: Relocations = [
-// CHECK: 0 = {
-// CHECK: VirtualAddress = 0x{{[0-9A-F]+}}
-// CHECK: SymbolTableIndex = 2
-// CHECK: Type = IMAGE_REL_I386_DIR32 (6)
-// CHECK: SymbolName = .data
-// CHECK: }
-// CHECK: 1 = {
-// CHECK: VirtualAddress = 0x{{[0-9A-F]+}}
-// CHECK: SymbolTableIndex = 5
-// CHECK: Type = IMAGE_REL_I386_REL32 (20)
-// CHECK: SymbolName = _printf
-// CHECK: }
-// CHECK: ]
-// CHECK: }
-// CHECK: 2 = {
-// CHECK: Name = .data
-// CHECK: VirtualSize = 0
-// CHECK: VirtualAddress = 0
-// CHECK: SizeOfRawData = {{[0-9]+}}
-// CHECK: PointerToRawData = 0x{{[0-9A-F]+}}
-// CHECK: PointerToRelocations = 0x0
-// CHECK: PointerToLineNumbers = 0x0
-// CHECK: NumberOfRelocations = 0
-// CHECK: NumberOfLineNumbers = 0
-// CHECK: Charateristics = 0xC0300040
-// CHECK: IMAGE_SCN_CNT_INITIALIZED_DATA
-// CHECK: IMAGE_SCN_ALIGN_4BYTES
-// CHECK: IMAGE_SCN_MEM_READ
-// CHECK: IMAGE_SCN_MEM_WRITE
-// CHECK: SectionData =
-// CHECK: 48 65 6C 6C 6F 20 57 6F - 72 6C 64 00 |Hello World.|
-// CHECK: Relocations = None
-// CHECK: }
-// CHECK: ]
-// CHECK: Symbols = [
-// CHECK: 0 = {
-// CHECK: Name = .text
-// CHECK: Value = 0
-// CHECK: SectionNumber = 1
-// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0)
-// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0)
-// CHECK: StorageClass = IMAGE_SYM_CLASS_STATIC (3)
-// CHECK: NumberOfAuxSymbols = 1
-// CHECK: AuxillaryData =
-// CHECK: 15 00 00 00 02 00 00 00 - 00 00 00 00 01 00 00 00 |................|
-// CHECK: 00 00 |..|
-// CHECK: }
-// CHECK: 2 = {
-// CHECK: Name = .data
-// CHECK: Value = 0
-// CHECK: SectionNumber = 2
-// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0)
-// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0)
-// CHECK: StorageClass = IMAGE_SYM_CLASS_STATIC (3)
-// CHECK: NumberOfAuxSymbols = 1
-// CHECK: AuxillaryData =
-// CHECK: 0C 00 00 00 00 00 00 00 - 00 00 00 00 02 00 00 00 |................|
-// CHECK: 00 00 |..|
-// CHECK: }
-// CHECK: 4 = {
-// CHECK: Name = _main
-// CHECK: Value = 0
-// CHECK: SectionNumber = 1
-// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0)
-// CHECK: ComplexType = IMAGE_SYM_DTYPE_FUNCTION (2)
-// CHECK: StorageClass = IMAGE_SYM_CLASS_EXTERNAL (2)
-// CHECK: NumberOfAuxSymbols = 0
-// CHECK: AuxillaryData =
-// CHECK: }
-// CHECK: 5 = {
-// CHECK: Name = _printf
-// CHECK: Value = 0
-// CHECK: SectionNumber = 0
-// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0)
-// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0)
-// CHECK: StorageClass = IMAGE_SYM_CLASS_EXTERNAL (2)
-// CHECK: NumberOfAuxSymbols = 0
-// CHECK: AuxillaryData =
-// CHECK: }
-// CHECK: ]
-// CHECK: }
+// This test checks that the COFF object emitter works for the most basic +// programs. + +// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | coff-dump.py | FileCheck %s +// I WOULD RUN, BUT THIS FAILS: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s + +.def _main; + .scl 2; + .type 32; + .endef + .text + .globl _main + .align 16, 0x90 +_main: # @main +# BB#0: # %entry + subl $4, %esp + movl $L_.str, (%esp) + calll _printf + xorl %eax, %eax + addl $4, %esp + ret + + .data +L_.str: # @.str + .asciz "Hello World" + +// CHECK: { +// CHECK: MachineType = IMAGE_FILE_MACHINE_I386 (0x14C) +// CHECK: NumberOfSections = 2 +// CHECK: TimeDateStamp = {{[0-9]+}} +// CHECK: PointerToSymbolTable = 0x{{[0-9A-F]+}} +// CHECK: NumberOfSymbols = 6 +// CHECK: SizeOfOptionalHeader = 0 +// CHECK: Characteristics = 0x0 +// CHECK: Sections = [ +// CHECK: 1 = { +// CHECK: Name = .text +// CHECK: VirtualSize = 0 +// CHECK: VirtualAddress = 0 +// CHECK: SizeOfRawData = {{[0-9]+}} +// CHECK: PointerToRawData = 0x{{[0-9A-F]+}} +// CHECK: PointerToRelocations = 0x{{[0-9A-F]+}} +// CHECK: PointerToLineNumbers = 0x0 +// CHECK: NumberOfRelocations = 2 +// CHECK: NumberOfLineNumbers = 0 +// CHECK: Charateristics = 0x60500020 +// CHECK: IMAGE_SCN_CNT_CODE +// CHECK: IMAGE_SCN_ALIGN_16BYTES +// CHECK: IMAGE_SCN_MEM_EXECUTE +// CHECK: IMAGE_SCN_MEM_READ +// CHECK: SectionData = +// CHECK: Relocations = [ +// CHECK: 0 = { +// CHECK: VirtualAddress = 0x{{[0-9A-F]+}} +// CHECK: SymbolTableIndex = 2 +// CHECK: Type = IMAGE_REL_I386_DIR32 (6) +// CHECK: SymbolName = .data +// CHECK: } +// CHECK: 1 = { +// CHECK: VirtualAddress = 0x{{[0-9A-F]+}} +// CHECK: SymbolTableIndex = 5 +// CHECK: Type = IMAGE_REL_I386_REL32 (20) +// CHECK: SymbolName = _printf +// CHECK: } +// CHECK: ] +// CHECK: } +// CHECK: 2 = { +// CHECK: Name = .data +// CHECK: VirtualSize = 0 +// CHECK: VirtualAddress = 0 +// CHECK: SizeOfRawData = {{[0-9]+}} +// CHECK: PointerToRawData = 0x{{[0-9A-F]+}} +// CHECK: PointerToRelocations = 0x0 +// CHECK: PointerToLineNumbers = 0x0 +// CHECK: NumberOfRelocations = 0 +// CHECK: NumberOfLineNumbers = 0 +// CHECK: Charateristics = 0xC0300040 +// CHECK: IMAGE_SCN_CNT_INITIALIZED_DATA +// CHECK: IMAGE_SCN_ALIGN_4BYTES +// CHECK: IMAGE_SCN_MEM_READ +// CHECK: IMAGE_SCN_MEM_WRITE +// CHECK: SectionData = +// CHECK: 48 65 6C 6C 6F 20 57 6F - 72 6C 64 00 |Hello World.| +// CHECK: Relocations = None +// CHECK: } +// CHECK: ] +// CHECK: Symbols = [ +// CHECK: 0 = { +// CHECK: Name = .text +// CHECK: Value = 0 +// CHECK: SectionNumber = 1 +// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0) +// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0) +// CHECK: StorageClass = IMAGE_SYM_CLASS_STATIC (3) +// CHECK: NumberOfAuxSymbols = 1 +// CHECK: AuxillaryData = +// CHECK: 15 00 00 00 02 00 00 00 - 00 00 00 00 01 00 00 00 |................| +// CHECK: 00 00 |..| +// CHECK: } +// CHECK: 2 = { +// CHECK: Name = .data +// CHECK: Value = 0 +// CHECK: SectionNumber = 2 +// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0) +// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0) +// CHECK: StorageClass = IMAGE_SYM_CLASS_STATIC (3) +// CHECK: NumberOfAuxSymbols = 1 +// CHECK: AuxillaryData = +// CHECK: 0C 00 00 00 00 00 00 00 - 00 00 00 00 02 00 00 00 |................| +// CHECK: 00 00 |..| +// CHECK: } +// CHECK: 4 = { +// CHECK: Name = _main +// CHECK: Value = 0 +// CHECK: SectionNumber = 1 +// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0) +// CHECK: ComplexType = IMAGE_SYM_DTYPE_FUNCTION (2) +// CHECK: StorageClass = IMAGE_SYM_CLASS_EXTERNAL (2) +// CHECK: NumberOfAuxSymbols = 0 +// CHECK: AuxillaryData = +// CHECK: } +// CHECK: 5 = { +// CHECK: Name = _printf +// CHECK: Value = 0 +// CHECK: SectionNumber = 0 +// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0) +// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0) +// CHECK: StorageClass = IMAGE_SYM_CLASS_EXTERNAL (2) +// CHECK: NumberOfAuxSymbols = 0 +// CHECK: AuxillaryData = +// CHECK: } +// CHECK: ] +// CHECK: } diff --git a/test/MC/COFF/bss.s b/test/MC/COFF/bss.s index f44225b5a336..3bed13d4aac9 100644 --- a/test/MC/COFF/bss.s +++ b/test/MC/COFF/bss.s @@ -1,15 +1,15 @@ -// The purpose of this test is to verify that bss sections are emited correctly.
-
-// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | coff-dump.py | FileCheck %s
-// RUN: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | coff-dump.py | FileCheck %s
-
- .bss
- .globl _g0
- .align 4
-_g0:
- .long 0
-
-// CHECK: Name = .bss
-// CHECK-NEXT: VirtualSize = 0
-// CHECK-NEXT: VirtualAddress = 0
-// CHECK-NEXT: SizeOfRawData = 4
+// The purpose of this test is to verify that bss sections are emited correctly. + +// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | coff-dump.py | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | coff-dump.py | FileCheck %s + + .bss + .globl _g0 + .align 4 +_g0: + .long 0 + +// CHECK: Name = .bss +// CHECK-NEXT: VirtualSize = 0 +// CHECK-NEXT: VirtualAddress = 0 +// CHECK-NEXT: SizeOfRawData = 4 diff --git a/test/MC/COFF/diff.s b/test/MC/COFF/diff.s new file mode 100644 index 000000000000..aa683f26a7b1 --- /dev/null +++ b/test/MC/COFF/diff.s @@ -0,0 +1,46 @@ +// RUN: llvm-mc -filetype=obj -triple i686-pc-mingw32 %s | coff-dump.py | FileCheck %s + + .def _foobar; + .scl 2; + .type 32; + .endef + .text + .long 0 + .globl _foobar + .align 16, 0x90 +_foobar: # @foobar +# BB#0: + ret + + .data + .globl _rust_crate # @rust_crate + .align 4 +_rust_crate: + .long 0 + .long _foobar + .long _foobar-_rust_crate + .long _foobar-_rust_crate + +// CHECK: Name = .data +// CHECK: SectionData = +// CHECK-NEXT: 00 00 00 00 00 00 00 00 - 1C 00 00 00 20 00 00 00 |............ ...| +// CHECK: Relocations = [ +// CHECK-NEXT: 0 = { +// CHECK-NEXT: VirtualAddress = 0x4 +// CHECK-NEXT: SymbolTableIndex = +// CHECK-NEXT: Type = IMAGE_REL_I386_DIR32 (6) +// CHECK-NEXT: SymbolName = _foobar +// CHECK-NEXT: } +// CHECK-NEXT: 1 = { +// CHECK-NEXT: VirtualAddress = 0x8 +// CHECK-NEXT: SymbolTableIndex = 0 +// CHECK-NEXT: Type = IMAGE_REL_I386_REL32 (20) +// CHECK-NEXT: SymbolName = .text +// CHECK-NEXT: } +// CHECK-NEXT: 2 = { +// CHECK-NEXT: VirtualAddress = 0xC +// CHECK-NEXT: SymbolTableIndex = 0 +// CHECK-NEXT: Type = IMAGE_REL_I386_REL32 (20) +// CHECK-NEXT: SymbolName = .text +// CHECK-NEXT: } +// CHECK-NEXT: ] diff --git a/test/MC/COFF/simple-fixups.s b/test/MC/COFF/simple-fixups.s index f86f4a9ff9e4..4c9b4d44528f 100644 --- a/test/MC/COFF/simple-fixups.s +++ b/test/MC/COFF/simple-fixups.s @@ -1,50 +1,50 @@ -// The purpose of this test is to verify that we do not produce unneeded
-// relocations when symbols are in the same section and we know their offset.
-
-// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | coff-dump.py | FileCheck %s
-// I WOULD RUN, BUT THIS FAILS: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | coff-dump.py | FileCheck %s
-
- .def _foo;
- .scl 2;
- .type 32;
- .endef
- .text
- .globl _foo
- .align 16, 0x90
-_foo: # @foo
-# BB#0: # %e
- .align 16, 0x90
-LBB0_1: # %i
- # =>This Inner Loop Header: Depth=1
- jmp LBB0_1
-
- .def _bar;
- .scl 2;
- .type 32;
- .endef
- .globl _bar
- .align 16, 0x90
-_bar: # @bar
-# BB#0: # %e
- .align 16, 0x90
-LBB1_1: # %i
- # =>This Inner Loop Header: Depth=1
- jmp LBB1_1
-
- .def _baz;
- .scl 2;
- .type 32;
- .endef
- .globl _baz
- .align 16, 0x90
-_baz: # @baz
-# BB#0: # %e
- subl $4, %esp
-Ltmp0:
- calll _baz
- addl $4, %esp
- ret
-
-// CHECK: Sections = [
-// CHECK-NOT: NumberOfRelocations = {{[^0]}}
-// CHECK: Symbols = [
+// The purpose of this test is to verify that we do not produce unneeded +// relocations when symbols are in the same section and we know their offset. + +// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | coff-dump.py | FileCheck %s +// I WOULD RUN, BUT THIS FAILS: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | coff-dump.py | FileCheck %s + + .def _foo; + .scl 2; + .type 32; + .endef + .text + .globl _foo + .align 16, 0x90 +_foo: # @foo +# BB#0: # %e + .align 16, 0x90 +LBB0_1: # %i + # =>This Inner Loop Header: Depth=1 + jmp LBB0_1 + + .def _bar; + .scl 2; + .type 32; + .endef + .globl _bar + .align 16, 0x90 +_bar: # @bar +# BB#0: # %e + .align 16, 0x90 +LBB1_1: # %i + # =>This Inner Loop Header: Depth=1 + jmp LBB1_1 + + .def _baz; + .scl 2; + .type 32; + .endef + .globl _baz + .align 16, 0x90 +_baz: # @baz +# BB#0: # %e + subl $4, %esp +Ltmp0: + calll _baz + addl $4, %esp + ret + +// CHECK: Sections = [ +// CHECK-NOT: NumberOfRelocations = {{[^0]}} +// CHECK: Symbols = [ diff --git a/test/MC/COFF/symbol-alias.s b/test/MC/COFF/symbol-alias.s index ede6b53c4511..03f07b2e5685 100644 --- a/test/MC/COFF/symbol-alias.s +++ b/test/MC/COFF/symbol-alias.s @@ -1,62 +1,62 @@ -// The purpose of this test is to verify that symbol aliases
-// (@foo = alias <type> @bar) generate the correct entries in the symbol table.
-// They should be identical except for the name.
-
-// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | coff-dump.py | FileCheck %s
-// RUN: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | coff-dump.py | FileCheck %s
-
- .def _foo;
- .scl 2;
- .type 32;
- .endef
- .text
- .globl _foo
- .align 16, 0x90
-_foo: # @foo
-# BB#0: # %entry
- ret
-
- .data
- .globl _bar # @bar
- .align 4
-_bar:
- .long 0 # 0x0
-
-
- .globl _foo_alias
-_foo_alias = _foo
- .globl _bar_alias
-_bar_alias = _bar
-
-// CHECK: Name = {{_?}}foo
-// CHECK-NEXT: Value = [[FOO_VALUE:.*$]]
-// CHECK-NEXT: SectionNumber = [[FOO_SECTION_NUMBER:.*$]]
-// CHECK-NEXT: SimpleType = [[FOO_SIMPLE_TYPE:.*$]]
-// CHECK-NEXT: ComplexType = [[FOO_COMPLEX_TYPE:.*$]]
-// CHECK-NEXT: StorageClass = [[FOO_STORAGE_CLASS:.*$]]
-// CHECK-NEXT: NumberOfAuxSymbols = [[FOO_NUMBER_OF_AUX_SYMBOLS:.*$]]
-
-// CHECK: Name = {{_?}}bar
-// CHECK-NEXT: Value = [[BAR_VALUE:.*$]]
-// CHECK-NEXT: SectionNumber = [[BAR_SECTION_NUMBER:.*$]]
-// CHECK-NEXT: SimpleType = [[BAR_SIMPLE_TYPE:.*$]]
-// CHECK-NEXT: ComplexType = [[BAR_COMPLEX_TYPE:.*$]]
-// CHECK-NEXT: StorageClass = [[BAR_STORAGE_CLASS:.*$]]
-// CHECK-NEXT: NumberOfAuxSymbols = [[BAR_NUMBER_OF_AUX_SYMBOLS:.*$]]
-
-// CHECK: Name = {{_?}}foo_alias
-// CHECK-NEXT: Value = [[FOO_VALUE]]
-// CHECK-NEXT: SectionNumber = [[FOO_SECTION_NUMBER]]
-// CHECK-NEXT: SimpleType = [[FOO_SIMPLE_TYPE]]
-// CHECK-NEXT: ComplexType = [[FOO_COMPLEX_TYPE]]
-// CHECK-NEXT: StorageClass = [[FOO_STORAGE_CLASS]]
-// CHECK-NEXT: NumberOfAuxSymbols = [[FOO_NUMBER_OF_AUX_SYMBOLS]]
-
-// CHECK: Name = {{_?}}bar_alias
-// CHECK-NEXT: Value = [[BAR_VALUE]]
-// CHECK-NEXT: SectionNumber = [[BAR_SECTION_NUMBER]]
-// CHECK-NEXT: SimpleType = [[BAR_SIMPLE_TYPE]]
-// CHECK-NEXT: ComplexType = [[BAR_COMPLEX_TYPE]]
-// CHECK-NEXT: StorageClass = [[BAR_STORAGE_CLASS]]
-// CHECK-NEXT: NumberOfAuxSymbols = [[BAR_NUMBER_OF_AUX_SYMBOLS]]
-
+// The purpose of this test is to verify that symbol aliases +// (@foo = alias <type> @bar) generate the correct entries in the symbol table. +// They should be identical except for the name. + +// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | coff-dump.py | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | coff-dump.py | FileCheck %s + + .def _foo; + .scl 2; + .type 32; + .endef + .text + .globl _foo + .align 16, 0x90 +_foo: # @foo +# BB#0: # %entry + ret + + .data + .globl _bar # @bar + .align 4 +_bar: + .long 0 # 0x0 + + + .globl _foo_alias +_foo_alias = _foo + .globl _bar_alias +_bar_alias = _bar + +// CHECK: Name = {{_?}}foo +// CHECK-NEXT: Value = [[FOO_VALUE:.*$]] +// CHECK-NEXT: SectionNumber = [[FOO_SECTION_NUMBER:.*$]] +// CHECK-NEXT: SimpleType = [[FOO_SIMPLE_TYPE:.*$]] +// CHECK-NEXT: ComplexType = [[FOO_COMPLEX_TYPE:.*$]] +// CHECK-NEXT: StorageClass = [[FOO_STORAGE_CLASS:.*$]] +// CHECK-NEXT: NumberOfAuxSymbols = [[FOO_NUMBER_OF_AUX_SYMBOLS:.*$]] + +// CHECK: Name = {{_?}}bar +// CHECK-NEXT: Value = [[BAR_VALUE:.*$]] +// CHECK-NEXT: SectionNumber = [[BAR_SECTION_NUMBER:.*$]] +// CHECK-NEXT: SimpleType = [[BAR_SIMPLE_TYPE:.*$]] +// CHECK-NEXT: ComplexType = [[BAR_COMPLEX_TYPE:.*$]] +// CHECK-NEXT: StorageClass = [[BAR_STORAGE_CLASS:.*$]] +// CHECK-NEXT: NumberOfAuxSymbols = [[BAR_NUMBER_OF_AUX_SYMBOLS:.*$]] + +// CHECK: Name = {{_?}}foo_alias +// CHECK-NEXT: Value = [[FOO_VALUE]] +// CHECK-NEXT: SectionNumber = [[FOO_SECTION_NUMBER]] +// CHECK-NEXT: SimpleType = [[FOO_SIMPLE_TYPE]] +// CHECK-NEXT: ComplexType = [[FOO_COMPLEX_TYPE]] +// CHECK-NEXT: StorageClass = [[FOO_STORAGE_CLASS]] +// CHECK-NEXT: NumberOfAuxSymbols = [[FOO_NUMBER_OF_AUX_SYMBOLS]] + +// CHECK: Name = {{_?}}bar_alias +// CHECK-NEXT: Value = [[BAR_VALUE]] +// CHECK-NEXT: SectionNumber = [[BAR_SECTION_NUMBER]] +// CHECK-NEXT: SimpleType = [[BAR_SIMPLE_TYPE]] +// CHECK-NEXT: ComplexType = [[BAR_COMPLEX_TYPE]] +// CHECK-NEXT: StorageClass = [[BAR_STORAGE_CLASS]] +// CHECK-NEXT: NumberOfAuxSymbols = [[BAR_NUMBER_OF_AUX_SYMBOLS]] + diff --git a/test/MC/COFF/symbol-fragment-offset.s b/test/MC/COFF/symbol-fragment-offset.s index c314ac20f4db..1df8baacaf22 100644 --- a/test/MC/COFF/symbol-fragment-offset.s +++ b/test/MC/COFF/symbol-fragment-offset.s @@ -1,187 +1,187 @@ -// The purpose of this test is to see if the COFF object writer is emitting the
-// proper relocations for multiple pieces of data in a single data fragment.
-
-// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | coff-dump.py | FileCheck %s
-// I WOULD RUN, BUT THIS FAILS: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s
-
-.def _main;
- .scl 2;
- .type 32;
- .endef
- .text
- .globl _main
- .align 16, 0x90
-_main: # @main
-# BB#0: # %entry
- subl $4, %esp
- movl $L_.str0, (%esp)
- calll _printf
- movl $L_.str1, (%esp)
- calll _puts
- movl $L_.str2, (%esp)
- calll _puts
- xorl %eax, %eax
- addl $4, %esp
- ret
-
- .data
-L_.str0: # @.str0
- .asciz "Hello "
-
-L_.str1: # @.str1
- .asciz "World!"
-
- .align 16 # @.str2
-L_.str2:
- .asciz "I'm The Last Line."
-
-// CHECK: {
-// CHECK: MachineType = IMAGE_FILE_MACHINE_I386 (0x14C)
-// CHECK: NumberOfSections = 2
-// CHECK: TimeDateStamp = {{[0-9]+}}
-// CHECK: PointerToSymbolTable = 0x{{[0-9A-F]+}}
-// CHECK: NumberOfSymbols = 7
-// CHECK: SizeOfOptionalHeader = 0
-// CHECK: Characteristics = 0x0
-// CHECK: Sections = [
-// CHECK: 1 = {
-// CHECK: Name = .text
-// CHECK: VirtualSize = 0
-// CHECK: VirtualAddress = 0
-// CHECK: SizeOfRawData = {{[0-9]+}}
-// CHECK: PointerToRawData = 0x{{[0-9A-F]+}}
-// CHECK: PointerToRelocations = 0x{{[0-9A-F]+}}
-// CHECK: PointerToLineNumbers = 0x0
-// CHECK: NumberOfRelocations = 6
-// CHECK: NumberOfLineNumbers = 0
-// CHECK: Charateristics = 0x60500020
-// CHECK: IMAGE_SCN_CNT_CODE
-// CHECK: IMAGE_SCN_ALIGN_16BYTES
-// CHECK: IMAGE_SCN_MEM_EXECUTE
-// CHECK: IMAGE_SCN_MEM_READ
-// CHECK: SectionData =
-// CHECK: 83 EC 04 C7 04 24 00 00 - 00 00 E8 00 00 00 00 C7 |.....$..........|
-// CHECK: 04 24 07 00 00 00 E8 00 - 00 00 00 C7 04 24 10 00 |.$...........$..|
-// CHECK: 00 00 E8 00 00 00 00 31 - C0 83 C4 04 C3 |.......1.....|
-// CHECK: Relocations = [
-// CHECK: 0 = {
-// CHECK: VirtualAddress = 0x6
-// CHECK: SymbolTableIndex = 2
-// CHECK: Type = IMAGE_REL_I386_DIR32 (6)
-// CHECK: SymbolName = .data
-// CHECK: }
-// CHECK: 1 = {
-// CHECK: VirtualAddress = 0xB
-// CHECK: SymbolTableIndex = 5
-// CHECK: Type = IMAGE_REL_I386_REL32 (20)
-// CHECK: SymbolName = _printf
-// CHECK: }
-// CHECK: 2 = {
-// CHECK: VirtualAddress = 0x12
-// CHECK: SymbolTableIndex = 2
-// CHECK: Type = IMAGE_REL_I386_DIR32 (6)
-// CHECK: SymbolName = .data
-// CHECK: }
-// CHECK: 3 = {
-// CHECK: VirtualAddress = 0x17
-// CHECK: SymbolTableIndex = 6
-// CHECK: Type = IMAGE_REL_I386_REL32 (20)
-// CHECK: SymbolName = _puts
-// CHECK: }
-// CHECK: 4 = {
-// CHECK: VirtualAddress = 0x1E
-// CHECK: SymbolTableIndex = 2
-// CHECK: Type = IMAGE_REL_I386_DIR32 (6)
-// CHECK: SymbolName = .data
-// CHECK: }
-// CHECK: 5 = {
-// CHECK: VirtualAddress = 0x23
-// CHECK: SymbolTableIndex = 6
-// CHECK: Type = IMAGE_REL_I386_REL32 (20)
-// CHECK: SymbolName = _puts
-// CHECK: }
-// CHECK: ]
-// CHECK: }
-// CHECK: 2 = {
-// CHECK: Name = .data
-// CHECK: VirtualSize = 0
-// CHECK: VirtualAddress = 0
-// CHECK: SizeOfRawData = {{[0-9]+}}
-// CHECK: PointerToRawData = 0x{{[0-9A-F]+}}
-// CHECK: PointerToRelocations = 0x0
-// CHECK: PointerToLineNumbers = 0x0
-// CHECK: NumberOfRelocations = 0
-// CHECK: NumberOfLineNumbers = 0
-// CHECK: Charateristics = 0xC0500040
-// CHECK: IMAGE_SCN_CNT_INITIALIZED_DATA
-// CHECK: IMAGE_SCN_ALIGN_16BYTES
-// CHECK: IMAGE_SCN_MEM_READ
-// CHECK: IMAGE_SCN_MEM_WRITE
-// CHECK: SectionData =
-// CHECK: 48 65 6C 6C 6F 20 00 57 - 6F 72 6C 64 21 00 00 00 |Hello .World!...|
-// CHECK: 49 27 6D 20 54 68 65 20 - 4C 61 73 74 20 4C 69 6E |I'm The Last Lin|
-// CHECK: 65 2E 00 |e..|
-// CHECK: Relocations = None
-// CHECK: }
-// CHECK: ]
-// CHECK: Symbols = [
-// CHECK: 0 = {
-// CHECK: Name = .text
-// CHECK: Value = 0
-// CHECK: SectionNumber = 1
-// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0)
-// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0)
-// CHECK: StorageClass = IMAGE_SYM_CLASS_STATIC (3)
-// CHECK: NumberOfAuxSymbols = 1
-// CHECK: AuxillaryData =
-// CHECK: 2D 00 00 00 06 00 00 00 - 00 00 00 00 01 00 00 00 |-...............|
-// CHECK: 00 00 |..|
-
-// CHECK: }
-// CHECK: 2 = {
-// CHECK: Name = .data
-// CHECK: Value = 0
-// CHECK: SectionNumber = 2
-// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0)
-// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0)
-// CHECK: StorageClass = IMAGE_SYM_CLASS_STATIC (3)
-// CHECK: NumberOfAuxSymbols = 1
-// CHECK: AuxillaryData =
-// CHECK: 23 00 00 00 00 00 00 00 - 00 00 00 00 02 00 00 00 |#...............|
-// CHECK: 00 00 |..|
-
-// CHECK: }
-// CHECK: 4 = {
-// CHECK: Name = _main
-// CHECK: Value = 0
-// CHECK: SectionNumber = 1
-// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0)
-// CHECK: ComplexType = IMAGE_SYM_DTYPE_FUNCTION (2)
-// CHECK: StorageClass = IMAGE_SYM_CLASS_EXTERNAL (2)
-// CHECK: NumberOfAuxSymbols = 0
-// CHECK: AuxillaryData =
-
-// CHECK: 5 = {
-// CHECK: Name = _printf
-// CHECK: Value = 0
-// CHECK: SectionNumber = 0
-// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0)
-// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0)
-// CHECK: StorageClass = IMAGE_SYM_CLASS_EXTERNAL (2)
-// CHECK: NumberOfAuxSymbols = 0
-// CHECK: AuxillaryData =
-
-// CHECK: }
-// CHECK: 6 = {
-// CHECK: Name = _puts
-// CHECK: Value = 0
-// CHECK: SectionNumber = 0
-// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0)
-// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0)
-// CHECK: StorageClass = IMAGE_SYM_CLASS_EXTERNAL (2)
-// CHECK: NumberOfAuxSymbols = 0
-// CHECK: AuxillaryData =
-
-// CHECK: }
-// CHECK: ]
-// CHECK: }
+// The purpose of this test is to see if the COFF object writer is emitting the +// proper relocations for multiple pieces of data in a single data fragment. + +// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | coff-dump.py | FileCheck %s +// I WOULD RUN, BUT THIS FAILS: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s + +.def _main; + .scl 2; + .type 32; + .endef + .text + .globl _main + .align 16, 0x90 +_main: # @main +# BB#0: # %entry + subl $4, %esp + movl $L_.str0, (%esp) + calll _printf + movl $L_.str1, (%esp) + calll _puts + movl $L_.str2, (%esp) + calll _puts + xorl %eax, %eax + addl $4, %esp + ret + + .data +L_.str0: # @.str0 + .asciz "Hello " + +L_.str1: # @.str1 + .asciz "World!" + + .align 16 # @.str2 +L_.str2: + .asciz "I'm The Last Line." + +// CHECK: { +// CHECK: MachineType = IMAGE_FILE_MACHINE_I386 (0x14C) +// CHECK: NumberOfSections = 2 +// CHECK: TimeDateStamp = {{[0-9]+}} +// CHECK: PointerToSymbolTable = 0x{{[0-9A-F]+}} +// CHECK: NumberOfSymbols = 7 +// CHECK: SizeOfOptionalHeader = 0 +// CHECK: Characteristics = 0x0 +// CHECK: Sections = [ +// CHECK: 1 = { +// CHECK: Name = .text +// CHECK: VirtualSize = 0 +// CHECK: VirtualAddress = 0 +// CHECK: SizeOfRawData = {{[0-9]+}} +// CHECK: PointerToRawData = 0x{{[0-9A-F]+}} +// CHECK: PointerToRelocations = 0x{{[0-9A-F]+}} +// CHECK: PointerToLineNumbers = 0x0 +// CHECK: NumberOfRelocations = 6 +// CHECK: NumberOfLineNumbers = 0 +// CHECK: Charateristics = 0x60500020 +// CHECK: IMAGE_SCN_CNT_CODE +// CHECK: IMAGE_SCN_ALIGN_16BYTES +// CHECK: IMAGE_SCN_MEM_EXECUTE +// CHECK: IMAGE_SCN_MEM_READ +// CHECK: SectionData = +// CHECK: 83 EC 04 C7 04 24 00 00 - 00 00 E8 00 00 00 00 C7 |.....$..........| +// CHECK: 04 24 07 00 00 00 E8 00 - 00 00 00 C7 04 24 10 00 |.$...........$..| +// CHECK: 00 00 E8 00 00 00 00 31 - C0 83 C4 04 C3 |.......1.....| +// CHECK: Relocations = [ +// CHECK: 0 = { +// CHECK: VirtualAddress = 0x6 +// CHECK: SymbolTableIndex = 2 +// CHECK: Type = IMAGE_REL_I386_DIR32 (6) +// CHECK: SymbolName = .data +// CHECK: } +// CHECK: 1 = { +// CHECK: VirtualAddress = 0xB +// CHECK: SymbolTableIndex = 5 +// CHECK: Type = IMAGE_REL_I386_REL32 (20) +// CHECK: SymbolName = _printf +// CHECK: } +// CHECK: 2 = { +// CHECK: VirtualAddress = 0x12 +// CHECK: SymbolTableIndex = 2 +// CHECK: Type = IMAGE_REL_I386_DIR32 (6) +// CHECK: SymbolName = .data +// CHECK: } +// CHECK: 3 = { +// CHECK: VirtualAddress = 0x17 +// CHECK: SymbolTableIndex = 6 +// CHECK: Type = IMAGE_REL_I386_REL32 (20) +// CHECK: SymbolName = _puts +// CHECK: } +// CHECK: 4 = { +// CHECK: VirtualAddress = 0x1E +// CHECK: SymbolTableIndex = 2 +// CHECK: Type = IMAGE_REL_I386_DIR32 (6) +// CHECK: SymbolName = .data +// CHECK: } +// CHECK: 5 = { +// CHECK: VirtualAddress = 0x23 +// CHECK: SymbolTableIndex = 6 +// CHECK: Type = IMAGE_REL_I386_REL32 (20) +// CHECK: SymbolName = _puts +// CHECK: } +// CHECK: ] +// CHECK: } +// CHECK: 2 = { +// CHECK: Name = .data +// CHECK: VirtualSize = 0 +// CHECK: VirtualAddress = 0 +// CHECK: SizeOfRawData = {{[0-9]+}} +// CHECK: PointerToRawData = 0x{{[0-9A-F]+}} +// CHECK: PointerToRelocations = 0x0 +// CHECK: PointerToLineNumbers = 0x0 +// CHECK: NumberOfRelocations = 0 +// CHECK: NumberOfLineNumbers = 0 +// CHECK: Charateristics = 0xC0500040 +// CHECK: IMAGE_SCN_CNT_INITIALIZED_DATA +// CHECK: IMAGE_SCN_ALIGN_16BYTES +// CHECK: IMAGE_SCN_MEM_READ +// CHECK: IMAGE_SCN_MEM_WRITE +// CHECK: SectionData = +// CHECK: 48 65 6C 6C 6F 20 00 57 - 6F 72 6C 64 21 00 00 00 |Hello .World!...| +// CHECK: 49 27 6D 20 54 68 65 20 - 4C 61 73 74 20 4C 69 6E |I'm The Last Lin| +// CHECK: 65 2E 00 |e..| +// CHECK: Relocations = None +// CHECK: } +// CHECK: ] +// CHECK: Symbols = [ +// CHECK: 0 = { +// CHECK: Name = .text +// CHECK: Value = 0 +// CHECK: SectionNumber = 1 +// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0) +// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0) +// CHECK: StorageClass = IMAGE_SYM_CLASS_STATIC (3) +// CHECK: NumberOfAuxSymbols = 1 +// CHECK: AuxillaryData = +// CHECK: 2D 00 00 00 06 00 00 00 - 00 00 00 00 01 00 00 00 |-...............| +// CHECK: 00 00 |..| + +// CHECK: } +// CHECK: 2 = { +// CHECK: Name = .data +// CHECK: Value = 0 +// CHECK: SectionNumber = 2 +// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0) +// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0) +// CHECK: StorageClass = IMAGE_SYM_CLASS_STATIC (3) +// CHECK: NumberOfAuxSymbols = 1 +// CHECK: AuxillaryData = +// CHECK: 23 00 00 00 00 00 00 00 - 00 00 00 00 02 00 00 00 |#...............| +// CHECK: 00 00 |..| + +// CHECK: } +// CHECK: 4 = { +// CHECK: Name = _main +// CHECK: Value = 0 +// CHECK: SectionNumber = 1 +// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0) +// CHECK: ComplexType = IMAGE_SYM_DTYPE_FUNCTION (2) +// CHECK: StorageClass = IMAGE_SYM_CLASS_EXTERNAL (2) +// CHECK: NumberOfAuxSymbols = 0 +// CHECK: AuxillaryData = + +// CHECK: 5 = { +// CHECK: Name = _printf +// CHECK: Value = 0 +// CHECK: SectionNumber = 0 +// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0) +// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0) +// CHECK: StorageClass = IMAGE_SYM_CLASS_EXTERNAL (2) +// CHECK: NumberOfAuxSymbols = 0 +// CHECK: AuxillaryData = + +// CHECK: } +// CHECK: 6 = { +// CHECK: Name = _puts +// CHECK: Value = 0 +// CHECK: SectionNumber = 0 +// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0) +// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0) +// CHECK: StorageClass = IMAGE_SYM_CLASS_EXTERNAL (2) +// CHECK: NumberOfAuxSymbols = 0 +// CHECK: AuxillaryData = + +// CHECK: } +// CHECK: ] +// CHECK: } diff --git a/test/MC/COFF/weak.s b/test/MC/COFF/weak.s index a240d7152c76..0f99313c9c03 100644 --- a/test/MC/COFF/weak.s +++ b/test/MC/COFF/weak.s @@ -1,51 +1,51 @@ -// This tests that default-null weak symbols (a GNU extension) are created
-// properly via the .weak directive.
-
-// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 < %s | coff-dump.py | FileCheck %s
-
- .def _main;
- .scl 2;
- .type 32;
- .endef
- .text
- .globl _main
- .align 16, 0x90
-_main: # @main
-# BB#0: # %entry
- subl $4, %esp
- movl $_test_weak, %eax
- testl %eax, %eax
- je LBB0_2
-# BB#1: # %if.then
- calll _test_weak
- movl $1, %eax
- addl $4, %esp
- ret
-LBB0_2: # %return
- xorl %eax, %eax
- addl $4, %esp
- ret
-
- .weak _test_weak
-
-// CHECK: Symbols = [
-
-// CHECK: Name = _test_weak
-// CHECK-NEXT: Value = 0
-// CHECK-NEXT: SectionNumber = 0
-// CHECK-NEXT: SimpleType = IMAGE_SYM_TYPE_NULL (0)
-// CHECK-NEXT: ComplexType = IMAGE_SYM_DTYPE_NULL (0)
-// CHECK-NEXT: StorageClass = IMAGE_SYM_CLASS_WEAK_EXTERNAL (105)
-// CHECK-NEXT: NumberOfAuxSymbols = 1
-// CHECK-NEXT: AuxillaryData =
-// CHECK-NEXT: 05 00 00 00 02 00 00 00 - 00 00 00 00 00 00 00 00 |................|
-// CHECK-NEXT: 00 00 |..|
-
-// CHECK: Name = .weak._test_weak.default
-// CHECK-NEXT: Value = 0
-// CHECK-NEXT: SectionNumber = 65535
-// CHECK-NEXT: SimpleType = IMAGE_SYM_TYPE_NULL (0)
-// CHECK-NEXT: ComplexType = IMAGE_SYM_DTYPE_NULL (0)
-// CHECK-NEXT: StorageClass = IMAGE_SYM_CLASS_EXTERNAL (2)
-// CHECK-NEXT: NumberOfAuxSymbols = 0
-// CHECK-NEXT: AuxillaryData =
+// This tests that default-null weak symbols (a GNU extension) are created +// properly via the .weak directive. + +// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 < %s | coff-dump.py | FileCheck %s + + .def _main; + .scl 2; + .type 32; + .endef + .text + .globl _main + .align 16, 0x90 +_main: # @main +# BB#0: # %entry + subl $4, %esp + movl $_test_weak, %eax + testl %eax, %eax + je LBB0_2 +# BB#1: # %if.then + calll _test_weak + movl $1, %eax + addl $4, %esp + ret +LBB0_2: # %return + xorl %eax, %eax + addl $4, %esp + ret + + .weak _test_weak + +// CHECK: Symbols = [ + +// CHECK: Name = _test_weak +// CHECK-NEXT: Value = 0 +// CHECK-NEXT: SectionNumber = 0 +// CHECK-NEXT: SimpleType = IMAGE_SYM_TYPE_NULL (0) +// CHECK-NEXT: ComplexType = IMAGE_SYM_DTYPE_NULL (0) +// CHECK-NEXT: StorageClass = IMAGE_SYM_CLASS_WEAK_EXTERNAL (105) +// CHECK-NEXT: NumberOfAuxSymbols = 1 +// CHECK-NEXT: AuxillaryData = +// CHECK-NEXT: 05 00 00 00 02 00 00 00 - 00 00 00 00 00 00 00 00 |................| +// CHECK-NEXT: 00 00 |..| + +// CHECK: Name = .weak._test_weak.default +// CHECK-NEXT: Value = 0 +// CHECK-NEXT: SectionNumber = 65535 +// CHECK-NEXT: SimpleType = IMAGE_SYM_TYPE_NULL (0) +// CHECK-NEXT: ComplexType = IMAGE_SYM_DTYPE_NULL (0) +// CHECK-NEXT: StorageClass = IMAGE_SYM_CLASS_EXTERNAL (2) +// CHECK-NEXT: NumberOfAuxSymbols = 0 +// CHECK-NEXT: AuxillaryData = diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 0f6aeb7052b9..ade29525937d 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -1,7 +1,16 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s +# CHECK: addpl r4, pc, #19, #8 +0x4c 0x45 0x8f 0x52 + # CHECK: b #0 -0xfe 0xff 0xff 0xea +0x00 0x00 0x00 0xea + +# CHECK: bl #7732 +0x8d 0x07 0x00 0xeb + +# CHECK: bleq #-4 +0xff 0xff 0xff 0x0b # CHECK: bfc r8, #0, #16 0x1f 0x80 0xcf 0xe7 @@ -12,6 +21,12 @@ # CHECK: mov pc, lr 0x0e 0xf0 0xa0 0xe1 +# CHECK: mov pc, #255, #2 +0xff 0xf1 0xa0 0xe3 + +# CHECK: movw r7, #4096 +0x00 0x70 0x01 0xe3 + # CHECK: cmn r0, #1 0x01 0x00 0x70 0xe3 @@ -36,6 +51,9 @@ # CHECK: ldr r0, [r2], #15 0x0f 0x00 0x92 0xe4 +# CHECK: ldr r5, [r7, -r10, lsl #2] +0x0a 0x51 0x17 0xe7 + # CHECK: ldrh r0, [r2], #0 0xb0 0x00 0xd2 0xe0 @@ -54,7 +72,7 @@ # CHECK: movt r8, #65535 0xff 0x8f 0x4f 0xe3 -# CHECK: mvnspl r7, #245, 2 +# CHECK: mvnspl r7, #245, #2 0xf5 0x71 0xf0 0x53 # CHECK-NOT: orr r7, r8, r7, rrx #0 @@ -64,9 +82,12 @@ # CHECK: pkhbt r8, r9, r10, lsl #4 0x1a 0x82 0x89 0xe6 -# CHECK-NOT: pkhbtls pc, r11, r11, lsl #0 -# CHECK: pkhbtls pc, r11, r11 -0x1b 0xf0 0x8b 0x96 +# CHECK-NOT: pkhbtls r10, r11, r11, lsl #0 +# CHECK: pkhbtls r10, r11, r11 +0x1b 0xa0 0x8b 0x96 + +# CHECK: pkhtbmi lr, r1, r6, asr #21 +0xd6 0xea 0x81 0x46 # CHECK: pop {r0, r2, r4, r6, r8, r10} 0x55 0x05 0xbd 0xe8 @@ -130,3 +151,136 @@ # CHECK: msr cpsr_fc, r0 0x00 0xf0 0x29 0xe1 + +# CHECK: msrmi cpsr_c, #241, #8 +0xf1 0xf4 0x21 0x43 + +# CHECK: rsbs r6, r7, r8 +0x08 0x60 0x77 0xe0 + +# CHECK: blxeq r5 +0x35 0xff 0x2f 0x01 + +# CHECK: bx r12 +0x1c 0xff 0x2f 0xe1 + +# CHECK: uqadd16mi r6, r11, r8 +0x18 0x60 0x6b 0x46 + +# CHECK: str r0, [sp, #4] +0x04 0x00 0x8d 0xe5 + +# CHECK: str r1, [sp] +0x00 0x10 0x8d 0xe5 + +# CHECK: ldr r3, [pc, #144] +0x90 0x30 0x9f 0xe5 + +# CHECK: ldr r3, [r0, #-4] +0x4 0x30 0x10 0xe5 + +# CHECK: ldr r5, [sp, r0, lsl #1]! +0x80 0x50 0xbd 0xe7 + +# CHECK: ldr r5, [r7], -r0, lsr #2 +0x20 0x51 0x17 0xe6 + +# CHECK: strdeq r2, r3, [r0], -r8 +0xf8 0x24 0x00 0x00 + +# CHECK: ldrdeq r2, r3, [r0], -r12 +0xdc 0x24 0x00 0x00 + +# CHECK: ldrbt r3, [r4], -r5, lsl #12 +0x05 0x36 0x74 0xe6 + +# CHECK: vcmpe.f64 d8, #0 +0xc0 0x8b 0xb5 0xee + +# CHECK: vldmdb r2!, {s7, s8, s9, s10, s11} +0x05 0x3a 0x72 0xed + +# CHECK: vldr.32 s23, [r2, #660] +0xa5 0xba 0xd2 0xed + +# CHECK: strtvc r5, [r3], r0, lsr #20 +0x20 0x5a 0xa3 0x76 + +# CHECK: stmiblo sp, {r0, r4, r8, r11, r12, pc} +0x11 0x99 0x8d 0x39 + +# CHECK: ldmdb sp, {r0, r4, r8, r11, r12, pc} +0x11 0x99 0x1d 0xe9 + +# CHECK: swpge r3, r2, [r6] +0x92 0x30 0x06 0xa1 + +# CHECK: umull r1, r2, r3, r4 +0x93 0x14 0x82 0xe0 + +# CHECK: pld [pc, #-0] +0x00 0xf0 0x1f 0xf5 + +# CHECK: pli [pc, #-0] +0x00 0xf0 0x5f 0xf4 + +# CHECK: pli [r3, r1, lsl #2] +0x01 0xf1 0xd3 0xf6 + +# CHECK: stc p2, cr4, [r9], {157} +0x9d 0x42 0x89 0xec + +# CHECK: stc2 p2, cr4, [r9], {157} +0x9d 0x42 0x89 0xfc + +# CHECK: blx #60 +0x0f 0x00 0x00 0xfa + +# CHECK-NOT: adcs r10, r8, r0, asr #6 +# CHECK: adcshi r10, r8, r0, asr #6 +0x40 0xa3 0xb8 0x80 + +# CHECK: adcshi r10, r8, r0, asr r3 +0x50 0xa3 0xb8 0x80 + +# CHECK: streq r1, [sp], #-1567 +0x1f 0x16 0xd 0x4 + +# CHECK: mrchs p2, #3, r11, c13, c6, #6 +0xd6 0xb2 0x7d 0x2e + +# CHECK: smlsldx r4, r12, r11, r4 +0x7b 0x44 0x4c 0xe7 + +# CHECK: lsl r3, r2, r1 +0x12 0x31 0xa0 0xe1 + +# CHECK: sxtab r9, r8, r5 +0x75 0x90 0xa8 0xe6 + +# CHECK: sxtb r9, r5, ror #8 +0x75 0x94 0xaf 0xe6 + +# CHECK: bfc r5, #0, #16 +0x1f 0x50 0xcf 0xe7 + +# CHECK: bfi r5, r6, #0, #16 +0x16 0x50 0xcf 0xe7 + +# CHECK: sbfx r5, r6, #8, #8 +0x56 0x54 0xa7 0xe7 + +# CHECK: rsb pc, r5, r0 +0x00 0xf0 0x65 0xe0 + +# CHECK: uqadd8 r5, r6, r7 +0x97 0x5f 0x66 0xe6 + +# CHECK: uqsax r5, r6, r7 +0x57 0x5f 0x66 0xe6 + +# CHECK: smmlareq r0, r0, r0, r0 +0x30 0x00 0x50 0x07 + +# CHECK: nop +0x00 0xf0 0x20 0xe3 diff --git a/test/MC/Disassembler/ARM/invalid-BFI-arm.txt b/test/MC/Disassembler/ARM/invalid-BFI-arm.txt new file mode 100644 index 000000000000..ca0c1abb77b7 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-BFI-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=60 Name=BFI Format=ARM_FORMAT_DPFRM(4) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 1| 0: 1: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# if d == 15 then UNPREDICTABLE; +0x16 0xf0 0xcf 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt b/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt new file mode 100644 index 000000000000..66c43c219780 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if cond = '1110' then UNDEFINED +0x6f 0xde diff --git a/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt new file mode 100644 index 000000000000..10748e9b1269 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt @@ -0,0 +1,4 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# invalid imod value (0b01) +0xc0 0x67 0x4 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt new file mode 100644 index 000000000000..5202217b6a71 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt @@ -0,0 +1,4 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# invalid (imod, M, iflags) combination +0x93 0x1c 0x02 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt b/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt new file mode 100644 index 000000000000..0a4be6826ccd --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt @@ -0,0 +1,16 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1908 Name=t2DMB Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1| +# ------------------------------------------------------------------------------------------------- +# +# Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST. +# Reject invalid encodings. +# +# See also A8.6.42 DSB +# All other encodings of option are reserved. It is IMPLEMENTATION DEFINED whether options +# other than SY are implemented. All unsupported and reserved options must execute as a full +# system DSB operation, but software must not rely on this behavior. +0xbf 0xf3 0x51 0x8f diff --git a/test/MC/Disassembler/ARM/invalid-DSB-arm.txt b/test/MC/Disassembler/ARM/invalid-DSB-arm.txt new file mode 100644 index 000000000000..afa2baff615d --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-DSB-arm.txt @@ -0,0 +1,16 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=102 Name=DSB Format=ARM_FORMAT_MISCFRM(26) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 1: 0: 1| 0: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST. +# Reject invalid encodings. +# +# See also A8.6.42 DSB +# All other encodings of option are reserved. It is IMPLEMENTATION DEFINED whether options +# other than SY are implemented. All unsupported and reserved options must execute as a full +# system DSB operation, but software must not rely on this behavior. +0x40 0xf0 0x7f 0xf5 diff --git a/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt b/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt new file mode 100644 index 000000000000..b966a9d773c2 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 0: 1| 1: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 1: 0: 1: 1| 0: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# The bytes have 0b0000 for P,U,D,W; from A8.6.51, it is undefined. +0x92 0xb4 0x1f 0xdc + diff --git a/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt new file mode 100644 index 000000000000..7a35c2d6ce0f --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 0: 1| 0: 1: 1: 1| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 0: 1| +# ------------------------------------------------------------------------------------------------- +# +# if wback && (n == 15 || n == t) then UNPREDICTABLE +0x05 0x70 0xd7 0xe6 diff --git a/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt b/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt new file mode 100644 index 000000000000..da2e6bed8615 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.66 LDRD (immediate) +# if Rn = '1111' then SEE LDRD (literal) +# A8.6.67 LDRD (literal) +# Inst{21} = 0 +0xff 0xe9 0x0 0xeb diff --git a/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt new file mode 100644 index 000000000000..fb2ce20d2c91 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 0| 0: 0: 1: 1| 0: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# The bytes have Inst{4} = 1, so it's not an LDRT Encoding A2 instruction. +0x10 0x51 0x37 0xe6 + + diff --git a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt new file mode 100644 index 000000000000..ad79986b2549 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt @@ -0,0 +1,4 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# LDR_PRE/POST has encoding Inst{4} = 0. +0xde 0x69 0x18 0x46 diff --git a/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt new file mode 100644 index 000000000000..36c1124bced5 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if m == 15 then UNPREDICTABLE +0x8f 0x60 0xb7 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt new file mode 100644 index 000000000000..23a0b85f3615 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt @@ -0,0 +1,4 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# LDR (register) has encoding Inst{4} = 0. +0xba 0xae 0x9f 0x57 diff --git a/test/MC/Disassembler/ARM/invalid-LSL-regform.txt b/test/MC/Disassembler/ARM/invalid-LSL-regform.txt new file mode 100644 index 000000000000..20293ada7983 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LSL-regform.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.89 LSL (register) +# if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; +0x12 0xf1 0xa0 0xe1 diff --git a/test/MC/Disassembler/ARM/invalid-MCR-arm.txt b/test/MC/Disassembler/ARM/invalid-MCR-arm.txt new file mode 100644 index 000000000000..d39b9c1d608e --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-MCR-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# Encoding error: coproc == 10 or 11 for MCR[R]/MR[R]C +0x1b 0x1b 0xa0 0x2e diff --git a/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt new file mode 100644 index 000000000000..0b8a0776cc41 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=185 Name=MOVTi16 Format=ARM_FORMAT_DPFRM(4) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# if d == 15 then UNPREDICTABLE +0x00 0xf0 0x41 0xe3 diff --git a/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt new file mode 100644 index 000000000000..f82d3cb0b10f --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100. +# The instruction is UNPREDICTABLE, and is not a valid intruction. +# +# See also +# A8.6.97 MOV (register) +0x2 0xd0 0xbc 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt new file mode 100644 index 000000000000..3165ff794f97 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 0: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 1| 0: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# A8.6.89 LSL (register): Inst{7-4} = 0b0001 +0x93 0x42 0xa0 0xd1 diff --git a/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt new file mode 100644 index 000000000000..cfbba43fd514 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100. +# The instruction is UNPREDICTABLE, and is not a valid intruction. +# +# See also +# A8.6.88 LSL (immediate) +# A8.6.98 MOV (shifted register), and +# I.1 Instruction encoding diagrams and pseudocode +0x2 0xd1 0xbc 0xf1 + + diff --git a/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt b/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt new file mode 100644 index 000000000000..e9d5deb04349 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate) +# The hints instructions have more specific encodings, so if mask == 0, +# we should reject this as an invalid instruction. +0xa7 0xf1 0x20 0x3 diff --git a/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt b/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt new file mode 100644 index 000000000000..1fdfa8299c78 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 0: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 0: 0: 1: 1| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# B6.1.8 RFE has Inst{15-0} as 0x0a00 ==> Not an RFE instruction +# A8.6.53 LDM/LDMIA/LDMFD is predicated with Inst{31-28} as cond ==> Not an LDMIA instruction +0x32 0xb1 0x99 0xf8 diff --git a/test/MC/Disassembler/ARM/invalid-RSC-arm.txt b/test/MC/Disassembler/ARM/invalid-RSC-arm.txt new file mode 100644 index 000000000000..e7992ae6342e --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-RSC-arm.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 1: 1| 0: 0: 0: 0| 1: 1: 1: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE; +0x5f 0xf8 0xe4 0x30 diff --git a/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt b/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt new file mode 100644 index 000000000000..1ecd87df07c2 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=271 Name=SBFX Format=ARM_FORMAT_DPFRM(4) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 0| 0: 1: 1: 1| 0: 1: 0: 1| 0: 1: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if d == 15 || n == 15 then UNPREDICTABLE; +0x5f 0x54 0xa7 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt b/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt new file mode 100644 index 000000000000..c3dcf83fbd21 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 0: 0: 1| 0: 1: 1: 1| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 1: 0| 1: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.167 +# if d == 15 || n == 15 | m == 15 then UNPREDICTABLE +0x1b 0x68 0xf 0x97 diff --git a/test/MC/Disassembler/ARM/invalid-SRS-arm.txt b/test/MC/Disassembler/ARM/invalid-SRS-arm.txt new file mode 100644 index 000000000000..fdca9f9eaec6 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-SRS-arm.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 0| 0: 1: 0: 1| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 0| 0: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# Unknown format +# +# B6.1.10 SRS +# Inst{19-8} = 0xd05 +# Inst{7-5} = 0b000 +0x83 0x1c 0xc5 0xf8 diff --git a/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt b/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt new file mode 100644 index 000000000000..9cc8351b781f --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=322 Name=SSAT Format=ARM_FORMAT_SATFRM(13) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.183 SSAT +# if d == 15 || n == 15 then UNPREDICTABLE; +0x1a 0xf4 0xa0 0xe6 diff --git a/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt new file mode 100644 index 000000000000..0000c60ce4b8 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# if BitCount(registers) < 1 then UNPREDICTABLE +0x00 0xc7 diff --git a/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt b/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt new file mode 100644 index 000000000000..5209323fa847 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=355 Name=STRBrs Format=ARM_FORMAT_STFRM(7) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# if t == 15 then UNPREDICTABLE +0x00 0xf0 0xcf 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt b/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt new file mode 100644 index 000000000000..4ec681daf954 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 1: 0: 0| 0: 1: 1: 1| 0: 1: 0: 1| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.223 SXTB +# if d == 15 || m == 15 then UNPREDICTABLE; +0x75 0xf4 0xaf 0xe6 diff --git a/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt b/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt new file mode 100644 index 000000000000..7a3ef3328aa6 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.244 UMAAL +# if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; +0x98 0xbf 0x4f 0xf0 diff --git a/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt b/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt new file mode 100644 index 000000000000..d3f508a1dabd --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=426 Name=UQADD8 Format=ARM_FORMAT_DPFRM(4) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 0| 0: 1: 1: 0| 0: 1: 1: 0| 0: 1: 0: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# DPFrm with bad reg specifier(s) +# +# if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; +0x9f 0x5f 0x66 0xe6 diff --git a/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt new file mode 100644 index 000000000000..56d9ad704a01 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| 1: 1: 0: 0| 0: 0: 1: 1| 1: 1: 0: 1| +# ------------------------------------------------------------------------------------------------- +# +# 'a' == 1 and data_size == 8 is invalid +0x3d 0x3c 0xa0 0xf4 diff --git a/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt new file mode 100644 index 000000000000..5fd02517991a --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 1: 0| 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 0: 1| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.315 VLD3 (single 3-element structure to all lanes) +# The a bit must be encoded as 0. +0xa2 0xf9 0x92 0x2e diff --git a/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt new file mode 100644 index 000000000000..887b983eddb3 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt @@ -0,0 +1,4 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# core registers out of range +0xa5 0xba 0x72 0xed diff --git a/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt b/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt new file mode 100644 index 000000000000..eed012b0be60 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 1: 0| 0: 1: 0: 0| 0: 0: 0: 0| 1: 1: 1: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# Qm -> bit[0] == 0, otherwise UNDEFINED +0xdb 0xe0 0x40 0xf2 diff --git a/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt new file mode 100644 index 000000000000..506250c3bc2a --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.393 VST2 (multiple 2-element structures) +# type == '1001' and align == '11' ==> UNDEFINED +0xb3 0x9 0x3 0xf4 diff --git a/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt new file mode 100644 index 000000000000..d0bc51ebaf39 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.16 B +# if cond<3:1> == '111' then SEE "Related Encodings" +0xaf 0xf7 0x44 0x8b diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt new file mode 100644 index 000000000000..9befbd6b6fba --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# The unpriviledged Load/Store cannot have SP or PC as Rt. +0x10 0xf8 0x3 0xfe diff --git a/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt new file mode 100644 index 000000000000..598efd1bc7c6 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1934 Name=t2LDREXD Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 1| 0: 0: 1: 0| 1: 0: 0: 0| 1: 0: 0: 0| 0: 1: 1: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if t == t2 then UNPREDICTABLE +0xd2 0xe8 0x7f 0x88 diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt new file mode 100644 index 000000000000..a501eb9cd541 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if Rt = '1111' then SEE "Unallocated memory hints" +0xb3 0xf9 0xdf 0xf8 diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt new file mode 100644 index 000000000000..f886a6f074b1 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 1: 1| 0: 1: 0: 1| 1: 1: 1: 1| 1: 1: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# if Rt == '1111' and PUW == '100' then SEE "Unallocated memory hints" +0x35 0xf9 0x00 0xfc diff --git a/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt new file mode 100644 index 000000000000..c8f8ec294ec1 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=2124 Name=t2STRD_PRE Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 0| 0: 1: 0: 0| 0: 1: 0: 0| 0: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# if wback && (n == t || n == t2) then UNPREDICTABLE +0xe4 0xe9 0x02 0x46 diff --git a/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt new file mode 100644 index 000000000000..35ea6511647f --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=2127 Name=t2STREXB Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# if d == n || d == t then UNPREDICTABLE +0xc2 0xe8 0x42 0x8f diff --git a/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt new file mode 100644 index 000000000000..9b0cf24ffb16 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=2128 Name=t2STREXD Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 0: 1: 1: 1| 1: 0: 0: 0| 0: 1: 1: 1| 1: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# if d == n || d == t || d == t2 then UNPREDICTABLE +mc-input.txt:1:1: warning: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt new file mode 100644 index 000000000000..129a2704d5c5 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if Rn == '1111' then UNDEFINED +0x4f 0xf8 0xff 0xeb diff --git a/test/MC/Disassembler/ARM/neon-tests.txt b/test/MC/Disassembler/ARM/neon-tests.txt index eb9adb7b6c2f..cfb5949284ce 100644 --- a/test/MC/Disassembler/ARM/neon-tests.txt +++ b/test/MC/Disassembler/ARM/neon-tests.txt @@ -21,6 +21,12 @@ # CHECK: vld4.8 {d4, d6, d8, d10}, [r2] 0x0f 0x41 0x22 0xf4 +# CHECK: vld1.32 {d3[], d4[]}, [r0, :32]! +0xbd 0x3c 0xa0 0xf4 + +# CHECK: vld4.16 {d3[], d4[], d5[], d6[]}, [r0, :64]! +0x7d 0x3f 0xa0 0xf4 + # CHECK: vmov d0, d15 0x1f 0x01 0x2f 0xf2 @@ -59,3 +65,27 @@ # CHECK: vmov.f64 d0, #5.000000e-01 0x00 0x0b 0xb6 0xee + +# CHECK: vpop {d8} +0x02 0x8b 0xbd 0xec + +# CHECK: vorr.i32 q15, #0x4F0000 +0x5f 0xe5 0xc4 0xf2 + +# CHECK: vbic.i32 q2, #0xA900 +0x79 0x43 0x82 0xf3 + +# CHECK: vst2.32 {d16, d18}, [r2, :64], r2 +0x92 0x9 0x42 0xf4 + +# CHECK: vmov.s8 r0, d8[1] +0x30 0x0b 0x58 0xee + +# CHECK: vmov r1, r0, d11 +0x1b 0x1b 0x50 0xec + +# CHECK: usada8mi r8, r9, r5, r9 +0x19 0x95 0x88 0x47 + +# CHECK: vext.8 q4, q2, q1, #4 +0x42 0x84 0xb4 0xf2 diff --git a/test/MC/Disassembler/ARM/thumb-printf.txt b/test/MC/Disassembler/ARM/thumb-printf.txt new file mode 100644 index 000000000000..6c2c500630d5 --- /dev/null +++ b/test/MC/Disassembler/ARM/thumb-printf.txt @@ -0,0 +1,77 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 | FileCheck %s + +# CHECK: push {r0, r1, r2, r3} +# CHECK-NEXT: push {r4, r5, r7, lr} +# CHECK-NEXT: add r7, sp, #8 +# CHECK-NEXT: sub sp, #4 +# CHECK-NEXT: add r3, sp, #20 +# CHECK-NEXT: ldr r5, [r3], #4 +# CHECK-NEXT: str r3, [sp] +# CHECK-NEXT: ldr r3, #52 +# CHECK-NEXT: add r3, pc +# CHECK-NEXT: ldr r0, [r3] +# CHECK-NEXT: ldr r4, [r0] +# CHECK-NEXT: ldr r0, #48 +# CHECK-NEXT: add r0, pc +# CHECK-NEXT: ldr r0, [r0] +# CHECK-NEXT: ldr r0, [r0] +# CHECK-NEXT: blx #191548 +# CHECK-NEXT: cbnz r0, #6 +# CHECK-NEXT: ldr r1, #40 +# CHECK-NEXT: add r1, pc +# CHECK-NEXT: ldr r1, [r1] +# CHECK-NEXT: b #0 +# CHECK-NEXT: mov r1, r0 +# CHECK-NEXT: mov r0, r4 +# CHECK-NEXT: mov r2, r5 +# CHECK-NEXT: ldr r3, [sp] +# CHECK-NEXT: bl #-8390 +# Data bytes (corresponds to an invalid instruction) +# But not: sub.w sp, r7, #8 +# CHECK-NEXT: pop.w {r4, r5, r7, lr} +# CHECK-NEXT: add sp, #16 +# CHECK-NEXT: bx lr +# CHECK-NEXT: nop +# CHECK-NEXT: movs r3, #142 +# CHECK-NEXT: movs r5, r0 +# CHECK-NEXT: adds r1, #122 +# CHECK-NEXT: movs r5, r0 +# CHECK-NEXT: adds r1, #104 +# CHECK-NEXT: movs r5, r0 +0x0f 0xb4 +0xb0 0xb5 +0x02 0xaf +0x81 0xb0 +0x05 0xab +0x53 0xf8 0x04 0x5b +0x00 0x93 +0x0d 0x4b +0x7b 0x44 +0x18 0x68 +0x04 0x68 +0x0c 0x48 +0x78 0x44 +0x00 0x68 +0x00 0x68 +0x2e 0xf0 0x1e 0xee +0x18 0xb9 +0x0a 0x49 +0x79 0x44 +0x09 0x68 +0x00 0xe0 +0x01 0x46 +0x20 0x46 +0x2a 0x46 +0x00 0x9b +0xfd 0xf7 0x9d 0xff +# 0xa7 0xf1 0x08 0x0d +0xbd 0xe8 0xb0 0x40 +0x04 0xb0 +0x70 0x47 +0x00 0xbf +0x8e 0x23 +0x05 0x00 +0x7a 0x31 +0x05 0x00 +0x68 0x31 +0x05 0x00 diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt index 6dab1237a118..774dbe4b42e5 100644 --- a/test/MC/Disassembler/ARM/thumb-tests.txt +++ b/test/MC/Disassembler/ARM/thumb-tests.txt @@ -6,11 +6,14 @@ # CHECK: adcs r0, r0, #1 0x50 0xf1 0x01 0x00 -# CHECK: b #34 +# CHECK: b #30 0x0f 0xe0 -# CHECK: b.w #-12 -0xff 0xf7 0xf8 0xaf +# CHECK: bgt.w #-16 +0x3f 0xf7 0xf8 0xaf + +# CHECK: bfc r0, #10, #10 +0x6f 0xf3 0x93 0x20 # CHECK: bfi r2, r10, #0, #1 0x6a 0xf3 0x00 0x02 @@ -27,14 +30,26 @@ # CHECK: ldmia r0!, {r1} 0x02 0xc8 +# CHECK: ldr r5, #432 +0x6c 0x4d + +# CHECK: str r0, [r3] +0x18 0x60 + +# CHECK: str r0, [r3, #4] +0x58 0x60 + +# CHECK: str r2, [r5, r3] +0xea 0x50 + # CHECK: ldrb.w r8, #-24 0x1f 0xf8 0x18 0x80 # CHECK: ldrd r0, r1, [r7, #64]! 0xf7 0xe9 0x10 0x01 -# CHECK: lsls.w r0, pc, #1 -0x5f 0xea 0x4f 0x00 +# CHECK: lsls.w r0, r5, #1 +0x5f 0xea 0x45 0x00 # CHECK: mov r11, r7 0xbb 0x46 @@ -118,3 +133,132 @@ # CHECK: msr cpsr_fc, r0 0x80 0xf3 0x00 0x89 + +# CHECK: blx #-4 +0xff 0xf7 0xfe 0xef + +# CHECK: vpush {d8, d9, d10} +0x2d 0xed 0x06 0x8b + +# CHECK: vcmpe.f64 d8, #0 +0xb5 0xee 0xc0 0x8b + +# CHECK: stmdb.w sp, {r0, r2, r3, r8, r11, lr} +0x0d 0xe9 0x0d 0x49 + +# CHECK: stmia r5!, {r0, r1, r2, r3, r4} +0x1f 0xc5 + +# CHECK: ldmia r5, {r0, r1, r2, r3, r4, r5} +0x3f 0xcd + +# CHECK: ldmia r5!, {r0, r1, r2, r3, r4} +0x1f 0xcd + +# CHECK: addw r0, pc, #1050 +0x0f 0xf2 0x1a 0x40 + +# CHECK: ldrd r3, r8, [r11, #-60] +0x5b 0xe9 0x0f 0x38 + +# CHECK: ldrex r8, [r2] +0x52 0xe8 0x00 0x8f + +# CHECK: ldrexd r8, r9, [r2] +0xd2 0xe8 0x7f 0x89 + +# CHECK: strexd r1, r7, r8, [r2] +0xc2 0xe8 0x71 0x78 + +# CHECK: tbh [r5, r4, lsl #1] +0xd5 0xe8 0x14 0xf0 + +# CHECK: tbb [r5, r4] +0xd5 0xe8 0x04 0xf0 + +# CHECK: ldr.w r4, [sp, r4, lsl #3] +0x5d 0xf8 0x34 0x40 + +# CHECK: ldr.w r5, [r6, #30] +0xd6 0xf8 0x1e 0x50 + +# CHECK: ldrh.w r5, [r6, #30] +0xb6 0xf8 0x1e 0x50 + +# CHECK: ldrt r5, [r6, #30] +0x56 0xf8 0x1e 0x5e + +# CHECK: ldr r5, [r6, #-30] +0x56 0xf8 0x1e 0x5c + +# CHECK: sel r7, r3, r5 +0xa3 0xfa 0x85 0xf7 + +# CHECK: lsl.w r7, r3, r5 +0x03 0xfa 0x05 0xf7 + +# CHECK: adds.w r7, r3, r5 +0x13 0xeb 0x05 0x07 + +# CHECK: smlabt r4, r3, r2, r1 +0x13 0xfb 0x12 0x14 + +# CHECK: smmulr r7, r8, r9 +0x58 0xfb 0x19 0xf7 + +# CHECK: umull r1, r2, r3, r4 +0xa3 0xfb 0x04 0x12 + +# CHECK: pld [r5, r0, lsl #1] +0x15 0xf8 0x10 0xf0 + +# CHECK: pld [pc, #-16] +0x1f 0xf8 0x10 0xf0 + +# CHECK: pld [r5, #30] +0x95 0xf8 0x1e 0xf0 + +# CHECK: stc2 p12, cr15, [r9], {137} +0x89 0xfc 0x89 0xfc + +# CHECK: vmov r1, r0, d11 +0x50 0xec 0x1b 0x1b + +# CHECK: dsb nsh +0xbf 0xf3 0x47 0x8f + +# CHECK: isb +0xbf 0xf3 0x6f 0x8f + +# CHECK: asrs r1, r0, #32 +0x1 0x10 + +# CHECK: lsr.w r10, r0, #32 +0x4f 0xea 0x10 0x0a + +# CHECK: blx sp +0xe8 0x47 + +# CHECK: bx lr +0x70 0x47 + +# CHECK: bx pc +0x78 0x47 + +# CHECK: svc #230 +0xe6 0xdf + +# CHECK: rfedb lr +0x1e 0xe8 0x00 0xc0 + +# CHECK: mov.w r3, #4294967295 +0x4f 0xf0 0xff 0x33 + +# CHECK: mov pc, sp +0xef 0x46 + +# CHECK: nop +0x00 0xbf + +# CHECK: nop.w +0xaf 0xf3 0x00 0x80 diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt index 13a19d2ca4c3..08fb4c55b385 100644 --- a/test/MC/Disassembler/X86/simple-tests.txt +++ b/test/MC/Disassembler/X86/simple-tests.txt @@ -66,3 +66,9 @@ # CHECK: movw $47416, -66(%rbp) 0x66 0xc7 0x45 0xbe 0x38 0xb9 + +# CHECK: vaddpd %ymm13, %ymm1, %ymm0 +0xc4 0xc1 0x75 0x58 0xc5 + +# CHECK: vaddps %ymm3, %ymm1, %ymm0 +0xc5 0xf4 0x58 0xc3 diff --git a/test/MC/ELF/alias-reloc.s b/test/MC/ELF/alias-reloc.s index c908c12404d5..67266d652064 100644 --- a/test/MC/ELF/alias-reloc.s +++ b/test/MC/ELF/alias-reloc.s @@ -17,6 +17,20 @@ foo2: .set bar2,foo2 .quad bar2 +// CHECK: # Relocation 0x00000000 +// CHECK-NEXT: (('r_offset', 0x00000001) +// CHECK-NEXT: ('r_sym', 0x00000001) +// CHECK-NEXT: ('r_type', 0x00000004) +// CHECK-NEXT: ('r_addend', 0xfffffffc) +// CHECK-NEXT: ), + +// CHECK: # Relocation 0x00000001 +// CHECK-NEXT: (('r_offset', 0x00000005) +// CHECK-NEXT: ('r_sym', 0x00000006) +// CHECK-NEXT: ('r_type', 0x00000001) +// CHECK-NEXT: ('r_addend', 0x00000000) +// CHECK-NEXT: ), + // CHECK: # Symbol 0x00000001 // CHECK-NEXT: (('st_name', 0x00000005) # 'bar' // CHECK-NEXT: ('st_bind', 0x00000000) @@ -36,17 +50,3 @@ foo2: // CHECK-NEXT: ('st_value', 0x0000000000000005) // CHECK-NEXT: ('st_size', 0x0000000000000000) // CHECK-NEXT: ), - -// CHECK: # Relocation 0x00000000 -// CHECK-NEXT: (('r_offset', 0x00000001) -// CHECK-NEXT: ('r_sym', 0x00000001) -// CHECK-NEXT: ('r_type', 0x00000004) -// CHECK-NEXT: ('r_addend', 0xfffffffc) -// CHECK-NEXT: ), - -// CHECK: # Relocation 0x00000001 -// CHECK-NEXT: (('r_offset', 0x00000005) -// CHECK-NEXT: ('r_sym', 0x00000006) -// CHECK-NEXT: ('r_type', 0x00000001) -// CHECK-NEXT: ('r_addend', 0x00000000) -// CHECK-NEXT: ), diff --git a/test/MC/ELF/align-bss.s b/test/MC/ELF/align-bss.s index 4f73a29f8e2d..ca6da9184e8e 100644 --- a/test/MC/ELF/align-bss.s +++ b/test/MC/ELF/align-bss.s @@ -5,7 +5,7 @@ .local foo .comm foo,2048,16 -// CHECK: ('sh_name', 0x0000000d) # '.bss' +// CHECK: ('sh_name', 0x00000007) # '.bss' // CHECK-NEXT: ('sh_type', 0x00000008) // CHECK-NEXT: ('sh_flags', 0x00000003) // CHECK-NEXT: ('sh_addr', 0x00000000) diff --git a/test/MC/ELF/align-nops.s b/test/MC/ELF/align-nops.s index 28d4b895f5d9..d29cb5b5e316 100644 --- a/test/MC/ELF/align-nops.s +++ b/test/MC/ELF/align-nops.s @@ -27,7 +27,7 @@ f0: // CHECK-NEXT: ('sh_entsize', 0x00000000) // CHECK-NEXT: ('_section_data', '00000000 0f1f4000 00000000 0f1f4000') -// CHECK: (('sh_name', 0x00000007) # '.data' +// CHECK: (('sh_name', 0x00000026) # '.data' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000003) // CHECK-NEXT: ('sh_addr', diff --git a/test/MC/ELF/align.s b/test/MC/ELF/align.s index c3912a7c67b0..c1e7086b8e60 100644 --- a/test/MC/ELF/align.s +++ b/test/MC/ELF/align.s @@ -8,7 +8,7 @@ .align 8 // CHECK: # Section 0x00000003 -// CHECK-NEXT: (('sh_name', 0x0000000d) # '.bss' +// CHECK-NEXT: (('sh_name', 0x00000007) # '.bss' // CHECK-NEXT: ('sh_type', 0x00000008) // CHECK-NEXT: ('sh_flags', 0x00000003) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -20,7 +20,7 @@ // CHECK-NEXT: ('sh_entsize', 0x00000000) // CHECK-NEXT: ), // CHECK-NEXT: # Section 0x00000004 -// CHECK-NEXT: (('sh_name', 0x00000012) # '.rodata' +// CHECK-NEXT: (('sh_name', 0x00000026) # '.rodata' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000002) // CHECK-NEXT: ('sh_addr', 0x00000000) diff --git a/test/MC/ELF/basic-elf-32.s b/test/MC/ELF/basic-elf-32.s index fa97da44d422..7c2927ad79b5 100644 --- a/test/MC/ELF/basic-elf-32.s +++ b/test/MC/ELF/basic-elf-32.s @@ -39,23 +39,6 @@ main: # @main // CHECK: # '.text' -// CHECK: ('st_bind', 0x00000000) -// CHECK: ('st_type', 0x00000003) - -// CHECK: ('st_bind', 0x00000000) -// CHECK: ('st_type', 0x00000003) - -// CHECK: ('st_bind', 0x00000000) -// CHECK: ('st_type', 0x00000003) - -// CHECK: # 'main' -// CHECK: ('st_bind', 0x00000001) -// CHECK-NEXT: ('st_type', 0x00000002) - -// CHECK: # 'puts' -// CHECK: ('st_bind', 0x00000001) -// CHECK-NEXT: ('st_type', 0x00000000) - // CHECK: # '.rel.text' // CHECK: ('_relocations', [ @@ -76,3 +59,20 @@ main: # @main // CHECK: ('r_type', 0x00000002) // CHECK: ), // CHECK: ]) + +// CHECK: ('st_bind', 0x00000000) +// CHECK: ('st_type', 0x00000003) + +// CHECK: ('st_bind', 0x00000000) +// CHECK: ('st_type', 0x00000003) + +// CHECK: ('st_bind', 0x00000000) +// CHECK: ('st_type', 0x00000003) + +// CHECK: # 'main' +// CHECK: ('st_bind', 0x00000001) +// CHECK-NEXT: ('st_type', 0x00000002) + +// CHECK: # 'puts' +// CHECK: ('st_bind', 0x00000001) +// CHECK-NEXT: ('st_type', 0x00000000) diff --git a/test/MC/ELF/basic-elf-64.s b/test/MC/ELF/basic-elf-64.s index 7fc40b790ff8..5ae1f4516639 100644 --- a/test/MC/ELF/basic-elf-64.s +++ b/test/MC/ELF/basic-elf-64.s @@ -39,23 +39,6 @@ main: # @main // CHECK: # '.text' -// CHECK: ('st_bind', 0x00000000) -// CHECK: ('st_type', 0x00000003) - -// CHECK: ('st_bind', 0x00000000) -// CHECK: ('st_type', 0x00000003) - -// CHECK: ('st_bind', 0x00000000) -// CHECK: ('st_type', 0x00000003) - -// CHECK: # 'main' -// CHECK-NEXT: ('st_bind', 0x00000001) -// CHECK-NEXT: ('st_type', 0x00000002) - -// CHECK: # 'puts' -// CHECK-NEXT: ('st_bind', 0x00000001) -// CHECK-NEXT: ('st_type', 0x00000000) - // CHECK: # '.rela.text' // CHECK: ('_relocations', [ @@ -80,3 +63,20 @@ main: # @main // CHECK: ('r_addend', 0xfffffffc) // CHECK: ), // CHECK: ]) + +// CHECK: ('st_bind', 0x00000000) +// CHECK: ('st_type', 0x00000003) + +// CHECK: ('st_bind', 0x00000000) +// CHECK: ('st_type', 0x00000003) + +// CHECK: ('st_bind', 0x00000000) +// CHECK: ('st_type', 0x00000003) + +// CHECK: # 'main' +// CHECK-NEXT: ('st_bind', 0x00000001) +// CHECK-NEXT: ('st_type', 0x00000002) + +// CHECK: # 'puts' +// CHECK-NEXT: ('st_bind', 0x00000001) +// CHECK-NEXT: ('st_type', 0x00000000) diff --git a/test/MC/ELF/cfi-adjust-cfa-offset.s b/test/MC/ELF/cfi-adjust-cfa-offset.s new file mode 100644 index 000000000000..5c1a9f9d8b78 --- /dev/null +++ b/test/MC/ELF/cfi-adjust-cfa-offset.s @@ -0,0 +1,46 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s + +f: + .cfi_startproc + subq $8, %rsp + .cfi_def_cfa_offset 16 + nop + .cfi_adjust_cfa_offset 4 + addq $8, %rsp + .cfi_def_cfa_offset 8 + ret + .cfi_endproc + +// CHECK: # Section 0x00000004 +// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame' +// CHECK-NEXT: ('sh_type', 0x00000001) +// CHECK-NEXT: ('sh_flags', 0x00000002) +// CHECK-NEXT: ('sh_addr', 0x00000000) +// CHECK-NEXT: ('sh_offset', 0x00000050) +// CHECK-NEXT: ('sh_size', 0x00000038) +// CHECK-NEXT: ('sh_link', 0x00000000) +// CHECK-NEXT: ('sh_info', 0x00000000) +// CHECK-NEXT: ('sh_addralign', 0x00000008) +// CHECK-NEXT: ('sh_entsize', 0x00000000) +// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 1c000000 1c000000 00000000 0a000000 00440e10 410e1444 0e080000 00000000') +// CHECK-NEXT: ), +// CHECK-NEXT: # Section 0x00000005 +// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame' +// CHECK-NEXT: ('sh_type', 0x00000004) +// CHECK-NEXT: ('sh_flags', 0x00000000) +// CHECK-NEXT: ('sh_addr', 0x00000000) +// CHECK-NEXT: ('sh_offset', 0x000003a0) +// CHECK-NEXT: ('sh_size', 0x00000018) +// CHECK-NEXT: ('sh_link', 0x00000007) +// CHECK-NEXT: ('sh_info', 0x00000004) +// CHECK-NEXT: ('sh_addralign', 0x00000008) +// CHECK-NEXT: ('sh_entsize', 0x00000018) +// CHECK-NEXT: ('_relocations', [ +// CHECK-NEXT: # Relocation 0x00000000 +// CHECK-NEXT: (('r_offset', 0x00000020) +// CHECK-NEXT: ('r_sym', 0x00000002) +// CHECK-NEXT: ('r_type', 0x00000002) +// CHECK-NEXT: ('r_addend', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: ]) +// CHECK-NEXT: ), diff --git a/test/MC/ELF/cfi-advance-loc2.s b/test/MC/ELF/cfi-advance-loc2.s index 3ffdd6cf0288..163e81022dde 100644 --- a/test/MC/ELF/cfi-advance-loc2.s +++ b/test/MC/ELF/cfi-advance-loc2.s @@ -10,7 +10,7 @@ f: nop .cfi_endproc -// CHECK: (('sh_name', 0x00000012) # '.eh_frame' +// CHECK: (('sh_name', 0x00000011) # '.eh_frame' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000002) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -24,13 +24,13 @@ f: // CHECK-NEXT: ), -// CHECK: (('sh_name', 0x00000036) # '.rela.eh_frame' +// CHECK: (('sh_name', 0x0000000c) # '.rela.eh_frame' // CHECK-NEXT: ('sh_type', 0x00000004) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) -// CHECK-NEXT: ('sh_offset', 0x00000258) +// CHECK-NEXT: ('sh_offset', 0x00000490) // CHECK-NEXT: ('sh_size', 0x00000018) -// CHECK-NEXT: ('sh_link', 0x00000006) +// CHECK-NEXT: ('sh_link', 0x00000007) // CHECK-NEXT: ('sh_info', 0x00000004) // CHECK-NEXT: ('sh_addralign', 0x00000008) // CHECK-NEXT: ('sh_entsize', 0x00000018) diff --git a/test/MC/ELF/cfi-def-cfa-offset.s b/test/MC/ELF/cfi-def-cfa-offset.s index efefb8789dce..124d02e95df1 100644 --- a/test/MC/ELF/cfi-def-cfa-offset.s +++ b/test/MC/ELF/cfi-def-cfa-offset.s @@ -11,7 +11,7 @@ f: .cfi_endproc // CHECK: # Section 0x00000004 -// CHECK-NEXT: (('sh_name', 0x00000012) # '.eh_frame' +// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000002) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -24,14 +24,14 @@ f: // CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 0a000000 00440e10 450e0800') // CHECK-NEXT: ), -// CHECK: # Section 0x00000008 -// CHECK-NEXT: (('sh_name', 0x00000036) # '.rela.eh_frame' +// CHECK: # Section 0x00000005 +// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame' // CHECK-NEXT: ('sh_type', 0x00000004) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) -// CHECK-NEXT: ('sh_offset', 0x00000160) +// CHECK-NEXT: ('sh_offset', 0x00000398) // CHECK-NEXT: ('sh_size', 0x00000018) -// CHECK-NEXT: ('sh_link', 0x00000006) +// CHECK-NEXT: ('sh_link', 0x00000007) // CHECK-NEXT: ('sh_info', 0x00000004) // CHECK-NEXT: ('sh_addralign', 0x00000008) // CHECK-NEXT: ('sh_entsize', 0x00000018) diff --git a/test/MC/ELF/cfi-def-cfa-register.s b/test/MC/ELF/cfi-def-cfa-register.s index 3df20218a273..75311e2e8443 100644 --- a/test/MC/ELF/cfi-def-cfa-register.s +++ b/test/MC/ELF/cfi-def-cfa-register.s @@ -7,7 +7,7 @@ f: nop .cfi_endproc -// CHECK: (('sh_name', 0x00000012) # '.eh_frame' +// CHECK: (('sh_name', 0x00000011) # '.eh_frame' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000002) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -20,13 +20,13 @@ f: // CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 02000000 00410d06 00000000') // CHECK-NEXT: ), -// CHECK: (('sh_name', 0x00000036) # '.rela.eh_frame' +// CHECK: (('sh_name', 0x0000000c) # '.rela.eh_frame' // CHECK-NEXT: ('sh_type', 0x00000004) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) -// CHECK-NEXT: ('sh_offset', 0x00000158) +// CHECK-NEXT: ('sh_offset', 0x00000390) // CHECK-NEXT: ('sh_size', 0x00000018) -// CHECK-NEXT: ('sh_link', 0x00000006) +// CHECK-NEXT: ('sh_link', 0x00000007) // CHECK-NEXT: ('sh_info', 0x00000004) // CHECK-NEXT: ('sh_addralign', 0x00000008) // CHECK-NEXT: ('sh_entsize', 0x00000018) diff --git a/test/MC/ELF/cfi-def-cfa.s b/test/MC/ELF/cfi-def-cfa.s index 1ad427b310c3..53a169c09ddf 100644 --- a/test/MC/ELF/cfi-def-cfa.s +++ b/test/MC/ELF/cfi-def-cfa.s @@ -7,7 +7,7 @@ f: nop .cfi_endproc -// CHECK: (('sh_name', 0x00000012) # '.eh_frame' +// CHECK: (('sh_name', 0x00000011) # '.eh_frame' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000002) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -21,13 +21,13 @@ f: // CHECK-NEXT: ), -// CHECK: (('sh_name', 0x00000036) # '.rela.eh_frame' +// CHECK: (('sh_name', 0x0000000c) # '.rela.eh_frame' // CHECK-NEXT: ('sh_type', 0x00000004) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) -// CHECK-NEXT: ('sh_offset', 0x00000158) +// CHECK-NEXT: ('sh_offset', 0x00000390) // CHECK-NEXT: ('sh_size', 0x00000018) -// CHECK-NEXT: ('sh_link', 0x00000006) +// CHECK-NEXT: ('sh_link', 0x00000007) // CHECK-NEXT: ('sh_info', 0x00000004) // CHECK-NEXT: ('sh_addralign', 0x00000008) // CHECK-NEXT: ('sh_entsize', 0x00000018) diff --git a/test/MC/ELF/cfi-offset.s b/test/MC/ELF/cfi-offset.s index 2f7e7976fa57..963a76c1fca6 100644 --- a/test/MC/ELF/cfi-offset.s +++ b/test/MC/ELF/cfi-offset.s @@ -7,7 +7,7 @@ f: nop .cfi_endproc -// CHECK: (('sh_name', 0x00000012) # '.eh_frame' +// CHECK: (('sh_name', 0x00000011) # '.eh_frame' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000002) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -21,13 +21,13 @@ f: // CHECK-NEXT: ), -// CHECK: (('sh_name', 0x00000036) # '.rela.eh_frame' +// CHECK: (('sh_name', 0x0000000c) # '.rela.eh_frame' // CHECK-NEXT: ('sh_type', 0x00000004) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) -// CHECK-NEXT: ('sh_offset', 0x00000158) +// CHECK-NEXT: ('sh_offset', 0x00000390) // CHECK-NEXT: ('sh_size', 0x00000018) -// CHECK-NEXT: ('sh_link', 0x00000006) +// CHECK-NEXT: ('sh_link', 0x00000007) // CHECK-NEXT: ('sh_info', 0x00000004) // CHECK-NEXT: ('sh_addralign', 0x00000008) // CHECK-NEXT: ('sh_entsize', 0x00000018) diff --git a/test/MC/ELF/cfi-rel-offset.s b/test/MC/ELF/cfi-rel-offset.s new file mode 100644 index 000000000000..87c0cf3b6589 --- /dev/null +++ b/test/MC/ELF/cfi-rel-offset.s @@ -0,0 +1,49 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s + +f: + .cfi_startproc + nop + .cfi_def_cfa_offset 8 + nop + .cfi_def_cfa_register 6 + nop + .cfi_rel_offset 6,16 + nop + .cfi_def_cfa_offset 16 + nop + .cfi_rel_offset 6,0 + .cfi_endproc + +// CHECK: # Section 0x00000004 +// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame' +// CHECK-NEXT: ('sh_type', 0x00000001) +// CHECK-NEXT: ('sh_flags', 0x00000002) +// CHECK-NEXT: ('sh_addr', 0x00000000) +// CHECK-NEXT: ('sh_offset', 0x00000048) +// CHECK-NEXT: ('sh_size', 0x00000040) +// CHECK-NEXT: ('sh_link', 0x00000000) +// CHECK-NEXT: ('sh_info', 0x00000000) +// CHECK-NEXT: ('sh_addralign', 0x00000008) +// CHECK-NEXT: ('sh_entsize', 0x00000000) +// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 24000000 1c000000 00000000 05000000 00410e08 410d0641 11067f41 0e104186 02000000 00000000') +// CHECK-NEXT: ), +// CHECK-NEXT: # Section 0x00000005 +// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame' +// CHECK-NEXT: ('sh_type', 0x00000004) +// CHECK-NEXT: ('sh_flags', 0x00000000) +// CHECK-NEXT: ('sh_addr', 0x00000000) +// CHECK-NEXT: ('sh_offset', 0x000003a0) +// CHECK-NEXT: ('sh_size', 0x00000018) +// CHECK-NEXT: ('sh_link', 0x00000007) +// CHECK-NEXT: ('sh_info', 0x00000004) +// CHECK-NEXT: ('sh_addralign', 0x00000008) +// CHECK-NEXT: ('sh_entsize', 0x00000018) +// CHECK-NEXT: ('_relocations', [ +// CHECK-NEXT: # Relocation 0x00000000 +// CHECK-NEXT: (('r_offset', 0x00000020) +// CHECK-NEXT: ('r_sym', 0x00000002) +// CHECK-NEXT: ('r_type', 0x00000002) +// CHECK-NEXT: ('r_addend', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: ]) +// CHECK-NEXT: ), diff --git a/test/MC/ELF/cfi-rel-offset2.s b/test/MC/ELF/cfi-rel-offset2.s new file mode 100644 index 000000000000..f14beaf09d21 --- /dev/null +++ b/test/MC/ELF/cfi-rel-offset2.s @@ -0,0 +1,41 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s + +f: + .cfi_startproc + nop + .cfi_rel_offset 6,16 + .cfi_endproc + +// CHECK: # Section 0x00000004 +// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame' +// CHECK-NEXT: ('sh_type', 0x00000001) +// CHECK-NEXT: ('sh_flags', 0x00000002) +// CHECK-NEXT: ('sh_addr', 0x00000000) +// CHECK-NEXT: ('sh_offset', 0x00000048) +// CHECK-NEXT: ('sh_size', 0x00000030) +// CHECK-NEXT: ('sh_link', 0x00000000) +// CHECK-NEXT: ('sh_info', 0x00000000) +// CHECK-NEXT: ('sh_addralign', 0x00000008) +// CHECK-NEXT: ('sh_entsize', 0x00000000) +// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 01000000 00411106 7f000000') +// CHECK-NEXT: ), +// CHECK-NEXT: # Section 0x00000005 +// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame' +// CHECK-NEXT: ('sh_type', 0x00000004) +// CHECK-NEXT: ('sh_flags', 0x00000000) +// CHECK-NEXT: ('sh_addr', 0x00000000) +// CHECK-NEXT: ('sh_offset', 0x00000390) +// CHECK-NEXT: ('sh_size', 0x00000018) +// CHECK-NEXT: ('sh_link', 0x00000007) +// CHECK-NEXT: ('sh_info', 0x00000004) +// CHECK-NEXT: ('sh_addralign', 0x00000008) +// CHECK-NEXT: ('sh_entsize', 0x00000018) +// CHECK-NEXT: ('_relocations', [ +// CHECK-NEXT: # Relocation 0x00000000 +// CHECK-NEXT: (('r_offset', 0x00000020) +// CHECK-NEXT: ('r_sym', 0x00000002) +// CHECK-NEXT: ('r_type', 0x00000002) +// CHECK-NEXT: ('r_addend', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: ]) +// CHECK-NEXT: ), diff --git a/test/MC/ELF/cfi-remember.s b/test/MC/ELF/cfi-remember.s index b5b380368f06..814812e2aaa6 100644 --- a/test/MC/ELF/cfi-remember.s +++ b/test/MC/ELF/cfi-remember.s @@ -10,7 +10,7 @@ f: .cfi_endproc // CHECK: # Section 0x00000004 -// CHECK-NEXT: (('sh_name', 0x00000012) # '.eh_frame' +// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000002) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -23,14 +23,14 @@ f: // CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 03000000 00410a41 0b000000') // CHECK-NEXT: ), -// CHECK: # Section 0x00000008 -// CHECK-NEXT: (('sh_name', 0x00000036) # '.rela.eh_frame' +// CHECK: # Section 0x00000005 +// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame' // CHECK-NEXT: ('sh_type', 0x00000004) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) -// CHECK-NEXT: ('sh_offset', 0x00000158) +// CHECK-NEXT: ('sh_offset', 0x00000390) // CHECK-NEXT: ('sh_size', 0x00000018) -// CHECK-NEXT: ('sh_link', 0x00000006) +// CHECK-NEXT: ('sh_link', 0x00000007) // CHECK-NEXT: ('sh_info', 0x00000004) // CHECK-NEXT: ('sh_addralign', 0x00000008) // CHECK-NEXT: ('sh_entsize', 0x00000018) diff --git a/test/MC/ELF/cfi-same-value.s b/test/MC/ELF/cfi-same-value.s new file mode 100644 index 000000000000..eab1ae4d4b21 --- /dev/null +++ b/test/MC/ELF/cfi-same-value.s @@ -0,0 +1,42 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s + +f: + .cfi_startproc + nop + .cfi_same_value 6 + nop + .cfi_endproc + +// CHECK: # Section 0x00000004 +// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame' +// CHECK-NEXT: ('sh_type', 0x00000001) +// CHECK-NEXT: ('sh_flags', 0x00000002) +// CHECK-NEXT: ('sh_addr', 0x00000000) +// CHECK-NEXT: ('sh_offset', 0x00000048) +// CHECK-NEXT: ('sh_size', 0x00000030) +// CHECK-NEXT: ('sh_link', 0x00000000) +// CHECK-NEXT: ('sh_info', 0x00000000) +// CHECK-NEXT: ('sh_addralign', 0x00000008) +// CHECK-NEXT: ('sh_entsize', 0x00000000) +// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 02000000 00410806 00000000') +// CHECK-NEXT: ), +// CHECK-NEXT: # Section 0x00000005 +// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame' +// CHECK-NEXT: ('sh_type', 0x00000004) +// CHECK-NEXT: ('sh_flags', 0x00000000) +// CHECK-NEXT: ('sh_addr', 0x00000000) +// CHECK-NEXT: ('sh_offset', 0x00000390) +// CHECK-NEXT: ('sh_size', 0x00000018) +// CHECK-NEXT: ('sh_link', 0x00000007) +// CHECK-NEXT: ('sh_info', 0x00000004) +// CHECK-NEXT: ('sh_addralign', 0x00000008) +// CHECK-NEXT: ('sh_entsize', 0x00000018) +// CHECK-NEXT: ('_relocations', [ +// CHECK-NEXT: # Relocation 0x00000000 +// CHECK-NEXT: (('r_offset', 0x00000020) +// CHECK-NEXT: ('r_sym', 0x00000002) +// CHECK-NEXT: ('r_type', 0x00000002) +// CHECK-NEXT: ('r_addend', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: ]) +// CHECK-NEXT: ), diff --git a/test/MC/ELF/cfi-zero-addr-delta.s b/test/MC/ELF/cfi-zero-addr-delta.s index 5585e296da54..3ddf69ec50c6 100644 --- a/test/MC/ELF/cfi-zero-addr-delta.s +++ b/test/MC/ELF/cfi-zero-addr-delta.s @@ -14,7 +14,7 @@ f: nop .cfi_endproc -// CHECK: (('sh_name', 0x00000012) # '.eh_frame' +// CHECK: (('sh_name', 0x00000011) # '.eh_frame' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000002) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -27,13 +27,13 @@ f: // CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 1c000000 1c000000 00000000 04000000 00410e10 410a0e08 410b0000 00000000') // CHECK-NEXT: ), -// CHECK: (('sh_name', 0x00000036) # '.rela.eh_frame' +// CHECK: (('sh_name', 0x0000000c) # '.rela.eh_frame' // CHECK-NEXT: ('sh_type', 0x00000004) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) -// CHECK-NEXT: ('sh_offset', 0x00000160) +// CHECK-NEXT: ('sh_offset', 0x00000398) // CHECK-NEXT: ('sh_size', 0x00000018) -// CHECK-NEXT: ('sh_link', 0x00000006) +// CHECK-NEXT: ('sh_link', 0x00000007) // CHECK-NEXT: ('sh_info', 0x00000004) // CHECK-NEXT: ('sh_addralign', 0x00000008) // CHECK-NEXT: ('sh_entsize', 0x00000018) diff --git a/test/MC/ELF/cfi.s b/test/MC/ELF/cfi.s index 93fd2e792238..133b85809aa6 100644 --- a/test/MC/ELF/cfi.s +++ b/test/MC/ELF/cfi.s @@ -213,7 +213,7 @@ f36: .cfi_endproc // CHECK: # Section 0x00000004 -// CHECK-NEXT: (('sh_name', 0x00000012) # '.eh_frame' +// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000002) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -226,14 +226,14 @@ f36: // CHECK-NEXT: ('_section_data', '14000000 00000000 017a4c52 00017810 02031b0c 07089001 14000000 1c000000 00000000 01000000 04000000 00000000 20000000 00000000 017a504c 52000178 100b0000 00000000 00000003 1b0c0708 90010000 14000000 28000000 00000000 01000000 04000000 00000000 14000000 70000000 00000000 01000000 04000000 00000000 20000000 00000000 017a504c 52000178 100b0000 00000000 00000002 1b0c0708 90010000 10000000 28000000 00000000 01000000 02000000 18000000 00000000 017a5052 00017810 04020000 1b0c0708 90010000 10000000 20000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 06030000 00001b0c 07089001 10000000 20000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a040000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 040a0000 1b0c0708 90010000 10000000 20000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 060b0000 00001b0c 07089001 10000000 20000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a0c0000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a080000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a100000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 04120000 1b0c0708 90010000 10000000 20000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 06130000 00001b0c 07089001 10000000 20000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a140000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 041a0000 1b0c0708 90010000 10000000 20000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 061b0000 00001b0c 07089001 10000000 20000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a1c0000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a180000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a800000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 04820000 1b0c0708 90010000 10000000 20000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 06830000 00001b0c 07089001 10000000 20000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a840000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 048a0000 1b0c0708 90010000 10000000 20000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 068b0000 00001b0c 07089001 10000000 20000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a8c0000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a880000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a900000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 04920000 1b0c0708 90010000 10000000 20000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 06930000 00001b0c 07089001 10000000 20000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a940000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 049a0000 1b0c0708 90010000 10000000 20000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 069b0000 00001b0c 07089001 10000000 20000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a9c0000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a980000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000') // CHECK-NEXT: ), -// CHECK: # Section 0x00000008 -// CHECK-NEXT: (('sh_name', 0x00000036) # '.rela.eh_frame' +// CHECK: # Section 0x00000005 +// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame' // CHECK-NEXT: ('sh_type', 0x00000004) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) -// CHECK-NEXT: ('sh_offset', 0x00000bf8) +// CHECK-NEXT: ('sh_offset', 0x00000e30) // CHECK-NEXT: ('sh_size', 0x000006c0) -// CHECK-NEXT: ('sh_link', 0x00000006) +// CHECK-NEXT: ('sh_link', 0x00000007) // CHECK-NEXT: ('sh_info', 0x00000004) // CHECK-NEXT: ('sh_addralign', 0x00000008) // CHECK-NEXT: ('sh_entsize', 0x00000018) diff --git a/test/MC/ELF/comdat.s b/test/MC/ELF/comdat.s index 0f1164e82068..be7128baf4e6 100644 --- a/test/MC/ELF/comdat.s +++ b/test/MC/ELF/comdat.s @@ -4,37 +4,37 @@ // of the file. // CHECK: # Section 0x00000001 -// CHECK-NEXT: (('sh_name', 0x00000026) # '.group' +// CHECK-NEXT: (('sh_name', 0x0000001b) # '.group' // CHECK-NEXT: ('sh_type', 0x00000011) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) // CHECK-NEXT: ('sh_offset', 0x00000040) // CHECK-NEXT: ('sh_size', 0x0000000c) -// CHECK-NEXT: ('sh_link', 0x0000000c) +// CHECK-NEXT: ('sh_link', 0x0000000d) // CHECK-NEXT: ('sh_info', 0x00000001) // CHECK-NEXT: ('sh_addralign', 0x00000004) // CHECK-NEXT: ('sh_entsize', 0x00000004) // CHECK-NEXT: ), // CHECK-NEXT: # Section 0x00000002 -// CHECK-NEXT: (('sh_name', 0x00000026) # '.group' +// CHECK-NEXT: (('sh_name', 0x0000001b) # '.group' // CHECK-NEXT: ('sh_type', 0x00000011) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) // CHECK-NEXT: ('sh_offset', 0x0000004c) // CHECK-NEXT: ('sh_size', 0x00000008) -// CHECK-NEXT: ('sh_link', 0x0000000c) +// CHECK-NEXT: ('sh_link', 0x0000000d) // CHECK-NEXT: ('sh_info', 0x00000002) // CHECK-NEXT: ('sh_addralign', 0x00000004) // CHECK-NEXT: ('sh_entsize', 0x00000004) // CHECK-NEXT: ), // CHECK-NEXT: # Section 0x00000003 -// CHECK-NEXT: (('sh_name', 0x00000026) # '.group' +// CHECK-NEXT: (('sh_name', 0x0000001b) # '.group' // CHECK-NEXT: ('sh_type', 0x00000011) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) // CHECK-NEXT: ('sh_offset', 0x00000054) // CHECK-NEXT: ('sh_size', 0x00000008) -// CHECK-NEXT: ('sh_link', 0x0000000c) +// CHECK-NEXT: ('sh_link', 0x0000000d) // CHECK-NEXT: ('sh_info', 0x0000000d) // CHECK-NEXT: ('sh_addralign', 0x00000004) // CHECK-NEXT: ('sh_entsize', 0x00000004) diff --git a/test/MC/ELF/common.s b/test/MC/ELF/common.s index 16b677b9e880..70e2ed2a95a6 100644 --- a/test/MC/ELF/common.s +++ b/test/MC/ELF/common.s @@ -38,7 +38,7 @@ // CHECK-NEXT: ('st_bind', 0x00000000) // CHECK-NEXT: ('st_type', 0x00000001) // CHECK-NEXT: ('st_other', 0x00000000) -// CHECK-NEXT: ('st_shndx', 0x00000003) +// CHECK-NEXT: ('st_shndx', 0x00000004) // CHECK-NEXT: ('st_value', 0x0000000000000010) // CHECK-NEXT: ('st_size', 0x0000000000000008) // CHECK-NEXT: ), diff --git a/test/MC/ELF/common2.s b/test/MC/ELF/common2.s index b54cdfe143fb..b48ca66b91e1 100644 --- a/test/MC/ELF/common2.s +++ b/test/MC/ELF/common2.s @@ -9,7 +9,7 @@ .zero 1 .align 8 -// CHECK: (('sh_name', 0x0000000d) # '.bss' +// CHECK: (('sh_name', 0x00000007) # '.bss' // CHECK-NEXT: ('sh_type', // CHECK-NEXT: ('sh_flags' // CHECK-NEXT: ('sh_addr', diff --git a/test/MC/ELF/debug-line.s b/test/MC/ELF/debug-line.s index 2979ca28f1ec..aa0197d0ce29 100644 --- a/test/MC/ELF/debug-line.s +++ b/test/MC/ELF/debug-line.s @@ -2,7 +2,7 @@ // Test that .debug_line is populated. -// CHECK: (('sh_name', 0x00000012) # '.debug_line' +// CHECK: (('sh_name', 0x00000011) # '.debug_line' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) diff --git a/test/MC/ELF/debug-loc.s b/test/MC/ELF/debug-loc.s index 36ae485ef062..68e36a55c715 100644 --- a/test/MC/ELF/debug-loc.s +++ b/test/MC/ELF/debug-loc.s @@ -8,7 +8,7 @@ // FIXME2: We need a debug_line dumper so that we can test the actual contents. // CHECK: # Section 0x00000004 -// CHECK-NEXT: (('sh_name', 0x00000012) # '.debug_line' +// CHECK-NEXT: (('sh_name', 0x00000011) # '.debug_line' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) diff --git a/test/MC/ELF/empty-dwarf-lines.s b/test/MC/ELF/empty-dwarf-lines.s index 0f791ae2aa3e..1b135a677ddc 100644 --- a/test/MC/ELF/empty-dwarf-lines.s +++ b/test/MC/ELF/empty-dwarf-lines.s @@ -8,7 +8,7 @@ c: .asciz "hi\n" // CHECK: # Section 0x00000004 -// CHECK-NEXT: (('sh_name', 0x00000012) # '.debug_line' +// CHECK-NEXT: (('sh_name', 0x0000000c) # '.debug_line' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) diff --git a/test/MC/ELF/empty.s b/test/MC/ELF/empty.s index e351936b901f..d98f0c6a9692 100644 --- a/test/MC/ELF/empty.s +++ b/test/MC/ELF/empty.s @@ -14,7 +14,7 @@ // CHECK-NEXT: ('sh_addralign', 0x00000004) // CHECK-NEXT: ('sh_entsize', 0x00000000) -// CHECK: ('sh_name', 0x00000007) # '.data' +// CHECK: ('sh_name', 0x00000026) # '.data' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000003) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -25,7 +25,7 @@ // CHECK-NEXT: ('sh_addralign', 0x00000004) // CHECK-NEXT: ('sh_entsize', 0x00000000) -// CHECK: ('sh_name', 0x0000000d) # '.bss' +// CHECK: ('sh_name', 0x00000007) # '.bss' // CHECK-NEXT: ('sh_type', 0x00000008) // CHECK-NEXT: ('sh_flags', 0x00000003) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -36,7 +36,7 @@ // CHECK-NEXT: ('sh_addralign', 0x00000004) // CHECK-NEXT: ('sh_entsize', 0x00000000) -// CHECK: ('sh_name', 0x00000012) # '.shstrtab' +// CHECK: ('sh_name', 0x0000000c) # '.shstrtab' // CHECK-NEXT: ('sh_type', 0x00000003) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -47,7 +47,7 @@ // CHECK-NEXT: ('sh_addralign', 0x00000001) // CHECK-NEXT: ('sh_entsize', 0x00000000) -// CHECK: ('sh_name', 0x0000001c) # '.symtab' +// CHECK: ('sh_name', 0x0000001e) # '.symtab' // CHECK-NEXT: ('sh_type', 0x00000002) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -58,7 +58,7 @@ // CHECK-NEXT: ('sh_addralign', 0x00000008) // CHECK-NEXT: ('sh_entsize', 0x00000018) -// CHECK: ('sh_name', 0x00000024) # '.strtab' +// CHECK: ('sh_name', 0x00000016) # '.strtab' // CHECK-NEXT: ('sh_type', 0x00000003) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) diff --git a/test/MC/ELF/entsize.ll b/test/MC/ELF/entsize.ll index 21179dfda9a3..74f0413ecbe6 100644 --- a/test/MC/ELF/entsize.ll +++ b/test/MC/ELF/entsize.ll @@ -20,7 +20,7 @@ declare void @foo(i64* nocapture) nounwind ;;;;; -; 64: (('sh_name', 0x00000012) # '.rodata.str1.1' +; 64: (('sh_name', 0x0000004e) # '.rodata.str1.1' ; 64-NEXT: ('sh_type', 0x00000001) ; 64-NEXT: ('sh_flags', 0x00000032) ; 64-NEXT: ('sh_addr', @@ -31,7 +31,7 @@ declare void @foo(i64* nocapture) nounwind ; 64-NEXT: ('sh_addralign', 0x00000001) ; 64-NEXT: ('sh_entsize', 0x00000001) -; 64: (('sh_name', 0x00000021) # '.rodata.cst8' +; 64: (('sh_name', 0x00000041) # '.rodata.cst8' ; 64-NEXT: ('sh_type', 0x00000001) ; 64-NEXT: ('sh_flags', 0x00000012) ; 64-NEXT: ('sh_addr', diff --git a/test/MC/ELF/entsize.s b/test/MC/ELF/entsize.s index e8eb62eb2ea5..415eaefe4660 100644 --- a/test/MC/ELF/entsize.s +++ b/test/MC/ELF/entsize.s @@ -33,7 +33,7 @@ .quad 42 // CHECK: # Section 0x00000004 -// CHECK-NEXT: ('sh_name', 0x00000012) # '.rodata.str1.1' +// CHECK-NEXT: ('sh_name', 0x00000048) # '.rodata.str1.1' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000032) // CHECK-NEXT: ('sh_addr', @@ -45,7 +45,7 @@ // CHECK-NEXT: ('sh_entsize', 0x00000001) // CHECK: # Section 0x00000005 -// CHECK-NEXT: ('sh_name', 0x00000021) # '.rodata.str2.1' +// CHECK-NEXT: ('sh_name', 0x00000039) # '.rodata.str2.1' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000032) // CHECK-NEXT: ('sh_addr', @@ -57,7 +57,7 @@ // CHECK-NEXT: ('sh_entsize', 0x00000002) // CHECK: # Section 0x00000006 -// CHECK-NEXT: ('sh_name', 0x00000030) # '.rodata.cst8 +// CHECK-NEXT: ('sh_name', 0x0000002c) # '.rodata.cst8 // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000012) // CHECK-NEXT: ('sh_addr', diff --git a/test/MC/ELF/global-offset.s b/test/MC/ELF/global-offset.s index aa6328760d44..77f72677108b 100644 --- a/test/MC/ELF/global-offset.s +++ b/test/MC/ELF/global-offset.s @@ -5,7 +5,7 @@ addl $_GLOBAL_OFFSET_TABLE_, %ebx -// CHECK: ('sh_name', 0x00000001) # '.text' +// CHECK: ('sh_name', 0x00000005) # '.text' // CHECK-NEXT: ('sh_type', // CHECK-NEXT: ('sh_flags', // CHECK-NEXT: ('sh_addr', diff --git a/test/MC/ELF/got.s b/test/MC/ELF/got.s index 798150e0f5f9..a3abef536a00 100644 --- a/test/MC/ELF/got.s +++ b/test/MC/ELF/got.s @@ -6,9 +6,6 @@ movl foo@GOT, %eax movl foo@GOTPCREL(%rip), %eax -// CHECK: (('st_name', 0x00000005) # '_GLOBAL_OFFSET_TABLE_' -// CHECK-NEXT: ('st_bind', 0x00000001) - // CHECK: ('_relocations', [ // CHECK-NEXT: # Relocation 0x00000000 // CHECK-NEXT: (('r_offset', @@ -23,3 +20,6 @@ // CHECK-NEXT: ('r_addend', // CHECK-NEXT: ), // CHECK-NEXT: ]) + +// CHECK: (('st_name', 0x00000005) # '_GLOBAL_OFFSET_TABLE_' +// CHECK-NEXT: ('st_bind', 0x00000001) diff --git a/test/MC/ELF/ident.s b/test/MC/ELF/ident.s index f79458f34501..b364d6007fec 100644 --- a/test/MC/ELF/ident.s +++ b/test/MC/ELF/ident.s @@ -1,6 +1,6 @@ // RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s -// CHECK: (('sh_name', 0x00000012) # '.comment' +// CHECK: (('sh_name', 0x00000007) # '.comment' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000030) // CHECK-NEXT: ('sh_addr', 0x00000000) diff --git a/test/MC/ELF/local-reloc.s b/test/MC/ELF/local-reloc.s index c2b477188cb2..8384e0e6cb77 100644 --- a/test/MC/ELF/local-reloc.s +++ b/test/MC/ELF/local-reloc.s @@ -10,16 +10,6 @@ foo: // CHECK: # Section 0x00000001 // CHECK-next: (('sh_name', 0x00000001) # '.text' -// Symbol number 2 is section number 1 -// CHECK: # Symbol 0x00000002 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK-NEXT: ('st_bind', 0x00000000) -// CHECK-NEXT: ('st_type', 0x00000003) -// CHECK-NEXT: ('st_other', 0x00000000) -// CHECK-NEXT: ('st_shndx', 0x00000001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) - // Relocation refers to symbol number 2 // CHECK: ('_relocations', [ // CHECK-NEXT: # Relocation 0x00000000 @@ -29,3 +19,13 @@ foo: // CHECK-NEXT: ('r_addend', // CHECK-NEXT: ), // CHECK-NEXT: ]) + +// Symbol number 2 is section number 1 +// CHECK: # Symbol 0x00000002 +// CHECK-NEXT: (('st_name', 0x00000000) # '' +// CHECK-NEXT: ('st_bind', 0x00000000) +// CHECK-NEXT: ('st_type', 0x00000003) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000001) +// CHECK-NEXT: ('st_value', 0x0000000000000000) +// CHECK-NEXT: ('st_size', 0x0000000000000000) diff --git a/test/MC/ELF/merge.s b/test/MC/ELF/merge.s index ec0222890071..befc2bfc0b52 100644 --- a/test/MC/ELF/merge.s +++ b/test/MC/ELF/merge.s @@ -22,30 +22,6 @@ zed: .section bar,"ax",@progbits foo: -// Section 4 is "sec1" -// CHECK: # Section 0x00000004 -// CHECK-NEXT: (('sh_name', 0x00000012) # '.sec1' - -// Symbol number 1 is .Lfoo -// CHECK: # Symbol 0x00000001 -// CHECK-NEXT: (('st_name', 0x00000001) # '.Lfoo' - -// Symbol number 2 is foo -// CHECK: # Symbol 0x00000002 -// CHECK-NEXT: (('st_name', 0x00000007) # 'foo' - -// Symbol number 6 is section 4 -// CHECK: # Symbol 0x00000006 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK-NEXT: ('st_bind', 0x00000000) -// CHECK-NEXT: ('st_type', 0x00000003) -// CHECK-NEXT: ('st_other', 0x00000000) -// CHECK-NEXT: ('st_shndx', 0x00000004) - -// Symbol number 8 is zed -// CHECK: # Symbol 0x00000008 -// CHECK-NEXT: (('st_name', 0x0000000b) # 'zed' - // Relocation 0 refers to symbol 1 // CHECK: ('_relocations', [ // CHECK-NEXT: # Relocation 0 @@ -95,3 +71,27 @@ foo: // CHECK-NEXT: ('r_addend', 0x00000000) // CHECK-NEXT: ), // CHECK-NEXT: ]) + +// Section 5 is "sec1" +// CHECK: # Section 0x00000005 +// CHECK-NEXT: (('sh_name', 0x00000035) # '.sec1' + +// Symbol number 1 is .Lfoo +// CHECK: # Symbol 0x00000001 +// CHECK-NEXT: (('st_name', 0x00000001) # '.Lfoo' + +// Symbol number 2 is foo +// CHECK: # Symbol 0x00000002 +// CHECK-NEXT: (('st_name', 0x00000007) # 'foo' + +// Symbol number 6 is section 5 +// CHECK: # Symbol 0x00000006 +// CHECK-NEXT: (('st_name', 0x00000000) # '' +// CHECK-NEXT: ('st_bind', 0x00000000) +// CHECK-NEXT: ('st_type', 0x00000003) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000005) + +// Symbol number 8 is zed +// CHECK: # Symbol 0x00000008 +// CHECK-NEXT: (('st_name', 0x0000000b) # 'zed' diff --git a/test/MC/ELF/noexec.s b/test/MC/ELF/noexec.s index 87b6f3aa85b8..c4b7d9851b93 100644 --- a/test/MC/ELF/noexec.s +++ b/test/MC/ELF/noexec.s @@ -1,7 +1,7 @@ // RUN: llvm-mc -mc-no-exec-stack -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s // CHECK: # Section 0x00000004 -// CHECK-NEXT: (('sh_name', 0x00000012) # '.note.GNU-stack' +// CHECK-NEXT: (('sh_name', 0x0000000c) # '.note.GNU-stack' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) diff --git a/test/MC/ELF/pic-diff.s b/test/MC/ELF/pic-diff.s index d1fc909dba8a..c2f96c250639 100644 --- a/test/MC/ELF/pic-diff.s +++ b/test/MC/ELF/pic-diff.s @@ -1,5 +1,14 @@ // RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// CHECK: ('_relocations', [ +// CHECK-NEXT: # Relocation 0x00000000 +// CHECK-NEXT: (('r_offset', 0x0000000c) +// CHECK-NEXT: ('r_sym', 0x00000005) +// CHECK-NEXT: ('r_type', 0x00000002) +// CHECK-NEXT: ('r_addend', 0x00000008) +// CHECK-NEXT: ), +// CHECK-NEXT: ]) + // CHECK: # Symbol 0x00000005 // CHECK-NEXT: (('st_name', 0x00000005) # 'baz' // CHECK-NEXT: ('st_bind', 0x00000001) @@ -10,15 +19,6 @@ // CHECK-NEXT: ('st_size', 0x0000000000000000) // CHECK-NEXT: ), -// CHECK: ('_relocations', [ -// CHECK-NEXT: # Relocation 0x00000000 -// CHECK-NEXT: (('r_offset', 0x0000000c) -// CHECK-NEXT: ('r_sym', 0x00000005) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x00000008) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) - .zero 4 .data diff --git a/test/MC/ELF/relocation-386.s b/test/MC/ELF/relocation-386.s index f106f89b7083..f7b20b56ba53 100644 --- a/test/MC/ELF/relocation-386.s +++ b/test/MC/ELF/relocation-386.s @@ -3,33 +3,6 @@ // Test that we produce the correct relocation types and that the relocations // correctly point to the section or the symbol. -// Section 3 is bss -// CHECK: # Section 0x00000003 -// CHECK-NEXT: (('sh_name', 0x0000000d) # '.bss' - -// CHECK: # Symbol 0x00000001 -// CHECK-NEXT: (('st_name', 0x00000005) # '.Lfoo' - -// Symbol 4 is zed -// CHECK: # Symbol 0x00000004 -// CHECK-NEXT: (('st_name', 0x00000035) # 'zed' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x00000000) -// CHECK-NEXT: ('st_type', 0x00000006) -// CHECK-NEXT: ('st_other', 0x00000000) -// CHECK-NEXT: ('st_shndx', 0x00000004) - -// Symbol 7 is section 3 -// CHECK: # Symbol 0x00000007 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x00000000) -// CHECK-NEXT: ('st_type', 0x00000003) -// CHECK-NEXT: ('st_other', 0x00000000) -// CHECK-NEXT: ('st_shndx', 0x00000003) - // CHECK: # Relocation 0x00000000 // CHECK-NEXT: (('r_offset', 0x00000002) // CHECK-NEXT: ('r_sym', 0x00000001) @@ -181,6 +154,34 @@ // CHECK-NEXT: ('r_type', 0x00000001) // CHECK-NEXT: ), +// Section 4 is bss +// CHECK: # Section 0x00000004 +// CHECK-NEXT: (('sh_name', 0x0000000b) # '.bss' + +// CHECK: # Symbol 0x00000001 +// CHECK-NEXT: (('st_name', 0x00000005) # '.Lfoo' + +// Symbol 4 is zed +// CHECK: # Symbol 0x00000004 +// CHECK-NEXT: (('st_name', 0x00000035) # 'zed' +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ('st_bind', 0x00000000) +// CHECK-NEXT: ('st_type', 0x00000006) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000005) + +// Symbol 7 is section 4 +// CHECK: # Symbol 0x00000007 +// CHECK-NEXT: (('st_name', 0x00000000) # '' +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ('st_bind', 0x00000000) +// CHECK-NEXT: ('st_type', 0x00000003) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000004) + + .text bar: leal .Lfoo@GOTOFF(%ebx), %eax diff --git a/test/MC/ELF/relocation-pc.s b/test/MC/ELF/relocation-pc.s index 58c5f410b517..36212cb7232a 100644 --- a/test/MC/ELF/relocation-pc.s +++ b/test/MC/ELF/relocation-pc.s @@ -5,14 +5,14 @@ loope 0 # R_X86_64_PC8 jmp -256 # R_X86_64_PC32 -// CHECK: # Section 0x00000007 -// CHECK-NEXT: (('sh_name', 0x0000002c) # '.rela.text' +// CHECK: # Section 0x00000002 +// CHECK-NEXT: (('sh_name', 0x00000001) # '.rela.text' // CHECK-NEXT: ('sh_type', 0x00000004) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) -// CHECK-NEXT: ('sh_offset', 0x000000e8) +// CHECK-NEXT: ('sh_offset', 0x000002e8) // CHECK-NEXT: ('sh_size', 0x00000030) -// CHECK-NEXT: ('sh_link', 0x00000005) +// CHECK-NEXT: ('sh_link', 0x00000006) // CHECK-NEXT: ('sh_info', 0x00000001) // CHECK-NEXT: ('sh_addralign', 0x00000008) // CHECK-NEXT: ('sh_entsize', 0x00000018) diff --git a/test/MC/ELF/relocation.s b/test/MC/ELF/relocation.s index dabe721d90bc..4df09e13fce0 100644 --- a/test/MC/ELF/relocation.s +++ b/test/MC/ELF/relocation.s @@ -20,14 +20,7 @@ bar: // CHECK: # Section 0x00000001 -// CHECK: (('sh_name', 0x00000001) # '.text' - -// CHECK: # Symbol 0x00000002 -// CHECK: (('st_name', 0x00000000) # '' -// CHECK: ('st_bind', 0x00000000) -// CHECK: ('st_type', 0x00000003) -// CHECK: ('st_other', 0x00000000) -// CHECK: ('st_shndx', 0x00000001) +// CHECK: (('sh_name', 0x00000006) # '.text' // CHECK: # Relocation 0x00000000 // CHECK-NEXT: (('r_offset', 0x00000001) @@ -112,3 +105,10 @@ bar: // CHECK-NEXT: ('r_sym', 0x00000006) // CHECK-NEXT: ('r_type', 0x00000002) // CHECK-NEXT: ('r_addend', 0x0000005c) + +// CHECK: # Symbol 0x00000002 +// CHECK: (('st_name', 0x00000000) # '' +// CHECK: ('st_bind', 0x00000000) +// CHECK: ('st_type', 0x00000003) +// CHECK: ('st_other', 0x00000000) +// CHECK: ('st_shndx', 0x00000001) diff --git a/test/MC/ELF/rename.s b/test/MC/ELF/rename.s index 36065603e784..e7cedd0afb47 100644 --- a/test/MC/ELF/rename.s +++ b/test/MC/ELF/rename.s @@ -17,7 +17,7 @@ defined3: // Section 1 is .text // CHECK: # Section 0x00000001 -// CHECK-NEXT: (('sh_name', 0x00000001) # '.text' +// CHECK-NEXT: (('sh_name', 0x00000006) # '.text' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000006) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -28,6 +28,13 @@ defined3: // CHECK-NEXT: ('sh_addralign', 0x00000004) // CHECK-NEXT: ('sh_entsize', 0x00000000) +// The relocation uses symbol 2 +// CHECK: # Relocation 0x00000000 +// CHECK-NEXT: (('r_offset', 0x00000000) +// CHECK-NEXT: ('r_sym', 0x00000002) +// CHECK-NEXT: ('r_type', 0x0000000a) +// CHECK-NEXT: ('r_addend', 0x00000000) + // Symbol 2 is section 1 // CHECK: # Symbol 0x00000002 // CHECK-NEXT: (('st_name', 0x00000000) # '' @@ -37,10 +44,3 @@ defined3: // CHECK-NEXT: ('st_shndx', 0x00000001) // CHECK-NEXT: ('st_value', 0x0000000000000000) // CHECK-NEXT: ('st_size', 0x0000000000000000) - -// The relocation uses symbol 2 -// CHECK: # Relocation 0x00000000 -// CHECK-NEXT: (('r_offset', 0x00000000) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', 0x00000000) diff --git a/test/MC/ELF/section-quoting.s b/test/MC/ELF/section-quoting.s new file mode 100644 index 000000000000..3751e722952d --- /dev/null +++ b/test/MC/ELF/section-quoting.s @@ -0,0 +1,10 @@ +// RUN: llvm-mc -triple x86_64-pc-linux-gnu %s -o - | FileCheck %s + +// Test that we handle the strings like gas +.section bar-"foo" +.section "foo" +.section "foo bar" + +// CHECK: .section "bar-\"foo\"" +// CHECK: .section foo +// CHECK: .section "foo bar" diff --git a/test/MC/ELF/section.s b/test/MC/ELF/section.s index 861dc4f057fe..5fb5525cba64 100644 --- a/test/MC/ELF/section.s +++ b/test/MC/ELF/section.s @@ -7,10 +7,10 @@ .section .note.GNU-,"",@progbits .section -.note.GNU,"",@progbits -// CHECK: ('sh_name', 0x00000012) # '.note.GNU-stack' -// CHECK: ('sh_name', 0x00000022) # '.note.GNU-stack2' -// CHECK: ('sh_name', 0x00000033) # '.note.GNU-' -// CHECK: ('sh_name', 0x0000003e) # '-.note.GNU' +// CHECK: ('sh_name', 0x00000038) # '.note.GNU-stack' +// CHECK: ('sh_name', 0x0000008f) # '.note.GNU-stack2' +// CHECK: ('sh_name', 0x000000a0) # '.note.GNU-' +// CHECK: ('sh_name', 0x00000084) # '-.note.GNU' // Test that the defaults are used @@ -19,7 +19,7 @@ .section .rodata .section zed, "" -// CHECK: (('sh_name', 0x00000049) # '.init' +// CHECK: (('sh_name', 0x00000012) # '.init' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000006) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -31,7 +31,7 @@ // CHECK-NEXT: ('sh_entsize', 0x00000000) // CHECK-NEXT: ), // CHECK-NEXT: # Section 0x0000000b -// CHECK-NEXT: (('sh_name', 0x0000004f) # '.fini' +// CHECK-NEXT: (('sh_name', 0x00000048) # '.fini' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000006) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -43,7 +43,7 @@ // CHECK-NEXT: ('sh_entsize', 0x00000000) // CHECK-NEXT: ), // CHECK-NEXT: # Section 0x0000000c -// CHECK-NEXT: (('sh_name', 0x00000055) # '.rodata' +// CHECK-NEXT: (('sh_name', 0x00000076) # '.rodata' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000002) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -55,7 +55,7 @@ // CHECK-NEXT: ('sh_entsize', 0x00000000) // CHECK-NEXT: ), // CHECK-NEXT: # Section 0x0000000d -// CHECK-NEXT: (('sh_name', 0x0000005d) # 'zed' +// CHECK-NEXT: (('sh_name', 0x00000058) # 'zed' // CHECK-NEXT: ('sh_type', 0x00000001) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -68,7 +68,7 @@ // CHECK-NEXT: ), .section .note.test,"",@note -// CHECK: (('sh_name', 0x00000061) # '.note.test' +// CHECK: (('sh_name', 0x00000007) # '.note.test' // CHECK-NEXT: ('sh_type', 0x00000007) // CHECK-NEXT: ('sh_flags', 0x00000000) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -90,7 +90,7 @@ bar: .section .eh_frame,"a",@unwind -// CHECK: (('sh_name', 0x00000080) # '.eh_frame' +// CHECK: (('sh_name', 0x0000004e) # '.eh_frame' // CHECK-NEXT: ('sh_type', 0x70000001) // CHECK-NEXT: ('sh_flags', 0x00000002) // CHECK-NEXT: ('sh_addr', 0x00000000) @@ -106,5 +106,5 @@ bar: .section bar-"foo" .section "foo" -// CHECK: ('sh_name', 0x0000008a) # 'bar-"foo"' -// CHECK: ('sh_name', 0x00000094) # 'foo' +// CHECK: ('sh_name', 0x000000ab) # 'bar-"foo"' +// CHECK: ('sh_name', 0x00000034) # 'foo' diff --git a/test/MC/ELF/symref.s b/test/MC/ELF/symref.s index b99e71b869bd..d945c826d74f 100644 --- a/test/MC/ELF/symref.s +++ b/test/MC/ELF/symref.s @@ -22,6 +22,38 @@ defined3: global1: +// CHECK: # Relocation 0x00000000 +// CHECK-NEXT: (('r_offset', 0x00000000) +// CHECK-NEXT: ('r_sym', 0x00000006) +// CHECK-NEXT: ('r_type', 0x0000000a) +// CHECK-NEXT: ('r_addend', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Relocation 0x00000001 +// CHECK-NEXT: (('r_offset', 0x00000004) +// CHECK-NEXT: ('r_sym', 0x0000000b) +// CHECK-NEXT: ('r_type', 0x0000000a) +// CHECK-NEXT: ('r_addend', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Relocation 0x00000002 +// CHECK-NEXT: (('r_offset', 0x00000008) +// CHECK-NEXT: ('r_sym', 0x00000006) +// CHECK-NEXT: ('r_type', 0x0000000a) +// CHECK-NEXT: ('r_addend', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Relocation 0x00000003 +// CHECK-NEXT: (('r_offset', 0x0000000c) +// CHECK-NEXT: ('r_sym', 0x00000006) +// CHECK-NEXT: ('r_type', 0x0000000a) +// CHECK-NEXT: ('r_addend', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT: # Relocation 0x00000004 +// CHECK-NEXT: (('r_offset', 0x00000010) +// CHECK-NEXT: ('r_sym', 0x0000000c) +// CHECK-NEXT: ('r_type', 0x0000000a) +// CHECK-NEXT: ('r_addend', 0x00000000) +// CHECK-NEXT: ), +// CHECK-NEXT:]) + // CHECK: # Symbol 0x00000001 // CHECK-NEXT: (('st_name', 0x00000013) # 'bar1@zed' // CHECK-NEXT: ('st_bind', 0x00000000) @@ -81,7 +113,7 @@ global1: // CHECK-NEXT: ('st_bind', 0x00000000) // CHECK-NEXT: ('st_type', 0x00000003) // CHECK-NEXT: ('st_other', 0x00000000) -// CHECK-NEXT: ('st_shndx', 0x00000002) +// CHECK-NEXT: ('st_shndx', 0x00000003) // CHECK-NEXT: ('st_value', 0x0000000000000000) // CHECK-NEXT: ('st_size', 0x0000000000000000) // CHECK-NEXT: ), @@ -90,7 +122,7 @@ global1: // CHECK-NEXT: ('st_bind', 0x00000000) // CHECK-NEXT: ('st_type', 0x00000003) // CHECK-NEXT: ('st_other', 0x00000000) -// CHECK-NEXT: ('st_shndx', 0x00000003) +// CHECK-NEXT: ('st_shndx', 0x00000004) // CHECK-NEXT: ('st_value', 0x0000000000000000) // CHECK-NEXT: ('st_size', 0x0000000000000000) // CHECK-NEXT: ), @@ -131,35 +163,3 @@ global1: // CHECK-NEXT: ('st_size', 0x0000000000000000) // CHECK-NEXT: ), // CHECK-NEXT:]) - -// CHECK: # Relocation 0x00000000 -// CHECK-NEXT: (('r_offset', 0x00000000) -// CHECK-NEXT: ('r_sym', 0x00000006) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', 0x00000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 0x00000001 -// CHECK-NEXT: (('r_offset', 0x00000004) -// CHECK-NEXT: ('r_sym', 0x0000000b) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', 0x00000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 0x00000002 -// CHECK-NEXT: (('r_offset', 0x00000008) -// CHECK-NEXT: ('r_sym', 0x00000006) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', 0x00000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 0x00000003 -// CHECK-NEXT: (('r_offset', 0x0000000c) -// CHECK-NEXT: ('r_sym', 0x00000006) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', 0x00000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 0x00000004 -// CHECK-NEXT: (('r_offset', 0x00000010) -// CHECK-NEXT: ('r_sym', 0x0000000c) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', 0x00000000) -// CHECK-NEXT: ), -// CHECK-NEXT:]) diff --git a/test/MC/ELF/tls-i386.s b/test/MC/ELF/tls-i386.s index 459d4cc69df9..c754121cd694 100644 --- a/test/MC/ELF/tls-i386.s +++ b/test/MC/ELF/tls-i386.s @@ -8,6 +8,7 @@ movl foo4@TLSLDM(%eax), %eax movl foo5@TPOFF(%eax), %eax movl foo6@DTPOFF(%eax), %eax + movl foo7@INDNTPOFF, %eax // CHECK: (('st_name', 0x00000001) # 'foo1' // CHECK-NEXT: ('st_value', 0x00000000) @@ -62,3 +63,12 @@ // CHECK-NEXT: ('st_other', 0x00000000) // CHECK-NEXT: ('st_shndx', 0x00000000) // CHECK-NEXT: ), +// CHECK-NEXT: # Symbol 0x0000000b +// CHECK-NEXT: (('st_name', 0x0000001f) # 'foo7' +// CHECK-NEXT: ('st_value', 0x00000000) +// CHECK-NEXT: ('st_size', 0x00000000) +// CHECK-NEXT: ('st_bind', 0x00000001) +// CHECK-NEXT: ('st_type', 0x00000006) +// CHECK-NEXT: ('st_other', 0x00000000) +// CHECK-NEXT: ('st_shndx', 0x00000000) +// CHECK-NEXT: ), diff --git a/test/MC/ELF/tls.s b/test/MC/ELF/tls.s index 2517a5bddc1f..f9d6425f10e9 100644 --- a/test/MC/ELF/tls.s +++ b/test/MC/ELF/tls.s @@ -14,7 +14,7 @@ foobar: // CHECK-NEXT: ('st_bind', 0x00000000) // CHECK-NEXT: ('st_type', 0x00000006) // CHECK-NEXT: ('st_other', 0x00000000) -// CHECK-NEXT: ('st_shndx', 0x00000004) +// CHECK-NEXT: ('st_shndx', 0x00000005) // CHECK-NEXT: ('st_value', 0x0000000000000000) // CHECK-NEXT: ('st_size', 0x0000000000000000) // CHECK-NEXT: ), diff --git a/test/MC/ELF/undef2.s b/test/MC/ELF/undef2.s index 9544fbc42ac8..6ce269bec2eb 100644 --- a/test/MC/ELF/undef2.s +++ b/test/MC/ELF/undef2.s @@ -7,4 +7,4 @@ // CHECK: ('_symbols', [ // CHECK: (('st_name', 0x00000001) # '.Lfoo' // CHECK-NEXT: ('st_bind', 0x00000001) -// CHECK: (('sh_name', 0x00000024) # '.strtab' +// CHECK: (('sh_name', 0x0000001b) # '.strtab' diff --git a/test/MC/ELF/weak-relocation.s b/test/MC/ELF/weak-relocation.s new file mode 100644 index 000000000000..ef331d7e6da2 --- /dev/null +++ b/test/MC/ELF/weak-relocation.s @@ -0,0 +1,15 @@ +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s + +// Test that weak symbols always produce relocations + + .weak foo +foo: +bar: + call foo + +//CHECK: # Relocation 0x00000000 +//CHECK-NEXT: (('r_offset', 0x00000001) +//CHECK-NEXT: ('r_sym', 0x00000005) +//CHECK-NEXT: ('r_type', 0x00000002) +//CHECK-NEXT: ('r_addend', 0xfffffffc) +//CHECK-NEXT: ), diff --git a/test/MC/ELF/weakref-reloc.s b/test/MC/ELF/weakref-reloc.s index c7cd7649d6f0..63c1f5ea2592 100644 --- a/test/MC/ELF/weakref-reloc.s +++ b/test/MC/ELF/weakref-reloc.s @@ -7,6 +7,19 @@ call zed@PLT call bar +// CHECK: # Relocation 0x00000000 +// CHECK-NEXT: (('r_offset', 0x00000001) +// CHECK-NEXT: ('r_sym', 0x00000006) +// CHECK-NEXT: ('r_type', 0x00000004) +// CHECK-NEXT: ('r_addend', 0xfffffffc) +// CHECK-NEXT: ), +// CHECK-NEXT: # Relocation 0x00000001 +// CHECK-NEXT: (('r_offset', 0x00000006) +// CHECK-NEXT: ('r_sym', 0x00000005) +// CHECK-NEXT: ('r_type', 0x00000002) +// CHECK-NEXT: ('r_addend', 0xfffffffc) +// CHECK-NEXT: ), + // CHECK: # Symbol 0x00000004 // CHECK-NEXT: (('st_name', 0x00000009) # '_GLOBAL_OFFSET_TABLE_' // CHECK-NEXT: ('st_bind', 0x00000001) @@ -34,16 +47,3 @@ // CHECK-NEXT: ('st_value', 0x0000000000000000) // CHECK-NEXT: ('st_size', 0x0000000000000000) // CHECK-NEXT: ), - -// CHECK: # Relocation 0x00000000 -// CHECK-NEXT: (('r_offset', 0x00000001) -// CHECK-NEXT: ('r_sym', 0x00000006) -// CHECK-NEXT: ('r_type', 0x00000004) -// CHECK-NEXT: ('r_addend', 0xfffffffc) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 0x00000001 -// CHECK-NEXT: (('r_offset', 0x00000006) -// CHECK-NEXT: ('r_sym', 0x00000005) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0xfffffffc) -// CHECK-NEXT: ), diff --git a/test/MC/ELF/weakref.s b/test/MC/ELF/weakref.s index aea10d1d9294..9100073551a2 100644 --- a/test/MC/ELF/weakref.s +++ b/test/MC/ELF/weakref.s @@ -128,7 +128,7 @@ bar15: // CHECK-NEXT: ('st_bind', 0x00000000) // CHECK-NEXT: ('st_type', 0x00000003) // CHECK-NEXT: ('st_other', 0x00000000) -// CHECK-NEXT: ('st_shndx', 0x00000002) +// CHECK-NEXT: ('st_shndx', 0x00000003) // CHECK-NEXT: ('st_value', 0x0000000000000000) // CHECK-NEXT: ('st_size', 0x0000000000000000) // CHECK-NEXT: ), @@ -137,7 +137,7 @@ bar15: // CHECK-NEXT: ('st_bind', 0x00000000) // CHECK-NEXT: ('st_type', 0x00000003) // CHECK-NEXT: ('st_other', 0x00000000) -// CHECK-NEXT: ('st_shndx', 0x00000003) +// CHECK-NEXT: ('st_shndx', 0x00000004) // CHECK-NEXT: ('st_value', 0x0000000000000000) // CHECK-NEXT: ('st_size', 0x0000000000000000) // CHECK-NEXT: ), diff --git a/test/MC/MachO/darwin-x86_64-diff-relocs.s b/test/MC/MachO/darwin-x86_64-diff-relocs.s index 449d2f593e73..f5d93ae6c0b9 100644 --- a/test/MC/MachO/darwin-x86_64-diff-relocs.s +++ b/test/MC/MachO/darwin-x86_64-diff-relocs.s @@ -157,7 +157,7 @@ L3: // FIXME: Unfortunately, we do not get these relocations in exactly the same // order as Darwin 'as'. It turns out that 'as' *usually* ends up emitting // them in reverse address order, but sometimes it allocates some -// additional relocations late so these end up preceed the other entries. I +// additional relocations late so these end up precede the other entries. I // haven't figured out the exact criteria for this yet. // CHECK: (('word-0', 0x56), diff --git a/test/MC/MachO/section-attributes.s b/test/MC/MachO/section-attributes.s new file mode 100644 index 000000000000..b21ef38ac561 --- /dev/null +++ b/test/MC/MachO/section-attributes.s @@ -0,0 +1,7 @@ +// RUN: llvm-mc -triple i386-apple-darwin9 %s -filetype=obj -o %t +// RUN: macho-dump %t | FileCheck %s + +// CHECK: # Section 1 +// CHECK: ('flags', 0x0) +.section __TEXT,__objc_opt_ro +.long 0 diff --git a/test/MC/MachO/temp-labels.s b/test/MC/MachO/temp-labels.s new file mode 100644 index 000000000000..b7382b7d2c82 --- /dev/null +++ b/test/MC/MachO/temp-labels.s @@ -0,0 +1,33 @@ +// RUN: llvm-mc -triple x86_64-apple-darwin10 %s -filetype=obj -L -o - | macho-dump --dump-section-data | FileCheck %s + +// CHECK: # Load Command 1 +// CHECK: (('command', 2) +// CHECK: ('size', 24) +// CHECK: ('symoff', 296) +// CHECK: ('nsyms', 2) +// CHECK: ('stroff', 328) +// CHECK: ('strsize', 8) +// CHECK: ('_string_data', '\x00_f0\x00L0\x00') +// CHECK: ('_symbols', [ +// CHECK: # Symbol 0 +// CHECK: (('n_strx', 1) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 1) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 0) +// CHECK: ('_string', '_f0') +// CHECK: ), +// CHECK: # Symbol 1 +// CHECK: (('n_strx', 5) +// CHECK: ('n_type', 0xe) +// CHECK: ('n_sect', 1) +// CHECK: ('n_desc', 0) +// CHECK: ('n_value', 4) +// CHECK: ('_string', 'L0') +// CHECK: ), +// CHECK: ]) +// CHECK: ), +_f0: + .long 0 +L0: + .long 0 diff --git a/test/MC/MachO/variable-errors.s b/test/MC/MachO/variable-errors.s new file mode 100644 index 000000000000..28308c691d91 --- /dev/null +++ b/test/MC/MachO/variable-errors.s @@ -0,0 +1,8 @@ +// RUN: not llvm-mc -triple x86_64-apple-darwin10 %s -filetype=obj -o %t.o 2> %t.err +// RUN: FileCheck < %t.err %s + + .data +t0_a: +t0_x = t0_a - t0_b +// CHECK: unable to evaluate offset to undefined symbol 't0_b' + .long t0_x diff --git a/test/MC/MachO/variable-exprs.s b/test/MC/MachO/variable-exprs.s new file mode 100644 index 000000000000..8eeb82f0faf7 --- /dev/null +++ b/test/MC/MachO/variable-exprs.s @@ -0,0 +1,446 @@ +// RUN: llvm-mc -triple i386-apple-darwin10 %s -filetype=obj -o %t.o +// RUN: macho-dump --dump-section-data < %t.o > %t.dump +// RUN: FileCheck --check-prefix=CHECK-I386 < %t.dump %s + +// RUN: llvm-mc -triple x86_64-apple-darwin10 %s -filetype=obj -o %t.o +// RUN: macho-dump --dump-section-data < %t.o > %t.dump +// RUN: FileCheck --check-prefix=CHECK-X86_64 < %t.dump %s + +.data + + .long 0 +a: + .long 0 +b = a + +c: .long b + +d2 = d +.globl d2 +d3 = d + 4 +.globl d3 + +e = a + 4 + +g: +f = g + .long 0 + + .long b + .long e + .long a + 4 + .long d + .long d2 + .long d3 + .long f + .long g + +/// + .text +t0: +Lt0_a: + ret + + .data +Lt0_b: +Lt0_x = Lt0_a - Lt0_b + .quad Lt0_x + +// CHECK-I386: ('cputype', 7) +// CHECK-I386: ('cpusubtype', 3) +// CHECK-I386: ('filetype', 1) +// CHECK-I386: ('num_load_commands', 3) +// CHECK-I386: ('load_commands_size', 296) +// CHECK-I386: ('flag', 0) +// CHECK-I386: ('load_commands', [ +// CHECK-I386: # Load Command 0 +// CHECK-I386: (('command', 1) +// CHECK-I386: ('size', 192) +// CHECK-I386: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK-I386: ('vm_addr', 0) +// CHECK-I386: ('vm_size', 57) +// CHECK-I386: ('file_offset', 324) +// CHECK-I386: ('file_size', 57) +// CHECK-I386: ('maxprot', 7) +// CHECK-I386: ('initprot', 7) +// CHECK-I386: ('num_sections', 2) +// CHECK-I386: ('flags', 0) +// CHECK-I386: ('sections', [ +// CHECK-I386: # Section 0 +// CHECK-I386: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK-I386: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK-I386: ('address', 0) +// CHECK-I386: ('size', 1) +// CHECK-I386: ('offset', 324) +// CHECK-I386: ('alignment', 0) +// CHECK-I386: ('reloc_offset', 0) +// CHECK-I386: ('num_reloc', 0) +// CHECK-I386: ('flags', 0x80000400) +// CHECK-I386: ('reserved1', 0) +// CHECK-I386: ('reserved2', 0) +// CHECK-I386: ), +// CHECK-I386: ('_relocations', [ +// CHECK-I386: ]) +// CHECK-I386: ('_section_data', 'c3') +// CHECK-I386: # Section 1 +// CHECK-I386: (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK-I386: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK-I386: ('address', 1) +// CHECK-I386: ('size', 56) +// CHECK-I386: ('offset', 325) +// CHECK-I386: ('alignment', 0) +// CHECK-I386: ('reloc_offset', 384) +// CHECK-I386: ('num_reloc', 9) +// CHECK-I386: ('flags', 0x0) +// CHECK-I386: ('reserved1', 0) +// CHECK-I386: ('reserved2', 0) +// CHECK-I386: ), +// CHECK-I386: ('_relocations', [ +// CHECK-I386: # Relocation 0 +// CHECK-I386: (('word-0', 0x2c), +// CHECK-I386: ('word-1', 0x4000002)), +// CHECK-I386: # Relocation 1 +// CHECK-I386: (('word-0', 0x28), +// CHECK-I386: ('word-1', 0x4000002)), +// CHECK-I386: # Relocation 2 +// CHECK-I386: (('word-0', 0x24), +// CHECK-I386: ('word-1', 0xc000009)), +// CHECK-I386: # Relocation 3 +// CHECK-I386: (('word-0', 0x20), +// CHECK-I386: ('word-1', 0xc000008)), +// CHECK-I386: # Relocation 4 +// CHECK-I386: (('word-0', 0x1c), +// CHECK-I386: ('word-1', 0xc000007)), +// CHECK-I386: # Relocation 5 +// CHECK-I386: (('word-0', 0xa0000018), +// CHECK-I386: ('word-1', 0x5)), +// CHECK-I386: # Relocation 6 +// CHECK-I386: (('word-0', 0x14), +// CHECK-I386: ('word-1', 0x4000002)), +// CHECK-I386: # Relocation 7 +// CHECK-I386: (('word-0', 0x10), +// CHECK-I386: ('word-1', 0x4000002)), +// CHECK-I386: # Relocation 8 +// CHECK-I386: (('word-0', 0x8), +// CHECK-I386: ('word-1', 0x4000002)), +// CHECK-I386: ]) +// CHECK-I386: ('_section_data', '00000000 00000000 05000000 00000000 05000000 09000000 09000000 00000000 00000000 00000000 0d000000 0d000000 cfffffff ffffffff') +// CHECK-I386: ]) +// CHECK-I386: ), +// CHECK-I386: # Load Command 1 +// CHECK-I386: (('command', 2) +// CHECK-I386: ('size', 24) +// CHECK-I386: ('symoff', 456) +// CHECK-I386: ('nsyms', 10) +// CHECK-I386: ('stroff', 576) +// CHECK-I386: ('strsize', 24) +// CHECK-I386: ('_string_data', '\x00d2\x00d\x00d3\x00a\x00b\x00c\x00e\x00g\x00f\x00t0\x00') +// CHECK-I386: ('_symbols', [ +// CHECK-I386: # Symbol 0 +// CHECK-I386: (('n_strx', 9) +// CHECK-I386: ('n_type', 0xe) +// CHECK-I386: ('n_sect', 2) +// CHECK-I386: ('n_desc', 0) +// CHECK-I386: ('n_value', 5) +// CHECK-I386: ('_string', 'a') +// CHECK-I386: ), +// CHECK-I386: # Symbol 1 +// CHECK-I386: (('n_strx', 11) +// CHECK-I386: ('n_type', 0xe) +// CHECK-I386: ('n_sect', 2) +// CHECK-I386: ('n_desc', 0) +// CHECK-I386: ('n_value', 5) +// CHECK-I386: ('_string', 'b') +// CHECK-I386: ), +// CHECK-I386: # Symbol 2 +// CHECK-I386: (('n_strx', 13) +// CHECK-I386: ('n_type', 0xe) +// CHECK-I386: ('n_sect', 2) +// CHECK-I386: ('n_desc', 0) +// CHECK-I386: ('n_value', 9) +// CHECK-I386: ('_string', 'c') +// CHECK-I386: ), +// CHECK-I386: # Symbol 3 +// CHECK-I386: (('n_strx', 15) +// CHECK-I386: ('n_type', 0xe) +// CHECK-I386: ('n_sect', 2) +// CHECK-I386: ('n_desc', 0) +// CHECK-I386: ('n_value', 9) +// CHECK-I386: ('_string', 'e') +// CHECK-I386: ), +// CHECK-I386: # Symbol 4 +// CHECK-I386: (('n_strx', 17) +// CHECK-I386: ('n_type', 0xe) +// CHECK-I386: ('n_sect', 2) +// CHECK-I386: ('n_desc', 0) +// CHECK-I386: ('n_value', 13) +// CHECK-I386: ('_string', 'g') +// CHECK-I386: ), +// CHECK-I386: # Symbol 5 +// CHECK-I386: (('n_strx', 19) +// CHECK-I386: ('n_type', 0xe) +// CHECK-I386: ('n_sect', 2) +// CHECK-I386: ('n_desc', 0) +// CHECK-I386: ('n_value', 13) +// CHECK-I386: ('_string', 'f') +// CHECK-I386: ), +// CHECK-I386: # Symbol 6 +// CHECK-I386: (('n_strx', 21) +// CHECK-I386: ('n_type', 0xe) +// CHECK-I386: ('n_sect', 1) +// CHECK-I386: ('n_desc', 0) +// CHECK-I386: ('n_value', 0) +// CHECK-I386: ('_string', 't0') +// CHECK-I386: ), +// CHECK-I386: # Symbol 7 +// CHECK-I386: (('n_strx', 4) +// CHECK-I386: ('n_type', 0x1) +// CHECK-I386: ('n_sect', 0) +// CHECK-I386: ('n_desc', 0) +// CHECK-I386: ('n_value', 0) +// CHECK-I386: ('_string', 'd') +// CHECK-I386: ), +// CHECK-I386: # Symbol 8 +// CHECK-I386: (('n_strx', 1) +// CHECK-I386: ('n_type', 0x1) +// CHECK-I386: ('n_sect', 0) +// CHECK-I386: ('n_desc', 0) +// CHECK-I386: ('n_value', 0) +// CHECK-I386: ('_string', 'd2') +// CHECK-I386: ), +// CHECK-I386: # Symbol 9 +// CHECK-I386: (('n_strx', 6) +// CHECK-I386: ('n_type', 0x1) +// CHECK-I386: ('n_sect', 0) +// CHECK-I386: ('n_desc', 0) +// CHECK-I386: ('n_value', 0) +// CHECK-I386: ('_string', 'd3') +// CHECK-I386: ), +// CHECK-I386: ]) +// CHECK-I386: ), +// CHECK-I386: # Load Command 2 +// CHECK-I386: (('command', 11) +// CHECK-I386: ('size', 80) +// CHECK-I386: ('ilocalsym', 0) +// CHECK-I386: ('nlocalsym', 7) +// CHECK-I386: ('iextdefsym', 7) +// CHECK-I386: ('nextdefsym', 0) +// CHECK-I386: ('iundefsym', 7) +// CHECK-I386: ('nundefsym', 3) +// CHECK-I386: ('tocoff', 0) +// CHECK-I386: ('ntoc', 0) +// CHECK-I386: ('modtaboff', 0) +// CHECK-I386: ('nmodtab', 0) +// CHECK-I386: ('extrefsymoff', 0) +// CHECK-I386: ('nextrefsyms', 0) +// CHECK-I386: ('indirectsymoff', 0) +// CHECK-I386: ('nindirectsyms', 0) +// CHECK-I386: ('extreloff', 0) +// CHECK-I386: ('nextrel', 0) +// CHECK-I386: ('locreloff', 0) +// CHECK-I386: ('nlocrel', 0) +// CHECK-I386: ('_indirect_symbols', [ +// CHECK-I386: ]) +// CHECK-I386: ), +// CHECK-I386: ]) + +// CHECK-X86_64: ('cputype', 16777223) +// CHECK-X86_64: ('cpusubtype', 3) +// CHECK-X86_64: ('filetype', 1) +// CHECK-X86_64: ('num_load_commands', 3) +// CHECK-X86_64: ('load_commands_size', 336) +// CHECK-X86_64: ('flag', 0) +// CHECK-X86_64: ('reserved', 0) +// CHECK-X86_64: ('load_commands', [ +// CHECK-X86_64: # Load Command 0 +// CHECK-X86_64: (('command', 25) +// CHECK-X86_64: ('size', 232) +// CHECK-X86_64: ('segment_name', '\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK-X86_64: ('vm_addr', 0) +// CHECK-X86_64: ('vm_size', 57) +// CHECK-X86_64: ('file_offset', 368) +// CHECK-X86_64: ('file_size', 57) +// CHECK-X86_64: ('maxprot', 7) +// CHECK-X86_64: ('initprot', 7) +// CHECK-X86_64: ('num_sections', 2) +// CHECK-X86_64: ('flags', 0) +// CHECK-X86_64: ('sections', [ +// CHECK-X86_64: # Section 0 +// CHECK-X86_64: (('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK-X86_64: ('segment_name', '__TEXT\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK-X86_64: ('address', 0) +// CHECK-X86_64: ('size', 1) +// CHECK-X86_64: ('offset', 368) +// CHECK-X86_64: ('alignment', 0) +// CHECK-X86_64: ('reloc_offset', 0) +// CHECK-X86_64: ('num_reloc', 0) +// CHECK-X86_64: ('flags', 0x80000400) +// CHECK-X86_64: ('reserved1', 0) +// CHECK-X86_64: ('reserved2', 0) +// CHECK-X86_64: ('reserved3', 0) +// CHECK-X86_64: ), +// CHECK-X86_64: ('_relocations', [ +// CHECK-X86_64: ]) +// CHECK-X86_64: ('_section_data', 'c3') +// CHECK-X86_64: # Section 1 +// CHECK-X86_64: (('section_name', '__data\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK-X86_64: ('segment_name', '__DATA\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') +// CHECK-X86_64: ('address', 1) +// CHECK-X86_64: ('size', 56) +// CHECK-X86_64: ('offset', 369) +// CHECK-X86_64: ('alignment', 0) +// CHECK-X86_64: ('reloc_offset', 428) +// CHECK-X86_64: ('num_reloc', 9) +// CHECK-X86_64: ('flags', 0x0) +// CHECK-X86_64: ('reserved1', 0) +// CHECK-X86_64: ('reserved2', 0) +// CHECK-X86_64: ('reserved3', 0) +// CHECK-X86_64: ), +// CHECK-X86_64: ('_relocations', [ +// CHECK-X86_64: # Relocation 0 +// CHECK-X86_64: (('word-0', 0x2c), +// CHECK-X86_64: ('word-1', 0xc000004)), +// CHECK-X86_64: # Relocation 1 +// CHECK-X86_64: (('word-0', 0x28), +// CHECK-X86_64: ('word-1', 0xc000005)), +// CHECK-X86_64: # Relocation 2 +// CHECK-X86_64: (('word-0', 0x24), +// CHECK-X86_64: ('word-1', 0xc000009)), +// CHECK-X86_64: # Relocation 3 +// CHECK-X86_64: (('word-0', 0x20), +// CHECK-X86_64: ('word-1', 0xc000008)), +// CHECK-X86_64: # Relocation 4 +// CHECK-X86_64: (('word-0', 0x1c), +// CHECK-X86_64: ('word-1', 0xc000007)), +// CHECK-X86_64: # Relocation 5 +// CHECK-X86_64: (('word-0', 0x18), +// CHECK-X86_64: ('word-1', 0xc000000)), +// CHECK-X86_64: # Relocation 6 +// CHECK-X86_64: (('word-0', 0x14), +// CHECK-X86_64: ('word-1', 0xc000003)), +// CHECK-X86_64: # Relocation 7 +// CHECK-X86_64: (('word-0', 0x10), +// CHECK-X86_64: ('word-1', 0xc000001)), +// CHECK-X86_64: # Relocation 8 +// CHECK-X86_64: (('word-0', 0x8), +// CHECK-X86_64: ('word-1', 0xc000001)), +// CHECK-X86_64: ]) +// CHECK-X86_64: ('_section_data', '00000000 00000000 00000000 00000000 00000000 00000000 04000000 00000000 00000000 00000000 00000000 00000000 cfffffff ffffffff') +// CHECK-X86_64: ]) +// CHECK-X86_64: ), +// CHECK-X86_64: # Load Command 1 +// CHECK-X86_64: (('command', 2) +// CHECK-X86_64: ('size', 24) +// CHECK-X86_64: ('symoff', 500) +// CHECK-X86_64: ('nsyms', 10) +// CHECK-X86_64: ('stroff', 660) +// CHECK-X86_64: ('strsize', 24) +// CHECK-X86_64: ('_string_data', '\x00d2\x00d\x00d3\x00a\x00b\x00c\x00e\x00g\x00f\x00t0\x00') +// CHECK-X86_64: ('_symbols', [ +// CHECK-X86_64: # Symbol 0 +// CHECK-X86_64: (('n_strx', 9) +// CHECK-X86_64: ('n_type', 0xe) +// CHECK-X86_64: ('n_sect', 2) +// CHECK-X86_64: ('n_desc', 0) +// CHECK-X86_64: ('n_value', 5) +// CHECK-X86_64: ('_string', 'a') +// CHECK-X86_64: ), +// CHECK-X86_64: # Symbol 1 +// CHECK-X86_64: (('n_strx', 11) +// CHECK-X86_64: ('n_type', 0xe) +// CHECK-X86_64: ('n_sect', 2) +// CHECK-X86_64: ('n_desc', 0) +// CHECK-X86_64: ('n_value', 5) +// CHECK-X86_64: ('_string', 'b') +// CHECK-X86_64: ), +// CHECK-X86_64: # Symbol 2 +// CHECK-X86_64: (('n_strx', 13) +// CHECK-X86_64: ('n_type', 0xe) +// CHECK-X86_64: ('n_sect', 2) +// CHECK-X86_64: ('n_desc', 0) +// CHECK-X86_64: ('n_value', 9) +// CHECK-X86_64: ('_string', 'c') +// CHECK-X86_64: ), +// CHECK-X86_64: # Symbol 3 +// CHECK-X86_64: (('n_strx', 15) +// CHECK-X86_64: ('n_type', 0xe) +// CHECK-X86_64: ('n_sect', 2) +// CHECK-X86_64: ('n_desc', 0) +// CHECK-X86_64: ('n_value', 9) +// CHECK-X86_64: ('_string', 'e') +// CHECK-X86_64: ), +// CHECK-X86_64: # Symbol 4 +// CHECK-X86_64: (('n_strx', 17) +// CHECK-X86_64: ('n_type', 0xe) +// CHECK-X86_64: ('n_sect', 2) +// CHECK-X86_64: ('n_desc', 0) +// CHECK-X86_64: ('n_value', 13) +// CHECK-X86_64: ('_string', 'g') +// CHECK-X86_64: ), +// CHECK-X86_64: # Symbol 5 +// CHECK-X86_64: (('n_strx', 19) +// CHECK-X86_64: ('n_type', 0xe) +// CHECK-X86_64: ('n_sect', 2) +// CHECK-X86_64: ('n_desc', 0) +// CHECK-X86_64: ('n_value', 13) +// CHECK-X86_64: ('_string', 'f') +// CHECK-X86_64: ), +// CHECK-X86_64: # Symbol 6 +// CHECK-X86_64: (('n_strx', 21) +// CHECK-X86_64: ('n_type', 0xe) +// CHECK-X86_64: ('n_sect', 1) +// CHECK-X86_64: ('n_desc', 0) +// CHECK-X86_64: ('n_value', 0) +// CHECK-X86_64: ('_string', 't0') +// CHECK-X86_64: ), +// CHECK-X86_64: # Symbol 7 +// CHECK-X86_64: (('n_strx', 4) +// CHECK-X86_64: ('n_type', 0x1) +// CHECK-X86_64: ('n_sect', 0) +// CHECK-X86_64: ('n_desc', 0) +// CHECK-X86_64: ('n_value', 0) +// CHECK-X86_64: ('_string', 'd') +// CHECK-X86_64: ), +// CHECK-X86_64: # Symbol 8 +// CHECK-X86_64: (('n_strx', 1) +// CHECK-X86_64: ('n_type', 0x1) +// CHECK-X86_64: ('n_sect', 0) +// CHECK-X86_64: ('n_desc', 0) +// CHECK-X86_64: ('n_value', 0) +// CHECK-X86_64: ('_string', 'd2') +// CHECK-X86_64: ), +// CHECK-X86_64: # Symbol 9 +// CHECK-X86_64: (('n_strx', 6) +// CHECK-X86_64: ('n_type', 0x1) +// CHECK-X86_64: ('n_sect', 0) +// CHECK-X86_64: ('n_desc', 0) +// CHECK-X86_64: ('n_value', 0) +// CHECK-X86_64: ('_string', 'd3') +// CHECK-X86_64: ), +// CHECK-X86_64: ]) +// CHECK-X86_64: ), +// CHECK-X86_64: # Load Command 2 +// CHECK-X86_64: (('command', 11) +// CHECK-X86_64: ('size', 80) +// CHECK-X86_64: ('ilocalsym', 0) +// CHECK-X86_64: ('nlocalsym', 7) +// CHECK-X86_64: ('iextdefsym', 7) +// CHECK-X86_64: ('nextdefsym', 0) +// CHECK-X86_64: ('iundefsym', 7) +// CHECK-X86_64: ('nundefsym', 3) +// CHECK-X86_64: ('tocoff', 0) +// CHECK-X86_64: ('ntoc', 0) +// CHECK-X86_64: ('modtaboff', 0) +// CHECK-X86_64: ('nmodtab', 0) +// CHECK-X86_64: ('extrefsymoff', 0) +// CHECK-X86_64: ('nextrefsyms', 0) +// CHECK-X86_64: ('indirectsymoff', 0) +// CHECK-X86_64: ('nindirectsyms', 0) +// CHECK-X86_64: ('extreloff', 0) +// CHECK-X86_64: ('nextrel', 0) +// CHECK-X86_64: ('locreloff', 0) +// CHECK-X86_64: ('nlocrel', 0) +// CHECK-X86_64: ('_indirect_symbols', [ +// CHECK-X86_64: ]) +// CHECK-X86_64: ), +// CHECK-X86_64: ]) diff --git a/test/MC/X86/padlock.s b/test/MC/X86/padlock.s new file mode 100644 index 000000000000..874786f9071d --- /dev/null +++ b/test/MC/X86/padlock.s @@ -0,0 +1,53 @@ +// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s + + xstore +// CHECK: xstore +// CHECK: encoding: [0x0f,0xa7,0xc0] + + rep xcryptecb +// CHECK: rep +// CHECK: encoding: [0xf3] +// CHECK: xcryptecb +// CHECK: encoding: [0x0f,0xa7,0xc8] + + rep xcryptcbc +// CHECK: rep +// CHECK: encoding: [0xf3] +// CHECK: xcryptcbc +// CHECK: encoding: [0x0f,0xa7,0xd0] + + rep xcryptctr +// CHECK: rep +// CHECK: encoding: [0xf3] +// CHECK: xcryptctr +// CHECK: encoding: [0x0f,0xa7,0xd8] + + rep xcryptcfb +// CHECK: rep +// CHECK: encoding: [0xf3] +// CHECK: xcryptcfb +// CHECK: encoding: [0x0f,0xa7,0xe0] + + rep xcryptofb +// CHECK: rep +// CHECK: encoding: [0xf3] +// CHECK: xcryptofb +// CHECK: encoding: [0x0f,0xa7,0xe8] + + rep xsha1 +// CHECK: rep +// CHECK: encoding: [0xf3] +// CHECK: xsha1 +// CHECK: encoding: [0x0f,0xa6,0xc8] + + rep xsha256 +// CHECK: rep +// CHECK: encoding: [0xf3] +// CHECK: xsha256 +// CHECK: encoding: [0x0f,0xa6,0xd0] + + rep montmul +// CHECK: rep +// CHECK: encoding: [0xf3] +// CHECK: montmul +// CHECK: encoding: [0x0f,0xa6,0xc0] diff --git a/test/MC/X86/x86-32-coverage.s b/test/MC/X86/x86-32-coverage.s index 4ec9fcdb1ee5..4ac7efda01d6 100644 --- a/test/MC/X86/x86-32-coverage.s +++ b/test/MC/X86/x86-32-coverage.s @@ -372,6 +372,14 @@ // CHECK: nop nop +// CHECK: flds (%edi) +// CHECK: encoding: [0xd9,0x07] + flds (%edi) + +// CHECK: filds (%edi) +// CHECK: encoding: [0xdf,0x07] + filds (%edi) + // CHECK: fldl 3735928559(%ebx,%ecx,8) fldl 0xdeadbeef(%ebx,%ecx,8) diff --git a/test/MC/X86/x86-32.s b/test/MC/X86/x86-32.s index 723983da6de6..28900bb7fd93 100644 --- a/test/MC/X86/x86-32.s +++ b/test/MC/X86/x86-32.s @@ -613,11 +613,11 @@ pshufw $90, %mm4, %mm0 // CHECK: encoding: [0xd5,0x01] aad $1 -// CHECK: aad $10 +// CHECK: aad // CHECK: encoding: [0xd5,0x0a] aad $0xA -// CHECK: aad $10 +// CHECK: aad // CHECK: encoding: [0xd5,0x0a] aad @@ -625,11 +625,11 @@ pshufw $90, %mm4, %mm0 // CHECK: encoding: [0xd4,0x02] aam $2 -// CHECK: aam $10 +// CHECK: aam // CHECK: encoding: [0xd4,0x0a] aam $0xA -// CHECK: aam $10 +// CHECK: aam // CHECK: encoding: [0xd4,0x0a] aam @@ -725,7 +725,7 @@ pshufw $90, %mm4, %mm0 // CHECK: encoding: [0xdf,0xf2] fcompi %st(2) -// CHECK: fcompi %st(1) +// CHECK: fcompi // CHECK: encoding: [0xdf,0xf1] fcompi @@ -737,7 +737,7 @@ pshufw $90, %mm4, %mm0 // CHECK: encoding: [0xdf,0xea] fucompi %st(2) -// CHECK: fucompi %st(1) +// CHECK: fucompi // CHECK: encoding: [0xdf,0xe9] fucompi @@ -816,3 +816,121 @@ pshufw $90, %mm4, %mm0 // CHECK: loopne 0 // CHECK: encoding: [0xe0,A] loopnz 0 + +// CHECK: outsb # encoding: [0x6e] +// CHECK: outsb +// CHECK: outsb + outsb + outsb %ds:(%esi), %dx + outsb (%esi), %dx + +// CHECK: outsw # encoding: [0x66,0x6f] +// CHECK: outsw +// CHECK: outsw + outsw + outsw %ds:(%esi), %dx + outsw (%esi), %dx + +// CHECK: outsl # encoding: [0x6f] +// CHECK: outsl + outsl + outsl %ds:(%esi), %dx + outsl (%esi), %dx + +// CHECK: insb # encoding: [0x6c] +// CHECK: insb + insb + insb %dx, %es:(%edi) + +// CHECK: insw # encoding: [0x66,0x6d] +// CHECK: insw + insw + insw %dx, %es:(%edi) + +// CHECK: insl # encoding: [0x6d] +// CHECK: insl + insl + insl %dx, %es:(%edi) + +// CHECK: movsb # encoding: [0xa4] +// CHECK: movsb +// CHECK: movsb + movsb + movsb %ds:(%esi), %es:(%edi) + movsb (%esi), %es:(%edi) + +// CHECK: movsw # encoding: [0x66,0xa5] +// CHECK: movsw +// CHECK: movsw + movsw + movsw %ds:(%esi), %es:(%edi) + movsw (%esi), %es:(%edi) + +// CHECK: movsd # encoding: [0xa5] +// CHECK: movsd +// CHECK: movsd + movsl + movsl %ds:(%esi), %es:(%edi) + movsl (%esi), %es:(%edi) + +// CHECK: lodsb # encoding: [0xac] +// CHECK: lodsb +// CHECK: lodsb +// CHECK: lodsb +// CHECK: lodsb + lodsb + lodsb %ds:(%esi), %al + lodsb (%esi), %al + lods %ds:(%esi), %al + lods (%esi), %al + +// CHECK: lodsw # encoding: [0x66,0xad] +// CHECK: lodsw +// CHECK: lodsw +// CHECK: lodsw +// CHECK: lodsw + lodsw + lodsw %ds:(%esi), %ax + lodsw (%esi), %ax + lods %ds:(%esi), %ax + lods (%esi), %ax + +// CHECK: lodsl # encoding: [0xad] +// CHECK: lodsl +// CHECK: lodsl +// CHECK: lodsl +// CHECK: lodsl + lodsl + lodsl %ds:(%esi), %eax + lodsl (%esi), %eax + lods %ds:(%esi), %eax + lods (%esi), %eax + +// CHECK: stosb # encoding: [0xaa] +// CHECK: stosb +// CHECK: stosb + stosb + stosb %al, %es:(%edi) + stos %al, %es:(%edi) + +// CHECK: stosw # encoding: [0x66,0xab] +// CHECK: stosw +// CHECK: stosw + stosw + stosw %ax, %es:(%edi) + stos %ax, %es:(%edi) + +// CHECK: stosl # encoding: [0xab] +// CHECK: stosl +// CHECK: stosl + stosl + stosl %eax, %es:(%edi) + stos %eax, %es:(%edi) + +// CHECK: strw +// CHECK: encoding: [0x66,0x0f,0x00,0xc8] + str %ax + +// CHECK: strl +// CHECK: encoding: [0x0f,0x00,0xc8] + str %eax diff --git a/test/MC/X86/x86-64.s b/test/MC/X86/x86-64.s index ee9757fa3176..fe08559be6f6 100644 --- a/test/MC/X86/x86-64.s +++ b/test/MC/X86/x86-64.s @@ -112,12 +112,12 @@ // rdar://8470918 smovb // CHECK: movsb smovw // CHECK: movsw -smovl // CHECK: movsl +smovl // CHECK: movsd smovq // CHECK: movsq // rdar://8456361 // CHECK: rep -// CHECK: movsl +// CHECK: movsd rep movsd // CHECK: rep @@ -190,6 +190,10 @@ fadd %st(7) // CHECK: int3 INT3 +// rdar://8735979 - int $3 -> int3 +// CHECK: int3 +int $3 + // Allow scale factor without index register. // CHECK: movaps %xmm3, (%esi) @@ -228,10 +232,10 @@ cmovnzq %rbx, %rax // rdar://8407928 // CHECK: inb $127, %al -// CHECK: inw %dx, %ax +// CHECK: inw %dx // CHECK: outb %al, $127 -// CHECK: outw %ax, %dx -// CHECK: inl %dx, %eax +// CHECK: outw %dx +// CHECK: inl %dx inb $0x7f inw %dx outb $0x7f @@ -240,12 +244,12 @@ inl %dx // PR8114 -// CHECK: outb %al, %dx -// CHECK: outb %al, %dx -// CHECK: outw %ax, %dx -// CHECK: outw %ax, %dx -// CHECK: outl %eax, %dx -// CHECK: outl %eax, %dx +// CHECK: outb %dx +// CHECK: outb %dx +// CHECK: outw %dx +// CHECK: outw %dx +// CHECK: outl %dx +// CHECK: outl %dx out %al, (%dx) outb %al, (%dx) @@ -254,12 +258,12 @@ outw %ax, (%dx) out %eax, (%dx) outl %eax, (%dx) -// CHECK: inb %dx, %al -// CHECK: inb %dx, %al -// CHECK: inw %dx, %ax -// CHECK: inw %dx, %ax -// CHECK: inl %dx, %eax -// CHECK: inl %dx, %eax +// CHECK: inb %dx +// CHECK: inb %dx +// CHECK: inw %dx +// CHECK: inw %dx +// CHECK: inl %dx +// CHECK: inl %dx in (%dx), %al inb (%dx), %al @@ -270,16 +274,16 @@ inl (%dx), %eax // rdar://8431422 -// CHECK: fxch %st(1) -// CHECK: fucom %st(1) -// CHECK: fucomp %st(1) -// CHECK: faddp %st(1) +// CHECK: fxch +// CHECK: fucom +// CHECK: fucomp +// CHECK: faddp // CHECK: faddp %st(0) -// CHECK: fsubp %st(1) -// CHECK: fsubrp %st(1) -// CHECK: fmulp %st(1) -// CHECK: fdivp %st(1) -// CHECK: fdivrp %st(1) +// CHECK: fsubp +// CHECK: fsubrp +// CHECK: fmulp +// CHECK: fdivp +// CHECK: fdivrp fxch fucom @@ -292,11 +296,11 @@ fmulp fdivp fdivrp -// CHECK: fcomi %st(1) +// CHECK: fcomi // CHECK: fcomi %st(2) -// CHECK: fucomi %st(1) -// CHECK: fucomi %st(2) -// CHECK: fucomi %st(2) +// CHECK: fucomi +// CHECK: fucomi %st(2) +// CHECK: fucomi %st(2) fcomi fcomi %st(2) @@ -600,7 +604,7 @@ movsq // CHECK: encoding: [0x48,0xa5] movsl -// CHECK: movsl +// CHECK: movsd // CHECK: encoding: [0xa5] stosq @@ -786,7 +790,7 @@ lock/incl 1(%rsp) rep movsl // CHECK: rep // CHECK: encoding: [0xf3] -// CHECK: movsl +// CHECK: movsd // CHECK: encoding: [0xa5] @@ -973,3 +977,154 @@ xsetbv // CHECK: xsetbv # encoding: [0x0f,0x01,0xd1] // CHECK: loopne 0 // CHECK: encoding: [0xe0,A] loopnz 0 + +// CHECK: outsb # encoding: [0x6e] +// CHECK: outsb +// CHECK: outsb + outsb + outsb %ds:(%rsi), %dx + outsb (%rsi), %dx + +// CHECK: outsw # encoding: [0x66,0x6f] +// CHECK: outsw +// CHECK: outsw + outsw + outsw %ds:(%rsi), %dx + outsw (%rsi), %dx + +// CHECK: outsl # encoding: [0x6f] +// CHECK: outsl + outsl + outsl %ds:(%rsi), %dx + outsl (%rsi), %dx + +// CHECK: insb # encoding: [0x6c] +// CHECK: insb + insb + insb %dx, %es:(%rdi) + +// CHECK: insw # encoding: [0x66,0x6d] +// CHECK: insw + insw + insw %dx, %es:(%rdi) + +// CHECK: insl # encoding: [0x6d] +// CHECK: insl + insl + insl %dx, %es:(%rdi) + +// CHECK: movsb # encoding: [0xa4] +// CHECK: movsb +// CHECK: movsb + movsb + movsb %ds:(%rsi), %es:(%rdi) + movsb (%rsi), %es:(%rdi) + +// CHECK: movsw # encoding: [0x66,0xa5] +// CHECK: movsw +// CHECK: movsw + movsw + movsw %ds:(%rsi), %es:(%rdi) + movsw (%rsi), %es:(%rdi) + +// CHECK: movsd # encoding: [0xa5] +// CHECK: movsd +// CHECK: movsd + movsl + movsl %ds:(%rsi), %es:(%rdi) + movsl (%rsi), %es:(%rdi) + +// CHECK: movsq # encoding: [0x48,0xa5] +// CHECK: movsq +// CHECK: movsq + movsq + movsq %ds:(%rsi), %es:(%rdi) + movsq (%rsi), %es:(%rdi) + +// CHECK: lodsb # encoding: [0xac] +// CHECK: lodsb +// CHECK: lodsb +// CHECK: lodsb +// CHECK: lodsb + lodsb + lodsb %ds:(%rsi), %al + lodsb (%rsi), %al + lods %ds:(%rsi), %al + lods (%rsi), %al + +// CHECK: lodsw # encoding: [0x66,0xad] +// CHECK: lodsw +// CHECK: lodsw +// CHECK: lodsw +// CHECK: lodsw + lodsw + lodsw %ds:(%rsi), %ax + lodsw (%rsi), %ax + lods %ds:(%rsi), %ax + lods (%rsi), %ax + +// CHECK: lodsl # encoding: [0xad] +// CHECK: lodsl +// CHECK: lodsl +// CHECK: lodsl +// CHECK: lodsl + lodsl + lodsl %ds:(%rsi), %eax + lodsl (%rsi), %eax + lods %ds:(%rsi), %eax + lods (%rsi), %eax + +// CHECK: lodsq # encoding: [0x48,0xad] +// CHECK: lodsq +// CHECK: lodsq +// CHECK: lodsq +// CHECK: lodsq + lodsq + lodsq %ds:(%rsi), %rax + lodsq (%rsi), %rax + lods %ds:(%rsi), %rax + lods (%rsi), %rax + +// CHECK: stosb # encoding: [0xaa] +// CHECK: stosb +// CHECK: stosb + stosb + stosb %al, %es:(%rdi) + stos %al, %es:(%rdi) + +// CHECK: stosw # encoding: [0x66,0xab] +// CHECK: stosw +// CHECK: stosw + stosw + stosw %ax, %es:(%rdi) + stos %ax, %es:(%rdi) + +// CHECK: stosl # encoding: [0xab] +// CHECK: stosl +// CHECK: stosl + stosl + stosl %eax, %es:(%rdi) + stos %eax, %es:(%rdi) + +// CHECK: stosq # encoding: [0x48,0xab] +// CHECK: stosq +// CHECK: stosq + stosq + stosq %rax, %es:(%rdi) + stos %rax, %es:(%rdi) + +// CHECK: strw +// CHECK: encoding: [0x66,0x0f,0x00,0xc8] + str %ax + +// CHECK: strl +// CHECK: encoding: [0x0f,0x00,0xc8] + str %eax + +// CHECK: strw +// CHECK: encoding: [0x66,0x0f,0x00,0xc8] + str %ax + +// CHECK: strq +// CHECK: encoding: [0x48,0x0f,0x00,0xc8] + str %rax diff --git a/test/MC/X86/x86_64-encoding.s b/test/MC/X86/x86_64-encoding.s index 756da4dc352d..cfdf87f3e343 100644 --- a/test/MC/X86/x86_64-encoding.s +++ b/test/MC/X86/x86_64-encoding.s @@ -155,3 +155,19 @@ pshufb CPI1_0(%rip), %xmm1 // CHECK: leave // CHECK: encoding: [0xc9] leaveq + +// CHECK: flds (%edi) +// CHECK: encoding: [0x67,0xd9,0x07] + flds (%edi) + +// CHECK: filds (%edi) +// CHECK: encoding: [0x67,0xdf,0x07] + filds (%edi) + +// CHECK: flds (%rdi) +// CHECK: encoding: [0xd9,0x07] + flds (%rdi) + +// CHECK: filds (%rdi) +// CHECK: encoding: [0xdf,0x07] + filds (%rdi) diff --git a/test/Makefile b/test/Makefile index b37bbfcc6f2a..0d84186b1e87 100644 --- a/test/Makefile +++ b/test/Makefile @@ -173,22 +173,24 @@ site.exp: FORCE lit.site.cfg: site.exp @echo "Making LLVM 'lit.site.cfg' file..." - @sed -e "s#@LLVM_SOURCE_DIR@#$(LLVM_SRC_ROOT)#g" \ - -e "s#@LLVM_BINARY_DIR@#$(LLVM_OBJ_ROOT)#g" \ - -e "s#@LLVM_TOOLS_DIR@#$(ToolDir)#g" \ - -e "s#@LLVMGCCDIR@#$(LLVMGCCDIR)#g" \ - -e "s#@ENABLE_SHARED@#$(ENABLE_SHARED)#g" \ - $(PROJ_SRC_DIR)/lit.site.cfg.in > $@ + @$(ECHOPATH) s=@LLVM_SOURCE_DIR@=$(LLVM_SRC_ROOT)=g > lit.tmp + @$(ECHOPATH) s=@LLVM_BINARY_DIR@=$(LLVM_OBJ_ROOT)=g >> lit.tmp + @$(ECHOPATH) s=@LLVM_TOOLS_DIR@=$(ToolDir)=g >> lit.tmp + @$(ECHOPATH) s=@LLVMGCCDIR@=$(LLVMGCCDIR)=g >> lit.tmp + @$(ECHOPATH) s=@PYTHON_EXECUTABLE@=python=g >> lit.tmp + @$(ECHOPATH) s=@ENABLE_SHARED@=$(ENABLE_SHARED)=g >> lit.tmp + @sed -f lit.tmp $(PROJ_SRC_DIR)/lit.site.cfg.in > $@ + @-rm -f lit.tmp Unit/lit.site.cfg: $(PROJ_OBJ_DIR)/Unit/.dir FORCE @echo "Making LLVM unittest 'lit.site.cfg' file..." - @sed -e "s#@LLVM_SOURCE_DIR@#$(LLVM_SRC_ROOT)#g" \ - -e "s#@LLVM_BINARY_DIR@#$(LLVM_OBJ_ROOT)#g" \ - -e "s#@LLVM_TOOLS_DIR@#$(ToolDir)#g" \ - -e "s#@LLVMGCCDIR@#$(LLVMGCCDIR)#g" \ - -e "s#@LLVM_BUILD_MODE@#$(BuildMode)#g" \ - -e "s#@ENABLE_SHARED@#$(ENABLE_SHARED)#g" \ - -e "s#@SHLIBDIR@#$(SharedLibDir)#g" \ - -e "s#@SHLIBPATH_VAR@#$(SHLIBPATH_VAR)#g" \ - $(PROJ_SRC_DIR)/Unit/lit.site.cfg.in > $@ - + @$(ECHOPATH) s=@LLVM_SOURCE_DIR@=$(LLVM_SRC_ROOT)=g > unit.tmp + @$(ECHOPATH) s=@LLVM_BINARY_DIR@=$(LLVM_OBJ_ROOT)=g >> unit.tmp + @$(ECHOPATH) s=@LLVM_TOOLS_DIR@=$(ToolDir)=g >> unit.tmp + @$(ECHOPATH) s=@LLVMGCCDIR@=$(LLVMGCCDIR)=g >> unit.tmp + @$(ECHOPATH) s=@LLVM_BUILD_MODE@=$(BuildMode)=g >> unit.tmp + @$(ECHOPATH) s=@ENABLE_SHARED@=$(ENABLE_SHARED)=g >> unit.tmp + @$(ECHOPATH) s=@SHLIBDIR@=$(SharedLibDir)=g >> unit.tmp + @$(ECHOPATH) s=@SHLIBPATH_VAR@=$(SHLIBPATH_VAR)=g >> unit.tmp + @sed -f unit.tmp $(PROJ_SRC_DIR)/Unit/lit.site.cfg.in > $@ + @-rm -f unit.tmp diff --git a/test/TableGen/TargetInstrInfo.td b/test/TableGen/TargetInstrInfo.td index 146ef6fd7682..6c39d5ce57c3 100644 --- a/test/TableGen/TargetInstrInfo.td +++ b/test/TableGen/TargetInstrInfo.td @@ -110,7 +110,7 @@ def SHL32rCL : Inst<(ops R32:$dst, R32:$src), [(set R32:$dst, (shl R32:$src, CL))]>; // The RTL list is a list, allowing complex instructions to be defined easily. -// Temporary 'internal' registers can be used to break instructions appart. +// Temporary 'internal' registers can be used to break instructions apart. let isTwoAddress = 1 in def XOR32mi : Inst<(ops addr:$addr, imm32:$imm), "xor $dst, $src2", 0x81, MRM6m, diff --git a/test/Transforms/CodeGenPrepare/basic.ll b/test/Transforms/CodeGenPrepare/basic.ll index 3b1fca328c5b..ebf10f0e9df2 100644 --- a/test/Transforms/CodeGenPrepare/basic.ll +++ b/test/Transforms/CodeGenPrepare/basic.ll @@ -14,13 +14,14 @@ entry: br i1 %1, label %T, label %trap ; CHECK: entry: -; HECK-NEXT: ret i32 4 +; CHECK-NEXT: br label %T trap: ; preds = %0, %entry tail call void @llvm.trap() noreturn nounwind unreachable T: +; CHECK: ret i32 4 ret i32 4 } diff --git a/test/Transforms/ConstProp/2002-05-03-NotOperator.ll b/test/Transforms/ConstProp/2002-05-03-NotOperator.ll index d9cd67406b06..b957220aa9cc 100644 --- a/test/Transforms/ConstProp/2002-05-03-NotOperator.ll +++ b/test/Transforms/ConstProp/2002-05-03-NotOperator.ll @@ -1,4 +1,4 @@ -; This bug has to do with the fact that constant propogation was implemented in +; This bug has to do with the fact that constant propagation was implemented in ; terms of _logical_ not (! in C) instead of _bitwise_ not (~ in C). This was ; due to a spec change. diff --git a/test/Transforms/ConstProp/basictest.ll b/test/Transforms/ConstProp/basictest.ll index df57fb6870b8..d0d0a5bb3352 100644 --- a/test/Transforms/ConstProp/basictest.ll +++ b/test/Transforms/ConstProp/basictest.ll @@ -1,6 +1,6 @@ ; RUN: opt < %s -constprop -die -S | FileCheck %s -; This is a basic sanity check for constant propogation. The add instruction +; This is a basic sanity check for constant propagation. The add instruction ; should be eliminated. define i32 @test1(i1 %B) { br i1 %B, label %BB1, label %BB2 diff --git a/test/Transforms/ConstProp/logicaltest.ll b/test/Transforms/ConstProp/logicaltest.ll index c74296aa2c0c..abd3275a4f74 100644 --- a/test/Transforms/ConstProp/logicaltest.ll +++ b/test/Transforms/ConstProp/logicaltest.ll @@ -1,4 +1,4 @@ -; Ensure constant propogation of logical instructions is working correctly. +; Ensure constant propagation of logical instructions is working correctly. ; RUN: opt < %s -constprop -die -S | FileCheck %s ; CHECK-NOT: {{and|or|xor}} diff --git a/test/Transforms/ConstProp/overflow-ops.ll b/test/Transforms/ConstProp/overflow-ops.ll index 5587e9b62330..d1cc2eb90a8e 100644 --- a/test/Transforms/ConstProp/overflow-ops.ll +++ b/test/Transforms/ConstProp/overflow-ops.ll @@ -2,6 +2,14 @@ %i8i1 = type {i8, i1} +declare {i8, i1} @llvm.uadd.with.overflow.i8(i8, i8) +declare {i8, i1} @llvm.usub.with.overflow.i8(i8, i8) +declare {i8, i1} @llvm.umul.with.overflow.i8(i8, i8) + +declare {i8, i1} @llvm.sadd.with.overflow.i8(i8, i8) +declare {i8, i1} @llvm.ssub.with.overflow.i8(i8, i8) +declare {i8, i1} @llvm.smul.with.overflow.i8(i8, i8) + ;;----------------------------- ;; uadd ;;----------------------------- @@ -47,6 +55,28 @@ entry: } ;;----------------------------- +;; umul +;;----------------------------- + +define {i8, i1} @umul_1() nounwind { +entry: + %t = call {i8, i1} @llvm.umul.with.overflow.i8(i8 100, i8 3) + ret {i8, i1} %t + +; CHECK: @umul_1 +; CHECK: ret %i8i1 { i8 44, i1 true } +} + +define {i8, i1} @umul_2() nounwind { +entry: + %t = call {i8, i1} @llvm.umul.with.overflow.i8(i8 100, i8 2) + ret {i8, i1} %t + +; CHECK: @umul_2 +; CHECK: ret %i8i1 { i8 -56, i1 false } +} + +;;----------------------------- ;; sadd ;;----------------------------- @@ -163,14 +193,9 @@ entry: ; CHECK: ret %i8i1 { i8 -10, i1 false } } - - -declare {i8, i1} @llvm.uadd.with.overflow.i8(i8, i8) -declare {i8, i1} @llvm.usub.with.overflow.i8(i8, i8) - -declare {i8, i1} @llvm.sadd.with.overflow.i8(i8, i8) -declare {i8, i1} @llvm.ssub.with.overflow.i8(i8, i8) -declare {i8, i1} @llvm.smul.with.overflow.i8(i8, i8) +;;----------------------------- +;; smul +;;----------------------------- ; rdar://8501501 define {i8, i1} @smul_1() nounwind { diff --git a/test/Transforms/ConstProp/phi.ll b/test/Transforms/ConstProp/phi.ll index 3d9e284457cf..c65d34cc933a 100644 --- a/test/Transforms/ConstProp/phi.ll +++ b/test/Transforms/ConstProp/phi.ll @@ -1,4 +1,4 @@ -; This is a basic sanity check for constant propogation. The add instruction +; This is a basic sanity check for constant propagation. The add instruction ; should be eliminated. ; RUN: opt < %s -constprop -die -S | not grep phi diff --git a/test/Transforms/DeadArgElim/deadexternal.ll b/test/Transforms/DeadArgElim/deadexternal.ll index 5a80aba6e2db..84092613130b 100644 --- a/test/Transforms/DeadArgElim/deadexternal.ll +++ b/test/Transforms/DeadArgElim/deadexternal.ll @@ -37,3 +37,16 @@ entry: call void @f(i32 %tmp) ret void } + +; Check that callers are not transformed for weak definitions. +define weak i32 @weak_f(i32 %x) nounwind { +entry: + ret i32 0 +} +define void @weak_f_caller() nounwind { +entry: +; CHECK: call i32 @weak_f(i32 10) + %call = tail call i32 @weak_f(i32 10) + ret void +} + diff --git a/test/Transforms/DeadStoreElimination/2011-03-25-DSEMiscompile.ll b/test/Transforms/DeadStoreElimination/2011-03-25-DSEMiscompile.ll new file mode 100644 index 000000000000..079eec43bf85 --- /dev/null +++ b/test/Transforms/DeadStoreElimination/2011-03-25-DSEMiscompile.ll @@ -0,0 +1,23 @@ +; RUN: opt < %s -basicaa -dse -S | FileCheck %s +; PR9561 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" +target triple = "i386-apple-darwin9.8" + +@A = external global [0 x i32] + +declare cc10 void @Func2(i32*, i32*, i32*, i32) + +define cc10 void @Func1(i32* noalias %Arg1, i32* noalias %Arg2, i32* %Arg3, i32 %Arg4) { +entry: + store i32 add (i32 ptrtoint ([0 x i32]* @A to i32), i32 1), i32* %Arg2 +; CHECK: store i32 add (i32 ptrtoint ([0 x i32]* @A to i32), i32 1), i32* %Arg2 + %ln2gz = getelementptr i32* %Arg1, i32 14 + %ln2gA = bitcast i32* %ln2gz to double* + %ln2gB = load double* %ln2gA + %ln2gD = getelementptr i32* %Arg2, i32 -3 + %ln2gE = bitcast i32* %ln2gD to double* + store double %ln2gB, double* %ln2gE +; CHECK: store double %ln2gB, double* %ln2gE + tail call cc10 void @Func2(i32* %Arg1, i32* %Arg2, i32* %Arg3, i32 %Arg4) nounwind + ret void +} diff --git a/test/Transforms/GVN/invariant-simple.ll b/test/Transforms/GVN/invariant-simple.ll deleted file mode 100644 index 98ea48cdde32..000000000000 --- a/test/Transforms/GVN/invariant-simple.ll +++ /dev/null @@ -1,36 +0,0 @@ -; RUN: opt < %s -basicaa -gvn -S | FileCheck %s - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" -target triple = "i386-apple-darwin7" - -define i8 @test(i8* %P) nounwind { -; CHECK: @test -; CHECK-NOT: load -; CHECK: ret i8 -entry: - store i8 1, i8* %P - %0 = call {}* @llvm.invariant.start(i64 32, i8* %P) - %1 = tail call i32 @foo(i8* %P) - call void @llvm.invariant.end({}* %0, i64 32, i8* %P) - %2 = load i8* %P - ret i8 %2 -} - -define i8 @test2(i8* %P) nounwind { -; CHECK: @test2 -; CHECK: store i8 1 -; CHECK: store i8 2 -; CHECK: ret i8 0 -entry: - store i8 1, i8* %P - %0 = call {}* @llvm.invariant.start(i64 32, i8* %P) - %1 = tail call i32 @bar(i8* %P) - call void @llvm.invariant.end({}* %0, i64 32, i8* %P) - store i8 2, i8* %P - ret i8 0 -} - -declare i32 @foo(i8*) nounwind -declare i32 @bar(i8*) nounwind readonly -declare {}* @llvm.invariant.start(i64 %S, i8* nocapture %P) readonly -declare void @llvm.invariant.end({}* %S, i64 %SS, i8* nocapture %P) diff --git a/test/Transforms/GVN/rle.ll b/test/Transforms/GVN/rle.ll index 2e4332175070..4ff5becb2064 100644 --- a/test/Transforms/GVN/rle.ll +++ b/test/Transforms/GVN/rle.ll @@ -1,7 +1,7 @@ -; RUN: opt < %s -basicaa -gvn -S | FileCheck %s +; RUN: opt < %s -basicaa -gvn -S -die | FileCheck %s ; 32-bit little endian target. -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" ;; Trivial RLE test. define i32 @test0(i32 %V, i32* %P) { @@ -544,3 +544,99 @@ entry: ; CHECK: ret i32 0 } + +;;===----------------------------------------------------------------------===;; +;; Load -> Load forwarding in partial alias case. +;;===----------------------------------------------------------------------===;; + +define i32 @load_load_partial_alias(i8* %P) nounwind ssp { +entry: + %0 = bitcast i8* %P to i32* + %tmp2 = load i32* %0 + %add.ptr = getelementptr inbounds i8* %P, i64 1 + %tmp5 = load i8* %add.ptr + %conv = zext i8 %tmp5 to i32 + %add = add nsw i32 %tmp2, %conv + ret i32 %add + +; CHECK: @load_load_partial_alias +; CHECK: load i32* +; CHECK-NOT: load +; CHECK: lshr i32 {{.*}}, 8 +; CHECK-NOT: load +; CHECK: trunc i32 {{.*}} to i8 +; CHECK-NOT: load +; CHECK: ret i32 +} + + +; Cross block partial alias case. +define i32 @load_load_partial_alias_cross_block(i8* %P) nounwind ssp { +entry: + %xx = bitcast i8* %P to i32* + %x1 = load i32* %xx, align 4 + %cmp = icmp eq i32 %x1, 127 + br i1 %cmp, label %land.lhs.true, label %if.end + +land.lhs.true: ; preds = %entry + %arrayidx4 = getelementptr inbounds i8* %P, i64 1 + %tmp5 = load i8* %arrayidx4, align 1 + %conv6 = zext i8 %tmp5 to i32 + ret i32 %conv6 + +if.end: + ret i32 52 +; CHECK: @load_load_partial_alias_cross_block +; CHECK: land.lhs.true: +; CHECK-NOT: load i8 +; CHECK: ret i32 %conv6 +} + + +;;===----------------------------------------------------------------------===;; +;; Load Widening +;;===----------------------------------------------------------------------===;; + +%widening1 = type { i32, i8, i8, i8, i8 } + +@f = global %widening1 zeroinitializer, align 4 + +define i32 @test_widening1(i8* %P) nounwind ssp noredzone { +entry: + %tmp = load i8* getelementptr inbounds (%widening1* @f, i64 0, i32 1), align 4 + %conv = zext i8 %tmp to i32 + %tmp1 = load i8* getelementptr inbounds (%widening1* @f, i64 0, i32 2), align 1 + %conv2 = zext i8 %tmp1 to i32 + %add = add nsw i32 %conv, %conv2 + ret i32 %add +; CHECK: @test_widening1 +; CHECK-NOT: load +; CHECK: load i16* +; CHECK-NOT: load +; CHECK-ret i32 +} + +define i32 @test_widening2() nounwind ssp noredzone { +entry: + %tmp = load i8* getelementptr inbounds (%widening1* @f, i64 0, i32 1), align 4 + %conv = zext i8 %tmp to i32 + %tmp1 = load i8* getelementptr inbounds (%widening1* @f, i64 0, i32 2), align 1 + %conv2 = zext i8 %tmp1 to i32 + %add = add nsw i32 %conv, %conv2 + + %tmp2 = load i8* getelementptr inbounds (%widening1* @f, i64 0, i32 3), align 2 + %conv3 = zext i8 %tmp2 to i32 + %add2 = add nsw i32 %add, %conv3 + + %tmp3 = load i8* getelementptr inbounds (%widening1* @f, i64 0, i32 4), align 1 + %conv4 = zext i8 %tmp3 to i32 + %add3 = add nsw i32 %add2, %conv3 + + ret i32 %add3 +; CHECK: @test_widening2 +; CHECK-NOT: load +; CHECK: load i32* +; CHECK-NOT: load +; CHECK-ret i32 +} + diff --git a/test/Transforms/GlobalOpt/2011-04-09-EmptyGlobalCtors.ll b/test/Transforms/GlobalOpt/2011-04-09-EmptyGlobalCtors.ll new file mode 100644 index 000000000000..321a487cc82f --- /dev/null +++ b/test/Transforms/GlobalOpt/2011-04-09-EmptyGlobalCtors.ll @@ -0,0 +1,5 @@ +; RUN: opt < %s -globalopt -disable-output + +%0 = type { i32, void ()* } +@llvm.global_ctors = appending global [0 x %0] zeroinitializer + diff --git a/test/Transforms/GlobalOpt/cxx-dtor.ll b/test/Transforms/GlobalOpt/cxx-dtor.ll new file mode 100644 index 000000000000..22635620baad --- /dev/null +++ b/test/Transforms/GlobalOpt/cxx-dtor.ll @@ -0,0 +1,31 @@ +; RUN: opt < %s -globalopt -S | FileCheck %s + +%0 = type { i32, void ()* } +%struct.A = type { i8 } + +@a = global %struct.A zeroinitializer, align 1 +@__dso_handle = external global i8* +@llvm.global_ctors = appending global [1 x %0] [%0 { i32 65535, void ()* @_GLOBAL__I_a }] + +; CHECK-NOT: call i32 @__cxa_atexit + +define internal void @__cxx_global_var_init() nounwind section "__TEXT,__StaticInit,regular,pure_instructions" { + %1 = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.A*)* @_ZN1AD1Ev to void (i8*)*), i8* getelementptr inbounds (%struct.A* @a, i32 0, i32 0), i8* bitcast (i8** @__dso_handle to i8*)) + ret void +} + +define linkonce_odr void @_ZN1AD1Ev(%struct.A* %this) nounwind align 2 { + call void @_ZN1AD2Ev(%struct.A* %this) + ret void +} + +declare i32 @__cxa_atexit(void (i8*)*, i8*, i8*) + +define linkonce_odr void @_ZN1AD2Ev(%struct.A* %this) nounwind align 2 { + ret void +} + +define internal void @_GLOBAL__I_a() nounwind section "__TEXT,__StaticInit,regular,pure_instructions" { + call void @__cxx_global_var_init() + ret void +} diff --git a/test/Transforms/IndVarSimplify/2009-04-14-shorten_iv_vars.ll b/test/Transforms/IndVarSimplify/2009-04-14-shorten_iv_vars.ll index 37ad63a9a772..0f6267bd1799 100644 --- a/test/Transforms/IndVarSimplify/2009-04-14-shorten_iv_vars.ll +++ b/test/Transforms/IndVarSimplify/2009-04-14-shorten_iv_vars.ll @@ -1,6 +1,6 @@ ; RUN: opt < %s -indvars -S | not grep {sext} ; ModuleID = '<stdin>' -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n:32:64" target triple = "x86_64-apple-darwin9.6" @a = external global i32* ; <i32**> [#uses=3] @b = external global i32* ; <i32**> [#uses=3] diff --git a/test/Transforms/IndVarSimplify/2009-04-15-shorten-iv-vars-2.ll b/test/Transforms/IndVarSimplify/2009-04-15-shorten-iv-vars-2.ll index 803b540606e5..46d6b380f000 100644 --- a/test/Transforms/IndVarSimplify/2009-04-15-shorten-iv-vars-2.ll +++ b/test/Transforms/IndVarSimplify/2009-04-15-shorten-iv-vars-2.ll @@ -13,7 +13,7 @@ ; d[(i+2)&15] = e[(i+2)&15]+f[(i+2)&15]+K[i+2]; ; } ;} -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n:32:64" target triple = "x86_64-apple-darwin9.6" @a = external global i32* ; <i32**> [#uses=3] @b = external global i32* ; <i32**> [#uses=3] diff --git a/test/Transforms/IndVarSimplify/2009-04-27-Floating.ll b/test/Transforms/IndVarSimplify/2009-04-27-Floating.ll index 9fd2d2f04f72..47164d86047e 100644 --- a/test/Transforms/IndVarSimplify/2009-04-27-Floating.ll +++ b/test/Transforms/IndVarSimplify/2009-04-27-Floating.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -indvars -S | grep icmp | grep next +; RUN: opt < %s -indvars -S | FileCheck %s ; PR4086 declare void @foo() @@ -6,13 +6,14 @@ define void @test() { entry: br label %loop_body -loop_body: - %i = phi float [ %nexti, %loop_body ], [ 0.0, %entry ] +loop_body: + %i = phi float [ %nexti, %loop_body ], [ 0.0, %entry ] tail call void @foo() %nexti = fadd float %i, 1.0 - %less = fcmp olt float %nexti, 2.0 + ; CHECK: icmp ne i32 %{{[a-zA-Z$._0-9]+}}, 2 + %less = fcmp olt float %nexti, 2.0 br i1 %less, label %loop_body, label %done -done: +done: ret void } diff --git a/test/Transforms/IndVarSimplify/ada-loops.ll b/test/Transforms/IndVarSimplify/ada-loops.ll index 436840ae9075..4a07d997e7d7 100644 --- a/test/Transforms/IndVarSimplify/ada-loops.ll +++ b/test/Transforms/IndVarSimplify/ada-loops.ll @@ -11,7 +11,7 @@ ; count without casting. ; ModuleID = 'ada.bc' -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-n:8:16:32" target triple = "i686-pc-linux-gnu" define void @kinds__sbytezero([256 x i32]* nocapture %a) nounwind { diff --git a/test/Transforms/IndVarSimplify/addrec-gep.ll b/test/Transforms/IndVarSimplify/addrec-gep.ll index 345f666c3b2e..58cba6057045 100644 --- a/test/Transforms/IndVarSimplify/addrec-gep.ll +++ b/test/Transforms/IndVarSimplify/addrec-gep.ll @@ -9,7 +9,7 @@ ; be able to reconstruct the full getelementptr, despite it having a few ; obstacles set in its way. -target datalayout = "e-p:64:64:64" +target datalayout = "e-p:64:64:64-n:32:64" define void @foo(i64 %n, i64 %m, i64 %o, i64 %q, double* nocapture %p) nounwind { entry: diff --git a/test/Transforms/IndVarSimplify/ashr-tripcount.ll b/test/Transforms/IndVarSimplify/ashr-tripcount.ll index baaefdc2bc51..09d559fe5114 100644 --- a/test/Transforms/IndVarSimplify/ashr-tripcount.ll +++ b/test/Transforms/IndVarSimplify/ashr-tripcount.ll @@ -4,7 +4,7 @@ ; Indvars should be able to eliminate all of the sign extensions ; inside the loop. -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n:32:64" @pow_2_tab = external constant [0 x float] ; <[0 x float]*> [#uses=1] @pow_2_025_tab = external constant [0 x float] ; <[0 x float]*> [#uses=1] @i_pow_2_tab = external constant [0 x float] ; <[0 x float]*> [#uses=1] diff --git a/test/Transforms/IndVarSimplify/iv-sext.ll b/test/Transforms/IndVarSimplify/iv-sext.ll index 55165022109a..3e9087399249 100644 --- a/test/Transforms/IndVarSimplify/iv-sext.ll +++ b/test/Transforms/IndVarSimplify/iv-sext.ll @@ -6,7 +6,7 @@ ; inner loop to i64. ; TODO: it should promote hiPart to i64 in the outer loop too. -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n:32:64" define void @t(float* %pTmp1, float* %peakWeight, float* %nrgReducePeakrate, i32 %bandEdgeIndex, float %tmp1) nounwind { entry: diff --git a/test/Transforms/IndVarSimplify/iv-zext.ll b/test/Transforms/IndVarSimplify/iv-zext.ll index 1cc559fd79f1..80a77b6e9365 100644 --- a/test/Transforms/IndVarSimplify/iv-zext.ll +++ b/test/Transforms/IndVarSimplify/iv-zext.ll @@ -2,7 +2,7 @@ ; RUN: not grep and %t ; RUN: not grep zext %t -target datalayout = "-p:64:64:64" +target datalayout = "-p:64:64:64-n:32:64" define void @foo(double* %d, i64 %n) nounwind { entry: diff --git a/test/Transforms/IndVarSimplify/max-pointer.ll b/test/Transforms/IndVarSimplify/max-pointer.ll index f18f968f595d..46ac2d89b504 100644 --- a/test/Transforms/IndVarSimplify/max-pointer.ll +++ b/test/Transforms/IndVarSimplify/max-pointer.ll @@ -2,7 +2,7 @@ ; RUN: grep {icmp ugt i8\\\*} %t | count 1 ; RUN: grep {icmp sgt i8\\\*} %t | count 1 -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n:32:64" %struct.CKenCodeCodec = type <{ i8 }> diff --git a/test/Transforms/IndVarSimplify/pointer.ll b/test/Transforms/IndVarSimplify/pointer.ll index 5eee655d4225..d55bf98d3136 100644 --- a/test/Transforms/IndVarSimplify/pointer.ll +++ b/test/Transforms/IndVarSimplify/pointer.ll @@ -9,7 +9,7 @@ ; Indvars should be able to expand the pointer-arithmetic ; IV into an integer IV indexing into a simple getelementptr. -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64" +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-n:32:64" define void @foo(i8* %A, i64 %n) nounwind { entry: diff --git a/test/Transforms/IndVarSimplify/preserve-gep-loop-variant.ll b/test/Transforms/IndVarSimplify/preserve-gep-loop-variant.ll index 3a5c0b650ffe..26f05c4b1ee9 100644 --- a/test/Transforms/IndVarSimplify/preserve-gep-loop-variant.ll +++ b/test/Transforms/IndVarSimplify/preserve-gep-loop-variant.ll @@ -2,7 +2,7 @@ ; RUN: not grep inttoptr %t ; RUN: not grep ptrtoint %t ; RUN: grep scevgep %t -target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" +target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128-n:32:64" ; Indvars shouldn't need inttoptr/ptrtoint to expand an address here. diff --git a/test/Transforms/IndVarSimplify/preserve-gep-nested.ll b/test/Transforms/IndVarSimplify/preserve-gep-nested.ll index bb0993c88eab..b41de5828a9d 100644 --- a/test/Transforms/IndVarSimplify/preserve-gep-nested.ll +++ b/test/Transforms/IndVarSimplify/preserve-gep-nested.ll @@ -13,7 +13,7 @@ ; FIXME: This test should pass with or without TargetData. Until opt ; supports running tests without targetdata, just hardware this in. -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n:32:64" %struct.Q = type { [10 x %struct.N] } %struct.N = type { %struct.S } diff --git a/test/Transforms/IndVarSimplify/preserve-gep-remainder.ll b/test/Transforms/IndVarSimplify/preserve-gep-remainder.ll index e17368b04ccf..ca0c39992760 100644 --- a/test/Transforms/IndVarSimplify/preserve-gep-remainder.ll +++ b/test/Transforms/IndVarSimplify/preserve-gep-remainder.ll @@ -1,6 +1,6 @@ ; RUN: opt < %s -indvars -S \ ; RUN: | grep {\[%\]p.2.ip.1 = getelementptr \\\[3 x \\\[3 x double\\\]\\\]\\* \[%\]p, i64 2, i64 \[%\]tmp, i64 1} -target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" +target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128-n:32:64" ; Indvars shouldn't expand this to ; %p.2.ip.1 = getelementptr [3 x [3 x double]]* %p, i64 0, i64 %tmp, i64 19 diff --git a/test/Transforms/IndVarSimplify/preserve-gep.ll b/test/Transforms/IndVarSimplify/preserve-gep.ll index a27d20dc9653..82eda0386e7f 100644 --- a/test/Transforms/IndVarSimplify/preserve-gep.ll +++ b/test/Transforms/IndVarSimplify/preserve-gep.ll @@ -6,7 +6,7 @@ ; Indvars shouldn't leave getelementptrs expanded out as ; inttoptr+ptrtoint in its output in common cases. -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n:32:64" target triple = "x86_64-unknown-linux-gnu" %struct.Foo = type { i32, i32, [10 x i32], i32 } diff --git a/test/Transforms/InstCombine/2011-03-08-SRemMinusOneBadOpt.ll b/test/Transforms/InstCombine/2011-03-08-SRemMinusOneBadOpt.ll new file mode 100644 index 000000000000..6a3e3e40e6d4 --- /dev/null +++ b/test/Transforms/InstCombine/2011-03-08-SRemMinusOneBadOpt.ll @@ -0,0 +1,12 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s +; PR9346 + +define i32 @test(i64 %x) nounwind { +; CHECK: ret i32 0 +entry: + %or = or i64 %x, 4294967294 + %conv = trunc i64 %or to i32 + %rem.i = srem i32 %conv, -1 + ret i32 %rem.i +} + diff --git a/test/Transforms/InstCombine/ExtractCast.ll b/test/Transforms/InstCombine/ExtractCast.ll new file mode 100644 index 000000000000..5ebbefd97b3e --- /dev/null +++ b/test/Transforms/InstCombine/ExtractCast.ll @@ -0,0 +1,27 @@ +; RUN: opt < %s -instcombine -S -o - | FileCheck %s + +; CHECK: @a +define i32 @a(<4 x i64> %I) { +entry: +; CHECK-NOT: trunc <4 x i64> + %J = trunc <4 x i64> %I to <4 x i32> + %K = extractelement <4 x i32> %J, i32 3 +; CHECK: extractelement <4 x i64> +; CHECK: trunc i64 +; CHECK: ret + ret i32 %K +} + + +; CHECK: @b +define i32 @b(<4 x float> %I) { +entry: +; CHECK-NOT: fptosi <4 x float> + %J = fptosi <4 x float> %I to <4 x i32> + %K = extractelement <4 x i32> %J, i32 3 +; CHECK: extractelement <4 x float> +; CHECK: fptosi float +; CHECK: ret + ret i32 %K +} + diff --git a/test/Transforms/InstCombine/and-or-not.ll b/test/Transforms/InstCombine/and-or-not.ll index 37ec3bc1aabb..bd878b04a350 100644 --- a/test/Transforms/InstCombine/and-or-not.ll +++ b/test/Transforms/InstCombine/and-or-not.ll @@ -4,7 +4,7 @@ ; PR1510 -; These are all equivelent to A^B +; These are all equivalent to A^B define i32 @test1(i32 %a, i32 %b) { entry: diff --git a/test/Transforms/InstCombine/and2.ll b/test/Transforms/InstCombine/and2.ll index d898ea3b037a..a8881522eac4 100644 --- a/test/Transforms/InstCombine/and2.ll +++ b/test/Transforms/InstCombine/and2.ll @@ -26,3 +26,12 @@ define i32 @test3(i32 %X, i32 %Y) { ; CHECK-NEXT: and i32 %X, %Y ; CHECK-NEXT: ret } + +define i1 @test4(i32 %X) { + %a = icmp ult i32 %X, 31 + %b = icmp slt i32 %X, 0 + %c = and i1 %a, %b + ret i1 %c +; CHECK: @test4 +; CHECK-NEXT: ret i1 false +} diff --git a/test/Transforms/InstCombine/debuginfo.ll b/test/Transforms/InstCombine/debuginfo.ll new file mode 100644 index 000000000000..f6892fc3e1f9 --- /dev/null +++ b/test/Transforms/InstCombine/debuginfo.ll @@ -0,0 +1,57 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +declare i64 @llvm.objectsize.i64(i8*, i1) nounwind readnone + +declare i8* @foo(i8*, i32, i64, i64) nounwind + +define hidden i8* @foobar(i8* %__dest, i32 %__val, i64 %__len) nounwind inlinehint ssp { +entry: + %__dest.addr = alloca i8*, align 8 + %__val.addr = alloca i32, align 4 + %__len.addr = alloca i64, align 8 + store i8* %__dest, i8** %__dest.addr, align 8, !tbaa !1 +; CHECK-NOT: call void @llvm.dbg.declare +; CHECK: call void @llvm.dbg.value + call void @llvm.dbg.declare(metadata !{i8** %__dest.addr}, metadata !0), !dbg !16 + store i32 %__val, i32* %__val.addr, align 4, !tbaa !17 + call void @llvm.dbg.declare(metadata !{i32* %__val.addr}, metadata !7), !dbg !18 + store i64 %__len, i64* %__len.addr, align 8, !tbaa !19 + call void @llvm.dbg.declare(metadata !{i64* %__len.addr}, metadata !9), !dbg !20 + %tmp = load i8** %__dest.addr, align 8, !dbg !21, !tbaa !13 + %tmp1 = load i32* %__val.addr, align 4, !dbg !21, !tbaa !17 + %tmp2 = load i64* %__len.addr, align 8, !dbg !21, !tbaa !19 + %tmp3 = load i8** %__dest.addr, align 8, !dbg !21, !tbaa !13 + %0 = call i64 @llvm.objectsize.i64(i8* %tmp3, i1 false), !dbg !21 + %call = call i8* @foo(i8* %tmp, i32 %tmp1, i64 %tmp2, i64 %0), !dbg !21 + ret i8* %call, !dbg !21 +} + +!llvm.dbg.lv.foobar = !{!0, !7, !9} +!llvm.dbg.sp = !{!1} + +!0 = metadata !{i32 590081, metadata !1, metadata !"__dest", metadata !2, i32 16777294, metadata !6, i32 0} ; [ DW_TAG_arg_variable ] +!1 = metadata !{i32 589870, i32 0, metadata !2, metadata !"foobar", metadata !"foobar", metadata !"", metadata !2, i32 79, metadata !4, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i8* (i8*, i32, i64)* @foobar} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 589865, metadata !"string.h", metadata !"Game", metadata !3} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 589841, i32 0, i32 12, metadata !"bits.c", metadata !"Game", metadata !"clang version 3.0 (trunk 127710)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 589845, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !5, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!5 = metadata !{metadata !6} +!6 = metadata !{i32 589839, metadata !3, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] +!7 = metadata !{i32 590081, metadata !1, metadata !"__val", metadata !2, i32 33554510, metadata !8, i32 0} ; [ DW_TAG_arg_variable ] +!8 = metadata !{i32 589860, metadata !3, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!9 = metadata !{i32 590081, metadata !1, metadata !"__len", metadata !2, i32 50331726, metadata !10, i32 0} ; [ DW_TAG_arg_variable ] +!10 = metadata !{i32 589846, metadata !3, metadata !"size_t", metadata !2, i32 80, i64 0, i64 0, i64 0, i32 0, metadata !11} ; [ DW_TAG_typedef ] +!11 = metadata !{i32 589846, metadata !3, metadata !"__darwin_size_t", metadata !2, i32 90, i64 0, i64 0, i64 0, i32 0, metadata !12} ; [ DW_TAG_typedef ] +!12 = metadata !{i32 589860, metadata !3, metadata !"long unsigned int", null, i32 0, i64 64, i64 64, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!13 = metadata !{metadata !"any pointer", metadata !14} +!14 = metadata !{metadata !"omnipotent char", metadata !15} +!15 = metadata !{metadata !"Simple C/C++ TBAA", null} +!16 = metadata !{i32 78, i32 28, metadata !1, null} +!17 = metadata !{metadata !"int", metadata !14} +!18 = metadata !{i32 78, i32 40, metadata !1, null} +!19 = metadata !{metadata !"long", metadata !14} +!20 = metadata !{i32 78, i32 54, metadata !1, null} +!21 = metadata !{i32 80, i32 3, metadata !22, null} +!22 = metadata !{i32 589835, metadata !23, i32 80, i32 3, metadata !2, i32 7} ; [ DW_TAG_lexical_block ] +!23 = metadata !{i32 589835, metadata !1, i32 79, i32 1, metadata !2, i32 6} ; [ DW_TAG_lexical_block ] diff --git a/test/Transforms/InstCombine/div.ll b/test/Transforms/InstCombine/div.ll index 0d1398082601..2e24f19dce4c 100644 --- a/test/Transforms/InstCombine/div.ll +++ b/test/Transforms/InstCombine/div.ll @@ -1,34 +1,44 @@ ; This test makes sure that div instructions are properly eliminated. -; RUN: opt < %s -instcombine -S | not grep div +; RUN: opt < %s -instcombine -S | FileCheck %s define i32 @test1(i32 %A) { %B = sdiv i32 %A, 1 ; <i32> [#uses=1] ret i32 %B +; CHECK: @test1 +; CHECK-NEXT: ret i32 %A } define i32 @test2(i32 %A) { ; => Shift %B = udiv i32 %A, 8 ; <i32> [#uses=1] ret i32 %B +; CHECK: @test2 +; CHECK-NEXT: lshr i32 %A, 3 } define i32 @test3(i32 %A) { ; => 0, don't need to keep traps %B = sdiv i32 0, %A ; <i32> [#uses=1] ret i32 %B +; CHECK: @test3 +; CHECK-NEXT: ret i32 0 } define i32 @test4(i32 %A) { ; 0-A %B = sdiv i32 %A, -1 ; <i32> [#uses=1] ret i32 %B +; CHECK: @test4 +; CHECK-NEXT: sub i32 0, %A } define i32 @test5(i32 %A) { %B = udiv i32 %A, -16 ; <i32> [#uses=1] %C = udiv i32 %B, -4 ; <i32> [#uses=1] ret i32 %C +; CHECK: @test5 +; CHECK-NEXT: ret i32 0 } define i1 @test6(i32 %A) { @@ -36,6 +46,8 @@ define i1 @test6(i32 %A) { ; A < 123 %C = icmp eq i32 %B, 0 ; <i1> [#uses=1] ret i1 %C +; CHECK: @test6 +; CHECK-NEXT: icmp ult i32 %A, 123 } define i1 @test7(i32 %A) { @@ -43,6 +55,9 @@ define i1 @test7(i32 %A) { ; A >= 20 && A < 30 %C = icmp eq i32 %B, 2 ; <i1> [#uses=1] ret i1 %C +; CHECK: @test7 +; CHECK-NEXT: add i32 %A, -20 +; CHECK-NEXT: icmp ult i32 } define i1 @test8(i8 %A) { @@ -50,6 +65,8 @@ define i1 @test8(i8 %A) { ; A >= 246 %C = icmp eq i8 %B, 2 ; <i1> [#uses=1] ret i1 %C +; CHECK: @test8 +; CHECK-NEXT: icmp ugt i8 %A, -11 } define i1 @test9(i8 %A) { @@ -57,28 +74,47 @@ define i1 @test9(i8 %A) { ; A < 246 %C = icmp ne i8 %B, 2 ; <i1> [#uses=1] ret i1 %C +; CHECK: @test9 +; CHECK-NEXT: icmp ult i8 %A, -10 } define i32 @test10(i32 %X, i1 %C) { %V = select i1 %C, i32 64, i32 8 ; <i32> [#uses=1] %R = udiv i32 %X, %V ; <i32> [#uses=1] ret i32 %R +; CHECK: @test10 +; CHECK-NEXT: select i1 %C, i32 6, i32 3 +; CHECK-NEXT: lshr i32 %X } define i32 @test11(i32 %X, i1 %C) { %A = select i1 %C, i32 1024, i32 32 ; <i32> [#uses=1] %B = udiv i32 %X, %A ; <i32> [#uses=1] ret i32 %B +; CHECK: @test11 +; CHECK-NEXT: select i1 %C, i32 10, i32 5 +; CHECK-NEXT: lshr i32 %X } ; PR2328 define i32 @test12(i32 %x) nounwind { %tmp3 = udiv i32 %x, %x ; 1 ret i32 %tmp3 +; CHECK: @test12 +; CHECK-NEXT: ret i32 1 } define i32 @test13(i32 %x) nounwind { %tmp3 = sdiv i32 %x, %x ; 1 ret i32 %tmp3 +; CHECK: @test13 +; CHECK-NEXT: ret i32 1 } +define i32 @test14(i8 %x) nounwind { + %zext = zext i8 %x to i32 + %div = udiv i32 %zext, 257 ; 0 + ret i32 %div +; CHECK: @test14 +; CHECK-NEXT: ret i32 0 +} diff --git a/test/Transforms/InstCombine/fcmp.ll b/test/Transforms/InstCombine/fcmp.ll new file mode 100644 index 000000000000..2eb4f058692d --- /dev/null +++ b/test/Transforms/InstCombine/fcmp.ll @@ -0,0 +1,60 @@ +; RUN: opt -S -instcombine < %s | FileCheck %s + +define i1 @test1(float %x, float %y) nounwind { + %ext1 = fpext float %x to double + %ext2 = fpext float %y to double + %cmp = fcmp ogt double %ext1, %ext2 + ret i1 %cmp +; CHECK: @test1 +; CHECK-NEXT: fcmp ogt float %x, %y +} + +define i1 @test2(float %a) nounwind { + %ext = fpext float %a to double + %cmp = fcmp ogt double %ext, 1.000000e+00 + ret i1 %cmp +; CHECK: @test2 +; CHECK-NEXT: fcmp ogt float %a, 1.0 +} + +define i1 @test3(float %a) nounwind { + %ext = fpext float %a to double + %cmp = fcmp ogt double %ext, 0x3FF0000000000001 ; more precision than float. + ret i1 %cmp +; CHECK: @test3 +; CHECK-NEXT: fpext float %a to double +} + +define i1 @test4(float %a) nounwind { + %ext = fpext float %a to double + %cmp = fcmp ogt double %ext, 0x36A0000000000000 ; denormal in float. + ret i1 %cmp +; CHECK: @test4 +; CHECK-NEXT: fpext float %a to double +} + +define i1 @test5(float %a) nounwind { + %neg = fsub float -0.000000e+00, %a + %cmp = fcmp ogt float %neg, 1.000000e+00 + ret i1 %cmp +; CHECK: @test5 +; CHECK-NEXT: fcmp olt float %a, -1.0 +} + +define i1 @test6(float %x, float %y) nounwind { + %neg1 = fsub float -0.000000e+00, %x + %neg2 = fsub float -0.000000e+00, %y + %cmp = fcmp olt float %neg1, %neg2 + ret i1 %cmp +; CHECK: @test6 +; CHECK-NEXT: fcmp ogt float %x, %y +} + +define i1 @test7(float %x) nounwind readnone ssp noredzone { + %ext = fpext float %x to ppc_fp128 + %cmp = fcmp ogt ppc_fp128 %ext, 0xM00000000000000000000000000000000 + ret i1 %cmp +; Can't convert ppc_fp128 +; CHECK: @test7 +; CHECK-NEXT: fpext float %x to ppc_fp128 +} diff --git a/test/Transforms/InstCombine/fdiv.ll b/test/Transforms/InstCombine/fdiv.ll new file mode 100644 index 000000000000..a2cce016e188 --- /dev/null +++ b/test/Transforms/InstCombine/fdiv.ll @@ -0,0 +1,25 @@ +; RUN: opt -S -instcombine < %s | FileCheck %s + +define float @test1(float %x) nounwind readnone ssp { + %div = fdiv float %x, 0x3810000000000000 + ret float %div + +; CHECK: @test1 +; CHECK-NEXT: fmul float %x, 0x47D0000000000000 +} + +define float @test2(float %x) nounwind readnone ssp { + %div = fdiv float %x, 0x47E0000000000000 + ret float %div + +; CHECK: @test2 +; CHECK-NEXT: fdiv float %x, 0x47E0000000000000 +} + +define float @test3(float %x) nounwind readnone ssp { + %div = fdiv float %x, 0x36A0000000000000 + ret float %div + +; CHECK: @test3 +; CHECK-NEXT: fdiv float %x, 0x36A0000000000000 +} diff --git a/test/Transforms/InstCombine/fold-bin-operand.ll b/test/Transforms/InstCombine/fold-bin-operand.ll index d0d072ac6bb5..a8bad0df5960 100644 --- a/test/Transforms/InstCombine/fold-bin-operand.ll +++ b/test/Transforms/InstCombine/fold-bin-operand.ll @@ -1,14 +1,17 @@ -; RUN: opt < %s -instcombine -S | not grep icmp +; RUN: opt < %s -instcombine -S | FileCheck %s target datalayout = "E-p:64:64:64-a0:0:8-f32:32:32-f64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-v64:64:64-v128:128:128" define i1 @f(i1 %x) { +; CHECK: @f +; CHECK: ret i1 false %b = and i1 %x, icmp eq (i8* inttoptr (i32 1 to i8*), i8* inttoptr (i32 2 to i8*)) ret i1 %b } -; FIXME: This doesn't fold at the moment! -; define i32 @f(i32 %x) { -; %b = add i32 %x, zext (i1 icmp eq (i8* inttoptr (i32 1000000 to i8*), i8* inttoptr (i32 2000000 to i8*)) to i32) -; ret i32 %b -;} +define i32 @g(i32 %x) { +; CHECK: @g +; CHECK: ret i32 %x + %b = add i32 %x, zext (i1 icmp eq (i8* inttoptr (i32 1000000 to i8*), i8* inttoptr (i32 2000000 to i8*)) to i32) + ret i32 %b +} diff --git a/test/Transforms/InstCombine/gep-addrspace.ll b/test/Transforms/InstCombine/gep-addrspace.ll new file mode 100644 index 000000000000..dfe12dbfaf7f --- /dev/null +++ b/test/Transforms/InstCombine/gep-addrspace.ll @@ -0,0 +1,19 @@ +; RUN: opt < %s -instcombine -S + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-pc-win32" + +%myStruct = type { float, [3 x float], [4 x float], i32 } + +; make sure that we are not crashing when creating an illegal type +define void @func(%myStruct addrspace(1)* nocapture %p) nounwind { +ST: + %A = getelementptr inbounds %myStruct addrspace(1)* %p, i64 0 + %B = bitcast %myStruct addrspace(1)* %A to %myStruct* + %C = getelementptr inbounds %myStruct* %B, i32 0, i32 1 + %D = getelementptr inbounds [3 x float]* %C, i32 0, i32 2 + %E = load float* %D, align 4 + %F = fsub float %E, undef + ret void +} + diff --git a/test/Transforms/InstCombine/icmp.ll b/test/Transforms/InstCombine/icmp.ll index 3150883e7d71..099540ac7453 100644 --- a/test/Transforms/InstCombine/icmp.ll +++ b/test/Transforms/InstCombine/icmp.ll @@ -377,3 +377,136 @@ define i1 @test38(i32 %x, i32 %y, i32 %z) { %c = icmp ugt i32 %lhs, %rhs ret i1 %c } + +; PR9343 #1 +; CHECK: @test39 +; CHECK: %B = icmp eq i32 %X, 0 +define i1 @test39(i32 %X, i32 %Y) { + %A = ashr exact i32 %X, %Y + %B = icmp eq i32 %A, 0 + ret i1 %B +} + +; CHECK: @test40 +; CHECK: %B = icmp ne i32 %X, 0 +define i1 @test40(i32 %X, i32 %Y) { + %A = lshr exact i32 %X, %Y + %B = icmp ne i32 %A, 0 + ret i1 %B +} + +; PR9343 #3 +; CHECK: @test41 +; CHECK: ret i1 true +define i1 @test41(i32 %X, i32 %Y) { + %A = urem i32 %X, %Y + %B = icmp ugt i32 %Y, %A + ret i1 %B +} + +; CHECK: @test42 +; CHECK: %B = icmp sgt i32 %Y, -1 +define i1 @test42(i32 %X, i32 %Y) { + %A = srem i32 %X, %Y + %B = icmp slt i32 %A, %Y + ret i1 %B +} + +; CHECK: @test43 +; CHECK: %B = icmp slt i32 %Y, 0 +define i1 @test43(i32 %X, i32 %Y) { + %A = srem i32 %X, %Y + %B = icmp slt i32 %Y, %A + ret i1 %B +} + +; CHECK: @test44 +; CHECK: %B = icmp sgt i32 %Y, -1 +define i1 @test44(i32 %X, i32 %Y) { + %A = srem i32 %X, %Y + %B = icmp slt i32 %A, %Y + ret i1 %B +} + +; CHECK: @test45 +; CHECK: %B = icmp slt i32 %Y, 0 +define i1 @test45(i32 %X, i32 %Y) { + %A = srem i32 %X, %Y + %B = icmp slt i32 %Y, %A + ret i1 %B +} + +; PR9343 #4 +; CHECK: @test46 +; CHECK: %C = icmp ult i32 %X, %Y +define i1 @test46(i32 %X, i32 %Y, i32 %Z) { + %A = ashr exact i32 %X, %Z + %B = ashr exact i32 %Y, %Z + %C = icmp ult i32 %A, %B + ret i1 %C +} + +; PR9343 #5 +; CHECK: @test47 +; CHECK: %C = icmp ugt i32 %X, %Y +define i1 @test47(i32 %X, i32 %Y, i32 %Z) { + %A = ashr exact i32 %X, %Z + %B = ashr exact i32 %Y, %Z + %C = icmp ugt i32 %A, %B + ret i1 %C +} + +; PR9343 #8 +; CHECK: @test48 +; CHECK: %C = icmp eq i32 %X, %Y +define i1 @test48(i32 %X, i32 %Y, i32 %Z) { + %A = sdiv exact i32 %X, %Z + %B = sdiv exact i32 %Y, %Z + %C = icmp eq i32 %A, %B + ret i1 %C +} + +; PR8469 +; CHECK: @test49 +; CHECK: ret <2 x i1> <i1 true, i1 true> +define <2 x i1> @test49(<2 x i32> %tmp3) { +entry: + %tmp11 = and <2 x i32> %tmp3, <i32 3, i32 3> + %cmp = icmp ult <2 x i32> %tmp11, <i32 4, i32 4> + ret <2 x i1> %cmp +} + +; PR9343 #7 +; CHECK: @test50 +; CHECK: ret i1 true +define i1 @test50(i16 %X, i32 %Y) { + %A = zext i16 %X to i32 + %B = srem i32 %A, %Y + %C = icmp sgt i32 %B, -1 + ret i1 %C +} + +; CHECK: @test51 +; CHECK: ret i1 %C +define i1 @test51(i32 %X, i32 %Y) { + %A = and i32 %X, 2147483648 + %B = srem i32 %A, %Y + %C = icmp sgt i32 %B, -1 + ret i1 %C +} + +; CHECK: @test52 +; CHECK-NEXT: and i32 %x1, 16711935 +; CHECK-NEXT: icmp eq i32 {{.*}}, 4980863 +; CHECK-NEXT: ret i1 +define i1 @test52(i32 %x1) nounwind { + %conv = and i32 %x1, 255 + %cmp = icmp eq i32 %conv, 127 + %tmp2 = lshr i32 %x1, 16 + %tmp3 = trunc i32 %tmp2 to i8 + %cmp15 = icmp eq i8 %tmp3, 76 + + %A = and i1 %cmp, %cmp15 + ret i1 %A +} + diff --git a/test/Transforms/InstCombine/intrinsics.ll b/test/Transforms/InstCombine/intrinsics.ll index 50e7f1f7c92d..332cd46098ce 100644 --- a/test/Transforms/InstCombine/intrinsics.ll +++ b/test/Transforms/InstCombine/intrinsics.ll @@ -112,6 +112,33 @@ define i8 @umultest2(i8 %A, i1* %overflowPtr) { ; CHECK-NEXT: ret i8 %A } +%ov.result.32 = type { i32, i1 } +declare %ov.result.32 @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone + +define i32 @umultest3(i32 %n) nounwind { + %shr = lshr i32 %n, 2 + %mul = call %ov.result.32 @llvm.umul.with.overflow.i32(i32 %shr, i32 3) + %ov = extractvalue %ov.result.32 %mul, 1 + %res = extractvalue %ov.result.32 %mul, 0 + %ret = select i1 %ov, i32 -1, i32 %res + ret i32 %ret +; CHECK: @umultest3 +; CHECK-NEXT: shr +; CHECK-NEXT: mul nuw +; CHECK-NEXT: ret +} + +define i32 @umultest4(i32 %n) nounwind { + %shr = lshr i32 %n, 1 + %mul = call %ov.result.32 @llvm.umul.with.overflow.i32(i32 %shr, i32 4) + %ov = extractvalue %ov.result.32 %mul, 1 + %res = extractvalue %ov.result.32 %mul, 0 + %ret = select i1 %ov, i32 -1, i32 %res + ret i32 %ret +; CHECK: @umultest4 +; CHECK: umul.with.overflow +} + define void @powi(double %V, double *%P) { entry: %A = tail call double @llvm.powi.f64(double %V, i32 -1) nounwind diff --git a/test/Transforms/InstCombine/merge-icmp.ll b/test/Transforms/InstCombine/merge-icmp.ll new file mode 100644 index 000000000000..00020b157e0f --- /dev/null +++ b/test/Transforms/InstCombine/merge-icmp.ll @@ -0,0 +1,29 @@ +; RUN: opt -S -instcombine < %s | FileCheck %s + +define i1 @test1(i16* %x) { + %load = load i16* %x, align 4 + %trunc = trunc i16 %load to i8 + %cmp1 = icmp eq i8 %trunc, 127 + %and = and i16 %load, -256 + %cmp2 = icmp eq i16 %and, 17664 + %or = and i1 %cmp1, %cmp2 + ret i1 %or +; CHECK: @test1 +; CHECK-NEXT: load i16 +; CHECK-NEXT: icmp eq i16 %load, 17791 +; CHECK-NEXT: ret i1 +} + +define i1 @test2(i16* %x) { + %load = load i16* %x, align 4 + %and = and i16 %load, -256 + %cmp1 = icmp eq i16 %and, 32512 + %trunc = trunc i16 %load to i8 + %cmp2 = icmp eq i8 %trunc, 69 + %or = and i1 %cmp1, %cmp2 + ret i1 %or +; CHECK: @test2 +; CHECK-NEXT: load i16 +; CHECK-NEXT: icmp eq i16 %load, 32581 +; CHECK-NEXT: ret i1 +} diff --git a/test/Transforms/InstCombine/or.ll b/test/Transforms/InstCombine/or.ll index f82f9faab2d5..94a57321862f 100644 --- a/test/Transforms/InstCombine/or.ll +++ b/test/Transforms/InstCombine/or.ll @@ -390,3 +390,22 @@ define i1 @test36(i32 %x) { ; CHECK-NEXT: ret i1 } +define i32 @test37(i32* %xp, i32 %y) { +; CHECK: @test37 +; CHECK: select i1 %tobool, i32 -1, i32 %x + %tobool = icmp ne i32 %y, 0 + %sext = sext i1 %tobool to i32 + %x = load i32* %xp + %or = or i32 %sext, %x + ret i32 %or +} + +define i32 @test38(i32* %xp, i32 %y) { +; CHECK: @test38 +; CHECK: select i1 %tobool, i32 -1, i32 %x + %tobool = icmp ne i32 %y, 0 + %sext = sext i1 %tobool to i32 + %x = load i32* %xp + %or = or i32 %x, %sext + ret i32 %or +} diff --git a/test/Transforms/InstCombine/phi.ll b/test/Transforms/InstCombine/phi.ll index 62c6a63a7e58..cd865ae81baf 100644 --- a/test/Transforms/InstCombine/phi.ll +++ b/test/Transforms/InstCombine/phi.ll @@ -197,25 +197,25 @@ declare i1 @test11a() define i1 @test11() { entry: %a = alloca i32 - %i = ptrtoint i32* %a to i32 + %i = ptrtoint i32* %a to i64 %b = call i1 @test11a() br i1 %b, label %one, label %two one: - %x = phi i32 [%i, %entry], [%y, %two] + %x = phi i64 [%i, %entry], [%y, %two] %c = call i1 @test11a() br i1 %c, label %two, label %end two: - %y = phi i32 [%i, %entry], [%x, %one] + %y = phi i64 [%i, %entry], [%x, %one] %d = call i1 @test11a() br i1 %d, label %one, label %end end: - %f = phi i32 [ %x, %one], [%y, %two] + %f = phi i64 [ %x, %one], [%y, %two] ; Change the %f to %i, and the optimizer suddenly becomes a lot smarter ; even though %f must equal %i at this point - %g = inttoptr i32 %f to i32* + %g = inttoptr i64 %f to i32* store i32 10, i32* %g %z = call i1 @test11a() ret i1 %z @@ -544,3 +544,79 @@ BB2: ; CHECK-NEXT: %C = add nuw i32 %A, 1 ; CHECK-NEXT: ret i32 %C } + +; Same as test11, but used to be missed due to a bug. +declare i1 @test25a() + +define i1 @test25() { +entry: + %a = alloca i32 + %i = ptrtoint i32* %a to i64 + %b = call i1 @test25a() + br i1 %b, label %one, label %two + +one: + %x = phi i64 [%y, %two], [%i, %entry] + %c = call i1 @test25a() + br i1 %c, label %two, label %end + +two: + %y = phi i64 [%x, %one], [%i, %entry] + %d = call i1 @test25a() + br i1 %d, label %one, label %end + +end: + %f = phi i64 [ %x, %one], [%y, %two] + ; Change the %f to %i, and the optimizer suddenly becomes a lot smarter + ; even though %f must equal %i at this point + %g = inttoptr i64 %f to i32* + store i32 10, i32* %g + %z = call i1 @test25a() + ret i1 %z +; CHECK: @test25 +; CHECK-NOT: phi i32 +; CHECK: ret i1 %z +} + +declare i1 @test26a() + +define i1 @test26(i32 %n) { +entry: + %a = alloca i32 + %i = ptrtoint i32* %a to i64 + %b = call i1 @test26a() + br label %one + +one: + %x = phi i64 [%y, %two], [%w, %three], [%i, %entry] + %c = call i1 @test26a() + switch i32 %n, label %end [ + i32 2, label %two + i32 3, label %three + ] + +two: + %y = phi i64 [%x, %one], [%w, %three] + %d = call i1 @test26a() + switch i32 %n, label %end [ + i32 10, label %one + i32 30, label %three + ] + +three: + %w = phi i64 [%y, %two], [%x, %one] + %e = call i1 @test26a() + br i1 %e, label %one, label %two + +end: + %f = phi i64 [ %x, %one], [%y, %two] + ; Change the %f to %i, and the optimizer suddenly becomes a lot smarter + ; even though %f must equal %i at this point + %g = inttoptr i64 %f to i32* + store i32 10, i32* %g + %z = call i1 @test26a() + ret i1 %z +; CHECK: @test26 +; CHECK-NOT: phi i32 +; CHECK: ret i1 %z +} diff --git a/test/Transforms/InstCombine/select.ll b/test/Transforms/InstCombine/select.ll index ba9d99c97dd5..39259078b877 100644 --- a/test/Transforms/InstCombine/select.ll +++ b/test/Transforms/InstCombine/select.ll @@ -714,3 +714,38 @@ define i32 @test52(i32 %n, i32 %m) nounwind { ret i32 %storemerge } +; PR9454 +define i32 @test53(i32 %x) nounwind { + %and = and i32 %x, 2 + %cmp = icmp eq i32 %and, %x + %sel = select i1 %cmp, i32 2, i32 1 + ret i32 %sel +; CHECK: @test53 +; CHECK: select i1 %cmp +; CHECK: ret +} + +define i32 @test54(i32 %X, i32 %Y) { + %A = ashr exact i32 %X, %Y + %B = icmp eq i32 %A, 0 + %C = select i1 %B, i32 %A, i32 1 + ret i32 %C +; CHECK: @test54 +; CHECK-NOT: ashr +; CHECK-NOT: select +; CHECK: icmp ne i32 %X, 0 +; CHECK: zext +; CHECK: ret +} + +define i1 @test55(i1 %X, i32 %Y, i32 %Z) { + %A = ashr exact i32 %Y, %Z + %B = select i1 %X, i32 %Y, i32 %A + %C = icmp eq i32 %B, 0 + ret i1 %C +; CHECK: @test55 +; CHECK-NOT: ashr +; CHECK-NOT: select +; CHECK: icmp eq +; CHECK: ret i1 +} diff --git a/test/Transforms/InstCombine/sext.ll b/test/Transforms/InstCombine/sext.ll index 60669b7a109f..f49a2efb39d8 100644 --- a/test/Transforms/InstCombine/sext.ll +++ b/test/Transforms/InstCombine/sext.ll @@ -126,3 +126,61 @@ define void @test11(<2 x i16> %srcA, <2 x i16> %srcB, <2 x i16>* %dst) { ; CHECK-NEXT: store <2 x i16> ; CHECK-NEXT: ret } + +define i64 @test12(i32 %x) nounwind { + %shr = lshr i32 %x, 1 + %sub = sub nsw i32 0, %shr + %conv = sext i32 %sub to i64 + ret i64 %conv +; CHECK: @test12 +; CHECK: sext +; CHECK: ret +} + +define i32 @test13(i32 %x) nounwind { + %and = and i32 %x, 8 + %cmp = icmp eq i32 %and, 0 + %ext = sext i1 %cmp to i32 + ret i32 %ext +; CHECK: @test13 +; CHECK-NEXT: %and = lshr i32 %x, 3 +; CHECK-NEXT: %1 = and i32 %and, 1 +; CHECK-NEXT: %sext = add i32 %1, -1 +; CHECK-NEXT: ret i32 %sext +} + +define i32 @test14(i16 %x) nounwind { + %and = and i16 %x, 16 + %cmp = icmp ne i16 %and, 16 + %ext = sext i1 %cmp to i32 + ret i32 %ext +; CHECK: @test14 +; CHECK-NEXT: %and = lshr i16 %x, 4 +; CHECK-NEXT: %1 = and i16 %and, 1 +; CHECK-NEXT: %sext = add i16 %1, -1 +; CHECK-NEXT: %ext = sext i16 %sext to i32 +; CHECK-NEXT: ret i32 %ext +} + +define i32 @test15(i32 %x) nounwind { + %and = and i32 %x, 16 + %cmp = icmp ne i32 %and, 0 + %ext = sext i1 %cmp to i32 + ret i32 %ext +; CHECK: @test15 +; CHECK-NEXT: %1 = shl i32 %x, 27 +; CHECK-NEXT: %sext = ashr i32 %1, 31 +; CHECK-NEXT: ret i32 %sext +} + +define i32 @test16(i16 %x) nounwind { + %and = and i16 %x, 8 + %cmp = icmp eq i16 %and, 8 + %ext = sext i1 %cmp to i32 + ret i32 %ext +; CHECK: @test16 +; CHECK-NEXT: %1 = shl i16 %x, 12 +; CHECK-NEXT: %sext = ashr i16 %1, 15 +; CHECK-NEXT: %ext = sext i16 %sext to i32 +; CHECK-NEXT: ret i32 %ext +} diff --git a/test/Transforms/InstCombine/shift.ll b/test/Transforms/InstCombine/shift.ll index 7fab1d2cab54..bded68ac4755 100644 --- a/test/Transforms/InstCombine/shift.ll +++ b/test/Transforms/InstCombine/shift.ll @@ -485,3 +485,24 @@ entry: ; CHECK: ret i8 %tmp551 ret i8 %tmp55 } + +; PR9809 +define i32 @test40(i32 %a, i32 %b) nounwind { + %shl1 = shl i32 1, %b + %shl2 = shl i32 %shl1, 2 + %div = udiv i32 %a, %shl2 + ret i32 %div +; CHECK: @test40 +; CHECK-NEXT: add i32 %b, 2 +; CHECK-NEXT: lshr i32 %a +; CHECK-NEXT: ret i32 +} + +define i32 @test41(i32 %a, i32 %b) nounwind { + %1 = shl i32 1, %b + %2 = shl i32 %1, 3 + ret i32 %2 +; CHECK: @test41 +; CHECK-NEXT: shl i32 8, %b +; CHECK-NEXT: ret i32 +} diff --git a/test/Transforms/InstCombine/sign-test-and-or.ll b/test/Transforms/InstCombine/sign-test-and-or.ll new file mode 100644 index 000000000000..47f5f3051e46 --- /dev/null +++ b/test/Transforms/InstCombine/sign-test-and-or.ll @@ -0,0 +1,79 @@ +; RUN: opt -S -instcombine < %s | FileCheck %s + +declare void @foo() + +define void @test1(i32 %a, i32 %b) nounwind { + %1 = icmp slt i32 %a, 0 + %2 = icmp slt i32 %b, 0 + %or.cond = or i1 %1, %2 + br i1 %or.cond, label %if.then, label %if.end + +; CHECK: @test1 +; CHECK-NEXT: %1 = or i32 %a, %b +; CHECK-NEXT: %2 = icmp slt i32 %1, 0 +; CHECK-NEXT: br + +if.then: + tail call void @foo() nounwind + ret void + +if.end: + ret void +} + +define void @test2(i32 %a, i32 %b) nounwind { + %1 = icmp sgt i32 %a, -1 + %2 = icmp sgt i32 %b, -1 + %or.cond = or i1 %1, %2 + br i1 %or.cond, label %if.then, label %if.end + +; CHECK: @test2 +; CHECK-NEXT: %1 = and i32 %a, %b +; CHECK-NEXT: %2 = icmp sgt i32 %1, -1 +; CHECK-NEXT: br + +if.then: + tail call void @foo() nounwind + ret void + +if.end: + ret void +} + +define void @test3(i32 %a, i32 %b) nounwind { + %1 = icmp slt i32 %a, 0 + %2 = icmp slt i32 %b, 0 + %or.cond = and i1 %1, %2 + br i1 %or.cond, label %if.then, label %if.end + +; CHECK: @test3 +; CHECK-NEXT: %1 = and i32 %a, %b +; CHECK-NEXT: %2 = icmp slt i32 %1, 0 +; CHECK-NEXT: br + +if.then: + tail call void @foo() nounwind + ret void + +if.end: + ret void +} + +define void @test4(i32 %a, i32 %b) nounwind { + %1 = icmp sgt i32 %a, -1 + %2 = icmp sgt i32 %b, -1 + %or.cond = and i1 %1, %2 + br i1 %or.cond, label %if.then, label %if.end + +; CHECK: @test4 +; CHECK-NEXT: %1 = or i32 %a, %b +; CHECK-NEXT: %2 = icmp sgt i32 %1, -1 +; CHECK-NEXT: br + +if.then: + tail call void @foo() nounwind + ret void + +if.end: + ret void +} diff --git a/test/Transforms/InstCombine/strcpy_chk-64.ll b/test/Transforms/InstCombine/strcpy_chk-64.ll new file mode 100644 index 000000000000..036fcbe6de1d --- /dev/null +++ b/test/Transforms/InstCombine/strcpy_chk-64.ll @@ -0,0 +1,18 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +define void @func(i8* %i) nounwind ssp { +; CHECK: @func +; CHECK: @__strcpy_chk(i8* %arraydecay, i8* %i, i64 32) +entry: + %s = alloca [32 x i8], align 16 + %arraydecay = getelementptr inbounds [32 x i8]* %s, i32 0, i32 0 + %call = call i8* @__strcpy_chk(i8* %arraydecay, i8* %i, i64 32) + call void @func2(i8* %arraydecay) + ret void +} + +declare i8* @__strcpy_chk(i8*, i8*, i64) nounwind + +declare void @func2(i8*) diff --git a/test/Transforms/InstCombine/udivrem-change-width.ll b/test/Transforms/InstCombine/udivrem-change-width.ll index 9983944df8d7..b388a3b0634e 100644 --- a/test/Transforms/InstCombine/udivrem-change-width.ll +++ b/test/Transforms/InstCombine/udivrem-change-width.ll @@ -1,14 +1,16 @@ -; RUN: opt < %s -instcombine -S | not grep zext -; PR4548 +; RUN: opt < %s -instcombine -S | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +; PR4548 define i8 @udiv_i8(i8 %a, i8 %b) nounwind { %conv = zext i8 %a to i32 %conv2 = zext i8 %b to i32 %div = udiv i32 %conv, %conv2 %conv3 = trunc i32 %div to i8 ret i8 %conv3 +; CHECK: @udiv_i8 +; CHECK: udiv i8 %a, %b } define i8 @urem_i8(i8 %a, i8 %b) nounwind { @@ -17,5 +19,44 @@ define i8 @urem_i8(i8 %a, i8 %b) nounwind { %div = urem i32 %conv, %conv2 %conv3 = trunc i32 %div to i8 ret i8 %conv3 +; CHECK: @urem_i8 +; CHECK: urem i8 %a, %b } +define i32 @udiv_i32(i8 %a, i8 %b) nounwind { + %conv = zext i8 %a to i32 + %conv2 = zext i8 %b to i32 + %div = udiv i32 %conv, %conv2 + ret i32 %div +; CHECK: @udiv_i32 +; CHECK: udiv i8 %a, %b +; CHECK: zext +} + +define i32 @urem_i32(i8 %a, i8 %b) nounwind { + %conv = zext i8 %a to i32 + %conv2 = zext i8 %b to i32 + %div = urem i32 %conv, %conv2 + ret i32 %div +; CHECK: @urem_i32 +; CHECK: urem i8 %a, %b +; CHECK: zext +} + +define i32 @udiv_i32_c(i8 %a) nounwind { + %conv = zext i8 %a to i32 + %div = udiv i32 %conv, 10 + ret i32 %div +; CHECK: @udiv_i32_c +; CHECK: udiv i8 %a, 10 +; CHECK: zext +} + +define i32 @urem_i32_c(i8 %a) nounwind { + %conv = zext i8 %a to i32 + %div = urem i32 %conv, 10 + ret i32 %div +; CHECK: @urem_i32_c +; CHECK: urem i8 %a, 10 +; CHECK: zext +} diff --git a/test/Transforms/InstSimplify/compare.ll b/test/Transforms/InstSimplify/compare.ll index 250e44ce340f..d2c564f567b4 100644 --- a/test/Transforms/InstSimplify/compare.ll +++ b/test/Transforms/InstSimplify/compare.ll @@ -137,22 +137,38 @@ define i1 @shl(i32 %x) { ; CHECK: ret i1 false } -define i1 @lshr(i32 %x) { -; CHECK: @lshr +define i1 @lshr1(i32 %x) { +; CHECK: @lshr1 %s = lshr i32 -1, %x %c = icmp eq i32 %s, 0 ret i1 %c ; CHECK: ret i1 false } -define i1 @ashr(i32 %x) { -; CHECK: @ashr +define i1 @lshr2(i32 %x) { +; CHECK: @lshr2 + %s = lshr i32 %x, 30 + %c = icmp ugt i32 %s, 8 + ret i1 %c +; CHECK: ret i1 false +} + +define i1 @ashr1(i32 %x) { +; CHECK: @ashr1 %s = ashr i32 -1, %x %c = icmp eq i32 %s, 0 ret i1 %c ; CHECK: ret i1 false } +define i1 @ashr2(i32 %x) { +; CHECK: @ashr2 + %s = ashr i32 %x, 30 + %c = icmp slt i32 %s, -5 + ret i1 %c +; CHECK: ret i1 false +} + define i1 @select1(i1 %cond) { ; CHECK: @select1 %s = select i1 %cond, i32 1, i32 0 @@ -187,3 +203,134 @@ define i1 @select4(i1 %cond) { ret i1 %c ; CHECK: ret i1 %cond } + +define i1 @urem1(i32 %X, i32 %Y) { +; CHECK: @urem1 + %A = urem i32 %X, %Y + %B = icmp ult i32 %A, %Y + ret i1 %B +; CHECK: ret i1 true +} + +define i1 @urem2(i32 %X, i32 %Y) { +; CHECK: @urem2 + %A = urem i32 %X, %Y + %B = icmp eq i32 %A, %Y + ret i1 %B +; CHECK: ret i1 false +} + +define i1 @urem3(i32 %X) { +; CHECK: @urem3 + %A = urem i32 %X, 10 + %B = icmp ult i32 %A, 15 + ret i1 %B +; CHECK: ret i1 true +} + +define i1 @urem4(i32 %X) { +; CHECK: @urem4 + %A = urem i32 %X, 15 + %B = icmp ult i32 %A, 10 + ret i1 %B +; CHECK: ret i1 %B +} + +define i1 @urem5(i16 %X, i32 %Y) { +; CHECK: @urem5 + %A = zext i16 %X to i32 + %B = urem i32 %A, %Y + %C = icmp slt i32 %B, %Y + ret i1 %C +; CHECK: ret i1 true +} + +define i1 @urem6(i32 %X, i32 %Y) { +; CHECK: @urem6 + %A = urem i32 %X, %Y + %B = icmp ugt i32 %Y, %A + ret i1 %B +; CHECK: ret i1 true +} + +define i1 @srem1(i32 %X) { +; CHECK: @srem1 + %A = srem i32 %X, -5 + %B = icmp sgt i32 %A, 5 + ret i1 %B +; CHECK: ret i1 false +} + +; PR9343 #15 +; CHECK: @srem2 +; CHECK: ret i1 false +define i1 @srem2(i16 %X, i32 %Y) { + %A = zext i16 %X to i32 + %B = add nsw i32 %A, 1 + %C = srem i32 %B, %Y + %D = icmp slt i32 %C, 0 + ret i1 %D +} + +; CHECK: @srem3 +; CHECK-NEXT: ret i1 false +define i1 @srem3(i16 %X, i32 %Y) { + %A = zext i16 %X to i32 + %B = or i32 2147483648, %A + %C = sub nsw i32 1, %B + %D = srem i32 %C, %Y + %E = icmp slt i32 %D, 0 + ret i1 %E +} + +; CHECK: @srem4 +; CHECK-NEXT: ret i1 false +define i1 @srem4(i16 %X, i32 %Y) { + %A = zext i16 %X to i32 + %B = or i32 2147483648, %A + %C = sub nsw i32 %A, %B + %D = srem i32 %C, %Y + %E = icmp slt i32 %D, 0 + ret i1 %E +} + +define i1 @udiv1(i32 %X) { +; CHECK: @udiv1 + %A = udiv i32 %X, 1000000 + %B = icmp ult i32 %A, 5000 + ret i1 %B +; CHECK: ret i1 true +} + +define i1 @udiv2(i32 %X, i32 %Y, i32 %Z) { +; CHECK: @udiv2 + %A = udiv exact i32 10, %Z + %B = udiv exact i32 20, %Z + %C = icmp ult i32 %A, %B + ret i1 %C +; CHECK: ret i1 true +} + +define i1 @sdiv1(i32 %X) { +; CHECK: @sdiv1 + %A = sdiv i32 %X, 1000000 + %B = icmp slt i32 %A, 3000 + ret i1 %B +; CHECK: ret i1 true +} + +define i1 @or1(i32 %X) { +; CHECK: @or1 + %A = or i32 %X, 62 + %B = icmp ult i32 %A, 50 + ret i1 %B +; CHECK: ret i1 false +} + +define i1 @and1(i32 %X) { +; CHECK: @and1 + %A = and i32 %X, 62 + %B = icmp ugt i32 %A, 70 + ret i1 %B +; CHECK: ret i1 false +} diff --git a/test/Transforms/InstSimplify/rem.ll b/test/Transforms/InstSimplify/rem.ll new file mode 100644 index 000000000000..4c8f87cf5e92 --- /dev/null +++ b/test/Transforms/InstSimplify/rem.ll @@ -0,0 +1,17 @@ +; RUN: opt < %s -instsimplify -S | FileCheck %s + +define i32 @select1(i32 %x, i1 %b) { +; CHECK: @select1 + %rhs = select i1 %b, i32 %x, i32 1 + %rem = srem i32 %x, %rhs + ret i32 %rem +; CHECK: ret i32 0 +} + +define i32 @select2(i32 %x, i1 %b) { +; CHECK: @select2 + %rhs = select i1 %b, i32 %x, i32 1 + %rem = urem i32 %x, %rhs + ret i32 %rem +; CHECK: ret i32 0 +} diff --git a/test/Transforms/Internalize/available_externally.ll b/test/Transforms/Internalize/available_externally.ll new file mode 100644 index 000000000000..a2cf23fb3909 --- /dev/null +++ b/test/Transforms/Internalize/available_externally.ll @@ -0,0 +1,16 @@ +; RUN: opt < %s -internalize -internalize-public-api-list foo -S | FileCheck %s + +; CHECK: define void @foo +define void @foo() { + ret void +} + +; CHECK: define internal void @zed +define void @zed() { + ret void +} + +; CHECK: define available_externally void @bar +define available_externally void @bar() { + ret void +} diff --git a/test/Transforms/JumpThreading/2011-04-02-SimplifyDeadBlock.ll b/test/Transforms/JumpThreading/2011-04-02-SimplifyDeadBlock.ll new file mode 100644 index 000000000000..76dd2d12bdec --- /dev/null +++ b/test/Transforms/JumpThreading/2011-04-02-SimplifyDeadBlock.ll @@ -0,0 +1,32 @@ +; RUN: opt < %s -jump-threading +; PR9446 +; Just check that it doesn't crash + +define void @int327() nounwind { +entry: + unreachable + +for.cond: ; preds = %for.cond4 + %tobool3 = icmp eq i8 undef, 0 + br i1 %tobool3, label %for.cond23, label %for.cond4 + +for.cond4: ; preds = %for.cond + br label %for.cond + +for.cond23: ; preds = %for.body28, %for.cond23, %for.cond + %conv321 = phi i32 [ %conv32, %for.body28 ], [ 0, %for.cond ], [ %conv321, %for.cond23 ] + %l_266.0 = phi i32 [ %phitmp, %for.body28 ], [ 0, %for.cond ], [ 0, %for.cond23 ] + %cmp26 = icmp eq i32 %l_266.0, 0 + br i1 %cmp26, label %for.body28, label %for.cond23 + +for.body28: ; preds = %for.cond23 + %and = and i32 %conv321, 1 + %conv32 = zext i8 undef to i32 + %add = add nsw i32 %l_266.0, 1 + %phitmp = and i32 %add, 255 + br label %for.cond23 + +if.end43: ; No predecessors! + ret void +} + diff --git a/test/Transforms/JumpThreading/2011-04-14-InfLoop.ll b/test/Transforms/JumpThreading/2011-04-14-InfLoop.ll new file mode 100644 index 000000000000..46aaa00380e3 --- /dev/null +++ b/test/Transforms/JumpThreading/2011-04-14-InfLoop.ll @@ -0,0 +1,31 @@ +; RUN: opt -jump-threading < %s +; <rdar://problem/9284786> + +%0 = type <{ i64, i16, i64, i8, i8 }> + +@g_338 = external global %0, align 8 + +define void @func_1() nounwind ssp { +entry: + ret void + +for.cond1177: + %inc1187 = add nsw i32 0, 1 + %cmp1179 = icmp slt i32 %inc1187, 5 + br i1 %cmp1179, label %for.cond1177, label %land.rhs1320 + +land.rhs1320: + %tmp1324 = volatile load i64* getelementptr inbounds (%0* @g_338, i64 0, i32 2), align 1, !tbaa !0 + br label %if.end.i + +if.end.i: + %tobool.pr.i = phi i1 [ false, %if.end.i ], [ false, %land.rhs1320 ] + br i1 %tobool.pr.i, label %return, label %if.end.i + +return: + ret void +} + +!0 = metadata !{metadata !"long long", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/Transforms/JumpThreading/pr9331.ll b/test/Transforms/JumpThreading/pr9331.ll new file mode 100644 index 000000000000..4c06d526ca18 --- /dev/null +++ b/test/Transforms/JumpThreading/pr9331.ll @@ -0,0 +1,50 @@ +; RUN: opt -jump-threading -S < %s + +define void @func(i8 zeroext %p_44) nounwind { +entry: + br i1 false, label %for.cond2, label %if.end50 + +for.cond2: ; preds = %for.inc46, %lor.end, %entry + %p_44.addr.1 = phi i8 [ %p_44.addr.1, %lor.end ], [ %p_44, %entry ], [ %p_44.addr.1, %for.inc46 ] + br i1 undef, label %for.inc46, label %for.body5 + +for.body5: ; preds = %for.cond2 + br i1 undef, label %lbl_465, label %if.then9 + +if.then9: ; preds = %for.body5 + br label %return + +lbl_465: ; preds = %lbl_465, %for.body5 + %tobool19 = icmp eq i8 undef, 0 + br i1 %tobool19, label %if.end21, label %lbl_465 + +if.end21: ; preds = %lbl_465 + %conv23 = zext i8 %p_44.addr.1 to i64 + %xor = xor i64 %conv23, 1 + %tobool.i = icmp eq i64 %conv23, 0 + br i1 %tobool.i, label %cond.false.i, label %safe_mod_func_uint64_t_u_u.exit + +cond.false.i: ; preds = %if.end21 + %div.i = udiv i64 %xor, %conv23 + br label %safe_mod_func_uint64_t_u_u.exit + +safe_mod_func_uint64_t_u_u.exit: ; preds = %cond.false.i, %if.end21 + %cond.i = phi i64 [ %div.i, %cond.false.i ], [ %conv23, %if.end21 ] + %tobool28 = icmp eq i64 %cond.i, 0 + br i1 %tobool28, label %lor.rhs, label %lor.end + +lor.rhs: ; preds = %safe_mod_func_uint64_t_u_u.exit + br label %lor.end + +lor.end: ; preds = %lor.rhs, %safe_mod_func_uint64_t_u_u.exit + br label %for.cond2 + +for.inc46: ; preds = %for.cond2 + br label %for.cond2 + +if.end50: ; preds = %entry + br label %return + +return: ; preds = %if.end50, %if.then9 + ret void +} diff --git a/test/Transforms/LCSSA/2006-06-03-IncorrectIDFPhis.ll b/test/Transforms/LCSSA/2006-06-03-IncorrectIDFPhis.ll index 7a80f8052b0d..153458579b89 100644 --- a/test/Transforms/LCSSA/2006-06-03-IncorrectIDFPhis.ll +++ b/test/Transforms/LCSSA/2006-06-03-IncorrectIDFPhis.ll @@ -1,7 +1,5 @@ ; RUN: opt < %s -loop-simplify -lcssa -S | \ ; RUN: grep {%%SJE.0.0.lcssa = phi .struct.SetJmpMapEntry} -; RUN: opt < %s -loop-simplify -lcssa -S | \ -; RUN: grep {%%SJE.0.0.lcssa1 = phi .struct.SetJmpMapEntry} %struct.SetJmpMapEntry = type { i8*, i32, %struct.SetJmpMapEntry* } diff --git a/test/Transforms/LCSSA/unused-phis.ll b/test/Transforms/LCSSA/unused-phis.ll new file mode 100644 index 000000000000..aa2ab963411d --- /dev/null +++ b/test/Transforms/LCSSA/unused-phis.ll @@ -0,0 +1,38 @@ +; RUN: opt < %s -lcssa -S | FileCheck %s +; CHECK: exit1: +; CHECK: .lcssa = +; CHECK: exit2: +; CHECK: .lcssa2 = +; CHECK: exit3: +; CHECK-NOT: .lcssa1 = + +; Test to ensure that when there are multiple exit blocks, PHI nodes are +; only inserted by LCSSA when there is a use dominated by a given exit +; block. + +declare void @printf(i32 %i) + +define i32 @unused_phis() nounwind { +entry: + br label %loop + +loop: + %i = phi i32 [0, %entry], [1, %then2] + br i1 undef, label %exit1, label %then1 + +then1: + br i1 undef, label %exit2, label %then2 + +then2: + br i1 undef, label %exit3, label %loop + +exit1: + call void @printf(i32 %i) + ret i32 %i + +exit2: + ret i32 %i + +exit3: + ret i32 0 +} diff --git a/test/Transforms/LICM/2007-10-01-PromoteSafeValue.ll b/test/Transforms/LICM/2007-10-01-PromoteSafeValue.ll index 59f1dcbe2d7b..e3d0d02edd9d 100644 --- a/test/Transforms/LICM/2007-10-01-PromoteSafeValue.ll +++ b/test/Transforms/LICM/2007-10-01-PromoteSafeValue.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -licm -S | grep promoted +; RUN: opt < %s -licm -S | FileCheck %s ; Promote value if at least one use is safe @@ -15,6 +15,8 @@ cond.true: ; preds = %loop.head store i32 40, i32* %p br label %loop.head +; CHECK: exit: +; CHECK: store i32 20, i32* %p exit: ; preds = %loop.head ret i32 0 } diff --git a/test/Transforms/LICM/2011-04-06-HoistMissedASTUpdate.ll b/test/Transforms/LICM/2011-04-06-HoistMissedASTUpdate.ll new file mode 100644 index 000000000000..5774f587f1c3 --- /dev/null +++ b/test/Transforms/LICM/2011-04-06-HoistMissedASTUpdate.ll @@ -0,0 +1,32 @@ +; RUN: opt < %s -basicaa -licm -S | FileCheck %s +; PR9630 + +@g_39 = external global i16, align 2 + +declare i32* @func_84(i32** nocapture) nounwind readonly + +declare i32** @func_108(i32*** nocapture) nounwind readonly + +define void @func() nounwind { +entry: + br label %for.body4.lr.ph + +for.body4.lr.ph: + br label %for.body4 + +; CHECK: for.body4: +; CHECK: volatile load i16* @g_39 + +for.body4: + %l_612.11 = phi i32* [ undef, %for.body4.lr.ph ], [ %call19, %for.body4 ] + %tmp7 = volatile load i16* @g_39, align 2 + %call = call i32** @func_108(i32*** undef) + %call19 = call i32* @func_84(i32** %call) + br i1 false, label %for.body4, label %for.cond.loopexit + +for.cond.loopexit: + br i1 false, label %for.body4.lr.ph, label %for.end26 + +for.end26: + ret void +} diff --git a/test/Transforms/LICM/2011-04-06-PromoteResultOfPromotion.ll b/test/Transforms/LICM/2011-04-06-PromoteResultOfPromotion.ll new file mode 100644 index 000000000000..86c2679b076a --- /dev/null +++ b/test/Transforms/LICM/2011-04-06-PromoteResultOfPromotion.ll @@ -0,0 +1,37 @@ +; RUN: opt < %s -tbaa -licm -S | FileCheck %s +; PR9634 + +@g_58 = common global i32 0, align 4 +@g_116 = common global i32* null, align 8 + +define void @f() nounwind { + +; CHECK: entry: +; CHECK: alloca [9 x i16] +; CHECK: load i32* @g_58 +; CHECK: br label %for.body + +entry: + %l_87.i = alloca [9 x i16], align 16 + br label %for.body + +for.body: ; preds = %entry, %for.inc + %inc12 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + store i32* @g_58, i32** @g_116, align 8, !tbaa !0 + %tmp2 = load i32** @g_116, align 8, !tbaa !0 + %tmp3 = load i32* %tmp2, !tbaa !4 + %or = or i32 %tmp3, 10 + store i32 %or, i32* %tmp2, !tbaa !4 + %inc = add nsw i32 %inc12, 1 + %cmp = icmp slt i32 %inc, 4 + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.inc + ret void +} + +!0 = metadata !{metadata !"any pointer", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} +!3 = metadata !{metadata !"short", metadata !1} +!4 = metadata !{metadata !"int", metadata !1} diff --git a/test/Transforms/LICM/2011-04-09-RAUW-AST.ll b/test/Transforms/LICM/2011-04-09-RAUW-AST.ll new file mode 100644 index 000000000000..4285bd19e5f1 --- /dev/null +++ b/test/Transforms/LICM/2011-04-09-RAUW-AST.ll @@ -0,0 +1,49 @@ +; RUN: opt < %s -loop-rotate -licm -S | FileCheck %s +; PR9604 + +@g_3 = global i32 0, align 4 +@.str = private unnamed_addr constant [4 x i8] c"%d\0A\00" + +define i32 @main() nounwind { +entry: + %tmp = load i32* @g_3, align 4 + %tobool = icmp eq i32 %tmp, 0 + br i1 %tobool, label %for.cond, label %if.then + +if.then: ; preds = %entry + br label %for.cond + +for.cond: ; preds = %for.inc10, %if.then, %entry + %g.0 = phi i32* [ %g.0, %for.inc10 ], [ @g_3, %entry ], [ null, %if.then ] + %x.0 = phi i32 [ %inc12, %for.inc10 ], [ 0, %entry ], [ 0, %if.then ] + %cmp = icmp slt i32 %x.0, 5 + br i1 %cmp, label %for.cond4, label %for.end13 + +for.cond4: ; preds = %for.body7, %for.cond + %y.0 = phi i32 [ %inc, %for.body7 ], [ 0, %for.cond ] + %cmp6 = icmp slt i32 %y.0, 5 + br i1 %cmp6, label %for.body7, label %for.inc10 + +; CHECK: for.body7: +; CHECK-NEXT: phi +; CHECK-NEXT: store i32 0 +; CHECK-NEXT: store i32 1 + +for.body7: ; preds = %for.cond4 + store i32 0, i32* @g_3, align 4 + store i32 1, i32* %g.0, align 4 + %inc = add nsw i32 %y.0, 1 + br label %for.cond4 + +for.inc10: ; preds = %for.cond4 + %inc12 = add nsw i32 %x.0, 1 + br label %for.cond + +for.end13: ; preds = %for.cond + %tmp14 = load i32* @g_3, align 4 + %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32 %tmp14) nounwind + ret i32 0 +} + +declare i32 @printf(i8* nocapture, ...) nounwind + diff --git a/test/Transforms/LICM/debug-value.ll b/test/Transforms/LICM/debug-value.ll new file mode 100644 index 000000000000..889d4e2e3af9 --- /dev/null +++ b/test/Transforms/LICM/debug-value.ll @@ -0,0 +1,62 @@ +; RUN: opt -licm -basicaa < %s -S | FileCheck %s + +define void @dgefa() nounwind ssp { +entry: + br label %for.body + +for.body: ; preds = %for.cond.backedge, %entry + br i1 undef, label %if.then, label %for.cond.backedge, !dbg !11 + +for.cond.backedge: ; preds = %for.body61, %for.body61.us, %for.body + br i1 undef, label %for.end104, label %for.body, !dbg !15 + +if.then: ; preds = %for.body + br i1 undef, label %if.then27, label %if.end.if.end.split_crit_edge.critedge, !dbg !16 + +if.then27: ; preds = %if.then +; CHECK: tail call void @llvm.dbg.value + tail call void @llvm.dbg.value(metadata !18, i64 0, metadata !19), !dbg !21 + br label %for.body61.us + +if.end.if.end.split_crit_edge.critedge: ; preds = %if.then + br label %for.body61 + +for.body61.us: ; preds = %for.body61.us, %if.then27 + br i1 undef, label %for.cond.backedge, label %for.body61.us, !dbg !23 + +for.body61: ; preds = %for.body61, %if.end.if.end.split_crit_edge.critedge + br i1 undef, label %for.cond.backedge, label %for.body61, !dbg !23 + +for.end104: ; preds = %for.cond.backedge + ret void, !dbg !24 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.sp = !{!0, !6, !9, !10} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"idamax", metadata !"idamax", metadata !"", metadata !1, i32 112, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/Benchmarks/CoyoteBench/lpbench.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/Benchmarks/CoyoteBench/lpbench.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 127169)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 589870, i32 0, metadata !1, metadata !"dscal", metadata !"dscal", metadata !"", metadata !1, i32 206, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, null} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!8 = metadata !{null} +!9 = metadata !{i32 589870, i32 0, metadata !1, metadata !"daxpy", metadata !"daxpy", metadata !"", metadata !1, i32 230, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, null} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 589870, i32 0, metadata !1, metadata !"dgefa", metadata !"dgefa", metadata !"", metadata !1, i32 267, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 281, i32 9, metadata !12, null} +!12 = metadata !{i32 589835, metadata !13, i32 272, i32 5, metadata !1, i32 32} ; [ DW_TAG_lexical_block ] +!13 = metadata !{i32 589835, metadata !14, i32 271, i32 5, metadata !1, i32 31} ; [ DW_TAG_lexical_block ] +!14 = metadata !{i32 589835, metadata !10, i32 267, i32 1, metadata !1, i32 30} ; [ DW_TAG_lexical_block ] +!15 = metadata !{i32 271, i32 5, metadata !14, null} +!16 = metadata !{i32 284, i32 10, metadata !17, null} +!17 = metadata !{i32 589835, metadata !12, i32 282, i32 9, metadata !1, i32 33} ; [ DW_TAG_lexical_block ] +!18 = metadata !{double undef} +!19 = metadata !{i32 590080, metadata !14, metadata !"temp", metadata !1, i32 268, metadata !20, i32 0} ; [ DW_TAG_auto_variable ] +!20 = metadata !{i32 589860, metadata !2, metadata !"double", null, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!21 = metadata !{i32 286, i32 14, metadata !22, null} +!22 = metadata !{i32 589835, metadata !17, i32 285, i32 13, metadata !1, i32 34} ; [ DW_TAG_lexical_block ] +!23 = metadata !{i32 296, i32 13, metadata !17, null} +!24 = metadata !{i32 313, i32 1, metadata !14, null} diff --git a/test/Transforms/LoopIdiom/debug-line.ll b/test/Transforms/LoopIdiom/debug-line.ll new file mode 100644 index 000000000000..d31662d57e98 --- /dev/null +++ b/test/Transforms/LoopIdiom/debug-line.ll @@ -0,0 +1,49 @@ +; RUN: opt -loop-idiom < %s -S | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + + +define void @foo(double* nocapture %a) nounwind ssp { +entry: + tail call void @llvm.dbg.value(metadata !{double* %a}, i64 0, metadata !5), !dbg !8 + tail call void @llvm.dbg.value(metadata !9, i64 0, metadata !10), !dbg !14 + br label %for.body + +for.body: ; preds = %entry, %for.body + %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %for.body ] + %arrayidx = getelementptr double* %a, i64 %indvar +; CHECK: call void @llvm.memset{{.+}} !dbg + store double 0.000000e+00, double* %arrayidx, align 8, !dbg !15 + %indvar.next = add i64 %indvar, 1 + %exitcond = icmp ne i64 %indvar.next, 1000 + br i1 %exitcond, label %for.body, label %for.end, !dbg !14 + +for.end: ; preds = %for.body + tail call void @llvm.dbg.value(metadata !{null}, i64 0, metadata !10), !dbg !16 + ret void, !dbg !17 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.sp = !{!0} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (double*)* @foo} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"li.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"li.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 127165:127174)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{null} +!5 = metadata !{i32 590081, metadata !0, metadata !"a", metadata !1, i32 16777218, metadata !6, i32 0} ; [ DW_TAG_arg_variable ] +!6 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !7} ; [ DW_TAG_pointer_type ] +!7 = metadata !{i32 589860, metadata !2, metadata !"double", null, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!8 = metadata !{i32 2, i32 18, metadata !0, null} +!9 = metadata !{i32 0} +!10 = metadata !{i32 590080, metadata !11, metadata !"i", metadata !1, i32 3, metadata !13, i32 0} ; [ DW_TAG_auto_variable ] +!11 = metadata !{i32 589835, metadata !12, i32 3, i32 3, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] +!12 = metadata !{i32 589835, metadata !0, i32 2, i32 21, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!13 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{i32 3, i32 3, metadata !12, null} +!15 = metadata !{i32 4, i32 5, metadata !11, null} +!16 = metadata !{i32 3, i32 29, metadata !11, null} +!17 = metadata !{i32 5, i32 1, metadata !12, null} diff --git a/test/Transforms/LoopRotate/crash.ll b/test/Transforms/LoopRotate/crash.ll index 9dc9862d150a..16a6868f8ff1 100644 --- a/test/Transforms/LoopRotate/crash.ll +++ b/test/Transforms/LoopRotate/crash.ll @@ -137,3 +137,19 @@ bb17: ; preds = %bb15 } + + +; PR9523 - Non-canonical loop. +define void @test7(i8* %P) nounwind { +entry: + indirectbr i8* %P, [label %"3", label %"5"] + +"3": ; preds = %"4", %entry + br i1 undef, label %"5", label %"4" + +"4": ; preds = %"3" + br label %"3" + +"5": ; preds = %"3", %entry + ret void +} diff --git a/test/Transforms/LoopSimplify/merge-exits.ll b/test/Transforms/LoopSimplify/merge-exits.ll index 93a224744ca3..e5e471766b9a 100644 --- a/test/Transforms/LoopSimplify/merge-exits.ll +++ b/test/Transforms/LoopSimplify/merge-exits.ll @@ -7,7 +7,7 @@ ; that indvars can promote the induction variable to i64 ; without needing casts. -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n:32:64" define float @t(float* %pTmp1, float* %peakWeight, i32 %bandEdgeIndex) nounwind { entry: diff --git a/test/Transforms/LoopStrengthReduce/invariant_value_first.ll b/test/Transforms/LoopStrengthReduce/invariant_value_first.ll index 4094e9c7e4d9..986a55a3f6c4 100644 --- a/test/Transforms/LoopStrengthReduce/invariant_value_first.ll +++ b/test/Transforms/LoopStrengthReduce/invariant_value_first.ll @@ -1,7 +1,8 @@ ; Check that the index of 'P[outer]' is pulled out of the loop. -; RUN: opt < %s -loop-reduce -S -default-data-layout="e-p:32:32:32" | \ +; RUN: opt < %s -loop-reduce -S | \ ; RUN: not grep {getelementptr.*%outer.*%INDVAR} +target datalayout = "e-p:32:32:32-n:8:16:32" declare i1 @pred() declare i32 @foo() diff --git a/test/Transforms/LoopStrengthReduce/invariant_value_first_arg.ll b/test/Transforms/LoopStrengthReduce/invariant_value_first_arg.ll index e2aed78c32e3..1d43961c356e 100644 --- a/test/Transforms/LoopStrengthReduce/invariant_value_first_arg.ll +++ b/test/Transforms/LoopStrengthReduce/invariant_value_first_arg.ll @@ -1,7 +1,8 @@ ; Check that the index of 'P[outer]' is pulled out of the loop. -; RUN: opt < %s -loop-reduce -S -default-data-layout="e-p:32:32:32" | \ +; RUN: opt < %s -loop-reduce -S | \ ; RUN: not grep {getelementptr.*%outer.*%INDVAR} +target datalayout = "e-p:32:32:32-n:32" declare i1 @pred() define void @test([10000 x i32]* %P, i32 %outer) { diff --git a/test/Transforms/LoopStrengthReduce/ops_after_indvar.ll b/test/Transforms/LoopStrengthReduce/ops_after_indvar.ll index 410d88f672b5..00bd068d0b8f 100644 --- a/test/Transforms/LoopStrengthReduce/ops_after_indvar.ll +++ b/test/Transforms/LoopStrengthReduce/ops_after_indvar.ll @@ -1,7 +1,9 @@ ; Check that this test makes INDVAR and related stuff dead, because P[indvar] ; gets reduced, making INDVAR dead. -; RUN: opt < %s -loop-reduce -S -default-data-layout="e-p:32:32:32" | not grep INDVAR +; RUN: opt < %s -loop-reduce -S | not grep INDVAR + +target datalayout = "e-p:32:32:32-n:32" declare i1 @pred() diff --git a/test/Transforms/LoopStrengthReduce/var_stride_used_by_compare.ll b/test/Transforms/LoopStrengthReduce/var_stride_used_by_compare.ll index 0a9fab0d5ea8..7547d8362929 100644 --- a/test/Transforms/LoopStrengthReduce/var_stride_used_by_compare.ll +++ b/test/Transforms/LoopStrengthReduce/var_stride_used_by_compare.ll @@ -9,7 +9,7 @@ ; mul uint %i, 3 -target datalayout = "e-p:32:32" +target datalayout = "e-p:32:32-n:32" target triple = "i686-apple-darwin8" @flags2 = external global [8193 x i8], align 32 ; <[8193 x i8]*> [#uses=1] diff --git a/test/Transforms/PhaseOrdering/basic.ll b/test/Transforms/PhaseOrdering/basic.ll new file mode 100644 index 000000000000..c66e150aa794 --- /dev/null +++ b/test/Transforms/PhaseOrdering/basic.ll @@ -0,0 +1,117 @@ +; RUN: opt -O3 -S %s | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-macosx10.6.7" + +declare i8* @malloc(i64) +declare void @free(i8*) + + +; PR2338 +define void @test1() nounwind ssp { + %retval = alloca i32, align 4 + %i = alloca i8*, align 8 + %call = call i8* @malloc(i64 1) + store i8* %call, i8** %i, align 8 + %tmp = load i8** %i, align 8 + store i8 1, i8* %tmp + %tmp1 = load i8** %i, align 8 + call void @free(i8* %tmp1) + ret void + +; CHECK: @test1 +; CHECK-NEXT: ret void +} + + +; PR6627 - This whole nasty sequence should be flattened down to a single +; 32-bit comparison. +define void @test2(i8* %arrayidx) nounwind ssp { +entry: + %xx = bitcast i8* %arrayidx to i32* + %x1 = load i32* %xx, align 4 + %tmp = trunc i32 %x1 to i8 + %conv = zext i8 %tmp to i32 + %cmp = icmp eq i32 %conv, 127 + br i1 %cmp, label %land.lhs.true, label %if.end + +land.lhs.true: ; preds = %entry + %arrayidx4 = getelementptr inbounds i8* %arrayidx, i64 1 + %tmp5 = load i8* %arrayidx4, align 1 + %conv6 = zext i8 %tmp5 to i32 + %cmp7 = icmp eq i32 %conv6, 69 + br i1 %cmp7, label %land.lhs.true9, label %if.end + +land.lhs.true9: ; preds = %land.lhs.true + %arrayidx12 = getelementptr inbounds i8* %arrayidx, i64 2 + %tmp13 = load i8* %arrayidx12, align 1 + %conv14 = zext i8 %tmp13 to i32 + %cmp15 = icmp eq i32 %conv14, 76 + br i1 %cmp15, label %land.lhs.true17, label %if.end + +land.lhs.true17: ; preds = %land.lhs.true9 + %arrayidx20 = getelementptr inbounds i8* %arrayidx, i64 3 + %tmp21 = load i8* %arrayidx20, align 1 + %conv22 = zext i8 %tmp21 to i32 + %cmp23 = icmp eq i32 %conv22, 70 + br i1 %cmp23, label %if.then, label %if.end + +if.then: ; preds = %land.lhs.true17 + %call25 = call i32 (...)* @doo() + br label %if.end + +if.end: + ret void + +; CHECK: @test2 +; CHECK: %x1 = load i32* %xx, align 4 +; CHECK-NEXT: icmp eq i32 %x1, 1179403647 +; CHECK-NEXT: br i1 {{.*}}, label %if.then, label %if.end +} + +declare i32 @doo(...) + +; PR6627 - This should all be flattened down to one compare. This is the same +; as test2, except that the initial load is done as an i8 instead of i32, thus +; requiring widening. +define void @test2a(i8* %arrayidx) nounwind ssp { +entry: + %x1 = load i8* %arrayidx, align 4 + %conv = zext i8 %x1 to i32 + %cmp = icmp eq i32 %conv, 127 + br i1 %cmp, label %land.lhs.true, label %if.end + +land.lhs.true: ; preds = %entry + %arrayidx4 = getelementptr inbounds i8* %arrayidx, i64 1 + %tmp5 = load i8* %arrayidx4, align 1 + %conv6 = zext i8 %tmp5 to i32 + %cmp7 = icmp eq i32 %conv6, 69 + br i1 %cmp7, label %land.lhs.true9, label %if.end + +land.lhs.true9: ; preds = %land.lhs.true + %arrayidx12 = getelementptr inbounds i8* %arrayidx, i64 2 + %tmp13 = load i8* %arrayidx12, align 1 + %conv14 = zext i8 %tmp13 to i32 + %cmp15 = icmp eq i32 %conv14, 76 + br i1 %cmp15, label %land.lhs.true17, label %if.end + +land.lhs.true17: ; preds = %land.lhs.true9 + %arrayidx20 = getelementptr inbounds i8* %arrayidx, i64 3 + %tmp21 = load i8* %arrayidx20, align 1 + %conv22 = zext i8 %tmp21 to i32 + %cmp23 = icmp eq i32 %conv22, 70 + br i1 %cmp23, label %if.then, label %if.end + +if.then: ; preds = %land.lhs.true17 + %call25 = call i32 (...)* @doo() + br label %if.end + +if.end: + ret void + +; CHECK: @test2a +; CHECK: %x1 = load i32* {{.*}}, align 4 +; CHECK-NEXT: icmp eq i32 %x1, 1179403647 +; CHECK-NEXT: br i1 {{.*}}, label %if.then, label %if.end +} + diff --git a/test/Transforms/Reassociate/crash.ll b/test/Transforms/Reassociate/crash.ll index 6f21b66ed005..7a819422eab8 100644 --- a/test/Transforms/Reassociate/crash.ll +++ b/test/Transforms/Reassociate/crash.ll @@ -42,3 +42,28 @@ define i32 @test3(i32 %Arg, i32 %x1, i32 %x2, i32 %x3) { %E = add i32 %D, %C ret i32 %E } + + +; rdar://9096268 +define void @x66303361ae3f602889d1b7d0f86e5455(i8* %arg) nounwind { +_: + br label %_33 + +_33: ; preds = %_33, %_ + %tmp348 = load i8* %arg, align 1 + %tmp349 = lshr i8 %tmp348, 7 + %tmp350 = or i8 %tmp349, 42 + %tmp351 = add i8 %tmp350, -42 + %tmp352 = zext i8 %tmp351 to i32 + %tmp358 = add i32 %tmp352, -501049439 + %tmp359 = mul i32 %tmp358, %tmp358 + %tmp360 = mul i32 %tmp352, %tmp352 + %tmp361 = sub i32 %tmp359, %tmp360 + %tmp362 = mul i32 %tmp361, -920056735 + %tmp363 = add i32 %tmp362, 501049439 + %tmp364 = add i32 %tmp362, -2000262972 + %tmp365 = sub i32 %tmp363, %tmp364 + %tmp366 = sub i32 -501049439, %tmp362 + %tmp367 = add i32 %tmp365, %tmp366 + br label %_33 +} diff --git a/test/Transforms/Reassociate/secondary.ll b/test/Transforms/Reassociate/secondary.ll new file mode 100644 index 000000000000..a52000ada537 --- /dev/null +++ b/test/Transforms/Reassociate/secondary.ll @@ -0,0 +1,24 @@ +; RUN: opt -S -reassociate < %s | FileCheck %s +; rdar://9167457 + +; Reassociate shouldn't break this testcase involving a secondary +; reassociation. + +; CHECK: define +; CHECK-NOT: undef +; CHECK: %factor = mul i32 %tmp3, -2 +; CHECK-NOT: undef +; CHECK: } + +define void @x0f2f640ab6718391b59ce96d9fdeda54(i32 %arg, i32 %arg1, i32 %arg2, i32* %.out) nounwind { +_: + %tmp = sub i32 %arg, %arg1 + %tmp3 = mul i32 %tmp, -1268345047 + %tmp4 = add i32 %tmp3, 2014710503 + %tmp5 = add i32 %tmp3, -1048397418 + %tmp6 = sub i32 %tmp4, %tmp5 + %tmp7 = sub i32 -2014710503, %tmp3 + %tmp8 = add i32 %tmp6, %tmp7 + store i32 %tmp8, i32* %.out + ret void +} diff --git a/test/Transforms/SCCP/apint-basictest.ll b/test/Transforms/SCCP/apint-basictest.ll index c03bfef74301..f6ef1ab3f23b 100644 --- a/test/Transforms/SCCP/apint-basictest.ll +++ b/test/Transforms/SCCP/apint-basictest.ll @@ -1,4 +1,4 @@ -; This is a basic sanity check for constant propogation. The add instruction +; This is a basic sanity check for constant propagation. The add instruction ; should be eliminated. ; RUN: opt < %s -sccp -S | not grep add diff --git a/test/Transforms/SCCP/apint-basictest2.ll b/test/Transforms/SCCP/apint-basictest2.ll index 173482786f20..ad8b4a460cc0 100644 --- a/test/Transforms/SCCP/apint-basictest2.ll +++ b/test/Transforms/SCCP/apint-basictest2.ll @@ -1,4 +1,4 @@ -; This is a basic sanity check for constant propogation. The add instruction +; This is a basic sanity check for constant propagation. The add instruction ; and phi instruction should be eliminated. ; RUN: opt < %s -sccp -S | not grep phi diff --git a/test/Transforms/SCCP/apint-basictest3.ll b/test/Transforms/SCCP/apint-basictest3.ll index 47671bf46b31..b8fcca6fda93 100644 --- a/test/Transforms/SCCP/apint-basictest3.ll +++ b/test/Transforms/SCCP/apint-basictest3.ll @@ -1,4 +1,4 @@ -; This is a basic sanity check for constant propogation. It tests the basic +; This is a basic sanity check for constant propagation. It tests the basic ; arithmatic operations. diff --git a/test/Transforms/SCCP/apint-basictest4.ll b/test/Transforms/SCCP/apint-basictest4.ll index 41036ea002d2..862426020e4f 100644 --- a/test/Transforms/SCCP/apint-basictest4.ll +++ b/test/Transforms/SCCP/apint-basictest4.ll @@ -1,4 +1,4 @@ -; This is a basic sanity check for constant propogation. It tests the basic +; This is a basic sanity check for constant propagation. It tests the basic ; logic operations. diff --git a/test/Transforms/SRETPromotion/2008-03-11-attributes.ll b/test/Transforms/SRETPromotion/2008-03-11-attributes.ll deleted file mode 100644 index 55abec55ed03..000000000000 --- a/test/Transforms/SRETPromotion/2008-03-11-attributes.ll +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: opt < %s -sretpromotion -disable-output - %struct.ObjPoint = type { double, double, double, double, double, double } - -define void @RotatePoint(%struct.ObjPoint* sret %agg.result, %struct.ObjPoint* byval %a, double %rx, double %ry, double %rz) nounwind { -entry: - unreachable -} diff --git a/test/Transforms/SRETPromotion/2008-06-04-function-pointer-passing.ll b/test/Transforms/SRETPromotion/2008-06-04-function-pointer-passing.ll deleted file mode 100644 index 1168b0b2e9d6..000000000000 --- a/test/Transforms/SRETPromotion/2008-06-04-function-pointer-passing.ll +++ /dev/null @@ -1,24 +0,0 @@ -; This test lures sretpromotion into promoting the sret argument of foo, even -; when the function is used as an argument to bar. It used to not check for -; this, assuming that all users of foo were direct calls, resulting in an -; assertion failure later on. - -; We're mainly testing for opt not to crash, but we'll check to see if the sret -; attribute is still there for good measure. -; RUN: opt < %s -sretpromotion -S | grep sret - -%struct.S = type <{ i32, i32 }> - -define i32 @main() { -entry: - %tmp = alloca %struct.S ; <%struct.S*> [#uses=1] - call void @bar( %struct.S* sret %tmp, void (%struct.S*, ...)* @foo ) - ret i32 undef -} - -declare void @bar(%struct.S* sret , void (%struct.S*, ...)*) - -define internal void @foo(%struct.S* sret %agg.result, ...) { -entry: - ret void -} diff --git a/test/Transforms/SRETPromotion/2008-06-05-non-call-use.ll b/test/Transforms/SRETPromotion/2008-06-05-non-call-use.ll deleted file mode 100644 index 26c6a6e5077b..000000000000 --- a/test/Transforms/SRETPromotion/2008-06-05-non-call-use.ll +++ /dev/null @@ -1,20 +0,0 @@ -; This test shows an sret function that is used as an operand to a bitcast. -; StructRetPromotion used to assume that a function was only used by call or -; invoke instructions, making this code cause an assertion failure. - -; We're mainly testing for opt not to crash, but we'll check to see if the sret -; attribute is still there for good measure. -; RUN: opt < %s -sretpromotion -S | grep sret - -%struct.S = type <{ i32, i32 }> - -define i32 @main() { -entry: - %bar = bitcast void (%struct.S*)* @foo to i32 ()* - ret i32 undef -} - -define internal void @foo(%struct.S* sret) { -entry: - ret void -} diff --git a/test/Transforms/SRETPromotion/basictest.ll b/test/Transforms/SRETPromotion/basictest.ll deleted file mode 100644 index ff047dc41eba..000000000000 --- a/test/Transforms/SRETPromotion/basictest.ll +++ /dev/null @@ -1,33 +0,0 @@ -; RUN: opt < %s -sretpromotion -S > %t -; RUN: cat %t | grep sret | count 1 - -; This function is promotable -define internal void @promotable({i32, i32}* sret %s) { - %A = getelementptr {i32, i32}* %s, i32 0, i32 0 - store i32 0, i32* %A - %B = getelementptr {i32, i32}* %s, i32 0, i32 0 - store i32 1, i32* %B - ret void -} - -; This function is not promotable (due to it's use below) -define internal void @notpromotable({i32, i32}* sret %s) { - %A = getelementptr {i32, i32}* %s, i32 0, i32 0 - store i32 0, i32* %A - %B = getelementptr {i32, i32}* %s, i32 0, i32 0 - store i32 1, i32* %B - ret void -} - -define void @caller({i32, i32}* %t) { - %s = alloca {i32, i32} - call void @promotable({i32, i32}* %s) - %A = getelementptr {i32, i32}* %s, i32 0, i32 0 - %a = load i32* %A - %B = getelementptr {i32, i32}* %s, i32 0, i32 0 - %b = load i32* %B - ; This passes in something that's not an alloca, which makes the argument not - ; promotable - call void @notpromotable({i32, i32}* %t) - ret void -} diff --git a/test/Transforms/SRETPromotion/dg.exp b/test/Transforms/SRETPromotion/dg.exp deleted file mode 100644 index f2005891a59a..000000000000 --- a/test/Transforms/SRETPromotion/dg.exp +++ /dev/null @@ -1,3 +0,0 @@ -load_lib llvm.exp - -RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] diff --git a/test/Transforms/ScalarRepl/2008-01-29-PromoteBug.ll b/test/Transforms/ScalarRepl/2008-01-29-PromoteBug.ll index d799bd77e458..8bc4ff0b3ffc 100644 --- a/test/Transforms/ScalarRepl/2008-01-29-PromoteBug.ll +++ b/test/Transforms/ScalarRepl/2008-01-29-PromoteBug.ll @@ -1,6 +1,6 @@ ; RUN: opt < %s -scalarrepl -instcombine -S | grep {ret i8 17} ; rdar://5707076 -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" target triple = "i386-apple-darwin9.1.0" %struct.T = type <{ i8, [3 x i8] }> diff --git a/test/Transforms/ScalarRepl/2008-06-05-loadstore-agg.ll b/test/Transforms/ScalarRepl/2008-06-05-loadstore-agg.ll index 87a08b7eaaf2..ce70a1b13b81 100644 --- a/test/Transforms/ScalarRepl/2008-06-05-loadstore-agg.ll +++ b/test/Transforms/ScalarRepl/2008-06-05-loadstore-agg.ll @@ -13,7 +13,7 @@ define i32 @foo() { %res2 = insertvalue { i32, i32 } %res1, i32 2, 1 ; <{ i32, i32 }> [#uses=1] ; And store it store { i32, i32 } %res2, { i32, i32 }* %target - ; Actually use %target, so it doesn't get removed alltogether + ; Actually use %target, so it doesn't get removed altogether %ptr = getelementptr { i32, i32 }* %target, i32 0, i32 0 %val = load i32* %ptr ret i32 %val @@ -26,7 +26,7 @@ define i32 @bar() { %res2 = insertvalue [ 2 x i32 ] %res1, i32 2, 1 ; <{ i32, i32 }> [#uses=1] ; And store it store [ 2 x i32 ] %res2, [ 2 x i32 ]* %target - ; Actually use %target, so it doesn't get removed alltogether + ; Actually use %target, so it doesn't get removed altogether %ptr = getelementptr [ 2 x i32 ]* %target, i32 0, i32 0 %val = load i32* %ptr ret i32 %val diff --git a/test/Transforms/ScalarRepl/dg.exp b/test/Transforms/ScalarRepl/dg.exp index f2005891a59a..39954d8a498d 100644 --- a/test/Transforms/ScalarRepl/dg.exp +++ b/test/Transforms/ScalarRepl/dg.exp @@ -1,3 +1,3 @@ load_lib llvm.exp -RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] +RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll}]] diff --git a/test/Transforms/ScalarRepl/inline-vector.ll b/test/Transforms/ScalarRepl/inline-vector.ll new file mode 100644 index 000000000000..2f51cc7cf59c --- /dev/null +++ b/test/Transforms/ScalarRepl/inline-vector.ll @@ -0,0 +1,53 @@ +; RUN: opt < %s -scalarrepl -S | FileCheck %s +; RUN: opt < %s -scalarrepl-ssa -S | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10.0.0" + +%struct.Vector4 = type { float, float, float, float } +@f.vector = internal constant %struct.Vector4 { float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00 }, align 16 + +; CHECK: define void @f +; CHECK-NOT: alloca +; CHECK: phi <4 x float> + +define void @f() nounwind ssp { +entry: + %i = alloca i32, align 4 + %vector = alloca %struct.Vector4, align 16 + %agg.tmp = alloca %struct.Vector4, align 16 + %tmp = bitcast %struct.Vector4* %vector to i8* + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp, i8* bitcast (%struct.Vector4* @f.vector to i8*), i32 16, i32 16, i1 false) + br label %for.cond + +for.cond: ; preds = %for.body, %entry + %storemerge = phi i32 [ 0, %entry ], [ %inc, %for.body ] + store i32 %storemerge, i32* %i, align 4 + %cmp = icmp slt i32 %storemerge, 1000000 + br i1 %cmp, label %for.body, label %for.end + +for.body: ; preds = %for.cond + %tmp2 = bitcast %struct.Vector4* %agg.tmp to i8* + %tmp3 = bitcast %struct.Vector4* %vector to i8* + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp2, i8* %tmp3, i32 16, i32 16, i1 false) + %0 = bitcast %struct.Vector4* %agg.tmp to [2 x i64]* + %1 = load [2 x i64]* %0, align 16 + %tmp2.i = extractvalue [2 x i64] %1, 0 + %tmp3.i = zext i64 %tmp2.i to i128 + %tmp10.i = bitcast i128 %tmp3.i to <4 x float> + %sub.i.i = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %tmp10.i + %2 = bitcast %struct.Vector4* %vector to <4 x float>* + store <4 x float> %sub.i.i, <4 x float>* %2, align 16 + %tmp4 = load i32* %i, align 4 + %inc = add nsw i32 %tmp4, 1 + br label %for.cond + +for.end: ; preds = %for.cond + %x = getelementptr inbounds %struct.Vector4* %vector, i32 0, i32 0 + %tmp5 = load float* %x, align 16 + %conv = fpext float %tmp5 to double + %call = call i32 (...)* @printf(double %conv) nounwind + ret void +} + +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind +declare i32 @printf(...) diff --git a/test/Transforms/ScalarRepl/only-memcpy-uses.ll b/test/Transforms/ScalarRepl/only-memcpy-uses.ll new file mode 100644 index 000000000000..cfb88bd80d60 --- /dev/null +++ b/test/Transforms/ScalarRepl/only-memcpy-uses.ll @@ -0,0 +1,27 @@ +; RUN: opt < %s -scalarrepl -S | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +%struct.S = type { [12 x i32] } + +; CHECK: @bar4 +define void @bar4(%struct.S* byval %s) nounwind ssp { +entry: +; CHECK: alloca +; CHECK-NOT: load +; CHECK: memcpy + %t = alloca %struct.S, align 4 + %agg.tmp = alloca %struct.S, align 4 + %tmp = bitcast %struct.S* %t to i8* + %tmp1 = bitcast %struct.S* %s to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp, i8* %tmp1, i64 48, i32 4, i1 false) + %tmp2 = bitcast %struct.S* %agg.tmp to i8* + %tmp3 = bitcast %struct.S* %t to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp2, i8* %tmp3, i64 48, i32 4, i1 false) + %call = call i32 (...)* @bazz(%struct.S* byval %agg.tmp) + ret void +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind + +declare i32 @bazz(...) diff --git a/test/Transforms/ScalarRepl/union-pointer.ll b/test/Transforms/ScalarRepl/union-pointer.ll index fe702fa21772..ea4ec14e5621 100644 --- a/test/Transforms/ScalarRepl/union-pointer.ll +++ b/test/Transforms/ScalarRepl/union-pointer.ll @@ -3,7 +3,7 @@ ; RUN: not grep alloca ; RUN: opt < %s -scalarrepl -S | grep {ret i8} -target datalayout = "e-p:32:32" +target datalayout = "e-p:32:32-n8:16:32" target triple = "i686-apple-darwin8.7.2" %struct.Val = type { i32*, i32 } diff --git a/test/Transforms/ScalarRepl/vector_promote.ll b/test/Transforms/ScalarRepl/vector_promote.ll index 37cb49f539d6..c51ef109c0b2 100644 --- a/test/Transforms/ScalarRepl/vector_promote.ll +++ b/test/Transforms/ScalarRepl/vector_promote.ll @@ -94,7 +94,172 @@ define i64 @test6(<2 x float> %X) { %tmp = load i64* %P ret i64 %tmp ; CHECK: @test6 -; CHECK: bitcast <2 x float> %X to <1 x i64> +; CHECK: bitcast <2 x float> %X to i64 ; CHECK: ret i64 } +define float @test7(<4 x float> %x) { + %a = alloca <4 x float> + store <4 x float> %x, <4 x float>* %a + %p = bitcast <4 x float>* %a to <2 x float>* + %b = load <2 x float>* %p + %q = getelementptr <4 x float>* %a, i32 0, i32 2 + %c = load float* %q + ret float %c +; CHECK: @test7 +; CHECK-NOT: alloca +; CHECK: bitcast <4 x float> %x to <2 x double> +; CHECK-NEXT: extractelement <2 x double> +; CHECK-NEXT: bitcast double %tmp4 to <2 x float> +; CHECK-NEXT: extractelement <4 x float> +} + +define void @test8(<4 x float> %x, <2 x float> %y) { + %a = alloca <4 x float> + store <4 x float> %x, <4 x float>* %a + %p = bitcast <4 x float>* %a to <2 x float>* + store <2 x float> %y, <2 x float>* %p + ret void +; CHECK: @test8 +; CHECK-NOT: alloca +; CHECK: bitcast <4 x float> %x to <2 x double> +; CHECK-NEXT: bitcast <2 x float> %y to double +; CHECK-NEXT: insertelement <2 x double> +; CHECK-NEXT: bitcast <2 x double> %tmp2 to <4 x float> +} + +define i256 @test9(<4 x i256> %x) { + %a = alloca <4 x i256> + store <4 x i256> %x, <4 x i256>* %a + %p = bitcast <4 x i256>* %a to <2 x i256>* + %b = load <2 x i256>* %p + %q = getelementptr <4 x i256>* %a, i32 0, i32 2 + %c = load i256* %q + ret i256 %c +; CHECK: @test9 +; CHECK-NOT: alloca +; CHECK: bitcast <4 x i256> %x to <2 x i512> +; CHECK-NEXT: extractelement <2 x i512> +; CHECK-NEXT: bitcast i512 %tmp4 to <2 x i256> +; CHECK-NEXT: extractelement <4 x i256> +} + +define void @test10(<4 x i256> %x, <2 x i256> %y) { + %a = alloca <4 x i256> + store <4 x i256> %x, <4 x i256>* %a + %p = bitcast <4 x i256>* %a to <2 x i256>* + store <2 x i256> %y, <2 x i256>* %p + ret void +; CHECK: @test10 +; CHECK-NOT: alloca +; CHECK: bitcast <4 x i256> %x to <2 x i512> +; CHECK-NEXT: bitcast <2 x i256> %y to i512 +; CHECK-NEXT: insertelement <2 x i512> +; CHECK-NEXT: bitcast <2 x i512> %tmp2 to <4 x i256> +} + +%union.v = type { <2 x i64> } + +define void @test11(<2 x i64> %x) { + %a = alloca %union.v + %p = getelementptr inbounds %union.v* %a, i32 0, i32 0 + store <2 x i64> %x, <2 x i64>* %p, align 16 + %q = getelementptr inbounds %union.v* %a, i32 0, i32 0 + %r = bitcast <2 x i64>* %q to <4 x float>* + %b = load <4 x float>* %r, align 16 + ret void +; CHECK: @test11 +; CHECK-NOT: alloca +} + +define void @test12() { +entry: + %a = alloca <64 x i8>, align 64 + store <64 x i8> undef, <64 x i8>* %a, align 64 + %p = bitcast <64 x i8>* %a to <16 x i8>* + %0 = load <16 x i8>* %p, align 64 + store <16 x i8> undef, <16 x i8>* %p, align 64 + %q = bitcast <16 x i8>* %p to <64 x i8>* + %1 = load <64 x i8>* %q, align 64 + ret void +; CHECK: @test12 +; CHECK-NOT: alloca +; CHECK: extractelement <4 x i128> +; CHECK: insertelement <4 x i128> +} + +define float @test13(<4 x float> %x, <2 x i32> %y) { + %a = alloca <4 x float> + store <4 x float> %x, <4 x float>* %a + %p = bitcast <4 x float>* %a to <2 x float>* + %b = load <2 x float>* %p + %q = getelementptr <4 x float>* %a, i32 0, i32 2 + %c = load float* %q + %r = bitcast <4 x float>* %a to <2 x i32>* + store <2 x i32> %y, <2 x i32>* %r + ret float %c +; CHECK: @test13 +; CHECK-NOT: alloca +; CHECK: bitcast <4 x float> %x to i128 +} + +define <3 x float> @test14(<3 x float> %x) { +entry: + %x.addr = alloca <3 x float>, align 16 + %r = alloca <3 x i32>, align 16 + %extractVec = shufflevector <3 x float> %x, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> + %storetmp = bitcast <3 x float>* %x.addr to <4 x float>* + store <4 x float> %extractVec, <4 x float>* %storetmp, align 16 + %tmp = load <3 x float>* %x.addr, align 16 + %cmp = fcmp une <3 x float> %tmp, zeroinitializer + %sext = sext <3 x i1> %cmp to <3 x i32> + %and = and <3 x i32> <i32 1065353216, i32 1065353216, i32 1065353216>, %sext + %extractVec1 = shufflevector <3 x i32> %and, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> + %storetmp2 = bitcast <3 x i32>* %r to <4 x i32>* + store <4 x i32> %extractVec1, <4 x i32>* %storetmp2, align 16 + %tmp3 = load <3 x i32>* %r, align 16 + %0 = bitcast <3 x i32> %tmp3 to <3 x float> + %tmp4 = load <3 x float>* %x.addr, align 16 + ret <3 x float> %tmp4 +; CHECK: @test14 +; CHECK-NOT: alloca +; CHECK: shufflevector <4 x i32> %extractVec1, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2> +} + +define void @test15(<3 x i64>* sret %agg.result, <3 x i64> %x, <3 x i64> %min) { +entry: + %x.addr = alloca <3 x i64>, align 32 + %min.addr = alloca <3 x i64>, align 32 + %extractVec = shufflevector <3 x i64> %x, <3 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> + %storetmp = bitcast <3 x i64>* %x.addr to <4 x i64>* + store <4 x i64> %extractVec, <4 x i64>* %storetmp, align 32 + %extractVec1 = shufflevector <3 x i64> %min, <3 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> + %storetmp2 = bitcast <3 x i64>* %min.addr to <4 x i64>* + store <4 x i64> %extractVec1, <4 x i64>* %storetmp2, align 32 + %tmp = load <3 x i64>* %x.addr + %tmp5 = extractelement <3 x i64> %tmp, i32 0 + %tmp11 = insertelement <3 x i64> %tmp, i64 %tmp5, i32 0 + store <3 x i64> %tmp11, <3 x i64>* %x.addr + %tmp30 = load <3 x i64>* %x.addr, align 32 + store <3 x i64> %tmp30, <3 x i64>* %agg.result + ret void +; CHECK: @test15 +; CHECK-NOT: alloca +; CHECK: shufflevector <4 x i64> %tmpV2, <4 x i64> undef, <3 x i32> <i32 0, i32 1, i32 2> +} + +define <4 x float> @test16(<4 x float> %x, i64 %y0, i64 %y1) { +entry: + %tmp8 = bitcast <4 x float> undef to <2 x double> + %tmp9 = bitcast i64 %y0 to double + %tmp10 = insertelement <2 x double> %tmp8, double %tmp9, i32 0 + %tmp11 = bitcast <2 x double> %tmp10 to <4 x float> + %tmp3 = bitcast <4 x float> %tmp11 to <2 x double> + %tmp4 = bitcast i64 %y1 to double + %tmp5 = insertelement <2 x double> %tmp3, double %tmp4, i32 1 + %tmp6 = bitcast <2 x double> %tmp5 to <4 x float> + ret <4 x float> %tmp6 +; CHECK: @test16 +; CHECK-NOT: alloca +; CHECK: bitcast <4 x float> %tmp11 to <2 x double> +} diff --git a/test/Transforms/SimplifyCFG/2006-08-03-Crash.ll b/test/Transforms/SimplifyCFG/2006-08-03-Crash.ll index 2c84c937ae39..70fbddfe33b4 100644 --- a/test/Transforms/SimplifyCFG/2006-08-03-Crash.ll +++ b/test/Transforms/SimplifyCFG/2006-08-03-Crash.ll @@ -1,7 +1,5 @@ -; RUN: opt < %s -gvn -simplifycfg \ -; RUN: -disable-output +; RUN: opt < %s -gvn -simplifycfg -disable-output ; PR867 -; END. target datalayout = "E-p:32:32" target triple = "powerpc-apple-darwin8" diff --git a/test/Transforms/SimplifyCFG/2008-05-16-PHIBlockMerge.ll b/test/Transforms/SimplifyCFG/2008-05-16-PHIBlockMerge.ll index 59e886b2ddbe..56f43b64f74e 100644 --- a/test/Transforms/SimplifyCFG/2008-05-16-PHIBlockMerge.ll +++ b/test/Transforms/SimplifyCFG/2008-05-16-PHIBlockMerge.ll @@ -1,6 +1,6 @@ ; RUN: opt < %s -simplifycfg -S > %t ; RUN: not grep {^BB.tomerge} %t -; RUN grep {^BB.nomerge} %t | count 2 +; RUN: grep {^BB.nomerge} %t | count 2 ; ModuleID = '<stdin>' declare i1 @foo() diff --git a/test/Transforms/SimplifyCFG/2011-03-08-UnreachableUse.ll b/test/Transforms/SimplifyCFG/2011-03-08-UnreachableUse.ll new file mode 100644 index 000000000000..329774e22429 --- /dev/null +++ b/test/Transforms/SimplifyCFG/2011-03-08-UnreachableUse.ll @@ -0,0 +1,31 @@ +; RUN: opt < %s -simplifycfg -S | FileCheck %s +; PR9420 + +; Note that the crash in PR9420 test is sensitive to the ordering of +; the transformations done by SimplifyCFG, so this test is likely to rot +; quickly. + +define noalias i8* @func_29() nounwind { +; CHECK: entry: +; CHECK-NEXT: unreachable +entry: + br label %for.cond + +for.cond: ; preds = %for.inc38, %entry + %p_34.addr.0 = phi i16 [ 1, %entry ], [ %conv40, %for.inc38 ] + br label %for.cond1 + +for.cond1: ; preds = %for.inc29, %for.cond + %p_32.addr.0 = phi i1 [ true, %for.cond ], [ true, %for.inc29 ] + br i1 %p_32.addr.0, label %for.body8, label %for.inc38 + +for.body8: ; preds = %for.cond1 + unreachable + +for.inc29: ; preds = %for.cond17 + br label %for.cond1 + +for.inc38: ; preds = %for.end32 + %conv40 = add i16 %p_34.addr.0, 1 + br label %for.cond +} diff --git a/test/Transforms/SimplifyCFG/PhiBlockMerge.ll b/test/Transforms/SimplifyCFG/PhiBlockMerge.ll index c28d0bac3759..36b52f52d490 100644 --- a/test/Transforms/SimplifyCFG/PhiBlockMerge.ll +++ b/test/Transforms/SimplifyCFG/PhiBlockMerge.ll @@ -6,6 +6,7 @@ define i32 @test(i1 %a, i1 %b) { ; CHECK: br i1 %a br i1 %a, label %M, label %O +; CHECK: O: O: ; preds = %0 ; CHECK: select i1 %b, i32 0, i32 1 ; CHECK-NOT: phi diff --git a/test/Transforms/SimplifyCFG/PhiEliminate2.ll b/test/Transforms/SimplifyCFG/PhiEliminate2.ll index c0f6781293db..0b3893d520db 100644 --- a/test/Transforms/SimplifyCFG/PhiEliminate2.ll +++ b/test/Transforms/SimplifyCFG/PhiEliminate2.ll @@ -1,14 +1,17 @@ ; RUN: opt < %s -simplifycfg -S | not grep br -define i32 @test(i1 %C, i32 %V1, i32 %V2) { +define i32 @test(i1 %C, i32 %V1, i32 %V2, i16 %V3) { entry: - br i1 %C, label %then, label %Cont + br i1 %C, label %then, label %else then: ; preds = %entry - %V3 = or i32 %V2, %V1 ; <i32> [#uses=1] + %V4 = or i32 %V2, %V1 ; <i32> [#uses=1] br label %Cont -Cont: ; preds = %then, %entry - %V4 = phi i32 [ %V1, %entry ], [ %V3, %then ] ; <i32> [#uses=0] - call i32 @test( i1 false, i32 0, i32 0 ) ; <i32>:0 [#uses=0] +else: ; preds = %entry + %V5 = sext i16 %V3 to i32 ; <i32> [#uses=1] + br label %Cont +Cont: ; preds = %then, %else + %V6 = phi i32 [ %V5, %else ], [ %V4, %then ] ; <i32> [#uses=0] + call i32 @test( i1 false, i32 0, i32 0, i16 0 ) ; <i32>:0 [#uses=0] ret i32 %V1 } diff --git a/test/Transforms/SimplifyCFG/PhiEliminate3.ll b/test/Transforms/SimplifyCFG/PhiEliminate3.ll new file mode 100644 index 000000000000..3566b874c0b7 --- /dev/null +++ b/test/Transforms/SimplifyCFG/PhiEliminate3.ll @@ -0,0 +1,34 @@ +; Test merging of blocks containing complex expressions, +; with various folding thresholds +; +; RUN: opt < %s -simplifycfg -S -phi-node-folding-threshold=1 | grep N: +; RUN: opt < %s -simplifycfg -S -phi-node-folding-threshold=2 | not grep N: +; RUN: opt < %s -simplifycfg -S -phi-node-folding-threshold=2 | grep M: +; RUN: opt < %s -simplifycfg -S -phi-node-folding-threshold=7 | not grep M: +; + +define i32 @test(i1 %a, i1 %b, i32 %i, i32 %j, i32 %k) { +entry: + br i1 %a, label %M, label %O +O: + br i1 %b, label %P, label %Q +P: + %iaj = add i32 %i, %j + %iajak = add i32 %iaj, %k + br label %N +Q: + %ixj = xor i32 %i, %j + %ixjxk = xor i32 %ixj, %k + br label %N +N: + ; This phi should be foldable if threshold >= 2 + %Wp = phi i32 [ %iajak, %P ], [ %ixjxk, %Q ] + %Wp2 = add i32 %Wp, %Wp + br label %M +M: + ; This phi should be foldable if threshold >= 7 + %W = phi i32 [ %Wp2, %N ], [ 2, %entry ] + %R = add i32 %W, 1 + ret i32 %R +} + diff --git a/test/Transforms/SimplifyCFG/UnreachableEliminate.ll b/test/Transforms/SimplifyCFG/UnreachableEliminate.ll index 7133d9875caf..4a692f3622ec 100644 --- a/test/Transforms/SimplifyCFG/UnreachableEliminate.ll +++ b/test/Transforms/SimplifyCFG/UnreachableEliminate.ll @@ -1,33 +1,73 @@ -; RUN: opt < %s -simplifycfg -S | not grep unreachable +; RUN: opt < %s -simplifycfg -S | FileCheck %s define void @test1(i1 %C, i1* %BP) { +; CHECK: @test1 +; CHECK: entry: +; CHECK-NEXT: ret void +entry: br i1 %C, label %T, label %F -T: ; preds = %0 +T: store i1 %C, i1* %BP unreachable -F: ; preds = %0 +F: ret void } define void @test2() { +; CHECK: @test2 +; CHECK: entry: +; CHECK-NEXT: call void @test2() +; CHECK-NEXT: ret void +entry: invoke void @test2( ) to label %N unwind label %U -U: ; preds = %0 +U: unreachable -N: ; preds = %0 +N: ret void } define i32 @test3(i32 %v) { +; CHECK: @test3 +; CHECK: entry: +; CHECK-NEXT: [[CMP:%[A-Za-z0-9]+]] = icmp eq i32 %v, 2 +; CHECK-NEXT: select i1 [[CMP]], i32 2, i32 1 +; CHECK-NEXT: ret +entry: switch i32 %v, label %default [ i32 1, label %U i32 2, label %T ] -default: ; preds = %0 +default: ret i32 1 -U: ; preds = %0 +U: unreachable -T: ; preds = %0 +T: ret i32 2 } +; PR9450 +define i32 @test4(i32 %v) { +; CHECK: entry: +; CHECK-NEXT: switch i32 %v, label %T [ +; CHECK-NEXT: i32 3, label %V +; CHECK-NEXT: i32 2, label %U +; CHECK-NEXT: ] + +entry: + br label %SWITCH +V: + ret i32 7 +SWITCH: + switch i32 %v, label %default [ + i32 1, label %T + i32 2, label %U + i32 3, label %V + ] +default: + unreachable +U: + ret i32 1 +T: + ret i32 2 +} diff --git a/test/Transforms/SimplifyCFG/branch-fold-dbg.ll b/test/Transforms/SimplifyCFG/branch-fold-dbg.ll new file mode 100644 index 000000000000..0897c95a6778 --- /dev/null +++ b/test/Transforms/SimplifyCFG/branch-fold-dbg.ll @@ -0,0 +1,58 @@ +; RUN: opt -simplifycfg -S %s | FileCheck %s + +%0 = type { i32*, i32* } + +@0 = external hidden constant [5 x %0], align 4 + +define void @foo(i32) nounwind ssp { +Entry: + %1 = icmp slt i32 %0, 0, !dbg !5 + br i1 %1, label %BB5, label %BB1, !dbg !5 + +BB1: ; preds = %Entry + %2 = icmp sgt i32 %0, 4, !dbg !5 + br i1 %2, label %BB5, label %BB2, !dbg !5 + +BB2: ; preds = %BB1 + %3 = shl i32 1, %0, !dbg !5 + %4 = and i32 %3, 31, !dbg !5 + %5 = icmp eq i32 %4, 0, !dbg !5 + br i1 %5, label %BB5, label %BB3, !dbg !5 + +;CHECK: icmp eq +;CHECK-NEXT: getelementptr +;CHECK-NEXT: icmp eq + +BB3: ; preds = %BB2 + %6 = getelementptr inbounds [5 x %0]* @0, i32 0, i32 %0, !dbg !6 + call void @llvm.dbg.value(metadata !{%0* %6}, i64 0, metadata !7), !dbg !12 + %7 = icmp eq %0* %6, null, !dbg !13 + br i1 %7, label %BB5, label %BB4, !dbg !13 + +BB4: ; preds = %BB3 + %8 = icmp slt i32 %0, 0, !dbg !5 + ret void, !dbg !14 + +BB5: ; preds = %BB3, %BB2, %BB1, %Entry + ret void, !dbg !14 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.sp = !{!0} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 231, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (i32)* @foo, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"a.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"a.i", metadata !"/private/tmp", metadata !"clang (trunk 129006)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{null} +!5 = metadata !{i32 131, i32 2, metadata !0, null} +!6 = metadata !{i32 134, i32 2, metadata !0, null} +!7 = metadata !{i32 590080, metadata !8, metadata !"bar", metadata !1, i32 232, metadata !9, i32 0} ; [ DW_TAG_auto_variable ] +!8 = metadata !{i32 589835, metadata !0, i32 231, i32 1, metadata !1, i32 3} ; [ DW_TAG_lexical_block ] +!9 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !10} ; [ DW_TAG_pointer_type ] +!10 = metadata !{i32 589862, metadata !2, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !11} ; [ DW_TAG_const_type ] +!11 = metadata !{i32 589860, metadata !2, metadata !"unsigned int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!12 = metadata !{i32 232, i32 40, metadata !8, null} +!13 = metadata !{i32 234, i32 2, metadata !8, null} +!14 = metadata !{i32 274, i32 1, metadata !8, null} diff --git a/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll b/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll new file mode 100644 index 000000000000..03053f037d0a --- /dev/null +++ b/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll @@ -0,0 +1,53 @@ +; RUN: opt -simplifycfg -S < %s | FileCheck %s + +define i32 @foo(i32 %i) nounwind ssp { + call void @llvm.dbg.value(metadata !{i32 %i}, i64 0, metadata !6), !dbg !7 + call void @llvm.dbg.value(metadata !8, i64 0, metadata !9), !dbg !11 + %1 = icmp ne i32 %i, 0, !dbg !12 +;CHECK: call i32 (...)* @bar() +;CHECK-NEXT: llvm.dbg.value + br i1 %1, label %2, label %4, !dbg !12 + +; <label>:2 ; preds = %0 + %3 = call i32 (...)* @bar(), !dbg !13 + call void @llvm.dbg.value(metadata !{i32 %3}, i64 0, metadata !9), !dbg !13 + br label %6, !dbg !15 + +; <label>:4 ; preds = %0 + %5 = call i32 (...)* @bar(), !dbg !16 + call void @llvm.dbg.value(metadata !{i32 %5}, i64 0, metadata !9), !dbg !16 + br label %6, !dbg !18 + +; <label>:6 ; preds = %4, %2 + %k.0 = phi i32 [ %3, %2 ], [ %5, %4 ] + ret i32 %k.0, !dbg !19 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +declare i32 @bar(...) + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.sp = !{!0} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 (i32)* @foo} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"b.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"b.c", metadata !"/private/tmp", metadata !"clang", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 590081, metadata !0, metadata !"i", metadata !1, i32 16777218, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!7 = metadata !{i32 2, i32 13, metadata !0, null} +!8 = metadata !{i32 0} +!9 = metadata !{i32 590080, metadata !10, metadata !"k", metadata !1, i32 3, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!10 = metadata !{i32 589835, metadata !0, i32 2, i32 16, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!11 = metadata !{i32 3, i32 12, metadata !10, null} +!12 = metadata !{i32 4, i32 3, metadata !10, null} +!13 = metadata !{i32 5, i32 5, metadata !14, null} +!14 = metadata !{i32 589835, metadata !10, i32 4, i32 10, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] +!15 = metadata !{i32 6, i32 3, metadata !14, null} +!16 = metadata !{i32 7, i32 5, metadata !17, null} +!17 = metadata !{i32 589835, metadata !10, i32 6, i32 10, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] +!18 = metadata !{i32 8, i32 3, metadata !17, null} +!19 = metadata !{i32 9, i32 3, metadata !10, null} diff --git a/test/Transforms/SimplifyCFG/switch-on-const-select.ll b/test/Transforms/SimplifyCFG/switch-on-const-select.ll new file mode 100644 index 000000000000..5494a651d47d --- /dev/null +++ b/test/Transforms/SimplifyCFG/switch-on-const-select.ll @@ -0,0 +1,138 @@ +; RUN: opt < %s -simplifycfg -S | FileCheck %s + +; Test basic folding to a conditional branch. +define i32 @foo(i64 %x, i64 %y) nounwind { +; CHECK: @foo +entry: + %eq = icmp eq i64 %x, %y + br i1 %eq, label %b, label %switch +switch: + %lt = icmp slt i64 %x, %y +; CHECK: br i1 %lt, label %a, label %b + %qux = select i1 %lt, i32 0, i32 2 + switch i32 %qux, label %bees [ + i32 0, label %a + i32 1, label %b + i32 2, label %b + ] +a: + tail call void @bees.a() nounwind + ret i32 1 +; CHECK: b: +; CHECK-NEXT: %retval = phi i32 [ 0, %switch ], [ 2, %entry ] +b: + %retval = phi i32 [0, %switch], [0, %switch], [2, %entry] + tail call void @bees.b() nounwind + ret i32 %retval +; CHECK-NOT: bees: +bees: + tail call void @llvm.trap() nounwind + unreachable +} + +; Test basic folding to an unconditional branch. +define i32 @bar(i64 %x, i64 %y) nounwind { +; CHECK: @bar +entry: +; CHECK-NEXT: entry: +; CHECK-NEXT: tail call void @bees.a() nounwind +; CHECK-NEXT: ret i32 0 + %lt = icmp slt i64 %x, %y + %qux = select i1 %lt, i32 0, i32 2 + switch i32 %qux, label %bees [ + i32 0, label %a + i32 1, label %b + i32 2, label %a + ] +a: + %retval = phi i32 [0, %entry], [0, %entry], [1, %b] + tail call void @bees.a() nounwind + ret i32 0 +b: + tail call void @bees.b() nounwind + br label %a +bees: + tail call void @llvm.trap() nounwind + unreachable +} + +; Test the edge case where both values from the select are the default case. +define void @bazz(i64 %x, i64 %y) nounwind { +; CHECK: @bazz +entry: +; CHECK-NEXT: entry: +; CHECK-NEXT: tail call void @bees.b() nounwind +; CHECK-NEXT: ret void + %lt = icmp slt i64 %x, %y + %qux = select i1 %lt, i32 10, i32 12 + switch i32 %qux, label %b [ + i32 0, label %a + i32 1, label %bees + i32 2, label %bees + ] +a: + tail call void @bees.a() nounwind + ret void +b: + tail call void @bees.b() nounwind + ret void +bees: + tail call void @llvm.trap() + unreachable +} + +; Test the edge case where both values from the select are equal. +define void @quux(i64 %x, i64 %y) nounwind { +; CHECK: @quux +entry: +; CHECK-NEXT: entry: +; CHECK-NEXT: tail call void @bees.a() nounwind +; CHECK-NEXT: ret void + %lt = icmp slt i64 %x, %y + %qux = select i1 %lt, i32 0, i32 0 + switch i32 %qux, label %b [ + i32 0, label %a + i32 1, label %bees + i32 2, label %bees + ] +a: + tail call void @bees.a() nounwind + ret void +b: + tail call void @bees.b() nounwind + ret void +bees: + tail call void @llvm.trap() + unreachable +} + +; A final test, for phi node munging. +define i32 @xyzzy(i64 %x, i64 %y) { +; CHECK: @xyzzy +entry: + %eq = icmp eq i64 %x, %y + br i1 %eq, label %r, label %cont +cont: +; CHECK: %lt = icmp slt i64 %x, %y + %lt = icmp slt i64 %x, %y +; CHECK-NEXT: br i1 %lt, label %a, label %r + %qux = select i1 %lt, i32 0, i32 2 + switch i32 %qux, label %bees [ + i32 0, label %a + i32 1, label %r + i32 2, label %r + ] +r: + %val = phi i32 [0, %entry], [1, %cont], [1, %cont] + ret i32 %val +a: + ret i32 -1 +; CHECK-NOT: bees: +bees: + tail call void @llvm.trap() + unreachable +} + +declare void @llvm.trap() nounwind noreturn +declare void @bees.a() nounwind +declare void @bees.b() nounwind diff --git a/test/Transforms/SimplifyCFG/trap-debugloc.ll b/test/Transforms/SimplifyCFG/trap-debugloc.ll new file mode 100644 index 000000000000..24540e5217b9 --- /dev/null +++ b/test/Transforms/SimplifyCFG/trap-debugloc.ll @@ -0,0 +1,19 @@ +; RUN: opt -S -simplifycfg < %s | FileCheck %s +; Radar 9342286 +; Assign DebugLoc to trap instruction. +define void @foo() nounwind ssp { +; CHECK: call void @llvm.trap(), !dbg + store i32 42, i32* null, !dbg !5 + ret void, !dbg !7 +} + +!llvm.dbg.sp = !{!0} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, void ()* @foo} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"foo.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"foo.c", metadata !"/private/tmp", metadata !"Apple clang version 3.0 (tags/Apple/clang-206.1) (based on LLVM 3.0svn)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{null} +!5 = metadata !{i32 4, i32 2, metadata !6, null} +!6 = metadata !{i32 589835, metadata !0, i32 3, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!7 = metadata !{i32 5, i32 1, metadata !6, null} diff --git a/test/Transforms/SimplifyLibCalls/debug-line.ll b/test/Transforms/SimplifyLibCalls/debug-line.ll new file mode 100644 index 000000000000..b668e4b9d342 --- /dev/null +++ b/test/Transforms/SimplifyLibCalls/debug-line.ll @@ -0,0 +1,24 @@ +; RUN: opt -simplify-libcalls -S < %s | FileCheck %s + + +@.str = private constant [3 x i8] c"%c\00" + +define void @foo() nounwind ssp { +;CHECK: call i32 @putchar{{.+}} !dbg + %1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i32 97), !dbg !5 + ret void, !dbg !7 +} + +declare i32 @printf(i8*, ...) + +!llvm.dbg.sp = !{!0} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, void ()* @foo} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"m.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"m.c", metadata !"/private/tmp", metadata !"clang", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{null} +!5 = metadata !{i32 5, i32 2, metadata !6, null} +!6 = metadata !{i32 589835, metadata !0, i32 4, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!7 = metadata !{i32 6, i32 1, metadata !6, null} + diff --git a/test/Transforms/SimplifyLibCalls/half-powr.ll b/test/Transforms/SimplifyLibCalls/half-powr.ll deleted file mode 100644 index 5d317fe864c6..000000000000 --- a/test/Transforms/SimplifyLibCalls/half-powr.ll +++ /dev/null @@ -1,46 +0,0 @@ -; RUN: opt -simplify-libcalls-halfpowr %s -S | FileCheck %s - -define float @__half_powrf4(float %f, float %g) nounwind readnone { -entry: - %0 = fcmp olt float %f, 2.000000e+00 ; <i1> [#uses=1] - br i1 %0, label %bb, label %bb1 - -bb: ; preds = %entry - %1 = fdiv float %f, 3.000000e+00 ; <float> [#uses=1] - br label %bb1 - -bb1: ; preds = %bb, %entry - %f_addr.0 = phi float [ %1, %bb ], [ %f, %entry ] ; <float> [#uses=1] - %2 = fmul float %f_addr.0, %g ; <float> [#uses=1] -; CHECK: fmul float %f_addr -; CHECK: fmul float %f_addr -; CHECK: fmul float %f_addr -; CHECK: fmul float %f_addr - - ret float %2 -} - -define void @foo(float* %p) nounwind { -entry: - %0 = load float* %p, align 4 ; <float> [#uses=1] - %1 = getelementptr float* %p, i32 1 ; <float*> [#uses=1] - %2 = load float* %1, align 4 ; <float> [#uses=1] - %3 = getelementptr float* %p, i32 2 ; <float*> [#uses=1] - %4 = load float* %3, align 4 ; <float> [#uses=1] - %5 = getelementptr float* %p, i32 3 ; <float*> [#uses=1] - %6 = load float* %5, align 4 ; <float> [#uses=1] - %7 = getelementptr float* %p, i32 4 ; <float*> [#uses=1] - %8 = load float* %7, align 4 ; <float> [#uses=1] - %9 = getelementptr float* %p, i32 5 ; <float*> [#uses=1] - %10 = load float* %9, align 4 ; <float> [#uses=1] - %11 = tail call float @__half_powrf4(float %0, float %6) nounwind ; <float> [#uses=1] - %12 = tail call float @__half_powrf4(float %2, float %8) nounwind ; <float> [#uses=1] - %13 = tail call float @__half_powrf4(float %4, float %10) nounwind ; <float> [#uses=1] - %14 = getelementptr float* %p, i32 6 ; <float*> [#uses=1] - store float %11, float* %14, align 4 - %15 = getelementptr float* %p, i32 7 ; <float*> [#uses=1] - store float %12, float* %15, align 4 - %16 = getelementptr float* %p, i32 8 ; <float*> [#uses=1] - store float %13, float* %16, align 4 - ret void -} diff --git a/test/Transforms/SimplifyLibCalls/iprintf.ll b/test/Transforms/SimplifyLibCalls/iprintf.ll new file mode 100644 index 000000000000..7f036fe3ab8b --- /dev/null +++ b/test/Transforms/SimplifyLibCalls/iprintf.ll @@ -0,0 +1,71 @@ +; RUN: opt < %s -simplify-libcalls -S -o %t +; RUN: FileCheck < %t %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" +target triple = "xcore-xmos-elf" + +@.str = internal constant [4 x i8] c"%f\0A\00" ; <[4 x i8]*> [#uses=1] +@.str1 = internal constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=1] + +; Verify printf with no floating point arguments is transformed to iprintf +define i32 @f0(i32 %x) nounwind { +entry: +; CHECK: define i32 @f0 +; CHECK: @iprintf +; CHECK: } + %0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @.str1, i32 0, i32 0), i32 %x) ; <i32> [#uses=0] + ret i32 %0 +} + +; Verify we don't turn this into an iprintf call +define void @f1(double %x) nounwind { +entry: +; CHECK: define void @f1 +; CHECK: @printf +; CHECK: } + %0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), double %x) nounwind ; <i32> [#uses=0] + ret void +} + +; Verify sprintf with no floating point arguments is transformed to siprintf +define i32 @f2(i8* %p, i32 %x) nounwind { +entry: +; CHECK: define i32 @f2 +; CHECK: @siprintf +; CHECK: } + %0 = tail call i32 (i8*, i8*, ...)* @sprintf(i8 *%p, i8* getelementptr ([4 x i8]* @.str1, i32 0, i32 0), i32 %x) + ret i32 %0 +} + +; Verify we don't turn this into an siprintf call +define i32 @f3(i8* %p, double %x) nounwind { +entry: +; CHECK: define i32 @f3 +; CHECK: @sprintf +; CHECK: } + %0 = tail call i32 (i8*, i8*, ...)* @sprintf(i8 *%p, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), double %x) + ret i32 %0 +} + +; Verify fprintf with no floating point arguments is transformed to fiprintf +define i32 @f4(i8* %p, i32 %x) nounwind { +entry: +; CHECK: define i32 @f4 +; CHECK: @fiprintf +; CHECK: } + %0 = tail call i32 (i8*, i8*, ...)* @fprintf(i8 *%p, i8* getelementptr ([4 x i8]* @.str1, i32 0, i32 0), i32 %x) + ret i32 %0 +} + +; Verify we don't turn this into an fiprintf call +define i32 @f5(i8* %p, double %x) nounwind { +entry: +; CHECK: define i32 @f5 +; CHECK: @fprintf +; CHECK: } + %0 = tail call i32 (i8*, i8*, ...)* @fprintf(i8 *%p, i8* getelementptr ([4 x i8]* @.str, i32 0, i32 0), double %x) + ret i32 %0 +} + +declare i32 @printf(i8* nocapture, ...) nounwind +declare i32 @sprintf(i8* nocapture, i8* nocapture, ...) nounwind +declare i32 @fprintf(i8* nocapture, i8* nocapture, ...) nounwind |