diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2011-05-02 19:34:44 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2011-05-02 19:34:44 +0000 |
| commit | 6b943ff3a3f8617113ecbf611cf0f8957e4e19d2 (patch) | |
| tree | fc5f365fb9035b2d0c622bbf06c9bbe8627d7279 /test/TableGen | |
| parent | d0e4e96dc17a6c1c6de3340842c80f0e187ba349 (diff) | |
| download | src-6b943ff3a3f8617113ecbf611cf0f8957e4e19d2.tar.gz src-6b943ff3a3f8617113ecbf611cf0f8957e4e19d2.zip | |
Vendor import of llvm trunk r130700:vendor/llvm/llvm-r130700
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=221337
svn path=/vendor/llvm/llvm-r130700/; revision=221338; tag=vendor/llvm/llvm-r130700
Diffstat (limited to 'test/TableGen')
| -rw-r--r-- | test/TableGen/TargetInstrInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/TableGen/TargetInstrInfo.td b/test/TableGen/TargetInstrInfo.td index 146ef6fd7682..6c39d5ce57c3 100644 --- a/test/TableGen/TargetInstrInfo.td +++ b/test/TableGen/TargetInstrInfo.td @@ -110,7 +110,7 @@ def SHL32rCL : Inst<(ops R32:$dst, R32:$src), [(set R32:$dst, (shl R32:$src, CL))]>; // The RTL list is a list, allowing complex instructions to be defined easily. -// Temporary 'internal' registers can be used to break instructions appart. +// Temporary 'internal' registers can be used to break instructions apart. let isTwoAddress = 1 in def XOR32mi : Inst<(ops addr:$addr, imm32:$imm), "xor $dst, $src2", 0x81, MRM6m, |