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author | Dimitry Andric <dim@FreeBSD.org> | 2020-07-26 19:36:28 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2020-07-26 19:36:28 +0000 |
commit | cfca06d7963fa0909f90483b42a6d7d194d01e08 (patch) | |
tree | 209fb2a2d68f8f277793fc8df46c753d31bc853b /llvm/lib/Target/X86/X86SchedSkylakeClient.td | |
parent | 706b4fc47bbc608932d3b491ae19a3b9cde9497b (diff) | |
download | src-vendor/llvm-project/master.tar.gz src-vendor/llvm-project/master.zip |
Vendor import of llvm-project master 2e10b7a39b9, the last commit beforevendor/llvm-project/llvmorg-11-init-20887-g2e10b7a39b9vendor/llvm-project/master
the llvmorg-12-init tag, from which release/11.x was branched.
Notes
Notes:
svn path=/vendor/llvm-project/master/; revision=363578
svn path=/vendor/llvm-project/llvmorg-11-init-20887-g2e10b7a39b9/; revision=363579; tag=vendor/llvm-project/llvmorg-11-init-20887-g2e10b7a39b9
Diffstat (limited to 'llvm/lib/Target/X86/X86SchedSkylakeClient.td')
-rw-r--r-- | llvm/lib/Target/X86/X86SchedSkylakeClient.td | 65 |
1 files changed, 33 insertions, 32 deletions
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index 9a511ecc0071..0599564765da 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -255,7 +255,8 @@ defm : SKLWriteResPair<WriteFCmp64X, [SKLPort01], 4, [1], 1, 6>; defm : SKLWriteResPair<WriteFCmp64Y, [SKLPort01], 4, [1], 1, 7>; defm : X86WriteResPairUnsupported<WriteFCmp64Z>; -defm : SKLWriteResPair<WriteFCom, [SKLPort0], 2>; // Floating point compare to flags. +defm : SKLWriteResPair<WriteFCom, [SKLPort0], 2>; // Floating point compare to flags (X87). +defm : SKLWriteResPair<WriteFComX, [SKLPort0], 2>; // Floating point compare to flags (SSE). defm : SKLWriteResPair<WriteFMul, [SKLPort01], 4, [1], 1, 5>; // Floating point multiplication. defm : SKLWriteResPair<WriteFMulX, [SKLPort01], 4, [1], 1, 6>; @@ -342,8 +343,10 @@ defm : X86WriteRes<WriteVecStoreX, [SKLPort237,SKLPort4], 1, [1,1], 2>; defm : X86WriteRes<WriteVecStoreY, [SKLPort237,SKLPort4], 1, [1,1], 2>; defm : X86WriteRes<WriteVecStoreNT, [SKLPort237,SKLPort4], 1, [1,1], 2>; defm : X86WriteRes<WriteVecStoreNTY, [SKLPort237,SKLPort4], 1, [1,1], 2>; -defm : X86WriteRes<WriteVecMaskedStore, [SKLPort237,SKLPort0], 2, [1,1], 2>; -defm : X86WriteRes<WriteVecMaskedStoreY, [SKLPort237,SKLPort0], 2, [1,1], 2>; +defm : X86WriteRes<WriteVecMaskedStore32, [SKLPort237,SKLPort0], 2, [1,1], 2>; +defm : X86WriteRes<WriteVecMaskedStore32Y, [SKLPort237,SKLPort0], 2, [1,1], 2>; +defm : X86WriteRes<WriteVecMaskedStore64, [SKLPort237,SKLPort0], 2, [1,1], 2>; +defm : X86WriteRes<WriteVecMaskedStore64Y, [SKLPort237,SKLPort0], 2, [1,1], 2>; defm : X86WriteRes<WriteVecMove, [SKLPort05], 1, [1], 1>; defm : X86WriteRes<WriteVecMoveX, [SKLPort015], 1, [1], 1>; defm : X86WriteRes<WriteVecMoveY, [SKLPort015], 1, [1], 1>; @@ -361,9 +364,9 @@ defm : X86WriteResPairUnsupported<WriteVecLogicZ>; defm : SKLWriteResPair<WriteVecTest, [SKLPort0,SKLPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions. defm : SKLWriteResPair<WriteVecTestY, [SKLPort0,SKLPort5], 3, [1,1], 2, 7>; defm : X86WriteResPairUnsupported<WriteVecTestZ>; -defm : SKLWriteResPair<WriteVecIMul, [SKLPort0] , 4, [1], 1, 5>; // Vector integer multiply. -defm : SKLWriteResPair<WriteVecIMulX, [SKLPort01], 4, [1], 1, 6>; -defm : SKLWriteResPair<WriteVecIMulY, [SKLPort01], 4, [1], 1, 7>; +defm : SKLWriteResPair<WriteVecIMul, [SKLPort0] , 5, [1], 1, 5>; // Vector integer multiply. +defm : SKLWriteResPair<WriteVecIMulX, [SKLPort01], 5, [1], 1, 6>; +defm : SKLWriteResPair<WriteVecIMulY, [SKLPort01], 5, [1], 1, 7>; defm : X86WriteResPairUnsupported<WriteVecIMulZ>; defm : SKLWriteResPair<WritePMULLD, [SKLPort01], 10, [2], 2, 6>; // Vector PMULLD. defm : SKLWriteResPair<WritePMULLDY, [SKLPort01], 10, [2], 2, 7>; @@ -1012,7 +1015,7 @@ def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKLWriteResGroup72], (instrs FARJMP64)>; +def: InstRW<[SKLWriteResGroup72], (instrs FARJMP64m)>; def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>; def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> { @@ -1193,7 +1196,7 @@ def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237, let ResourceCycles = [1,1,1,1,1]; } def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m")>; -def: InstRW<[SKLWriteResGroup102], (instrs FARCALL64)>; +def: InstRW<[SKLWriteResGroup102], (instrs FARCALL64m)>; def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> { let Latency = 7; @@ -1592,33 +1595,31 @@ def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> { } def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>; -def SKLWriteResGroup196_1 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { - let Latency = 22; - let NumMicroOps = 5; +def SKLWriteResGroupVEX2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { + let Latency = 18; + let NumMicroOps = 5; // 2 uops perform multiple loads let ResourceCycles = [1,2,1,1]; } -def: InstRW<[SKLWriteResGroup196_1], (instrs VGATHERDPSrm, - VGATHERDPDrm, - VGATHERQPDrm, - VGATHERQPSrm, - VPGATHERDDrm, - VPGATHERDQrm, - VPGATHERQDrm, - VPGATHERQQrm)>; +def: InstRW<[SKLWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm, + VGATHERQPDrm, VPGATHERQQrm, + VGATHERQPSrm, VPGATHERQDrm)>; -def SKLWriteResGroup196_2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { - let Latency = 25; - let NumMicroOps = 5; - let ResourceCycles = [1,2,1,1]; +def SKLWriteResGroupVEX4 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { + let Latency = 20; + let NumMicroOps = 5; // 2 uops peform multiple loads + let ResourceCycles = [1,4,1,1]; +} +def: InstRW<[SKLWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm, + VGATHERDPSrm, VPGATHERDDrm, + VGATHERQPDYrm, VPGATHERQQYrm, + VGATHERQPSYrm, VPGATHERQDYrm)>; + +def SKLWriteResGroupVEX8 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { + let Latency = 22; + let NumMicroOps = 5; // 2 uops perform multiple loads + let ResourceCycles = [1,8,1,1]; } -def: InstRW<[SKLWriteResGroup196_2], (instrs VGATHERDPSYrm, - VGATHERQPDYrm, - VGATHERQPSYrm, - VPGATHERDDYrm, - VPGATHERDQYrm, - VPGATHERQDYrm, - VPGATHERQQYrm, - VGATHERDPDYrm)>; +def: InstRW<[SKLWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>; def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { let Latency = 23; @@ -1745,7 +1746,7 @@ def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>; def: InstRW<[WriteZero], (instrs CLC)>; -// Intruction variants handled by the renamer. These might not need execution +// Instruction variants handled by the renamer. These might not need execution // ports in certain conditions. // See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", // section "Skylake Pipeline" > "Register allocation and renaming". |