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author | Dimitry Andric <dim@FreeBSD.org> | 2020-07-26 19:36:28 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2020-07-26 19:36:28 +0000 |
commit | cfca06d7963fa0909f90483b42a6d7d194d01e08 (patch) | |
tree | 209fb2a2d68f8f277793fc8df46c753d31bc853b /llvm/lib/Target/PowerPC/PPC.td | |
parent | 706b4fc47bbc608932d3b491ae19a3b9cde9497b (diff) | |
download | src-vendor/llvm-project/master.tar.gz src-vendor/llvm-project/master.zip |
Vendor import of llvm-project master 2e10b7a39b9, the last commit beforevendor/llvm-project/llvmorg-11-init-20887-g2e10b7a39b9vendor/llvm-project/master
the llvmorg-12-init tag, from which release/11.x was branched.
Notes
Notes:
svn path=/vendor/llvm-project/master/; revision=363578
svn path=/vendor/llvm-project/llvmorg-11-init-20887-g2e10b7a39b9/; revision=363579; tag=vendor/llvm-project/llvmorg-11-init-20887-g2e10b7a39b9
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPC.td')
-rw-r--r-- | llvm/lib/Target/PowerPC/PPC.td | 95 |
1 files changed, 76 insertions, 19 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td index bef0a81ee3ad..9ad78bf67fe6 100644 --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -51,6 +51,7 @@ def DirectivePwr6x def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">; def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">; def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">; +def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">; def DirectivePwrFuture : SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">; @@ -166,6 +167,16 @@ def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true", "Enable Hardware Transactional Memory instructions">; def FeatureMFTB : SubtargetFeature<"", "FeatureMFTB", "true", "Implement mftb using the mfspr instruction">; +def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true", + "Target supports instruction fusion">; +def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load", + "HasAddiLoadFusion", "true", + "Power8 Addi-Load fusion", + [FeatureFusion]>; +def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load", + "HasAddisLoadFusion", "true", + "Power8 Addis-Load fusion", + [FeatureFusion]>; def FeatureUnalignedFloats : SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess", "true", "CPU does not trap on unaligned FP access">; @@ -194,7 +205,11 @@ def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0", "true", - "Enable instructions added in ISA 3.0.">; + "Enable instructions in ISA 3.0.">; +def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1", + "true", + "Enable instructions in ISA 3.1.", + [FeatureISA3_0]>; def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true", "Enable POWER9 Altivec instructions", [FeatureISA3_0, FeatureP8Altivec]>; @@ -202,6 +217,10 @@ def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true", "Enable POWER9 vector instructions", [FeatureISA3_0, FeatureP8Vector, FeatureP9Altivec]>; +def FeatureP10Vector : SubtargetFeature<"power10-vector", "HasP10Vector", + "true", + "Enable POWER10 vector instructions", + [FeatureISA3_1, FeatureP9Vector]>; // A separate feature for this even though it is equivalent to P9Vector // because this is a feature of the implementation rather than the architecture // and may go away with future CPU's. @@ -209,6 +228,21 @@ def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units", "VectorsUseTwoUnits", "true", "Vectors use two units">; +def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs", + "true", + "Enable prefixed instructions", + [FeatureISA3_0, FeatureP8Vector, + FeatureP9Altivec]>; +def FeaturePCRelativeMemops : + SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true", + "Enable PC relative Memory Ops", + [FeatureISA3_0]>; + +def FeaturePredictableSelectIsExpensive : + SubtargetFeature<"predictable-select-expensive", + "PredictableSelectIsExpensive", + "true", + "Prefer likely predicted branches over selects">; // Since new processors generally contain a superset of features of those that // came before them, the idea is to make implementations of new processors @@ -225,7 +259,7 @@ def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units", // !listconcat(FutureProcessorInheritableFeatures, // FutureProcessorSpecificFeatures) -// Makes it explicit and obvious what is new in FutureProcesor vs. Power8 as +// Makes it explicit and obvious what is new in FutureProcessor vs. Power8 as // well as providing a single point of definition if the feature set will be // used elsewhere. def ProcessorFeatures { @@ -262,25 +296,34 @@ def ProcessorFeatures { !listconcat(P7InheritableFeatures, P7SpecificFeatures); // Power8 - list<SubtargetFeature> P8AdditionalFeatures = [DirectivePwr8, - FeatureP8Altivec, - FeatureP8Vector, - FeatureP8Crypto, - FeatureHTM, - FeatureDirectMove, - FeatureICBT, - FeaturePartwordAtomic]; - list<SubtargetFeature> P8SpecificFeatures = []; + list<SubtargetFeature> P8AdditionalFeatures = + [DirectivePwr8, + FeatureP8Altivec, + FeatureP8Vector, + FeatureP8Crypto, + FeatureHTM, + FeatureDirectMove, + FeatureICBT, + FeaturePartwordAtomic, + FeaturePredictableSelectIsExpensive + ]; + + list<SubtargetFeature> P8SpecificFeatures = [FeatureAddiLoadFusion, + FeatureAddisLoadFusion]; list<SubtargetFeature> P8InheritableFeatures = !listconcat(P7InheritableFeatures, P8AdditionalFeatures); list<SubtargetFeature> P8Features = !listconcat(P8InheritableFeatures, P8SpecificFeatures); // Power9 - list<SubtargetFeature> P9AdditionalFeatures = [DirectivePwr9, - FeatureP9Altivec, - FeatureP9Vector, - FeatureISA3_0]; + list<SubtargetFeature> P9AdditionalFeatures = + [DirectivePwr9, + FeatureP9Altivec, + FeatureP9Vector, + FeatureISA3_0, + FeaturePredictableSelectIsExpensive + ]; + // Some features are unique to Power9 and there is no reason to assume // they will be part of any future CPUs. One example is the narrower // dispatch for vector operations than scalar ones. For the time being, @@ -294,13 +337,25 @@ def ProcessorFeatures { list<SubtargetFeature> P9Features = !listconcat(P9InheritableFeatures, P9SpecificFeatures); + // Power10 + // For P10 CPU we assume that all of the existing features from Power9 + // still exist with the exception of those we know are Power9 specific. + list<SubtargetFeature> P10AdditionalFeatures = + [DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs, + FeaturePCRelativeMemops, FeatureP10Vector]; + list<SubtargetFeature> P10SpecificFeatures = []; + list<SubtargetFeature> P10InheritableFeatures = + !listconcat(P9InheritableFeatures, P10AdditionalFeatures); + list<SubtargetFeature> P10Features = + !listconcat(P10InheritableFeatures, P10SpecificFeatures); + // Future - // For future CPU we assume that all of the existing features from Power 9 - // still exist with the exception of those we know are Power 9 specific. + // For future CPU we assume that all of the existing features from Power10 + // still exist with the exception of those we know are Power10 specific. list<SubtargetFeature> FutureAdditionalFeatures = []; list<SubtargetFeature> FutureSpecificFeatures = []; list<SubtargetFeature> FutureInheritableFeatures = - !listconcat(P9InheritableFeatures, FutureAdditionalFeatures); + !listconcat(P10InheritableFeatures, FutureAdditionalFeatures); list<SubtargetFeature> FutureFeatures = !listconcat(FutureInheritableFeatures, FutureSpecificFeatures); } @@ -442,7 +497,7 @@ def : ProcessorModel<"g5", G5Model, def : ProcessorModel<"e500", PPCE500Model, [DirectiveE500, FeatureICBT, FeatureBookE, - FeatureISEL, FeatureMFTB, FeatureSPE]>; + FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>; def : ProcessorModel<"e500mc", PPCE500mcModel, [DirectiveE500mc, FeatureSTFIWX, FeatureICBT, FeatureBookE, @@ -505,6 +560,8 @@ def : ProcessorModel<"pwr6x", G5Model, def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>; def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>; def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>; +// No scheduler model yet. +def : ProcessorModel<"pwr10", NoSchedModel, ProcessorFeatures.P10Features>; // No scheduler model for future CPU. def : ProcessorModel<"future", NoSchedModel, ProcessorFeatures.FutureFeatures>; |