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| author | Dimitry Andric <dim@FreeBSD.org> | 2017-05-08 17:12:57 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-05-08 17:12:57 +0000 |
| commit | c46e6a5940c50058e00c0c5f9123fd82e338d29a (patch) | |
| tree | 89a719d723035c54a190b1f81d329834f1f93336 /lib/Target/Hexagon/HexagonScheduleV55.td | |
| parent | 148779df305667b6942fee7e758fdf81a6498f38 (diff) | |
| download | src-c46e6a5940c50058e00c0c5f9123fd82e338d29a.tar.gz src-c46e6a5940c50058e00c0c5f9123fd82e338d29a.zip | |
Vendor import of llvm trunk r302418:vendor/llvm/llvm-trunk-r302418
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=317948
svn path=/vendor/llvm/llvm-trunk-r302418/; revision=317950; tag=vendor/llvm/llvm-trunk-r302418
Diffstat (limited to 'lib/Target/Hexagon/HexagonScheduleV55.td')
| -rw-r--r-- | lib/Target/Hexagon/HexagonScheduleV55.td | 207 |
1 files changed, 25 insertions, 182 deletions
diff --git a/lib/Target/Hexagon/HexagonScheduleV55.td b/lib/Target/Hexagon/HexagonScheduleV55.td index 06cbcb16abb7..ca738be5d6ef 100644 --- a/lib/Target/Hexagon/HexagonScheduleV55.td +++ b/lib/Target/Hexagon/HexagonScheduleV55.td @@ -1,4 +1,4 @@ -//=-HexagonScheduleV4.td - HexagonV4 Scheduling Definitions --*- tablegen -*-=// +//=-HexagonScheduleV55.td - HexagonV55 Scheduling Definitions -*- tablegen -*=// // // The LLVM Compiler Infrastructure // @@ -7,190 +7,33 @@ // //===----------------------------------------------------------------------===// -// There are four SLOTS (four parallel pipelines) in Hexagon V4 machine. -// This file describes that machine information. -// -// |===========|==================================================| -// | PIPELINE | Instruction Classes | -// |===========|==================================================| -// | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM | -// |-----------|--------------------------------------------------| -// | SLOT1 | LD ST ALU32 | -// |-----------|--------------------------------------------------| -// | SLOT2 | XTYPE ALU32 J JR | -// |-----------|--------------------------------------------------| -// | SLOT3 | XTYPE ALU32 J CR | -// |===========|==================================================| +class HexagonV55PseudoItin { + list<InstrItinData> V55PseudoItin_list = [ + InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], + [1, 1, 1]>, + InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>, + InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>, + InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>, + InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]> + ]; +} -def CJ_tc_1_SLOT23 : InstrItinClass; -def CJ_tc_2early_SLOT23 : InstrItinClass; -def COPROC_VMEM_vtc_long_SLOT01 : InstrItinClass; -def COPROC_VX_vtc_long_SLOT23 : InstrItinClass; -def COPROC_VX_vtc_SLOT23 : InstrItinClass; -def J_tc_3stall_SLOT2 : InstrItinClass; -def MAPPING_tc_1_SLOT0123 : InstrItinClass; -def M_tc_3stall_SLOT23 : InstrItinClass; +def HexagonV55ItinList : DepScalarItinV55, + HexagonV55PseudoItin { + list<InstrItinData> V55Itin_list = [ + InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>], [2, 1]>, + InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>], + [1, 1, 1]> + ]; + list<InstrItinData> ItinList = + !listconcat(V55Itin_list, DepScalarItinV55_list, + V55PseudoItin_list); +} def HexagonItinerariesV55 : - ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [ - // ALU32 - InstrItinData<ALU32_2op_tc_1_SLOT0123 , - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>, - InstrItinData<ALU32_2op_tc_2early_SLOT0123, - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>, - InstrItinData<ALU32_3op_tc_1_SLOT0123 , - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>, - InstrItinData<ALU32_3op_tc_2_SLOT0123 , - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>, - InstrItinData<ALU32_3op_tc_2early_SLOT0123, - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>, - InstrItinData<ALU32_ADDI_tc_1_SLOT0123 , - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>, - - // ALU64 - InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], - [1, 1, 1]>, - InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], - [2, 1, 1]>, - InstrItinData<ALU64_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], - [2, 1, 1]>, - InstrItinData<ALU64_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], - [3, 1, 1]>, - - // CR -> System - InstrItinData<CR_tc_2_SLOT3 , [InstrStage<1, [SLOT3]>], [2, 1, 1]>, - InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<1, [SLOT3]>], [2, 1, 1]>, - InstrItinData<CR_tc_3x_SLOT3 , [InstrStage<1, [SLOT3]>], [3, 1, 1]>, - - // Jump (conditional/unconditional/return etc) - InstrItinData<CR_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], - [2, 1, 1, 1]>, - InstrItinData<CR_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], - [3, 1, 1, 1]>, - InstrItinData<CJ_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], - [1, 1, 1, 1]>, - InstrItinData<CJ_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], - [2, 1, 1, 1]>, - InstrItinData<J_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], - [2, 1, 1, 1]>, - InstrItinData<J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, - [InstrStage<1, [SLOT2, SLOT3]>], [2, 1, 1, 1]>, - - // JR - InstrItinData<J_tc_2early_SLOT2 , [InstrStage<1, [SLOT2]>], [2, 1, 1]>, - InstrItinData<J_tc_3stall_SLOT2 , [InstrStage<1, [SLOT2]>], [3, 1, 1]>, - - // Extender - InstrItinData<EXTENDER_tc_1_SLOT0123, - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>, - - // Load - InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], - [2, 1]>, - InstrItinData<LD_tc_ld_pi_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], - [2, 1]>, - InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<1, [SLOT0]>], [2, 1]>, - InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>], [2, 1]>, - - // M - InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], - [1, 1, 1]>, - InstrItinData<M_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], - [2, 1, 1]>, - InstrItinData<M_tc_2_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], - [2, 1, 1]>, - InstrItinData<M_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], - [1, 1, 1]>, - InstrItinData<M_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], - [3, 1, 1]>, - InstrItinData<M_tc_3x_acc_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], - [3, 1, 1, 1]>, - InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], - [3, 1, 1]>, - InstrItinData<M_tc_3or4x_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], - [3, 1, 1]>, - InstrItinData<M_tc_3stall_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], - [3, 1, 1]>, - - // Store - InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], - [1, 1, 1]>, - InstrItinData<ST_tc_st_pi_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>], - [1, 1, 1]>, - InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<1, [SLOT0]>], [2, 1, 1]>, - InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>], [2, 1, 1]>, - InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>], [1, 1, 1]>, - InstrItinData<ST_tc_st_pi_SLOT0 , [InstrStage<1, [SLOT0]>], [1, 1, 1]>, - - // S - InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], - [1, 1, 1]>, - InstrItinData<S_2op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], - [2, 1, 1]>, - InstrItinData<S_2op_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], - [2, 1, 1]>, - InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], - [3, 1, 1]>, - InstrItinData<S_3op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], - [1, 1, 1]>, - InstrItinData<S_3op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], - [2, 1, 1]>, - InstrItinData<S_3op_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], - [2, 1, 1]>, - InstrItinData<S_3op_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], - [3, 1, 1]>, - InstrItinData<S_3op_tc_3stall_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], - [3, 1, 1]>, - InstrItinData<S_3op_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], - [3, 1, 1]>, - - // New Value Compare Jump - InstrItinData<NCJ_tc_3or4stall_SLOT0, [InstrStage<1, [SLOT0]>], - [3, 1, 1, 1]>, - - // Mem ops - InstrItinData<V2LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>], - [1, 1, 1, 1]>, - InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], - [2, 1, 1, 1]>, - InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], - [1, 1, 1, 1]>, - InstrItinData<V4LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>], - [1, 1, 1, 1]>, - InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], - [3, 1, 1, 1]>, - InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], - [1, 1, 1, 1]>, - - // Endloop - InstrItinData<J_tc_2early_SLOT0123, [InstrStage<1, [SLOT_ENDLOOP]>], - [2]>, - - // Vector - InstrItinData<COPROC_VMEM_vtc_long_SLOT01, - [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 1]>, - InstrItinData<COPROC_VX_vtc_long_SLOT23 , - [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1, 1]>, - InstrItinData<COPROC_VX_vtc_SLOT23 , - [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1, 1]>, - InstrItinData<MAPPING_tc_1_SLOT0123 , - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], - [1, 1, 1, 1]>, - - // Misc - InstrItinData<COMPOUND_CJ_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>], - [1, 1, 1]>, - InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>], - [1, 1, 1]>, - InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>], [1, 1, 1]>, - InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], - [1, 1, 1]>, - InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], - [1, 1, 1]>, - InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>, - InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]> - ]>; + ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], + [Hex_FWD], HexagonV55ItinList.ItinList>; def HexagonModelV55 : SchedMachineModel { // Max issue per cycle == bundle width. @@ -201,5 +44,5 @@ def HexagonModelV55 : SchedMachineModel { } //===----------------------------------------------------------------------===// -// Hexagon V4 Resource Definitions - +// Hexagon V55 Resource Definitions - //===----------------------------------------------------------------------===// |