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| author | Dimitry Andric <dim@FreeBSD.org> | 2016-07-23 20:41:05 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2016-07-23 20:41:05 +0000 |
| commit | 01095a5d43bbfde13731688ddcf6048ebb8b7721 (patch) | |
| tree | 4def12e759965de927d963ac65840d663ef9d1ea /lib/Target/Hexagon/HexagonScheduleV55.td | |
| parent | f0f4822ed4b66e3579e92a89f368f8fb860e218e (diff) | |
| download | src-01095a5d43bbfde13731688ddcf6048ebb8b7721.tar.gz src-01095a5d43bbfde13731688ddcf6048ebb8b7721.zip | |
Vendor import of llvm release_39 branch r276489:vendor/llvm/llvm-release_39-r276489
Notes
Notes:
svn path=/vendor/llvm/dist/; revision=303231
svn path=/vendor/llvm/llvm-release_39-r276489/; revision=303232; tag=vendor/llvm/llvm-release_39-r276489
Diffstat (limited to 'lib/Target/Hexagon/HexagonScheduleV55.td')
| -rw-r--r-- | lib/Target/Hexagon/HexagonScheduleV55.td | 186 |
1 files changed, 105 insertions, 81 deletions
diff --git a/lib/Target/Hexagon/HexagonScheduleV55.td b/lib/Target/Hexagon/HexagonScheduleV55.td index d9ad25d4cd5a..b2a75f7200d7 100644 --- a/lib/Target/Hexagon/HexagonScheduleV55.td +++ b/lib/Target/Hexagon/HexagonScheduleV55.td @@ -31,131 +31,154 @@ def COPROC_VX_vtc_SLOT23 : InstrItinClass; def J_tc_3stall_SLOT2 : InstrItinClass; def MAPPING_tc_1_SLOT0123 : InstrItinClass; def M_tc_3stall_SLOT23 : InstrItinClass; -def SUBINSN_tc_1_SLOT01 : InstrItinClass; -def SUBINSN_tc_2early_SLOT0 : InstrItinClass; -def SUBINSN_tc_2early_SLOT01 : InstrItinClass; -def SUBINSN_tc_3stall_SLOT0 : InstrItinClass; -def SUBINSN_tc_ld_SLOT0 : InstrItinClass; -def SUBINSN_tc_ld_SLOT01 : InstrItinClass; -def SUBINSN_tc_st_SLOT01 : InstrItinClass; def HexagonItinerariesV55 : ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [ // ALU32 InstrItinData<ALU32_2op_tc_1_SLOT0123 , - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>, InstrItinData<ALU32_2op_tc_2early_SLOT0123, - [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>, InstrItinData<ALU32_3op_tc_1_SLOT0123 , - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>, InstrItinData<ALU32_3op_tc_2_SLOT0123 , - [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>, InstrItinData<ALU32_3op_tc_2early_SLOT0123, - [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>, InstrItinData<ALU32_ADDI_tc_1_SLOT0123 , - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>, // ALU64 - InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>, - InstrItinData<ALU64_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>, - InstrItinData<ALU64_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>, + InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [1, 1, 1]>, + InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1]>, + InstrItinData<ALU64_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1]>, + InstrItinData<ALU64_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1]>, // CR -> System - InstrItinData<CR_tc_2_SLOT3 , [InstrStage<2, [SLOT3]>]>, - InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<2, [SLOT3]>]>, - InstrItinData<CR_tc_3x_SLOT3 , [InstrStage<3, [SLOT3]>]>, + InstrItinData<CR_tc_2_SLOT3 , [InstrStage<1, [SLOT3]>], [2, 1, 1]>, + InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<1, [SLOT3]>], [2, 1, 1]>, + InstrItinData<CR_tc_3x_SLOT3 , [InstrStage<1, [SLOT3]>], [3, 1, 1]>, // Jump (conditional/unconditional/return etc) - InstrItinData<CR_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>, - InstrItinData<CR_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>, - InstrItinData<CJ_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData<CJ_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>, - InstrItinData<J_tc_2early_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>, - InstrItinData<J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>, + InstrItinData<CR_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1, 1]>, + InstrItinData<CR_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1, 1]>, + InstrItinData<CJ_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [1, 1, 1, 1]>, + InstrItinData<CJ_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1, 1]>, + InstrItinData<J_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1, 1]>, + InstrItinData<J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT, + [InstrStage<1, [SLOT2, SLOT3]>], [2, 1, 1, 1]>, // JR - InstrItinData<J_tc_2early_SLOT2 , [InstrStage<2, [SLOT2]>]>, - InstrItinData<J_tc_3stall_SLOT2 , [InstrStage<3, [SLOT2]>]>, + InstrItinData<J_tc_2early_SLOT2 , [InstrStage<1, [SLOT2]>], [2, 1, 1]>, + InstrItinData<J_tc_3stall_SLOT2 , [InstrStage<1, [SLOT2]>], [3, 1, 1]>, // Extender InstrItinData<EXTENDER_tc_1_SLOT0123, - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>, // Load - InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>, - InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<3, [SLOT0]>]>, - InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>, + InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], + [2, 1]>, + InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<1, [SLOT0]>], [2, 1]>, + InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>], [2, 1]>, // M - InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData<M_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>, - InstrItinData<M_tc_3_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>, - InstrItinData<M_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>, - InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>, - InstrItinData<M_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>, + InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [1, 1, 1]>, + InstrItinData<M_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1]>, + InstrItinData<M_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [1, 1, 1]>, + InstrItinData<M_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1]>, + InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1]>, + InstrItinData<M_tc_3stall_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1]>, // Store - InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>, - InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>, - InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>, - - // Subinsn - InstrItinData<SUBINSN_tc_2early_SLOT0, [InstrStage<2, [SLOT0]>]>, - InstrItinData<SUBINSN_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>, - InstrItinData<SUBINSN_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>, - InstrItinData<SUBINSN_tc_1_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData<SUBINSN_tc_2early_SLOT01, - [InstrStage<2, [SLOT0, SLOT1]>]>, - InstrItinData<SUBINSN_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>, - InstrItinData<SUBINSN_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], + [1, 1, 1]>, + InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<1, [SLOT0]>], [2, 1, 1]>, + InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>], [2, 1, 1]>, + InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>], [1, 1, 1]>, // S - InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData<S_2op_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>, - InstrItinData<S_2op_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>, - InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>, - InstrItinData<S_3op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData<S_3op_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>, - InstrItinData<S_3op_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>, - InstrItinData<S_3op_tc_3_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>, - InstrItinData<S_3op_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>, - InstrItinData<S_3op_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>, + InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [1, 1, 1]>, + InstrItinData<S_2op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1]>, + InstrItinData<S_2op_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1]>, + InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1]>, + InstrItinData<S_3op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [1, 1, 1]>, + InstrItinData<S_3op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1]>, + InstrItinData<S_3op_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], + [2, 1, 1]>, + InstrItinData<S_3op_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1]>, + InstrItinData<S_3op_tc_3stall_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1]>, + InstrItinData<S_3op_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>], + [3, 1, 1]>, // New Value Compare Jump - InstrItinData<NCJ_tc_3or4stall_SLOT0, [InstrStage<3, [SLOT0]>]>, + InstrItinData<NCJ_tc_3or4stall_SLOT0, [InstrStage<1, [SLOT0]>], + [3, 1, 1, 1]>, // Mem ops - InstrItinData<V2LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>, - InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<2, [SLOT0, SLOT1]>]>, - InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, - InstrItinData<V4LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>, - InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>, - InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>, + InstrItinData<V2LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>], + [1, 1, 1, 1]>, + InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], + [2, 1, 1, 1]>, + InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], + [1, 1, 1, 1]>, + InstrItinData<V4LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>], + [1, 1, 1, 1]>, + InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], + [3, 1, 1, 1]>, + InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>], + [1, 1, 1, 1]>, // Endloop - InstrItinData<J_tc_2early_SLOT0123, [InstrStage<2, [SLOT_ENDLOOP]>]>, + InstrItinData<J_tc_2early_SLOT0123, [InstrStage<1, [SLOT_ENDLOOP]>], + [2]>, // Vector InstrItinData<COPROC_VMEM_vtc_long_SLOT01, - [InstrStage<3, [SLOT0, SLOT1]>]>, + [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 1]>, InstrItinData<COPROC_VX_vtc_long_SLOT23 , - [InstrStage<3, [SLOT2, SLOT3]>]>, + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1, 1]>, InstrItinData<COPROC_VX_vtc_SLOT23 , - [InstrStage<3, [SLOT2, SLOT3]>]>, + [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1, 1]>, InstrItinData<MAPPING_tc_1_SLOT0123 , - [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], + [1, 1, 1, 1]>, // Misc - InstrItinData<COMPOUND_CJ_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>]>, - InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>]>, - InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, - InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>, + InstrItinData<COMPOUND_CJ_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>], + [1, 1, 1]>, + InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>], + [1, 1, 1]>, + InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>], [1, 1, 1]>, + InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], + [1, 1, 1]>, + InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], + [1, 1, 1]>, InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>, - InstrStage<1, [SLOT2, SLOT3]>]> - + InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]> ]>; def HexagonModelV55 : SchedMachineModel { @@ -163,6 +186,7 @@ def HexagonModelV55 : SchedMachineModel { let IssueWidth = 4; let Itineraries = HexagonItinerariesV55; let LoadLatency = 1; + let CompleteModel = 0; } //===----------------------------------------------------------------------===// |