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author | Dimitry Andric <dim@FreeBSD.org> | 2019-03-11 19:15:57 +0000 |
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committer | Dimitry Andric <dim@FreeBSD.org> | 2019-03-11 19:15:57 +0000 |
commit | e6ec44cf36928e182f1e73267c4f5b7ba71cc9e9 (patch) | |
tree | dff5cd711799cb4772af8b31c2c963863c54a9d4 /contrib/llvm/lib/CodeGen | |
parent | 66c4b4f1ce4ae07d4633e978dfec5535e92ee37b (diff) |
Pull in r355854 from upstream llvm trunk (by Jonas Paulsson):
[RegAlloc] Avoid compile time regression with multiple copy hints.
As a fix for https://bugs.llvm.org/show_bug.cgi?id=40986 ("excessive
compile time building opencollada"), this patch makes sure that no
phys reg is hinted more than once from getRegAllocationHints().
This handles the case were many virtual registers are assigned to the
same physreg. The previous compile time fix (r343686) in
weightCalcHelper() only made sure that physical/virtual registers are
passed no more than once to addRegAllocationHint().
Review: Dimitry Andric, Quentin Colombet
https://reviews.llvm.org/D59201
This should fix a hang when compiling certain generated .cpp files in
the graphics/opencollada port.
PR: 236313
MFC after: 1 month
X-MFC-With: r344779
Notes
Notes:
svn path=/head/; revision=345021
Diffstat (limited to 'contrib/llvm/lib/CodeGen')
-rw-r--r-- | contrib/llvm/lib/CodeGen/TargetRegisterInfo.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/contrib/llvm/lib/CodeGen/TargetRegisterInfo.cpp b/contrib/llvm/lib/CodeGen/TargetRegisterInfo.cpp index 661dc18f7a85..d3059280a60f 100644 --- a/contrib/llvm/lib/CodeGen/TargetRegisterInfo.cpp +++ b/contrib/llvm/lib/CodeGen/TargetRegisterInfo.cpp @@ -14,6 +14,7 @@ #include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/BitVector.h" +#include "llvm/ADT/SmallSet.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringExtras.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -398,6 +399,7 @@ TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg, const std::pair<unsigned, SmallVector<unsigned, 4>> &Hints_MRI = MRI.getRegAllocationHints(VirtReg); + SmallSet<unsigned, 32> HintedRegs; // First hint may be a target hint. bool Skip = (Hints_MRI.first != 0); for (auto Reg : Hints_MRI.second) { @@ -411,6 +413,10 @@ TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg, if (VRM && isVirtualRegister(Phys)) Phys = VRM->getPhys(Phys); + // Don't add the same reg twice (Hints_MRI may contain multiple virtual + // registers allocated to the same physreg). + if (!HintedRegs.insert(Phys).second) + continue; // Check that Phys is a valid hint in VirtReg's register class. if (!isPhysicalRegister(Phys)) continue; |