Gcc 3.3.1-pre as of 2003-07-11.

1 files changed, 699 insertions, 508 deletions

diff --git a/contrib/gcc/config/ia64/ia64.md b/contrib/gcc/config/ia64/ia64.md
index 7b11c068f5ce..4d177c21aed7 100644
--- a/contrib/gcc/config/ia64/ia64.md
+++ b/contrib/gcc/config/ia64/ia64.md
@@ -1,5 +1,5 @@
 ;; IA-64 Machine description template
-;; Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
+;; Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
 ;; Contributed by James E. Wilson <wilson@cygnus.com> and
 ;;		  David Mosberger <davidm@hpl.hp.com>.
 
@@ -48,35 +48,43 @@
 
 ;; ??? Need a better way to describe alternate fp status registers.
 
-;; Unspec usage:
-;;
-;; unspec:
-;;	1	gr_spill
-;;	2	gr_restore
-;;	3	fr_spill
-;;	4	fr_restore
-;;	5	recip_approx
-;;	7	pred_rel_mutex
-;;	8	popcnt
-;;	9	pic call
-;;	12	mf
-;;	13	cmpxchg_acq
-;;	19	fetchadd_acq
-;;	20	bsp_value
-;;	21	flushrs
-;;	22      bundle selector
-;;	23      cycle display
-;;      24      addp4
-;;	25	prologue_use
-;;
-;; unspec_volatile:
-;;	0	alloc
-;;	1	blockage
-;;	2	insn_group_barrier
-;;	3	break
-;;	5	set_bsp
-;;	8	pred.safe_across_calls all
-;;	9	pred.safe_across_calls normal
+(define_constants
+  [; Relocations
+   (UNSPEC_LTOFF_DTPMOD		0)
+   (UNSPEC_LTOFF_DTPREL		1)
+   (UNSPEC_DTPREL		2)
+   (UNSPEC_LTOFF_TPREL		3)
+   (UNSPEC_TPREL		4)
+
+   (UNSPEC_LD_BASE		9)
+   (UNSPEC_GR_SPILL		10)
+   (UNSPEC_GR_RESTORE		11)
+   (UNSPEC_FR_SPILL		12)
+   (UNSPEC_FR_RESTORE		13)
+   (UNSPEC_FR_RECIP_APPROX	14)
+   (UNSPEC_PRED_REL_MUTEX	15)
+   (UNSPEC_POPCNT		16)
+   (UNSPEC_PIC_CALL		17)
+   (UNSPEC_MF			18)
+   (UNSPEC_CMPXCHG_ACQ		19)
+   (UNSPEC_FETCHADD_ACQ		20)
+   (UNSPEC_BSP_VALUE		21)
+   (UNSPEC_FLUSHRS		22)
+   (UNSPEC_BUNDLE_SELECTOR	23)
+   (UNSPEC_ADDP4		24)
+   (UNSPEC_PROLOGUE_USE		25)
+  ])
+
+(define_constants
+  [(UNSPECV_ALLOC		0)
+   (UNSPECV_BLOCKAGE		1)
+   (UNSPECV_INSN_GROUP_BARRIER	2)
+   (UNSPECV_BREAK		3)
+   (UNSPECV_SET_BSP		4)
+   (UNSPECV_PSAC_ALL		5)	; pred.safe_across_calls
+   (UNSPECV_PSAC_NORMAL		6)
+   (UNSPECV_SETJMP_RECEIVER	7)
+  ])
 
 ;; ::::::::::::::::::::
 ;; ::
@@ -100,8 +108,12 @@
 ;; multiple instructions, patterns which emit 0 instructions, and patterns
 ;; which emit instruction that can go in any slot (e.g. nop).
 
-(define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld,chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0,syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop_b,nop_f,nop_i,nop_m,nop_x,lfetch"
-         (const_string "unknown"))
+(define_attr "itanium_class" "unknown,ignore,stop_bit,br,fcmp,fcvtfx,fld,
+	fmac,fmisc,frar_i,frar_m,frbr,frfr,frpr,ialu,icmp,ilog,ishf,ld,
+	chk_s,long_i,mmmul,mmshf,mmshfi,rse_m,scall,sem,stf,st,syst_m0,
+	syst_m,tbit,toar_i,toar_m,tobr,tofr,topr,xmpy,xtd,nop_b,nop_f,
+	nop_i,nop_m,nop_x,lfetch"
+  (const_string "unknown"))
 
 ;; chk_s has an I and an M form; use type A for convenience.
 (define_attr "type" "unknown,A,I,M,F,B,L,X,S"
@@ -262,7 +274,7 @@
    && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
   [(set (match_dup 2) (match_dup 4))
    (set (match_dup 3) (match_dup 5))
-   (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))]
+   (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
   "operands[2] = gen_rtx_REG (CCImode, REGNO (operands[0]));
    operands[3] = gen_rtx_REG (CCImode, REGNO (operands[0]) + 1);
    operands[4] = gen_rtx_REG (CCImode, REGNO (operands[1]));
@@ -272,12 +284,12 @@
   [(set (match_operand:QI 0 "general_operand" "")
 	(match_operand:QI 1 "general_operand" ""))]
   ""
-  "
 {
-  if (! reload_in_progress && ! reload_completed
-      && ! ia64_move_ok (operands[0], operands[1]))
-    operands[1] = force_reg (QImode, operands[1]);
-}")
+  rtx op1 = ia64_expand_move (operands[0], operands[1]);
+  if (!op1)
+    DONE;
+  operands[1] = op1;
+})
 
 (define_insn "*movqi_internal"
   [(set (match_operand:QI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
@@ -297,12 +309,12 @@
   [(set (match_operand:HI 0 "general_operand" "")
 	(match_operand:HI 1 "general_operand" ""))]
   ""
-  "
 {
-  if (! reload_in_progress && ! reload_completed
-      && ! ia64_move_ok (operands[0], operands[1]))
-    operands[1] = force_reg (HImode, operands[1]);
-}")
+  rtx op1 = ia64_expand_move (operands[0], operands[1]);
+  if (!op1)
+    DONE;
+  operands[1] = op1;
+})
 
 (define_insn "*movhi_internal"
   [(set (match_operand:HI 0 "destination_operand" "=r,r,r, m, r,*f,*f")
@@ -322,12 +334,35 @@
   [(set (match_operand:SI 0 "general_operand" "")
 	(match_operand:SI 1 "general_operand" ""))]
   ""
-  "
 {
-  if (! reload_in_progress && ! reload_completed
-      && ! ia64_move_ok (operands[0], operands[1]))
-    operands[1] = force_reg (SImode, operands[1]);
-}")
+  rtx op1 = ia64_expand_move (operands[0], operands[1]);
+  if (!op1)
+    DONE;
+  operands[1] = op1;
+})
+
+;; This is used during early compilation to delay the decision on
+;; how to refer to a variable as long as possible.  This is especially
+;; important between initial rtl generation and optimization for
+;; deferred functions, since we may acquire additional information
+;; on the variables used in the meantime.
+
+(define_insn_and_split "movsi_symbolic"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(match_operand:SI 1 "symbolic_operand" "s"))
+   (clobber (match_scratch:DI 2 "=r"))
+   (use (reg:DI 1))]
+  ""
+  "* abort ();"
+  "!no_new_pseudos || reload_completed"
+  [(const_int 0)]
+{
+  rtx scratch = operands[2];
+  if (!reload_completed)
+    scratch = gen_reg_rtx (Pmode);
+  ia64_expand_load_address (operands[0], operands[1], scratch); 
+  DONE;
+})
 
 (define_insn "*movsi_internal"
   [(set (match_operand:SI 0 "destination_operand" "=r,r,r,r, m, r,*f,*f, r,*d")
@@ -344,39 +379,19 @@
   mov %0 = %1
   mov %0 = %1
   mov %0 = %r1"
-;; frar_m, toar_m ??? why not frar_i and toar_i
+  ;; frar_m, toar_m ??? why not frar_i and toar_i
   [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,frar_m,toar_m")])
 
 (define_expand "movdi"
   [(set (match_operand:DI 0 "general_operand" "")
 	(match_operand:DI 1 "general_operand" ""))]
   ""
-  "
 {
-  if (! reload_in_progress && ! reload_completed
-      && ! ia64_move_ok (operands[0], operands[1]))
-    operands[1] = force_reg (DImode, operands[1]);
-  if (! TARGET_NO_PIC && symbolic_operand (operands[1], DImode))
-    {
-      /* Before optimization starts, delay committing to any particular
-	 type of PIC address load.  If this function gets deferred, we
-	 may acquire information that changes the value of the
-	 sdata_symbolic_operand predicate.  */
-      /* But don't delay for function pointers.  Loading a function address
-	 actually loads the address of the descriptor not the function.
-	 If we represent these as SYMBOL_REFs, then they get cse'd with
-	 calls, and we end up with calls to the descriptor address instead of
-	 calls to the function address.  Functions are not candidates for
-	 sdata anyways.  */
-      if (rtx_equal_function_value_matters
-	  && ! (GET_CODE (operands[1]) == SYMBOL_REF
-		&& SYMBOL_REF_FLAG (operands[1])))
-	emit_insn (gen_movdi_symbolic (operands[0], operands[1], gen_reg_rtx (DImode)));
-      else
-        ia64_expand_load_address (operands[0], operands[1], NULL_RTX);
-      DONE;
-    }
-}")
+  rtx op1 = ia64_expand_move (operands[0], operands[1]);
+  if (!op1)
+    DONE;
+  operands[1] = op1;
+})
 
 ;; This is used during early compilation to delay the decision on
 ;; how to refer to a variable as long as possible.  This is especially
@@ -384,19 +399,22 @@
 ;; deferred functions, since we may acquire additional information
 ;; on the variables used in the meantime.
 
-;; ??? This causes us to lose REG_LABEL notes, because the insn splitter
-;; does not attempt to preserve any REG_NOTES on the input instruction.
-
 (define_insn_and_split "movdi_symbolic"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(match_operand:DI 1 "symbolic_operand" "s"))
-   (clobber (match_operand:DI  2 "register_operand" "+r"))
+   (clobber (match_scratch:DI 2 "=r"))
    (use (reg:DI 1))]
   ""
   "* abort ();"
-  ""
+  "!no_new_pseudos || reload_completed"
   [(const_int 0)]
-  "ia64_expand_load_address (operands[0], operands[1], operands[2]); DONE;")
+{
+  rtx scratch = operands[2];
+  if (!reload_completed)
+    scratch = gen_reg_rtx (Pmode);
+  ia64_expand_load_address (operands[0], operands[1], scratch); 
+  DONE;
+})
 
 (define_insn "*movdi_internal"
   [(set (match_operand:DI 0 "destination_operand"
@@ -404,27 +422,26 @@
 	(match_operand:DI 1 "move_operand"
 		    "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
   "ia64_move_ok (operands[0], operands[1])"
-  "*
 {
   static const char * const alt[] = {
-    \"%,mov %0 = %r1\",
-    \"%,addl %0 = %1, r0\",
-    \"%,movl %0 = %1\",
-    \"%,ld8%O1 %0 = %1%P1\",
-    \"%,st8%Q0 %0 = %r1%P0\",
-    \"%,getf.sig %0 = %1\",
-    \"%,setf.sig %0 = %r1\",
-    \"%,mov %0 = %1\",
-    \"%,ldf8 %0 = %1%P1\",
-    \"%,stf8 %0 = %1%P0\",
-    \"%,mov %0 = %1\",
-    \"%,mov %0 = %r1\",
-    \"%,mov %0 = %1\",
-    \"%,mov %0 = %1\",
-    \"%,mov %0 = %1\",
-    \"%,mov %0 = %1\",
-    \"mov %0 = pr\",
-    \"mov pr = %1, -1\"
+    "%,mov %0 = %r1",
+    "%,addl %0 = %1, r0",
+    "%,movl %0 = %1",
+    "%,ld8%O1 %0 = %1%P1",
+    "%,st8%Q0 %0 = %r1%P0",
+    "%,getf.sig %0 = %1",
+    "%,setf.sig %0 = %r1",
+    "%,mov %0 = %1",
+    "%,ldf8 %0 = %1%P1",
+    "%,stf8 %0 = %1%P0",
+    "%,mov %0 = %1",
+    "%,mov %0 = %r1",
+    "%,mov %0 = %1",
+    "%,mov %0 = %1",
+    "%,mov %0 = %1",
+    "%,mov %0 = %1",
+    "mov %0 = pr",
+    "mov pr = %1, -1"
   };
 
   if (which_alternative == 2 && ! TARGET_NO_PIC
@@ -432,7 +449,7 @@
     abort ();
 
   return alt[which_alternative];
-}"
+}
   [(set_attr "itanium_class" "ialu,ialu,long_i,ld,st,frfr,tofr,fmisc,fld,stf,frbr,tobr,frar_i,toar_i,frar_m,toar_m,frpr,topr")])
 
 (define_split
@@ -440,34 +457,32 @@
 	(match_operand:DI 1 "symbolic_operand" ""))]
   "reload_completed && ! TARGET_NO_PIC"
   [(const_int 0)]
-  "
 {
   ia64_expand_load_address (operands[0], operands[1], NULL_RTX);
   DONE;
-}")
+})
 
 (define_expand "load_fptr"
   [(set (match_dup 2)
-	(plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" "")))
+	(plus:DI (reg:DI 1) (match_operand 1 "function_operand" "")))
    (set (match_operand:DI 0 "register_operand" "") (match_dup 3))]
   ""
-  "
 {
   operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
   operands[3] = gen_rtx_MEM (DImode, operands[2]);
   RTX_UNCHANGING_P (operands[3]) = 1;
-}")
+})
 
 (define_insn "*load_fptr_internal1"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" "s")))]
+	(plus:DI (reg:DI 1) (match_operand 1 "function_operand" "s")))]
   ""
   "addl %0 = @ltoff(@fptr(%1)), gp"
   [(set_attr "itanium_class" "ialu")])
 
 (define_insn "load_gprel"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (reg:DI 1) (match_operand:DI 1 "sdata_symbolic_operand" "s")))]
+	(plus:DI (reg:DI 1) (match_operand 1 "sdata_symbolic_operand" "s")))]
   ""
   "addl %0 = @gprel(%1), gp"
   [(set_attr "itanium_class" "ialu")])
@@ -485,29 +500,171 @@
    (set (match_operand:DI 0 "register_operand" "")
 	(plus:DI (match_dup 3) (match_dup 2)))]
   ""
-  "
 {
   operands[2] = no_new_pseudos ? operands[0] : gen_reg_rtx (DImode);
   operands[3] = pic_offset_table_rtx;
-}")
+})
 
 (define_expand "load_symptr"
   [(set (match_operand:DI 2 "register_operand" "")
-	(plus:DI (match_dup 4) (match_operand:DI 1 "got_symbolic_operand" "")))
-   (set (match_operand:DI 0 "register_operand" "") (match_dup 3))]
+	(plus:DI (high:DI (match_operand:DI 1 "got_symbolic_operand" ""))
+		 (match_dup 3)))
+   (set (match_operand:DI 0 "register_operand" "")
+	(lo_sum:DI (match_dup 2) (match_dup 1)))]
   ""
-  "
 {
-  operands[3] = gen_rtx_MEM (DImode, operands[2]);
-  operands[4] = pic_offset_table_rtx;
-  RTX_UNCHANGING_P (operands[3]) = 1;
-}")
+  operands[3] = pic_offset_table_rtx;
+})
+
+(define_insn "*load_symptr_high"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s"))
+		 (match_operand:DI 2 "register_operand" "a")))]
+  ""
+{
+  if (HAVE_AS_LTOFFX_LDXMOV_RELOCS)
+    return "%,addl %0 = @ltoffx(%1), %2";
+  else
+    return "%,addl %0 = @ltoff(%1), %2";
+}
+  [(set_attr "itanium_class" "ialu")])
+
+(define_insn "*load_symptr_low"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
+		   (match_operand 2 "got_symbolic_operand" "s")))]
+  ""
+{
+  if (HAVE_AS_LTOFFX_LDXMOV_RELOCS)
+    return "%,ld8.mov %0 = [%1], %2";
+  else
+    return "%,ld8 %0 = [%1]";
+}
+  [(set_attr "itanium_class" "ld")])
+
+(define_insn "load_ltoff_dtpmod"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(plus:DI (reg:DI 1)
+		 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
+			    UNSPEC_LTOFF_DTPMOD)))]
+  ""
+  "addl %0 = @ltoff(@dtpmod(%1)), gp"
+  [(set_attr "itanium_class" "ialu")])
+
+(define_insn "load_ltoff_dtprel"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(plus:DI (reg:DI 1)
+		 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
+			    UNSPEC_LTOFF_DTPREL)))]
+  ""
+  "addl %0 = @ltoff(@dtprel(%1)), gp"
+  [(set_attr "itanium_class" "ialu")])
+
+(define_expand "load_dtprel"
+  [(set (match_operand:DI 0 "register_operand" "")
+	(unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
+		   UNSPEC_DTPREL))]
+  ""
+  "")
 
-(define_insn "*load_symptr_internal1"
+(define_insn "*load_dtprel64"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (reg:DI 1) (match_operand:DI 1 "got_symbolic_operand" "s")))]
+	(unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
+		   UNSPEC_DTPREL))]
+  "TARGET_TLS64"
+  "movl %0 = @dtprel(%1)"
+  [(set_attr "itanium_class" "long_i")])
+
+(define_insn "*load_dtprel22"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
+		   UNSPEC_DTPREL))]
   ""
-  "addl %0 = @ltoff(%1), gp"
+  "addl %0 = @dtprel(%1), r0"
+  [(set_attr "itanium_class" "ialu")])
+
+(define_expand "add_dtprel"
+  [(set (match_operand:DI 0 "register_operand" "")
+	(plus:DI (match_operand:DI 1 "register_operand" "")
+		 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
+			    UNSPEC_DTPREL)))]
+  "!TARGET_TLS64"
+  "")
+
+(define_insn "*add_dtprel14"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(plus:DI (match_operand:DI 1 "register_operand" "r")
+		 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
+			    UNSPEC_DTPREL)))]
+  "TARGET_TLS14"
+  "adds %0 = @dtprel(%2), %1"
+  [(set_attr "itanium_class" "ialu")])
+
+(define_insn "*add_dtprel22"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(plus:DI (match_operand:DI 1 "register_operand" "a")
+		 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
+			    UNSPEC_DTPREL)))]
+  "TARGET_TLS22"
+  "addl %0 = @dtprel(%2), %1"
+  [(set_attr "itanium_class" "ialu")])
+
+(define_insn "load_ltoff_tprel"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(plus:DI (reg:DI 1)
+		 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
+			    UNSPEC_LTOFF_TPREL)))]
+  ""
+  "addl %0 = @ltoff(@tprel(%1)), gp"
+  [(set_attr "itanium_class" "ialu")])
+
+(define_expand "load_tprel"
+  [(set (match_operand:DI 0 "register_operand" "")
+	(unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
+		   UNSPEC_TPREL))]
+  ""
+  "")
+
+(define_insn "*load_tprel64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
+		   UNSPEC_TPREL))]
+  "TARGET_TLS64"
+  "movl %0 = @tprel(%1)"
+  [(set_attr "itanium_class" "long_i")])
+
+(define_insn "*load_tprel22"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
+		   UNSPEC_TPREL))]
+  ""
+  "addl %0 = @tprel(%1), r0"
+  [(set_attr "itanium_class" "ialu")])
+
+(define_expand "add_tprel"
+  [(set (match_operand:DI 0 "register_operand" "")
+	(plus:DI (match_operand:DI 1 "register_operand" "")
+		 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
+			    UNSPEC_TPREL)))]
+  "!TARGET_TLS64"
+  "")
+
+(define_insn "*add_tprel14"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(plus:DI (match_operand:DI 1 "register_operand" "r")
+		 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
+			    UNSPEC_TPREL)))]
+  "TARGET_TLS14"
+  "adds %0 = @tprel(%2), %1"
+  [(set_attr "itanium_class" "ialu")])
+
+(define_insn "*add_tprel22"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(plus:DI (match_operand:DI 1 "register_operand" "a")
+		 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
+			    UNSPEC_TPREL)))]
+  "TARGET_TLS22"
+  "addl %0 = @tprel(%2), %1"
   [(set_attr "itanium_class" "ialu")])
 
 ;; With no offsettable memory references, we've got to have a scratch
@@ -517,12 +674,12 @@
 		   (match_operand:TI 1 "general_operand" ""))
 	      (clobber (match_scratch:DI 2 ""))])]
   ""
-  "
 {
-  if (! reload_in_progress && ! reload_completed
-      && ! ia64_move_ok (operands[0], operands[1]))
-    operands[1] = force_reg (TImode, operands[1]);
-}")
+  rtx op1 = ia64_expand_move (operands[0], operands[1]);
+  if (!op1)
+    DONE;
+  operands[1] = op1;
+})
 
 (define_insn_and_split "*movti_internal"
   [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
@@ -532,7 +689,6 @@
   "#"
   "reload_completed"
   [(const_int 0)]
-  "
 {
   rtx adj1, adj2, in[2], out[2], insn;
   int first;
@@ -567,7 +723,7 @@
 					  XEXP (XEXP (out[!first], 0), 0),
 					  REG_NOTES (insn));
   DONE;
-}"
+}
   [(set_attr "itanium_class" "unknown")
    (set_attr "predicable" "no")])
 
@@ -581,7 +737,6 @@
   "#"
   "reload_completed"
   [(const_int 0)]
-  "
 {
   rtx in[2], out[2];
   int first;
@@ -600,7 +755,7 @@
   emit_insn (gen_rtx_SET (VOIDmode, out[first], in[first]));
   emit_insn (gen_rtx_SET (VOIDmode, out[!first], in[!first]));
   DONE;
-}"
+}
   [(set_attr "itanium_class" "unknown")
    (set_attr "predicable" "no")])
 
@@ -609,82 +764,80 @@
 		   (match_operand:TI 1 "" "m"))
 	      (clobber (match_operand:TI 2 "register_operand" "=&r"))])]
   ""
-  "
 {
   unsigned int s_regno = REGNO (operands[2]);
   if (s_regno == REGNO (operands[0]))
     s_regno += 1;
   operands[2] = gen_rtx_REG (DImode, s_regno);
-}")
+})
 
 (define_expand "reload_outti"
   [(parallel [(set (match_operand:TI 0 "" "=m")
 		   (match_operand:TI 1 "register_operand" "r"))
 	      (clobber (match_operand:TI 2 "register_operand" "=&r"))])]
   ""
-  "
 {
   unsigned int s_regno = REGNO (operands[2]);
   if (s_regno == REGNO (operands[1]))
     s_regno += 1;
   operands[2] = gen_rtx_REG (DImode, s_regno);
-}")
+})
 
 ;; Floating Point Moves
 ;;
 ;; Note - Patterns for SF mode moves are compulsory, but
-;; patterns for DF are optional, as GCC can synthesise them.
+;; patterns for DF are optional, as GCC can synthesize them.
 
 (define_expand "movsf"
   [(set (match_operand:SF 0 "general_operand" "")
 	(match_operand:SF 1 "general_operand" ""))]
   ""
-  "
 {
-  if (! reload_in_progress && ! reload_completed
-      && ! ia64_move_ok (operands[0], operands[1]))
-    operands[1] = force_reg (SFmode, operands[1]);
-}")
+  rtx op1 = ia64_expand_move (operands[0], operands[1]);
+  if (!op1)
+    DONE;
+  operands[1] = op1;
+})
 
 (define_insn "*movsf_internal"
   [(set (match_operand:SF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
 	(match_operand:SF 1 "general_operand"     "fG,Q,fG,fG,*r,*r, m,*r"))]
   "ia64_move_ok (operands[0], operands[1])"
   "@
-  mov %0 = %F1
-  ldfs %0 = %1%P1
-  stfs %0 = %F1%P0
-  getf.s %0 = %F1
-  setf.s %0 = %1
-  mov %0 = %1
-  ld4%O1 %0 = %1%P1
-  st4%Q0 %0 = %1%P0"
+   mov %0 = %F1
+   ldfs %0 = %1%P1
+   stfs %0 = %F1%P0
+   getf.s %0 = %F1
+   setf.s %0 = %1
+   mov %0 = %1
+   ld4%O1 %0 = %1%P1
+   st4%Q0 %0 = %1%P0"
   [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
 
 (define_expand "movdf"
   [(set (match_operand:DF 0 "general_operand" "")
 	(match_operand:DF 1 "general_operand" ""))]
   ""
-  "
 {
-  if (! reload_in_progress && ! reload_completed
-      && ! ia64_move_ok (operands[0], operands[1]))
-    operands[1] = force_reg (DFmode, operands[1]);
-}")
+  rtx op1 = ia64_expand_move (operands[0], operands[1]);
+  if (!op1)
+    DONE;
+  operands[1] = op1;
+})
 
 (define_insn "*movdf_internal"
   [(set (match_operand:DF 0 "destination_operand" "=f,f, Q,*r, f,*r,*r, m")
 	(match_operand:DF 1 "general_operand"     "fG,Q,fG,fG,*r,*r, m,*r"))]
   "ia64_move_ok (operands[0], operands[1])"
   "@
-  mov %0 = %F1
-  ldfd %0 = %1%P1
-  stfd %0 = %F1%P0
-  getf.d %0 = %F1
-  setf.d %0 = %1
-  mov %0 = %1
-  ld8%O1 %0 = %1%P1
-  st8%Q0 %0 = %1%P0"
+   mov %0 = %F1
+   ldfd %0 = %1%P1
+   stfd %0 = %F1%P0
+   getf.d %0 = %F1
+   setf.d %0 = %1
+   mov %0 = %1
+   ld8%O1 %0 = %1%P1
+   st8%Q0 %0 = %1%P0"
   [(set_attr "itanium_class" "fmisc,fld,stf,frfr,tofr,ialu,ld,st")])
 
 ;; With no offsettable memory references, we've got to have a scratch
@@ -693,7 +846,6 @@
   [(set (match_operand:TF 0 "general_operand" "")
 	(match_operand:TF 1 "general_operand" ""))]
   "INTEL_EXTENDED_IEEE_FORMAT"
-  "
 {
   /* We must support TFmode loads into general registers for stdarg/vararg
      and unprototyped calls.  We split them into DImode loads for convenience.
@@ -754,7 +906,7 @@
       if (! ia64_move_ok (operands[0], operands[1]))
 	operands[1] = force_reg (TFmode, operands[1]);
     }
-}")
+})
 
 ;; ??? There's no easy way to mind volatile acquire/release semantics.
 
@@ -763,9 +915,9 @@
 	(match_operand:TF 1 "general_tfmode_operand"     "fG,m,fG"))]
   "INTEL_EXTENDED_IEEE_FORMAT && ia64_move_ok (operands[0], operands[1])"
   "@
-  mov %0 = %F1
-  ldfe %0 = %1%P1
-  stfe %0 = %F1%P0"
+   mov %0 = %F1
+   ldfe %0 = %1%P1
+   stfe %0 = %F1%P0"
   [(set_attr "itanium_class" "fmisc,fld,stf")])
 
 ;; ::::::::::::::::::::
@@ -902,7 +1054,7 @@
   [(set (match_operand:DF 0 "register_operand" "=f")
         (float:DF (match_operand:DI 1 "register_operand" "f")))]
   "!INTEL_EXTENDED_IEEE_FORMAT"
-  "fcvt.xf %0 = %1\;;;\;fnorm.d %0 = %0"
+  "fcvt.xf %0 = %1\;;;\;%,fnorm.d %0 = %0"
   [(set_attr "itanium_class" "fcvtfx")])
 
 ;; ??? Suboptimal.  This should be split somehow.
@@ -910,7 +1062,7 @@
   [(set (match_operand:SF 0 "register_operand" "=f")
         (float:SF (match_operand:DI 1 "register_operand" "f")))]
   "!INTEL_EXTENDED_IEEE_FORMAT"
-  "fcvt.xf %0 = %1\;;;\;fnorm.s %0 = %0"
+  "fcvt.xf %0 = %1\;;;\;%,fnorm.s %0 = %0"
   [(set_attr "itanium_class" "fcvtfx")])
 
 (define_insn "fix_truncsfdi2"
@@ -1033,7 +1185,6 @@
 			 (match_operand:DI 2 "const_int_operand" ""))
 	(match_operand:DI 3 "nonmemory_operand" ""))]
   ""
-  "
 {
   int width = INTVAL (operands[1]);
   int shift = INTVAL (operands[2]);
@@ -1101,7 +1252,7 @@
       operands[2] = GEN_INT (shift);
 #endif
     }
-}")
+})
 
 (define_insn "*insv_internal"
   [(set (zero_extract:DI (match_operand:DI 0 "gr_register_operand" "+r")
@@ -1113,7 +1264,7 @@
   "dep %0 = %3, %0, %2, %1"
   [(set_attr "itanium_class" "ishf")])
 
-;; Combine doesn't like to create bitfield insertions into zero.
+;; Combine doesn't like to create bit-field insertions into zero.
 (define_insn "*depz_internal"
   [(set (match_operand:DI 0 "gr_register_operand" "=r")
 	(and:DI (ashift:DI (match_operand:DI 1 "gr_register_operand" "r")
@@ -1121,11 +1272,10 @@
 		(match_operand:DI 3 "const_int_operand" "n")))]
   "CONST_OK_FOR_M (INTVAL (operands[2]))
    && ia64_depz_field_mask (operands[3], operands[2]) > 0"
-  "*
 {
   operands[3] = GEN_INT (ia64_depz_field_mask (operands[3], operands[2]));
-  return \"%,dep.z %0 = %1, %2, %3\";
-}"
+  return "%,dep.z %0 = %1, %2, %3";
+}
   [(set_attr "itanium_class" "ishf")])
 
 (define_insn "shift_mix4left"
@@ -1289,7 +1439,7 @@
    (set (match_dup 0) (const_int 1))
    (cond_exec (ne (match_dup 2) (const_int 0))
      (set (match_dup 0) (const_int 0)))
-   (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))]
+   (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
   "operands[3] = gen_rtx_REG (CCImode, REGNO (operands[1]));
    operands[4] = gen_rtx_REG (CCImode, REGNO (operands[2]));")
 
@@ -1305,7 +1455,7 @@
      (set (match_dup 0) (const_int 0)))
    (cond_exec (eq (match_dup 1) (const_int 0))
      (set (match_dup 0) (const_int 1)))
-   (set (match_dup 0) (unspec:BI [(match_dup 0)] 7))]
+   (set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
   "")
 
 (define_insn "*cmpsi_and_0"
@@ -1693,7 +1843,7 @@
    (set (match_operand:CCI 4 "register_operand" "")
 	(match_operand:CCI 5 "register_operand" ""))
    (set (match_operand:BI 6 "register_operand" "")
-	(unspec:BI [(match_dup 6)] 7))]
+	(unspec:BI [(match_dup 6)] UNSPEC_PRED_REL_MUTEX))]
   "REGNO (operands[3]) == REGNO (operands[0])
    && REGNO (operands[4]) == REGNO (operands[0]) + 1
    && REGNO (operands[4]) == REGNO (operands[2]) + 1
@@ -1729,9 +1879,9 @@
 		 (match_operand:SI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
   ""
   "@
-  add %0 = %1, %2
-  adds %0 = %2, %1
-  addl %0 = %2, %1"
+   add %0 = %1, %2
+   adds %0 = %2, %1
+   addl %0 = %2, %1"
   [(set_attr "itanium_class" "ialu")])
 
 (define_insn "*addsi3_plus1"
@@ -1811,10 +1961,7 @@
 			 (neg:SI (match_dup 1))
 			 (match_dup 1)))]
   ""
-  "
-{
-  operands[2] = gen_reg_rtx (BImode);
-}")
+  { operands[2] = gen_reg_rtx (BImode); })
 
 (define_expand "sminsi3"
   [(set (match_dup 3)
@@ -1824,10 +1971,7 @@
 	(if_then_else:SI (ne (match_dup 3) (const_int 0))
 			 (match_dup 2) (match_dup 1)))]
   ""
-  "
-{
-  operands[3] = gen_reg_rtx (BImode);
-}")
+  { operands[3] = gen_reg_rtx (BImode); })
 
 (define_expand "smaxsi3"
   [(set (match_dup 3)
@@ -1837,10 +1981,7 @@
 	(if_then_else:SI (ne (match_dup 3) (const_int 0))
 			 (match_dup 1) (match_dup 2)))]
   ""
-  "
-{
-  operands[3] = gen_reg_rtx (BImode);
-}")
+  { operands[3] = gen_reg_rtx (BImode); })
 
 (define_expand "uminsi3"
   [(set (match_dup 3)
@@ -1850,10 +1991,7 @@
 	(if_then_else:SI (ne (match_dup 3) (const_int 0))
 			 (match_dup 2) (match_dup 1)))]
   ""
-  "
-{
-  operands[3] = gen_reg_rtx (BImode);
-}")
+  { operands[3] = gen_reg_rtx (BImode); })
 
 (define_expand "umaxsi3"
   [(set (match_dup 3)
@@ -1863,19 +2001,16 @@
 	(if_then_else:SI (ne (match_dup 3) (const_int 0))
 			 (match_dup 1) (match_dup 2)))]
   ""
-  "
-{
-  operands[3] = gen_reg_rtx (BImode);
-}")
+  { operands[3] = gen_reg_rtx (BImode); })
 
 (define_expand "divsi3"
   [(set (match_operand:SI 0 "register_operand" "")
 	(div:SI (match_operand:SI 1 "general_operand" "")
 		(match_operand:SI 2 "general_operand" "")))]
-  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
-  "
+  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
 {
   rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
+  REAL_VALUE_TYPE twon34_r;
 
   op0_tf = gen_reg_rtx (TFmode);
   op0_di = gen_reg_rtx (DImode);
@@ -1891,28 +2026,22 @@
   expand_float (op2_tf, operands[2], 0);
 
   /* 2^-34 */
-#if 0
-  twon34 = (CONST_DOUBLE_FROM_REAL_VALUE
-	    (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), TFmode));
+  real_2expN (&twon34_r, -34);
+  twon34 = CONST_DOUBLE_FROM_REAL_VALUE (twon34_r, TFmode);
   twon34 = force_reg (TFmode, twon34);
-#else
-  twon34 = gen_reg_rtx (TFmode);
-  convert_move (twon34, force_const_mem (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), SFmode)), 0);
-#endif
 
   emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34));
 
   emit_insn (gen_fix_trunctfdi2_alts (op0_di, op0_tf, const1_rtx));
   emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
   DONE;
-}")
+})
 
 (define_expand "modsi3"
   [(set (match_operand:SI 0 "register_operand" "")
 	(mod:SI (match_operand:SI 1 "general_operand" "")
 		(match_operand:SI 2 "general_operand" "")))]
-  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
-  "
+  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
 {
   rtx op2_neg, op1_di, div;
 
@@ -1929,16 +2058,16 @@
   emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
 			  gen_lowpart (SImode, op1_di)));
   DONE;
-}")
+})
 
 (define_expand "udivsi3"
   [(set (match_operand:SI 0 "register_operand" "")
 	(udiv:SI (match_operand:SI 1 "general_operand" "")
 		 (match_operand:SI 2 "general_operand" "")))]
-  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
-  "
+  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
 {
   rtx op1_tf, op2_tf, op0_tf, op0_di, twon34;
+  REAL_VALUE_TYPE twon34_r;
 
   op0_tf = gen_reg_rtx (TFmode);
   op0_di = gen_reg_rtx (DImode);
@@ -1954,28 +2083,22 @@
   expand_float (op2_tf, operands[2], 1);
 
   /* 2^-34 */
-#if 0
-  twon34 = (CONST_DOUBLE_FROM_REAL_VALUE
-	    (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), TFmode));
+  real_2expN (&twon34_r, -34);
+  twon34 = CONST_DOUBLE_FROM_REAL_VALUE (twon34_r, TFmode);
   twon34 = force_reg (TFmode, twon34);
-#else
-  twon34 = gen_reg_rtx (TFmode);
-  convert_move (twon34, force_const_mem (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (REAL_VALUE_FROM_TARGET_SINGLE (0x2e800000), SFmode)), 0);
-#endif
 
   emit_insn (gen_divsi3_internal (op0_tf, op1_tf, op2_tf, twon34));
 
   emit_insn (gen_fixuns_trunctfdi2_alts (op0_di, op0_tf, const1_rtx));
   emit_move_insn (operands[0], gen_lowpart (SImode, op0_di));
   DONE;
-}")
+})
 
 (define_expand "umodsi3"
   [(set (match_operand:SI 0 "register_operand" "")
 	(umod:SI (match_operand:SI 1 "general_operand" "")
 		 (match_operand:SI 2 "general_operand" "")))]
-  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
-  "
+  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
 {
   rtx op2_neg, op1_di, div;
 
@@ -1992,7 +2115,7 @@
   emit_insn (gen_maddsi4 (operands[0], div, op2_neg,
 			  gen_lowpart (SImode, op1_di)));
   DONE;
-}")
+})
 
 (define_insn_and_split "divsi3_internal"
   [(set (match_operand:TF 0 "fr_register_operand" "=&f")
@@ -2002,11 +2125,12 @@
    (clobber (match_scratch:TF 5 "=&f"))
    (clobber (match_scratch:BI 6 "=c"))
    (use (match_operand:TF 3 "fr_register_operand" "f"))]
-  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
+  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
-	      (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
+	      (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)]
+					    UNSPEC_FR_RECIP_APPROX))
 	      (use (const_int 1))])
    (cond_exec (ne (match_dup 6) (const_int 0))
      (parallel [(set (match_dup 4) (mult:TF (match_dup 1) (match_dup 0)))
@@ -2047,9 +2171,9 @@
 		 (match_operand:DI 2 "gr_reg_or_22bit_operand" "r,I,J")))]
   ""
   "@
-  add %0 = %1, %2
-  adds %0 = %2, %1
-  addl %0 = %2, %1"
+   add %0 = %1, %2
+   adds %0 = %2, %1
+   addl %0 = %2, %1"
   [(set_attr "itanium_class" "ialu")])
 
 (define_insn "*adddi3_plus1"
@@ -2198,10 +2322,7 @@
 			 (neg:DI (match_dup 1))
 			 (match_dup 1)))]
   ""
-  "
-{
-  operands[2] = gen_reg_rtx (BImode);
-}")
+  { operands[2] = gen_reg_rtx (BImode); })
 
 (define_expand "smindi3"
   [(set (match_dup 3)
@@ -2211,10 +2332,7 @@
 	(if_then_else:DI (ne (match_dup 3) (const_int 0))
 			 (match_dup 2) (match_dup 1)))]
   ""
-  "
-{
-  operands[3] = gen_reg_rtx (BImode);
-}")
+  { operands[3] = gen_reg_rtx (BImode); })
 
 (define_expand "smaxdi3"
   [(set (match_dup 3)
@@ -2224,10 +2342,7 @@
 	(if_then_else:DI (ne (match_dup 3) (const_int 0))
 			 (match_dup 1) (match_dup 2)))]
   ""
-  "
-{
-  operands[3] = gen_reg_rtx (BImode);
-}")
+  { operands[3] = gen_reg_rtx (BImode); })
 
 (define_expand "umindi3"
   [(set (match_dup 3)
@@ -2237,10 +2352,7 @@
 	(if_then_else:DI (ne (match_dup 3) (const_int 0))
 			 (match_dup 2) (match_dup 1)))]
   ""
-  "
-{
-  operands[3] = gen_reg_rtx (BImode);
-}")
+  { operands[3] = gen_reg_rtx (BImode); })
 
 (define_expand "umaxdi3"
   [(set (match_dup 3)
@@ -2250,10 +2362,7 @@
 	(if_then_else:DI (ne (match_dup 3) (const_int 0))
 			 (match_dup 1) (match_dup 2)))]
   ""
-  "
-{
-  operands[3] = gen_reg_rtx (BImode);
-}")
+  { operands[3] = gen_reg_rtx (BImode); })
 
 (define_expand "ffsdi2"
   [(set (match_dup 6)
@@ -2261,23 +2370,23 @@
    (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1)))
    (set (match_dup 5) (const_int 0))
    (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2)))
-   (set (match_dup 4) (unspec:DI [(match_dup 3)] 8))
+   (set (match_dup 4) (unspec:DI [(match_dup 3)] UNSPEC_POPCNT))
    (set (match_operand:DI 0 "gr_register_operand" "")
 	(if_then_else:DI (ne (match_dup 6) (const_int 0))
 			 (match_dup 5) (match_dup 4)))]
   ""
-  "
 {
   operands[2] = gen_reg_rtx (DImode);
   operands[3] = gen_reg_rtx (DImode);
   operands[4] = gen_reg_rtx (DImode);
   operands[5] = gen_reg_rtx (DImode);
   operands[6] = gen_reg_rtx (BImode);
-}")
+})
 
 (define_insn "*popcnt"
   [(set (match_operand:DI 0 "gr_register_operand" "=r")
-	(unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")] 8))]
+	(unspec:DI [(match_operand:DI 1 "gr_register_operand" "r")]
+		   UNSPEC_POPCNT))]
   ""
   "popcnt %0 = %1"
   [(set_attr "itanium_class" "mmmul")])
@@ -2286,8 +2395,7 @@
   [(set (match_operand:DI 0 "register_operand" "")
 	(div:DI (match_operand:DI 1 "general_operand" "")
 		(match_operand:DI 2 "general_operand" "")))]
-  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
-  "
+  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
 {
   rtx op1_tf, op2_tf, op0_tf;
 
@@ -2303,21 +2411,20 @@
   op2_tf = gen_reg_rtx (TFmode);
   expand_float (op2_tf, operands[2], 0);
 
-  if (TARGET_INLINE_DIV_LAT)
+  if (TARGET_INLINE_INT_DIV_LAT)
     emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
   else
     emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
 
   emit_insn (gen_fix_trunctfdi2_alts (operands[0], op0_tf, const1_rtx));
   DONE;
-}")
+})
 
 (define_expand "moddi3"
   [(set (match_operand:DI 0 "register_operand" "")
 	(mod:SI (match_operand:DI 1 "general_operand" "")
 		(match_operand:DI 2 "general_operand" "")))]
-  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
-  "
+  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
 {
   rtx op2_neg, div;
 
@@ -2328,14 +2435,13 @@
 
   emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
   DONE;
-}")
+})
 
 (define_expand "udivdi3"
   [(set (match_operand:DI 0 "register_operand" "")
 	(udiv:DI (match_operand:DI 1 "general_operand" "")
 		 (match_operand:DI 2 "general_operand" "")))]
-  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
-  "
+  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
 {
   rtx op1_tf, op2_tf, op0_tf;
 
@@ -2351,21 +2457,20 @@
   op2_tf = gen_reg_rtx (TFmode);
   expand_float (op2_tf, operands[2], 1);
 
-  if (TARGET_INLINE_DIV_LAT)
+  if (TARGET_INLINE_INT_DIV_LAT)
     emit_insn (gen_divdi3_internal_lat (op0_tf, op1_tf, op2_tf));
   else
     emit_insn (gen_divdi3_internal_thr (op0_tf, op1_tf, op2_tf));
 
   emit_insn (gen_fixuns_trunctfdi2_alts (operands[0], op0_tf, const1_rtx));
   DONE;
-}")
+})
 
 (define_expand "umoddi3"
   [(set (match_operand:DI 0 "register_operand" "")
 	(umod:DI (match_operand:DI 1 "general_operand" "")
 		 (match_operand:DI 2 "general_operand" "")))]
-  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
-  "
+  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV"
 {
   rtx op2_neg, div;
 
@@ -2376,7 +2481,7 @@
 
   emit_insn (gen_madddi4 (operands[0], div, op2_neg, operands[1]));
   DONE;
-}")
+})
 
 (define_insn_and_split "divdi3_internal_lat"
   [(set (match_operand:TF 0 "fr_register_operand" "=&f")
@@ -2386,11 +2491,12 @@
    (clobber (match_scratch:TF 4 "=&f"))
    (clobber (match_scratch:TF 5 "=&f"))
    (clobber (match_scratch:BI 6 "=c"))]
-  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT"
+  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV_LAT"
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
-	      (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
+	      (set (match_dup 6) (unspec:BI [(match_dup 1) (match_dup 2)]
+					    UNSPEC_FR_RECIP_APPROX))
 	      (use (const_int 1))])
    (cond_exec (ne (match_dup 6) (const_int 0))
      (parallel [(set (match_dup 3)
@@ -2444,11 +2550,12 @@
    (clobber (match_scratch:TF 3 "=&f"))
    (clobber (match_scratch:TF 4 "=f"))
    (clobber (match_scratch:BI 5 "=c"))]
-  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR"
+  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_INT_DIV_THR"
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
-	      (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
+	      (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 
+					    UNSPEC_FR_RECIP_APPROX))
 	      (use (const_int 1))])
    (cond_exec (ne (match_dup 5) (const_int 0))
      (parallel [(set (match_dup 3)
@@ -2594,17 +2701,16 @@
   [(set (match_operand:SF 0 "fr_register_operand" "")
 	(div:SF (match_operand:SF 1 "fr_register_operand" "")
 		(match_operand:SF 2 "fr_register_operand" "")))]
-  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
-  "
+  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
 {
   rtx insn;
-  if (TARGET_INLINE_DIV_LAT)
+  if (TARGET_INLINE_FLOAT_DIV_LAT)
     insn = gen_divsf3_internal_lat (operands[0], operands[1], operands[2]);
   else
     insn = gen_divsf3_internal_thr (operands[0], operands[1], operands[2]);
   emit_insn (insn);
   DONE;
-}")
+})
 
 (define_insn_and_split "divsf3_internal_lat"
   [(set (match_operand:SF 0 "fr_register_operand" "=&f")
@@ -2613,11 +2719,12 @@
    (clobber (match_scratch:TF 3 "=&f"))
    (clobber (match_scratch:TF 4 "=f"))
    (clobber (match_scratch:BI 5 "=c"))]
-  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT"
+  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
-	      (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5))
+	      (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
+					    UNSPEC_FR_RECIP_APPROX))
 	      (use (const_int 1))])
    (cond_exec (ne (match_dup 5) (const_int 0))
      (parallel [(set (match_dup 3) (mult:TF (match_dup 7) (match_dup 6)))
@@ -2653,11 +2760,13 @@
      (set (match_dup 0)
 	  (float_truncate:SF (match_dup 6))))
   ] 
-  "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
-   operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
-   operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
-   operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0]));
-   operands[10] = CONST1_RTX (TFmode);"
+{
+  operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
+  operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
+  operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
+  operands[9] = gen_rtx_REG (DFmode, REGNO (operands[0]));
+  operands[10] = CONST1_RTX (TFmode);
+}
   [(set_attr "predicable" "no")])
 
 (define_insn_and_split "divsf3_internal_thr"
@@ -2667,11 +2776,12 @@
    (clobber (match_scratch:TF 3 "=&f"))
    (clobber (match_scratch:TF 4 "=f"))
    (clobber (match_scratch:BI 5 "=c"))]
-  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR"
+  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
-	      (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5))
+	      (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
+					    UNSPEC_FR_RECIP_APPROX))
 	      (use (const_int 1))])
    (cond_exec (ne (match_dup 5) (const_int 0))
      (parallel [(set (match_dup 3)
@@ -2704,11 +2814,13 @@
 	    (plus:TF (mult:TF (match_dup 4) (match_dup 6))
 			      (match_dup 3)))))
   ] 
-  "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
-   operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
-   operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
-   operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3]));
-   operands[10] = CONST1_RTX (TFmode);"
+{
+  operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
+  operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
+  operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
+  operands[9] = gen_rtx_REG (SFmode, REGNO (operands[3]));
+  operands[10] = CONST1_RTX (TFmode);
+}
   [(set_attr "predicable" "no")])
 
 ;; ::::::::::::::::::::
@@ -2898,17 +3010,16 @@
   [(set (match_operand:DF 0 "fr_register_operand" "")
 	(div:DF (match_operand:DF 1 "fr_register_operand" "")
 		(match_operand:DF 2 "fr_register_operand" "")))]
-  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
-  "
+  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
 {
   rtx insn;
-  if (TARGET_INLINE_DIV_LAT)
+  if (TARGET_INLINE_FLOAT_DIV_LAT)
     insn = gen_divdf3_internal_lat (operands[0], operands[1], operands[2]);
   else
     insn = gen_divdf3_internal_thr (operands[0], operands[1], operands[2]);
   emit_insn (insn);
   DONE;
-}")
+})
 
 (define_insn_and_split "divdf3_internal_lat"
   [(set (match_operand:DF 0 "fr_register_operand" "=&f")
@@ -2918,11 +3029,12 @@
    (clobber (match_scratch:TF 4 "=&f"))
    (clobber (match_scratch:TF 5 "=&f"))
    (clobber (match_scratch:BI 6 "=c"))]
-  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT"
+  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 7) (div:TF (const_int 1) (match_dup 9)))
-	      (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)] 5))
+	      (set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)]
+					    UNSPEC_FR_RECIP_APPROX))
 	      (use (const_int 1))])
    (cond_exec (ne (match_dup 6) (const_int 0))
      (parallel [(set (match_dup 3) (mult:TF (match_dup 8) (match_dup 7)))
@@ -2980,12 +3092,14 @@
 	  (float_truncate:DF (plus:TF (mult:TF (match_dup 5) (match_dup 7))
 			      (match_dup 3)))))
   ] 
-  "operands[7] = gen_rtx_REG (TFmode, REGNO (operands[0]));
-   operands[8] = gen_rtx_REG (TFmode, REGNO (operands[1]));
-   operands[9] = gen_rtx_REG (TFmode, REGNO (operands[2]));
-   operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3]));
-   operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5]));
-   operands[12] = CONST1_RTX (TFmode);"
+{
+  operands[7] = gen_rtx_REG (TFmode, REGNO (operands[0]));
+  operands[8] = gen_rtx_REG (TFmode, REGNO (operands[1]));
+  operands[9] = gen_rtx_REG (TFmode, REGNO (operands[2]));
+  operands[10] = gen_rtx_REG (DFmode, REGNO (operands[3]));
+  operands[11] = gen_rtx_REG (DFmode, REGNO (operands[5]));
+  operands[12] = CONST1_RTX (TFmode);
+}
   [(set_attr "predicable" "no")])
 
 (define_insn_and_split "divdf3_internal_thr"
@@ -2995,11 +3109,12 @@
    (clobber (match_scratch:TF 3 "=&f"))
    (clobber (match_scratch:DF 4 "=f"))
    (clobber (match_scratch:BI 5 "=c"))]
-  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR"
+  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 6) (div:TF (const_int 1) (match_dup 8)))
-	      (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)] 5))
+	      (set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
+					    UNSPEC_FR_RECIP_APPROX))
 	      (use (const_int 1))])
    (cond_exec (ne (match_dup 5) (const_int 0))
      (parallel [(set (match_dup 3)
@@ -3044,11 +3159,13 @@
 	  (plus:DF (mult:DF (match_dup 4) (match_dup 0))
 			    (match_dup 9))))
   ] 
-  "operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
-   operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
-   operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
-   operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3]));
-   operands[10] = CONST1_RTX (TFmode);"
+{
+  operands[6] = gen_rtx_REG (TFmode, REGNO (operands[0]));
+  operands[7] = gen_rtx_REG (TFmode, REGNO (operands[1]));
+  operands[8] = gen_rtx_REG (TFmode, REGNO (operands[2]));
+  operands[9] = gen_rtx_REG (DFmode, REGNO (operands[3]));
+  operands[10] = CONST1_RTX (TFmode);
+}
   [(set_attr "predicable" "no")])
 
 ;; ::::::::::::::::::::
@@ -3370,17 +3487,16 @@
   [(set (match_operand:TF 0 "fr_register_operand" "")
 	(div:TF (match_operand:TF 1 "fr_register_operand" "")
 		(match_operand:TF 2 "fr_register_operand" "")))]
-  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV"
-  "
+  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV"
 {
   rtx insn;
-  if (TARGET_INLINE_DIV_LAT)
+  if (TARGET_INLINE_FLOAT_DIV_LAT)
     insn = gen_divtf3_internal_lat (operands[0], operands[1], operands[2]);
   else
     insn = gen_divtf3_internal_thr (operands[0], operands[1], operands[2]);
   emit_insn (insn);
   DONE;
-}")
+})
 
 (define_insn_and_split "divtf3_internal_lat"
   [(set (match_operand:TF 0 "fr_register_operand" "=&f")
@@ -3391,11 +3507,12 @@
    (clobber (match_scratch:TF 5 "=&f"))
    (clobber (match_scratch:TF 6 "=&f"))
    (clobber (match_scratch:BI 7 "=c"))]
-  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_LAT"
+  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_LAT"
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
-	      (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
+	      (set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)]
+					    UNSPEC_FR_RECIP_APPROX))
 	      (use (const_int 1))])
    (cond_exec (ne (match_dup 7) (const_int 0))
      (parallel [(set (match_dup 3)
@@ -3468,11 +3585,12 @@
    (clobber (match_scratch:TF 3 "=&f"))
    (clobber (match_scratch:TF 4 "=&f"))
    (clobber (match_scratch:BI 5 "=c"))]
-  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_DIV_THR"
+  "INTEL_EXTENDED_IEEE_FORMAT && TARGET_INLINE_FLOAT_DIV_THR"
   "#"
   "&& reload_completed"
   [(parallel [(set (match_dup 0) (div:TF (const_int 1) (match_dup 2)))
-	      (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)] 5))
+	      (set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)]
+					    UNSPEC_FR_RECIP_APPROX))
 	      (use (const_int 1))])
    (cond_exec (ne (match_dup 5) (const_int 0))
      (parallel [(set (match_dup 3)
@@ -3546,7 +3664,7 @@
 		(match_operand:TF 3 "fr_register_operand" "f")))
    (set (match_operand:BI 1 "register_operand" "=c")
 	(unspec:BI [(match_operand:TF 2 "fr_register_operand" "f")
-		    (match_dup 3)] 5))
+		    (match_dup 3)] UNSPEC_FR_RECIP_APPROX))
    (use (match_operand:SI 4 "const_int_operand" ""))]
   "INTEL_EXTENDED_IEEE_FORMAT"
   "frcpa.s%4 %0, %1 = %2, %3"
@@ -3564,7 +3682,6 @@
 	(ashift:SI (match_operand:SI 1 "gr_register_operand" "")
 		   (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
   ""
-  "
 {
   if (GET_CODE (operands[2]) != CONST_INT)
     {
@@ -3574,7 +3691,7 @@
       emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
       operands[2] = subshift;
     }
-}")
+})
 
 (define_insn "*ashlsi3_internal"
   [(set (match_operand:SI 0 "gr_register_operand" "=r,r,r")
@@ -3592,7 +3709,6 @@
 	(ashiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
 		     (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
   ""
-  "
 {
   rtx subtarget = gen_reg_rtx (DImode);
   if (GET_CODE (operands[2]) == CONST_INT)
@@ -3607,14 +3723,13 @@
     }
   emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
   DONE;
-}")
+})
 
 (define_expand "lshrsi3"
   [(set (match_operand:SI 0 "gr_register_operand" "")
 	(lshiftrt:SI (match_operand:SI 1 "gr_register_operand" "")
 		     (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
   ""
-  "
 {
   rtx subtarget = gen_reg_rtx (DImode);
   if (GET_CODE (operands[2]) == CONST_INT)
@@ -3629,7 +3744,7 @@
     }
   emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
   DONE;
-}")
+})
 
 ;; Use mix4.r/shr to implement rotrsi3.  We only get 32 bits of valid result
 ;; here, instead of 64 like the patterns above.  Keep the pattern together
@@ -3640,7 +3755,6 @@
 	(rotatert:SI (match_operand:SI 1 "gr_register_operand" "")
 		     (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
   ""
-  "
 {
   if (GET_MODE (operands[2]) != VOIDmode)
     {
@@ -3648,7 +3762,7 @@
       emit_insn (gen_zero_extendsidi2 (tmp, operands[2]));
       operands[2] = tmp;
     }
-}")
+})
 
 (define_insn_and_split "*rotrsi3_internal"
   [(set (match_operand:SI 0 "gr_register_operand" "=&r")
@@ -3669,7 +3783,6 @@
 	(rotate:SI (match_operand:SI 1 "gr_register_operand" "")
 		   (match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
   ""
-  "
 {
   if (! shift_32bit_count_operand (operands[2], SImode))
     {
@@ -3678,7 +3791,7 @@
       emit_insn (gen_rotrsi3 (operands[0], operands[1], tmp));
       DONE;
     }
-}")
+})
 
 (define_insn_and_split "*rotlsi3_internal"
   [(set (match_operand:SI 0 "gr_register_operand" "=r")
@@ -3692,8 +3805,10 @@
 		(ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
    (set (match_dup 3)
 	(lshiftrt:DI (match_dup 3) (match_dup 2)))]
-  "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));
-   operands[2] = GEN_INT (32 - INTVAL (operands[2]));")
+{
+  operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));
+  operands[2] = GEN_INT (32 - INTVAL (operands[2]));
+})
 
 ;; ::::::::::::::::::::
 ;; ::
@@ -3776,11 +3891,10 @@
 	(rotatert:DI (match_operand:DI 1 "gr_register_operand" "")
 		     (match_operand:DI 2 "nonmemory_operand" "")))]
   ""
-  "
 {
   if (! shift_count_operand (operands[2], DImode))
     FAIL;
-}")
+})
 
 (define_insn "*rotrdi3_internal"
   [(set (match_operand:DI 0 "gr_register_operand" "=r")
@@ -3795,11 +3909,10 @@
 	(rotate:DI (match_operand:DI 1 "gr_register_operand" "")
 		   (match_operand:DI 2 "nonmemory_operand" "")))]
   ""
-  "
 {
   if (! shift_count_operand (operands[2], DImode))
     FAIL;
-}")
+})
 
 (define_insn "*rotldi3_internal"
   [(set (match_operand:DI 0 "gr_register_operand" "=r")
@@ -3900,72 +4013,66 @@
         (compare (match_operand:BI 0 "register_operand" "")
   		 (match_operand:BI 1 "const_int_operand" "")))]
   ""
-  "
 {
   ia64_compare_op0 = operands[0];
   ia64_compare_op1 = operands[1];
   DONE;
-}")
+})
 
 (define_expand "cmpsi"
   [(set (cc0)
         (compare (match_operand:SI 0 "gr_register_operand" "")
   		 (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
   ""
-  "
 {
   ia64_compare_op0 = operands[0];
   ia64_compare_op1 = operands[1];
   DONE;
-}")
+})
 
 (define_expand "cmpdi"
   [(set (cc0)
         (compare (match_operand:DI 0 "gr_register_operand" "")
   		 (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
   ""
-  "
 {
   ia64_compare_op0 = operands[0];
   ia64_compare_op1 = operands[1];
   DONE;
-}")
+})
 
 (define_expand "cmpsf"
   [(set (cc0)
         (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "")
   		 (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))]
   ""
-  "
 {
   ia64_compare_op0 = operands[0];
   ia64_compare_op1 = operands[1];
   DONE;
-}")
+})
 
 (define_expand "cmpdf"
   [(set (cc0)
         (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "")
   		 (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))]
   ""
-  "
 {
   ia64_compare_op0 = operands[0];
   ia64_compare_op1 = operands[1];
   DONE;
-}")
+})
 
 (define_expand "cmptf"
   [(set (cc0)
         (compare (match_operand:TF 0 "tfreg_or_fp01_operand" "")
   		 (match_operand:TF 1 "tfreg_or_fp01_operand" "")))]
   "INTEL_EXTENDED_IEEE_FORMAT"
-  "
 {
   ia64_compare_op0 = operands[0];
   ia64_compare_op1 = operands[1];
   DONE;
-}")
+})
 
 (define_insn "*cmpsi_normal"
   [(set (match_operand:BI 0 "register_operand" "=c")
@@ -4197,7 +4304,6 @@
    (use (match_operand 3 "" ""))	; loop level
    (use (match_operand 4 "" ""))]	; label
   ""
-  "
 {
   /* Only use cloop on innermost loops.  */
   if (INTVAL (operands[3]) > 1)
@@ -4205,7 +4311,7 @@
   emit_jump_insn (gen_doloop_end_internal (gen_rtx_REG (DImode, AR_LC_REGNUM),
 					   operands[4]));
   DONE;
-}")
+})
 
 (define_insn "doloop_end_internal"
   [(set (pc) (if_then_else (ne (match_operand:DI 0 "ar_lc_reg_operand" "")
@@ -4213,8 +4319,8 @@
 		(label_ref (match_operand 1 "" ""))
 		(pc)))
    (set (match_dup 0) (if_then_else:DI (ne (match_dup 0) (const_int 0))
-			 (match_dup 0)
-			 (plus:DI (match_dup 0) (const_int -1))))]
+			 (plus:DI (match_dup 0) (const_int -1))
+			 (match_dup 0)))]
   ""
   "br.cloop.sptk.few %l1"
   [(set_attr "itanium_class" "br")
@@ -4338,12 +4444,12 @@
 		"c,c,c,c,c,c,c,c,c,c,c,c,c,c,c")
 	     (const_int 0)])
 	  (match_operand:DI 2 "move_operand"
-	   "rim, *f, *b,*d*e,rim,rim, rim,*f,*b,*d*e,rO,*f,rOQ,rO,  rK")
+	   "rnm, *f, *b,*d*e,rnm,rnm, rnm,*f,*b,*d*e,rO,*f,rOQ,rO,  rK")
 	  (match_operand:DI 3 "move_operand"
-	   "rim,rim,rim, rim, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO,  rK")))]
+	   "rnm,rnm,rnm, rnm, *f, *b,*d*e,*f,*b,*d*e,rO,*f,rOQ,rO,  rK")))]
   "ia64_move_ok (operands[0], operands[2])
    && ia64_move_ok (operands[0], operands[3])"
-  "* abort ();"
+  { abort (); }
   [(set_attr "predicable" "no")])
 
 (define_split
@@ -4356,14 +4462,17 @@
 	  (match_operand 3 "move_operand" "")))]
   "reload_completed"
   [(const_int 0)]
-  "
 {
   rtx tmp;
+  int emitted_something;
+
+  emitted_something = 0;
   if (! rtx_equal_p (operands[0], operands[2]))
     {
       tmp = gen_rtx_SET (VOIDmode, operands[0], operands[2]);
       tmp = gen_rtx_COND_EXEC (VOIDmode, operands[4], tmp);
       emit_insn (tmp);
+      emitted_something = 1;
     }
   if (! rtx_equal_p (operands[0], operands[3]))
     {
@@ -4373,9 +4482,12 @@
 			       gen_rtx_SET (VOIDmode, operands[0],
 					    operands[3]));
       emit_insn (tmp);
+      emitted_something = 1;
     }
+  if (! emitted_something)
+    emit_note (NULL, NOTE_INSN_DELETED);
   DONE;
-}")
+})
 
 ;; Absolute value pattern.
 
@@ -4422,11 +4534,10 @@
    (cond_exec
      (match_dup 5)
      (set (match_dup 0) (match_dup 3)))]
-  "
 {
   operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
 				VOIDmode, operands[1], const0_rtx);
-}")
+})
 
 ;;
 ;; SImode if_then_else patterns.
@@ -4439,12 +4550,12 @@
 	    [(match_operand:BI 1 "register_operand" "c,c,c,c,c,c,c,c,c")
 	     (const_int 0)])
 	  (match_operand:SI 2 "move_operand"
-		    "0,0,0,rim*f,rO,rO,rim*f,rO,rO")
+		    "0,0,0,rnm*f,rO,rO,rnm*f,rO,rO")
 	  (match_operand:SI 3 "move_operand"
-		    "rim*f,rO,rO,0,0,0,rim*f,rO,rO")))]
+		    "rnm*f,rO,rO,0,0,0,rnm*f,rO,rO")))]
   "ia64_move_ok (operands[0], operands[2])
    && ia64_move_ok (operands[0], operands[3])"
-  "* abort ();"
+  { abort (); }
   [(set_attr "predicable" "no")])
 
 (define_insn "*abssi2_internal"
@@ -4490,11 +4601,10 @@
    (cond_exec
      (match_dup 5)
      (set (match_dup 0) (match_dup 3)))]
-  "
 {
   operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
 				VOIDmode, operands[1], const0_rtx);
-}")
+})
 
 (define_insn_and_split "*cond_opsi2_internal"
   [(set (match_operand:SI 0 "gr_register_operand" "=r")
@@ -4515,11 +4625,10 @@
    (cond_exec
      (match_dup 7)
      (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))]
-  "
 {
   operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
 				VOIDmode, operands[1], const0_rtx);
-}"
+}
   [(set_attr "itanium_class" "ialu")
    (set_attr "predicable" "no")])
 
@@ -4543,11 +4652,10 @@
    (cond_exec
      (match_dup 7)
      (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))]
-  "
 {
   operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
 				VOIDmode, operands[1], const0_rtx);
-}"
+}
   [(set_attr "itanium_class" "ialu")
    (set_attr "predicable" "no")])
 
@@ -4574,11 +4682,10 @@
    (use (match_operand 2 "" ""))
    (use (match_operand 3 "" ""))]
   ""
-  "
 {
-  ia64_expand_call (NULL_RTX, operands[0], operands[2], 0);
+  ia64_expand_call (NULL_RTX, operands[0], operands[2], false);
   DONE;
-}")
+})
 
 (define_expand "sibcall"
   [(use (match_operand:DI 0 "" ""))
@@ -4586,11 +4693,10 @@
    (use (match_operand 2 "" ""))
    (use (match_operand 3 "" ""))]
   ""
-  "
 {
-  ia64_expand_call (NULL_RTX, operands[0], operands[2], 1);
+  ia64_expand_call (NULL_RTX, operands[0], operands[2], true);
   DONE;
-}")
+})
 
 ;; Subroutine call instruction returning a value.  Operand 0 is the hard
 ;; register in which the value is returned.  There are three more operands,
@@ -4606,11 +4712,10 @@
    (use (match_operand 3 "" ""))
    (use (match_operand 4 "" ""))]
   ""
-  "
 {
-  ia64_expand_call (operands[0], operands[1], operands[3], 0);
+  ia64_expand_call (operands[0], operands[1], operands[3], false);
   DONE;
-}")
+})
 
 (define_expand "sibcall_value"
   [(use (match_operand 0 "" ""))
@@ -4619,11 +4724,10 @@
    (use (match_operand 3 "" ""))
    (use (match_operand 4 "" ""))]
   ""
-  "
 {
-  ia64_expand_call (operands[0], operands[1], operands[3], 1);
+  ia64_expand_call (operands[0], operands[1], operands[3], true);
   DONE;
-}")
+})
 
 ;; Call subroutine returning any type.
 
@@ -4633,7 +4737,6 @@
 	      (match_operand 1 "" "")
 	      (match_operand 2 "" "")])]
   ""
-  "
 {
   int i;
 
@@ -4652,61 +4755,127 @@
   emit_insn (gen_blockage ());
 
   DONE;
-}")
+})
 
-(define_insn "call_nopic"
-  [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i"))
-	 (match_operand 1 "" ""))
-   (clobber (match_operand:DI 2 "register_operand" "=b,b"))]
+(define_insn "call_nogp"
+  [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i"))
+	 (const_int 0))
+   (clobber (match_operand:DI 1 "register_operand" "=b,b"))]
   ""
-  "br.call%+.many %2 = %0"
+  "br.call%+.many %1 = %0"
   [(set_attr "itanium_class" "br,scall")])
 
-(define_insn "call_value_nopic"
+(define_insn "call_value_nogp"
   [(set (match_operand 0 "" "")
-	(call (mem:DI (match_operand:DI 1 "call_operand" "b,i"))
-	      (match_operand 2 "" "")))
-   (clobber (match_operand:DI 3 "register_operand" "=b,b"))]
+	(call (mem:DI (match_operand:DI 1 "call_operand" "?b,i"))
+	      (const_int 0)))
+   (clobber (match_operand:DI 2 "register_operand" "=b,b"))]
   ""
-  "br.call%+.many %3 = %1"
+  "br.call%+.many %2 = %1"
   [(set_attr "itanium_class" "br,scall")])
 
-(define_insn "sibcall_nopic"
-  [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i"))
-	 (match_operand 1 "" ""))
-   (use (match_operand:DI 2 "register_operand" "=b,b"))
-   (use (match_operand:DI 3 "ar_pfs_reg_operand" ""))]
+(define_insn "sibcall_nogp"
+  [(call (mem:DI (match_operand:DI 0 "call_operand" "?b,i"))
+	 (const_int 0))]
   ""
   "br%+.many %0"
   [(set_attr "itanium_class" "br,scall")])
 
-(define_insn "call_pic"
-  [(call (mem:DI (match_operand:DI 0 "call_operand" "b,i"))
-	 (match_operand 1 "" ""))
-   (use (unspec [(reg:DI 1)] 9))
-   (clobber (match_operand:DI 2 "register_operand" "=b,b"))]
+(define_insn "call_gp"
+  [(call (mem (match_operand 0 "call_operand" "?r,i"))
+	 (const_int 1))
+   (clobber (match_operand:DI 1 "register_operand" "=b,b"))
+   (clobber (match_scratch:DI 2 "=&r,X"))
+   (clobber (match_scratch:DI 3 "=b,X"))]
   ""
-  "br.call%+.many %2 = %0"
+  "#"
   [(set_attr "itanium_class" "br,scall")])
 
-(define_insn "call_value_pic"
+;; Irritatingly, we don't have access to INSN within the split body.
+;; See commentary in ia64_split_call as to why these aren't peep2.
+(define_split
+  [(call (mem (match_operand 0 "call_operand" ""))
+	 (const_int 1))
+   (clobber (match_operand:DI 1 "register_operand" ""))
+   (clobber (match_scratch:DI 2 ""))
+   (clobber (match_scratch:DI 3 ""))]
+  "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
+  [(const_int 0)]
+{
+  ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2],
+		   operands[3], true, false);
+  DONE;
+})
+
+(define_split
+  [(call (mem (match_operand 0 "call_operand" ""))
+	 (const_int 1))
+   (clobber (match_operand:DI 1 "register_operand" ""))
+   (clobber (match_scratch:DI 2 ""))
+   (clobber (match_scratch:DI 3 ""))]
+  "reload_completed"
+  [(const_int 0)]
+{
+  ia64_split_call (NULL_RTX, operands[0], operands[1], operands[2],
+		   operands[3], false, false);
+  DONE;
+})
+
+(define_insn "call_value_gp"
   [(set (match_operand 0 "" "")
-	(call (mem:DI (match_operand:DI 1 "call_operand" "b,i"))
-	      (match_operand 2 "" "")))
-   (use (unspec [(reg:DI 1)] 9))
-   (clobber (match_operand:DI 3 "register_operand" "=b,b"))]
+	(call (mem:DI (match_operand:DI 1 "call_operand" "?r,i"))
+	      (const_int 1)))
+   (clobber (match_operand:DI 2 "register_operand" "=b,b"))
+   (clobber (match_scratch:DI 3 "=&r,X"))
+   (clobber (match_scratch:DI 4 "=b,X"))]
   ""
-  "br.call%+.many %3 = %1"
+  "#"
   [(set_attr "itanium_class" "br,scall")])
 
-(define_insn "sibcall_pic"
-  [(call (mem:DI (match_operand:DI 0 "call_operand" "bi"))
-	 (match_operand 1 "" ""))
-   (use (unspec [(reg:DI 1)] 9))
-   (use (match_operand:DI 2 "register_operand" "=b"))
-   (use (match_operand:DI 3 "ar_pfs_reg_operand" ""))]
+(define_split
+  [(set (match_operand 0 "" "")
+	(call (mem:DI (match_operand:DI 1 "call_operand" ""))
+	      (const_int 1)))
+   (clobber (match_operand:DI 2 "register_operand" ""))
+   (clobber (match_scratch:DI 3 ""))
+   (clobber (match_scratch:DI 4 ""))]
+  "reload_completed && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
+  [(const_int 0)]
+{
+  ia64_split_call (operands[0], operands[1], operands[2], operands[3],
+		   operands[4], true, false);
+  DONE;
+})
+
+(define_split
+  [(set (match_operand 0 "" "")
+	(call (mem:DI (match_operand:DI 1 "call_operand" ""))
+	      (const_int 1)))
+   (clobber (match_operand:DI 2 "register_operand" ""))
+   (clobber (match_scratch:DI 3 ""))
+   (clobber (match_scratch:DI 4 ""))]
+  "reload_completed"
+  [(const_int 0)]
+{
+  ia64_split_call (operands[0], operands[1], operands[2], operands[3],
+		   operands[4], false, false);
+  DONE;
+})
+
+(define_insn_and_split "sibcall_gp"
+  [(call (mem:DI (match_operand:DI 0 "call_operand" "?r,i"))
+	 (const_int 1))
+   (clobber (match_scratch:DI 1 "=&r,X"))
+   (clobber (match_scratch:DI 2 "=b,X"))]
   ""
-  "br%+.many %0"
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+{
+  ia64_split_call (NULL_RTX, operands[0], NULL_RTX, operands[1],
+		   operands[2], true, true);
+  DONE;
+}
   [(set_attr "itanium_class" "br")])
 
 (define_insn "return_internal"
@@ -4817,29 +4986,26 @@
 (define_expand "prologue"
   [(const_int 1)]
   ""
-  "
 {
   ia64_expand_prologue ();
   DONE;
-}")
+})
 
 (define_expand "epilogue"
   [(return)]
   ""
-  "
 {
   ia64_expand_epilogue (0);
   DONE;
-}")
+})
 
 (define_expand "sibcall_epilogue"
   [(return)]
   ""
-  "
 {
   ia64_expand_epilogue (1);
   DONE;
-}")
+})
 
 ;; This prevents the scheduler from moving the SP decrement past FP-relative
 ;; stack accesses.  This is the same as adddi3 plus the extra set.
@@ -4852,9 +5018,9 @@
 	(match_dup 3))]
   ""
   "@
-  add %0 = %1, %2
-  adds %0 = %2, %1
-  addl %0 = %2, %1"
+   add %0 = %1, %2
+   adds %0 = %2, %1
+   addl %0 = %2, %1"
   [(set_attr "itanium_class" "ialu")])
 
 ;; This prevents the scheduler from moving the SP restore past FP-relative
@@ -4868,11 +5034,21 @@
   "mov %0 = %1"
   [(set_attr "itanium_class" "ialu")])
 
+;; As USE insns aren't meaningful after reload, this is used instead
+;; to prevent deleting instructions setting registers for EH handling
+(define_insn "prologue_use"
+  [(unspec:DI [(match_operand:DI 0 "register_operand" "")]
+	      UNSPEC_PROLOGUE_USE)]
+  ""
+  ""
+  [(set_attr "itanium_class" "ignore")
+   (set_attr "predicable" "no")])
+
 ;; Allocate a new register frame.
 
 (define_insn "alloc"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(unspec_volatile:DI [(const_int 0)] 0))
+	(unspec_volatile:DI [(const_int 0)] UNSPECV_ALLOC))
    (use (match_operand:DI 1 "const_int_operand" "i"))
    (use (match_operand:DI 2 "const_int_operand" "i"))
    (use (match_operand:DI 3 "const_int_operand" "i"))
@@ -4886,7 +5062,8 @@
 (define_expand "gr_spill"
   [(parallel [(set (match_operand:DI 0 "memory_operand" "=m")
 		   (unspec:DI [(match_operand:DI 1 "register_operand" "r")
-			       (match_operand:DI 2 "const_int_operand" "")] 1))
+			       (match_operand:DI 2 "const_int_operand" "")]
+			      UNSPEC_GR_SPILL))
 	      (clobber (match_dup 3))])]
   ""
   "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
@@ -4894,20 +5071,23 @@
 (define_insn "gr_spill_internal"
   [(set (match_operand:DI 0 "memory_operand" "=m")
 	(unspec:DI [(match_operand:DI 1 "register_operand" "r")
-		    (match_operand:DI 2 "const_int_operand" "")] 1))
+		    (match_operand:DI 2 "const_int_operand" "")]
+		   UNSPEC_GR_SPILL))
    (clobber (match_operand:DI 3 "register_operand" ""))]
   ""
-  "*
 {
-  return \".mem.offset %2, 0\;%,st8.spill %0 = %1%P0\";
-}"
+  /* Note that we use a C output pattern here to avoid the predicate
+     being automatically added before the .mem.offset directive.  */
+  return ".mem.offset %2, 0\;%,st8.spill %0 = %1%P0";
+}
   [(set_attr "itanium_class" "st")])
 
 ;; Reads ar.unat
 (define_expand "gr_restore"
   [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
 		   (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
-			       (match_operand:DI 2 "const_int_operand" "")] 2))
+			       (match_operand:DI 2 "const_int_operand" "")]
+			      UNSPEC_GR_RESTORE))
 	      (use (match_dup 3))])]
   ""
   "operands[3] = gen_rtx_REG (DImode, AR_UNAT_REGNUM);")
@@ -4915,25 +5095,25 @@
 (define_insn "gr_restore_internal"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(unspec:DI [(match_operand:DI 1 "memory_operand" "m")
-		    (match_operand:DI 2 "const_int_operand" "")] 2))
+		    (match_operand:DI 2 "const_int_operand" "")]
+		   UNSPEC_GR_RESTORE))
    (use (match_operand:DI 3 "register_operand" ""))]
   ""
-  "*
-{
-  return \".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1\";
-}"
+  { return ".mem.offset %2, 0\;%,ld8.fill %0 = %1%P1"; }
   [(set_attr "itanium_class" "ld")])
 
 (define_insn "fr_spill"
   [(set (match_operand:TF 0 "memory_operand" "=m")
-	(unspec:TF [(match_operand:TF 1 "register_operand" "f")] 3))]
+	(unspec:TF [(match_operand:TF 1 "register_operand" "f")]
+		   UNSPEC_FR_SPILL))]
   ""
   "stf.spill %0 = %1%P0"
   [(set_attr "itanium_class" "stf")])
 
 (define_insn "fr_restore"
   [(set (match_operand:TF 0 "register_operand" "=f")
-	(unspec:TF [(match_operand:TF 1 "memory_operand" "m")] 4))]
+	(unspec:TF [(match_operand:TF 1 "memory_operand" "m")]
+		   UNSPEC_FR_RESTORE))]
   ""
   "ldf.fill %0 = %1%P1"
   [(set_attr "itanium_class" "fld")])
@@ -4944,15 +5124,33 @@
 
 (define_insn "bsp_value"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(unspec:DI [(const_int 0)] 20))]
+	(unspec:DI [(const_int 0)] UNSPEC_BSP_VALUE))]
   ""
-  ";;\;mov %0 = ar.bsp"
+  "*
+{
+  return \";;\;%,mov %0 = ar.bsp\";
+}"
   [(set_attr "itanium_class" "frar_i")])
 
 (define_insn "set_bsp"
-  [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 5)]
-  ""
-  "flushrs\;mov r19=ar.rsc\;;;\;and r19=0x1c,r19\;;;\;mov ar.rsc=r19\;;;\;mov ar.bspstore=%0\;;;\;or r19=0x3,r19\;;;\;loadrs\;invala\;;;\;mov ar.rsc=r19"
+  [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
+		    UNSPECV_SET_BSP)]
+  ""
+  "flushrs
+	mov r19=ar.rsc
+	;;
+	and r19=0x1c,r19
+	;;
+	mov ar.rsc=r19
+	;;
+	mov ar.bspstore=%0
+	;;
+	or r19=0x3,r19
+	;;
+	loadrs
+	invala
+	;;
+	mov ar.rsc=r19"
   [(set_attr "itanium_class" "unknown")
    (set_attr "predicable" "no")])
 
@@ -4961,10 +5159,11 @@
 ;; fixed later.  This avoids an RSE DV.
 
 (define_insn "flushrs"
-  [(unspec [(const_int 0)] 21)]
+  [(unspec [(const_int 0)] UNSPEC_FLUSHRS)]
   ""
   ";;\;flushrs\;;;"
-  [(set_attr "itanium_class" "rse_m")])
+  [(set_attr "itanium_class" "rse_m")
+   (set_attr "predicable" "no")])
 
 ;; ::::::::::::::::::::
 ;; ::
@@ -5012,34 +5211,25 @@
   ""
   [(set_attr "itanium_class" "nop_x")])
 
-(define_insn "cycle_display"
-  [(unspec [(match_operand 0 "const_int_operand" "")] 23)]
-  ""
-  "// cycle %0"
-  [(set_attr "itanium_class" "ignore")
-   (set_attr "predicable" "no")])
-
 (define_insn "bundle_selector"
-  [(unspec [(match_operand 0 "const_int_operand" "")] 22)]
+  [(unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BUNDLE_SELECTOR)]
   ""
-  "*
-{
-  return get_bundle_name (INTVAL (operands[0]));
-}"
+  { return get_bundle_name (INTVAL (operands[0])); }
   [(set_attr "itanium_class" "ignore")
    (set_attr "predicable" "no")])
 
 ;; Pseudo instruction that prevents the scheduler from moving code above this
 ;; point.
 (define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 1)]
+  [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
   ""
   ""
   [(set_attr "itanium_class" "ignore")
    (set_attr "predicable" "no")])
 
 (define_insn "insn_group_barrier"
-  [(unspec_volatile [(match_operand 0 "const_int_operand" "")] 2)]
+  [(unspec_volatile [(match_operand 0 "const_int_operand" "")]
+		    UNSPECV_INSN_GROUP_BARRIER)]
   ""
   ";;"
   [(set_attr "itanium_class" "stop_bit")
@@ -5077,7 +5267,7 @@
    (set_attr "predicable" "no")])
 
 (define_insn "break_f"
-  [(unspec_volatile [(const_int 0)] 3)]
+  [(unspec_volatile [(const_int 0)] UNSPECV_BREAK)]
   ""
   "break.f 0"
   [(set_attr "itanium_class" "nop_f")])
@@ -5119,14 +5309,13 @@
   [(use (match_operand:OI 0 "memory_operand" ""))
    (use (match_operand:DI 1 "register_operand" ""))]
   ""
-  "
 {
   emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
 					 \"__ia64_save_stack_nonlocal\"),
 		     0, VOIDmode, 2, XEXP (operands[0], 0), Pmode,
 		     operands[1], Pmode);
   DONE;
-}")
+})
 
 (define_expand "nonlocal_goto"
   [(use (match_operand 0 "general_operand" ""))
@@ -5134,7 +5323,6 @@
    (use (match_operand 2 "general_operand" ""))
    (use (match_operand 3 "general_operand" ""))]
   ""
-  "
 {
   emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"),
 		     LCT_NORETURN, VOIDmode, 3,
@@ -5143,34 +5331,24 @@
 		     operands[3], Pmode);
   emit_barrier ();
   DONE;
-}")
-
-;; The rest of the setjmp processing happens with the nonlocal_goto expander.
-;; ??? This is not tested.
-(define_expand "builtin_setjmp_setup"
-  [(use (match_operand:DI 0 "" ""))]
-  ""
-  "
-{
-  emit_move_insn (ia64_gp_save_reg (0), gen_rtx_REG (DImode, GR_REG (1)));
-  DONE;
-}")
+})
 
-(define_expand "builtin_setjmp_receiver"
-  [(use (match_operand:DI 0 "" ""))]
+(define_insn_and_split "builtin_setjmp_receiver"
+  [(unspec_volatile [(match_operand:DI 0 "" "")] UNSPECV_SETJMP_RECEIVER)]
   ""
-  "
+  "#"
+  "reload_completed"
+  [(const_int 0)]
 {
-  emit_move_insn (gen_rtx_REG (DImode, GR_REG (1)), ia64_gp_save_reg (0));
+  ia64_reload_gp ();
   DONE;
-}")
+})
 
 (define_expand "eh_epilogue"
   [(use (match_operand:DI 0 "register_operand" "r"))
    (use (match_operand:DI 1 "register_operand" "r"))
    (use (match_operand:DI 2 "register_operand" "r"))]
   ""
-  "
 {
   rtx bsp = gen_rtx_REG (Pmode, 10);
   rtx sp = gen_rtx_REG (Pmode, 9);
@@ -5190,7 +5368,7 @@
 
   cfun->machine->ia64_eh_epilogue_sp = sp;
   cfun->machine->ia64_eh_epilogue_bsp = bsp;
-}")
+})
 
 ;; Builtin apply support.
 
@@ -5198,31 +5376,29 @@
   [(use (match_operand:DI 0 "register_operand" ""))
    (use (match_operand:OI 1 "memory_operand" ""))]
   ""
-  "
 {
   emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
-					 \"__ia64_restore_stack_nonlocal\"),
+					 "__ia64_restore_stack_nonlocal"),
 		     0, VOIDmode, 1,
 		     copy_to_reg (XEXP (operands[1], 0)), Pmode);
   DONE;
-}")
+})
 
 
 ;;; Intrinsics support.
 
 (define_expand "mf"
   [(set (mem:BLK (match_dup 0))
-	(unspec:BLK [(mem:BLK (match_dup 0))] 12))]
+	(unspec:BLK [(mem:BLK (match_dup 0))] UNSPEC_MF))]
   ""
-  "
 {
   operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode));
   MEM_VOLATILE_P (operands[0]) = 1;
-}")
+})
 
 (define_insn "*mf_internal"
   [(set (match_operand:BLK 0 "" "")
-	(unspec:BLK [(match_operand:BLK 1 "" "")] 12))]
+	(unspec:BLK [(match_operand:BLK 1 "" "")] UNSPEC_MF))]
   ""
   "mf"
   [(set_attr "itanium_class" "syst_m")])
@@ -5232,7 +5408,8 @@
 	(match_dup 1))
    (set (match_operand:SI 1 "not_postinc_memory_operand" "+S")
 	(unspec:SI [(match_dup 1)
-		    (match_operand:SI 2 "fetchadd_operand" "n")] 19))]
+		    (match_operand:SI 2 "fetchadd_operand" "n")]
+		   UNSPEC_FETCHADD_ACQ))]
   ""
   "fetchadd4.acq %0 = %1, %2"
   [(set_attr "itanium_class" "sem")])
@@ -5242,7 +5419,8 @@
 	(match_dup 1))
    (set (match_operand:DI 1 "not_postinc_memory_operand" "+S")
 	(unspec:DI [(match_dup 1)
-		    (match_operand:DI 2 "fetchadd_operand" "n")] 19))]
+		    (match_operand:DI 2 "fetchadd_operand" "n")]
+		   UNSPEC_FETCHADD_ACQ))]
   ""
   "fetchadd8.acq %0 = %1, %2"
   [(set_attr "itanium_class" "sem")])
@@ -5253,7 +5431,8 @@
    (set (match_operand:SI 1 "not_postinc_memory_operand" "+S")
         (unspec:SI [(match_dup 1)
                     (match_operand:SI 2 "gr_register_operand" "r")
-		    (match_operand:SI 3 "ar_ccv_reg_operand" "")] 13))]
+		    (match_operand 3 "ar_ccv_reg_operand" "")]
+		   UNSPEC_CMPXCHG_ACQ))]
   ""
   "cmpxchg4.acq %0 = %1, %2, %3"
   [(set_attr "itanium_class" "sem")])
@@ -5264,7 +5443,8 @@
    (set (match_operand:DI 1 "not_postinc_memory_operand" "+S")
         (unspec:DI [(match_dup 1)
                     (match_operand:DI 2 "gr_register_operand" "r")
-		    (match_operand:DI 3 "ar_ccv_reg_operand" "")] 13))]
+		    (match_operand:DI 3 "ar_ccv_reg_operand" "")]
+		   UNSPEC_CMPXCHG_ACQ))]
   ""
   "cmpxchg8.acq %0 = %1, %2, %3"
   [(set_attr "itanium_class" "sem")])
@@ -5298,48 +5478,59 @@
 
 (define_insn "pred_rel_mutex"
   [(set (match_operand:BI 0 "register_operand" "+c")
-       (unspec:BI [(match_dup 0)] 7))]
+       (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
   ""
   ".pred.rel.mutex %0, %I0"
   [(set_attr "itanium_class" "ignore")
    (set_attr "predicable" "no")])
 
 (define_insn "safe_across_calls_all"
-  [(unspec_volatile [(const_int 0)] 8)]
+  [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_ALL)]
   ""
   ".pred.safe_across_calls p1-p63"
   [(set_attr "itanium_class" "ignore")
    (set_attr "predicable" "no")])
 
 (define_insn "safe_across_calls_normal"
-  [(unspec_volatile [(const_int 0)] 9)]
+  [(unspec_volatile [(const_int 0)] UNSPECV_PSAC_NORMAL)]
   ""
-  "*
 {
   emit_safe_across_calls (asm_out_file);
-  return \"\";
-}"
+  return "";
+}
   [(set_attr "itanium_class" "ignore")
    (set_attr "predicable" "no")])
 
-;;
-;;
 ;; UNSPEC instruction definition to "swizzle" 32 bit pointer into 64 bit
 ;; pointer.  This is used by the HP-UX 32 bit mode.
 
 (define_insn "ptr_extend"
   [(set (match_operand:DI 0 "gr_register_operand" "=r")
-        (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")] 24))]
+        (unspec:DI [(match_operand:SI 1 "gr_register_operand" "r")]
+		   UNSPEC_ADDP4))]
   ""
   "addp4 %0 = 0,%1"
   [(set_attr "itanium_class" "ialu")])
 
 ;;
-;; As USE insns aren't meaningful after reload, this is used instead
-;; to prevent deleting instructions setting registers for EH handling
-(define_insn "prologue_use"
-  [(unspec:DI [(match_operand:DI 0 "register_operand" "")] 25)]
-  ""
-  "// %0 needed for EH"
-  [(set_attr "itanium_class" "ignore")
-   (set_attr "predicable" "no")])
+;; Optimizations for ptr_extend
+
+(define_insn "*ptr_extend_plus_1"
+  [(set (match_operand:DI 0 "gr_register_operand" "=r")
+        (unspec:DI
+         [(plus:SI (match_operand:SI 1 "basereg_operand" "r")
+                   (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))]
+         UNSPEC_ADDP4))]
+  "addp4_optimize_ok (operands[1], operands[2])"
+  "addp4 %0 = %2, %1"
+  [(set_attr "itanium_class" "ialu")])
+
+(define_insn "*ptr_extend_plus_2"
+  [(set (match_operand:DI 0 "gr_register_operand" "=r")
+        (unspec:DI
+         [(plus:SI (match_operand:SI 1 "gr_register_operand" "r")
+                   (match_operand:SI 2 "basereg_operand" "r"))]
+         UNSPEC_ADDP4))]
+  "addp4_optimize_ok (operands[1], operands[2])"
+  "addp4 %0 = %1, %2"
+  [(set_attr "itanium_class" "ialu")])