Virgin import of gcc from EGCS 1.1.2

25 files changed, 7888 insertions, 1850 deletions

diff --git a/contrib/gcc/config/alpha/alpha.c b/contrib/gcc/config/alpha/alpha.c
index b77dc149bc61..0b72289e15aa 100644
--- a/contrib/gcc/config/alpha/alpha.c
+++ b/contrib/gcc/config/alpha/alpha.c
@@ -1,5 +1,5 @@
 /* Subroutines used for code generation on the DEC Alpha.
-   Copyright (C) 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
+   Copyright (C) 1992, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
    Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
 
 This file is part of GNU CC.
@@ -20,8 +20,8 @@ the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
 
-#include <stdio.h>
 #include "config.h"
+#include "system.h"
 #include "rtl.h"
 #include "regs.h"
 #include "hard-reg-set.h"
@@ -34,9 +34,44 @@ Boston, MA 02111-1307, USA.  */
 #include "flags.h"
 #include "recog.h"
 #include "reload.h"
+#include "tree.h"
 #include "expr.h"
 #include "obstack.h"
-#include "tree.h"
+#include "except.h"
+#include "function.h"
+#include "toplev.h"
+
+/* External data.  */
+extern char *version_string;
+extern int rtx_equal_function_value_matters;
+
+/* Specify which cpu to schedule for. */
+
+enum processor_type alpha_cpu;
+static char* const alpha_cpu_name[] = 
+{
+  "ev4", "ev5", "ev6"
+};
+
+/* Specify how accurate floating-point traps need to be.  */
+
+enum alpha_trap_precision alpha_tp;
+
+/* Specify the floating-point rounding mode.  */
+
+enum alpha_fp_rounding_mode alpha_fprm;
+
+/* Specify which things cause traps.  */
+
+enum alpha_fp_trap_mode alpha_fptm;
+
+/* Strings decoded into the above options.  */
+
+char *alpha_cpu_string;		/* -mcpu= */
+char *alpha_tp_string;		/* -mtrap-precision=[p|s|i] */
+char *alpha_fprm_string;	/* -mfp-rounding-mode=[n|m|c|d] */
+char *alpha_fptm_string;	/* -mfp-trap-mode=[n|u|su|sui] */
+char *alpha_mlat_string;	/* -mmemory-latency= */
 
 /* Save information from a "cmpxx" operation until the branch or scc is
    emitted.  */
@@ -44,26 +79,226 @@ Boston, MA 02111-1307, USA.  */
 rtx alpha_compare_op0, alpha_compare_op1;
 int alpha_compare_fp_p;
 
-/* Save the name of the current function as used by the assembler.  This
-   is used by the epilogue.  */
-
-char *alpha_function_name;
-
 /* Non-zero if inside of a function, because the Alpha asm can't
    handle .files inside of functions.  */
 
 static int inside_function = FALSE;
 
-/* Nonzero if the current function needs gp.  */
+/* If non-null, this rtx holds the return address for the function.  */
 
-int alpha_function_needs_gp;
+static rtx alpha_return_addr_rtx;
 
-extern char *version_string;
-extern int rtx_equal_function_value_matters;
+/* The number of cycles of latency we should assume on memory reads.  */
+
+int alpha_memory_latency = 3;
+
+/* Whether the function needs the GP.  */
+
+static int alpha_function_needs_gp;
 
 /* Declarations of static functions.  */
-static void alpha_set_memflags_1  PROTO((rtx, int, int, int));
-static void add_long_const	PROTO((FILE *, HOST_WIDE_INT, int, int, int));
+static void alpha_set_memflags_1
+  PROTO((rtx, int, int, int));
+static rtx alpha_emit_set_const_1
+  PROTO((rtx, enum machine_mode, HOST_WIDE_INT, int));
+static void alpha_expand_unaligned_load_words
+  PROTO((rtx *out_regs, rtx smem, HOST_WIDE_INT words, HOST_WIDE_INT ofs));
+static void alpha_expand_unaligned_store_words
+  PROTO((rtx *out_regs, rtx smem, HOST_WIDE_INT words, HOST_WIDE_INT ofs));
+static void alpha_sa_mask
+  PROTO((unsigned long *imaskP, unsigned long *fmaskP));
+static int alpha_does_function_need_gp
+  PROTO((void));
+
+
+/* Get the number of args of a function in one of two ways.  */
+#ifdef OPEN_VMS
+#define NUM_ARGS current_function_args_info.num_args
+#else
+#define NUM_ARGS current_function_args_info
+#endif
+
+#define REG_PV 27
+#define REG_RA 26
+
+/* Parse target option strings. */
+
+void
+override_options ()
+{
+  alpha_cpu
+    = TARGET_CPU_DEFAULT & MASK_CPU_EV6 ? PROCESSOR_EV6
+      : (TARGET_CPU_DEFAULT & MASK_CPU_EV5 ? PROCESSOR_EV5 : PROCESSOR_EV4);
+
+  if (alpha_cpu_string)
+    {
+      if (! strcmp (alpha_cpu_string, "ev4")
+	  || ! strcmp (alpha_cpu_string, "21064"))
+	{
+	  alpha_cpu = PROCESSOR_EV4;
+	  target_flags &= ~ (MASK_BWX | MASK_CIX | MASK_MAX);
+	}
+      else if (! strcmp (alpha_cpu_string, "ev5")
+	       || ! strcmp (alpha_cpu_string, "21164"))
+	{
+	  alpha_cpu = PROCESSOR_EV5;
+	  target_flags &= ~ (MASK_BWX | MASK_CIX | MASK_MAX);
+	}
+      else if (! strcmp (alpha_cpu_string, "ev56")
+	       || ! strcmp (alpha_cpu_string, "21164a"))
+	{
+	  alpha_cpu = PROCESSOR_EV5;
+	  target_flags |= MASK_BWX;
+	  target_flags &= ~ (MASK_CIX | MASK_MAX);
+	}
+      else if (! strcmp (alpha_cpu_string, "pca56")
+	       || ! strcmp (alpha_cpu_string, "21164PC")
+	       || ! strcmp (alpha_cpu_string, "21164pc"))
+	{
+	  alpha_cpu = PROCESSOR_EV5;
+	  target_flags |= MASK_BWX | MASK_MAX;
+	  target_flags &= ~ MASK_CIX;
+	}
+      else if (! strcmp (alpha_cpu_string, "ev6")
+	       || ! strcmp (alpha_cpu_string, "21264"))
+	{
+	  alpha_cpu = PROCESSOR_EV6;
+	  target_flags |= MASK_BWX | MASK_CIX | MASK_MAX;
+	}
+      else
+	error ("bad value `%s' for -mcpu switch", alpha_cpu_string);
+    }
+
+  alpha_tp = ALPHA_TP_PROG;
+  alpha_fprm = ALPHA_FPRM_NORM;
+  alpha_fptm = ALPHA_FPTM_N;
+
+  if (TARGET_IEEE)
+    {
+      alpha_tp = ALPHA_TP_INSN;
+      alpha_fptm = ALPHA_FPTM_SU;
+    }
+
+  if (TARGET_IEEE_WITH_INEXACT)
+    {
+      alpha_tp = ALPHA_TP_INSN;
+      alpha_fptm = ALPHA_FPTM_SUI;
+    }
+
+  if (alpha_tp_string)
+    {
+      if (! strcmp (alpha_tp_string, "p"))
+	alpha_tp = ALPHA_TP_PROG;
+      else if (! strcmp (alpha_tp_string, "f"))
+	alpha_tp = ALPHA_TP_FUNC;
+      else if (! strcmp (alpha_tp_string, "i"))
+	alpha_tp = ALPHA_TP_INSN;
+      else
+	error ("bad value `%s' for -mtrap-precision switch", alpha_tp_string);
+    }
+
+  if (alpha_fprm_string)
+    {
+      if (! strcmp (alpha_fprm_string, "n"))
+	alpha_fprm = ALPHA_FPRM_NORM;
+      else if (! strcmp (alpha_fprm_string, "m"))
+	alpha_fprm = ALPHA_FPRM_MINF;
+      else if (! strcmp (alpha_fprm_string, "c"))
+	alpha_fprm = ALPHA_FPRM_CHOP;
+      else if (! strcmp (alpha_fprm_string,"d"))
+	alpha_fprm = ALPHA_FPRM_DYN;
+      else
+	error ("bad value `%s' for -mfp-rounding-mode switch",
+	       alpha_fprm_string);
+    }
+
+  if (alpha_fptm_string)
+    {
+      if (strcmp (alpha_fptm_string, "n") == 0)
+	alpha_fptm = ALPHA_FPTM_N;
+      else if (strcmp (alpha_fptm_string, "u") == 0)
+	alpha_fptm = ALPHA_FPTM_U;
+      else if (strcmp (alpha_fptm_string, "su") == 0)
+	alpha_fptm = ALPHA_FPTM_SU;
+      else if (strcmp (alpha_fptm_string, "sui") == 0)
+	alpha_fptm = ALPHA_FPTM_SUI;
+      else
+	error ("bad value `%s' for -mfp-trap-mode switch", alpha_fptm_string);
+    }
+
+  /* Do some sanity checks on the above option. */
+
+  if ((alpha_fptm == ALPHA_FPTM_SU || alpha_fptm == ALPHA_FPTM_SUI)
+      && alpha_tp != ALPHA_TP_INSN)
+    {
+      warning ("fp software completion requires -mtrap-precision=i");
+      alpha_tp = ALPHA_TP_INSN;
+    }
+
+  if (TARGET_FLOAT_VAX)
+    {
+      if (alpha_fprm == ALPHA_FPRM_MINF || alpha_fprm == ALPHA_FPRM_DYN)
+	{
+	  warning ("rounding mode not supported for VAX floats");
+	  alpha_fprm = ALPHA_FPRM_NORM;
+	}
+      if (alpha_fptm == ALPHA_FPTM_SUI)
+	{
+	  warning ("trap mode not supported for VAX floats");
+	  alpha_fptm = ALPHA_FPTM_SU;
+	}
+    }
+
+  {
+    char *end;
+    int lat;
+
+    if (!alpha_mlat_string)
+      alpha_mlat_string = "L1";
+
+    if (isdigit (alpha_mlat_string[0])
+	&& (lat = strtol (alpha_mlat_string, &end, 10), *end == '\0'))
+      ;
+    else if ((alpha_mlat_string[0] == 'L' || alpha_mlat_string[0] == 'l')
+	     && isdigit (alpha_mlat_string[1])
+	     && alpha_mlat_string[2] == '\0')
+      {
+	static int const cache_latency[][4] = 
+	{
+	  { 3, 30, -1 },	/* ev4 -- Bcache is a guess */
+	  { 2, 12, 38 },	/* ev5 -- Bcache from PC164 LMbench numbers */
+	  { 3, 13, -1 },	/* ev6 -- Ho hum, doesn't exist yet */
+	};
+
+	lat = alpha_mlat_string[1] - '0';
+	if (lat < 0 || lat > 3 || cache_latency[alpha_cpu][lat-1] == -1)
+	  {
+	    warning ("L%d cache latency unknown for %s",
+		     lat, alpha_cpu_name[alpha_cpu]);
+	    lat = 3;
+	  }
+	else
+	  lat = cache_latency[alpha_cpu][lat-1];
+      }
+    else if (! strcmp (alpha_mlat_string, "main"))
+      {
+	/* Most current memories have about 370ns latency.  This is
+	   a reasonable guess for a fast cpu.  */
+	lat = 150;
+      }
+    else
+      {
+	warning ("bad value `%s' for -mmemory-latency", alpha_mlat_string);
+	lat = 3;
+      }
+
+    alpha_memory_latency = lat;
+  }
+
+  /* Default the definition of "small data" to 8 bytes.  */
+  if (!g_switch_set)
+    g_switch_value = 8;
+}
 
 /* Returns 1 if VALUE is a mask that contains full bytes of zero or ones.  */
 
@@ -102,6 +337,7 @@ reg_or_6bit_operand (op, mode)
 {
   return ((GET_CODE (op) == CONST_INT
 	   && (unsigned HOST_WIDE_INT) INTVAL (op) < 64)
+	  || GET_CODE (op) == CONSTANT_P_RTX
 	  || register_operand (op, mode));
 }
 
@@ -115,6 +351,7 @@ reg_or_8bit_operand (op, mode)
 {
   return ((GET_CODE (op) == CONST_INT
 	   && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100)
+	  || GET_CODE (op) == CONSTANT_P_RTX
 	  || register_operand (op, mode));
 }
 
@@ -123,10 +360,11 @@ reg_or_8bit_operand (op, mode)
 int
 cint8_operand (op, mode)
      register rtx op;
-     enum machine_mode mode;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
-  return (GET_CODE (op) == CONST_INT
-	  && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100);
+  return ((GET_CODE (op) == CONST_INT
+	   && (unsigned HOST_WIDE_INT) INTVAL (op) < 0x100)
+	  || GET_CODE (op) == CONSTANT_P_RTX);
 }
 
 /* Return 1 if the operand is a valid second operand to an add insn.  */
@@ -140,6 +378,8 @@ add_operand (op, mode)
     return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')
 	    || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L')
 	    || CONST_OK_FOR_LETTER_P (INTVAL (op), 'O'));
+  else if (GET_CODE (op) == CONSTANT_P_RTX)
+    return 1;
 
   return register_operand (op, mode);
 }
@@ -155,6 +395,8 @@ sext_add_operand (op, mode)
   if (GET_CODE (op) == CONST_INT)
     return ((unsigned HOST_WIDE_INT) INTVAL (op) < 255
 	    || (unsigned HOST_WIDE_INT) (- INTVAL (op)) < 255);
+  else if (GET_CODE (op) == CONSTANT_P_RTX)
+    return 1;
 
   return register_operand (op, mode);
 }
@@ -164,7 +406,7 @@ sext_add_operand (op, mode)
 int
 const48_operand (op, mode)
      register rtx op;
-     enum machine_mode mode;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   return (GET_CODE (op) == CONST_INT
 	  && (INTVAL (op) == 4 || INTVAL (op) == 8));
@@ -185,6 +427,8 @@ and_operand (op, mode)
     return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
 	    || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100
 	    || zap_mask (INTVAL (op)));
+  else if (GET_CODE (op) == CONSTANT_P_RTX)
+    return 1;
 
   return register_operand (op, mode);
 }
@@ -199,6 +443,8 @@ or_operand (op, mode)
   if (GET_CODE (op) == CONST_INT)
     return ((unsigned HOST_WIDE_INT) INTVAL (op) < 0x100
 	    || (unsigned HOST_WIDE_INT) ~ INTVAL (op) < 0x100);
+  else if (GET_CODE (op) == CONSTANT_P_RTX)
+    return 1;
 
   return register_operand (op, mode);
 }
@@ -209,10 +455,11 @@ or_operand (op, mode)
 int
 mode_width_operand (op, mode)
      register rtx op;
-     enum machine_mode mode;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   return (GET_CODE (op) == CONST_INT
-	  && (INTVAL (op) == 8 || INTVAL (op) == 16 || INTVAL (op) == 32));
+	  && (INTVAL (op) == 8 || INTVAL (op) == 16
+	      || INTVAL (op) == 32 || INTVAL (op) == 64));
 }
 
 /* Return 1 if OP is a constant that is the width of an integral machine mode
@@ -221,18 +468,24 @@ mode_width_operand (op, mode)
 int
 mode_mask_operand (op, mode)
      register rtx op;
-     enum machine_mode mode;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
 #if HOST_BITS_PER_WIDE_INT == 32
   if (GET_CODE (op) == CONST_DOUBLE)
-    return CONST_DOUBLE_HIGH (op) == 0 && CONST_DOUBLE_LOW (op) == -1;
+    return (CONST_DOUBLE_LOW (op) == -1
+	    && (CONST_DOUBLE_HIGH (op) == -1
+		|| CONST_DOUBLE_HIGH (op) == 0));
+#else
+  if (GET_CODE (op) == CONST_DOUBLE)
+    return (CONST_DOUBLE_LOW (op) == -1 && CONST_DOUBLE_HIGH (op) == 0);
 #endif
 
   return (GET_CODE (op) == CONST_INT
 	  && (INTVAL (op) == 0xff
 	      || INTVAL (op) == 0xffff
-#if HOST_BITS_PER_WIDE_INT == 64
 	      || INTVAL (op) == 0xffffffff
+#if HOST_BITS_PER_WIDE_INT == 64
+	      || INTVAL (op) == 0xffffffffffffffff
 #endif
 	      ));
 }
@@ -242,7 +495,7 @@ mode_mask_operand (op, mode)
 int
 mul8_operand (op, mode)
      register rtx op;
-     enum machine_mode mode;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   return (GET_CODE (op) == CONST_INT
 	  && (unsigned HOST_WIDE_INT) INTVAL (op) < 64
@@ -270,6 +523,18 @@ reg_or_fp0_operand (op, mode)
   return fp0_operand (op, mode) || register_operand (op, mode);
 }
 
+/* Return 1 if OP is a hard floating-point register.  */
+
+int
+hard_fp_register_operand (op, mode)
+     register rtx op;
+     enum machine_mode mode;
+{
+  return ((GET_CODE (op) == REG && REGNO_REG_CLASS (REGNO (op)) == FLOAT_REGS)
+	  || (GET_CODE (op) == SUBREG
+	      && hard_fp_register_operand (SUBREG_REG (op), mode)));
+}
+
 /* Return 1 if OP is a register or a constant integer.  */
 
 
@@ -278,7 +543,9 @@ reg_or_cint_operand (op, mode)
     register rtx op;
     enum machine_mode mode;
 {
-     return GET_CODE (op) == CONST_INT || register_operand (op, mode);
+     return (GET_CODE (op) == CONST_INT
+	     || GET_CODE (op) == CONSTANT_P_RTX
+	     || register_operand (op, mode));
 }
 
 /* Return 1 if OP is something that can be reloaded into a register;
@@ -294,12 +561,15 @@ some_operand (op, mode)
 
   switch (GET_CODE (op))
     {
-    case REG:  case MEM:  case CONST_DOUBLE:
-    case CONST_INT:  case LABEL_REF:  case SYMBOL_REF:  case CONST:
+    case REG:  case MEM:  case CONST_DOUBLE:  case CONST_INT:  case LABEL_REF:
+    case SYMBOL_REF:  case CONST:  case CONSTANT_P_RTX:
       return 1;
 
     case SUBREG:
       return some_operand (SUBREG_REG (op), VOIDmode);
+
+    default:
+      break;
     }
 
   return 0;
@@ -323,7 +593,7 @@ input_operand (op, mode)
     case LABEL_REF:
     case SYMBOL_REF:
     case CONST:
-        /* This handles both the Windows/NT and OSF cases.  */
+      /* This handles both the Windows/NT and OSF cases.  */
       return mode == ptr_mode || mode == DImode;
 
     case REG:
@@ -334,13 +604,18 @@ input_operand (op, mode)
 	return 1;
       /* ... fall through ... */
     case MEM:
-      return mode != HImode && mode != QImode && general_operand (op, mode);
+      return ((TARGET_BWX || (mode != HImode && mode != QImode))
+	      && general_operand (op, mode));
 
     case CONST_DOUBLE:
       return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
 
     case CONST_INT:
+    case CONSTANT_P_RTX:
       return mode == QImode || mode == HImode || add_operand (op, mode);
+
+    default:
+      break;
     }
 
   return 0;
@@ -352,7 +627,7 @@ input_operand (op, mode)
 int
 current_file_function_operand (op, mode)
      rtx op;
-     enum machine_mode mode;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   return (GET_CODE (op) == SYMBOL_REF
 	  && ! profile_flag && ! profile_block_flag
@@ -370,7 +645,9 @@ call_operand (op, mode)
   if (mode != Pmode)
     return 0;
 
-  return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
+  return (GET_CODE (op) == SYMBOL_REF
+	  || (GET_CODE (op) == REG
+	      && (TARGET_OPEN_VMS || TARGET_WINDOWS_NT || REGNO (op) == 27)));
 }
 
 /* Return 1 if OP is a valid Alpha comparison operator.  Here we know which
@@ -390,17 +667,37 @@ alpha_comparison_operator (op, mode)
 	  || (mode == DImode && (code == LEU || code == LTU)));
 }
 
+/* Return 1 if OP is a valid Alpha swapped comparison operator.  */
+
+int
+alpha_swapped_comparison_operator (op, mode)
+     register rtx op;
+     enum machine_mode mode;
+{
+  enum rtx_code code = GET_CODE (op);
+
+  if (mode != GET_MODE (op) || GET_RTX_CLASS (code) != '<')
+    return 0;
+
+  code = swap_condition (code);
+  return (code == EQ || code == LE || code == LT
+	  || (mode == DImode && (code == LEU || code == LTU)));
+}
+
 /* Return 1 if OP is a signed comparison operation.  */
 
 int
 signed_comparison_operator (op, mode)
      register rtx op;
-     enum machine_mode mode;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   switch (GET_CODE (op))
     {
     case EQ:  case NE:  case LE:  case LT:  case GE:   case GT:
       return 1;
+
+    default:
+      break;
     }
 
   return 0;
@@ -411,12 +708,15 @@ signed_comparison_operator (op, mode)
 int
 divmod_operator (op, mode)
      register rtx op;
-     enum machine_mode mode;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   switch (GET_CODE (op))
     {
     case DIV:  case MOD:  case UDIV:  case UMOD:
       return 1;
+
+    default:
+      break;
     }
 
   return 0;
@@ -459,10 +759,7 @@ aligned_memory_operand (op, mode)
     op = XEXP (op, 0);
 
   return (GET_CODE (op) == REG
-	  && (REGNO (op) == STACK_POINTER_REGNUM
-	      || op == hard_frame_pointer_rtx
-	      || (REGNO (op) >= FIRST_VIRTUAL_REGISTER
-		  && REGNO (op) <= LAST_VIRTUAL_REGISTER)));
+	  && REGNO_POINTER_ALIGN (REGNO (op)) >= 4);
 }
 
 /* Similar, but return 1 if OP is a MEM which is not alignable.  */
@@ -496,10 +793,17 @@ unaligned_memory_operand (op, mode)
     op = XEXP (op, 0);
 
   return (GET_CODE (op) != REG
-	  || (REGNO (op) != STACK_POINTER_REGNUM
-	      && op != hard_frame_pointer_rtx
-	      && (REGNO (op) < FIRST_VIRTUAL_REGISTER
-		  || REGNO (op) > LAST_VIRTUAL_REGISTER)));
+	  || REGNO_POINTER_ALIGN (REGNO (op)) < 4);
+}
+
+/* Return 1 if OP is either a register or an unaligned memory location.  */
+
+int
+reg_or_unaligned_mem_operand (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return register_operand (op, mode) || unaligned_memory_operand (op, mode);
 }
 
 /* Return 1 if OP is any memory location.  During reload a pseudo matches.  */
@@ -507,7 +811,7 @@ unaligned_memory_operand (op, mode)
 int
 any_memory_operand (op, mode)
      register rtx op;
-     enum machine_mode mode;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
 {
   return (GET_CODE (op) == MEM
 	  || (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
@@ -518,6 +822,17 @@ any_memory_operand (op, mode)
 	      && REGNO (SUBREG_REG (op)) >= FIRST_PSEUDO_REGISTER));
 }
 
+/* Return 1 if this function can directly return via $26.  */
+
+int
+direct_return ()
+{
+  return (! TARGET_OPEN_VMS && reload_completed && alpha_sa_size () == 0
+	  && get_frame_size () == 0
+	  && current_function_outgoing_args_size == 0
+	  && current_function_pretend_args_size == 0);
+}
+
 /* REF is an alignable memory location.  Place an aligned SImode
    reference into *PALIGNED_MEM and the number of bits to shift into
    *PBITNUM.  */
@@ -551,7 +866,7 @@ get_aligned_mem (ref, paligned_mem, pbitnum)
   if (GET_CODE (base) == PLUS)
     offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
 
-  *paligned_mem = gen_rtx (MEM, SImode,
+  *paligned_mem = gen_rtx_MEM (SImode,
 			   plus_constant (base, offset & ~3));
   MEM_IN_STRUCT_P (*paligned_mem) = MEM_IN_STRUCT_P (ref);
   MEM_VOLATILE_P (*paligned_mem) = MEM_VOLATILE_P (ref);
@@ -560,11 +875,13 @@ get_aligned_mem (ref, paligned_mem, pbitnum)
   *pbitnum = GEN_INT ((offset & 3) * 8);
 }
 
-/* Similar, but just get the address.  Handle the two reload cases.  */
+/* Similar, but just get the address.  Handle the two reload cases.  
+   Add EXTRA_OFFSET to the address we return.  */
 
 rtx
-get_unaligned_address (ref)
+get_unaligned_address (ref, extra_offset)
      rtx ref;
+     int extra_offset;
 {
   rtx base;
   HOST_WIDE_INT offset = 0;
@@ -590,7 +907,7 @@ get_unaligned_address (ref)
   if (GET_CODE (base) == PLUS)
     offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
 
-  return plus_constant (base, offset);
+  return plus_constant (base, offset + extra_offset);
 }
 
 /* Subfunction of the following function.  Update the flags of any MEM
@@ -629,6 +946,9 @@ alpha_set_memflags_1 (x, in_struct_p, volatile_p, unchanging_p)
       MEM_VOLATILE_P (x) = volatile_p;
       RTX_UNCHANGING_P (x) = unchanging_p;
       break;
+
+    default:
+      break;
     }
 }
 
@@ -669,6 +989,26 @@ alpha_emit_set_const (target, mode, c, n)
      HOST_WIDE_INT c;
      int n;
 {
+  rtx pat;
+  int i;
+
+  /* Try 1 insn, then 2, then up to N. */
+  for (i = 1; i <= n; i++)
+    if ((pat = alpha_emit_set_const_1 (target, mode, c, i)) != 0)
+      return pat;
+
+  return 0;
+}
+
+/* Internal routine for the above to check for N or below insns.  */
+
+static rtx
+alpha_emit_set_const_1 (target, mode, c, n)
+     rtx target;
+     enum machine_mode mode;
+     HOST_WIDE_INT c;
+     int n;
+{
   HOST_WIDE_INT new = c;
   int i, bits;
   /* Use a pseudo if highly optimizing and still generating RTL.  */
@@ -688,12 +1028,10 @@ alpha_emit_set_const (target, mode, c, n)
 
   /* If this is a sign-extended 32-bit constant, we can do this in at most
      three insns, so do it if we have enough insns left.  We always have
-     a sign-extended 32-bit constant when compiling on a narrow machine. 
-     Note that we cannot handle the constant 0x80000000.  */
+     a sign-extended 32-bit constant when compiling on a narrow machine.   */
 
-  if ((HOST_BITS_PER_WIDE_INT != 64
-       || c >> 31 == -1 || c >> 31 == 0)
-      && c != 0x80000000U)
+  if (HOST_BITS_PER_WIDE_INT != 64
+      || c >> 31 == -1 || c >> 31 == 0)
     {
       HOST_WIDE_INT low = (c & 0xffff) - 2 * (c & 0x8000);
       HOST_WIDE_INT tmp1 = c - low;
@@ -712,13 +1050,19 @@ alpha_emit_set_const (target, mode, c, n)
 	}
 
       if (c == low || (low == 0 && extra == 0))
-	return copy_to_suggested_reg (GEN_INT (c), target, mode);
-      else if (n >= 2 + (extra != 0)
-	       /* We can't do this when SImode if HIGH required adjustment.
-		  This is because the code relies on an implicit overflow
-		  which is invisible to the RTL.  We can thus get incorrect
-		  code if the two ldah instructions are combined.  */
-	       && ! (mode == SImode && extra != 0))
+	{
+	  /* We used to use copy_to_suggested_reg (GEN_INT (c), target, mode)
+	     but that meant that we can't handle INT_MIN on 32-bit machines
+	     (like NT/Alpha), because we recurse indefinitely through 
+	     emit_move_insn to gen_movdi.  So instead, since we know exactly
+	     what we want, create it explicitly.  */
+
+	  if (target == NULL)
+	    target = gen_reg_rtx (mode);
+	  emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (c)));
+	  return target;
+	}
+      else if (n >= 2 + (extra != 0))
 	{
 	  temp = copy_to_suggested_reg (GEN_INT (low), subtarget, mode);
 
@@ -795,9 +1139,11 @@ alpha_emit_set_const (target, mode, c, n)
       /* Now try high-order zero bits.  Here we try the shifted-in bits as
 	 all zero and all ones.  Be careful to avoid shifting outside the
 	 mode and to avoid shifting outside the host wide int size.  */
+      /* On narrow hosts, don't shift a 1 into the high bit, since we'll
+	 confuse the recursive call and set all of the high 32 bits.  */
 
       if ((bits = (MIN (HOST_BITS_PER_WIDE_INT, GET_MODE_SIZE (mode) * 8)
-		   - floor_log2 (c) - 1)) > 0)
+		   - floor_log2 (c) - 1 - (HOST_BITS_PER_WIDE_INT < 64))) > 0)
 	for (; bits > 0; bits--)
 	  if ((temp = alpha_emit_set_const (subtarget, mode,
 					    c << bits, i)) != 0
@@ -829,6 +1175,1077 @@ alpha_emit_set_const (target, mode, c, n)
 
   return 0;
 }
+
+#if HOST_BITS_PER_WIDE_INT == 64
+/* Having failed to find a 3 insn sequence in alpha_emit_set_const,
+   fall back to a straight forward decomposition.  We do this to avoid
+   exponential run times encountered when looking for longer sequences
+   with alpha_emit_set_const.  */
+
+rtx
+alpha_emit_set_long_const (target, c)
+     rtx target;
+     HOST_WIDE_INT c;
+{
+  /* Use a pseudo if highly optimizing and still generating RTL.  */
+  rtx subtarget
+    = (flag_expensive_optimizations && rtx_equal_function_value_matters
+       ? 0 : target);
+  HOST_WIDE_INT d1, d2, d3, d4;
+  rtx r1, r2;
+
+  /* Decompose the entire word */
+  d1 = ((c & 0xffff) ^ 0x8000) - 0x8000;
+  c -= d1;
+  d2 = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
+  c = (c - d2) >> 32;
+  d3 = ((c & 0xffff) ^ 0x8000) - 0x8000;
+  c -= d3;
+  d4 = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
+
+  if (c - d4 != 0)
+    abort();
+
+  /* Construct the high word */
+  if (d3 == 0)
+    r1 = copy_to_suggested_reg (GEN_INT (d4), subtarget, DImode);
+  else if (d4 == 0)
+    r1 = copy_to_suggested_reg (GEN_INT (d3), subtarget, DImode);
+  else
+    r1 = expand_binop (DImode, add_optab, GEN_INT (d3), GEN_INT (d4),
+		       subtarget, 0, OPTAB_WIDEN);
+
+  /* Shift it into place */
+  r2 = expand_binop (DImode, ashl_optab, r1, GEN_INT (32), 
+		     subtarget, 0, OPTAB_WIDEN);
+
+  if (subtarget == 0 && d1 == d3 && d2 == d4)
+    r1 = expand_binop (DImode, add_optab, r1, r2, subtarget, 0, OPTAB_WIDEN);
+  else
+    {
+      r1 = r2;
+
+      /* Add in the low word */
+      if (d2 != 0)
+	r1 = expand_binop (DImode, add_optab, r1, GEN_INT (d2),
+		           subtarget, 0, OPTAB_WIDEN);
+      if (d1 != 0)
+	r1 = expand_binop (DImode, add_optab, r1, GEN_INT (d1),
+		           subtarget, 0, OPTAB_WIDEN);
+    }
+
+  if (subtarget == 0)
+    r1 = copy_to_suggested_reg(r1, target, DImode);
+
+  return r1;
+}
+#endif /* HOST_BITS_PER_WIDE_INT == 64 */
+
+/* Generate the comparison for a conditional branch.  */
+
+rtx
+alpha_emit_conditional_branch (code)
+     enum rtx_code code;
+{
+  enum rtx_code cmp_code, branch_code;
+  enum machine_mode cmp_mode, branch_mode = VOIDmode;
+  rtx op0 = alpha_compare_op0, op1 = alpha_compare_op1;
+  rtx tem;
+
+  /* The general case: fold the comparison code to the types of compares
+     that we have, choosing the branch as necessary.  */
+  switch (code)
+    {
+    case EQ:  case LE:  case LT:  case LEU:  case LTU:
+      /* We have these compares: */
+      cmp_code = code, branch_code = NE;
+      break;
+
+    case NE:
+      /* This must be reversed. */
+      cmp_code = EQ, branch_code = EQ;
+      break;
+
+    case GE:  case GT: case GEU:  case GTU:
+      /* For FP, we swap them, for INT, we reverse them.  */
+      if (alpha_compare_fp_p)
+	{
+	  cmp_code = swap_condition (code);
+	  branch_code = NE;
+	  tem = op0, op0 = op1, op1 = tem;
+	}
+      else
+	{
+	  cmp_code = reverse_condition (code);
+	  branch_code = EQ;
+	}
+      break;
+
+    default:
+      abort ();
+    }
+
+  if (alpha_compare_fp_p)
+    {
+      cmp_mode = DFmode;
+      if (flag_fast_math)
+	{
+	  /* When we are not as concerned about non-finite values, and we
+	     are comparing against zero, we can branch directly.  */
+	  if (op1 == CONST0_RTX (DFmode))
+	    cmp_code = NIL, branch_code = code;
+	  else if (op0 == CONST0_RTX (DFmode))
+	    {
+	      /* Undo the swap we probably did just above.  */
+	      tem = op0, op0 = op1, op1 = tem;
+	      branch_code = swap_condition (cmp_code);
+	      cmp_code = NIL;
+	    }
+	}
+      else
+	{
+	  /* ??? We mark the the branch mode to be CCmode to prevent the
+	     compare and branch from being combined, since the compare 
+	     insn follows IEEE rules that the branch does not.  */
+	  branch_mode = CCmode;
+	}
+    }
+  else
+    {
+      cmp_mode = DImode;
+
+      /* The following optimizations are only for signed compares.  */
+      if (code != LEU && code != LTU && code != GEU && code != GTU)
+	{
+	  /* Whee.  Compare and branch against 0 directly.  */
+	  if (op1 == const0_rtx)
+	    cmp_code = NIL, branch_code = code;
+
+	  /* We want to use cmpcc/bcc when we can, since there is a zero delay
+	     bypass between logicals and br/cmov on EV5.  But we don't want to
+	     force valid immediate constants into registers needlessly.  */
+	  else if (GET_CODE (op1) == CONST_INT)
+	    {
+	      HOST_WIDE_INT v = INTVAL (op1), n = -v;
+
+	      if (! CONST_OK_FOR_LETTER_P (v, 'I')
+		  && (CONST_OK_FOR_LETTER_P (n, 'K')
+		      || CONST_OK_FOR_LETTER_P (n, 'L')))
+		{
+		  cmp_code = PLUS, branch_code = code;
+		  op1 = GEN_INT (n);
+		}
+	    }
+	}
+    }
+
+  /* Force op0 into a register.  */
+  if (GET_CODE (op0) != REG)
+    op0 = force_reg (cmp_mode, op0);
+
+  /* Emit an initial compare instruction, if necessary.  */
+  tem = op0;
+  if (cmp_code != NIL)
+    {
+      tem = gen_reg_rtx (cmp_mode);
+      emit_move_insn (tem, gen_rtx_fmt_ee (cmp_code, cmp_mode, op0, op1));
+    }
+
+  /* Return the branch comparison.  */
+  return gen_rtx_fmt_ee (branch_code, branch_mode, tem, CONST0_RTX (cmp_mode));
+}
+
+
+/* Rewrite a comparison against zero CMP of the form
+   (CODE (cc0) (const_int 0)) so it can be written validly in
+   a conditional move (if_then_else CMP ...).
+   If both of the operands that set cc0 are non-zero we must emit
+   an insn to perform the compare (it can't be done within
+   the conditional move). */
+rtx
+alpha_emit_conditional_move (cmp, mode)
+     rtx cmp;
+     enum machine_mode mode;
+{
+  enum rtx_code code = GET_CODE (cmp);
+  enum rtx_code cmov_code = NE;
+  rtx op0 = alpha_compare_op0;
+  rtx op1 = alpha_compare_op1;
+  enum machine_mode cmp_mode
+    = (GET_MODE (op0) == VOIDmode ? DImode : GET_MODE (op0));
+  enum machine_mode cmp_op_mode = alpha_compare_fp_p ? DFmode : DImode;
+  enum machine_mode cmov_mode = VOIDmode;
+  rtx tem;
+
+  if (alpha_compare_fp_p != FLOAT_MODE_P (mode))
+    return 0;
+
+  /* We may be able to use a conditional move directly.
+     This avoids emitting spurious compares. */
+  if (signed_comparison_operator (cmp, cmp_op_mode)
+      && (!alpha_compare_fp_p || flag_fast_math)
+      && (op0 == CONST0_RTX (cmp_mode) || op1 == CONST0_RTX (cmp_mode)))
+    return gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
+
+  /* We can't put the comparison insides a conditional move;
+     emit a compare instruction and put that inside the
+     conditional move.  Make sure we emit only comparisons we have;
+     swap or reverse as necessary.  */
+
+  switch (code)
+    {
+    case EQ:  case LE:  case LT:  case LEU:  case LTU:
+      /* We have these compares: */
+      break;
+
+    case NE:
+      /* This must be reversed. */
+      code = reverse_condition (code);
+      cmov_code = EQ;
+      break;
+
+    case GE:  case GT:  case GEU:  case GTU:
+      /* These must be swapped.  Make sure the new first operand is in
+	 a register.  */
+      code = swap_condition (code);
+      tem = op0, op0 = op1, op1 = tem;
+      op0 = force_reg (cmp_mode, op0);
+      break;
+
+    default:
+      abort ();
+    }
+
+  /* ??? We mark the the branch mode to be CCmode to prevent the compare
+     and cmov from being combined, since the compare insn follows IEEE
+     rules that the cmov does not.  */
+  if (alpha_compare_fp_p && !flag_fast_math)
+    cmov_mode = CCmode;
+
+  tem = gen_reg_rtx (cmp_op_mode);
+  emit_move_insn (tem, gen_rtx_fmt_ee (code, cmp_op_mode, op0, op1));
+  return gen_rtx_fmt_ee (cmov_code, cmov_mode, tem, CONST0_RTX (cmp_op_mode));
+}
+
+/* Use ext[wlq][lh] as the Architecture Handbook describes for extracting
+   unaligned data:
+
+           unsigned:                       signed:
+   word:   ldq_u  r1,X(r11)                ldq_u  r1,X(r11)
+           ldq_u  r2,X+1(r11)              ldq_u  r2,X+1(r11)
+           lda    r3,X(r11)                lda    r3,X+2(r11)
+           extwl  r1,r3,r1                 extql  r1,r3,r1
+           extwh  r2,r3,r2                 extqh  r2,r3,r2
+           or     r1.r2.r1                 or     r1,r2,r1
+                                           sra    r1,48,r1
+
+   long:   ldq_u  r1,X(r11)                ldq_u  r1,X(r11)
+           ldq_u  r2,X+3(r11)              ldq_u  r2,X+3(r11)
+           lda    r3,X(r11)                lda    r3,X(r11)
+           extll  r1,r3,r1                 extll  r1,r3,r1
+           extlh  r2,r3,r2                 extlh  r2,r3,r2
+           or     r1.r2.r1                 addl   r1,r2,r1
+
+   quad:   ldq_u  r1,X(r11)
+           ldq_u  r2,X+7(r11)
+           lda    r3,X(r11)
+           extql  r1,r3,r1
+           extqh  r2,r3,r2
+           or     r1.r2.r1
+*/
+
+void
+alpha_expand_unaligned_load (tgt, mem, size, ofs, sign)
+     rtx tgt, mem;
+     HOST_WIDE_INT size, ofs;
+     int sign;
+{
+  rtx meml, memh, addr, extl, exth;
+  enum machine_mode mode;
+
+  meml = gen_reg_rtx (DImode);
+  memh = gen_reg_rtx (DImode);
+  addr = gen_reg_rtx (DImode);
+  extl = gen_reg_rtx (DImode);
+  exth = gen_reg_rtx (DImode);
+
+  emit_move_insn (meml,
+		  change_address (mem, DImode,
+				  gen_rtx_AND (DImode, 
+					       plus_constant (XEXP (mem, 0),
+							      ofs),
+					       GEN_INT (-8))));
+
+  emit_move_insn (memh,
+		  change_address (mem, DImode,
+				  gen_rtx_AND (DImode, 
+					       plus_constant (XEXP (mem, 0),
+							      ofs + size - 1),
+					       GEN_INT (-8))));
+
+  if (sign && size == 2)
+    {
+      emit_move_insn (addr, plus_constant (XEXP (mem, 0), ofs+2));
+
+      emit_insn (gen_extxl (extl, meml, GEN_INT (64), addr));
+      emit_insn (gen_extqh (exth, memh, addr));
+
+      /* We must use tgt here for the target.  Alpha-vms port fails if we use
+	 addr for the target, because addr is marked as a pointer and combine
+	 knows that pointers are always sign-extended 32 bit values.  */
+      addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
+      addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (48), 
+			   addr, 1, OPTAB_WIDEN);
+    }
+  else
+    {
+      emit_move_insn (addr, plus_constant (XEXP (mem, 0), ofs));
+      emit_insn (gen_extxl (extl, meml, GEN_INT (size*8), addr));
+      switch (size)
+	{
+	case 2:
+	  emit_insn (gen_extwh (exth, memh, addr));
+	  mode = HImode;
+	  break;
+
+	case 4:
+	  emit_insn (gen_extlh (exth, memh, addr));
+	  mode = SImode;
+	  break;
+
+	case 8:
+	  emit_insn (gen_extqh (exth, memh, addr));
+	  mode = DImode;
+	  break;
+	}
+
+      addr = expand_binop (mode, ior_optab, gen_lowpart (mode, extl),
+			   gen_lowpart (mode, exth), gen_lowpart (mode, tgt),
+			   sign, OPTAB_WIDEN);
+    }
+
+  if (addr != tgt)
+    emit_move_insn (tgt, gen_lowpart(GET_MODE (tgt), addr));
+}
+
+/* Similarly, use ins and msk instructions to perform unaligned stores.  */
+
+void
+alpha_expand_unaligned_store (dst, src, size, ofs)
+     rtx dst, src;
+     HOST_WIDE_INT size, ofs;
+{
+  rtx dstl, dsth, addr, insl, insh, meml, memh;
+  
+  dstl = gen_reg_rtx (DImode);
+  dsth = gen_reg_rtx (DImode);
+  insl = gen_reg_rtx (DImode);
+  insh = gen_reg_rtx (DImode);
+
+  meml = change_address (dst, DImode,
+			 gen_rtx_AND (DImode, 
+				      plus_constant (XEXP (dst, 0), ofs),
+				      GEN_INT (-8)));
+  memh = change_address (dst, DImode,
+			 gen_rtx_AND (DImode, 
+				      plus_constant (XEXP (dst, 0),
+						     ofs+size-1),
+				      GEN_INT (-8)));
+
+  emit_move_insn (dsth, memh);
+  emit_move_insn (dstl, meml);
+  addr = copy_addr_to_reg (plus_constant (XEXP (dst, 0), ofs));
+
+  if (src != const0_rtx)
+    {
+      emit_insn (gen_insxh (insh, gen_lowpart (DImode, src),
+			    GEN_INT (size*8), addr));
+
+      switch (size)
+	{
+	case 2:
+	  emit_insn (gen_inswl (insl, gen_lowpart (HImode, src), addr));
+	  break;
+	case 4:
+	  emit_insn (gen_insll (insl, gen_lowpart (SImode, src), addr));
+	  break;
+	case 8:
+	  emit_insn (gen_insql (insl, src, addr));
+	  break;
+	}
+    }
+
+  emit_insn (gen_mskxh (dsth, dsth, GEN_INT (size*8), addr));
+
+  switch (size)
+    {
+    case 2:
+      emit_insn (gen_mskxl (dstl, dstl, GEN_INT (0xffff), addr));
+      break;
+    case 4:
+      emit_insn (gen_mskxl (dstl, dstl, GEN_INT (0xffffffff), addr));
+      break;
+    case 8:
+      {
+#if HOST_BITS_PER_WIDE_INT == 32
+	rtx msk = immed_double_const (0xffffffff, 0xffffffff, DImode);
+#else
+	rtx msk = immed_double_const (0xffffffffffffffff, 0, DImode);
+#endif
+	emit_insn (gen_mskxl (dstl, dstl, msk, addr));
+      }
+      break;
+    }
+
+  if (src != const0_rtx)
+    {
+      dsth = expand_binop (DImode, ior_optab, insh, dsth, dsth, 0, OPTAB_WIDEN);
+      dstl = expand_binop (DImode, ior_optab, insl, dstl, dstl, 0, OPTAB_WIDEN);
+    }
+  
+  /* Must store high before low for degenerate case of aligned.  */
+  emit_move_insn (memh, dsth);
+  emit_move_insn (meml, dstl);
+}
+
+/* The block move code tries to maximize speed by separating loads and
+   stores at the expense of register pressure: we load all of the data
+   before we store it back out.  There are two secondary effects worth
+   mentioning, that this speeds copying to/from aligned and unaligned
+   buffers, and that it makes the code significantly easier to write.  */
+
+#define MAX_MOVE_WORDS	8
+
+/* Load an integral number of consecutive unaligned quadwords.  */
+
+static void
+alpha_expand_unaligned_load_words (out_regs, smem, words, ofs)
+     rtx *out_regs;
+     rtx smem;
+     HOST_WIDE_INT words, ofs;
+{
+  rtx const im8 = GEN_INT (-8);
+  rtx const i64 = GEN_INT (64);
+  rtx ext_tmps[MAX_MOVE_WORDS], data_regs[MAX_MOVE_WORDS+1];
+  rtx sreg, areg;
+  HOST_WIDE_INT i;
+
+  /* Generate all the tmp registers we need.  */
+  for (i = 0; i < words; ++i)
+    {
+      data_regs[i] = out_regs[i];
+      ext_tmps[i] = gen_reg_rtx (DImode);
+    }
+  data_regs[words] = gen_reg_rtx (DImode);
+
+  if (ofs != 0)
+    smem = change_address (smem, GET_MODE (smem),
+			   plus_constant (XEXP (smem, 0), ofs));
+  
+  /* Load up all of the source data.  */
+  for (i = 0; i < words; ++i)
+    {
+      emit_move_insn (data_regs[i],
+		      change_address (smem, DImode,
+				      gen_rtx_AND (DImode,
+						   plus_constant (XEXP(smem,0),
+								  8*i),
+						   im8)));
+    }
+  emit_move_insn (data_regs[words],
+		  change_address (smem, DImode,
+				  gen_rtx_AND (DImode,
+					       plus_constant (XEXP(smem,0),
+							      8*words - 1),
+					       im8)));
+
+  /* Extract the half-word fragments.  Unfortunately DEC decided to make
+     extxh with offset zero a noop instead of zeroing the register, so 
+     we must take care of that edge condition ourselves with cmov.  */
+
+  sreg = copy_addr_to_reg (XEXP (smem, 0));
+  areg = expand_binop (DImode, and_optab, sreg, GEN_INT (7), NULL, 
+		       1, OPTAB_WIDEN);
+  for (i = 0; i < words; ++i)
+    {
+      emit_insn (gen_extxl (data_regs[i], data_regs[i], i64, sreg));
+
+      emit_insn (gen_extqh (ext_tmps[i], data_regs[i+1], sreg));
+      emit_insn (gen_rtx_SET (VOIDmode, ext_tmps[i],
+			      gen_rtx_IF_THEN_ELSE (DImode,
+						    gen_rtx_EQ (DImode, areg,
+								const0_rtx),
+						    const0_rtx, ext_tmps[i])));
+    }
+
+  /* Merge the half-words into whole words.  */
+  for (i = 0; i < words; ++i)
+    {
+      out_regs[i] = expand_binop (DImode, ior_optab, data_regs[i],
+				  ext_tmps[i], data_regs[i], 1, OPTAB_WIDEN);
+    }
+}
+
+/* Store an integral number of consecutive unaligned quadwords.  DATA_REGS
+   may be NULL to store zeros.  */
+
+static void
+alpha_expand_unaligned_store_words (data_regs, dmem, words, ofs)
+     rtx *data_regs;
+     rtx dmem;
+     HOST_WIDE_INT words, ofs;
+{
+  rtx const im8 = GEN_INT (-8);
+  rtx const i64 = GEN_INT (64);
+#if HOST_BITS_PER_WIDE_INT == 32
+  rtx const im1 = immed_double_const (0xffffffff, 0xffffffff, DImode);
+#else
+  rtx const im1 = immed_double_const (0xffffffffffffffff, 0, DImode);
+#endif
+  rtx ins_tmps[MAX_MOVE_WORDS];
+  rtx st_tmp_1, st_tmp_2, dreg;
+  rtx st_addr_1, st_addr_2;
+  HOST_WIDE_INT i;
+
+  /* Generate all the tmp registers we need.  */
+  if (data_regs != NULL)
+    for (i = 0; i < words; ++i)
+      ins_tmps[i] = gen_reg_rtx(DImode);
+  st_tmp_1 = gen_reg_rtx(DImode);
+  st_tmp_2 = gen_reg_rtx(DImode);
+  
+  if (ofs != 0)
+    dmem = change_address (dmem, GET_MODE (dmem),
+			   plus_constant (XEXP (dmem, 0), ofs));
+  
+
+  st_addr_2 = change_address (dmem, DImode,
+			      gen_rtx_AND (DImode,
+					   plus_constant (XEXP(dmem,0),
+							  words*8 - 1),
+				       im8));
+  st_addr_1 = change_address (dmem, DImode,
+			      gen_rtx_AND (DImode, 
+					   XEXP (dmem, 0),
+					   im8));
+
+  /* Load up the destination end bits.  */
+  emit_move_insn (st_tmp_2, st_addr_2);
+  emit_move_insn (st_tmp_1, st_addr_1);
+
+  /* Shift the input data into place.  */
+  dreg = copy_addr_to_reg (XEXP (dmem, 0));
+  if (data_regs != NULL)
+    {
+      for (i = words-1; i >= 0; --i)
+	{
+	  emit_insn (gen_insxh (ins_tmps[i], data_regs[i], i64, dreg));
+	  emit_insn (gen_insql (data_regs[i], data_regs[i], dreg));
+	}
+      for (i = words-1; i > 0; --i)
+	{
+	  ins_tmps[i-1] = expand_binop (DImode, ior_optab, data_regs[i],
+					ins_tmps[i-1], ins_tmps[i-1], 1,
+					OPTAB_WIDEN);
+	}
+    }
+
+  /* Split and merge the ends with the destination data.  */
+  emit_insn (gen_mskxh (st_tmp_2, st_tmp_2, i64, dreg));
+  emit_insn (gen_mskxl (st_tmp_1, st_tmp_1, im1, dreg));
+
+  if (data_regs != NULL)
+    {
+      st_tmp_2 = expand_binop (DImode, ior_optab, st_tmp_2, ins_tmps[words-1],
+			       st_tmp_2, 1, OPTAB_WIDEN);
+      st_tmp_1 = expand_binop (DImode, ior_optab, st_tmp_1, data_regs[0],
+			       st_tmp_1, 1, OPTAB_WIDEN);
+    }
+
+  /* Store it all.  */
+  emit_move_insn (st_addr_2, st_tmp_2);
+  for (i = words-1; i > 0; --i)
+    {
+      emit_move_insn (change_address (dmem, DImode,
+				      gen_rtx_AND (DImode,
+						   plus_constant(XEXP (dmem,0),
+								 i*8),
+					       im8)),
+		      data_regs ? ins_tmps[i-1] : const0_rtx);
+    }
+  emit_move_insn (st_addr_1, st_tmp_1);
+}
+
+
+/* Expand string/block move operations.
+
+   operands[0] is the pointer to the destination.
+   operands[1] is the pointer to the source.
+   operands[2] is the number of bytes to move.
+   operands[3] is the alignment.  */
+
+int
+alpha_expand_block_move (operands)
+     rtx operands[];
+{
+  rtx bytes_rtx	= operands[2];
+  rtx align_rtx = operands[3];
+  HOST_WIDE_INT bytes = INTVAL (bytes_rtx);
+  HOST_WIDE_INT src_align = INTVAL (align_rtx);
+  HOST_WIDE_INT dst_align = src_align;
+  rtx orig_src	= operands[1];
+  rtx orig_dst	= operands[0];
+  rtx data_regs[2*MAX_MOVE_WORDS+16];
+  rtx tmp;
+  int i, words, ofs, nregs = 0;
+  
+  if (bytes <= 0)
+    return 1;
+  if (bytes > MAX_MOVE_WORDS*8)
+    return 0;
+
+  /* Look for additional alignment information from recorded register info.  */
+
+  tmp = XEXP (orig_src, 0);
+  if (GET_CODE (tmp) == REG)
+    {
+      if (REGNO_POINTER_ALIGN (REGNO (tmp)) > src_align)
+	src_align = REGNO_POINTER_ALIGN (REGNO (tmp));
+    }
+  else if (GET_CODE (tmp) == PLUS
+	   && GET_CODE (XEXP (tmp, 0)) == REG
+	   && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
+    {
+      HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
+      int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
+
+      if (a > src_align)
+	{
+          if (a >= 8 && c % 8 == 0)
+	    src_align = 8;
+          else if (a >= 4 && c % 4 == 0)
+	    src_align = 4;
+          else if (a >= 2 && c % 2 == 0)
+	    src_align = 2;
+	}
+    }
+	
+  tmp = XEXP (orig_dst, 0);
+  if (GET_CODE (tmp) == REG)
+    {
+      if (REGNO_POINTER_ALIGN (REGNO (tmp)) > dst_align)
+	dst_align = REGNO_POINTER_ALIGN (REGNO (tmp));
+    }
+  else if (GET_CODE (tmp) == PLUS
+	   && GET_CODE (XEXP (tmp, 0)) == REG
+	   && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
+    {
+      HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
+      int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
+
+      if (a > dst_align)
+	{
+          if (a >= 8 && c % 8 == 0)
+	    dst_align = 8;
+          else if (a >= 4 && c % 4 == 0)
+	    dst_align = 4;
+          else if (a >= 2 && c % 2 == 0)
+	    dst_align = 2;
+	}
+    }
+
+  /*
+   * Load the entire block into registers.
+   */
+
+  if (GET_CODE (XEXP (orig_src, 0)) == ADDRESSOF)
+    {
+      enum machine_mode mode;
+      tmp = XEXP (XEXP (orig_src, 0), 0);
+
+      mode = mode_for_size (bytes, MODE_INT, 1);
+      if (mode != BLKmode
+	  && GET_MODE_SIZE (GET_MODE (tmp)) <= bytes)
+	{
+	  /* Whee!  Optimize the load to use the existing register.  */
+	  data_regs[nregs++] = gen_lowpart (mode, tmp);
+	  goto src_done;
+	}
+
+      /* ??? We could potentially be copying 3 bytes or whatnot from
+	 a wider reg.  Probably not worth worrying about.  */
+      /* No appropriate mode; fall back on memory.  */
+      orig_src = change_address (orig_src, GET_MODE (orig_src),
+				 copy_addr_to_reg (XEXP (orig_src, 0)));
+    }
+
+  ofs = 0;
+  if (src_align >= 8 && bytes >= 8)
+    {
+      words = bytes / 8;
+
+      for (i = 0; i < words; ++i)
+	data_regs[nregs+i] = gen_reg_rtx(DImode);
+
+      for (i = 0; i < words; ++i)
+	{
+	  emit_move_insn (data_regs[nregs+i],
+			  change_address(orig_src, DImode,
+					 plus_constant (XEXP (orig_src, 0),
+							ofs + i*8)));
+	}
+
+      nregs += words;
+      bytes -= words * 8;
+      ofs += words * 8;
+    }
+  if (src_align >= 4 && bytes >= 4)
+    {
+      words = bytes / 4;
+
+      for (i = 0; i < words; ++i)
+	data_regs[nregs+i] = gen_reg_rtx(SImode);
+
+      for (i = 0; i < words; ++i)
+	{
+	  emit_move_insn (data_regs[nregs+i],
+			  change_address(orig_src, SImode,
+					 plus_constant (XEXP (orig_src, 0),
+							ofs + i*4)));
+	}
+
+      nregs += words;
+      bytes -= words * 4;
+      ofs += words * 4;
+    }
+  if (bytes >= 16)
+    {
+      words = bytes / 8;
+
+      for (i = 0; i < words+1; ++i)
+	data_regs[nregs+i] = gen_reg_rtx(DImode);
+
+      alpha_expand_unaligned_load_words(data_regs+nregs, orig_src, words, ofs);
+
+      nregs += words;
+      bytes -= words * 8;
+      ofs += words * 8;
+    }
+  if (!TARGET_BWX && bytes >= 8)
+    {
+      data_regs[nregs++] = tmp = gen_reg_rtx (DImode);
+      alpha_expand_unaligned_load (tmp, orig_src, 8, ofs, 0);
+      bytes -= 8;
+      ofs += 8;
+    }
+  if (!TARGET_BWX && bytes >= 4)
+    {
+      data_regs[nregs++] = tmp = gen_reg_rtx (SImode);
+      alpha_expand_unaligned_load (tmp, orig_src, 4, ofs, 0);
+      bytes -= 4;
+      ofs += 4;
+    }
+  if (bytes >= 2)
+    {
+      if (src_align >= 2)
+	{
+	  do {
+	    data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
+	    emit_move_insn (tmp,
+			    change_address (orig_src, HImode,
+					    plus_constant (XEXP (orig_src, 0),
+							   ofs)));
+	    bytes -= 2;
+	    ofs += 2;
+	  } while (bytes >= 2);
+	}
+      else if (!TARGET_BWX)
+	{
+	  data_regs[nregs++] = tmp = gen_reg_rtx (HImode);
+	  alpha_expand_unaligned_load (tmp, orig_src, 2, ofs, 0);
+	  bytes -= 2;
+	  ofs += 2;
+	}
+    }
+  while (bytes > 0)
+    {
+      data_regs[nregs++] = tmp = gen_reg_rtx (QImode);
+      emit_move_insn (tmp,
+		      change_address (orig_src, QImode,
+				      plus_constant (XEXP (orig_src, 0),
+						     ofs)));
+      bytes -= 1;
+      ofs += 1;
+    }
+ src_done:
+
+  if (nregs > sizeof(data_regs)/sizeof(*data_regs))
+    abort();
+
+  /*
+   * Now save it back out again.
+   */
+
+  i = 0, ofs = 0;
+
+  if (GET_CODE (XEXP (orig_dst, 0)) == ADDRESSOF)
+    {
+      enum machine_mode mode;
+      tmp = XEXP (XEXP (orig_dst, 0), 0);
+
+      mode = mode_for_size (bytes, MODE_INT, 1);
+      if (GET_MODE (tmp) == mode && nregs == 1)
+	{
+	  emit_move_insn (tmp, data_regs[0]);
+	  i = 1;
+	  goto dst_done;
+	}
+
+      /* ??? If nregs > 1, consider reconstructing the word in regs.  */
+      /* ??? Optimize mode < dst_mode with strict_low_part.  */
+      /* No appropriate mode; fall back on memory.  */
+      orig_dst = change_address (orig_dst, GET_MODE (orig_dst),
+				 copy_addr_to_reg (XEXP (orig_dst, 0)));
+    }
+
+  /* Write out the data in whatever chunks reading the source allowed.  */
+  if (dst_align >= 8)
+    {
+      while (i < nregs && GET_MODE (data_regs[i]) == DImode)
+	{
+	  emit_move_insn (change_address(orig_dst, DImode,
+					 plus_constant (XEXP (orig_dst, 0),
+							ofs)),
+			  data_regs[i]);
+	  ofs += 8;
+	  i++;
+	}
+    }
+  if (dst_align >= 4)
+    {
+      /* If the source has remaining DImode regs, write them out in
+	 two pieces.  */
+      while (i < nregs && GET_MODE (data_regs[i]) == DImode)
+	{
+	  tmp = expand_binop (DImode, lshr_optab, data_regs[i], GEN_INT (32),
+			      NULL_RTX, 1, OPTAB_WIDEN);
+
+	  emit_move_insn (change_address(orig_dst, SImode,
+					 plus_constant (XEXP (orig_dst, 0),
+							ofs)),
+			  gen_lowpart (SImode, data_regs[i]));
+	  emit_move_insn (change_address(orig_dst, SImode,
+					 plus_constant (XEXP (orig_dst, 0),
+							ofs+4)),
+			  gen_lowpart (SImode, tmp));
+	  ofs += 8;
+	  i++;
+	}
+
+      while (i < nregs && GET_MODE (data_regs[i]) == SImode)
+	{
+	  emit_move_insn (change_address(orig_dst, SImode,
+					 plus_constant (XEXP (orig_dst, 0),
+							ofs)),
+			  data_regs[i]);
+	  ofs += 4;
+	  i++;
+	}
+    }
+  if (i < nregs && GET_MODE (data_regs[i]) == DImode)
+    {
+      /* Write out a remaining block of words using unaligned methods.  */
+
+      for (words = 1; i+words < nregs ; ++words)
+	if (GET_MODE (data_regs[i+words]) != DImode)
+	  break;
+
+      if (words == 1)
+	alpha_expand_unaligned_store (orig_dst, data_regs[i], 8, ofs);
+      else
+        alpha_expand_unaligned_store_words (data_regs+i, orig_dst, words, ofs);
+     
+      i += words;
+      ofs += words * 8;
+    }
+
+  /* Due to the above, this won't be aligned.  */
+  /* ??? If we have more than one of these, consider constructing full
+     words in registers and using alpha_expand_unaligned_store_words.  */
+  while (i < nregs && GET_MODE (data_regs[i]) == SImode)
+    {
+      alpha_expand_unaligned_store (orig_dst, data_regs[i], 4, ofs);
+      ofs += 4;
+      i++;
+    }
+
+  if (dst_align >= 2)
+    while (i < nregs && GET_MODE (data_regs[i]) == HImode)
+      {
+	emit_move_insn (change_address (orig_dst, HImode,
+					plus_constant (XEXP (orig_dst, 0),
+						       ofs)),
+			data_regs[i]);
+	i++;
+	ofs += 2;
+      }
+  else
+    while (i < nregs && GET_MODE (data_regs[i]) == HImode)
+      {
+	alpha_expand_unaligned_store (orig_dst, data_regs[i], 2, ofs);
+	i++;
+	ofs += 2;
+      }
+  while (i < nregs && GET_MODE (data_regs[i]) == QImode)
+    {
+      emit_move_insn (change_address (orig_dst, QImode,
+				      plus_constant (XEXP (orig_dst, 0),
+						     ofs)),
+		      data_regs[i]);
+      i++;
+      ofs += 1;
+    }
+ dst_done:
+
+  if (i != nregs)
+    abort();
+
+  return 1;
+}
+
+int
+alpha_expand_block_clear (operands)
+     rtx operands[];
+{
+  rtx bytes_rtx	= operands[1];
+  rtx align_rtx = operands[2];
+  HOST_WIDE_INT bytes = INTVAL (bytes_rtx);
+  HOST_WIDE_INT align = INTVAL (align_rtx);
+  rtx orig_dst	= operands[0];
+  rtx tmp;
+  HOST_WIDE_INT i, words, ofs = 0;
+  
+  if (bytes <= 0)
+    return 1;
+  if (bytes > MAX_MOVE_WORDS*8)
+    return 0;
+
+  /* Look for stricter alignment.  */
+
+  tmp = XEXP (orig_dst, 0);
+  if (GET_CODE (tmp) == REG)
+    {
+      if (REGNO_POINTER_ALIGN (REGNO (tmp)) > align)
+	align = REGNO_POINTER_ALIGN (REGNO (tmp));
+    }
+  else if (GET_CODE (tmp) == PLUS
+	   && GET_CODE (XEXP (tmp, 0)) == REG
+	   && GET_CODE (XEXP (tmp, 1)) == CONST_INT)
+    {
+      HOST_WIDE_INT c = INTVAL (XEXP (tmp, 1));
+      int a = REGNO_POINTER_ALIGN (REGNO (XEXP (tmp, 0)));
+
+      if (a > align)
+	{
+          if (a >= 8 && c % 8 == 0)
+	    align = 8;
+          else if (a >= 4 && c % 4 == 0)
+	    align = 4;
+          else if (a >= 2 && c % 2 == 0)
+	    align = 2;
+	}
+    }
+
+  /* Handle a block of contiguous words first.  */
+
+  if (align >= 8 && bytes >= 8)
+    {
+      words = bytes / 8;
+
+      for (i = 0; i < words; ++i)
+	{
+	  emit_move_insn (change_address(orig_dst, DImode,
+					 plus_constant (XEXP (orig_dst, 0),
+							ofs + i*8)),
+			  const0_rtx);
+	}
+
+      bytes -= words * 8;
+      ofs += words * 8;
+    }
+  if (align >= 4 && bytes >= 4)
+    {
+      words = bytes / 4;
+
+      for (i = 0; i < words; ++i)
+	{
+	  emit_move_insn (change_address(orig_dst, SImode,
+					 plus_constant (XEXP (orig_dst, 0),
+							ofs + i*4)),
+			  const0_rtx);
+	}
+
+      bytes -= words * 4;
+      ofs += words * 4;
+    }
+  if (bytes >= 16)
+    {
+      words = bytes / 8;
+
+      alpha_expand_unaligned_store_words (NULL, orig_dst, words, ofs);
+
+      bytes -= words * 8;
+      ofs += words * 8;
+    }
+
+  /* Next clean up any trailing pieces.  We know from the contiguous
+     block move that there are no aligned SImode or DImode hunks left.  */
+
+  if (!TARGET_BWX && bytes >= 8)
+    {
+      alpha_expand_unaligned_store (orig_dst, const0_rtx, 8, ofs);
+      bytes -= 8;
+      ofs += 8;
+    }
+  if (!TARGET_BWX && bytes >= 4)
+    {
+      alpha_expand_unaligned_store (orig_dst, const0_rtx, 4, ofs);
+      bytes -= 4;
+      ofs += 4;
+    }
+  if (bytes >= 2)
+    {
+      if (align >= 2)
+	{
+	  do {
+	    emit_move_insn (change_address (orig_dst, HImode,
+					    plus_constant (XEXP (orig_dst, 0),
+							   ofs)),
+			    const0_rtx);
+	    bytes -= 2;
+	    ofs += 2;
+	  } while (bytes >= 2);
+	}
+      else if (!TARGET_BWX)
+	{
+	  alpha_expand_unaligned_store (orig_dst, const0_rtx, 2, ofs);
+	  bytes -= 2;
+	  ofs += 2;
+	}
+    }
+  while (bytes > 0)
+    {
+      emit_move_insn (change_address (orig_dst, QImode,
+				      plus_constant (XEXP (orig_dst, 0),
+						     ofs)),
+		      const0_rtx);
+      bytes -= 1;
+      ofs += 1;
+    }
+
+  return 1;
+}
+
 
 /* Adjust the cost of a scheduling dependency.  Return the new cost of
    a dependency LINK or INSN on DEP_INSN.  COST is the current cost.  */
@@ -840,7 +2257,8 @@ alpha_adjust_cost (insn, link, dep_insn, cost)
      rtx dep_insn;
      int cost;
 {
-  rtx set;
+  rtx set, set_src;
+  enum attr_type insn_type, dep_insn_type;
 
   /* If the dependence is an anti-dependence, there is no cost.  For an
      output dependence, there is sometimes a cost, but it doesn't seem
@@ -849,60 +2267,224 @@ alpha_adjust_cost (insn, link, dep_insn, cost)
   if (REG_NOTE_KIND (link) != 0)
     return 0;
 
-  /* If INSN is a store insn and DEP_INSN is setting the data being stored,
-     we can sometimes lower the cost.  */
+  /* If we can't recognize the insns, we can't really do anything.  */
+  if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
+    return cost;
 
-  if (recog_memoized (insn) >= 0 && get_attr_type (insn) == TYPE_ST
-      && (set = single_set (dep_insn)) != 0
-      && GET_CODE (PATTERN (insn)) == SET
-      && rtx_equal_p (SET_DEST (set), SET_SRC (PATTERN (insn))))
-    switch (get_attr_type (dep_insn))
-      {
-      case TYPE_LD:
-	/* No savings here.  */
-	return cost;
-
-      case TYPE_IMULL:
-      case TYPE_IMULQ:
-	/* In these cases, we save one cycle.  */
-	return cost - 2;
-
-      default:
-	/* In all other cases, we save two cycles.  */
-	return MAX (0, cost - 4);
-      }
+  insn_type = get_attr_type (insn);
+  dep_insn_type = get_attr_type (dep_insn);
 
-  /* Another case that needs adjustment is an arithmetic or logical
-     operation.  It's cost is usually one cycle, but we default it to
-     two in the MD file.  The only case that it is actually two is
-     for the address in loads and stores.  */
+  /* Bring in the user-defined memory latency.  */
+  if (dep_insn_type == TYPE_ILD
+      || dep_insn_type == TYPE_FLD
+      || dep_insn_type == TYPE_LDSYM)
+    cost += alpha_memory_latency-1;
 
-  if (recog_memoized (dep_insn) >= 0
-      && get_attr_type (dep_insn) == TYPE_IADDLOG)
-    switch (get_attr_type (insn))
-      {
-      case TYPE_LD:
-      case TYPE_ST:
-	return cost;
+  switch (alpha_cpu)
+    {
+    case PROCESSOR_EV4:
+      /* On EV4, if INSN is a store insn and DEP_INSN is setting the data
+	 being stored, we can sometimes lower the cost.  */
+
+      if ((insn_type == TYPE_IST || insn_type == TYPE_FST)
+	  && (set = single_set (dep_insn)) != 0
+	  && GET_CODE (PATTERN (insn)) == SET
+	  && rtx_equal_p (SET_DEST (set), SET_SRC (PATTERN (insn))))
+	{
+	  switch (dep_insn_type)
+	    {
+	    case TYPE_ILD:
+	    case TYPE_FLD:
+	      /* No savings here.  */
+	      return cost;
+
+	    case TYPE_IMUL:
+	      /* In these cases, we save one cycle.  */
+	      return cost - 1;
+
+	    default:
+	      /* In all other cases, we save two cycles.  */
+	      return MAX (0, cost - 2);
+	    }
+	}
 
-      default:
-	return 2;
-      }
+      /* Another case that needs adjustment is an arithmetic or logical
+	 operation.  It's cost is usually one cycle, but we default it to
+	 two in the MD file.  The only case that it is actually two is
+	 for the address in loads, stores, and jumps.  */
 
-  /* The final case is when a compare feeds into an integer branch.  The cost
-     is only one cycle in that case.  */
+      if (dep_insn_type == TYPE_IADD || dep_insn_type == TYPE_ILOG)
+	{
+	  switch (insn_type)
+	    {
+	    case TYPE_ILD:
+	    case TYPE_IST:
+	    case TYPE_FLD:
+	    case TYPE_FST:
+	    case TYPE_JSR:
+	      return cost;
+	    default:
+	      return 1;
+	    }
+	}
 
-  if (recog_memoized (dep_insn) >= 0
-      && get_attr_type (dep_insn) == TYPE_ICMP
-      && recog_memoized (insn) >= 0
-      && get_attr_type (insn) == TYPE_IBR)
-    return 2;
+      /* The final case is when a compare feeds into an integer branch;
+	 the cost is only one cycle in that case.  */
 
-  /* Otherwise, return the default cost. */
+      if (dep_insn_type == TYPE_ICMP && insn_type == TYPE_IBR)
+	return 1;
+      break;
+
+    case PROCESSOR_EV5:
+      /* And the lord DEC saith:  "A special bypass provides an effective
+	 latency of 0 cycles for an ICMP or ILOG insn producing the test
+	 operand of an IBR or ICMOV insn." */
+
+      if ((dep_insn_type == TYPE_ICMP || dep_insn_type == TYPE_ILOG)
+	  && (set = single_set (dep_insn)) != 0)
+	{
+	  /* A branch only has one input.  This must be it.  */
+	  if (insn_type == TYPE_IBR)
+	    return 0;
+	  /* A conditional move has three, make sure it is the test.  */
+	  if (insn_type == TYPE_ICMOV
+	      && GET_CODE (set_src = PATTERN (insn)) == SET
+	      && GET_CODE (set_src = SET_SRC (set_src)) == IF_THEN_ELSE
+	      && rtx_equal_p (SET_DEST (set), XEXP (set_src, 0)))
+	    return 0;
+	}
+
+      /* "The multiplier is unable to receive data from IEU bypass paths.
+	 The instruction issues at the expected time, but its latency is
+	 increased by the time it takes for the input data to become
+	 available to the multiplier" -- which happens in pipeline stage
+	 six, when results are comitted to the register file.  */
 
+      if (insn_type == TYPE_IMUL)
+	{
+	  switch (dep_insn_type)
+	    {
+	    /* These insns produce their results in pipeline stage five.  */
+	    case TYPE_ILD:
+	    case TYPE_ICMOV:
+	    case TYPE_IMUL:
+	    case TYPE_MVI:
+	      return cost + 1;
+
+	    /* Other integer insns produce results in pipeline stage four.  */
+	    default:
+	      return cost + 2;
+	    }
+	}
+      break;
+
+    case PROCESSOR_EV6:
+      /* There is additional latency to move the result of (most) FP 
+         operations anywhere but the FP register file.  */
+
+      if ((insn_type == TYPE_FST || insn_type == TYPE_FTOI)
+	  && (dep_insn_type == TYPE_FADD ||
+	      dep_insn_type == TYPE_FMUL ||
+	      dep_insn_type == TYPE_FCMOV))
+        return cost + 2;
+
+      break;
+    }
+
+  /* Otherwise, return the default cost. */
   return cost;
 }
 
+/* Functions to save and restore alpha_return_addr_rtx.  */
+
+struct machine_function
+{
+  rtx ra_rtx;
+};
+
+static void
+alpha_save_machine_status (p)
+     struct function *p;
+{
+  struct machine_function *machine =
+    (struct machine_function *) xmalloc (sizeof (struct machine_function));
+
+  p->machine = machine;
+  machine->ra_rtx = alpha_return_addr_rtx;
+}
+
+static void
+alpha_restore_machine_status (p)
+     struct function *p;
+{
+  struct machine_function *machine = p->machine;
+
+  alpha_return_addr_rtx = machine->ra_rtx;
+
+  free (machine);
+  p->machine = (struct machine_function *)0;
+}
+
+/* Do anything needed before RTL is emitted for each function.  */
+
+void
+alpha_init_expanders ()
+{
+  alpha_return_addr_rtx = NULL_RTX;
+
+  /* Arrange to save and restore machine status around nested functions.  */
+  save_machine_status = alpha_save_machine_status;
+  restore_machine_status = alpha_restore_machine_status;
+}
+
+/* Start the ball rolling with RETURN_ADDR_RTX.  */
+
+rtx
+alpha_return_addr (count, frame)
+     int count;
+     rtx frame ATTRIBUTE_UNUSED;
+{
+  rtx init;
+
+  if (count != 0)
+    return const0_rtx;
+
+  if (alpha_return_addr_rtx)
+    return alpha_return_addr_rtx;
+
+  /* No rtx yet.  Invent one, and initialize it from $26 in the prologue.  */
+  alpha_return_addr_rtx = gen_reg_rtx (Pmode);
+  init = gen_rtx_SET (Pmode, alpha_return_addr_rtx,
+		      gen_rtx_REG (Pmode, REG_RA));
+
+  /* Emit the insn to the prologue with the other argument copies.  */
+  push_topmost_sequence ();
+  emit_insn_after (init, get_insns ());
+  pop_topmost_sequence ();
+
+  return alpha_return_addr_rtx;
+}
+
+static int
+alpha_ra_ever_killed ()
+{
+  rtx top;
+
+#ifdef ASM_OUTPUT_MI_THUNK
+  if (current_function_is_thunk)
+    return 0;
+#endif
+  if (!alpha_return_addr_rtx)
+    return regs_ever_live[REG_RA];
+
+  push_topmost_sequence ();
+  top = get_insns();
+  pop_topmost_sequence ();
+  
+  return reg_set_between_p (gen_rtx_REG (Pmode, REG_RA), top, NULL_RTX);
+}
+
+
 /* Print an operand.  Recognize special options, documented below.  */
 
 void
@@ -915,6 +2497,115 @@ print_operand (file, x, code)
 
   switch (code)
     {
+    case '&':
+      /* Generates fp-rounding mode suffix: nothing for normal, 'c' for
+	 chopped, 'm' for minus-infinity, and 'd' for dynamic rounding
+	 mode.  alpha_fprm controls which suffix is generated.  */
+      switch (alpha_fprm)
+	{
+	case ALPHA_FPRM_NORM:
+	  break;
+	case ALPHA_FPRM_MINF: 
+	  fputc ('m', file);
+	  break;
+	case ALPHA_FPRM_CHOP:
+	  fputc ('c', file);
+	  break;
+	case ALPHA_FPRM_DYN:
+	  fputc ('d', file);
+	  break;
+	}
+      break;
+
+    case '\'':
+      /* Generates trap-mode suffix for instructions that accept the su
+	 suffix only (cmpt et al).  */
+      if (alpha_tp == ALPHA_TP_INSN)
+	fputs ("su", file);
+      break;
+
+    case '`':
+      /* Generates trap-mode suffix for instructions that accept the
+	 v and sv suffix.  The only instruction that needs this is cvtql.  */
+      switch (alpha_fptm)
+	{
+	case ALPHA_FPTM_N:
+	  break;
+	case ALPHA_FPTM_U:
+	  fputs ("v", file);
+	  break;
+	case ALPHA_FPTM_SU:
+	case ALPHA_FPTM_SUI:
+	  fputs ("sv", file);
+	  break;
+	}
+      break;
+
+    case '(':
+      /* Generates trap-mode suffix for instructions that accept the
+	 v, sv, and svi suffix.  The only instruction that needs this
+	 is cvttq.  */
+      switch (alpha_fptm)
+	{
+	case ALPHA_FPTM_N:
+	  break;
+	case ALPHA_FPTM_U:
+	  fputs ("v", file);
+	  break;
+	case ALPHA_FPTM_SU:
+	  fputs ("sv", file);
+	  break;
+	case ALPHA_FPTM_SUI:
+	  fputs ("svi", file);
+	  break;
+	}
+      break;
+
+    case ')':
+      /* Generates trap-mode suffix for instructions that accept the u, su,
+	 and sui suffix.  This is the bulk of the IEEE floating point
+	 instructions (addt et al).  */
+      switch (alpha_fptm)
+	{
+	case ALPHA_FPTM_N:
+	  break;
+	case ALPHA_FPTM_U:
+	  fputc ('u', file);
+	  break;
+	case ALPHA_FPTM_SU:
+	  fputs ("su", file);
+	  break;
+	case ALPHA_FPTM_SUI:
+	  fputs ("sui", file);
+	  break;
+	}
+      break;
+
+    case '+':
+      /* Generates trap-mode suffix for instructions that accept the sui
+	 suffix (cvtqt and cvtqs).  */
+      switch (alpha_fptm)
+	{
+	case ALPHA_FPTM_N:
+	case ALPHA_FPTM_U:
+	case ALPHA_FPTM_SU:	/* cvtqt/cvtqs can't cause underflow */
+	  break;
+	case ALPHA_FPTM_SUI:
+	  fputs ("sui", file);
+	  break;
+	}
+      break;
+
+    case ',':
+      /* Generates single precision instruction suffix.  */
+      fprintf (file, "%c", (TARGET_FLOAT_VAX ? 'f' : 's'));
+      break;
+
+    case '-':
+      /* Generates double precision instruction suffix.  */
+      fprintf (file, "%c", (TARGET_FLOAT_VAX ? 'g' : 't'));
+      break;
+
     case 'r':
       /* If this operand is the constant zero, write it as "$31".  */
       if (GET_CODE (x) == REG)
@@ -942,7 +2633,7 @@ print_operand (file, x, code)
       if (GET_CODE (x) != CONST_INT)
 	output_operand_lossage ("invalid %%N value");
 
-      fprintf (file, "%ld", ~ INTVAL (x));
+      fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
       break;
 
     case 'P':
@@ -950,7 +2641,7 @@ print_operand (file, x, code)
       if (GET_CODE (x) != CONST_INT)
 	output_operand_lossage ("invalid %%P value");
 
-      fprintf (file, "%ld", (HOST_WIDE_INT) 1 << INTVAL (x));
+      fprintf (file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT) 1 << INTVAL (x));
       break;
 
     case 'h':
@@ -958,7 +2649,7 @@ print_operand (file, x, code)
       if (GET_CODE (x) != CONST_INT)
 	output_operand_lossage ("invalid %%h value");
 
-      fprintf (file, "%ld", INTVAL (x) >> 16);
+      fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) >> 16);
       break;
 
     case 'L':
@@ -966,7 +2657,8 @@ print_operand (file, x, code)
       if (GET_CODE (x) != CONST_INT)
 	output_operand_lossage ("invalid %%L value");
 
-      fprintf (file, "%ld", (INTVAL (x) & 0xffff) - 2 * (INTVAL (x) & 0x8000));
+      fprintf (file, HOST_WIDE_INT_PRINT_DEC,
+	       (INTVAL (x) & 0xffff) - 2 * (INTVAL (x) & 0x8000));
       break;
 
     case 'm':
@@ -988,7 +2680,7 @@ print_operand (file, x, code)
 	    if (value & 0xff)
 	      mask |= (1 << (i + sizeof (int)));
 
-	  fprintf (file, "%ld", mask & 0xff);
+	  fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask & 0xff);
 	}
 
       else if (GET_CODE (x) == CONST_INT)
@@ -999,20 +2691,24 @@ print_operand (file, x, code)
 	    if (value & 0xff)
 	      mask |= (1 << i);
 
-	  fprintf (file, "%ld", mask);
+	  fprintf (file, HOST_WIDE_INT_PRINT_DEC, mask);
 	}
       else
 	output_operand_lossage ("invalid %%m value");
       break;
 
     case 'M':
-      /* 'b', 'w', or 'l' as the value of the constant.  */
+      /* 'b', 'w', 'l', or 'q' as the value of the constant.  */
       if (GET_CODE (x) != CONST_INT
-	  || (INTVAL (x) != 8 && INTVAL (x) != 16 && INTVAL (x) != 32))
+	  || (INTVAL (x) != 8 && INTVAL (x) != 16
+	      && INTVAL (x) != 32 && INTVAL (x) != 64))
 	output_operand_lossage ("invalid %%M value");
 
       fprintf (file, "%s",
-	       INTVAL (x) == 8 ? "b" : INTVAL (x) == 16 ? "w" : "l");
+	       (INTVAL (x) == 8 ? "b"
+		: INTVAL (x) == 16 ? "w"
+		: INTVAL (x) == 32 ? "l"
+		: "q"));
       break;
 
     case 'U':
@@ -1021,14 +2717,24 @@ print_operand (file, x, code)
 	fprintf (file, "b");
       else if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xffff)
 	fprintf (file, "w");
+      else if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xffffffff)
+	fprintf (file, "l");
 #if HOST_BITS_PER_WIDE_INT == 32
       else if (GET_CODE (x) == CONST_DOUBLE
 	       && CONST_DOUBLE_HIGH (x) == 0
 	       && CONST_DOUBLE_LOW (x) == -1)
 	fprintf (file, "l");
+      else if (GET_CODE (x) == CONST_DOUBLE
+	       && CONST_DOUBLE_HIGH (x) == -1
+	       && CONST_DOUBLE_LOW (x) == -1)
+	fprintf (file, "q");
 #else
-      else if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xffffffff)
-	fprintf (file, "l");
+      else if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0xffffffffffffffff)
+	fprintf (file, "q");
+      else if (GET_CODE (x) == CONST_DOUBLE
+	       && CONST_DOUBLE_HIGH (x) == 0
+	       && CONST_DOUBLE_LOW (x) == -1)
+	fprintf (file, "q");
 #endif
       else
 	output_operand_lossage ("invalid %%U value");
@@ -1041,7 +2747,7 @@ print_operand (file, x, code)
 	  && (INTVAL (x) & 7) != 8)
 	output_operand_lossage ("invalid %%s value");
 
-      fprintf (file, "%ld", INTVAL (x) / 8);
+      fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) / 8);
       break;
 
     case 'S':
@@ -1052,46 +2758,31 @@ print_operand (file, x, code)
 	  && (INTVAL (x) & 7) != 8)
 	output_operand_lossage ("invalid %%s value");
 
-      fprintf (file, "%ld", (64 - INTVAL (x)) / 8);
+      fprintf (file, HOST_WIDE_INT_PRINT_DEC, (64 - INTVAL (x)) / 8);
       break;
 
-    case 'C':
+    case 'C': case 'D': case 'c': case 'd':
       /* Write out comparison name.  */
-      if (GET_RTX_CLASS (GET_CODE (x)) != '<')
-	output_operand_lossage ("invalid %%C value");
-
-      if (GET_CODE (x) == LEU)
-	fprintf (file, "ule");
-      else if (GET_CODE (x) == LTU)
-	fprintf (file, "ult");
-      else
-	fprintf (file, "%s", GET_RTX_NAME (GET_CODE (x)));
-      break;
-
-    case 'D':
-      /* Similar, but write reversed code.  We can't get an unsigned code
-	 here.  */
-      if (GET_RTX_CLASS (GET_CODE (x)) != '<')
-	output_operand_lossage ("invalid %%D value");
-
-      fprintf (file, "%s", GET_RTX_NAME (reverse_condition (GET_CODE (x))));
-      break;
-
-    case 'c':
-      /* Similar to `c', but swap.  We can't get unsigned here either.  */
-      if (GET_RTX_CLASS (GET_CODE (x)) != '<')
-	output_operand_lossage ("invalid %%D value");
-
-      fprintf (file, "%s", GET_RTX_NAME (swap_condition (GET_CODE (x))));
-      break;
-
-    case 'd':
-      /* Similar, but reverse and swap.  We can't get unsigned here either.  */
-      if (GET_RTX_CLASS (GET_CODE (x)) != '<')
-	output_operand_lossage ("invalid %%D value");
-
-      fprintf (file, "%s",
-	       GET_RTX_NAME (swap_condition (reverse_condition ((GET_CODE (x))))));
+      {
+	enum rtx_code c = GET_CODE (x);
+
+        if (GET_RTX_CLASS (c) != '<')
+	  output_operand_lossage ("invalid %%C value");
+
+	if (code == 'D')
+	  c = reverse_condition (c);
+	else if (code == 'c')
+	  c = swap_condition (c);
+	else if (code == 'd')
+	  c = swap_condition (reverse_condition (c));
+
+        if (c == LEU)
+	  fprintf (file, "ule");
+        else if (c == LTU)
+	  fprintf (file, "ult");
+        else
+	  fprintf (file, "%s", GET_RTX_NAME (c));
+      }
       break;
 
     case 'E':
@@ -1136,6 +2827,65 @@ print_operand (file, x, code)
     }
 }
 
+/* Emit RTL insns to initialize the variable parts of a trampoline at
+   TRAMP. FNADDR is an RTX for the address of the function's pure
+   code.  CXT is an RTX for the static chain value for the function.
+
+   The three offset parameters are for the individual template's
+   layout.  A JMPOFS < 0 indicates that the trampoline does not 
+   contain instructions at all.
+
+   We assume here that a function will be called many more times than
+   its address is taken (e.g., it might be passed to qsort), so we
+   take the trouble to initialize the "hint" field in the JMP insn.
+   Note that the hint field is PC (new) + 4 * bits 13:0.  */
+
+void
+alpha_initialize_trampoline (tramp, fnaddr, cxt, fnofs, cxtofs, jmpofs)
+     rtx tramp, fnaddr, cxt;
+     int fnofs, cxtofs, jmpofs;
+{
+  rtx temp, temp1, addr;
+  /* ??? Something is wrong with VMS codegen in that we get aborts when
+     using ptr_mode.  Hack around it for now.  */
+  enum machine_mode mode = TARGET_OPEN_VMS ? Pmode : ptr_mode;
+
+  /* Store function address and CXT.  */
+  addr = memory_address (mode, plus_constant (tramp, fnofs));
+  emit_move_insn (gen_rtx (MEM, mode, addr), fnaddr);
+  addr = memory_address (mode, plus_constant (tramp, cxtofs));
+  emit_move_insn (gen_rtx (MEM, mode, addr), cxt);
+
+  /* This has been disabled since the hint only has a 32k range, and in
+     no existing OS is the stack within 32k of the text segment. */
+  if (0 && jmpofs >= 0)
+    {
+      /* Compute hint value.  */
+      temp = force_operand (plus_constant (tramp, jmpofs+4), NULL_RTX);
+      temp = expand_binop (DImode, sub_optab, fnaddr, temp, temp, 1,
+			   OPTAB_WIDEN);
+      temp = expand_shift (RSHIFT_EXPR, Pmode, temp,
+		           build_int_2 (2, 0), NULL_RTX, 1);
+      temp = expand_and (gen_lowpart (SImode, temp), GEN_INT (0x3fff), 0);
+
+      /* Merge in the hint.  */
+      addr = memory_address (SImode, plus_constant (tramp, jmpofs));
+      temp1 = force_reg (SImode, gen_rtx (MEM, SImode, addr));
+      temp1 = expand_and (temp1, GEN_INT (0xffffc000), NULL_RTX);
+      temp1 = expand_binop (SImode, ior_optab, temp1, temp, temp1, 1,
+			    OPTAB_WIDEN);
+      emit_move_insn (gen_rtx (MEM, SImode, addr), temp1);
+    }
+
+#ifdef TRANSFER_FROM_TRAMPOLINE
+  emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
+		     0, VOIDmode, 1, addr, Pmode);
+#endif
+
+  if (jmpofs >= 0)
+    emit_insn (gen_imb ());
+}
+
 /* Do what is necessary for `va_start'.  The argument is ignored;
    We look at the current function to determine if stdarg or varargs
    is used and fill in an initial va_list.  A pointer to this constructor
@@ -1143,9 +2893,9 @@ print_operand (file, x, code)
 
 struct rtx_def *
 alpha_builtin_saveregs (arglist)
-     tree arglist;
+     tree arglist ATTRIBUTE_UNUSED;
 {
-  rtx block, addr, argsize;
+  rtx block, addr, dest, argsize;
   tree fntype = TREE_TYPE (current_function_decl);
   int stdarg = (TYPE_ARG_TYPES (fntype) != 0
 		&& (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
@@ -1153,11 +2903,11 @@ alpha_builtin_saveregs (arglist)
 
   /* Compute the current position into the args, taking into account
      both registers and memory.  Both of these are already included in
-     current_function_args_info.  */
+     NUM_ARGS.  */
 
-  argsize = GEN_INT (current_function_args_info * UNITS_PER_WORD);
+  argsize = GEN_INT (NUM_ARGS * UNITS_PER_WORD);
 
-  /* SETUP_INCOMING_VARARGS moves the starting address base up by 48,
+  /* For Unix, SETUP_INCOMING_VARARGS moves the starting address base up by 48,
      storing fp arg registers in the first 48 bytes, and the integer arg
      registers in the next 48 bytes.  This is only done, however, if any
      integer registers need to be stored.
@@ -1166,35 +2916,71 @@ alpha_builtin_saveregs (arglist)
      order to account for the integer arg registers which are counted in
      argsize above, but which are not actually stored on the stack.  */
 
-  addr = (current_function_args_info <= 5 + stdarg
-	  ? plus_constant (virtual_incoming_args_rtx, 6 * UNITS_PER_WORD)
-	  : plus_constant (virtual_incoming_args_rtx, - (6 * UNITS_PER_WORD)));
-
-  addr = force_operand (addr, NULL_RTX);
+  if (TARGET_OPEN_VMS)
+    addr = plus_constant (virtual_incoming_args_rtx,
+			  NUM_ARGS <= 5 + stdarg
+			  ? UNITS_PER_WORD : - 6 * UNITS_PER_WORD);
+  else
+    addr = (NUM_ARGS <= 5 + stdarg
+	    ? plus_constant (virtual_incoming_args_rtx,
+			     6 * UNITS_PER_WORD)
+	    : plus_constant (virtual_incoming_args_rtx,
+			     - (6 * UNITS_PER_WORD)));
 
-  /* Allocate the va_list constructor */
-  block = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
-  RTX_UNCHANGING_P (block) = 1;
-  RTX_UNCHANGING_P (XEXP (block, 0)) = 1;
+  /* For VMS, we include the argsize, while on Unix, it's handled as
+     a separate field.  */
+  if (TARGET_OPEN_VMS)
+    addr = plus_constant (addr, INTVAL (argsize));
 
-  /* Store the address of the first integer register in the __base member.  */
+  addr = force_operand (addr, NULL_RTX);
 
 #ifdef POINTERS_EXTEND_UNSIGNED
   addr = convert_memory_address (ptr_mode, addr);
 #endif
 
-  emit_move_insn (change_address (block, ptr_mode, XEXP (block, 0)), addr);
-
-  /* Store the argsize as the __va_offset member.  */
-  emit_move_insn (change_address (block, TYPE_MODE (integer_type_node),
-				  plus_constant (XEXP (block, 0),
-						 POINTER_SIZE/BITS_PER_UNIT)),
-		  argsize);
-
-  /* Return the address of the va_list constructor, but don't put it in a
-     register.  Doing so would fail when not optimizing and produce worse
-     code when optimizing.  */
-  return XEXP (block, 0);
+  if (TARGET_OPEN_VMS)
+    return addr;
+  else
+    {
+      /* Allocate the va_list constructor */
+      block = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
+      RTX_UNCHANGING_P (block) = 1;
+      RTX_UNCHANGING_P (XEXP (block, 0)) = 1;
+
+      /* Store the address of the first integer register in the __base
+	 member.  */
+
+      dest = change_address (block, ptr_mode, XEXP (block, 0));
+      emit_move_insn (dest, addr);
+
+      if (flag_check_memory_usage)
+	emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
+			   dest, ptr_mode,
+			   GEN_INT (GET_MODE_SIZE (ptr_mode)),
+			   TYPE_MODE (sizetype),
+			   GEN_INT (MEMORY_USE_RW), 
+			   TYPE_MODE (integer_type_node));
+  
+      /* Store the argsize as the __va_offset member.  */
+      dest = change_address (block, TYPE_MODE (integer_type_node),
+			     plus_constant (XEXP (block, 0),
+					    POINTER_SIZE/BITS_PER_UNIT));
+      emit_move_insn (dest, argsize);
+
+      if (flag_check_memory_usage)
+	emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
+			   dest, ptr_mode,
+			   GEN_INT (GET_MODE_SIZE
+				    (TYPE_MODE (integer_type_node))),
+			   TYPE_MODE (sizetype),
+			   GEN_INT (MEMORY_USE_RW),
+			   TYPE_MODE (integer_type_node));
+
+      /* Return the address of the va_list constructor, but don't put it in a
+	 register.  Doing so would fail when not optimizing and produce worse
+	 code when optimizing.  */
+      return XEXP (block, 0);
+    }
 }
 
 /* This page contains routines that are used to determine what the function
@@ -1202,43 +2988,203 @@ alpha_builtin_saveregs (arglist)
 
 /* Compute the size of the save area in the stack.  */
 
+/* These variables are used for communication between the following functions.
+   They indicate various things about the current function being compiled
+   that are used to tell what kind of prologue, epilogue and procedure
+   descriptior to generate. */
+
+/* Nonzero if we need a stack procedure.  */
+static int vms_is_stack_procedure;
+
+/* Register number (either FP or SP) that is used to unwind the frame.  */
+static int vms_unwind_regno;
+
+/* Register number used to save FP.  We need not have one for RA since
+   we don't modify it for register procedures.  This is only defined
+   for register frame procedures.  */
+static int vms_save_fp_regno;
+
+/* Register number used to reference objects off our PV.  */
+static int vms_base_regno;
+
+/* Compute register masks for saved registers.  */
+
+static void
+alpha_sa_mask (imaskP, fmaskP)
+    unsigned long *imaskP;
+    unsigned long *fmaskP;
+{
+  unsigned long imask = 0;
+  unsigned long fmask = 0;
+  int i;
+
+#ifdef ASM_OUTPUT_MI_THUNK
+  if (!current_function_is_thunk)
+#endif
+    {
+      if (TARGET_OPEN_VMS && vms_is_stack_procedure)
+	imask |= (1L << HARD_FRAME_POINTER_REGNUM);
+
+      /* One for every register we have to save.  */
+      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+	if (! fixed_regs[i] && ! call_used_regs[i]
+	    && regs_ever_live[i] && i != REG_RA)
+	  {
+	    if (i < 32)
+	      imask |= (1L << i);
+	    else
+	      fmask |= (1L << (i - 32));
+	  }
+
+      if (imask || fmask || alpha_ra_ever_killed ())
+	imask |= (1L << REG_RA);
+    }
+
+  *imaskP = imask;
+  *fmaskP = fmask;
+}
+
 int
 alpha_sa_size ()
 {
-  int size = 0;
+  int sa_size = 0;
   int i;
 
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-    if (! fixed_regs[i] && ! call_used_regs[i] && regs_ever_live[i])
-      size++;
+#ifdef ASM_OUTPUT_MI_THUNK
+  if (current_function_is_thunk)
+    sa_size = 0;
+  else
+#endif
+    {
+      /* One for every register we have to save.  */
+      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+	if (! fixed_regs[i] && ! call_used_regs[i]
+	    && regs_ever_live[i] && i != REG_RA)
+	  sa_size++;
+    }
 
-  /* If some registers were saved but not reg 26, reg 26 must also
-     be saved, so leave space for it.  */
-  if (size != 0 && ! regs_ever_live[26])
-    size++;
+  if (TARGET_OPEN_VMS)
+    {
+      /* Start by assuming we can use a register procedure if we don't
+	 make any calls (REG_RA not used) or need to save any
+	 registers and a stack procedure if we do.  */
+      vms_is_stack_procedure = sa_size != 0 || alpha_ra_ever_killed ();
+
+      /* Decide whether to refer to objects off our PV via FP or PV.
+	 If we need FP for something else or if we receive a nonlocal
+	 goto (which expects PV to contain the value), we must use PV.
+	 Otherwise, start by assuming we can use FP.  */
+      vms_base_regno = (frame_pointer_needed
+			|| current_function_has_nonlocal_label
+			|| vms_is_stack_procedure
+			|| current_function_outgoing_args_size
+			? REG_PV : HARD_FRAME_POINTER_REGNUM);
+
+      /* If we want to copy PV into FP, we need to find some register
+	 in which to save FP.  */
+
+      vms_save_fp_regno = -1;
+      if (vms_base_regno == HARD_FRAME_POINTER_REGNUM)
+	for (i = 0; i < 32; i++)
+	  if (! fixed_regs[i] && call_used_regs[i] && ! regs_ever_live[i])
+	    vms_save_fp_regno = i;
+
+      if (vms_save_fp_regno == -1)
+	vms_base_regno = REG_PV, vms_is_stack_procedure = 1;
+
+      /* Stack unwinding should be done via FP unless we use it for PV.  */
+      vms_unwind_regno = (vms_base_regno == REG_PV
+			  ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM);
+
+      /* If this is a stack procedure, allow space for saving FP and RA.  */
+      if (vms_is_stack_procedure)
+	sa_size += 2;
+    }
+  else
+    {
+      /* If some registers were saved but not RA, RA must also be saved,
+	 so leave space for it.  */
+      if (sa_size != 0 || alpha_ra_ever_killed ())
+	sa_size++;
+
+      /* Our size must be even (multiple of 16 bytes).  */
+      if (sa_size & 1)
+	sa_size++;
+    }
 
-  /* Our size must be even (multiple of 16 bytes).  */
-  if (size & 1)
-    size ++;
+  return sa_size * 8;
+}
 
-  return size * 8;
+int
+alpha_pv_save_size ()
+{
+  alpha_sa_size ();
+  return vms_is_stack_procedure ? 8 : 0;
 }
 
-/* Return 1 if this function can directly return via $26.  */
+int
+alpha_using_fp ()
+{
+  alpha_sa_size ();
+  return vms_unwind_regno == HARD_FRAME_POINTER_REGNUM;
+}
 
 int
-direct_return ()
+vms_valid_decl_attribute_p (decl, attributes, identifier, args)
+     tree decl ATTRIBUTE_UNUSED;
+     tree attributes ATTRIBUTE_UNUSED;
+     tree identifier;
+     tree args;
 {
-  return (reload_completed && alpha_sa_size () == 0
-	  && get_frame_size () == 0
-	  && current_function_outgoing_args_size == 0
-	  && current_function_pretend_args_size == 0);
+  if (is_attribute_p ("overlaid", identifier))
+    return (args == NULL_TREE);
+  return 0;
+}
+
+static int
+alpha_does_function_need_gp ()
+{
+  rtx insn;
+
+  /* We never need a GP for Windows/NT or VMS.  */
+  if (TARGET_WINDOWS_NT || TARGET_OPEN_VMS)
+    return 0;
+
+#ifdef TARGET_PROFILING_NEEDS_GP
+  if (profile_flag)
+    return 1;
+#endif
+
+#ifdef ASM_OUTPUT_MI_THUNK
+  if (current_function_is_thunk)
+    return 1;
+#endif
+
+  /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first. 
+     Even if we are a static function, we still need to do this in case
+     our address is taken and passed to something like qsort.  */
+
+  push_topmost_sequence ();
+  insn = get_insns ();
+  pop_topmost_sequence ();
+
+  for (; insn; insn = NEXT_INSN (insn))
+    if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
+	&& GET_CODE (PATTERN (insn)) != USE
+	&& GET_CODE (PATTERN (insn)) != CLOBBER)
+      {
+	enum attr_type type = get_attr_type (insn);
+	if (type == TYPE_LDSYM || type == TYPE_JSR)
+	  return 1;
+      }
+
+  return 0;
 }
 
 /* Write a version stamp.  Don't write anything if we are running as a
    cross-compiler.  Otherwise, use the versions in /usr/include/stamp.h.  */
 
-#if !defined(CROSS_COMPILE) && !defined(_WIN32)
+#ifdef HAVE_STAMP_H
 #include <stamp.h>
 #endif
 
@@ -1251,145 +3197,58 @@ alpha_write_verstamp (file)
 #endif
 }
 
-/* Write code to add constant C to register number IN_REG (possibly 31)
-   and put the result into OUT_REG.  Use TEMP_REG as a scratch register;
-   usually this will be OUT_REG, but should not be if OUT_REG is 
-   STACK_POINTER_REGNUM, since it must be updated in a single instruction.
-   Write the code to FILE.  */
-
-static void
-add_long_const (file, c, in_reg, out_reg, temp_reg)
-     FILE *file;
-     HOST_WIDE_INT c;
-     int in_reg, out_reg, temp_reg;
-{
-  HOST_WIDE_INT low = (c & 0xffff) - 2 * (c & 0x8000);
-  HOST_WIDE_INT tmp1 = c - low;
-  HOST_WIDE_INT high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
-  HOST_WIDE_INT extra = 0;
-
-  /* We don't have code to write out constants larger than 32 bits.  */
-#if HOST_BITS_PER_LONG_INT == 64
-  if ((unsigned HOST_WIDE_INT) c >> 32 != 0)
-    abort ();
-#endif
-
-  /* If HIGH will be interpreted as negative, we must adjust it to do two
-     ldha insns.  Note that we will never be building a negative constant
-     here.  */
-
-  if (high & 0x8000)
-    {
-      extra = 0x4000;
-      tmp1 -= 0x40000000;
-      high = ((tmp1 >> 16) & 0xffff) - 2 * ((tmp1 >> 16) & 0x8000);
-    }
-
-  if (low != 0)
-    {
-      int result_reg = (extra == 0 && high == 0) ? out_reg : temp_reg;
-
-      if (low >= 0 && low < 255)
-	fprintf (file, "\taddq $%d,%d,$%d\n", in_reg, low, result_reg);
-      else
-	fprintf (file, "\tlda $%d,%d($%d)\n", result_reg, low, in_reg);
-
-      in_reg = result_reg;
-    }
+/* Write function prologue.  */
 
-  if (extra)
-    {
-      int result_reg = (high == 0) ? out_reg : temp_reg;
+/* On vms we have two kinds of functions:
 
-      fprintf (file, "\tldah $%d,%d($%d)\n", result_reg, extra, in_reg);
-      in_reg = result_reg;
-    }
+   - stack frame (PROC_STACK)
+	these are 'normal' functions with local vars and which are
+	calling other functions
+   - register frame (PROC_REGISTER)
+	keeps all data in registers, needs no stack
 
-  if (high)
-    fprintf (file, "\tldah $%d,%d($%d)\n", out_reg, high, in_reg);
-}
+   We must pass this to the assembler so it can generate the
+   proper pdsc (procedure descriptor)
+   This is done with the '.pdesc' command.
 
-/* Write function prologue.  */
+   On not-vms, we don't really differentiate between the two, as we can
+   simply allocate stack without saving registers.  */
 
 void
-output_prolog (file, size)
-     FILE *file;
-     int size;
-{
-  HOST_WIDE_INT out_args_size
-    = ALPHA_ROUND (current_function_outgoing_args_size);
-  HOST_WIDE_INT sa_size = alpha_sa_size ();
-  HOST_WIDE_INT frame_size
-    = (out_args_size + sa_size
-       + ALPHA_ROUND (size + current_function_pretend_args_size));
-  HOST_WIDE_INT reg_offset = out_args_size;
-  HOST_WIDE_INT start_reg_offset = reg_offset;
-  HOST_WIDE_INT actual_start_reg_offset = start_reg_offset;
-  int int_reg_save_area_size = 0;
-  rtx insn;
-  unsigned reg_mask = 0;
+alpha_expand_prologue ()
+{
+  /* Registers to save.  */
+  unsigned long imask = 0;
+  unsigned long fmask = 0;
+  /* Stack space needed for pushing registers clobbered by us.  */
+  HOST_WIDE_INT sa_size;
+  /* Complete stack size needed.  */
+  HOST_WIDE_INT frame_size;
+  /* Offset from base reg to register save area.  */
+  HOST_WIDE_INT reg_offset;
+  rtx sa_reg;
   int i;
 
-  /* Ecoff can handle multiple .file directives, so put out file and lineno.
-     We have to do that before the .ent directive as we cannot switch
-     files within procedures with native ecoff because line numbers are
-     linked to procedure descriptors.
-     Outputting the lineno helps debugging of one line functions as they
-     would otherwise get no line number at all. Please note that we would
-     like to put out last_linenum from final.c, but it is not accessible.  */
-
-  if (write_symbols == SDB_DEBUG)
-    {
-      ASM_OUTPUT_SOURCE_FILENAME (file,
-				  DECL_SOURCE_FILE (current_function_decl));
-      if (debug_info_level != DINFO_LEVEL_TERSE)
-        ASM_OUTPUT_SOURCE_LINE (file,
-				DECL_SOURCE_LINE (current_function_decl));
-    }
-
-  /* The assembly language programmer's guide states that the second argument
-     to the .ent directive, the lex_level, is ignored by the assembler,
-     so we might as well omit it.  */
-     
-  fprintf (file, "\t.ent ");
-  assemble_name (file, alpha_function_name);
-  fprintf (file, "\n");
-  ASM_OUTPUT_LABEL (file, alpha_function_name);
-  inside_function = TRUE;
-
-  /* Set up offsets to alpha virtual arg/local debugging pointer.  */
+  sa_size = alpha_sa_size ();
 
-  alpha_auto_offset = -frame_size + current_function_pretend_args_size;
-  alpha_arg_offset = -frame_size + 48;
-
-  /* If we need a GP (we have a LDSYM insn or a CALL_INSN), load it first. 
-     Even if we are a static function, we still need to do this in case
-     our address is taken and passed to something like qsort.
-
-     We never need a GP for Windows/NT.  */
-
-  alpha_function_needs_gp = 0;
-  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
-    if ((GET_CODE (insn) == CALL_INSN)
-	|| (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
-	    && GET_CODE (PATTERN (insn)) != USE
-	    && GET_CODE (PATTERN (insn)) != CLOBBER
-	    && (get_attr_type (insn) == TYPE_LDSYM
-		|| get_attr_type (insn) == TYPE_ISUBR)))
-      {
-	alpha_function_needs_gp = 1;
-	break;
-      }
+  frame_size = get_frame_size ();
+  if (TARGET_OPEN_VMS)
+    frame_size = ALPHA_ROUND (sa_size 
+			      + (vms_is_stack_procedure ? 8 : 0)
+			      + frame_size
+			      + current_function_pretend_args_size);
+  else
+    frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
+		  + sa_size
+		  + ALPHA_ROUND (frame_size
+				 + current_function_pretend_args_size));
 
-  if (WINDOWS_NT == 0)
-    {
-      if (alpha_function_needs_gp)
-	fprintf (file, "\tldgp $29,0($27)\n");
+  if (TARGET_OPEN_VMS)
+    reg_offset = 8;
+  else
+    reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
 
-      /* Put a label after the GP load so we can enter the function at it.  */
-      assemble_name (file, alpha_function_name);
-      fprintf (file, "..ng:\n");
-    }
+  alpha_sa_mask (&imask, &fmask);
 
   /* Adjust the stack by the frame size.  If the frame size is > 4096
      bytes, we need to be sure we probe somewhere in the first and last
@@ -1400,28 +3259,30 @@ output_prolog (file, size)
 
      Note that we are only allowed to adjust sp once in the prologue.  */
 
-  if (frame_size < 32768)
+  if (frame_size <= 32768)
     {
       if (frame_size > 4096)
 	{
 	  int probed = 4096;
 
-	  fprintf (file, "\tstq $31,-%d($30)\n", probed);
-
-	  while (probed + 8192 < frame_size)
-	    fprintf (file, "\tstq $31,-%d($30)\n", probed += 8192);
+	  do
+	    emit_insn (gen_probe_stack (GEN_INT (-probed)));
+	  while ((probed += 8192) < frame_size);
 
 	  /* We only have to do this probe if we aren't saving registers.  */
 	  if (sa_size == 0 && probed + 4096 < frame_size)
-	    fprintf (file, "\tstq $31,-%d($30)\n", frame_size);
+	    emit_insn (gen_probe_stack (GEN_INT (-frame_size)));
 	}
 
       if (frame_size != 0)
-	fprintf (file, "\tlda $30,-%d($30)\n", frame_size);
+	{
+	  emit_move_insn (stack_pointer_rtx,
+			  plus_constant (stack_pointer_rtx, -frame_size));
+	}
     }
   else
     {
-      /* Here we generate code to set R4 to SP + 4096 and set R5 to the
+      /* Here we generate code to set R22 to SP + 4096 and set R23 to the
 	 number of 8192 byte blocks to probe.  We then probe each block
 	 in the loop and then set SP to the proper location.  If the
 	 amount remaining is > 4096, we have to do one more probe if we
@@ -1429,182 +3290,538 @@ output_prolog (file, size)
 
       HOST_WIDE_INT blocks = (frame_size + 4096) / 8192;
       HOST_WIDE_INT leftover = frame_size + 4096 - blocks * 8192;
+      rtx ptr = gen_rtx_REG (DImode, 22);
+      rtx count = gen_rtx_REG (DImode, 23);
 
-      add_long_const (file, blocks, 31, 5, 5);
+      emit_move_insn (count, GEN_INT (blocks));
+      emit_move_insn (ptr, plus_constant (stack_pointer_rtx, 4096));
 
-      fprintf (file, "\tlda $4,4096($30)\n");
+      /* Because of the difficulty in emitting a new basic block this
+	 late in the compilation, generate the loop as a single insn.  */
+      emit_insn (gen_prologue_stack_probe_loop (count, ptr));
 
-      assemble_name (file, alpha_function_name);
-      fprintf (file, "..sc:\n");
+      if (leftover > 4096 && sa_size == 0)
+	{
+	  rtx last = gen_rtx_MEM (DImode, plus_constant (ptr, -leftover));
+	  MEM_VOLATILE_P (last) = 1;
+	  emit_move_insn (last, const0_rtx);
+	}
 
-      fprintf (file, "\tstq $31,-8192($4)\n");
-      fprintf (file, "\tsubq $5,1,$5\n");
-      fprintf (file, "\tlda $4,-8192($4)\n");
+      emit_move_insn (stack_pointer_rtx, plus_constant (ptr, -leftover));
+    }
 
-      fprintf (file, "\tbne $5,");
-      assemble_name (file, alpha_function_name);
-      fprintf (file, "..sc\n");
+  /* Cope with very large offsets to the register save area.  */
+  sa_reg = stack_pointer_rtx;
+  if (reg_offset + sa_size > 0x8000)
+    {
+      int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
+      HOST_WIDE_INT bias;
 
-      if (leftover > 4096 && sa_size == 0)
-	fprintf (file, "\tstq $31,-%d($4)\n", leftover);
+      if (low + sa_size <= 0x8000)
+	bias = reg_offset - low, reg_offset = low;
+      else 
+	bias = reg_offset, reg_offset = 0;
 
-      fprintf (file, "\tlda $30,-%d($4)\n", leftover);
+      sa_reg = gen_rtx_REG (DImode, 24);
+      emit_move_insn (sa_reg, plus_constant (stack_pointer_rtx, bias));
     }
-
-  /* Describe our frame.  */
-  fprintf (file, "\t.frame $%d,%d,$26,%d\n", 
-	   (frame_pointer_needed
-	    ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM),
-	   frame_size, current_function_pretend_args_size);
     
-  /* Save register 26 if any other register needs to be saved.  */
-  if (sa_size != 0)
+  /* Save regs in stack order.  Beginning with VMS PV.  */
+  if (TARGET_OPEN_VMS && vms_is_stack_procedure)
     {
-      reg_mask |= 1 << 26;
-      fprintf (file, "\tstq $26,%d($30)\n", reg_offset);
+      emit_move_insn (gen_rtx_MEM (DImode, stack_pointer_rtx),
+		      gen_rtx_REG (DImode, REG_PV));
+    }
+
+  /* Save register RA next.  */
+  if (imask & (1L << REG_RA))
+    {
+      emit_move_insn (gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset)),
+		      gen_rtx_REG (DImode, REG_RA));
+      imask &= ~(1L << REG_RA);
       reg_offset += 8;
-      int_reg_save_area_size += 8;
     }
 
-  /* Now save any other used integer registers required to be saved.  */
+  /* Now save any other registers required to be saved.  */
   for (i = 0; i < 32; i++)
-    if (! fixed_regs[i] && ! call_used_regs[i] && regs_ever_live[i] && i != 26)
+    if (imask & (1L << i))
       {
-	reg_mask |= 1 << i;
-	fprintf (file, "\tstq $%d,%d($30)\n", i, reg_offset);
+	emit_move_insn (gen_rtx_MEM (DImode,
+				     plus_constant (sa_reg, reg_offset)),
+			gen_rtx_REG (DImode, i));
 	reg_offset += 8;
-	int_reg_save_area_size += 8;
       }
 
-  /* Print the register mask and do floating-point saves.  */
-  if (reg_mask)
-    fprintf (file, "\t.mask 0x%x,%d\n", reg_mask,
-	     actual_start_reg_offset - frame_size);
-
-  start_reg_offset = reg_offset;
-  reg_mask = 0;
-
   for (i = 0; i < 32; i++)
-    if (! fixed_regs[i + 32] && ! call_used_regs[i + 32]
-	&& regs_ever_live[i + 32])
+    if (fmask & (1L << i))
       {
-	reg_mask |= 1 << i;
-	fprintf (file, "\tstt $f%d,%d($30)\n", i, reg_offset);
+	emit_move_insn (gen_rtx_MEM (DFmode,
+				     plus_constant (sa_reg, reg_offset)),
+			gen_rtx_REG (DFmode, i+32));
 	reg_offset += 8;
       }
 
-  /* Print the floating-point mask, if we've saved any fp register.  */
-  if (reg_mask)
-    fprintf (file, "\t.fmask 0x%x,%d\n", reg_mask,
-	     actual_start_reg_offset - frame_size + int_reg_save_area_size);
+  if (TARGET_OPEN_VMS)
+    {
+      if (!vms_is_stack_procedure)
+	{
+	  /* Register frame procedures fave the fp.  */
+	  emit_move_insn (gen_rtx_REG (DImode, vms_save_fp_regno),
+			  hard_frame_pointer_rtx);
+	}
+
+      if (vms_base_regno != REG_PV)
+	emit_move_insn (gen_rtx_REG (DImode, vms_base_regno),
+			gen_rtx_REG (DImode, REG_PV));
 
-  /* If we need a frame pointer, set it from the stack pointer.  Note that
-     this must always be the last instruction in the prologue.  */
-  if (frame_pointer_needed)
-    fprintf (file, "\tbis $30,$30,$15\n");
+      if (vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
+	{
+	  emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
+	}
 
-  /* End the prologue and say if we used gp.  */
-  fprintf (file, "\t.prologue %d\n", alpha_function_needs_gp);
+      /* If we have to allocate space for outgoing args, do it now.  */
+      if (current_function_outgoing_args_size != 0)
+	{
+	  emit_move_insn (stack_pointer_rtx, 
+	    plus_constant (hard_frame_pointer_rtx,
+	      - ALPHA_ROUND (current_function_outgoing_args_size)));
+	}
+    }
+  else
+    {
+      /* If we need a frame pointer, set it from the stack pointer.  */
+      if (frame_pointer_needed)
+	{
+	  if (TARGET_CAN_FAULT_IN_PROLOGUE)
+	    emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
+	  else
+	    {
+	      /* This must always be the last instruction in the
+		 prologue, thus we emit a special move + clobber.  */
+	      emit_insn (gen_init_fp (hard_frame_pointer_rtx,
+				      stack_pointer_rtx, sa_reg));
+	    }
+	}
+    }
+
+  /* The ABIs for VMS and OSF/1 say that while we can schedule insns into
+     the prologue, for exception handling reasons, we cannot do this for
+     any insn that might fault.  We could prevent this for mems with a
+     (clobber:BLK (scratch)), but this doesn't work for fp insns.  So we
+     have to prevent all such scheduling with a blockage.
+
+     Linux, on the other hand, never bothered to implement OSF/1's 
+     exception handling, and so doesn't care about such things.  Anyone
+     planning to use dwarf2 frame-unwind info can also omit the blockage.  */
+
+  if (! TARGET_CAN_FAULT_IN_PROLOGUE)
+    emit_insn (gen_blockage ());
 }
 
-/* Write function epilogue.  */
+/* Output the textual info surrounding the prologue.  */
 
 void
-output_epilog (file, size)
+alpha_start_function (file, fnname, decl)
      FILE *file;
-     int size;
-{
-  rtx insn = get_last_insn ();
-  HOST_WIDE_INT out_args_size
-    = ALPHA_ROUND (current_function_outgoing_args_size);
-  HOST_WIDE_INT sa_size = alpha_sa_size ();
-  HOST_WIDE_INT frame_size
-    = (out_args_size + sa_size
-       + ALPHA_ROUND (size + current_function_pretend_args_size));
-  HOST_WIDE_INT reg_offset = out_args_size;
-  HOST_WIDE_INT frame_size_from_reg_save = frame_size - reg_offset;
-  int restore_fp
-    = frame_pointer_needed && regs_ever_live[HARD_FRAME_POINTER_REGNUM];
+     char *fnname;
+     tree decl ATTRIBUTE_UNUSED;
+{
+  unsigned long imask = 0;
+  unsigned long fmask = 0;
+  /* Stack space needed for pushing registers clobbered by us.  */
+  HOST_WIDE_INT sa_size;
+  /* Complete stack size needed.  */
+  HOST_WIDE_INT frame_size;
+  /* Offset from base reg to register save area.  */
+  HOST_WIDE_INT reg_offset;
+  char *entry_label = (char *) alloca (strlen (fnname) + 6);
   int i;
 
-  /* If the last insn was a BARRIER, we don't have to write anything except
-     the .end pseudo-op.  */
-  if (GET_CODE (insn) == NOTE)
-    insn = prev_nonnote_insn (insn);
-  if (insn == 0 || GET_CODE (insn) != BARRIER)
+  sa_size = alpha_sa_size ();
+
+  frame_size = get_frame_size ();
+  if (TARGET_OPEN_VMS)
+    frame_size = ALPHA_ROUND (sa_size 
+			      + (vms_is_stack_procedure ? 8 : 0)
+			      + frame_size
+			      + current_function_pretend_args_size);
+  else
+    frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
+		  + sa_size
+		  + ALPHA_ROUND (frame_size
+				 + current_function_pretend_args_size));
+
+  if (TARGET_OPEN_VMS)
+    reg_offset = 8;
+  else
+    reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
+
+  alpha_sa_mask (&imask, &fmask);
+
+  /* Ecoff can handle multiple .file directives, so put out file and lineno.
+     We have to do that before the .ent directive as we cannot switch
+     files within procedures with native ecoff because line numbers are
+     linked to procedure descriptors.
+     Outputting the lineno helps debugging of one line functions as they
+     would otherwise get no line number at all. Please note that we would
+     like to put out last_linenum from final.c, but it is not accessible.  */
+
+  if (write_symbols == SDB_DEBUG)
+    {
+      ASM_OUTPUT_SOURCE_FILENAME (file,
+				  DECL_SOURCE_FILE (current_function_decl));
+      if (debug_info_level != DINFO_LEVEL_TERSE)
+        ASM_OUTPUT_SOURCE_LINE (file,
+				DECL_SOURCE_LINE (current_function_decl));
+    }
+
+  /* Issue function start and label.  */
+  if (TARGET_OPEN_VMS || !flag_inhibit_size_directive)
+    {
+      fputs ("\t.ent ", file);
+      assemble_name (file, fnname);
+      putc ('\n', file);
+    }
+
+  strcpy (entry_label, fnname);
+  if (TARGET_OPEN_VMS)
+    strcat (entry_label, "..en");
+  ASM_OUTPUT_LABEL (file, entry_label);
+  inside_function = TRUE;
+
+  if (TARGET_OPEN_VMS)
+    fprintf (file, "\t.base $%d\n", vms_base_regno);
+
+  if (!TARGET_OPEN_VMS && TARGET_IEEE_CONFORMANT
+      && !flag_inhibit_size_directive)
+    {
+      /* Set flags in procedure descriptor to request IEEE-conformant
+	 math-library routines.  The value we set it to is PDSC_EXC_IEEE
+	 (/usr/include/pdsc.h). */
+      fputs ("\t.eflag 48\n", file);
+    }
+
+  /* Set up offsets to alpha virtual arg/local debugging pointer.  */
+  alpha_auto_offset = -frame_size + current_function_pretend_args_size;
+  alpha_arg_offset = -frame_size + 48;
+
+  /* Describe our frame.  If the frame size is larger than an integer,
+     print it as zero to avoid an assembler error.  We won't be
+     properly describing such a frame, but that's the best we can do.  */
+  if (TARGET_OPEN_VMS)
     {
-      int fp_offset = 0;
+      fprintf (file, "\t.frame $%d,", vms_unwind_regno);
+      fprintf (file, HOST_WIDE_INT_PRINT_DEC,
+	       frame_size >= (1l << 31) ? 0 : frame_size);
+      fputs (",$26,", file);
+      fprintf (file, HOST_WIDE_INT_PRINT_DEC, reg_offset);
+      fputs ("\n", file);
+    }
+  else if (!flag_inhibit_size_directive)
+    {
+      fprintf (file, "\t.frame $%d,",
+	       (frame_pointer_needed
+		? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM));
+      fprintf (file, HOST_WIDE_INT_PRINT_DEC,
+	       frame_size >= (1l << 31) ? 0 : frame_size);
+      fprintf (file, ",$26,%d\n", current_function_pretend_args_size);
+    }
+
+  /* Describe which registers were spilled.  */
+  if (TARGET_OPEN_VMS)
+    {
+      if (imask)
+        /* ??? Does VMS care if mask contains ra?  The old code did'nt
+           set it, so I don't here.  */
+	fprintf (file, "\t.mask 0x%lx,0\n", imask & ~(1L << REG_RA));
+      if (fmask)
+	fprintf (file, "\t.fmask 0x%lx,0\n", fmask);
+      if (!vms_is_stack_procedure)
+	fprintf (file, "\t.fp_save $%d\n", vms_save_fp_regno);
+    }
+  else if (!flag_inhibit_size_directive)
+    {
+      if (imask)
+	{
+	  fprintf (file, "\t.mask 0x%lx,", imask);
+	  fprintf (file, HOST_WIDE_INT_PRINT_DEC,
+		   frame_size >= (1l << 31) ? 0 : reg_offset - frame_size);
+	  putc ('\n', file);
+
+	  for (i = 0; i < 32; ++i)
+	    if (imask & (1L << i))
+	      reg_offset += 8;
+	}
+
+      if (fmask)
+	{
+	  fprintf (file, "\t.fmask 0x%lx,", fmask);
+	  fprintf (file, HOST_WIDE_INT_PRINT_DEC,
+		   frame_size >= (1l << 31) ? 0 : reg_offset - frame_size);
+	  putc ('\n', file);
+	}
+    }
+
+  /* Emit GP related things.  It is rather unfortunate about the alignment
+     issues surrounding a CODE_LABEL that forces us to do the label in 
+     plain text.  */
+  if (!TARGET_OPEN_VMS && !TARGET_WINDOWS_NT)
+    {
+      alpha_function_needs_gp = alpha_does_function_need_gp ();
+      if (alpha_function_needs_gp)
+	fputs ("\tldgp $29,0($27)\n", file);
+
+      putc ('$', file);
+      assemble_name (file, fnname);
+      fputs ("..ng:\n", file);
+    }
+
+#ifdef OPEN_VMS
+  /* Ifdef'ed cause readonly_section and link_section are only
+     available then.  */
+  readonly_section ();
+  fprintf (file, "\t.align 3\n");
+  assemble_name (file, fnname); fputs ("..na:\n", file);
+  fputs ("\t.ascii \"", file);
+  assemble_name (file, fnname);
+  fputs ("\\0\"\n", file);
+      
+  link_section ();
+  fprintf (file, "\t.align 3\n");
+  fputs ("\t.name ", file);
+  assemble_name (file, fnname);
+  fputs ("..na\n", file);
+  ASM_OUTPUT_LABEL (file, fnname);
+  fprintf (file, "\t.pdesc ");
+  assemble_name (file, fnname);
+  fprintf (file, "..en,%s\n", vms_is_stack_procedure ? "stack" : "reg");
+  alpha_need_linkage (fnname, 1);
+  text_section ();
+#endif
+}
+
+/* Emit the .prologue note at the scheduled end of the prologue.  */
+
+void
+output_end_prologue (file)
+     FILE *file;
+{
+  if (TARGET_OPEN_VMS)
+    fputs ("\t.prologue\n", file);
+  else if (TARGET_WINDOWS_NT)
+    fputs ("\t.prologue 0\n", file);
+  else if (!flag_inhibit_size_directive)
+    fprintf (file, "\t.prologue %d\n", alpha_function_needs_gp);
+}
+
+/* Write function epilogue.  */
+
+void
+alpha_expand_epilogue ()
+{
+  /* Registers to save.  */
+  unsigned long imask = 0;
+  unsigned long fmask = 0;
+  /* Stack space needed for pushing registers clobbered by us.  */
+  HOST_WIDE_INT sa_size;
+  /* Complete stack size needed.  */
+  HOST_WIDE_INT frame_size;
+  /* Offset from base reg to register save area.  */
+  HOST_WIDE_INT reg_offset;
+  int fp_is_frame_pointer, fp_offset;
+  rtx sa_reg, sa_reg_exp = NULL;
+  rtx sp_adj1, sp_adj2;
+  int i;
+
+  sa_size = alpha_sa_size ();
+
+  frame_size = get_frame_size ();
+  if (TARGET_OPEN_VMS)
+    frame_size = ALPHA_ROUND (sa_size 
+			      + (vms_is_stack_procedure ? 8 : 0)
+			      + frame_size
+			      + current_function_pretend_args_size);
+  else
+    frame_size = (ALPHA_ROUND (current_function_outgoing_args_size)
+		  + sa_size
+		  + ALPHA_ROUND (frame_size
+				 + current_function_pretend_args_size));
+
+  if (TARGET_OPEN_VMS)
+    reg_offset = 8;
+  else
+    reg_offset = ALPHA_ROUND (current_function_outgoing_args_size);
 
+  alpha_sa_mask (&imask, &fmask);
+
+  fp_is_frame_pointer = ((TARGET_OPEN_VMS && vms_is_stack_procedure)
+			 || (!TARGET_OPEN_VMS && frame_pointer_needed));
+
+  if (sa_size)
+    {
       /* If we have a frame pointer, restore SP from it.  */
-      if (frame_pointer_needed)
-	fprintf (file, "\tbis $15,$15,$30\n");
+      if ((TARGET_OPEN_VMS
+	   && vms_unwind_regno == HARD_FRAME_POINTER_REGNUM)
+	  || (!TARGET_OPEN_VMS && frame_pointer_needed))
+	{
+	  emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
+	}
 
-      /* Restore all the registers, starting with the return address
-	 register.  */
-      if (sa_size != 0)
+      /* Cope with very large offsets to the register save area.  */
+      sa_reg = stack_pointer_rtx;
+      if (reg_offset + sa_size > 0x8000)
 	{
-	  fprintf (file, "\tldq $26,%d($30)\n", reg_offset);
-	  reg_offset += 8;
+	  int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000;
+	  HOST_WIDE_INT bias;
+
+	  if (low + sa_size <= 0x8000)
+	    bias = reg_offset - low, reg_offset = low;
+	  else 
+	    bias = reg_offset, reg_offset = 0;
+
+	  sa_reg = gen_rtx_REG (DImode, 22);
+	  sa_reg_exp = plus_constant (stack_pointer_rtx, bias);
+
+	  emit_move_insn (sa_reg, sa_reg_exp);
 	}
+	  
+      /* Restore registers in order, excepting a true frame pointer. */
 
-      /* Now restore any other used integer registers that that we saved,
-	 except for FP if it is being used as FP, since it must be
-	 restored last.  */
+      emit_move_insn (gen_rtx_REG (DImode, REG_RA),
+		      gen_rtx_MEM (DImode, plus_constant(sa_reg, reg_offset)));
+      reg_offset += 8;
+      imask &= ~(1L << REG_RA);
 
-      for (i = 0; i < 32; i++)
-	if (! fixed_regs[i] && ! call_used_regs[i] && regs_ever_live[i]
-	    && i != 26)
+      for (i = 0; i < 32; ++i)
+	if (imask & (1L << i))
 	  {
-	    if (i == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
+	    if (i == HARD_FRAME_POINTER_REGNUM && fp_is_frame_pointer)
 	      fp_offset = reg_offset;
 	    else
-	      fprintf (file, "\tldq $%d,%d($30)\n", i, reg_offset);
+	      {
+		emit_move_insn (gen_rtx_REG (DImode, i),
+				gen_rtx_MEM (DImode,
+					     plus_constant(sa_reg,
+						           reg_offset)));
+	      }
 	    reg_offset += 8;
 	  }
 
-      for (i = 0; i < 32; i++)
-	if (! fixed_regs[i + 32] && ! call_used_regs[i + 32]
-	    && regs_ever_live[i + 32])
+      for (i = 0; i < 32; ++i)
+	if (fmask & (1L << i))
 	  {
-	    fprintf (file, "\tldt $f%d,%d($30)\n", i, reg_offset);
+	    emit_move_insn (gen_rtx_REG (DFmode, i+32),
+			    gen_rtx_MEM (DFmode,
+					 plus_constant(sa_reg, reg_offset)));
 	    reg_offset += 8;
 	  }
+    }
 
-      /* If the stack size is large and we have a frame pointer, compute the
-	 size of the stack into a register because the old FP restore, stack
-	 pointer adjust, and return are required to be consecutive
-	 instructions.   */
-      if (frame_size > 32767 && restore_fp)
-	add_long_const (file, frame_size, 31, 1, 1);
-
-      /* If we needed a frame pointer and we have to restore it, do it
-	 now.  This must be done in one instruction immediately
-	 before the SP update.  */
-      if (restore_fp && fp_offset)
-	fprintf (file, "\tldq $15,%d($30)\n", fp_offset);
-
-      /* Now update the stack pointer, if needed.  Only one instruction must
-	 modify the stack pointer.  It must be the last instruction in the
-	 sequence and must be an ADDQ or LDA instruction.  If the frame
-	 pointer was loaded above, we may only put one instruction here.  */
-
-      if (frame_size > 32768 && restore_fp)
-	fprintf  (file, "\taddq $1,$30,$30\n");
+  if (frame_size)
+    {
+      /* If the stack size is large, begin computation into a temporary
+	 register so as not to interfere with a potential fp restore,
+	 which must be consecutive with an SP restore.  */
+      if (frame_size < 32768)
+	{
+	  sp_adj1 = stack_pointer_rtx;
+	  sp_adj2 = GEN_INT (frame_size);
+	}
+      else if (frame_size < 0x40007fffL)
+	{
+	  int low = ((frame_size & 0xffff) ^ 0x8000) - 0x8000;
+
+	  sp_adj2 = plus_constant (stack_pointer_rtx, frame_size - low);
+	  if (sa_reg_exp && rtx_equal_p (sa_reg_exp, sp_adj2))
+	    sp_adj1 = sa_reg;
+	  else
+	    {
+	      sp_adj1 = gen_rtx_REG (DImode, 23);
+	      emit_move_insn (sp_adj1, sp_adj2);
+	    }
+	  sp_adj2 = GEN_INT (low);
+	}
       else
-	add_long_const (file, frame_size, 30, 30, 1);
+	{
+	  sp_adj2 = gen_rtx_REG (DImode, 23);
+	  sp_adj1 = alpha_emit_set_const (sp_adj2, DImode, frame_size, 3);
+	  if (!sp_adj1)
+	    {
+	      /* We can't drop new things to memory this late, afaik,
+		 so build it up by pieces.  */
+#if HOST_BITS_PER_WIDE_INT == 64
+	      sp_adj1 = alpha_emit_set_long_const (sp_adj2, frame_size);
+	      if (!sp_adj1)
+		abort ();
+#else
+	      abort ();
+#endif
+	    }
+	  sp_adj2 = stack_pointer_rtx;
+	}
+
+      /* From now on, things must be in order.  So emit blockages.  */
+
+      /* Restore the frame pointer.  */
+      if (fp_is_frame_pointer)
+	{
+	  emit_insn (gen_blockage ());
+	  emit_move_insn (hard_frame_pointer_rtx,
+			  gen_rtx_MEM (DImode,
+				       plus_constant(sa_reg, fp_offset)));
+	}
+      else if (TARGET_OPEN_VMS)
+	{
+	  emit_insn (gen_blockage ());
+	  emit_move_insn (hard_frame_pointer_rtx,
+			  gen_rtx_REG (DImode, vms_save_fp_regno));
+	}
 
-      /* Finally return to the caller.  */
-      fprintf (file, "\tret $31,($26),1\n");
+      /* Restore the stack pointer.  */
+      emit_insn (gen_blockage ());
+      emit_move_insn (stack_pointer_rtx,
+		      gen_rtx_PLUS (DImode, sp_adj1, sp_adj2));
+    }
+  else 
+    {
+      if (TARGET_OPEN_VMS && !vms_is_stack_procedure)
+        {
+          emit_insn (gen_blockage ());
+          emit_move_insn (hard_frame_pointer_rtx,
+			  gen_rtx_REG (DImode, vms_save_fp_regno));
+        }
     }
 
+  /* Return.  */
+  emit_jump_insn (gen_return_internal ());
+}
+
+/* Output the rest of the textual info surrounding the epilogue.  */
+
+void
+alpha_end_function (file, fnname, decl)
+     FILE *file;
+     char *fnname;
+     tree decl ATTRIBUTE_UNUSED;
+{
   /* End the function.  */
-  fprintf (file, "\t.end ");
-  assemble_name (file, alpha_function_name);
-  fprintf (file, "\n");
+  if (!flag_inhibit_size_directive)
+    {
+      fputs ("\t.end ", file);
+      assemble_name (file, fnname);
+      putc ('\n', file);
+    }
   inside_function = FALSE;
 
-  /* Show that we know this function if it is called again.  */
-  SYMBOL_REF_FLAG (XEXP (DECL_RTL (current_function_decl), 0)) = 1;
+  /* Show that we know this function if it is called again. 
+
+     Don't do this for global functions in object files destined for a
+     shared library because the function may be overridden by the application
+     or other libraries.
+     ??? Is this just ELF?  */
+
+  if (!flag_pic || !TREE_PUBLIC (current_function_decl))
+    SYMBOL_REF_FLAG (XEXP (DECL_RTL (current_function_decl), 0)) = 1;
 }
 
 /* Debugging support.  */
@@ -1655,7 +3872,7 @@ alpha_output_filename (stream, name)
 	fprintf (stream, "\t#@stabs\n");
     }
 
-  else if (!TARGET_GAS && write_symbols == DBX_DEBUG)
+  else if (write_symbols == DBX_DEBUG)
     {
       ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
       fprintf (stream, "%s ", ASM_STABS_OP);
@@ -1664,7 +3881,7 @@ alpha_output_filename (stream, name)
     }
 
   else if (name != current_function_file
-      && strcmp (name, current_function_file) != 0)
+	   && strcmp (name, current_function_file) != 0)
     {
       if (inside_function && ! TARGET_GAS)
 	fprintf (stream, "\t#.file\t%d ", num_source_filenames);
@@ -1687,7 +3904,7 @@ alpha_output_lineno (stream, line)
      FILE *stream;
      int line;
 {
-  if (! TARGET_GAS && write_symbols == DBX_DEBUG)
+  if (write_symbols == DBX_DEBUG)
     {
       /* mips-tfile doesn't understand .stabd directives.  */
       ++sym_lineno;
@@ -1697,3 +3914,543 @@ alpha_output_lineno (stream, line)
   else
     fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
 }
+
+/* Structure to show the current status of registers and memory.  */
+
+struct shadow_summary
+{
+  struct {
+    unsigned long i     : 31;	/* Mask of int regs */
+    unsigned long fp    : 31;	/* Mask of fp regs */
+    unsigned long mem   :  1;	/* mem == imem | fpmem */
+  } used, defd;
+};
+
+static void summarize_insn PROTO((rtx, struct shadow_summary *, int));
+static void alpha_handle_trap_shadows PROTO((rtx));
+
+/* Summary the effects of expression X on the machine.  Update SUM, a pointer
+   to the summary structure.  SET is nonzero if the insn is setting the
+   object, otherwise zero.  */
+
+static void
+summarize_insn (x, sum, set)
+     rtx x;
+     struct shadow_summary *sum;
+     int set;
+{
+  char *format_ptr;
+  int i, j;
+
+  if (x == 0)
+    return;
+
+  switch (GET_CODE (x))
+    {
+      /* ??? Note that this case would be incorrect if the Alpha had a
+	 ZERO_EXTRACT in SET_DEST.  */
+    case SET:
+      summarize_insn (SET_SRC (x), sum, 0);
+      summarize_insn (SET_DEST (x), sum, 1);
+      break;
+
+    case CLOBBER:
+      summarize_insn (XEXP (x, 0), sum, 1);
+      break;
+
+    case USE:
+      summarize_insn (XEXP (x, 0), sum, 0);
+      break;
+
+    case ASM_OPERANDS:
+      for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--)
+	summarize_insn (ASM_OPERANDS_INPUT (x, i), sum, 0);
+      break;
+
+    case PARALLEL:
+      for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
+	summarize_insn (XVECEXP (x, 0, i), sum, 0);
+      break;
+
+    case SUBREG:
+      summarize_insn (SUBREG_REG (x), sum, 0);
+      break;
+
+    case REG:
+      {
+	int regno = REGNO (x);
+	unsigned long mask = 1UL << (regno % 32);
+
+	if (regno == 31 || regno == 63)
+	  break;
+
+	if (set)
+	  {
+	    if (regno < 32)
+	      sum->defd.i |= mask;
+	    else
+	      sum->defd.fp |= mask;
+	  }
+	else
+	  {
+	    if (regno < 32)
+	      sum->used.i  |= mask;
+	    else
+	      sum->used.fp |= mask;
+	  }
+	}
+      break;
+
+    case MEM:
+      if (set)
+	sum->defd.mem = 1;
+      else
+	sum->used.mem = 1;
+
+      /* Find the regs used in memory address computation: */
+      summarize_insn (XEXP (x, 0), sum, 0);
+      break;
+
+    case CONST_INT:   case CONST_DOUBLE:
+    case SYMBOL_REF:  case LABEL_REF:     case CONST:
+      break;
+
+      /* Handle common unary and binary ops for efficiency.  */
+    case COMPARE:  case PLUS:    case MINUS:   case MULT:      case DIV:
+    case MOD:      case UDIV:    case UMOD:    case AND:       case IOR:
+    case XOR:      case ASHIFT:  case ROTATE:  case ASHIFTRT:  case LSHIFTRT:
+    case ROTATERT: case SMIN:    case SMAX:    case UMIN:      case UMAX:
+    case NE:       case EQ:      case GE:      case GT:        case LE:
+    case LT:       case GEU:     case GTU:     case LEU:       case LTU:
+      summarize_insn (XEXP (x, 0), sum, 0);
+      summarize_insn (XEXP (x, 1), sum, 0);
+      break;
+
+    case NEG:  case NOT:  case SIGN_EXTEND:  case ZERO_EXTEND:
+    case TRUNCATE:  case FLOAT_EXTEND:  case FLOAT_TRUNCATE:  case FLOAT:
+    case FIX:  case UNSIGNED_FLOAT:  case UNSIGNED_FIX:  case ABS:
+    case SQRT:  case FFS: 
+      summarize_insn (XEXP (x, 0), sum, 0);
+      break;
+
+    default:
+      format_ptr = GET_RTX_FORMAT (GET_CODE (x));
+      for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
+	switch (format_ptr[i])
+	  {
+	  case 'e':
+	    summarize_insn (XEXP (x, i), sum, 0);
+	    break;
+
+	  case 'E':
+	    for (j = XVECLEN (x, i) - 1; j >= 0; j--)
+	      summarize_insn (XVECEXP (x, i, j), sum, 0);
+	    break;
+
+	  case 'i':
+	    break;
+
+	  default:
+	    abort ();
+	  }
+    }
+}
+
+/* Ensure a sufficient number of `trapb' insns are in the code when
+   the user requests code with a trap precision of functions or
+   instructions.
+
+   In naive mode, when the user requests a trap-precision of
+   "instruction", a trapb is needed after every instruction that may
+   generate a trap.  This ensures that the code is resumption safe but
+   it is also slow.
+
+   When optimizations are turned on, we delay issuing a trapb as long
+   as possible.  In this context, a trap shadow is the sequence of
+   instructions that starts with a (potentially) trap generating
+   instruction and extends to the next trapb or call_pal instruction
+   (but GCC never generates call_pal by itself).  We can delay (and
+   therefore sometimes omit) a trapb subject to the following
+   conditions:
+
+   (a) On entry to the trap shadow, if any Alpha register or memory
+   location contains a value that is used as an operand value by some
+   instruction in the trap shadow (live on entry), then no instruction
+   in the trap shadow may modify the register or memory location.
+
+   (b) Within the trap shadow, the computation of the base register
+   for a memory load or store instruction may not involve using the
+   result of an instruction that might generate an UNPREDICTABLE
+   result.
+
+   (c) Within the trap shadow, no register may be used more than once
+   as a destination register.  (This is to make life easier for the
+   trap-handler.)
+
+   (d) The trap shadow may not include any branch instructions.  */
+
+static void
+alpha_handle_trap_shadows (insns)
+     rtx insns;
+{
+  struct shadow_summary shadow;
+  int trap_pending, exception_nesting;
+  rtx i;
+
+  if (alpha_tp == ALPHA_TP_PROG && !flag_exceptions)
+    return;
+
+  trap_pending = 0;
+  exception_nesting = 0;
+  shadow.used.i = 0;
+  shadow.used.fp = 0;
+  shadow.used.mem = 0;
+  shadow.defd = shadow.used;
+  
+  for (i = insns; i ; i = NEXT_INSN (i))
+    {
+      if (GET_CODE (i) == NOTE)
+	{
+	  switch (NOTE_LINE_NUMBER (i))
+	    {
+	    case NOTE_INSN_EH_REGION_BEG:
+	      exception_nesting++;
+	      if (trap_pending)
+		goto close_shadow;
+	      break;
+
+	    case NOTE_INSN_EH_REGION_END:
+	      exception_nesting--;
+	      if (trap_pending)
+		goto close_shadow;
+	      break;
+
+	    case NOTE_INSN_EPILOGUE_BEG:
+	      if (trap_pending && alpha_tp >= ALPHA_TP_FUNC)
+		goto close_shadow;
+	      break;
+	    }
+	}
+      else if (trap_pending)
+	{
+	  if (alpha_tp == ALPHA_TP_FUNC)
+	    {
+	      if (GET_CODE (i) == JUMP_INSN
+		  && GET_CODE (PATTERN (i)) == RETURN)
+		goto close_shadow;
+	    }
+	  else if (alpha_tp == ALPHA_TP_INSN)
+	    {
+	      if (optimize > 0)
+		{
+		  struct shadow_summary sum;
+
+		  sum.used.i = 0;
+		  sum.used.fp = 0;
+		  sum.used.mem = 0;
+		  sum.defd = sum.used;
+
+		  switch (GET_CODE (i))
+		    {
+		    case INSN:
+		      /* Annoyingly, get_attr_trap will abort on these.  */
+		      if (GET_CODE (PATTERN (i)) == USE
+			  || GET_CODE (PATTERN (i)) == CLOBBER)
+			break;
+
+		      summarize_insn (PATTERN (i), &sum, 0);
+
+		      if ((sum.defd.i & shadow.defd.i)
+			  || (sum.defd.fp & shadow.defd.fp))
+			{
+			  /* (c) would be violated */
+			  goto close_shadow;
+			}
+
+		      /* Combine shadow with summary of current insn: */
+		      shadow.used.i   |= sum.used.i;
+		      shadow.used.fp  |= sum.used.fp;
+		      shadow.used.mem |= sum.used.mem;
+		      shadow.defd.i   |= sum.defd.i;
+		      shadow.defd.fp  |= sum.defd.fp;
+		      shadow.defd.mem |= sum.defd.mem;
+
+		      if ((sum.defd.i & shadow.used.i)
+			  || (sum.defd.fp & shadow.used.fp)
+			  || (sum.defd.mem & shadow.used.mem))
+			{
+			  /* (a) would be violated (also takes care of (b))  */
+			  if (get_attr_trap (i) == TRAP_YES
+			      && ((sum.defd.i & sum.used.i)
+				  || (sum.defd.fp & sum.used.fp)))
+			    abort ();
+
+			  goto close_shadow;
+			}
+		      break;
+
+		    case JUMP_INSN:
+		    case CALL_INSN:
+		    case CODE_LABEL:
+		      goto close_shadow;
+
+		    default:
+		      abort ();
+		    }
+		}
+	      else
+		{
+		close_shadow:
+		  emit_insn_before (gen_trapb (), i);
+		  trap_pending = 0;
+		  shadow.used.i = 0;
+		  shadow.used.fp = 0;
+		  shadow.used.mem = 0;
+		  shadow.defd = shadow.used;
+		}
+	    }
+	}
+
+      if ((exception_nesting > 0 || alpha_tp >= ALPHA_TP_FUNC)
+	  && GET_CODE (i) == INSN
+	  && GET_CODE (PATTERN (i)) != USE
+	  && GET_CODE (PATTERN (i)) != CLOBBER
+	  && get_attr_trap (i) == TRAP_YES)
+	{
+	  if (optimize && !trap_pending)
+	    summarize_insn (PATTERN (i), &shadow, 0);
+	  trap_pending = 1;
+	}
+    }
+}
+
+/* Machine dependant reorg pass.  */
+
+void
+alpha_reorg (insns)
+     rtx insns;
+{
+  alpha_handle_trap_shadows (insns);
+}
+
+
+/* Check a floating-point value for validity for a particular machine mode.  */
+
+static char * const float_strings[] =
+{
+  /* These are for FLOAT_VAX.  */
+   "1.70141173319264430e+38", /* 2^127 (2^24 - 1) / 2^24 */
+  "-1.70141173319264430e+38",
+   "2.93873587705571877e-39", /* 2^-128 */
+  "-2.93873587705571877e-39",
+  /* These are for the default broken IEEE mode, which traps
+     on infinity or denormal numbers.  */
+   "3.402823466385288598117e+38", /* 2^128 (1 - 2^-24) */
+  "-3.402823466385288598117e+38",
+   "1.1754943508222875079687e-38", /* 2^-126 */
+  "-1.1754943508222875079687e-38",
+};
+
+static REAL_VALUE_TYPE float_values[8];
+static int inited_float_values = 0;
+
+int
+check_float_value (mode, d, overflow)
+     enum machine_mode mode;
+     REAL_VALUE_TYPE *d;
+     int overflow ATTRIBUTE_UNUSED;
+{
+
+  if (TARGET_IEEE || TARGET_IEEE_CONFORMANT || TARGET_IEEE_WITH_INEXACT)
+    return 0;
+
+  if (inited_float_values == 0)
+    {
+      int i;
+      for (i = 0; i < 8; i++)
+	float_values[i] = REAL_VALUE_ATOF (float_strings[i], DFmode);
+
+      inited_float_values = 1;
+    }
+
+  if (mode == SFmode)
+    {
+      REAL_VALUE_TYPE r;
+      REAL_VALUE_TYPE *fvptr;
+
+      if (TARGET_FLOAT_VAX)
+	fvptr = &float_values[0];
+      else
+	fvptr = &float_values[4];
+
+      bcopy ((char *) d, (char *) &r, sizeof (REAL_VALUE_TYPE));
+      if (REAL_VALUES_LESS (fvptr[0], r))
+	{
+	  bcopy ((char *) &fvptr[0], (char *) d,
+		 sizeof (REAL_VALUE_TYPE));
+	  return 1;
+	}
+      else if (REAL_VALUES_LESS (r, fvptr[1]))
+	{
+	  bcopy ((char *) &fvptr[1], (char *) d,
+		 sizeof (REAL_VALUE_TYPE));
+	  return 1;
+	}
+      else if (REAL_VALUES_LESS (dconst0, r)
+		&& REAL_VALUES_LESS (r, fvptr[2]))
+	{
+	  bcopy ((char *) &dconst0, (char *) d, sizeof (REAL_VALUE_TYPE));
+	  return 1;
+	}
+      else if (REAL_VALUES_LESS (r, dconst0)
+		&& REAL_VALUES_LESS (fvptr[3], r))
+	{
+	  bcopy ((char *) &dconst0, (char *) d, sizeof (REAL_VALUE_TYPE));
+	  return 1;
+	}
+    }
+
+  return 0;
+}
+
+#if OPEN_VMS
+
+/* Return the VMS argument type corresponding to MODE.  */
+
+enum avms_arg_type
+alpha_arg_type (mode)
+     enum machine_mode mode;
+{
+  switch (mode)
+    {
+    case SFmode:
+      return TARGET_FLOAT_VAX ? FF : FS;
+    case DFmode:
+      return TARGET_FLOAT_VAX ? FD : FT;
+    default:
+      return I64;
+    }
+}
+
+/* Return an rtx for an integer representing the VMS Argument Information
+   register value.  */
+
+struct rtx_def *
+alpha_arg_info_reg_val (cum)
+     CUMULATIVE_ARGS cum;
+{
+  unsigned HOST_WIDE_INT regval = cum.num_args;
+  int i;
+
+  for (i = 0; i < 6; i++)
+    regval |= ((int) cum.atypes[i]) << (i * 3 + 8);
+
+  return GEN_INT (regval);
+}
+
+/* Structure to collect function names for final output
+   in link section.  */
+
+enum links_kind {KIND_UNUSED, KIND_LOCAL, KIND_EXTERN};
+
+
+struct alpha_links {
+  struct alpha_links *next;
+  char *name;
+  enum links_kind kind;
+};
+
+static struct alpha_links *alpha_links_base = 0;
+
+/* Make (or fake) .linkage entry for function call.
+
+   IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.  */
+
+void
+alpha_need_linkage (name, is_local)
+    char *name;
+    int is_local;
+{
+  rtx x;
+  struct alpha_links *lptr, *nptr;
+
+  if (name[0] == '*')
+    name++;
+
+  /* Is this name already defined ?  */
+
+  for (lptr = alpha_links_base; lptr; lptr = lptr->next)
+    if (strcmp (lptr->name, name) == 0)
+      {
+	if (is_local)
+	  {
+	    /* Defined here but external assumed.  */
+	    if (lptr->kind == KIND_EXTERN)
+	      lptr->kind = KIND_LOCAL;
+	  }
+	else
+	  {
+	    /* Used here but unused assumed.  */
+	    if (lptr->kind == KIND_UNUSED)
+	      lptr->kind = KIND_LOCAL;
+	  }
+	return;
+      }
+
+  nptr = (struct alpha_links *) xmalloc (sizeof (struct alpha_links));
+  nptr->next = alpha_links_base;
+  nptr->name = xstrdup (name);
+
+  /* Assume external if no definition.  */
+  nptr->kind = (is_local ? KIND_UNUSED : KIND_EXTERN);
+
+  /* Ensure we have an IDENTIFIER so assemble_name can mark is used.  */
+  get_identifier (name);
+
+  alpha_links_base = nptr;
+
+  return;
+}
+
+
+void
+alpha_write_linkage (stream)
+    FILE *stream;
+{
+  struct alpha_links *lptr, *nptr;
+
+  readonly_section ();
+
+  fprintf (stream, "\t.align 3\n");
+
+  for (lptr = alpha_links_base; lptr; lptr = nptr)
+    {
+      nptr = lptr->next;
+
+      if (lptr->kind == KIND_UNUSED
+	  || ! TREE_SYMBOL_REFERENCED (get_identifier (lptr->name)))
+	continue;
+
+      fprintf (stream, "$%s..lk:\n", lptr->name);
+      if (lptr->kind == KIND_LOCAL)   
+	{
+	  /*  Local and used, build linkage pair.  */
+	  fprintf (stream, "\t.quad %s..en\n", lptr->name);
+	  fprintf (stream, "\t.quad %s\n", lptr->name);
+	}
+      else
+	/* External and used, request linkage pair.  */
+	fprintf (stream, "\t.linkage %s\n", lptr->name);
+    }
+}
+
+#else
+
+void
+alpha_need_linkage (name, is_local)
+     char *name ATTRIBUTE_UNUSED;
+     int is_local ATTRIBUTE_UNUSED;
+{
+}
+
+#endif /* OPEN_VMS */
diff --git a/contrib/gcc/config/alpha/alpha.h b/contrib/gcc/config/alpha/alpha.h
index 9504c09a1ad5..43b0deed743f 100644
--- a/contrib/gcc/config/alpha/alpha.h
+++ b/contrib/gcc/config/alpha/alpha.h
@@ -1,5 +1,5 @@
 /* Definitions of target machine for GNU compiler, for DEC Alpha.
-   Copyright (C) 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
+   Copyright (C) 1992, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
    Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
 
 This file is part of GNU CC.
@@ -20,21 +20,21 @@ the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
 
-/* Names to predefine in the preprocessor for this target machine.  */
-
-#define CPP_PREDEFINES "\
--Dunix -D__osf__ -D__alpha -D__alpha__ -D_LONGLONG -DSYSTYPE_BSD  \
--D_SYSTYPE_BSD -Asystem(unix) -Asystem(xpg4) -Acpu(alpha) -Amachine(alpha)"
-
 /* Write out the correct language type definition for the header files.  
    Unless we have assembler language, write out the symbols for C.  */
 #define CPP_SPEC "\
-%{!.S:	-D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}}  \
-%{.S:	-D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
-%{.cc:	-D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus} \
-%{.cxx:	-D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus} \
-%{.C:	-D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus} \
-%{.m:	-D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C}"
+%{!undef:\
+%{.S:-D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY }}\
+%{.cc|.cxx|.C:-D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus }\
+%{.m:-D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C }\
+%{!.S:%{!.cc:%{!.cxx:%{!.C:%{!.m:-D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C }}}}}}\
+%{mieee:-D_IEEE_FP }\
+%{mieee-with-inexact:-D_IEEE_FP -D_IEEE_FP_INEXACT }}\
+%(cpp_cpu) %(cpp_subtarget)"
+
+#ifndef CPP_SUBTARGET_SPEC
+#define CPP_SUBTARGET_SPEC ""
+#endif
 
 /* Set the spec to use for signed char.  The default tests the above macro
    but DEC's compiler can't handle the conditional in a "constant"
@@ -42,18 +42,6 @@ Boston, MA 02111-1307, USA.  */
 
 #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
 
-/* Under OSF/1, -p and -pg require -lprof1.  */
-
-#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} %{a:-lprof2} -lc"
-
-/* Pass "-G 8" to ld because Alpha's CC does.  Pass -O3 if we are
-   optimizing, -O1 if we are not.  Pass -shared, -non_shared or
-   -call_shared as appropriate.  Also pass -pg.  */
-#define LINK_SPEC  \
-  "-G 8 %{O*:-O3} %{!O*:-O1} %{static:-non_shared} \
-   %{!static:%{shared:-shared} %{!shared:-call_shared}} %{pg} %{taso} \
-   %{rpath*}"
-
 #define WORD_SWITCH_TAKES_ARG(STR)		\
  (!strcmp (STR, "rpath") || !strcmp (STR, "include")	\
   || !strcmp (STR, "imacros") || !strcmp (STR, "aux-info") \
@@ -61,62 +49,296 @@ Boston, MA 02111-1307, USA.  */
   || !strcmp (STR, "iwithprefix") || !strcmp (STR, "iwithprefixbefore") \
   || !strcmp (STR, "isystem"))
 
-#define STARTFILE_SPEC  \
-  "%{!shared:%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}}"
-
 /* Print subsidiary information on the compiler version in use.  */
 #define TARGET_VERSION
 
-/* Default this to not be compiling for Windows/NT.  */
-#ifndef WINDOWS_NT
-#define WINDOWS_NT 0
-#endif
-
-/* Define the location for the startup file on OSF/1 for Alpha.  */
-
-#define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
-
 /* Run-time compilation parameters selecting different hardware subsets.  */
 
+/* Which processor to schedule for. The cpu attribute defines a list that
+   mirrors this list, so changes to alpha.md must be made at the same time.  */
+
+enum processor_type
+ {PROCESSOR_EV4,			/* 2106[46]{a,} */
+  PROCESSOR_EV5,			/* 21164{a,pc,} */
+  PROCESSOR_EV6};			/* 21264 */
+
+extern enum processor_type alpha_cpu;
+
+enum alpha_trap_precision
+{
+  ALPHA_TP_PROG,	/* No precision (default).  */
+  ALPHA_TP_FUNC,      	/* Trap contained within originating function.  */
+  ALPHA_TP_INSN		/* Instruction accuracy and code is resumption safe. */
+};
+
+enum alpha_fp_rounding_mode
+{
+  ALPHA_FPRM_NORM,	/* Normal rounding mode.  */
+  ALPHA_FPRM_MINF,	/* Round towards minus-infinity.  */
+  ALPHA_FPRM_CHOP,	/* Chopped rounding mode (towards 0). */
+  ALPHA_FPRM_DYN	/* Dynamic rounding mode.  */
+};
+
+enum alpha_fp_trap_mode
+{
+  ALPHA_FPTM_N,		/* Normal trap mode. */
+  ALPHA_FPTM_U,		/* Underflow traps enabled.  */
+  ALPHA_FPTM_SU,	/* Software completion, w/underflow traps */
+  ALPHA_FPTM_SUI	/* Software completion, w/underflow & inexact traps */
+};
+
 extern int target_flags;
 
+extern enum alpha_trap_precision alpha_tp;
+extern enum alpha_fp_rounding_mode alpha_fprm;
+extern enum alpha_fp_trap_mode alpha_fptm;
+
 /* This means that floating-point support exists in the target implementation
    of the Alpha architecture.  This is usually the default.  */
 
-#define TARGET_FP	(target_flags & 1)
+#define MASK_FP		1
+#define TARGET_FP	(target_flags & MASK_FP)
 
 /* This means that floating-point registers are allowed to be used.  Note
    that Alpha implementations without FP operations are required to
    provide the FP registers.  */
 
-#define TARGET_FPREGS	(target_flags & 2)
+#define MASK_FPREGS	2
+#define TARGET_FPREGS	(target_flags & MASK_FPREGS)
 
 /* This means that gas is used to process the assembler file.  */
 
 #define MASK_GAS 4
 #define TARGET_GAS	(target_flags & MASK_GAS)
 
+/* This means that we should mark procedures as IEEE conformant. */
+
+#define MASK_IEEE_CONFORMANT 8
+#define TARGET_IEEE_CONFORMANT	(target_flags & MASK_IEEE_CONFORMANT)
+
+/* This means we should be IEEE-compliant except for inexact.  */
+
+#define MASK_IEEE	16
+#define TARGET_IEEE	(target_flags & MASK_IEEE)
+
+/* This means we should be fully IEEE-compliant.  */
+
+#define MASK_IEEE_WITH_INEXACT 32
+#define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)
+
+/* This means we must construct all constants rather than emitting
+   them as literal data.  */
+
+#define MASK_BUILD_CONSTANTS 128
+#define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)
+
+/* This means we handle floating points in VAX F- (float)
+   or G- (double) Format.  */
+
+#define MASK_FLOAT_VAX 512
+#define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)
+
+/* This means that the processor has byte and half word loads and stores
+   (the BWX extension).  */
+
+#define MASK_BWX 1024
+#define TARGET_BWX	(target_flags & MASK_BWX)
+
+/* This means that the processor has the CIX extension.  */
+#define MASK_CIX 2048
+#define TARGET_CIX	(target_flags & MASK_CIX)
+
+/* This means that the processor has the MAX extension.  */
+#define MASK_MAX 4096
+#define TARGET_MAX	(target_flags & MASK_MAX)
+
+/* This means that the processor is an EV5, EV56, or PCA56.  This is defined
+   only in TARGET_CPU_DEFAULT.  */
+#define MASK_CPU_EV5 8192
+
+/* Likewise for EV6.  */
+#define MASK_CPU_EV6 16384
+
+/* This means we support the .arch directive in the assembler.  Only
+   defined in TARGET_CPU_DEFAULT.  */
+#define MASK_SUPPORT_ARCH 32768
+#define TARGET_SUPPORT_ARCH	(target_flags & MASK_SUPPORT_ARCH)
+
+/* These are for target os support and cannot be changed at runtime.  */
+#ifndef TARGET_WINDOWS_NT
+#define TARGET_WINDOWS_NT 0
+#endif
+#ifndef TARGET_OPEN_VMS
+#define TARGET_OPEN_VMS 0
+#endif
+
+#ifndef TARGET_AS_CAN_SUBTRACT_LABELS
+#define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS
+#endif
+#ifndef TARGET_CAN_FAULT_IN_PROLOGUE
+#define TARGET_CAN_FAULT_IN_PROLOGUE 0
+#endif
+
 /* Macro to define tables used to set the flags.
    This is a list in braces of pairs in braces,
    each pair being { "NAME", VALUE }
    where VALUE is the bits to set or minus the bits to clear.
    An empty string NAME is used to identify the default VALUE.  */
 
-#define TARGET_SWITCHES			\
-  { {"no-soft-float", 1},		\
-    {"soft-float", -1},			\
-    {"fp-regs", 2},			\
-    {"no-fp-regs", -3},			\
-    {"alpha-as", -MASK_GAS},		\
-    {"gas", MASK_GAS},			\
+#define TARGET_SWITCHES				\
+  { {"no-soft-float", MASK_FP},			\
+    {"soft-float", - MASK_FP},			\
+    {"fp-regs", MASK_FPREGS},			\
+    {"no-fp-regs", - (MASK_FP|MASK_FPREGS)},	\
+    {"alpha-as", -MASK_GAS},			\
+    {"gas", MASK_GAS},				\
+    {"ieee-conformant", MASK_IEEE_CONFORMANT},	\
+    {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT},	\
+    {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT}, \
+    {"build-constants", MASK_BUILD_CONSTANTS},  \
+    {"float-vax", MASK_FLOAT_VAX},		\
+    {"float-ieee", -MASK_FLOAT_VAX},		\
+    {"bwx", MASK_BWX},				\
+    {"no-bwx", -MASK_BWX},			\
+    {"cix", MASK_CIX},				\
+    {"no-cix", -MASK_CIX},			\
+    {"max", MASK_MAX},				\
+    {"no-max", -MASK_MAX},			\
     {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT} }
 
-#define TARGET_DEFAULT 3
+#define TARGET_DEFAULT MASK_FP|MASK_FPREGS
 
 #ifndef TARGET_CPU_DEFAULT
 #define TARGET_CPU_DEFAULT 0
 #endif
 
+/* This macro is similar to `TARGET_SWITCHES' but defines names of
+   command options that have values.  Its definition is an initializer
+   with a subgrouping for each command option.
+
+   Each subgrouping contains a string constant, that defines the fixed
+   part of the option name, and the address of a variable.  The
+   variable, type `char *', is set to the variable part of the given
+   option if the fixed part matches.  The actual option name is made
+   by appending `-m' to the specified name.
+
+   Here is an example which defines `-mshort-data-NUMBER'.  If the
+   given option is `-mshort-data-512', the variable `m88k_short_data'
+   will be set to the string `"512"'.
+
+	extern char *m88k_short_data;
+	#define TARGET_OPTIONS { { "short-data-", &m88k_short_data } }  */
+
+extern char *alpha_cpu_string;  /* For -mcpu= */
+extern char *alpha_fprm_string;	/* For -mfp-rounding-mode=[n|m|c|d] */
+extern char *alpha_fptm_string;	/* For -mfp-trap-mode=[n|u|su|sui]  */
+extern char *alpha_tp_string;	/* For -mtrap-precision=[p|f|i] */
+extern char *alpha_mlat_string;	/* For -mmemory-latency= */
+
+#define TARGET_OPTIONS				\
+{						\
+  {"cpu=",		&alpha_cpu_string},	\
+  {"fp-rounding-mode=",	&alpha_fprm_string},	\
+  {"fp-trap-mode=",	&alpha_fptm_string},	\
+  {"trap-precision=",	&alpha_tp_string},	\
+  {"memory-latency=",	&alpha_mlat_string},	\
+}
+
+/* Attempt to describe CPU characteristics to the preprocessor.  */
+
+/* Corresponding to amask... */
+#define CPP_AM_BWX_SPEC	"-D__alpha_bwx__ -Acpu(bwx)"
+#define CPP_AM_MAX_SPEC	"-D__alpha_max__ -Acpu(max)"
+#define CPP_AM_CIX_SPEC	"-D__alpha_cix__ -Acpu(cix)"
+
+/* Corresponding to implver... */
+#define CPP_IM_EV4_SPEC	"-D__alpha_ev4__ -Acpu(ev4)"
+#define CPP_IM_EV5_SPEC	"-D__alpha_ev5__ -Acpu(ev5)"
+#define CPP_IM_EV6_SPEC	"-D__alpha_ev6__ -Acpu(ev6)"
+
+/* Common combinations.  */
+#define CPP_CPU_EV4_SPEC	"%(cpp_im_ev4)"
+#define CPP_CPU_EV5_SPEC	"%(cpp_im_ev5)"
+#define CPP_CPU_EV56_SPEC	"%(cpp_im_ev5) %(cpp_am_bwx)"
+#define CPP_CPU_PCA56_SPEC	"%(cpp_im_ev5) %(cpp_am_bwx) %(cpp_am_max)"
+#define CPP_CPU_EV6_SPEC	"%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_cix)"
+
+#ifndef CPP_CPU_DEFAULT_SPEC
+# if TARGET_CPU_DEFAULT & MASK_CPU_EV6
+#  define CPP_CPU_DEFAULT_SPEC		CPP_CPU_EV6_SPEC
+# else
+#  if TARGET_CPU_DEFAULT & MASK_CPU_EV5
+#   if TARGET_CPU_DEFAULT & MASK_MAX
+#    define CPP_CPU_DEFAULT_SPEC	CPP_CPU_PCA56_SPEC
+#   else
+#    if TARGET_CPU_DEFAULT & MASK_BWX
+#     define CPP_CPU_DEFAULT_SPEC	CPP_CPU_EV56_SPEC
+#    else
+#     define CPP_CPU_DEFAULT_SPEC	CPP_CPU_EV5_SPEC
+#    endif
+#   endif
+#  else
+#   define CPP_CPU_DEFAULT_SPEC		CPP_CPU_EV4_SPEC
+#  endif
+# endif
+#endif /* CPP_CPU_DEFAULT_SPEC */
+
+#ifndef CPP_CPU_SPEC
+#define CPP_CPU_SPEC "\
+%{!undef:-Acpu(alpha) -Amachine(alpha) -D__alpha -D__alpha__ \
+%{mcpu=ev4|mcpu=21064:%(cpp_cpu_ev4) }\
+%{mcpu=ev5|mcpu=21164:%(cpp_cpu_ev5) }\
+%{mcpu=ev56|mcpu=21164a:%(cpp_cpu_ev56) }\
+%{mcpu=pca56|mcpu=21164pc|mcpu=21164PC:%(cpp_cpu_pca56) }\
+%{mcpu=ev6|mcpu=21264:%(cpp_cpu_ev6) }\
+%{!mcpu*:%(cpp_cpu_default) }}"
+#endif
+
+/* This macro defines names of additional specifications to put in the
+   specs that can be used in various specifications like CC1_SPEC.  Its
+   definition is an initializer with a subgrouping for each command option.
+
+   Each subgrouping contains a string constant, that defines the
+   specification name, and a string constant that used by the GNU CC driver
+   program.
+
+   Do not define this macro if it does not need to do anything.  */
+
+#ifndef SUBTARGET_EXTRA_SPECS
+#define SUBTARGET_EXTRA_SPECS
+#endif
+
+#define EXTRA_SPECS				\
+  { "cpp_am_bwx", CPP_AM_BWX_SPEC },		\
+  { "cpp_am_max", CPP_AM_MAX_SPEC },		\
+  { "cpp_am_cix", CPP_AM_CIX_SPEC },		\
+  { "cpp_im_ev4", CPP_IM_EV4_SPEC },		\
+  { "cpp_im_ev5", CPP_IM_EV5_SPEC },		\
+  { "cpp_im_ev6", CPP_IM_EV6_SPEC },		\
+  { "cpp_cpu_ev4", CPP_CPU_EV4_SPEC },		\
+  { "cpp_cpu_ev5", CPP_CPU_EV5_SPEC },		\
+  { "cpp_cpu_ev56", CPP_CPU_EV56_SPEC },	\
+  { "cpp_cpu_pca56", CPP_CPU_PCA56_SPEC },	\
+  { "cpp_cpu_ev6", CPP_CPU_EV6_SPEC },		\
+  { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC },	\
+  { "cpp_cpu", CPP_CPU_SPEC },			\
+  { "cpp_subtarget", CPP_SUBTARGET_SPEC },	\
+  SUBTARGET_EXTRA_SPECS
+
+
+/* Sometimes certain combinations of command options do not make sense
+   on a particular target machine.  You can define a macro
+   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
+   defined, is executed once just after all the command options have
+   been parsed.
+
+   On the Alpha, it is used to translate target-option strings into
+   numeric values.  */
+
+extern void override_options ();
+#define OVERRIDE_OPTIONS override_options ()
+
+
 /* Define this macro to change register usage conditional on target flags.
 
    On the Alpha, we use this to disable the floating-point registers when
@@ -135,6 +357,23 @@ extern int target_flags;
 /* Define to enable software floating point emulation. */
 #define REAL_ARITHMETIC
 
+/* The following #defines are used when compiling the routines in
+   libgcc1.c.  Since the Alpha calling conventions require single
+   precision floats to be passed in the floating-point registers
+   (rather than in the general registers) we have to build the
+   libgcc1.c routines in such a way that they know the actual types
+   of their formal arguments and the actual types of their return
+   values.  Otherwise, gcc will generate calls to the libgcc1.c
+   routines, passing arguments in the floating-point registers,
+   but the libgcc1.c routines will expect their arguments on the
+   stack (where the Alpha calling conventions require structs &
+   unions to be passed).  */
+
+#define FLOAT_VALUE_TYPE	double
+#define INTIFY(FLOATVAL)	(FLOATVAL)
+#define FLOATIFY(INTVAL)	(INTVAL)
+#define FLOAT_ARG_TYPE		double
+
 /* Define the size of `int'.  The default is the same as the word size.  */
 #define INT_TYPE_SIZE 32
 
@@ -149,8 +388,8 @@ extern int target_flags;
 #define DOUBLE_TYPE_SIZE 64
 #define LONG_DOUBLE_TYPE_SIZE 64
 
-#define WCHAR_TYPE "short unsigned int"
-#define WCHAR_TYPE_SIZE 16
+#define	WCHAR_TYPE "unsigned int"
+#define	WCHAR_TYPE_SIZE 32
 
 /* Define this macro if it is advisable to hold scalars in registers
    in a wider mode than that declared by the program.  In such cases, 
@@ -220,7 +459,7 @@ extern int target_flags;
 #define STACK_BOUNDARY 64
 
 /* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY 64
+#define FUNCTION_BOUNDARY 256
 
 /* Alignment of field after `int : 0' in a structure.  */
 #define EMPTY_FIELD_BOUNDARY 64
@@ -237,31 +476,31 @@ extern int target_flags;
    we don't optimize and also if we are writing ECOFF symbols to work around
    a bug in DEC's assembler. */
 
-#define ASM_OUTPUT_LOOP_ALIGN(FILE) \
-  if (optimize > 0 && write_symbols != SDB_DEBUG)  \
-    ASM_OUTPUT_ALIGN (FILE, 5)
+#define LOOP_ALIGN(LABEL) \
+  (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
 
-/* This is how to align an instruction for optimal branching.
-   On Alpha we'll get better performance by aligning on a quadword
+/* This is how to align an instruction for optimal branching.  On
+   Alpha we'll get better performance by aligning on an octaword
    boundary.  */
 
-#define ASM_OUTPUT_ALIGN_CODE(FILE)	\
-  if (optimize > 0 && write_symbols != SDB_DEBUG) \
-    ASM_OUTPUT_ALIGN ((FILE), 4)
+#define ALIGN_LABEL_AFTER_BARRIER(FILE)	\
+  (optimize > 0 && write_symbols != SDB_DEBUG ? 4 : 0)
 
 /* No data type wants to be aligned rounder than this.  */
 #define BIGGEST_ALIGNMENT 64
 
-/* Make strings word-aligned so strcpy from constants will be faster.  */
-#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
-  (TREE_CODE (EXP) == STRING_CST	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
-
-/* Make arrays of chars word-aligned for the same reasons.  */
-#define DATA_ALIGNMENT(TYPE, ALIGN)		\
-  (TREE_CODE (TYPE) == ARRAY_TYPE		\
-   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode	\
-   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
+/* For atomic access to objects, must have at least 32-bit alignment
+   unless the machine has byte operations.  */
+#define MINIMUM_ATOMIC_ALIGNMENT (TARGET_BWX ? 8 : 32)
+
+/* Align all constants and variables to at least a word boundary so
+   we can pick up pieces of them faster.  */
+/* ??? Only if block-move stuff knows about different source/destination
+   alignment.  */
+#if 0
+#define CONSTANT_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
+#define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD)
+#endif
 
 /* Set this non-zero if move instructions will actually fail to work
    when given unaligned data.
@@ -325,11 +564,11 @@ extern int target_flags;
    listed once, even those in FIXED_REGISTERS.
 
    We allocate in the following order:
-   $f1			(nonsaved floating-point register)
-   $f10-$f15		(likewise)
+   $f10-$f15		(nonsaved floating-point register)
    $f22-$f30		(likewise)
    $f21-$f16		(likewise, but input args)
    $f0			(nonsaved, but return value)
+   $f1			(nonsaved, but immediate before saved)
    $f2-$f9		(saved floating-point registers)
    $1-$8		(nonsaved integer registers)
    $22-$25		(likewise)
@@ -344,11 +583,10 @@ extern int target_flags;
    $30, $31, $f31	(stack pointer and always zero/ap & fp)  */
 
 #define REG_ALLOC_ORDER		\
-  {33,					\
-   42, 43, 44, 45, 46, 47,		\
+  {42, 43, 44, 45, 46, 47,		\
    54, 55, 56, 57, 58, 59, 60, 61, 62,	\
    53, 52, 51, 50, 49, 48,		\
-   32,					\
+   32, 33,				\
    34, 35, 36, 37, 38, 39, 40, 41,	\
    1, 2, 3, 4, 5, 6, 7, 8,		\
    22, 23, 24, 25,			\
@@ -373,18 +611,20 @@ extern int target_flags;
 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
    On Alpha, the integer registers can hold any mode.  The floating-point
    registers can hold 32-bit and 64-bit integers as well, but not 16-bit
-   or 8-bit values.  If we only allowed the larger integers into FP registers,
-   we'd have to say that QImode and SImode aren't tiable, which is a
-   pain.  So say all registers can hold everything and see how that works.  */
+   or 8-bit values.  */
 
-#define HARD_REGNO_MODE_OK(REGNO, MODE) 1
+#define HARD_REGNO_MODE_OK(REGNO, MODE) 			\
+  ((REGNO) < 32 || ((MODE) != QImode && (MODE) != HImode))
 
 /* Value is 1 if it is a good idea to tie two pseudo registers
    when one has mode MODE1 and one has mode MODE2.
    If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
    for any hard reg, then this must be 0 for correct output.  */
 
-#define MODES_TIEABLE_P(MODE1, MODE2) 1
+#define MODES_TIEABLE_P(MODE1, MODE2) 				\
+  ((MODE1) == QImode || (MODE1) == HImode			\
+   ? (MODE2) == QImode || (MODE2) == HImode			\
+   : 1)
 
 /* Specify the registers used for certain standard purposes.
    The values of these macros are register numbers.  */
@@ -499,9 +739,7 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
    : (C) == 'J' ? (VALUE) == 0					\
    : (C) == 'K' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000	\
    : (C) == 'L' ? (((VALUE) & 0xffff) == 0			\
-		   && (((VALUE)) >> 31 == -1 || (VALUE) >> 31 == 0) \
-		   && ((HOST_BITS_PER_WIDE_INT == 64		\
-			|| (unsigned) (VALUE) != 0x80000000U)))	\
+                  && (((VALUE)) >> 31 == -1 || (VALUE) >> 31 == 0)) \
    : (C) == 'M' ? zap_mask (VALUE)				\
    : (C) == 'N' ? (unsigned HOST_WIDE_INT) (~ (VALUE)) < 0x100	\
    : (C) == 'O' ? (unsigned HOST_WIDE_INT) (- (VALUE)) < 0x100	\
@@ -526,12 +764,17 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
 
    For the Alpha, `Q' means that this is a memory operand but not a
    reference to an unaligned location.
+
    `R' is a SYMBOL_REF that has SYMBOL_REF_FLAG set or is the current
-   function.  */
+   function.
+
+   'S' is a 6-bit constant (valid for a shift insn).  */
 
 #define EXTRA_CONSTRAINT(OP, C)				\
-  ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) != AND \
-   : (C) == 'R' ? current_file_function_operand (OP, Pmode)	\
+  ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) != AND	\
+   : (C) == 'R' ? current_file_function_operand (OP, Pmode)		\
+   : (C) == 'S' ? (GET_CODE (OP) == CONST_INT				\
+		   && (unsigned HOST_WIDE_INT) INTVAL (OP) < 64)	\
    : 0)
 
 /* Given an rtx X being reloaded into a reg required to be
@@ -544,12 +787,13 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
 
 #define PREFERRED_RELOAD_CLASS(X, CLASS)		\
   (CONSTANT_P (X) && (X) != const0_rtx && (X) != CONST0_RTX (GET_MODE (X)) \
-   ? ((CLASS) == FLOAT_REGS ? NO_REGS : GENERAL_REGS)			\
+   ? ((CLASS) == FLOAT_REGS || (CLASS) == NO_REGS ? NO_REGS : GENERAL_REGS)\
    : (CLASS))
 
 /* Loading and storing HImode or QImode values to and from memory
    usually requires a scratch register.  The exceptions are loading
-   QImode and HImode from an aligned address to a general register. 
+   QImode and HImode from an aligned address to a general register
+   unless byte instructions are permitted.
    We also cannot load an unaligned address or a paradoxical SUBREG into an
    FP register.   */
 
@@ -563,7 +807,7 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
   && (((CLASS) == FLOAT_REGS						\
        && ((MODE) == SImode || (MODE) == HImode || (MODE) == QImode))	\
       || (((MODE) == QImode || (MODE) == HImode)			\
-	  && unaligned_memory_operand (IN, MODE))))			\
+	  && ! TARGET_BWX && unaligned_memory_operand (IN, MODE)))) \
  ? GENERAL_REGS								\
  : ((CLASS) == FLOAT_REGS && GET_CODE (IN) == MEM			\
     && GET_CODE (XEXP (IN, 0)) == AND) ? GENERAL_REGS			\
@@ -579,8 +823,9 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
        && (GET_CODE (SUBREG_REG (OUT)) == MEM				\
 	   || (GET_CODE (SUBREG_REG (OUT)) == REG			\
 	       && REGNO (SUBREG_REG (OUT)) >= FIRST_PSEUDO_REGISTER)))) \
-  && (((MODE) == HImode || (MODE) == QImode				\
-       || ((MODE) == SImode && (CLASS) == FLOAT_REGS))))		\
+  && ((((MODE) == HImode || (MODE) == QImode)				\
+       && (! TARGET_BWX || (CLASS) == FLOAT_REGS))			\
+      || ((MODE) == SImode && (CLASS) == FLOAT_REGS)))			\
  ? GENERAL_REGS								\
  : ((CLASS) == FLOAT_REGS && GET_CODE (OUT) == MEM			\
     && GET_CODE (XEXP (OUT, 0)) == AND) ? GENERAL_REGS			\
@@ -590,9 +835,10 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
  : NO_REGS)
 
 /* If we are copying between general and FP registers, we need a memory
-   location.  */
+   location unless the CIX extension is available.  */
 
-#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) ((CLASS1) != (CLASS2))
+#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
+ (! TARGET_CIX && (CLASS1) != (CLASS2))
 
 /* Specify the mode to be used for memory when a secondary memory
    location is needed.  If MODE is floating-point, use it.  Otherwise,
@@ -622,15 +868,18 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
    reduce the impact of not being able to allocate a pseudo to a
    hard register.  */
 
-#define REGISTER_MOVE_COST(CLASS1, CLASS2)	\
-  (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS) ? 2 : 20)
+#define REGISTER_MOVE_COST(CLASS1, CLASS2)		\
+  (((CLASS1) == FLOAT_REGS) == ((CLASS2) == FLOAT_REGS)	\
+   ? 2							\
+   : TARGET_CIX ? 3 : 4+2*alpha_memory_latency)
 
 /* A C expressions returning the cost of moving data of MODE from a register to
    or from memory.
 
    On the Alpha, bump this up a bit.  */
 
-#define MEMORY_MOVE_COST(MODE)  6
+extern int alpha_memory_latency;
+#define MEMORY_MOVE_COST(MODE,CLASS,IN)  (2*alpha_memory_latency)
 
 /* Provide the cost of a branch.  Exact meaning under development.  */
 #define BRANCH_COST 5
@@ -664,6 +913,9 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
    On Alpha, don't define this because there are no push insns.  */
 /*  #define PUSH_ROUNDING(BYTES) */
 
+/* Define this to be nonzero if stack checking is built into the ABI.  */
+#define STACK_CHECK_BUILTIN 1
+
 /* Define this if the maximum size of all the outgoing args is to be
    accumulated and pushed during the prologue.  The amount can be
    found in the variable current_function_outgoing_args_size.  */
@@ -738,18 +990,25 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
    $f0 for floating-point functions.  */
 
 #define FUNCTION_VALUE(VALTYPE, FUNC)	\
-  gen_rtx (REG,						\
-	   (INTEGRAL_MODE_P (TYPE_MODE (VALTYPE))	\
-	    && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
-	   ? word_mode : TYPE_MODE (VALTYPE),		\
-	   TARGET_FPREGS && TREE_CODE (VALTYPE) == REAL_TYPE ? 32 : 0)
+  gen_rtx (REG,							\
+	   ((INTEGRAL_TYPE_P (VALTYPE)				\
+	     && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD)	\
+	    || POINTER_TYPE_P (VALTYPE))			\
+	   ? word_mode : TYPE_MODE (VALTYPE),			\
+	   ((TARGET_FPREGS					\
+	     && (TREE_CODE (VALTYPE) == REAL_TYPE		\
+		 || TREE_CODE (VALTYPE) == COMPLEX_TYPE))	\
+	    ? 32 : 0))
 
 /* Define how to find the value returned by a library function
    assuming the value has mode MODE.  */
 
 #define LIBCALL_VALUE(MODE)	\
-   gen_rtx (REG, MODE,		\
-	    TARGET_FPREGS && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 0)
+   gen_rtx (REG, MODE,						\
+	    (TARGET_FPREGS					\
+	     && (GET_MODE_CLASS (MODE) == MODE_FLOAT		\
+		 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
+	     ? 32 : 0))
 
 /* The definition of this macro implies that there are cases where
    a scalar value cannot be returned in registers.
@@ -764,7 +1023,8 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
 /* 1 if N is a possible register number for a function value
    as seen by the caller.  */
 
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 32)
+#define FUNCTION_VALUE_REGNO_P(N)  \
+  ((N) == 0 || (N) == 1 || (N) == 32 || (N) == 33)
 
 /* 1 if N is a possible register number for function argument passing.
    On Alpha, these are $16-$21 and $f16-$f21.  */
@@ -788,7 +1048,7 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
    for a call to a function whose data type is FNTYPE.
    For a library call, FNTYPE is 0.  */
 
-#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME)  (CUM) = 0
+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT)  (CUM) = 0
 
 /* Define intermediate macro to compute the size (in registers) of an argument
    for the Alpha.  */
@@ -894,6 +1154,7 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
 		      plus_constant (virtual_incoming_args_rtx,		\
 				     (CUM) * UNITS_PER_WORD)),		\
 	     6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD);			\
+	   emit_insn (gen_blockage ());					\
 	 }								\
       PRETEND_SIZE = 12 * UNITS_PER_WORD;				\
     }									\
@@ -905,6 +1166,9 @@ enum reg_class { NO_REGS, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
    emitted.  If it would take more than N insns, zero is returned and no
    insns and emitted.  */
 extern struct rtx_def *alpha_emit_set_const ();
+extern struct rtx_def *alpha_emit_set_long_const ();
+extern struct rtx_def *alpha_emit_conditional_branch ();
+extern struct rtx_def *alpha_emit_conditional_move ();
 
 /* Generate necessary RTL for __builtin_saveregs().
    ARGLIST is the argument list; see expr.c.  */
@@ -918,25 +1182,34 @@ extern struct rtx_def *alpha_builtin_saveregs ();
 extern struct rtx_def *alpha_compare_op0, *alpha_compare_op1;
 extern int alpha_compare_fp_p;
 
-/* This macro produces the initial definition of a function name.  On the
-   Alpha, we need to save the function name for the prologue and epilogue.  */
+/* Make (or fake) .linkage entry for function call.
+   IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.  */
+extern void alpha_need_linkage ();
 
-extern char *alpha_function_name;
+/* This macro defines the start of an assembly comment.  */
 
-#define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL)	\
-{							\
-   alpha_function_name = NAME;				\
-}
+#define ASM_COMMENT_START " #"
+
+/* This macro produces the initial definition of a function.  */
+
+#define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \
+  alpha_start_function(FILE,NAME,DECL);
+extern void alpha_start_function ();
+
+/* This macro closes up a function definition for the assembler.  */
+
+#define ASM_DECLARE_FUNCTION_SIZE(FILE,NAME,DECL) \
+  alpha_end_function(FILE,NAME,DECL)
+extern void alpha_end_function ();
    
-/* This macro generates the assembly code for function entry.
-   FILE is a stdio stream to output the code to.
-   SIZE is an int: how many units of temporary storage to allocate.
-   Refer to the array `regs_ever_live' to determine which registers
-   to save; `regs_ever_live[I]' is nonzero if register number I
-   is ever used in the function.  This macro is responsible for
-   knowing which registers should not be saved even if used.  */
+/* This macro notes the end of the prologue.  */
 
-#define FUNCTION_PROLOGUE(FILE, SIZE)  output_prolog (FILE, SIZE)
+#define FUNCTION_END_PROLOGUE(FILE)  output_end_prologue (FILE)
+extern void output_end_prologue ();
+
+/* Output any profiling code before the prologue.  */
+
+#define PROFILE_BEFORE_PROLOGUE 1
 
 /* Output assembler code to FILE to increment profiler label # LABELNO
    for profiling a function entry.  Under OSF/1, profiling is enabled
@@ -986,19 +1259,6 @@ extern char *alpha_function_name;
    No definition is equivalent to always zero.  */
 
 #define EXIT_IGNORE_STACK 1
-
-/* This macro generates the assembly code for function exit,
-   on machines that need it.  If FUNCTION_EPILOGUE is not defined
-   then individual return instructions are generated for each
-   return statement.  Args are same as for FUNCTION_PROLOGUE.
-
-   The function epilogue should not depend on the current stack pointer!
-   It should use the frame pointer only.  This is mandatory because
-   of alloca; we also take advantage of it to omit stack adjustments
-   before returning.  */
-
-#define FUNCTION_EPILOGUE(FILE, SIZE)	output_epilog (FILE, SIZE)
-
 
 /* Output assembler code for a block containing the constant parts
    of a trampoline, leaving space for the variable parts.
@@ -1010,13 +1270,13 @@ extern char *alpha_function_name;
    aligned to FUNCTION_BOUNDARY, which is 64 bits.  */
 
 #define TRAMPOLINE_TEMPLATE(FILE)		\
-{						\
+do {						\
   fprintf (FILE, "\tldq $1,24($27)\n");		\
   fprintf (FILE, "\tldq $27,16($27)\n");	\
   fprintf (FILE, "\tjmp $31,($27),0\n");	\
   fprintf (FILE, "\tnop\n");			\
   fprintf (FILE, "\t.quad 0,0\n");		\
-}
+} while (0)
 
 /* Section in which to place the trampoline.  On Alpha, instructions
    may only be placed in a text segment.  */
@@ -1029,76 +1289,24 @@ extern char *alpha_function_name;
 
 /* Emit RTL insns to initialize the variable parts of a trampoline.
    FNADDR is an RTX for the address of the function's pure code.
-   CXT is an RTX for the static chain value for the function.  We assume
-   here that a function will be called many more times than its address
-   is taken (e.g., it might be passed to qsort), so we take the trouble 
-   to initialize the "hint" field in the JMP insn.  Note that the hint
-   field is PC (new) + 4 * bits 13:0.  */
-
-#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
-{									\
-  rtx _temp, _temp1, _addr;						\
-									\
-  _addr = memory_address (Pmode, plus_constant ((TRAMP), 16));		\
-  emit_move_insn (gen_rtx (MEM, Pmode, _addr), (FNADDR));		\
-  _addr = memory_address (Pmode, plus_constant ((TRAMP), 24));		\
-  emit_move_insn (gen_rtx (MEM, Pmode, _addr), (CXT));			\
-									\
-  _temp = force_operand (plus_constant ((TRAMP), 12), NULL_RTX);	\
-  _temp = expand_binop (DImode, sub_optab, (FNADDR), _temp, _temp, 1,	\
-			OPTAB_WIDEN);					\
-  _temp = expand_shift (RSHIFT_EXPR, Pmode, _temp,			\
-			build_int_2 (2, 0), NULL_RTX, 1);		\
-  _temp = expand_and (gen_lowpart (SImode, _temp),			\
-		      GEN_INT (0x3fff), 0); 				\
-									\
-  _addr = memory_address (SImode, plus_constant ((TRAMP), 8));		\
-  _temp1 = force_reg (SImode, gen_rtx (MEM, SImode, _addr));		\
-  _temp1 = expand_and (_temp1, GEN_INT (0xffffc000), NULL_RTX);		\
-  _temp1 = expand_binop (SImode, ior_optab, _temp1, _temp, _temp1, 1,	\
-			 OPTAB_WIDEN);					\
-									\
-  emit_move_insn (gen_rtx (MEM, SImode, _addr), _temp1);		\
-									\
-  emit_library_call (gen_rtx (SYMBOL_REF, Pmode,			\
-			      "__enable_execute_stack"),		\
-		     0, VOIDmode, 1,_addr, Pmode);			\
-									\
-  emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode,			\
-		      gen_rtvec (1, const0_rtx), 0));			\
-}
+   CXT is an RTX for the static chain value for the function.  */
 
-/* Attempt to turn on access permissions for the stack.  */
-
-#define TRANSFER_FROM_TRAMPOLINE					\
-									\
-void									\
-__enable_execute_stack (addr)						\
-     void *addr;							\
-{									\
-  long size = getpagesize ();						\
-  long mask = ~(size-1);						\
-  char *page = (char *) (((long) addr) & mask);				\
-  char *end  = (char *) ((((long) (addr + TRAMPOLINE_SIZE)) & mask) + size); \
-									\
-  /* 7 is PROT_READ | PROT_WRITE | PROT_EXEC */				\
-  if (mprotect (page, end - page, 7) < 0)				\
-    perror ("mprotect of trampoline code");				\
-}
+#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
+  alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, 8)
 
 /* A C expression whose value is RTL representing the value of the return
    address for the frame COUNT steps up from the current frame.
    FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of
-   the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME} is defined.
+   the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME is defined.  */
+
+#define RETURN_ADDR_RTX  alpha_return_addr
+extern struct rtx_def *alpha_return_addr ();
 
-   This definition for Alpha is broken, but is put in at the request of
-   Mike Stump.  */
+/* Initialize data used by insn expanders.  This is called from insn_emit,
+   once for every function before code is generated.  */
 
-#define RETURN_ADDR_RTX(COUNT, FRAME)					\
-((COUNT == 0 && alpha_sa_size () == 0 && 0 /* not right. */)		\
- ? gen_rtx (REG, Pmode, 26)						\
- : gen_rtx (MEM, Pmode,							\
-	    memory_address (Pmode, FRAME)))
+#define INIT_EXPANDERS  alpha_init_expanders ()
+extern void alpha_init_expanders ();
 
 /* Addressing modes, and classification of registers for them.  */
 
@@ -1284,6 +1492,58 @@ __enable_execute_stack (addr)						\
     }								\
 }
 
+/* Try a machine-dependent way of reloading an illegitimate address
+   operand.  If we find one, push the reload and jump to WIN.  This
+   macro is used in only one place: `find_reloads_address' in reload.c.
+
+   For the Alpha, we wish to handle large displacements off a base
+   register by splitting the addend across an ldah and the mem insn.
+   This cuts number of extra insns needed from 3 to 1.  */
+   
+#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN)	\
+do {									\
+  /* We must recognize output that we have already generated ourselves.  */ \
+  if (GET_CODE (X) == PLUS						\
+      && GET_CODE (XEXP (X, 0)) == PLUS					\
+      && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG			\
+      && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT			\
+      && GET_CODE (XEXP (X, 1)) == CONST_INT)				\
+    {									\
+      push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR,	\
+		   BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0,	\
+		   OPNUM, TYPE);					\
+      goto WIN;								\
+    }									\
+  if (GET_CODE (X) == PLUS						\
+      && GET_CODE (XEXP (X, 0)) == REG					\
+      && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER			\
+      && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE)			\
+      && GET_CODE (XEXP (X, 1)) == CONST_INT)				\
+    {									\
+      HOST_WIDE_INT val = INTVAL (XEXP (X, 1));				\
+      HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;		\
+      HOST_WIDE_INT high						\
+	= (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;	\
+									\
+      /* Check for 32-bit overflow.  */					\
+      if (high + low != val)						\
+	break;								\
+									\
+      /* Reload the high part into a base reg; leave the low part	\
+	 in the mem directly.  */					\
+									\
+      X = gen_rtx_PLUS (GET_MODE (X),					\
+			gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0),	\
+				      GEN_INT (high)),			\
+			GEN_INT (low));					\
+	  								\
+      push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL_PTR,	\
+		   BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0,	\
+		   OPNUM, TYPE);					\
+      goto WIN;								\
+    }									\
+} while (0)
+
 /* Go to LABEL if ADDR (a legitimate address expression)
    has an effect that depends on the machine mode it is used for.
    On the Alpha this is true only for the unaligned modes.   We can
@@ -1297,22 +1557,22 @@ __enable_execute_stack (addr)						\
 
 #define ADDRESS_COST(X)  0
 
-/* Define this if some processing needs to be done immediately before
-   emitting code for an insn.  */
-
-/* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
+/* Machine-dependent reorg pass.   */
+#define MACHINE_DEPENDENT_REORG(X)	alpha_reorg(X)
 
 /* Specify the machine mode that this machine uses
    for the index in the tablejump instruction.  */
 #define CASE_VECTOR_MODE SImode
 
-/* Define this if the tablejump instruction expects the table
-   to contain offsets from the address of the table.
+/* Define as C expression which evaluates to nonzero if the tablejump
+   instruction expects the table to contain offsets from the address of the
+   table.
+
    Do not define this if the table should contain absolute addresses.
    On the Alpha, the table is really GP-relative, not relative to the PC
    of the table, but we pretend that it is PC-relative; this should be OK,
    but we should try to find some better way sometime.  */
-#define CASE_VECTOR_PC_RELATIVE
+#define CASE_VECTOR_PC_RELATIVE 1
 
 /* Specify the tree operation to be used to convert reals to integers.  */
 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
@@ -1336,6 +1596,12 @@ __enable_execute_stack (addr)						\
 
 #define MOVE_MAX 8
 
+/* Controls how many units are moved by expr.c before resorting to movstr.
+   Without byte/word accesses, we want no more than one; with, several single
+   byte accesses are better.   */
+
+#define MOVE_RATIO  (TARGET_BWX ? 7 : 2)
+
 /* Largest number of bytes of an object that can be placed in a register.
    On the Alpha we have plenty of registers, so use TImode.  */
 #define MAX_FIXED_MODE_SIZE	GET_MODE_BITSIZE (TImode)
@@ -1357,7 +1623,7 @@ __enable_execute_stack (addr)						\
    will either zero-extend or sign-extend.  The value of this macro should
    be the code that says which one of the two operations is implicitly
    done, NIL if none.  */
-#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
+#define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
 
 /* Define if loading short immediate values into registers sign extends.  */
 #define SHORT_IMMEDIATES_SIGN_EXTEND
@@ -1373,7 +1639,7 @@ __enable_execute_stack (addr)						\
 
 /* Define the value returned by a floating-point comparison instruction.  */
 
-#define FLOAT_STORE_FLAG_VALUE 0.5
+#define FLOAT_STORE_FLAG_VALUE (TARGET_FLOAT_VAX ? 0.5 : 2.0)
 
 /* Canonicalize a comparison from one we don't have to one we do have.  */
 
@@ -1424,6 +1690,9 @@ __enable_execute_stack (addr)						\
    our own exit function.  */
 #define HAVE_ATEXIT
 
+/* The EV4 is dual issue; EV5/EV6 are quad issue.  */
+#define ISSUE_RATE  (alpha_cpu == PROCESSOR_EV4 ? 2 : 4)
+
 /* Compute the cost of computing a constant rtl expression RTX
    whose rtx-code is CODE.  The body of this macro is a portion
    of a switch statement.  If the code is computed here,
@@ -1440,7 +1709,9 @@ __enable_execute_stack (addr)						\
     if (INTVAL (RTX) >= 0 && INTVAL (RTX) < 256)		\
       return 0;							\
   case CONST_DOUBLE:						\
-    if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode))	\
+    if ((RTX) == CONST0_RTX (GET_MODE (RTX)))			\
+      return 0;							\
+    else if (((OUTER_CODE) == PLUS && add_operand (RTX, VOIDmode)) \
 	|| ((OUTER_CODE) == AND && and_operand (RTX, VOIDmode))) \
       return 0;							\
     else if (add_operand (RTX, VOIDmode) || and_operand (RTX, VOIDmode)) \
@@ -1450,7 +1721,15 @@ __enable_execute_stack (addr)						\
   case CONST:							\
   case SYMBOL_REF:						\
   case LABEL_REF:						\
-    return COSTS_N_INSNS (3);
+  switch (alpha_cpu)						\
+    {								\
+    case PROCESSOR_EV4:						\
+      return COSTS_N_INSNS (3);					\
+    case PROCESSOR_EV5:						\
+    case PROCESSOR_EV6:						\
+      return COSTS_N_INSNS (2);					\
+    default: abort();						\
+    }
     
 /* Provide the costs of a rtl expression.  This is in the body of a
    switch on CODE.  */
@@ -1458,52 +1737,128 @@ __enable_execute_stack (addr)						\
 #define RTX_COSTS(X,CODE,OUTER_CODE)			\
   case PLUS:  case MINUS:				\
     if (FLOAT_MODE_P (GET_MODE (X)))			\
-      return COSTS_N_INSNS (6);				\
+      switch (alpha_cpu)				\
+        {						\
+        case PROCESSOR_EV4:				\
+          return COSTS_N_INSNS (6);			\
+        case PROCESSOR_EV5:				\
+        case PROCESSOR_EV6:				\
+          return COSTS_N_INSNS (4); 			\
+	default: abort();				\
+	}						\
     else if (GET_CODE (XEXP (X, 0)) == MULT		\
 	     && const48_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \
       return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE)	\
 	      + rtx_cost (XEXP (X, 1), OUTER_CODE));	\
     break;						\
   case MULT:						\
-    if (FLOAT_MODE_P (GET_MODE (X)))			\
-      return COSTS_N_INSNS (6);				\
-    return COSTS_N_INSNS (23);				\
+    switch (alpha_cpu)					\
+      {							\
+      case PROCESSOR_EV4:				\
+        if (FLOAT_MODE_P (GET_MODE (X)))		\
+          return COSTS_N_INSNS (6);			\
+        return COSTS_N_INSNS (23);			\
+      case PROCESSOR_EV5:				\
+        if (FLOAT_MODE_P (GET_MODE (X)))		\
+          return COSTS_N_INSNS (4);			\
+        else if (GET_MODE (X) == DImode)		\
+          return COSTS_N_INSNS (12);			\
+        else						\
+          return COSTS_N_INSNS (8);			\
+      case PROCESSOR_EV6:				\
+	if (FLOAT_MODE_P (GET_MODE (X)))		\
+	  return COSTS_N_INSNS (4);			\
+	else 						\
+	  return COSTS_N_INSNS (7);			\
+      default: abort();					\
+      }							\
   case ASHIFT:						\
     if (GET_CODE (XEXP (X, 1)) == CONST_INT		\
 	&& INTVAL (XEXP (X, 1)) <= 3)			\
       break;						\
     /* ... fall through ... */				\
-  case ASHIFTRT:  case LSHIFTRT:  case IF_THEN_ELSE:	\
-    return COSTS_N_INSNS (2);				\
+  case ASHIFTRT:  case LSHIFTRT:			\
+    switch (alpha_cpu)					\
+      {							\
+      case PROCESSOR_EV4:				\
+        return COSTS_N_INSNS (2);			\
+      case PROCESSOR_EV5:				\
+      case PROCESSOR_EV6:				\
+        return COSTS_N_INSNS (1); 			\
+      default: abort();					\
+      }							\
+  case IF_THEN_ELSE:					\
+    switch (alpha_cpu)					\
+      {							\
+      case PROCESSOR_EV4:				\
+      case PROCESSOR_EV6:				\
+        return COSTS_N_INSNS (2);			\
+      case PROCESSOR_EV5:				\
+        return COSTS_N_INSNS (1); 			\
+      default: abort();					\
+      }							\
   case DIV:  case UDIV:  case MOD:  case UMOD:		\
-    if (GET_MODE (X) == SFmode)				\
-      return COSTS_N_INSNS (34);			\
-    else if (GET_MODE (X) == DFmode)			\
-      return COSTS_N_INSNS (63);			\
-    else						\
-      return COSTS_N_INSNS (70);			\
+    switch (alpha_cpu)					\
+      {							\
+      case PROCESSOR_EV4:				\
+        if (GET_MODE (X) == SFmode)			\
+          return COSTS_N_INSNS (34);			\
+        else if (GET_MODE (X) == DFmode)		\
+          return COSTS_N_INSNS (63);			\
+        else						\
+          return COSTS_N_INSNS (70);			\
+      case PROCESSOR_EV5:				\
+        if (GET_MODE (X) == SFmode)			\
+          return COSTS_N_INSNS (15);			\
+        else if (GET_MODE (X) == DFmode)		\
+          return COSTS_N_INSNS (22);			\
+        else						\
+          return COSTS_N_INSNS (70);	/* ??? */	\
+      case PROCESSOR_EV6:				\
+	if (GET_MODE (X) == SFmode)			\
+	  return COSTS_N_INSNS (12);			\
+        else if (GET_MODE (X) == DFmode)		\
+          return COSTS_N_INSNS (15);			\
+        else						\
+          return COSTS_N_INSNS (70);	/* ??? */	\
+      default: abort();					\
+      }							\
   case MEM:						\
-    return COSTS_N_INSNS (3);				\
+    switch (alpha_cpu)					\
+      {							\
+      case PROCESSOR_EV4:				\
+      case PROCESSOR_EV6:				\
+        return COSTS_N_INSNS (3);			\
+      case PROCESSOR_EV5:				\
+        return COSTS_N_INSNS (2); 			\
+      default: abort();					\
+      }							\
+  case NEG:  case ABS:					\
+    if (! FLOAT_MODE_P (GET_MODE (X)))			\
+      break;						\
+    /* ... fall through ... */				\
   case FLOAT:  case UNSIGNED_FLOAT:  case FIX:  case UNSIGNED_FIX: \
   case FLOAT_EXTEND:  case FLOAT_TRUNCATE:		\
-    return COSTS_N_INSNS (6);				\
-  case NEG:  case ABS:					\
-    if (FLOAT_MODE_P (GET_MODE (X)))			\
-      return COSTS_N_INSNS (6);				\
-    break;
+    switch (alpha_cpu)					\
+      {							\
+      case PROCESSOR_EV4:				\
+        return COSTS_N_INSNS (6);			\
+      case PROCESSOR_EV5:				\
+      case PROCESSOR_EV6:				\
+        return COSTS_N_INSNS (4); 			\
+      default: abort();					\
+      }
 
 /* Control the assembler format that we output.  */
 
-/* Output at beginning of assembler file.  */
-
-#define ASM_FILE_START(FILE)					\
-{								\
-  alpha_write_verstamp (FILE);					\
-  fprintf (FILE, "\t.set noreorder\n");				\
-  fprintf (FILE, "\t.set volatile\n");                                \
-  fprintf (FILE, "\t.set noat\n");				\
-  ASM_OUTPUT_SOURCE_FILENAME (FILE, main_input_filename);	\
-}
+/* We don't emit these labels, so as to avoid getting linker errors about
+   missing exception handling info.  If we emit a gcc_compiled. label into
+   text, and the file has no code, then the DEC assembler gives us a zero
+   sized text section with no associated exception handling info.  The
+   DEC linker sees this text section, and gives a warning saying that
+   the exception handling info is missing.  */
+#define ASM_IDENTIFY_GCC(x)
+#define ASM_IDENTIFY_LANGUAGE(x)
 
 /* Output to assembler file text saying following lines
    may contain character constants, extra white space, comments, etc.  */
@@ -1592,20 +1947,15 @@ literal_section ()						\
 #define ASM_GLOBALIZE_LABEL(FILE,NAME)	\
   do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
 
-/* This is how to output a reference to a user-level label named NAME.
-   `assemble_name' uses this.  */
+/* The prefix to add to user-visible assembler symbols. */
 
-#define ASM_OUTPUT_LABELREF(FILE,NAME)	\
-  fprintf (FILE, "%s", NAME)
+#define USER_LABEL_PREFIX ""
 
 /* This is how to output an internal numbered label where
    PREFIX is the class of label and NUM is the number within the class.  */
 
 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)	\
-  if ((PREFIX)[0] == 'L')				\
-    fprintf (FILE, "$%s%d:\n", & (PREFIX)[1], NUM + 32); \
-  else							\
-    fprintf (FILE, "%s%d:\n", PREFIX, NUM);
+  fprintf (FILE, "$%s%d:\n", PREFIX, NUM)
 
 /* This is how to output a label for a jump table.  Arguments are the same as
    for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is
@@ -1620,10 +1970,12 @@ literal_section ()						\
    This is suitable for output with `assemble_name'.  */
 
 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)	\
-  if ((PREFIX)[0] == 'L')				\
-    sprintf (LABEL, "*$%s%d", & (PREFIX)[1], NUM + 32);	\
-  else							\
-    sprintf (LABEL, "*%s%d", PREFIX, NUM)
+  sprintf (LABEL, "*$%s%d", PREFIX, NUM)
+
+/* Check a floating-point value for validity for a particular machine mode.  */
+
+#define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \
+  ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW))
 
 /* This is how to output an assembler line defining a `double' constant.  */
 
@@ -1642,29 +1994,18 @@ literal_section ()						\
       {									\
 	char str[30];							\
 	REAL_VALUE_TO_DECIMAL (VALUE, "%.20e", str);			\
-	fprintf (FILE, "\t.t_floating %s\n", str);			\
+	fprintf (FILE, "\t.%c_floating %s\n", (TARGET_FLOAT_VAX)?'g':'t', str);			\
       }									\
   }
 
 /* This is how to output an assembler line defining a `float' constant.  */
 
-#define ASM_OUTPUT_FLOAT(FILE,VALUE)					\
-  {									\
-    if (REAL_VALUE_ISINF (VALUE)					\
-        || REAL_VALUE_ISNAN (VALUE)					\
-	|| REAL_VALUE_MINUS_ZERO (VALUE))				\
-      {									\
-	long t;								\
-	REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);			\
-	fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff);		\
-      }									\
-    else								\
-      {									\
-	char str[30];							\
-	REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);			\
-	fprintf (FILE, "\t.s_floating %s\n", str);			\
-      }									\
-  }
+#define ASM_OUTPUT_FLOAT(FILE,VALUE)				\
+  do {								\
+    long t;							\
+    REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);			\
+    fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff);		\
+} while (0)
   
 /* This is how to output an assembler line defining an `int' constant.  */
 
@@ -1684,12 +2025,12 @@ literal_section ()						\
 
 #define ASM_OUTPUT_SHORT(FILE,VALUE)  \
   fprintf (FILE, "\t.word %d\n",		\
-    (GET_CODE (VALUE) == CONST_INT		\
+    (int)(GET_CODE (VALUE) == CONST_INT		\
      ? INTVAL (VALUE) & 0xffff : (abort (), 0)))
 
 #define ASM_OUTPUT_CHAR(FILE,VALUE)		\
   fprintf (FILE, "\t.byte %d\n",		\
-    (GET_CODE (VALUE) == CONST_INT		\
+    (int)(GET_CODE (VALUE) == CONST_INT		\
      ? INTVAL (VALUE) & 0xff : (abort (), 0)))
 
 /* We use the default ASCII-output routine, except that we don't write more
@@ -1756,7 +2097,7 @@ literal_section ()						\
 /* This is how to output an assembler line for a numeric constant byte.  */
 
 #define ASM_OUTPUT_BYTE(FILE,VALUE)  \
-  fprintf (FILE, "\t.byte 0x%x\n", (VALUE) & 0xff)
+  fprintf (FILE, "\t.byte 0x%x\n", (int) ((VALUE) & 0xff))
 
 /* This is how to output an element of a case-vector that is absolute.
    (Alpha does not use such vectors, but we must define this macro anyway.)  */
@@ -1765,13 +2106,9 @@ literal_section ()						\
 
 /* This is how to output an element of a case-vector that is relative.  */
 
-#if WINDOWS_NT
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
-  fprintf (FILE, "\t.long $%d\n", (VALUE) + 32)
-#else
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
-  fprintf (FILE, "\t.gprel32 $%d\n", (VALUE) + 32)
-#endif
+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
+  fprintf (FILE, "\t.%s $L%d\n", TARGET_WINDOWS_NT ? "long" : "gprel32", \
+	   (VALUE))
 
 /* This is how to output an assembler line
    that says to advance the location counter
@@ -1816,6 +2153,36 @@ literal_section ()						\
 #define ASM_OPEN_PAREN "("
 #define ASM_CLOSE_PAREN ")"
 
+/* Output code to add DELTA to the first argument, and then jump to FUNCTION.
+   Used for C++ multiple inheritance.  */
+
+#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION)	\
+do {									\
+  char *fn_name = XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0);		\
+  int reg;								\
+									\
+  /* Mark end of prologue.  */						\
+  output_end_prologue (FILE);						\
+									\
+  /* Rely on the assembler to macro expand a large delta.  */		\
+  reg = aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) ? 17 : 16;	\
+  fprintf (FILE, "\tlda $%d,%ld($%d)\n", reg, (long)(DELTA), reg);	\
+									\
+  if (current_file_function_operand (XEXP (DECL_RTL (FUNCTION), 0)))	\
+    {									\
+      fprintf (FILE, "\tbr $31,$");					\
+      assemble_name (FILE, fn_name);					\
+      fprintf (FILE, "..ng\n");						\
+    }									\
+  else									\
+    {									\
+      fprintf (FILE, "\tjmp $31,");					\
+      assemble_name (FILE, fn_name);					\
+      fputc ('\n', FILE);						\
+    }									\
+} while (0)
+
+
 /* Define results of standard character escape sequences.  */
 #define TARGET_BELL 007
 #define TARGET_BS 010
@@ -1832,9 +2199,41 @@ literal_section ()						\
 #define PRINT_OPERAND(FILE, X, CODE)  print_operand (FILE, X, CODE)
 
 /* Determine which codes are valid without a following integer.  These must
-   not be alphabetic.  */
+   not be alphabetic (the characters are chosen so that
+   PRINT_OPERAND_PUNCT_VALID_P translates into a simple range change when
+   using ASCII).
+
+   &	Generates fp-rounding mode suffix: nothing for normal, 'c' for
+   	chopped, 'm' for minus-infinity, and 'd' for dynamic rounding
+	mode.  alpha_fprm controls which suffix is generated.
+
+   '	Generates trap-mode suffix for instructions that accept the
+        su suffix only (cmpt et al).
+
+   `    Generates trap-mode suffix for instructions that accept the
+	v and sv suffix.  The only instruction that needs this is cvtql.
+
+   (	Generates trap-mode suffix for instructions that accept the
+	v, sv, and svi suffix.  The only instruction that needs this
+	is cvttq.
 
-#define PRINT_OPERAND_PUNCT_VALID_P(CODE) 0
+   )    Generates trap-mode suffix for instructions that accept the
+	u, su, and sui suffix.  This is the bulk of the IEEE floating
+	point instructions (addt et al).
+
+   +    Generates trap-mode suffix for instructions that accept the
+	sui suffix (cvtqt and cvtqs).
+
+   ,    Generates single precision suffix for floating point
+	instructions (s for IEEE, f for VAX)
+
+   -	Generates double precision suffix for floating point
+	instructions (t for IEEE, g for VAX)
+   */
+
+#define PRINT_OPERAND_PUNCT_VALID_P(CODE)				\
+  ((CODE) == '&' || (CODE) == '`' || (CODE) == '\'' || (CODE) == '('	\
+   || (CODE) == ')' || (CODE) == '+' || (CODE) == ',' || (CODE) == '-')
 
 /* Print a memory address as an operand to reference that memory location.  */
 
@@ -1857,38 +2256,42 @@ literal_section ()						\
   else							\
     abort ();						\
 							\
-  fprintf (FILE, "%d($%d)", offset, basereg);		\
+  fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, offset);		\
+  fprintf (FILE, "($%d)", basereg);		\
 }
 /* Define the codes that are matched by predicates in alpha.c.  */
 
-#define PREDICATE_CODES \
-  {"reg_or_0_operand", {SUBREG, REG, CONST_INT}},	\
-  {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}},	\
-  {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}},	\
-  {"cint8_operand", {CONST_INT}},                       \
-  {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}},	\
-  {"add_operand", {SUBREG, REG, CONST_INT}},		\
-  {"sext_add_operand", {SUBREG, REG, CONST_INT}},	\
-  {"const48_operand", {CONST_INT}},			\
-  {"and_operand", {SUBREG, REG, CONST_INT}},		\
-  {"or_operand", {SUBREG, REG, CONST_INT}},		\
-  {"mode_mask_operand", {CONST_INT}},			\
-  {"mul8_operand", {CONST_INT}},			\
-  {"mode_width_operand", {CONST_INT}},			\
-  {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}},	\
-  {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \
-  {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \
-  {"divmod_operator", {DIV, MOD, UDIV, UMOD}},		\
-  {"fp0_operand", {CONST_DOUBLE}},			\
-  {"current_file_function_operand", {SYMBOL_REF}},	\
-  {"call_operand", {REG, SYMBOL_REF}},			\
-  {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE,	\
-		     SYMBOL_REF, CONST, LABEL_REF}},	\
-  {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \
-		    SYMBOL_REF, CONST, LABEL_REF}},	\
-  {"aligned_memory_operand", {MEM}},			\
-  {"unaligned_memory_operand", {MEM}},			\
-  {"any_memory_operand", {MEM}},
+#define PREDICATE_CODES 						\
+  {"reg_or_0_operand", {SUBREG, REG, CONST_INT}},			\
+  {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}},	\
+  {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}},	\
+  {"cint8_operand", {CONST_INT, CONSTANT_P_RTX}},                       \
+  {"reg_or_cint_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}},	\
+  {"add_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}},		\
+  {"sext_add_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}},	\
+  {"const48_operand", {CONST_INT}},					\
+  {"and_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}},		\
+  {"or_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}},		\
+  {"mode_mask_operand", {CONST_INT}},					\
+  {"mul8_operand", {CONST_INT}},					\
+  {"mode_width_operand", {CONST_INT}},					\
+  {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}},			\
+  {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}},		\
+  {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}},	\
+  {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}},		\
+  {"divmod_operator", {DIV, MOD, UDIV, UMOD}},				\
+  {"fp0_operand", {CONST_DOUBLE}},					\
+  {"current_file_function_operand", {SYMBOL_REF}},			\
+  {"call_operand", {REG, SYMBOL_REF}},					\
+  {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE,		\
+		     SYMBOL_REF, CONST, LABEL_REF, CONSTANT_P_RTX}},	\
+  {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE,		\
+		    SYMBOL_REF, CONST, LABEL_REF, CONSTANT_P_RTX}},	\
+  {"aligned_memory_operand", {MEM}},					\
+  {"unaligned_memory_operand", {MEM}},					\
+  {"reg_or_unaligned_mem_operand", {SUBREG, REG, MEM}},			\
+  {"any_memory_operand", {MEM}},					\
+  {"hard_fp_register_operand", {SUBREG, REG}},
 
 /* Tell collect that the object format is ECOFF.  */
 #define OBJECT_FORMAT_COFF
@@ -1904,8 +2307,7 @@ literal_section ()						\
 #define MIPS_DEBUGGING_INFO		/* MIPS specific debugging info */
 
 #ifndef PREFERRED_DEBUGGING_TYPE	/* assume SDB_DEBUGGING_INFO */
-#define PREFERRED_DEBUGGING_TYPE  \
- ((len > 1 && !strncmp (str, "ggdb", len)) ? DBX_DEBUG : SDB_DEBUG)
+#define PREFERRED_DEBUGGING_TYPE  SDB_DEBUG
 #endif
 
 
@@ -1937,13 +2339,17 @@ extern void alpha_output_lineno ();
   alpha_output_filename (STREAM, NAME)
 extern void alpha_output_filename ();
 
-
-/* mips-tfile.c limits us to strings of one page.  */
-#define DBX_CONTIN_LENGTH 4000
+/* mips-tfile.c limits us to strings of one page.  We must underestimate this
+   number, because the real length runs past this up to the next
+   continuation point.  This is really a dbxout.c bug.  */
+#define DBX_CONTIN_LENGTH 3000
 
 /* By default, turn on GDB extensions.  */
 #define DEFAULT_GDB_EXTENSIONS 1
 
+/* Stabs-in-ECOFF can't handle dbxout_function_end().  */
+#define NO_DBX_FUNCTION_END 1
+
 /* If we are smuggling stabs through the ALPHA ECOFF object
    format, put a comment in front of the .stab<x> operation so
    that the ALPHA assembler does not choke.  The mips-tfile program
@@ -2011,47 +2417,7 @@ do {							\
 
 #define PUT_SDB_FUNCTION_END(LINE)
 
-#define PUT_SDB_EPILOGUE_END(NAME)
-
-/* No point in running CPP on our assembler output.  */
-#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_GAS) != 0
-/* Don't pass -g to GNU as, because some versions don't accept this option.  */
-#define ASM_SPEC "%{malpha-as:-g} -nocpp %{pg}"
-#else
-/* In OSF/1 v3.2c, the assembler by default does not output file names which
-   causes mips-tfile to fail.  Passing -g to the assembler fixes this problem.
-   ??? Stricly speaking, we only need -g if the user specifies -g.  Passing
-   it always means that we get slightly larger than necessary object files
-   if the user does not specify -g.  If we don't pass -g, then mips-tfile
-   will need to be fixed to work in this case.  */
-#define ASM_SPEC "%{!mgas:-g} -nocpp %{pg}"
-#endif
-
-/* Specify to run a post-processor, mips-tfile after the assembler
-   has run to stuff the ecoff debug information into the object file.
-   This is needed because the Alpha assembler provides no way
-   of specifying such information in the assembly file.  */
-
-#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_GAS) != 0
-
-#define ASM_FINAL_SPEC "\
-%{malpha-as: %{!mno-mips-tfile: \
-	\n mips-tfile %{v*: -v} \
-		%{K: -I %b.o~} \
-		%{!K: %{save-temps: -I %b.o~}} \
-		%{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
-		%{.s:%i} %{!.s:%g.s}}}"
-
-#else
-#define ASM_FINAL_SPEC "\
-%{!mgas: %{!mno-mips-tfile: \
-	\n mips-tfile %{v*: -v} \
-		%{K: -I %b.o~} \
-		%{!K: %{save-temps: -I %b.o~}} \
-		%{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
-		%{.s:%i} %{!.s:%g.s}}}"
-
-#endif
+#define PUT_SDB_EPILOGUE_END(NAME) ((void)(NAME))
 
 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
    mips-tdump.c to print them out.
@@ -2073,16 +2439,55 @@ do {							\
 
 #define ALIGN_SYMTABLE_OFFSET(OFFSET) (((OFFSET) + 7) & ~7)
 
-/* The system headers under OSF/1 are C++-aware.  */
-#define NO_IMPLICIT_EXTERN_C
-
-/* Also define __LANGUAGE_C__ when running fix-header. */
-#define FIXPROTO_INIT(CPPFILE)  cpp_define (CPPFILE, "__LANGUAGE_C__")
-
 /* The linker will stick __main into the .init section.  */
 #define HAS_INIT_SECTION
 #define LD_INIT_SWITCH "-init"
 #define LD_FINI_SWITCH "-fini"
 
-/* We do want to link in libgcc when building shared libraries under OSF/1.  */
-#define LIBGCC_SPEC "-lgcc"
+/* The system headers under Alpha systems are generally C++-aware.  */
+#define NO_IMPLICIT_EXTERN_C
+
+/* Prototypes for alpha.c functions used in the md file & elsewhere.  */
+extern struct rtx_def *get_unaligned_address ();
+extern void alpha_write_verstamp ();
+extern void alpha_reorg ();
+extern int check_float_value ();
+extern int direct_return ();
+extern int const48_operand ();
+extern int add_operand ();
+extern int and_operand ();
+extern int unaligned_memory_operand ();
+extern int zap_mask ();
+extern int current_file_function_operand ();
+extern int alpha_sa_size ();
+extern int alpha_adjust_cost ();
+extern void print_operand ();
+extern int reg_or_0_operand ();
+extern int reg_or_8bit_operand ();
+extern int mul8_operand ();
+extern int reg_or_6bit_operand ();
+extern int alpha_comparison_operator ();
+extern int alpha_swapped_comparison_operator ();
+extern int sext_add_operand ();
+extern int cint8_operand ();
+extern int mode_mask_operand ();
+extern int or_operand ();
+extern int mode_width_operand ();
+extern int reg_or_fp0_operand ();
+extern int signed_comparison_operator ();
+extern int fp0_operand ();
+extern int some_operand ();
+extern int input_operand ();
+extern int divmod_operator ();
+extern int call_operand ();
+extern int reg_or_cint_operand ();
+extern int hard_fp_register_operand ();
+extern void alpha_set_memflags ();
+extern int aligned_memory_operand ();
+extern void get_aligned_mem ();
+extern void alpha_expand_unaligned_load ();
+extern void alpha_expand_unaligned_store ();
+extern int alpha_expand_block_move ();
+extern int alpha_expand_block_clear ();
+extern void alpha_expand_prologue ();
+extern void alpha_expand_epilogue ();
diff --git a/contrib/gcc/config/alpha/alpha.md b/contrib/gcc/config/alpha/alpha.md
index 72c54eee371b..87ebf95e168f 100644
--- a/contrib/gcc/config/alpha/alpha.md
+++ b/contrib/gcc/config/alpha/alpha.md
@@ -1,5 +1,5 @@
 ;; Machine description for DEC Alpha for GNU C compiler
-;; Copyright (C) 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
+;; Copyright (C) 1992, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
 
 ;; This file is part of GNU CC.
@@ -20,71 +20,396 @@
 ;; Boston, MA 02111-1307, USA.
 
 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
+
+;; Uses of UNSPEC in this file:
+;;
+;;	0	arg_home
+;;	1	cttz
+;;	2	insxh
+;;	3	mskxh
+;;	4	cvtlq
+;;	5	cvtql
+;;	
+;; UNSPEC_VOLATILE:
+;;
+;;	0	imb
+;;	1	blockage
+;;	2	builtin_setjmp_receiver
+;;	3	builtin_longjmp
+;;	4	trapb
+;;	5	prologue_stack_probe_loop
 
+;; Processor type -- this attribute must exactly match the processor_type
+;; enumeration in alpha.h.
+
+(define_attr "cpu" "ev4,ev5,ev6"
+  (const (symbol_ref "alpha_cpu")))
+
 ;; Define an insn type attribute.  This is used in function unit delay
 ;; computations, among other purposes.  For the most part, we use the names
 ;; defined in the EV4 documentation, but add a few that we have to know about
 ;; separately.
 
 (define_attr "type"
-  "ld,st,ibr,fbr,jsr,iaddlog,shiftcm,icmp,imull,imulq,fpop,fdivs,fdivt,ldsym,isubr"
-  (const_string "shiftcm"))
-
-;; We include four function units: ABOX, which computes the address,
-;; BBOX, used for branches, EBOX, used for integer operations, and FBOX,
-;; used for FP operations.
-;;
-;; We assume that we have been successful in getting double issues and
-;; hence multiply all costs by two insns per cycle.  The minimum time in
-;; a function unit is 2 cycle, which will tend to produce the double
-;; issues.
+  "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof"
+  (const_string "iadd"))
 
-;; Memory delivers its result in three cycles.
-(define_function_unit "abox" 1 0 (eq_attr "type" "ld,ldsym,st") 6 2)
+;; Define the operand size an insn operates on.  Used primarily by mul
+;; and div operations that have size dependant timings.
 
-;; Branches have no delay cost, but do tie up the unit for two cycles.
-(define_function_unit "bbox" 1 1 (eq_attr "type" "ibr,fbr,jsr") 4 4)
+(define_attr "opsize" "si,di,udi" (const_string "di"))
 
-;; Arithmetic insns are normally have their results available after two
-;; cycles.  There are a number of exceptions.  They are encoded in
-;; ADJUST_COST.  Some of the other insns have similar exceptions.
+;; The TRAP_TYPE attribute marks instructions that may generate traps
+;; (which are imprecise and may need a trapb if software completion
+;; is desired).
 
-(define_function_unit "ebox" 1 0 (eq_attr "type" "iaddlog,shiftcm,icmp") 4 2)
+(define_attr "trap" "no,yes" (const_string "no"))
 
-;; These really don't take up the integer pipeline, but they do occupy
-;; IBOX1; we approximate here.
+;; The length of an instruction sequence in bytes.
 
-(define_function_unit "ebox" 1 0 (eq_attr "type" "imull") 42 2)
-(define_function_unit "ebox" 1 0 (eq_attr "type" "imulq") 46 2)
-
-(define_function_unit "imult" 1 0 (eq_attr "type" "imull") 42 38)
-(define_function_unit "imult" 1 0 (eq_attr "type" "imulq") 46 42)
-
-(define_function_unit "fbox" 1 0 (eq_attr "type" "fpop") 12 2)
-
-(define_function_unit "fbox" 1 0 (eq_attr "type" "fdivs") 68 0)
-(define_function_unit "fbox" 1 0 (eq_attr "type" "fdivt") 126 0)
+(define_attr "length" "" (const_int 4))
+
+;; On EV4 there are two classes of resources to consider: resources needed
+;; to issue, and resources needed to execute.  IBUS[01] are in the first
+;; category.  ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second.
+;; (There are a few other register-like resources, but ...)
+
+; First, describe all of the issue constraints with single cycle delays.
+; All insns need a bus, but all except loads require one or the other.
+(define_function_unit "ev4_ibus0" 1 0
+  (and (eq_attr "cpu" "ev4")
+       (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp"))
+  1 1)
+
+(define_function_unit "ev4_ibus1" 1 0
+  (and (eq_attr "cpu" "ev4")
+       (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc"))
+  1 1)
+
+; Memory delivers its result in three cycles.  Actually return one and
+; take care of this in adjust_cost, since we want to handle user-defined
+; memory latencies.
+(define_function_unit "ev4_abox" 1 0
+  (and (eq_attr "cpu" "ev4")
+       (eq_attr "type" "ild,fld,ldsym,ist,fst"))
+  1 1)
+
+; Branches have no delay cost, but do tie up the unit for two cycles.
+(define_function_unit "ev4_bbox" 1 1
+  (and (eq_attr "cpu" "ev4")
+       (eq_attr "type" "ibr,fbr,jsr"))
+  2 2)
+
+; Arithmetic insns are normally have their results available after
+; two cycles.  There are a number of exceptions.  They are encoded in
+; ADJUST_COST.  Some of the other insns have similar exceptions.
+(define_function_unit "ev4_ebox" 1 0
+  (and (eq_attr "cpu" "ev4")
+       (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc"))
+  2 1)
+
+(define_function_unit "imul" 1 0
+  (and (eq_attr "cpu" "ev4")
+       (and (eq_attr "type" "imul")
+	    (eq_attr "opsize" "si")))
+  21 19)
+
+(define_function_unit "imul" 1 0
+  (and (eq_attr "cpu" "ev4")
+       (and (eq_attr "type" "imul")
+	    (eq_attr "opsize" "!si")))
+  23 21)
+
+(define_function_unit "ev4_fbox" 1 0
+  (and (eq_attr "cpu" "ev4")
+       (eq_attr "type" "fadd,fmul,fcpys,fcmov"))
+  6 1)
+
+(define_function_unit "fdiv" 1 0
+  (and (eq_attr "cpu" "ev4")
+       (and (eq_attr "type" "fdiv")
+	    (eq_attr "opsize" "si")))
+  34 30)
+
+(define_function_unit "fdiv" 1 0
+  (and (eq_attr "cpu" "ev4")
+       (and (eq_attr "type" "fdiv")
+	    (eq_attr "opsize" "di")))
+  63 59)
+
+;; EV5 scheduling.  EV5 can issue 4 insns per clock.
+;;
+;; EV5 has two asymetric integer units.  Model this with E0 & E1 along
+;; with the combined resource EBOX.
+
+(define_function_unit "ev5_ebox" 2 0
+  (and (eq_attr "cpu" "ev5")
+       (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv"))
+  1 1)
+
+; Memory takes at least 2 clocks.  Return one from here and fix up with
+; user-defined latencies in adjust_cost.
+; ??? How to: "An instruction of class LD cannot be issued in the _second_
+; cycle after an instruction of class ST is issued."
+(define_function_unit "ev5_ebox" 2 0
+  (and (eq_attr "cpu" "ev5")
+       (eq_attr "type" "ild,fld,ldsym"))
+  1 1)
+
+; Stores, shifts, multiplies can only issue to E0
+(define_function_unit "ev5_e0" 1 0
+  (and (eq_attr "cpu" "ev5")
+       (eq_attr "type" "ist,fst,shift,imul"))
+  1 1)
+
+; Motion video insns also issue only to E0, and take two ticks.
+(define_function_unit "ev5_e0" 1 0
+  (and (eq_attr "cpu" "ev5")
+       (eq_attr "type" "mvi"))
+  2 1)
+
+; Conditional moves always take 2 ticks.
+(define_function_unit "ev5_ebox" 2 0
+  (and (eq_attr "cpu" "ev5")
+       (eq_attr "type" "icmov"))
+  2 1)
+
+; Branches can only issue to E1
+(define_function_unit "ev5_e1" 1 0
+  (and (eq_attr "cpu" "ev5")
+       (eq_attr "type" "ibr,jsr"))
+  1 1)
+
+; Multiplies also use the integer multiplier.
+; ??? How to: "No instruction can be issued to pipe E0 exactly two
+; cycles before an integer multiplication completes."
+(define_function_unit "imul" 1 0
+  (and (eq_attr "cpu" "ev5")
+       (and (eq_attr "type" "imul")
+	    (eq_attr "opsize" "si")))
+  8 4)
+
+(define_function_unit "imul" 1 0
+  (and (eq_attr "cpu" "ev5")
+       (and (eq_attr "type" "imul")
+	    (eq_attr "opsize" "di")))
+  12 8)
+
+(define_function_unit "imul" 1 0
+  (and (eq_attr "cpu" "ev5")
+       (and (eq_attr "type" "imul")
+	    (eq_attr "opsize" "udi")))
+  14 8)
+
+;; Similarly for the FPU we have two asymetric units.  But fcpys can issue
+;; on either so we have to play the game again.
+
+(define_function_unit "ev5_fbox" 2 0
+  (and (eq_attr "cpu" "ev5")
+       (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv"))
+  4 1)
+  
+(define_function_unit "ev5_fm" 1 0
+  (and (eq_attr "cpu" "ev5")
+       (eq_attr "type" "fmul"))
+  4 1)
+
+; Add and cmov as you would expect; fbr never produces a result;
+; fdiv issues through fa to the divider, 
+(define_function_unit "ev5_fa" 1 0
+  (and (eq_attr "cpu" "ev5")
+       (eq_attr "type" "fadd,fcmov,fbr,fdiv"))
+  4 1)
+
+; ??? How to: "No instruction can be issued to pipe FA exactly five
+; cycles before a floating point divide completes."
+(define_function_unit "fdiv" 1 0
+  (and (eq_attr "cpu" "ev5")
+       (and (eq_attr "type" "fdiv")
+	    (eq_attr "opsize" "si")))
+  15 15)				; 15 to 31 data dependant
+
+(define_function_unit "fdiv" 1 0
+  (and (eq_attr "cpu" "ev5")
+       (and (eq_attr "type" "fdiv")
+	    (eq_attr "opsize" "di")))
+  22 22)				; 22 to 60 data dependant
+
+;; EV6 scheduling.  EV6 can issue 4 insns per clock.
+;;
+;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units
+;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1.
+
+;; Conditional moves decompose into two independant primitives, each 
+;; taking one cycle.  Since ev6 is out-of-order, we can't see anything
+;; but two cycles.
+(define_function_unit "ev6_ebox" 4 0
+  (and (eq_attr "cpu" "ev6")
+       (eq_attr "type" "icmov"))
+  2 1)
+
+(define_function_unit "ev6_ebox" 4 0
+  (and (eq_attr "cpu" "ev6")
+       (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt"))
+  1 1)
+
+;; Integer loads take at least 3 clocks, and only issue to lower units.
+;; Return one from here and fix up with user-defined latencies in adjust_cost.
+(define_function_unit "ev6_l" 2 0
+  (and (eq_attr "cpu" "ev6")
+       (eq_attr "type" "ild,ldsym,ist,fst"))
+  1 1)
+
+;; FP loads take at least 4 clocks.  Return two from here...
+(define_function_unit "ev6_l" 2 0
+  (and (eq_attr "cpu" "ev6")
+       (eq_attr "type" "fld"))
+  2 1)
+
+;; Motion video insns also issue only to U0, and take three ticks.
+(define_function_unit "ev6_u0" 1 0
+  (and (eq_attr "cpu" "ev6")
+       (eq_attr "type" "mvi"))
+  3 1)
+
+(define_function_unit "ev6_u" 2 0
+  (and (eq_attr "cpu" "ev6")
+       (eq_attr "type" "mvi"))
+  3 1)
+
+;; Shifts issue to either upper pipe.
+(define_function_unit "ev6_u" 2 0
+  (and (eq_attr "cpu" "ev6")
+       (eq_attr "type" "shift"))
+  1 1)
+
+;; Multiplies issue only to U1, and all take 7 ticks.
+;; Rather than create a new function unit just for U1, reuse IMUL
+(define_function_unit "imul" 1 0
+  (and (eq_attr "cpu" "ev6")
+       (eq_attr "type" "imul"))
+  7 1)
+
+(define_function_unit "ev6_u" 2 0
+  (and (eq_attr "cpu" "ev6")
+       (eq_attr "type" "imul"))
+  7 1)
+
+;; Branches issue to either upper pipe
+(define_function_unit "ev6_u" 2 0
+  (and (eq_attr "cpu" "ev6")
+       (eq_attr "type" "ibr"))
+  3 1)
+
+;; Calls only issue to L0.
+(define_function_unit "ev6_l0" 1 0
+  (and (eq_attr "cpu" "ev6")
+       (eq_attr "type" "jsr"))
+  1 1)
+
+(define_function_unit "ev6_l" 2 0
+  (and (eq_attr "cpu" "ev6")
+       (eq_attr "type" "jsr"))
+  1 1)
+
+;; Ftoi/itof only issue to lower pipes
+(define_function_unit "ev6_l" 2 0
+  (and (eq_attr "cpu" "ev6")
+       (eq_attr "type" "ftoi"))
+  3 1)
+
+(define_function_unit "ev6_l" 2 0
+  (and (eq_attr "cpu" "ev6")
+       (eq_attr "type" "itof"))
+  4 1)
+
+;; For the FPU we are very similar to EV5, except there's no insn that
+;; can issue to fm & fa, so we get to leave that out.
+  
+(define_function_unit "ev6_fm" 1 0
+  (and (eq_attr "cpu" "ev6")
+       (eq_attr "type" "fmul"))
+  4 1)
+
+(define_function_unit "ev6_fa" 1 0
+  (and (eq_attr "cpu" "ev6")
+       (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt"))
+  4 1)
+
+(define_function_unit "ev6_fa" 1 0
+  (and (eq_attr "cpu" "ev6")
+       (eq_attr "type" "fcmov"))
+  8 1)
+
+(define_function_unit "fdiv" 1 0
+  (and (eq_attr "cpu" "ev6")
+       (and (eq_attr "type" "fdiv")
+	    (eq_attr "opsize" "si")))
+  12 10)
+
+(define_function_unit "fdiv" 1 0
+  (and (eq_attr "cpu" "ev6")
+       (and (eq_attr "type" "fdiv")
+	    (eq_attr "opsize" "di")))
+  15 13)
+
+(define_function_unit "fsqrt" 1 0
+  (and (eq_attr "cpu" "ev6")
+       (and (eq_attr "type" "fsqrt")
+	    (eq_attr "opsize" "si")))
+  16 14)
+
+(define_function_unit "fsqrt" 1 0
+  (and (eq_attr "cpu" "ev6")
+       (and (eq_attr "type" "fsqrt")
+	    (eq_attr "opsize" "di")))
+  32 30)
+
+; ??? The FPU communicates with memory and the integer register file
+; via two fp store units.  We need a slot in the fst immediately, and
+; a slot in LOW after the operand data is ready.  At which point the
+; data may be moved either to the store queue or the integer register
+; file and the insn retired.
 
-(define_function_unit "divider" 1 0 (eq_attr "type" "fdivs") 68 60)
-(define_function_unit "divider" 1 0 (eq_attr "type" "fdivt") 126 118)
 
 ;; First define the arithmetic insns.  Note that the 32-bit forms also
 ;; sign-extend.
 
-;; Note that we can do sign extensions in both FP and integer registers.
-;; However, the result must be in the same type of register as the input.
-;; The register preferencing code can't handle this case very well, so, for
-;; now, don't let the FP case show up here for preferencing.  Also,
-;; sign-extends in FP registers take two instructions.
+;; Handle 32-64 bit extension from memory to a floating point register
+;; specially, since this ocurrs frequently in int->double conversions.
+;; This is done with a define_split after reload converting the plain
+;; sign-extension into a load+unspec, which of course results in lds+cvtlq.
+;;
+;; Note that while we must retain the =f case in the insn for reload's
+;; benefit, it should be eliminated after reload, so we should never emit
+;; code for that case.  But we don't reject the possibility.
+
 (define_insn "extendsidi2"
-  [(set (match_operand:DI 0 "register_operand" "=r,r,*f")
-	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,*f")))]
+  [(set (match_operand:DI 0 "register_operand" "=r,r,?f")
+	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))]
   ""
   "@
    addl %1,$31,%0
    ldl %0,%1
-   cvtql %1,%0\;cvtlq %0,%0"
-  [(set_attr "type" "iaddlog,ld,fpop")])
+   lds %0,%1\;cvtlq %0,%0"
+  [(set_attr "type" "iadd,ild,fld")
+   (set_attr "length" "*,*,8")])
+
+;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
+(define_split
+  [(set (match_operand:DI 0 "hard_fp_register_operand" "")
+	(sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
+  "reload_completed"
+  [(set (match_dup 2) (match_dup 1))
+   (set (match_dup 0) (unspec:DI [(match_dup 2)] 4))]
+  "operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=f")
+	(unspec:DI [(match_operand:SI 1 "register_operand" "f")] 4))]
+  ""
+  "cvtlq %1,%0"
+  [(set_attr "type" "fadd")])
 
 ;; Do addsi3 the way expand_binop would do if we didn't have one.  This
 ;; generates better code.  We have the anonymous addsi3 pattern below in
@@ -95,10 +420,10 @@
 		 (match_operand:SI 2 "add_operand" "")))]
   ""
   "
-{ emit_insn (gen_rtx (SET, VOIDmode, gen_lowpart (DImode, operands[0]),
-		      gen_rtx (PLUS, DImode,
-			       gen_lowpart (DImode, operands[1]),
-			       gen_lowpart (DImode, operands[2]))));
+{ emit_insn (gen_rtx_SET (VOIDmode, gen_lowpart (DImode, operands[0]),
+			  gen_rtx_PLUS (DImode,
+					gen_lowpart (DImode, operands[1]),
+					gen_lowpart (DImode, operands[2]))));
   DONE;
 } ")
 
@@ -111,8 +436,7 @@
    addl %r1,%2,%0
    subl %r1,%n2,%0
    lda %0,%2(%r1)
-   ldah %0,%h2(%r1)"
-  [(set_attr "type" "iaddlog")])
+   ldah %0,%h2(%r1)")
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
@@ -139,8 +463,7 @@
   ""
   "@
    addl %r1,%2,%0
-   subl %r1,%n2,%0"
-  [(set_attr "type" "iaddlog")])
+   subl %r1,%n2,%0")
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -179,8 +502,8 @@
    (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
   "
 {
-  operands[6] = gen_rtx (GET_CODE (operands[1]), DImode,
-			 operands[2], operands[3]);
+  operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
+				operands[2], operands[3]);
   operands[7] = gen_lowpart (SImode, operands[5]);
 }")
 
@@ -193,8 +516,7 @@
    addq %r1,%2,%0
    subq %r1,%n2,%0
    lda %0,%2(%r1)
-   ldah %0,%h2(%r1)"
-  [(set_attr "type" "iaddlog")])
+   ldah %0,%h2(%r1)")
 
 ;; Don't do this if we are adjusting SP since we don't want to do
 ;; it in two steps. 
@@ -224,8 +546,7 @@
   ""
   "@
    s%2addl %r1,%3,%0
-   s%2subl %r1,%n3,%0"
-  [(set_attr "type" "iaddlog")])
+   s%2subl %r1,%n3,%0")
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r,r")
@@ -236,8 +557,7 @@
   ""
   "@
    s%2addl %r1,%3,%0
-   s%2subl %r1,%n3,%0"
-  [(set_attr "type" "iaddlog")])
+   s%2subl %r1,%n3,%0")
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -255,8 +575,8 @@
 				 (match_dup 5))))]
   "
 {
-  operands[7] = gen_rtx (GET_CODE (operands[1]), DImode,
-			 operands[2], operands[3]);
+  operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
+				operands[2], operands[3]);
   operands[8] = gen_lowpart (SImode, operands[6]);
 }")
 
@@ -268,8 +588,7 @@
   ""
   "@
    s%2addq %r1,%3,%0
-   s%2subq %1,%n3,%0"
-  [(set_attr "type" "iaddlog")])
+   s%2subq %1,%n3,%0")
 
 ;; These variants of the above insns can occur if the third operand
 ;; is the frame pointer.  This is a kludge, but there doesn't
@@ -281,8 +600,7 @@
 			  (match_operand:DI 2 "some_operand" "r"))
 		 (match_operand:DI 3 "some_operand" "rIOKL")))]
   "reload_in_progress"
-  "#"
-  [(set_attr "type" "iaddlog")])
+  "#")
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -301,8 +619,7 @@
 			  (match_operand:SI 3 "some_operand" "r"))
 		 (match_operand:SI 4 "some_operand" "rIOKL")))]
   "reload_in_progress"
-  "#"
-  [(set_attr "type" "iaddlog")])
+  "#")
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "r")
@@ -325,8 +642,7 @@
 		   (match_operand:SI 3 "some_operand" "r"))
 		  (match_operand:SI 4 "some_operand" "rIOKL"))))]
   "reload_in_progress"
-  "#"
-  [(set_attr "type" "iaddlog")])
+  "#")
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -351,8 +667,7 @@
 			  (match_operand:DI 3 "some_operand" "r"))
 		 (match_operand:DI 4 "some_operand" "rIOKL")))]
   "reload_in_progress"
-  "#"
-  [(set_attr "type" "iaddlog")])
+  "#")
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "=")
@@ -370,23 +685,20 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
   ""
-  "subl $31,%1,%0"
-  [(set_attr "type" "iaddlog")])
+  "subl $31,%1,%0")
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(sign_extend:DI (neg:SI
 			 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
   ""
-  "subl $31,%1,%0"
-  [(set_attr "type" "iaddlog")])
+  "subl $31,%1,%0")
 
 (define_insn "negdi2"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
   ""
-  "subq $31,%1,%0"
-  [(set_attr "type" "iaddlog")])
+  "subq $31,%1,%0")
 
 (define_expand "subsi3"
   [(set (match_operand:SI 0 "register_operand" "")
@@ -394,12 +706,11 @@
 		  (match_operand:SI 2 "reg_or_8bit_operand" "")))]
   ""
   "
-{ emit_insn (gen_rtx (SET, VOIDmode, gen_lowpart (DImode, operands[0]),
-		      gen_rtx (MINUS, DImode,
-			       gen_lowpart (DImode, operands[1]),
-			       gen_lowpart (DImode, operands[2]))));
+{ emit_insn (gen_rtx_SET (VOIDmode, gen_lowpart (DImode, operands[0]),
+			  gen_rtx_MINUS (DImode,
+					 gen_lowpart (DImode, operands[1]),
+					 gen_lowpart (DImode, operands[2]))));
   DONE;
-
 } ")
 
 (define_insn ""
@@ -407,24 +718,21 @@
 	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
 		  (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
   ""
-  "subl %r1,%2,%0"
-  [(set_attr "type" "iaddlog")])
+  "subl %r1,%2,%0")
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
 				  (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
   ""
-  "subl %r1,%2,%0"
-  [(set_attr "type" "iaddlog")])
+  "subl %r1,%2,%0")
 
 (define_insn "subdi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
 		  (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
   ""
-  "subq %r1,%2,%0"
-  [(set_attr "type" "iaddlog")])
+  "subq %r1,%2,%0")
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -432,8 +740,7 @@
 			   (match_operand:SI 2 "const48_operand" "I"))
 		  (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
   ""
-  "s%2subl %r1,%3,%0"
-  [(set_attr "type" "iaddlog")])
+  "s%2subl %r1,%3,%0")
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -442,8 +749,7 @@
 			    (match_operand:SI 2 "const48_operand" "I"))
 		   (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
   ""
-  "s%2subl %r1,%3,%0"
-  [(set_attr "type" "iaddlog")])
+  "s%2subl %r1,%3,%0")
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -451,8 +757,7 @@
 			   (match_operand:DI 2 "const48_operand" "I"))
 		  (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
   ""
-  "s%2subq %r1,%3,%0"
-  [(set_attr "type" "iaddlog")])
+  "s%2subq %r1,%3,%0")
 
 (define_insn "mulsi3"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -460,7 +765,8 @@
 		 (match_operand:SI 2 "reg_or_0_operand" "rJ")))]
   ""
   "mull %r1,%r2,%0"
-  [(set_attr "type" "imull")])
+  [(set_attr "type" "imul")
+   (set_attr "opsize" "si")])
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -468,7 +774,8 @@
 				 (match_operand:SI 2 "reg_or_0_operand" "rJ"))))]
   ""
   "mull %r1,%r2,%0"
-  [(set_attr "type" "imull")])
+  [(set_attr "type" "imul")
+   (set_attr "opsize" "si")])
 
 (define_insn "muldi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -476,7 +783,7 @@
 		 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
   ""
   "mulq %r1,%r2,%0"
-  [(set_attr "type" "imulq")])
+  [(set_attr "type" "imul")])
 
 (define_insn "umuldi3_highpart"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -487,7 +794,8 @@
 	  (const_int 64))))]
   ""
   "umulh %1,%2,%0"
-  [(set_attr "type" "imulq")])
+  [(set_attr "type" "imul")
+   (set_attr "opsize" "udi")])
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -498,61 +806,71 @@
 	  (const_int 64))))]
   ""
   "umulh %1,%2,%0"
-  [(set_attr "type" "imulq")])
+  [(set_attr "type" "imul")
+   (set_attr "opsize" "udi")])
 
 ;; The divide and remainder operations always take their inputs from
 ;; r24 and r25, put their output in r27, and clobber r23 and r28.
 
+;; ??? Force sign-extension here because some versions of OSF/1 don't
+;; do the right thing if the inputs are not properly sign-extended.
+;; But Linux, for instance, does not have this problem.  Is it worth
+;; the complication here to eliminate the sign extension?
+
 (define_expand "divsi3"
-  [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
-   (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
-   (parallel [(set (reg:SI 27)
-		   (div:SI (reg:SI 24)
-			   (reg:SI 25)))
+  [(set (reg:DI 24)
+	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
+   (set (reg:DI 25)
+	(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
+   (parallel [(set (reg:DI 27)
+		   (sign_extend:DI (div:SI (reg:DI 24) (reg:DI 25))))
 	      (clobber (reg:DI 23))
 	      (clobber (reg:DI 28))])
    (set (match_operand:SI 0 "general_operand" "")
-	(reg:SI 27))]
-  ""
+	(subreg:SI (reg:DI 27) 0))]
+  "!TARGET_OPEN_VMS"
   "")
 
 (define_expand "udivsi3"
-  [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
-   (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
-   (parallel [(set (reg:SI 27)
-		   (udiv:SI (reg:SI 24)
-			    (reg:SI 25)))
+  [(set (reg:DI 24)
+	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
+   (set (reg:DI 25)
+	(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
+   (parallel [(set (reg:DI 27)
+		   (sign_extend:DI (udiv:SI (reg:DI 24) (reg:DI 25))))
 	      (clobber (reg:DI 23))
 	      (clobber (reg:DI 28))])
    (set (match_operand:SI 0 "general_operand" "")
-	(reg:SI 27))]
-  ""
+	(subreg:SI (reg:DI 27) 0))]
+  "!TARGET_OPEN_VMS"
   "")
 
 (define_expand "modsi3"
-  [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
-   (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
-   (parallel [(set (reg:SI 27)
-		   (mod:SI (reg:SI 24)
-			   (reg:SI 25)))
+  [(set (reg:DI 24)
+	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
+   (set (reg:DI 25)
+	(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
+   (parallel [(set (reg:DI 27)
+		   (sign_extend:DI (mod:SI (reg:DI 24) (reg:DI 25))))
 	      (clobber (reg:DI 23))
 	      (clobber (reg:DI 28))])
    (set (match_operand:SI 0 "general_operand" "")
-	(reg:SI 27))]
-  ""
+	(subreg:SI (reg:DI 27) 0))]
+  "!TARGET_OPEN_VMS"
   "")
 
 (define_expand "umodsi3"
-  [(set (reg:SI 24) (match_operand:SI 1 "input_operand" ""))
-   (set (reg:SI 25) (match_operand:SI 2 "input_operand" ""))
-   (parallel [(set (reg:SI 27)
-		   (umod:SI (reg:SI 24)
-			    (reg:SI 25)))
+  [(set (reg:DI 24)
+	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
+   (set (reg:DI 25)
+	(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
+   (parallel [(set (reg:DI 27)
+		   (sign_extend:DI (umod:SI (reg:DI 24) (reg:DI 25))))
 	      (clobber (reg:DI 23))
 	      (clobber (reg:DI 28))])
    (set (match_operand:SI 0 "general_operand" "")
-	(reg:SI 27))]
-  ""
+	(subreg:SI (reg:DI 27) 0))]
+  "!TARGET_OPEN_VMS"
   "")
 
 (define_expand "divdi3"
@@ -565,7 +883,7 @@
 	      (clobber (reg:DI 28))])
    (set (match_operand:DI 0 "general_operand" "")
 	(reg:DI 27))]
-  ""
+  "!TARGET_OPEN_VMS"
   "")
 
 (define_expand "udivdi3"
@@ -578,7 +896,7 @@
 	      (clobber (reg:DI 28))])
    (set (match_operand:DI 0 "general_operand" "")
 	(reg:DI 27))]
-  ""
+  "!TARGET_OPEN_VMS"
   "")
 
 (define_expand "moddi3"
@@ -591,7 +909,7 @@
 	      (clobber (reg:DI 28))])
    (set (match_operand:DI 0 "general_operand" "")
 	(reg:DI 27))]
-  ""
+  "!TARGET_OPEN_VMS"
   "")
 
 (define_expand "umoddi3"
@@ -604,18 +922,21 @@
 	      (clobber (reg:DI 28))])
    (set (match_operand:DI 0 "general_operand" "")
 	(reg:DI 27))]
-  ""
+  "!TARGET_OPEN_VMS"
   "")
 
+;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
+;; expanded by the assembler.
 (define_insn ""
-  [(set (reg:SI 27)
-	(match_operator:SI 1 "divmod_operator"
-			[(reg:SI 24) (reg:SI 25)]))
+  [(set (reg:DI 27)
+	(sign_extend:DI (match_operator:SI 1 "divmod_operator"
+			[(reg:DI 24) (reg:DI 25)])))
    (clobber (reg:DI 23))
    (clobber (reg:DI 28))]
-  ""
+  "!TARGET_OPEN_VMS"
   "%E1 $24,$25,$27"
-  [(set_attr "type" "isubr")])
+  [(set_attr "type" "jsr")
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (reg:DI 27)
@@ -623,9 +944,10 @@
 			[(reg:DI 24) (reg:DI 25)]))
    (clobber (reg:DI 23))
    (clobber (reg:DI 28))]
-  ""
+  "!TARGET_OPEN_VMS"
   "%E1 $24,$25,$27"
-  [(set_attr "type" "isubr")])
+  [(set_attr "type" "jsr")
+   (set_attr "length" "8")])
 
 ;; Next are the basic logical operations.  These only exist in DImode.
 
@@ -638,12 +960,12 @@
    and %r1,%2,%0
    bic %r1,%N2,%0
    zapnot %r1,%m2,%0"
-  [(set_attr "type" "iaddlog,iaddlog,shiftcm")])
+  [(set_attr "type" "ilog,ilog,shift")])
 
-;; There are times when we can split and AND into two AND insns.  This occurs
+;; There are times when we can split an AND into two AND insns.  This occurs
 ;; when we can first clear any bytes and then clear anything else.  For
 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
-;; Only to this when running on 64-bit host since the computations are
+;; Only do this when running on 64-bit host since the computations are
 ;; too messy otherwise.
 
 (define_split
@@ -675,43 +997,103 @@
   [(set (match_operand:HI 0 "register_operand" "=r")
 	(zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
   ""
-  "zapnot %1,1,%0"
-  [(set_attr "type" "iaddlog")])
+  "and %1,0xff,%0"
+  [(set_attr "type" "ilog")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
+  "TARGET_BWX"
+  "@
+   and %1,0xff,%0
+   ldbu %0,%1"
+  [(set_attr "type" "ilog,ild")])
 
-(define_insn "zero_extendqisi2"
+(define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
+  "! TARGET_BWX"
+  "and %1,0xff,%0"
+  [(set_attr "type" "ilog")])
+
+(define_expand "zero_extendqisi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
   ""
-  "zapnot %1,1,%0"
-  [(set_attr "type" "iaddlog")])
+  "")
 
-(define_insn "zero_extendqidi2"
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+	(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
+  "TARGET_BWX"
+  "@
+   and %1,0xff,%0
+   ldbu %0,%1"
+  [(set_attr "type" "ilog,ild")])
+
+(define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
+  "! TARGET_BWX"
+  "and %1,0xff,%0"
+  [(set_attr "type" "ilog")])
+  
+(define_expand "zero_extendqidi2"
+  [(set (match_operand:DI 0 "register_operand" "")
+	(zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
   ""
-  "zapnot %1,1,%0"
-  [(set_attr "type" "iaddlog")])
+  "")
+  
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r,r")
+	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
+  "TARGET_BWX"
+  "@
+   zapnot %1,3,%0
+   ldwu %0,%1"
+  [(set_attr "type" "shift,ild")])
 
-(define_insn "zero_extendhisi2"
+(define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
-  ""
+  "! TARGET_BWX"
   "zapnot %1,3,%0"
-  [(set_attr "type" "iaddlog")])
+  [(set_attr "type" "shift")])
+
+(define_expand "zero_extendhisi2"
+  [(set (match_operand:SI 0 "register_operand" "")
+	(zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
+  ""
+  "")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+	(zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
+  "TARGET_BWX"
+  "@
+   zapnot %1,3,%0
+   ldwu %0,%1"
+  [(set_attr "type" "shift,ild")])
 
-(define_insn "zero_extendhidi2"
+(define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
   ""
   "zapnot %1,3,%0"
-  [(set_attr "type" "iaddlog")])
+  [(set_attr "type" "shift")])
+
+(define_expand "zero_extendhidi2"
+  [(set (match_operand:DI 0 "register_operand" "")
+	(zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
+  ""
+  "")
 
 (define_insn "zero_extendsidi2"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
   ""
   "zapnot %1,15,%0"
-  [(set_attr "type" "iaddlog")])
+  [(set_attr "type" "shift")])
 
 (define_insn  ""
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -719,7 +1101,7 @@
 		(match_operand:DI 2 "reg_or_0_operand" "rJ")))]
   ""
   "bic %r2,%1,%0"
-  [(set_attr "type" "iaddlog")])
+  [(set_attr "type" "ilog")])
 
 (define_insn "iordi3"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
@@ -729,14 +1111,14 @@
   "@
    bis %r1,%2,%0
    ornot %r1,%N2,%0"
-  [(set_attr "type" "iaddlog")])
+  [(set_attr "type" "ilog")])
 
 (define_insn "one_cmpldi2"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
   ""
   "ornot $31,%1,%0"
-  [(set_attr "type" "iaddlog")])
+  [(set_attr "type" "ilog")])
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -744,7 +1126,7 @@
 		(match_operand:DI 2 "reg_or_0_operand" "rJ")))]
   ""
   "ornot %r2,%1,%0"
-  [(set_attr "type" "iaddlog")])
+  [(set_attr "type" "ilog")])
 
 (define_insn "xordi3"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
@@ -754,7 +1136,7 @@
   "@
    xor %r1,%2,%0
    eqv %r1,%N2,%0"
-  [(set_attr "type" "iaddlog")])
+  [(set_attr "type" "ilog")])
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -762,14 +1144,40 @@
 			(match_operand:DI 2 "register_operand" "rI"))))]
   ""
   "eqv %r1,%2,%0"
-  [(set_attr "type" "iaddlog")])
+  [(set_attr "type" "ilog")])
+
+;; Handle the FFS insn if we support CIX. 
+
+(define_expand "ffsdi2"
+  [(set (match_dup 2)
+	(unspec [(match_operand:DI 1 "register_operand" "")] 1))
+   (set (match_dup 3)
+	(plus:DI (match_dup 2) (const_int 1)))
+   (set (match_operand:DI 0 "register_operand" "")
+	(if_then_else:DI (eq (match_dup 1) (const_int 0))
+			 (const_int 0) (match_dup 3)))]
+  "TARGET_CIX"
+  "
+{
+  operands[2] = gen_reg_rtx (DImode);
+  operands[3] = gen_reg_rtx (DImode);
+}")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(unspec [(match_operand:DI 1 "register_operand" "r")] 1))]
+  "TARGET_CIX"
+  "cttz %1,%0"
+  ; ev6 calls all mvi and cttz/ctlz/popc class imisc, so just 
+  ; reuse the existing type name.
+  [(set_attr "type" "mvi")])
 
 ;; Next come the shifts and the various extract and insert operations.
 
 (define_insn "ashldi3"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
 	(ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
-		   (match_operand:DI 2 "reg_or_6bit_operand" "P,rI")))]
+		   (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
   ""
   "*
 {
@@ -782,9 +1190,11 @@
 	return \"s%P2addq %r1,0,%0\";
     case 1:
       return \"sll %r1,%2,%0\";
+    default:
+      abort();
     }
 }"
-  [(set_attr "type" "iaddlog,shiftcm")])
+  [(set_attr "type" "iadd,shift")])
 
 ;; ??? The following pattern is made by combine, but earlier phases
 ;; (specifically flow) can't handle it.  This occurs in jump.c.  Deal
@@ -803,224 +1213,469 @@
 ;;  else
 ;;    return \"s%P2addl %r1,0,%0\";
 ;; }"
-;;  [(set_attr "type" "iaddlog")])
+;;  [(set_attr "type" "iadd")])
 			  
 (define_insn "lshrdi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-		     (match_operand:DI 2 "reg_or_6bit_operand" "rI")))]
+		     (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
   ""
-  "srl %r1,%2,%0")
+  "srl %r1,%2,%0"
+  [(set_attr "type" "shift")])
 
 (define_insn "ashrdi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-		     (match_operand:DI 2 "reg_or_6bit_operand" "rI")))]
+		     (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
   ""
-  "sra %r1,%2,%0")
+  "sra %r1,%2,%0"
+  [(set_attr "type" "shift")])
 
 (define_expand "extendqihi2"
   [(set (match_dup 2)
-	(ashift:DI (match_operand:QI 1 "register_operand" "")
+	(ashift:DI (match_operand:QI 1 "some_operand" "")
 		   (const_int 56)))
    (set (match_operand:HI 0 "register_operand" "")
 	(ashiftrt:DI (match_dup 2)
 		     (const_int 56)))]
   ""
   "
-{ operands[0] = gen_lowpart (DImode, operands[0]);
-  operands[1] = gen_lowpart (DImode, operands[1]);
+{
+  if (TARGET_BWX)
+    {
+      emit_insn (gen_extendqihi2x (operands[0],
+				   force_reg (QImode, operands[1])));
+      DONE;
+    }
+ 
+ /* If we have an unaligned MEM, extend to DImode (which we do
+     specially) and then copy to the result.  */
+  if (unaligned_memory_operand (operands[1], HImode))
+    {
+      rtx temp = gen_reg_rtx (DImode);
+
+      emit_insn (gen_extendqidi2 (temp, operands[1]));
+      emit_move_insn (operands[0], gen_lowpart (HImode, temp));
+      DONE;
+    }
+
+  operands[0] = gen_lowpart (DImode, operands[0]);
+  operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
   operands[2] = gen_reg_rtx (DImode);
 }")
 
+(define_insn "extendqidi2x"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
+  "TARGET_BWX"
+  "sextb %1,%0"
+  [(set_attr "type" "shift")])
+
+(define_insn "extendhidi2x"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
+  "TARGET_BWX"
+  "sextw %1,%0"
+  [(set_attr "type" "shift")])
+
+(define_insn "extendqisi2x"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
+  "TARGET_BWX"
+  "sextb %1,%0"
+  [(set_attr "type" "shift")])
+
+(define_insn "extendhisi2x"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
+  "TARGET_BWX"
+  "sextw %1,%0"
+  [(set_attr "type" "shift")])
+
+(define_insn "extendqihi2x"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
+  "TARGET_BWX"
+  "sextb %1,%0"
+  [(set_attr "type" "shift")])
+
 (define_expand "extendqisi2"
   [(set (match_dup 2)
-	(ashift:DI (match_operand:QI 1 "register_operand" "")
+	(ashift:DI (match_operand:QI 1 "some_operand" "")
 		   (const_int 56)))
    (set (match_operand:SI 0 "register_operand" "")
 	(ashiftrt:DI (match_dup 2)
 		     (const_int 56)))]
   ""
   "
-{ operands[0] = gen_lowpart (DImode, operands[0]);
-  operands[1] = gen_lowpart (DImode, operands[1]);
+{
+  if (TARGET_BWX)
+    {
+      emit_insn (gen_extendqisi2x (operands[0],
+				   force_reg (QImode, operands[1])));
+      DONE;
+    }
+
+  /* If we have an unaligned MEM, extend to a DImode form of
+     the result (which we do specially).  */
+  if (unaligned_memory_operand (operands[1], QImode))
+    {
+      rtx temp = gen_reg_rtx (DImode);
+
+      emit_insn (gen_extendqidi2 (temp, operands[1]));
+      emit_move_insn (operands[0], gen_lowpart (SImode, temp));
+      DONE;
+    }
+
+  operands[0] = gen_lowpart (DImode, operands[0]);
+  operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
   operands[2] = gen_reg_rtx (DImode);
 }")
 
 (define_expand "extendqidi2"
   [(set (match_dup 2)
-	(ashift:DI (match_operand:QI 1 "register_operand" "")
+	(ashift:DI (match_operand:QI 1 "some_operand" "")
 		   (const_int 56)))
    (set (match_operand:DI 0 "register_operand" "")
 	(ashiftrt:DI (match_dup 2)
 		     (const_int 56)))]
   ""
   "
-{ operands[1] = gen_lowpart (DImode, operands[1]);
+{
+  if (TARGET_BWX)
+    {
+      emit_insn (gen_extendqidi2x (operands[0],
+				   force_reg (QImode, operands[1])));
+      DONE;
+    }
+
+  if (unaligned_memory_operand (operands[1], QImode))
+    {
+      rtx seq
+	= gen_unaligned_extendqidi (operands[0],
+				    get_unaligned_address (operands[1], 1));
+
+      alpha_set_memflags (seq, operands[1]);
+      emit_insn (seq);
+      DONE;
+    }
+
+  operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
   operands[2] = gen_reg_rtx (DImode);
 }")
 
 (define_expand "extendhisi2"
   [(set (match_dup 2)
-	(ashift:DI (match_operand:HI 1 "register_operand" "")
+	(ashift:DI (match_operand:HI 1 "some_operand" "")
 		   (const_int 48)))
    (set (match_operand:SI 0 "register_operand" "")
 	(ashiftrt:DI (match_dup 2)
 		     (const_int 48)))]
   ""
   "
-{ operands[0] = gen_lowpart (DImode, operands[0]);
-  operands[1] = gen_lowpart (DImode, operands[1]);
+{
+  if (TARGET_BWX)
+    {
+      emit_insn (gen_extendhisi2x (operands[0],
+				   force_reg (HImode, operands[1])));
+      DONE;
+    }
+
+  /* If we have an unaligned MEM, extend to a DImode form of
+     the result (which we do specially).  */
+  if (unaligned_memory_operand (operands[1], HImode))
+    {
+      rtx temp = gen_reg_rtx (DImode);
+
+      emit_insn (gen_extendhidi2 (temp, operands[1]));
+      emit_move_insn (operands[0], gen_lowpart (SImode, temp));
+      DONE;
+    }
+
+  operands[0] = gen_lowpart (DImode, operands[0]);
+  operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
   operands[2] = gen_reg_rtx (DImode);
 }")
 
 (define_expand "extendhidi2"
   [(set (match_dup 2)
-	(ashift:DI (match_operand:HI 1 "register_operand" "")
+	(ashift:DI (match_operand:HI 1 "some_operand" "")
 		   (const_int 48)))
    (set (match_operand:DI 0 "register_operand" "")
 	(ashiftrt:DI (match_dup 2)
 		     (const_int 48)))]
   ""
   "
-{ operands[1] = gen_lowpart (DImode, operands[1]);
+{
+  if (TARGET_BWX)
+    {
+      emit_insn (gen_extendhidi2x (operands[0],
+				   force_reg (HImode, operands[1])));
+      DONE;
+    }
+
+  if (unaligned_memory_operand (operands[1], HImode))
+    {
+      rtx seq
+	= gen_unaligned_extendhidi (operands[0],
+				    get_unaligned_address (operands[1], 2));
+
+      alpha_set_memflags (seq, operands[1]);
+      emit_insn (seq);
+      DONE;
+    }
+
+  operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
   operands[2] = gen_reg_rtx (DImode);
 }")
 
+;; Here's how we sign extend an unaligned byte and halfword.  Doing this
+;; as a pattern saves one instruction.  The code is similar to that for
+;; the unaligned loads (see below).
+;;
+;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
+(define_expand "unaligned_extendqidi"
+  [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
+   (set (match_dup 3)
+	(mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
+			(const_int -8))))
+   (set (match_dup 4)
+	(ashift:DI (match_dup 3)
+		   (minus:DI (const_int 56)
+			     (ashift:DI
+			      (and:DI (plus:DI (match_dup 2) (const_int -1))
+				      (const_int 7))
+			      (const_int 3)))))
+   (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
+	(ashiftrt:DI (match_dup 4) (const_int 56)))]
+  ""
+  "
+{ operands[2] = gen_reg_rtx (DImode);
+  operands[3] = gen_reg_rtx (DImode);
+  operands[4] = gen_reg_rtx (DImode);
+}")
+
+(define_expand "unaligned_extendhidi"
+  [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
+   (set (match_dup 3)
+	(mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
+			(const_int -8))))
+   (set (match_dup 4)
+	(ashift:DI (match_dup 3)
+		   (minus:DI (const_int 56)
+			     (ashift:DI
+			      (and:DI (plus:DI (match_dup 2) (const_int -1))
+				      (const_int 7))
+			      (const_int 3)))))
+   (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
+	(ashiftrt:DI (match_dup 4) (const_int 48)))]
+  ""
+  "
+{ operands[2] = gen_reg_rtx (DImode);
+  operands[3] = gen_reg_rtx (DImode);
+  operands[4] = gen_reg_rtx (DImode);
+}")
+
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
 			 (match_operand:DI 2 "mode_width_operand" "n")
 			 (match_operand:DI 3 "mul8_operand" "I")))]
   ""
-  "ext%M2l %r1,%s3,%0")
+  "ext%M2l %r1,%s3,%0"
+  [(set_attr "type" "shift")])
 
-(define_insn ""
+(define_insn "extxl"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
 			 (match_operand:DI 2 "mode_width_operand" "n")
 			 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
 				    (const_int 3))))]
   ""
-  "ext%M2l %r1,%3,%0")
+  "ext%M2l %r1,%3,%0"
+  [(set_attr "type" "shift")])
 
-(define_insn ""
+(define_insn "extqh"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashift:DI
-	 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-			  (const_int 8)
-			  (ashift:DI
-			   (plus:DI
-			    (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-			    (const_int -1))
-			   (const_int 3)))
-	 (const_int 56)))]
-  ""
-  "extqh %r1,%2,%0")
-
-(define_insn ""
+	 (match_operand:DI 1 "reg_or_0_operand" "rJ")
+	  (minus:DI (const_int 56)
+		    (ashift:DI
+		     (and:DI
+		      (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
+			       (const_int -1))
+		      (const_int 7))
+		     (const_int 3)))))]
+  ""
+  "extqh %r1,%2,%0"
+  [(set_attr "type" "shift")])
+
+(define_insn "extlh"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashift:DI
-	 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-			  (const_int 16)
-			  (ashift:DI
-			   (plus:DI
-			    (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-			    (const_int -2))
-			   (const_int 3)))
-	 (const_int 48)))]
-  ""
-  "extwh %r1,%2,%0")
-
-(define_insn ""
+	 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
+		 (const_int 2147483647))
+	 (minus:DI (const_int 56)
+		    (ashift:DI
+		     (and:DI
+		      (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
+			       (const_int -1))
+		      (const_int 7))
+		     (const_int 3)))))]
+  ""
+  "extlh %r1,%2,%0"
+  [(set_attr "type" "shift")])
+
+(define_insn "extwh"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashift:DI
-	 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
-			  (const_int 32)
-			  (ashift:DI
-			   (plus:DI
-			    (match_operand:DI 2 "reg_or_8bit_operand" "rI")
-			    (const_int -4))
-			   (const_int 3)))
-	 (const_int 32)))]
-  ""
-  "extlh %r1,%2,%0")
+	 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
+		 (const_int 65535))
+	 (minus:DI (const_int 56)
+		    (ashift:DI
+		     (and:DI
+		      (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
+			       (const_int -1))
+		      (const_int 7))
+		     (const_int 3)))))]
+  ""
+  "extwh %r1,%2,%0"
+  [(set_attr "type" "shift")])
 
 ;; This converts an extXl into an extXh with an appropriate adjustment
 ;; to the address calculation.
 
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
-				    (match_operand:DI 2 "mode_width_operand" "")
-				    (ashift:DI (match_operand:DI 3 "" "")
-					       (const_int 3)))
-		   (match_operand:DI 4 "const_int_operand" "")))
-   (clobber (match_operand:DI 5 "register_operand" ""))]
-  "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
-  [(set (match_dup 5) (match_dup 6))
-   (set (match_dup 0)
-	(ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
-				    (ashift:DI (plus:DI (match_dup 5)
-							(match_dup 7))
-					       (const_int 3)))
-		   (match_dup 4)))]
-  "
-{
-  operands[6] = plus_constant (operands[3], 
-			       INTVAL (operands[2]) / BITS_PER_UNIT);
-  operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
-}")
+;;(define_split
+;;  [(set (match_operand:DI 0 "register_operand" "")
+;;	(ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
+;;				    (match_operand:DI 2 "mode_width_operand" "")
+;;				    (ashift:DI (match_operand:DI 3 "" "")
+;;					       (const_int 3)))
+;;		   (match_operand:DI 4 "const_int_operand" "")))
+;;   (clobber (match_operand:DI 5 "register_operand" ""))]
+;;  "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
+;;  [(set (match_dup 5) (match_dup 6))
+;;   (set (match_dup 0)
+;;	(ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
+;;				    (ashift:DI (plus:DI (match_dup 5)
+;;							(match_dup 7))
+;;					       (const_int 3)))
+;;		   (match_dup 4)))]
+;;  "
+;;{
+;;  operands[6] = plus_constant (operands[3], 
+;;			       INTVAL (operands[2]) / BITS_PER_UNIT);
+;;  operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
+;;}")
   
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
 		   (match_operand:DI 2 "mul8_operand" "I")))]
   ""
-  "insbl %1,%s2,%0")
+  "insbl %1,%s2,%0"
+  [(set_attr "type" "shift")])
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
 		   (match_operand:DI 2 "mul8_operand" "I")))]
   ""
-  "inswl %1,%s2,%0")
+  "inswl %1,%s2,%0"
+  [(set_attr "type" "shift")])
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
 		   (match_operand:DI 2 "mul8_operand" "I")))]
   ""
-  "insll %1,%s2,%0")
+  "insll %1,%s2,%0"
+  [(set_attr "type" "shift")])
 
-(define_insn ""
+(define_insn "insbl"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
 		   (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
 			      (const_int 3))))]
   ""
-  "insbl %1,%2,%0")
+  "insbl %1,%2,%0"
+  [(set_attr "type" "shift")])
 
-(define_insn ""
+(define_insn "inswl"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
 		   (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
 			      (const_int 3))))]
   ""
-  "inswl %1,%2,%0")
+  "inswl %1,%2,%0"
+  [(set_attr "type" "shift")])
 
-(define_insn ""
+(define_insn "insll"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
 		   (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
 			      (const_int 3))))]
   ""
-  "insll %1,%2,%0")
+  "insll %1,%2,%0"
+  [(set_attr "type" "shift")])
+
+(define_insn "insql"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(ashift:DI (match_operand:DI 1 "register_operand" "r")
+		   (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
+			      (const_int 3))))]
+  ""
+  "insql %1,%2,%0"
+  [(set_attr "type" "shift")])
+
+;; Combine has this sometimes habit of moving the and outside of the
+;; shift, making life more interesting.
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
+		   	   (match_operand:DI 2 "mul8_operand" "I"))
+		(match_operand:DI 3 "immediate_operand" "i")))]
+  "HOST_BITS_PER_WIDE_INT == 64
+   && GET_CODE (operands[3]) == CONST_INT
+   && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
+        == INTVAL (operands[3]))
+       || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
+        == INTVAL (operands[3]))
+       || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
+        == INTVAL (operands[3])))"
+  "*
+{
+#if HOST_BITS_PER_WIDE_INT == 64
+  if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
+      == INTVAL (operands[3]))
+    return \"insbl %1,%s2,%0\";
+  if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
+      == INTVAL (operands[3]))
+    return \"inswl %1,%s2,%0\";
+  if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
+      == INTVAL (operands[3]))
+    return \"insll %1,%s2,%0\";
+#endif
+  abort();
+}"
+  [(set_attr "type" "shift")])
 
 ;; We do not include the insXh insns because they are complex to express
 ;; and it does not appear that we would ever want to generate them.
+;;
+;; Since we need them for block moves, though, cop out and use unspec.
 
-(define_insn ""
+(define_insn "insxh"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(unspec [(match_operand:DI 1 "register_operand" "r")
+		 (match_operand:DI 2 "mode_width_operand" "n")
+		 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 2))]
+  ""
+  "ins%M2h %1,%3,%0"
+  [(set_attr "type" "shift")])
+
+(define_insn "mskxl"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(and:DI (not:DI (ashift:DI
 			 (match_operand:DI 2 "mode_mask_operand" "n")
@@ -1029,10 +1684,22 @@
 			  (const_int 3))))
 		(match_operand:DI 1 "reg_or_0_operand" "rJ")))]
   ""
-  "msk%U2l %r1,%3,%0")
+  "msk%U2l %r1,%3,%0"
+  [(set_attr "type" "shift")])
 
-;; We do not include the mskXh insns because it does not appear we would ever
-;; generate one.
+;; We do not include the mskXh insns because it does not appear we would
+;; ever generate one.
+;;
+;; Again, we do for block moves and we use unspec again.
+
+(define_insn "mskxh"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(unspec [(match_operand:DI 1 "register_operand" "r")
+		 (match_operand:DI 2 "mode_width_operand" "n")
+		 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 3))]
+  ""
+  "msk%M2h %1,%3,%0"
+  [(set_attr "type" "shift")])
 
 ;; Floating-point operations.  All the double-precision insns can extend
 ;; from single, so indicate that.  The exception are the ones that simply
@@ -1043,53 +1710,74 @@
 	(abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
   "cpys $f31,%R1,%0"
-  [(set_attr "type" "fpop")])
+  [(set_attr "type" "fcpys")])
 
 (define_insn "absdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
   "cpys $f31,%R1,%0"
-  [(set_attr "type" "fpop")])
+  [(set_attr "type" "fcpys")])
 
 (define_insn "negsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
   "cpysn %R1,%R1,%0"
-  [(set_attr "type" "fpop")])
+  [(set_attr "type" "fadd")])
 
 (define_insn "negdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
   "cpysn %R1,%R1,%0"
-  [(set_attr "type" "fpop")])
+  [(set_attr "type" "fadd")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=&f")
+	(plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
+		 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "add%,%)%& %R1,%R2,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
 
 (define_insn "addsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
 		 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
-  "adds %R1,%R2,%0"
-  [(set_attr "type" "fpop")])
+  "add%,%)%& %R1,%R2,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=&f")
+	(plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
+		 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "add%-%)%& %R1,%R2,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
 
 (define_insn "adddf3"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
 		 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
-  "addt %R1,%R2,%0"
-  [(set_attr "type" "fpop")])
+  "add%-%)%& %R1,%R2,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(plus:DF (float_extend:DF
 		  (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
 		 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
-  "addt %R1,%R2,%0"
-  [(set_attr "type" "fpop")])
+  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
+  "add%-%)%& %R1,%R2,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -1097,120 +1785,344 @@
 		  (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
 		 (float_extend:DF
 		  (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
+  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
+  "add%-%)%& %R1,%R2,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+;; Define conversion operators between DFmode and SImode, using the cvtql
+;; instruction.  To allow combine et al to do useful things, we keep the
+;; operation as a unit until after reload, at which point we split the
+;; instructions.
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(fix:SI (match_operand:DF 1 "reg_or_fp0_operand" "")))
+   (clobber (match_scratch:DI 2 ""))]
+  "TARGET_FP && reload_completed"
+  [(set (match_dup 2) (fix:DI (match_dup 1)))
+   (set (match_dup 0) (unspec:SI [(match_dup 2)] 5))]
+  "")
+
+;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(fix:SI (match_operand:DF 1 "reg_or_fp0_operand" "")))]
+  "TARGET_FP && reload_completed"
+  [(set (match_dup 2) (fix:DI (match_dup 1)))
+   (set (match_dup 0) (unspec:SI [(match_dup 2)] 5))]
+  "operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=f")
+	(unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")] 5))]
   "TARGET_FP"
-  "addt %R1,%R2,%0"
-  [(set_attr "type" "fpop")])
+  "cvtql%` %R1,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+(define_insn "fix_truncdfsi2_tp"
+  [(set (match_operand:SI 0 "register_operand" "=&f")
+	(fix:SI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))
+   (clobber (match_scratch:DI 2 "=&f"))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "#"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=f")
+	(fix:SI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
+  "#"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+(define_expand "fix_truncdfsi2"
+  [(set (match_operand:SI 0 "register_operand" "=f")
+	(fix:SI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+  "TARGET_FP"
+  "{ if (alpha_tp == ALPHA_TP_INSN)
+       { emit_insn(gen_fix_truncdfsi2_tp(operands[0], operands[1])); DONE; }
+   }")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=&f")
+	(fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "cvt%-q%(c %R1,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
 
 (define_insn "fix_truncdfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
 	(fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
-  "cvttqc %R1,%0"
-  [(set_attr "type" "fpop")])
+  "cvt%-q%(c %R1,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+;; Likewise between SFmode and SImode.
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(fix:SI (float_extend:DF
+		 (match_operand:SF 1 "reg_or_fp0_operand" ""))))
+   (clobber (match_scratch:DI 2 ""))]
+  "TARGET_FP && reload_completed"
+  [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
+   (set (match_dup 0) (unspec:SI [(match_dup 2)] 5))]
+  "")
+
+;; Due to issues with CLASS_CANNOT_CHANGE_SIZE, we cannot use a subreg here.
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(fix:SI (float_extend:DF
+		 (match_operand:SF 1 "reg_or_fp0_operand" ""))))]
+  "TARGET_FP && reload_completed"
+  [(set (match_dup 2) (fix:DI (float_extend:DF (match_dup 1))))
+   (set (match_dup 0) (unspec:SI [(match_dup 2)] 5))]
+  "operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));")
+
+(define_insn "fix_truncsfsi2_tp"
+  [(set (match_operand:SI 0 "register_operand" "=&f")
+	(fix:SI (float_extend:DF
+		 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))
+   (clobber (match_scratch:DI 2 "=&f"))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "#"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=f")
+	(fix:SI (float_extend:DF
+		 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
+  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
+  "#"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+(define_expand "fix_truncsfsi2"
+  [(set (match_operand:SI 0 "register_operand" "=f")
+	(fix:SI (float_extend:DF
+		 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
+  "TARGET_FP"
+  "{ if (alpha_tp == ALPHA_TP_INSN)
+       { emit_insn(gen_fix_truncsfsi2_tp(operands[0], operands[1])); DONE; }
+   }")
+
+(define_insn ""
+  [(set (match_operand:DI 0 "register_operand" "=&f")
+	(fix:DI (float_extend:DF
+		 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "cvt%-q%(c %R1,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
 
 (define_insn "fix_truncsfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
 	(fix:DI (float_extend:DF
 		 (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))]
   "TARGET_FP"
-  "cvttqc %R1,%0"
-  [(set_attr "type" "fpop")])
+  "cvt%-q%(c %R1,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=&f")
+	(float:SF (match_operand:DI 1 "register_operand" "f")))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "cvtq%,%+%& %1,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
 
 (define_insn "floatdisf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(float:SF (match_operand:DI 1 "register_operand" "f")))]
   "TARGET_FP"
-  "cvtqs %1,%0"
-  [(set_attr "type" "fpop")])
+  "cvtq%,%+%& %1,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=&f")
+	(float:DF (match_operand:DI 1 "register_operand" "f")))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "cvtq%-%+%& %1,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
 
 (define_insn "floatdidf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(float:DF (match_operand:DI 1 "register_operand" "f")))]
   "TARGET_FP"
-  "cvtqt %1,%0"
-  [(set_attr "type" "fpop")])
+  "cvtq%-%+%& %1,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
 
-(define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f,f")
-	(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
+(define_expand "extendsfdf2"
+  [(use (match_operand:DF 0 "register_operand" ""))
+   (use (match_operand:SF 1 "nonimmediate_operand" ""))]
   "TARGET_FP"
+"
+{
+  if (alpha_tp == ALPHA_TP_INSN)
+    emit_insn (gen_extendsfdf2_tp (operands[0],
+				   force_reg (SFmode, operands[1])));
+  else
+    emit_insn (gen_extendsfdf2_no_tp (operands[0], operands[1]));
+
+  DONE;
+}")
+;; FIXME
+(define_insn "extendsfdf2_tp"
+  [(set (match_operand:DF 0 "register_operand" "=&f")
+	(float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "cvtsts %1,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+(define_insn "extendsfdf2_no_tp"
+  [(set (match_operand:DF 0 "register_operand" "=f,f,m")
+	(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
+  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
   "@
-   addt $f31,%1,%0
-   lds %0,%1"
-  [(set_attr "type" "fpop,ld")])
+   cpys %1,%1,%0
+   ld%, %0,%1
+   st%- %1,%0"
+  [(set_attr "type" "fcpys,fld,fst")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=&f")
+	(float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "cvt%-%,%)%& %R1,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
 
 (define_insn "truncdfsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
-  "cvtts %R1,%0"
-  [(set_attr "type" "fpop")])
+  "cvt%-%,%)%& %R1,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=&f")
+	(div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
+		(match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "div%,%)%& %R1,%R2,%0"
+  [(set_attr "type" "fdiv")
+   (set_attr "opsize" "si")
+   (set_attr "trap" "yes")])
 
 (define_insn "divsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
 		(match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
-  "divs %R1,%R2,%0"
-  [(set_attr "type" "fdivs")])
+  "div%,%)%& %R1,%R2,%0"
+  [(set_attr "type" "fdiv")
+   (set_attr "opsize" "si")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=&f")
+	(div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
+		(match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "div%-%)%& %R1,%R2,%0"
+  [(set_attr "type" "fdiv")
+   (set_attr "trap" "yes")])
 
 (define_insn "divdf3"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
 		(match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
-  "divt %R1,%R2,%0"
-  [(set_attr "type" "fdivt")])
+  "div%-%)%& %R1,%R2,%0"
+  [(set_attr "type" "fdiv")
+   (set_attr "trap" "yes")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
 		(match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
-  "divt %R1,%R2,%0"
-  [(set_attr "type" "fdivt")])
+  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
+  "div%-%)%& %R1,%R2,%0"
+  [(set_attr "type" "fdiv")
+   (set_attr "trap" "yes")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
 		(float_extend:DF
 		 (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
-  "TARGET_FP"
-  "divt %R1,%R2,%0"
-  [(set_attr "type" "fdivt")])
+  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
+  "div%-%)%& %R1,%R2,%0"
+  [(set_attr "type" "fdiv")
+   (set_attr "trap" "yes")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
 		(float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
-  "TARGET_FP"
-  "divt %R1,%R2,%0"
-  [(set_attr "type" "fdivt")])
+  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
+  "div%-%)%& %R1,%R2,%0"
+  [(set_attr "type" "fdiv")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=&f")
+	(mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
+		 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "mul%,%)%& %R1,%R2,%0"
+  [(set_attr "type" "fmul")
+   (set_attr "trap" "yes")])
 
 (define_insn "mulsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG")
 		 (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
-  "muls %R1,%R2,%0"
-  [(set_attr "type" "fpop")])
+  "mul%,%)%& %R1,%R2,%0"
+  [(set_attr "type" "fmul")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=&f")
+	(mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
+		 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "mul%-%)%& %R1,%R2,%0"
+  [(set_attr "type" "fmul")
+   (set_attr "trap" "yes")])
 
 (define_insn "muldf3"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG")
 		 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
-  "mult %R1,%R2,%0"
-  [(set_attr "type" "fpop")])
+  "mul%-%)%& %R1,%R2,%0"
+  [(set_attr "type" "fmul")
+   (set_attr "trap" "yes")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(mult:DF (float_extend:DF
 		  (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
 		 (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
-  "mult %R1,%R2,%0"
-  [(set_attr "type" "fpop")])
+  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
+  "mul%-%)%& %R1,%R2,%0"
+  [(set_attr "type" "fmul")
+   (set_attr "trap" "yes")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -1218,43 +2130,66 @@
 		  (match_operand:SF 1 "reg_or_fp0_operand" "%fG"))
 		 (float_extend:DF
 		  (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
-  "TARGET_FP"
-  "mult %R1,%R2,%0"
-  [(set_attr "type" "fpop")])
+  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
+  "mul%-%)%& %R1,%R2,%0"
+  [(set_attr "type" "fmul")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=&f")
+	(minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
+		  (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "sub%,%)%& %R1,%R2,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
 
 (define_insn "subsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")
 		  (match_operand:SF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
-  "subs %R1,%R2,%0"
-  [(set_attr "type" "fpop")])
+  "sub%,%)%& %R1,%R2,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=&f")
+	(minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
+		  (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "sub%-%)%& %R1,%R2,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
 
 (define_insn "subdf3"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
 		  (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
   "TARGET_FP"
-  "subt %R1,%R2,%0"
-  [(set_attr "type" "fpop")])
+  "sub%-%)%& %R1,%R2,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(minus:DF (float_extend:DF
 		   (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
 		  (match_operand:DF 2 "reg_or_fp0_operand" "fG")))]
-  "TARGET_FP"
-  "subt %R1,%R2,%0"
-  [(set_attr "type" "fpop")])
+  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
+  "sub%-%)%& %R1,%R2,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")
 		  (float_extend:DF
 		   (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
-  "TARGET_FP"
-  "subt %R1,%R2,%0"
-  [(set_attr "type" "fpop")])
+  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
+  "sub%-%)%& %R1,%R2,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -1262,9 +2197,44 @@
 		   (match_operand:SF 1 "reg_or_fp0_operand" "fG"))
 		  (float_extend:DF
 		   (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))]
-  "TARGET_FP"
-  "subt %R1,%R2,%0"
-  [(set_attr "type" "fpop")])
+  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
+  "sub%-%)%& %R1,%R2,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=&f")
+	(sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
+  "TARGET_FP && TARGET_CIX && alpha_tp == ALPHA_TP_INSN"
+  "sqrt%,%)%& %R1,%0"
+  [(set_attr "type" "fsqrt")
+   (set_attr "opsize" "si")
+   (set_attr "trap" "yes")])
+
+(define_insn "sqrtsf2"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))]
+  "TARGET_FP && TARGET_CIX"
+  "sqrt%,%)%& %R1,%0"
+  [(set_attr "type" "fsqrt")
+   (set_attr "opsize" "si")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=&f")
+	(sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+  "TARGET_FP && TARGET_CIX && alpha_tp == ALPHA_TP_INSN"
+  "sqrt%-%)%& %R1,%0"
+  [(set_attr "type" "fsqrt")
+   (set_attr "trap" "yes")])
+
+(define_insn "sqrtdf2"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))]
+  "TARGET_FP && TARGET_CIX"
+  "sqrt%-%)%& %1,%0"
+  [(set_attr "type" "fsqrt")
+   (set_attr "trap" "yes")])
 
 ;; Next are all the integer comparisons, and conditional moves and branches
 ;; and some of the related define_expand's and define_split's.
@@ -1278,31 +2248,13 @@
   "cmp%C1 %r2,%3,%0"
   [(set_attr "type" "icmp")])
 
-;; There are three important special-case that don't fit the above pattern
-;; but which we want to handle here.
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ne:DI (match_operand:DI 1 "register_operand" "r")
-	       (const_int 0)))]
-  ""
-  "cmpult $31,%1,%0"
-  [(set_attr "type" "icmp")])
-
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
-	(gt:DI (match_operand:DI 1 "register_operand" "r")
-	       (const_int 0)))]
+        (match_operator:DI 1 "alpha_swapped_comparison_operator"
+			   [(match_operand:DI 2 "reg_or_8bit_operand" "rI")
+			    (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
   ""
-  "cmplt $31,%1,%0"
-  [(set_attr "type" "icmp")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(ge:DI (match_operand:DI 1 "register_operand" "r")
-	       (const_int 0)))]
-  ""
-  "cmple $31,%1,%0"
+  "cmp%c1 %r3,%2,%0"
   [(set_attr "type" "icmp")])
 
 ;; This pattern exists so conditional moves of SImode values are handled.
@@ -1321,7 +2273,8 @@
    cmov%C2 %r3,%1,%0
    cmov%D2 %r3,%5,%0
    cmov%c2 %r4,%1,%0
-   cmov%d2 %r4,%5,%0")
+   cmov%d2 %r4,%5,%0"
+  [(set_attr "type" "icmov")])
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
@@ -1336,7 +2289,8 @@
    cmov%C2 %r3,%1,%0
    cmov%D2 %r3,%5,%0
    cmov%c2 %r4,%1,%0
-   cmov%d2 %r4,%5,%0")
+   cmov%d2 %r4,%5,%0"
+  [(set_attr "type" "icmov")])
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r,r")
@@ -1350,7 +2304,8 @@
   ""
   "@
    cmovlbc %r2,%1,%0
-   cmovlbs %r2,%3,%0")
+   cmovlbs %r2,%3,%0"
+  [(set_attr "type" "icmov")])
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r,r")
@@ -1364,7 +2319,8 @@
   ""
   "@
    cmovlbs %r2,%1,%0
-   cmovlbc %r2,%3,%0")
+   cmovlbc %r2,%3,%0"
+  [(set_attr "type" "icmov")])
 
 ;; This form is added since combine thinks that an IF_THEN_ELSE with both
 ;; arms constant is a single insn, so it won't try to form it if combine
@@ -1382,7 +2338,9 @@
 	 (match_dup 0)))
    (clobber (match_scratch:DI 4 "=&r"))]
   ""
-  "addq %0,%1,%4\;cmov%C2 %r3,%4,%0")
+  "addq %0,%1,%4\;cmov%C2 %r3,%4,%0"
+  [(set_attr "type" "icmov")
+   (set_attr "length" "8")])
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -1500,6 +2458,70 @@
 				       (match_dup 0) (match_dup 1)))]
   "")
 
+(define_insn "sminqi3"
+  [(set (match_operand:QI 0 "register_operand" "=r")
+	(smin:SI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
+		 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
+  "TARGET_MAX"
+  "minsb8 %r1,%2,%0"
+  [(set_attr "type" "mvi")])
+
+(define_insn "uminqi3"
+  [(set (match_operand:QI 0 "register_operand" "=r")
+	(umin:SI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
+		 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
+  "TARGET_MAX"
+  "minub8 %r1,%2,%0"
+  [(set_attr "type" "mvi")])
+
+(define_insn "smaxqi3"
+  [(set (match_operand:QI 0 "register_operand" "=r")
+	(smax:SI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
+		 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
+  "TARGET_MAX"
+  "maxsb8 %r1,%2,%0"
+  [(set_attr "type" "mvi")])
+
+(define_insn "umaxqi3"
+  [(set (match_operand:QI 0 "register_operand" "=r")
+	(umax:SI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
+		 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
+  "TARGET_MAX"
+  "maxub8 %r1,%2,%0"
+  [(set_attr "type" "mvi")])
+
+(define_insn "sminhi3"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(smin:SI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
+		 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
+  "TARGET_MAX"
+  "minsw4 %r1,%2,%0"
+  [(set_attr "type" "mvi")])
+
+(define_insn "uminhi3"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(umin:SI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
+		 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
+  "TARGET_MAX"
+  "minuw4 %r1,%2,%0"
+  [(set_attr "type" "mvi")])
+
+(define_insn "smaxhi3"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(smax:SI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
+		 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
+  "TARGET_MAX"
+  "maxsw4 %r1,%2,%0"
+  [(set_attr "type" "mvi")])
+
+(define_insn "umaxhi3"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(umax:SI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
+		 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
+  "TARGET_MAX"
+  "maxuw4 %r1,%2,%0"
+  [(set_attr "type" "shift")])
+
 (define_expand "smaxdi3"
   [(set (match_dup 3)
 	(le:DI (match_operand:DI 1 "reg_or_0_operand" "")
@@ -1528,7 +2550,8 @@
 	(smax:DI (match_operand:DI 1 "register_operand" "0")
 		 (const_int 0)))]
   ""
-  "cmovlt %0,0,%0")
+  "cmovlt %0,0,%0"
+  [(set_attr "type" "icmov")])
 
 (define_expand "smindi3"
   [(set (match_dup 3)
@@ -1558,7 +2581,8 @@
 	(smin:DI (match_operand:DI 1 "register_operand" "0")
 		 (const_int 0)))]
   ""
-  "cmovgt %0,0,%0")
+  "cmovgt %0,0,%0"
+  [(set_attr "type" "icmov")])
 
 (define_expand "umaxdi3"
   [(set (match_dup 3) 
@@ -1621,6 +2645,18 @@
 (define_insn ""
   [(set (pc)
 	(if_then_else
+	 (match_operator 1 "signed_comparison_operator"
+			 [(const_int 0)
+			  (match_operand:DI 2 "register_operand" "r")])
+	 (label_ref (match_operand 0 "" ""))
+	 (pc)))]
+  ""
+  "b%c1 %2,%0"
+  [(set_attr "type" "ibr")])
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else
 	 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
 			      (const_int 1)
 			      (const_int 0))
@@ -1674,13 +2710,35 @@
 ;; to DFmode.
 
 (define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=&f")
+	(match_operator:DF 1 "alpha_comparison_operator"
+			   [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
+			    (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "cmp%-%C1%' %R2,%R3,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(match_operator:DF 1 "alpha_comparison_operator"
 			   [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
 			    (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
-  "TARGET_FP"
-  "cmpt%C1 %R2,%R3,%0"
-  [(set_attr "type" "fpop")])
+  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
+  "cmp%-%C1%' %R2,%R3,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=&f")
+	(match_operator:DF 1 "alpha_comparison_operator"
+			   [(float_extend:DF
+			     (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
+			    (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "cmp%-%C1%' %R2,%R3,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -1688,9 +2746,21 @@
 			   [(float_extend:DF
 			     (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
 			    (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))]
-  "TARGET_FP"
-  "cmpt%C1 %R2,%R3,%0"
-  [(set_attr "type" "fpop")])
+  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
+  "cmp%-%C1%' %R2,%R3,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=&f")
+	(match_operator:DF 1 "alpha_comparison_operator"
+			   [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
+			    (float_extend:DF
+			     (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "cmp%-%C1%' %R2,%R3,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -1698,9 +2768,22 @@
 			   [(match_operand:DF 2 "reg_or_fp0_operand" "fG")
 			    (float_extend:DF
 			     (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
-  "TARGET_FP"
-  "cmpt%C1 %R2,%R3,%0"
-  [(set_attr "type" "fpop")])
+  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
+  "cmp%-%C1%' %R2,%R3,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=&f")
+	(match_operator:DF 1 "alpha_comparison_operator"
+			   [(float_extend:DF
+			     (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
+			    (float_extend:DF
+			     (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
+  "TARGET_FP && alpha_tp == ALPHA_TP_INSN"
+  "cmp%-%C1%' %R2,%R3,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -1709,9 +2792,10 @@
 			     (match_operand:SF 2 "reg_or_fp0_operand" "fG"))
 			    (float_extend:DF
 			     (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))]
-  "TARGET_FP"
-  "cmpt%C1 %R2,%R3,%0"
-  [(set_attr "type" "fpop")])
+  "TARGET_FP && alpha_tp != ALPHA_TP_INSN"
+  "cmp%-%C1%' %R2,%R3,%0"
+  [(set_attr "type" "fadd")
+   (set_attr "trap" "yes")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f,f")
@@ -1725,7 +2809,7 @@
   "@
    fcmov%C3 %R4,%R1,%0
    fcmov%D3 %R4,%R5,%0"
-  [(set_attr "type" "fpop")])
+  [(set_attr "type" "fcmov")])
 
 (define_insn ""
   [(set (match_operand:SF 0 "register_operand" "=f,f")
@@ -1739,21 +2823,21 @@
   "@
    fcmov%C3 %R4,%R1,%0
    fcmov%D3 %R4,%R5,%0"
-  [(set_attr "type" "fpop")])
+  [(set_attr "type" "fcmov")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f,f")
 	(if_then_else:DF 
 	 (match_operator 3 "signed_comparison_operator"
-			 [(match_operand:DF 1 "reg_or_fp0_operand" "fG,fG")
+			 [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG")
 			  (match_operand:DF 2 "fp0_operand" "G,G")])
-	 (float_extend:DF (match_operand:SF 4 "reg_or_fp0_operand" "fG,0"))
+	 (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0"))
 	 (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))]
   "TARGET_FP"
   "@
    fcmov%C3 %R4,%R1,%0
    fcmov%D3 %R4,%R5,%0"
-  [(set_attr "type" "fpop")])
+  [(set_attr "type" "fcmov")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f,f")
@@ -1768,7 +2852,7 @@
   "@
    fcmov%C3 %R4,%R1,%0
    fcmov%D3 %R4,%R5,%0"
-  [(set_attr "type" "fpop")])
+  [(set_attr "type" "fcmov")])
 
 (define_insn ""
   [(set (match_operand:SF 0 "register_operand" "=f,f")
@@ -1783,7 +2867,7 @@
   "@
    fcmov%C3 %R4,%R1,%0
    fcmov%D3 %R4,%R5,%0"
-  [(set_attr "type" "fpop")])
+  [(set_attr "type" "fcmov")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f,f")
@@ -1798,7 +2882,7 @@
   "@
    fcmov%C3 %R4,%R1,%0
    fcmov%D3 %R4,%R5,%0"
-  [(set_attr "type" "fpop")])
+  [(set_attr "type" "fcmov")])
 
 (define_expand "maxdf3"
   [(set (match_dup 3)
@@ -1905,198 +2989,84 @@
 }")
 
 (define_expand "beq"
-  [(set (match_dup 1) (match_dup 2))
-   (set (pc)
-	(if_then_else (match_dup 3)
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  enum machine_mode mode;
-  enum rtx_code compare_code, branch_code;
-
-  if (alpha_compare_fp_p)
-    mode = DFmode, compare_code = EQ, branch_code = NE;
-  else
-    {
-      mode = DImode, compare_code = MINUS, branch_code = EQ;
-      if (GET_CODE (alpha_compare_op1) == CONST_INT)
-	{
-	  compare_code = PLUS;
-	  alpha_compare_op1 = GEN_INT (- INTVAL (alpha_compare_op1));
-	}
-    }
-
-  operands[1] = gen_reg_rtx (mode);
-  operands[2] = gen_rtx (compare_code, mode,
-			 alpha_compare_op0, alpha_compare_op1);
-  operands[3] = gen_rtx (branch_code, VOIDmode,
-			 operands[1], CONST0_RTX (mode));
-}")
+  "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
 
 (define_expand "bne"
-  [(set (match_dup 1) (match_dup 2))
-   (set (pc)
-	(if_then_else (match_dup 3)
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  enum machine_mode mode;
-  enum rtx_code compare_code, branch_code;
-
-  if (alpha_compare_fp_p)
-    mode = DFmode, compare_code = EQ, branch_code = EQ;
-  else
-    {
-      mode = DImode, compare_code = MINUS, branch_code = NE;
-      if (GET_CODE (alpha_compare_op1) == CONST_INT)
-	{
-	  compare_code = PLUS;
-	  alpha_compare_op1 = GEN_INT (- INTVAL (alpha_compare_op1));
-	}
-    }
-
-  operands[1] = gen_reg_rtx (mode);
-  operands[2] = gen_rtx (compare_code, mode,
-			 alpha_compare_op0, alpha_compare_op1);
-  operands[3] = gen_rtx (branch_code, VOIDmode,
-			 operands[1], CONST0_RTX (mode));
-}")
+  "{ operands[1] = alpha_emit_conditional_branch (NE); }")
 
 (define_expand "blt"
-  [(set (match_dup 1) (match_dup 2))
-   (set (pc)
-	(if_then_else (match_dup 3)
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  enum machine_mode mode = alpha_compare_fp_p ? DFmode : DImode;
-  operands[1] = gen_reg_rtx (mode);
-  operands[2] = gen_rtx (LT, mode, alpha_compare_op0, alpha_compare_op1);
-  operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (mode));
-}")
+  "{ operands[1] = alpha_emit_conditional_branch (LT); }")
 
 (define_expand "ble"
-  [(set (match_dup 1) (match_dup 2))
-   (set (pc)
-	(if_then_else (match_dup 3)
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  enum machine_mode mode = alpha_compare_fp_p ? DFmode : DImode;
-  operands[1] = gen_reg_rtx (mode);
-  operands[2] = gen_rtx (LE, mode, alpha_compare_op0, alpha_compare_op1);
-  operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (mode));
-}")
+  "{ operands[1] = alpha_emit_conditional_branch (LE); }")
 
 (define_expand "bgt"
-  [(set (match_dup 1) (match_dup 2))
-   (set (pc)
-	(if_then_else (match_dup 3)
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  if (alpha_compare_fp_p)
-    {
-      operands[1] = gen_reg_rtx (DFmode);
-      operands[2] = gen_rtx (LT, DFmode, alpha_compare_op1, alpha_compare_op0);
-      operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (DFmode));
-    }
-  else
-    {
-      operands[1] = gen_reg_rtx (DImode);
-      operands[2] = gen_rtx (LE, DImode, alpha_compare_op0, alpha_compare_op1);
-      operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
-    }
-}")
+  "{ operands[1] = alpha_emit_conditional_branch (GT); }")
 
 (define_expand "bge"
-  [(set (match_dup 1) (match_dup 2))
-   (set (pc)
-	(if_then_else (match_dup 3)
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  if (alpha_compare_fp_p)
-    {
-      operands[1] = gen_reg_rtx (DFmode);
-      operands[2] = gen_rtx (LE, DFmode, alpha_compare_op1, alpha_compare_op0);
-      operands[3] = gen_rtx (NE, VOIDmode, operands[1], CONST0_RTX (DFmode));
-    }
-  else
-    {
-      operands[1] = gen_reg_rtx (DImode);
-      operands[2] = gen_rtx (LT, DImode, alpha_compare_op0, alpha_compare_op1);
-      operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
-    }
-}")
+  "{ operands[1] = alpha_emit_conditional_branch (GE); }")
 
 (define_expand "bltu"
-  [(set (match_dup 1) (match_dup 2))
-   (set (pc)
-	(if_then_else (match_dup 3)
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (DImode);
-  operands[2] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1);
-  operands[3] = gen_rtx (NE, VOIDmode, operands[1], const0_rtx);
-}")
+  "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
 
 (define_expand "bleu"
-  [(set (match_dup 1) (match_dup 2))
-   (set (pc)
-	(if_then_else (match_dup 3)
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (DImode);
-  operands[2] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1);
-  operands[3] = gen_rtx (NE, VOIDmode, operands[1], const0_rtx);
-}")
+  "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
 
 (define_expand "bgtu"
-  [(set (match_dup 1) (match_dup 2))
-   (set (pc)
-	(if_then_else (match_dup 3)
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (DImode);
-  operands[2] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1);
-  operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
-}")
+  "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
 
 (define_expand "bgeu"
-  [(set (match_dup 1) (match_dup 2))
-   (set (pc)
-	(if_then_else (match_dup 3)
+  [(set (pc)
+	(if_then_else (match_dup 1)
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
-{
-  operands[1] = gen_reg_rtx (DImode);
-  operands[2] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1);
-  operands[3] = gen_rtx (EQ, VOIDmode, operands[1], const0_rtx);
-}")
+  "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
 
 (define_expand "seq"
   [(set (match_operand:DI 0 "register_operand" "")
@@ -2107,7 +3077,7 @@
   if (alpha_compare_fp_p)
     FAIL;
 
-  operands[1] = gen_rtx (EQ, DImode, alpha_compare_op0, alpha_compare_op1);
+  operands[1] = gen_rtx_EQ (DImode, alpha_compare_op0, alpha_compare_op1);
 }")
 
 (define_expand "sne"
@@ -2120,7 +3090,7 @@
   if (alpha_compare_fp_p)
     FAIL;
 
-  operands[1] = gen_rtx (EQ, DImode, alpha_compare_op0, alpha_compare_op1);
+  operands[1] = gen_rtx_EQ (DImode, alpha_compare_op0, alpha_compare_op1);
 }")
 
 (define_expand "slt"
@@ -2132,7 +3102,7 @@
   if (alpha_compare_fp_p)
     FAIL;
 
-  operands[1] = gen_rtx (LT, DImode, alpha_compare_op0, alpha_compare_op1);
+  operands[1] = gen_rtx_LT (DImode, alpha_compare_op0, alpha_compare_op1);
 }")
 
 (define_expand "sle"
@@ -2144,7 +3114,7 @@
   if (alpha_compare_fp_p)
     FAIL;
 
-  operands[1] = gen_rtx (LE, DImode, alpha_compare_op0, alpha_compare_op1);
+  operands[1] = gen_rtx_LE (DImode, alpha_compare_op0, alpha_compare_op1);
 }")
 
 (define_expand "sgt"
@@ -2156,8 +3126,8 @@
   if (alpha_compare_fp_p)
     FAIL;
 
-  operands[1] = gen_rtx (LT, DImode, force_reg (DImode, alpha_compare_op1),
-			 alpha_compare_op0);
+  operands[1] = gen_rtx_LT (DImode, force_reg (DImode, alpha_compare_op1),
+			    alpha_compare_op0);
 }")
 
 (define_expand "sge"
@@ -2169,8 +3139,8 @@
   if (alpha_compare_fp_p)
     FAIL;
 
-  operands[1] = gen_rtx (LE, DImode, force_reg (DImode, alpha_compare_op1),
-			 alpha_compare_op0);
+  operands[1] = gen_rtx_LE (DImode, force_reg (DImode, alpha_compare_op1),
+			    alpha_compare_op0);
 }")
 
 (define_expand "sltu"
@@ -2182,7 +3152,7 @@
   if (alpha_compare_fp_p)
     FAIL;
 
-  operands[1] = gen_rtx (LTU, DImode, alpha_compare_op0, alpha_compare_op1);
+  operands[1] = gen_rtx_LTU (DImode, alpha_compare_op0, alpha_compare_op1);
 }")
 
 (define_expand "sleu"
@@ -2194,7 +3164,7 @@
   if (alpha_compare_fp_p)
     FAIL;
 
-  operands[1] = gen_rtx (LEU, DImode, alpha_compare_op0, alpha_compare_op1);
+  operands[1] = gen_rtx_LEU (DImode, alpha_compare_op0, alpha_compare_op1);
 }")
 
 (define_expand "sgtu"
@@ -2206,8 +3176,8 @@
   if (alpha_compare_fp_p)
     FAIL;
 
-  operands[1] = gen_rtx (LTU, DImode, force_reg (DImode, alpha_compare_op1),
-			 alpha_compare_op0);
+  operands[1] = gen_rtx_LTU (DImode, force_reg (DImode, alpha_compare_op1),
+			     alpha_compare_op0);
 }")
 
 (define_expand "sgeu"
@@ -2219,184 +3189,58 @@
   if (alpha_compare_fp_p)
     FAIL;
 
-  operands[1] = gen_rtx (LEU, DImode, force_reg (DImode, alpha_compare_op1),
-			 alpha_compare_op0);
+  operands[1] = gen_rtx_LEU (DImode, force_reg (DImode, alpha_compare_op1),
+			     alpha_compare_op0);
 }")
 
 ;; These are the main define_expand's used to make conditional moves.
 
 (define_expand "movsicc"
-  [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
-   (set (match_operand:SI 0 "register_operand" "")
-	(if_then_else:DI (match_dup 5)
+  [(set (match_operand:SI 0 "register_operand" "")
+	(if_then_else:DI (match_operand 1 "comparison_operator" "")
 			 (match_operand:SI 2 "reg_or_8bit_operand" "")
 			 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
   ""
   "
 {
-  rtx op0,op1;
-  enum rtx_code code = GET_CODE (operands[1]), code2 = NE;
-
-  if (alpha_compare_fp_p)
+  if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
     FAIL;
-  switch (code)
-    {
-    case EQ: case LE: case LT:
-      op0 = alpha_compare_op0;
-      op1 = alpha_compare_op1;
-      break;
-    case NE:
-      code = code2 = EQ;
-      op0 = alpha_compare_op0;
-      op1 = alpha_compare_op1;
-      break;
-    case GE:
-      code = LE;
-      op0 = force_reg (DImode, alpha_compare_op1);
-      op1 = alpha_compare_op0;
-      break;
-    case GT:
-      code = LT;
-      op0 = force_reg (DImode, alpha_compare_op1);
-      op1 = alpha_compare_op0;
-      break;
-    default:
-      FAIL;
-    }
-  operands[1] = gen_rtx (code, DImode, op0, op1);
-  operands[4] = gen_reg_rtx (DImode);
-  operands[5] = gen_rtx (code2, VOIDmode, operands[4], CONST0_RTX (DImode));
 }")
 
 (define_expand "movdicc"
-  [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
-   (set (match_operand:DI 0 "register_operand" "")
-	(if_then_else:DI (match_dup 5)
+  [(set (match_operand:DI 0 "register_operand" "")
+	(if_then_else:DI (match_operand 1 "comparison_operator" "")
 			 (match_operand:DI 2 "reg_or_8bit_operand" "")
 			 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
   ""
   "
 {
-  rtx op0,op1;
-  enum rtx_code code = GET_CODE (operands[1]), code2 = NE;
-
-  if (alpha_compare_fp_p)
+  if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
     FAIL;
-  switch (code)
-    {
-    case EQ: case LE: case LT:
-      op0 = alpha_compare_op0;
-      op1 = alpha_compare_op1;
-      break;
-    case NE:
-      code = code2 = EQ;
-      op0 = alpha_compare_op0;
-      op1 = alpha_compare_op1;
-      break;
-    case GE:
-      code = LE;
-      op0 = force_reg (DImode, alpha_compare_op1);
-      op1 = alpha_compare_op0;
-      break;
-    case GT:
-      code = LT;
-      op0 = force_reg (DImode, alpha_compare_op1);
-      op1 = alpha_compare_op0;
-      break;
-    default:
-      FAIL;
-    }
-  operands[1] = gen_rtx (code, DImode, op0, op1);
-  operands[4] = gen_reg_rtx (DImode);
-  operands[5] = gen_rtx (code2, VOIDmode, operands[4], CONST0_RTX (DImode));
 }")
 
 (define_expand "movsfcc"
-  [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
-   (set (match_operand:SF 0 "register_operand" "")
-	(if_then_else:SF (match_dup 5)
-			 (match_operand:SF 2 "reg_or_fp0_operand" "")
-			 (match_operand:SF 3 "reg_or_fp0_operand" "")))]
+  [(set (match_operand:SF 0 "register_operand" "")
+	(if_then_else:SF (match_operand 1 "comparison_operator" "")
+			 (match_operand:SF 2 "reg_or_8bit_operand" "")
+			 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
   ""
   "
 {
-  rtx op0,op1;
-  enum rtx_code code = GET_CODE (operands[1]), code2 = NE;
-
-  if (!alpha_compare_fp_p)
+  if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
     FAIL;
-  switch (code)
-    {
-    case EQ: case LE: case LT:
-      op0 = alpha_compare_op0;
-      op1 = alpha_compare_op1;
-      break;
-    case NE:
-      /* There isn't a cmptne insn.  */
-      code = code2 = EQ;
-      op0 = alpha_compare_op0;
-      op1 = alpha_compare_op1;
-      break;
-    case GE:
-      code = LE;
-      op0 = force_reg (DFmode, alpha_compare_op1);
-      op1 = alpha_compare_op0;
-      break;
-    case GT:
-      code = LT;
-      op0 = force_reg (DFmode, alpha_compare_op1);
-      op1 = alpha_compare_op0;
-      break;
-    default:
-      FAIL;
-    }
-  operands[1] = gen_rtx (code, DFmode, op0, op1);
-  operands[4] = gen_reg_rtx (DFmode);
-  operands[5] = gen_rtx (code2, VOIDmode, operands[4], CONST0_RTX (DFmode));
 }")
 
 (define_expand "movdfcc"
-  [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
-   (set (match_operand:DF 0 "register_operand" "")
-	(if_then_else:DF (match_dup 5)
-			 (match_operand:DF 2 "reg_or_fp0_operand" "")
-			 (match_operand:DF 3 "reg_or_fp0_operand" "")))]
+  [(set (match_operand:DF 0 "register_operand" "")
+	(if_then_else:DF (match_operand 1 "comparison_operator" "")
+			 (match_operand:DF 2 "reg_or_8bit_operand" "")
+			 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
   ""
   "
 {
-  rtx op0,op1;
-  enum rtx_code code = GET_CODE (operands[1]), code2 = NE;
-
-  if (!alpha_compare_fp_p)
+  if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
     FAIL;
-  switch (code)
-    {
-    case EQ: case LE: case LT:
-      op0 = alpha_compare_op0;
-      op1 = alpha_compare_op1;
-      break;
-    case NE:
-      /* There isn't a cmptne insn.  */
-      code = code2 = EQ;
-      op0 = alpha_compare_op0;
-      op1 = alpha_compare_op1;
-      break;
-    case GE:
-      code = LE;
-      op0 = force_reg (DFmode, alpha_compare_op1);
-      op1 = alpha_compare_op0;
-      break;
-    case GT:
-      code = LT;
-      op0 = force_reg (DFmode, alpha_compare_op1);
-      op1 = alpha_compare_op0;
-      break;
-    default:
-      FAIL;
-    }
-  operands[1] = gen_rtx (code, DFmode, op0, op1);
-  operands[4] = gen_reg_rtx (DFmode);
-  operands[5] = gen_rtx (code2, VOIDmode, operands[4], CONST0_RTX (DFmode));
 }")
 
 ;; These define_split definitions are used in cases when comparisons have
@@ -2451,25 +3295,25 @@
 	  && extended_count (operands[3], DImode, unsignedp) >= 1))
     {
       if (GET_CODE (operands[3]) == CONST_INT)
-	operands[7] = gen_rtx (PLUS, DImode, operands[2],
-			       GEN_INT (- INTVAL (operands[3])));
+	operands[7] = gen_rtx_PLUS (DImode, operands[2],
+				    GEN_INT (- INTVAL (operands[3])));
       else
-	operands[7] = gen_rtx (MINUS, DImode, operands[2], operands[3]);
+	operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
 
-      operands[8] = gen_rtx (code, VOIDmode, operands[6], const0_rtx);
+      operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
     }
 
   else if (code == EQ || code == LE || code == LT
 	   || code == LEU || code == LTU)
     {
-      operands[7] = gen_rtx (code, DImode, operands[2], operands[3]);
-      operands[8] = gen_rtx (NE, VOIDmode, operands[6], const0_rtx);
+      operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
+      operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
     }
   else
     {
-      operands[7] = gen_rtx (reverse_condition (code), DImode, operands[2],
-			     operands[3]);
-      operands[8] = gen_rtx (EQ, VOIDmode, operands[6], const0_rtx);
+      operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
+				    operands[2], operands[3]);
+      operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
     }
 }")
 
@@ -2498,14 +3342,14 @@
     FAIL;
  
   if (GET_CODE (operands[3]) == CONST_INT)
-    tem = gen_rtx (PLUS, SImode, operands[2],
-		   GEN_INT (- INTVAL (operands[3])));
+    tem = gen_rtx_PLUS (SImode, operands[2],
+			GEN_INT (- INTVAL (operands[3])));
   else
-    tem = gen_rtx (MINUS, SImode, operands[2], operands[3]);
+    tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
 
-  operands[7] = gen_rtx (SIGN_EXTEND, DImode, tem);
-  operands[8] = gen_rtx (GET_CODE (operands[1]), VOIDmode, operands[6],
-			 const0_rtx);
+  operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
+  operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
+				operands[6], const0_rtx);
 }")
 
 (define_split
@@ -2529,25 +3373,25 @@
 	  && extended_count (operands[3], DImode, unsignedp) >= 1))
     {
       if (GET_CODE (operands[3]) == CONST_INT)
-	operands[5] = gen_rtx (PLUS, DImode, operands[2],
-			       GEN_INT (- INTVAL (operands[3])));
+	operands[5] = gen_rtx_PLUS (DImode, operands[2],
+				    GEN_INT (- INTVAL (operands[3])));
       else
-	operands[5] = gen_rtx (MINUS, DImode, operands[2], operands[3]);
+	operands[5] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
 
-      operands[6] = gen_rtx (code, VOIDmode, operands[4], const0_rtx);
+      operands[6] = gen_rtx_fmt_ee (code, VOIDmode, operands[4], const0_rtx);
     }
 
   else if (code == EQ || code == LE || code == LT
 	   || code == LEU || code == LTU)
     {
-      operands[5] = gen_rtx (code, DImode, operands[2], operands[3]);
-      operands[6] = gen_rtx (NE, VOIDmode, operands[4], const0_rtx);
+      operands[5] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
+      operands[6] = gen_rtx_NE (VOIDmode, operands[4], const0_rtx);
     }
   else
     {
-      operands[5] = gen_rtx (reverse_condition (code), DImode, operands[2],
-			     operands[3]);
-      operands[6] = gen_rtx (EQ, VOIDmode, operands[4], const0_rtx);
+      operands[5] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
+				    operands[2], operands[3]);
+      operands[6] = gen_rtx_EQ (VOIDmode, operands[4], const0_rtx);
     }
 }")
 
@@ -2568,14 +3412,14 @@
 { rtx tem;
 
   if (GET_CODE (operands[3]) == CONST_INT)
-    tem = gen_rtx (PLUS, SImode, operands[2],
-		   GEN_INT (- INTVAL (operands[3])));
+    tem = gen_rtx_PLUS (SImode, operands[2],
+			GEN_INT (- INTVAL (operands[3])));
   else
-    tem = gen_rtx (MINUS, SImode, operands[2], operands[3]);
+    tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
   
-  operands[5] = gen_rtx (SIGN_EXTEND, DImode, tem);
-  operands[6] = gen_rtx (GET_CODE (operands[1]), VOIDmode,
-			 operands[4], const0_rtx);
+  operands[5] = gen_rtx_SIGN_EXTEND (DImode, tem);
+  operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
+				operands[4], const0_rtx);
 }")
 
 ;; We can convert such things as "a > 0xffff" to "t = a & ~ 0xffff; t != 0".
@@ -2597,10 +3441,10 @@
   "
 {
   operands[5] = GEN_INT (~ INTVAL (operands[3]));
-  operands[6] = gen_rtx (((GET_CODE (operands[1]) == GTU
-			   || GET_CODE (operands[1]) == GT)
-			  ? NE : EQ),
-			 DImode, operands[4], const0_rtx);
+  operands[6] = gen_rtx_fmt_ee (((GET_CODE (operands[1]) == GTU
+				  || GET_CODE (operands[1]) == GT)
+				 ? NE : EQ),
+				DImode, operands[4], const0_rtx);
 }")
 
 ;; Here are the CALL and unconditional branch insns.  Calls on NT and OSF
@@ -2608,11 +3452,15 @@
 
 (define_expand "call"
   [(use (match_operand:DI 0 "" ""))
-   (use (match_operand 1 "" ""))]
+   (use (match_operand 1 "" ""))
+   (use (match_operand 2 "" ""))
+   (use (match_operand 3 "" ""))]
   ""
   "
-{ if (WINDOWS_NT)
+{ if (TARGET_WINDOWS_NT)
     emit_call_insn (gen_call_nt (operands[0], operands[1]));
+  else if (TARGET_OPEN_VMS)
+    emit_call_insn (gen_call_vms (operands[0], operands[2]));
   else
     emit_call_insn (gen_call_osf (operands[0], operands[1]));
 
@@ -2634,39 +3482,95 @@
   if (GET_CODE (operands[0]) != SYMBOL_REF
       && ! (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 27))
     {
-      rtx tem = gen_rtx (REG, DImode, 27);
+      rtx tem = gen_rtx_REG (DImode, 27);
       emit_move_insn (tem, operands[0]);
       operands[0] = tem;
     }
 }")
 
 (define_expand "call_nt"
-  [(parallel [(call (mem:DI (match_operand:DI 0 "" ""))
+  [(parallel [(call (mem:DI (match_operand 0 "" ""))
 		    (match_operand 1 "" ""))
 	      (clobber (reg:DI 26))])]
   ""
   "
 { if (GET_CODE (operands[0]) != MEM)
     abort ();
+
   operands[0] = XEXP (operands[0], 0);
+  if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
+    operands[0] = force_reg (DImode, operands[0]);
+}")
 
-  if (GET_CODE (operands[1]) != SYMBOL_REF
-      && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
+;;
+;; call openvms/alpha
+;; op 0: symbol ref for called function
+;; op 1: next_arg_reg (argument information value for R25)
+;;
+(define_expand "call_vms"
+  [(parallel [(call (mem:DI (match_operand 0 "" ""))
+		    (match_operand 1 "" ""))
+	      (use (match_dup 2))
+	      (use (reg:DI 25))
+	      (use (reg:DI 26))
+	      (clobber (reg:DI 27))])]
+  ""
+  "
+{ if (GET_CODE (operands[0]) != MEM)
+    abort ();
+
+  operands[0] = XEXP (operands[0], 0);
+
+  /* Always load AI with argument information, then handle symbolic and
+     indirect call differently.  Load RA and set operands[2] to PV in
+     both cases.  */
+
+  emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
+  if (GET_CODE (operands[0]) == SYMBOL_REF)
     {
-      rtx tem = gen_rtx (REG, DImode, 27);
-      emit_move_insn (tem, operands[1]);
-      operands[1] = tem;
+      extern char *savealloc ();
+      char *linksym, *symbol = XSTR (operands[0], 0);
+      rtx linkage;
+
+      if (*symbol == '*')
+	symbol++;
+      linksym = savealloc (strlen (symbol) + 6);
+
+      alpha_need_linkage (symbol, 0);
+
+      linksym[0] = '$';
+      strcpy (linksym+1, symbol);
+      strcat (linksym, \"..lk\");
+      linkage = gen_rtx_SYMBOL_REF (Pmode, linksym);
+
+      emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
+
+      operands[2]
+	= validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
     }
+  else
+    {
+      emit_move_insn (gen_rtx_REG (Pmode, 26),
+		      gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
+
+      operands[2] = operands[0];
+    }
+
 }")
 
 (define_expand "call_value"
   [(use (match_operand 0 "" ""))
    (use (match_operand:DI 1 "" ""))
-   (use (match_operand 2 "" ""))]
+   (use (match_operand 2 "" ""))
+   (use (match_operand 3 "" ""))
+   (use (match_operand 4 "" ""))]
   ""
   "
-{ if (WINDOWS_NT)
+{ if (TARGET_WINDOWS_NT)
     emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
+  else if (TARGET_OPEN_VMS)
+    emit_call_insn (gen_call_value_vms (operands[0], operands[1],
+					operands[3]));
   else
     emit_call_insn (gen_call_value_osf (operands[0], operands[1],
 					operands[2]));
@@ -2689,7 +3593,7 @@
   if (GET_CODE (operands[1]) != SYMBOL_REF
       && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
     {
-      rtx tem = gen_rtx (REG, DImode, 27);
+      rtx tem = gen_rtx_REG (DImode, 27);
       emit_move_insn (tem, operands[1]);
       operands[1] = tem;
     }
@@ -2697,7 +3601,7 @@
 
 (define_expand "call_value_nt"
   [(parallel [(set (match_operand 0 "" "")
-		   (call (mem:DI (match_operand:DI 1 "" ""))
+		   (call (mem:DI (match_operand 1 "" ""))
 			 (match_operand 2 "" "")))
 	      (clobber (reg:DI 26))])]
   ""
@@ -2706,12 +3610,57 @@
     abort ();
 
   operands[1] = XEXP (operands[1], 0);
-  if (GET_CODE (operands[1]) != SYMBOL_REF
-      && ! (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 27))
+  if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
+    operands[1] = force_reg (DImode, operands[1]);
+}")
+
+(define_expand "call_value_vms"
+  [(parallel [(set (match_operand 0 "" "")
+		   (call (mem:DI (match_operand:DI 1 "" ""))
+			 (match_operand 2 "" "")))
+	      (use (match_dup 3))
+	      (use (reg:DI 25))
+	      (use (reg:DI 26))
+	      (clobber (reg:DI 27))])]
+  ""
+  "
+{ if (GET_CODE (operands[1]) != MEM)
+    abort ();
+
+  operands[1] = XEXP (operands[1], 0);
+
+  /* Always load AI with argument information, then handle symbolic and
+     indirect call differently.  Load RA and set operands[3] to PV in
+     both cases.  */
+
+  emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
+  if (GET_CODE (operands[1]) == SYMBOL_REF)
     {
-      rtx tem = gen_rtx (REG, DImode, 27);
-      emit_move_insn (tem, operands[1]);
-      operands[1] = tem;
+      extern char *savealloc ();
+      char *linksym, *symbol = XSTR (operands[1], 0);
+      rtx linkage;
+
+      if (*symbol == '*')
+	symbol++;
+      linksym = savealloc (strlen (symbol) + 6);
+
+      alpha_need_linkage (symbol, 0);
+      linksym[0] = '$';
+      strcpy (linksym+1, symbol);
+      strcat (linksym, \"..lk\");
+      linkage = gen_rtx_SYMBOL_REF (Pmode, linksym);
+
+      emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage));
+
+      operands[3]
+	= validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8)));
+    }
+  else
+    {
+      emit_move_insn (gen_rtx_REG (Pmode, 26),
+		      gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
+
+      operands[3] = operands[1];
     }
 }")
 
@@ -2720,46 +3669,81 @@
 	 (match_operand 1 "" ""))
    (clobber (reg:DI 27))
    (clobber (reg:DI 26))]
-  "! WINDOWS_NT"
+  "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
   "@
    jsr $26,($27),0\;ldgp $29,0($26)
-   bsr $26,%0..ng
+   bsr $26,$%0..ng
    jsr $26,%0\;ldgp $29,0($26)"
-  [(set_attr "type" "jsr,jsr,ibr")])
+  [(set_attr "type" "jsr")
+   (set_attr "length" "12,*,12")])
       
 (define_insn ""
-  [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
+  [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,i"))
 	 (match_operand 1 "" ""))
    (clobber (reg:DI 26))]
-  "WINDOWS_NT"
+  "TARGET_WINDOWS_NT"
   "@
    jsr $26,(%0)
-   bsr $26,%0"
-  [(set_attr "type" "jsr")])
+   bsr $26,%0
+   jsr $26,%0"
+  [(set_attr "type" "jsr")
+   (set_attr "length" "*,*,12")])
       
 (define_insn ""
+  [(call (mem:DI (match_operand:DI 0 "call_operand" "r,i"))
+	 (match_operand 1 "" ""))
+   (use (match_operand:DI 2 "general_operand" "r,m"))
+   (use (reg:DI 25))
+   (use (reg:DI 26))
+   (clobber (reg:DI 27))]
+  "TARGET_OPEN_VMS"
+  "@
+   bis %2,%2,$27\;jsr $26,0\;ldq $27,0($29)
+   ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"
+  [(set_attr "type" "jsr")
+   (set_attr "length" "12,16")])
+
+(define_insn ""
   [(set (match_operand 0 "register_operand" "=rf,rf,rf")
 	(call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
 	      (match_operand 2 "" "")))
    (clobber (reg:DI 27))
    (clobber (reg:DI 26))]
-  "! WINDOWS_NT"
+  "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS"
   "@
    jsr $26,($27),0\;ldgp $29,0($26)
-   bsr $26,%1..ng
+   bsr $26,$%1..ng
    jsr $26,%1\;ldgp $29,0($26)"
-  [(set_attr "type" "jsr,jsr,ibr")])
+  [(set_attr "type" "jsr")
+   (set_attr "length" "12,*,12")])
 
 (define_insn ""
-  [(set (match_operand 0 "register_operand" "=rf,rf")
-	(call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
+  [(set (match_operand 0 "register_operand" "=rf,rf,rf")
+	(call (mem:DI (match_operand:DI 1 "call_operand" "r,R,i"))
 	      (match_operand 2 "" "")))
    (clobber (reg:DI 26))]
-  "WINDOWS_NT"
+  "TARGET_WINDOWS_NT"
   "@
    jsr $26,(%1)
-   bsr $26,%1"
-  [(set_attr "type" "jsr")])
+   bsr $26,%1
+   jsr $26,%1"
+  [(set_attr "type" "jsr")
+   (set_attr "length" "*,*,12")])
+
+(define_insn ""
+  [(set (match_operand 0 "register_operand" "")
+	(call (mem:DI (match_operand:DI 1 "call_operand" "r,i"))
+	      (match_operand 2 "" "")))
+   (use (match_operand:DI 3 "general_operand" "r,m"))
+   (use (reg:DI 25))
+   (use (reg:DI 26))
+   (clobber (reg:DI 27))]
+  "TARGET_OPEN_VMS"
+  "@
+   bis %3,%3,$27\;jsr $26,0\;ldq $27,0($29)
+   ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"
+  [(set_attr "type" "jsr")
+   (set_attr "length" "12,16")])
 
 ;; Call subroutine returning any type.
 
@@ -2796,7 +3780,8 @@
 (define_insn "blockage"
   [(unspec_volatile [(const_int 0)] 1)]
   ""
-  "")
+  ""
+  [(set_attr "length" "0")])
 
 (define_insn "jump"
   [(set (pc)
@@ -2811,6 +3796,15 @@
   "ret $31,($26),1"
   [(set_attr "type" "ibr")])
 
+;; Use a different pattern for functions which have non-trivial
+;; epilogues so as not to confuse jump and reorg.
+(define_insn "return_internal"
+  [(use (reg:DI 26))
+   (return)]
+  ""
+  "ret $31,($26),1"
+  [(set_attr "type" "ibr")])
+
 (define_insn "indirect_jump"
   [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
   ""
@@ -2820,8 +3814,8 @@
 (define_insn "nop"
   [(const_int 0)]
   ""
-  "bis $31,$31,$31"
-  [(set_attr "type" "iaddlog")])
+  "nop"
+  [(set_attr "type" "ilog")])
 
 (define_expand "tablejump"
   [(use (match_operand:SI 0 "register_operand" ""))
@@ -2829,8 +3823,10 @@
   ""
   "
 {
-  if (WINDOWS_NT)
+  if (TARGET_WINDOWS_NT)
     emit_jump_insn (gen_tablejump_nt (operands[0], operands[1]));
+  else if (TARGET_OPEN_VMS)
+    emit_jump_insn (gen_tablejump_vms (operands[0], operands[1]));
   else
     emit_jump_insn (gen_tablejump_osf (operands[0], operands[1]));
 
@@ -2858,12 +3854,27 @@
   "
 { operands[3] = gen_reg_rtx (DImode); }")
 
+;;
+;; tablejump, openVMS way
+;; op 0: offset
+;; op 1: label preceding jump-table
+;;
+(define_expand "tablejump_vms"
+  [(set (match_dup 2)
+      (match_operand:DI 0 "register_operand" ""))
+        (set (pc)
+	(plus:DI (match_dup 2)
+		(label_ref:DI (match_operand 1 "" ""))))]
+  ""
+  "
+{ operands[2] = gen_reg_rtx (DImode); }")
+
 (define_insn ""
   [(set (pc)
 	(plus:DI (match_operand:DI 0 "register_operand" "r")
 		 (label_ref:DI (match_operand 1 "" ""))))
    (clobber (match_scratch:DI 2 "=r"))]
-  "! WINDOWS_NT && next_active_insn (insn) != 0
+  "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && next_active_insn (insn) != 0
    && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
    && PREV_INSN (next_active_insn (insn)) == operands[1]"
   "*
@@ -2900,13 +3911,14 @@
   else
     return \"addq %0,$29,%2\;jmp $31,(%2),0\";
 }"
-  [(set_attr "type" "ibr")])
+  [(set_attr "type" "ibr")
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (pc)
 	(match_operand:DI 0 "register_operand" "r"))
    (use (label_ref (match_operand 1 "" "")))]
-  "WINDOWS_NT && next_active_insn (insn) != 0
+  "TARGET_WINDOWS_NT && next_active_insn (insn) != 0
    && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
    && PREV_INSN (next_active_insn (insn)) == operands[1]"
   "*
@@ -2945,12 +3957,30 @@
 }"
   [(set_attr "type" "ibr")])
 
+;;
+;; op 0 is table offset
+;; op 1 is table label
+;;
+
+(define_insn ""
+  [(set (pc)
+	(plus:DI (match_operand 0 "register_operand" "r")
+		(label_ref (match_operand 1 "" ""))))]
+  "TARGET_OPEN_VMS"
+  "jmp $31,(%0),0"
+  [(set_attr "type" "ibr")])
+
 ;; Cache flush.  Used by INITIALIZE_TRAMPOLINE.  0x86 is PAL_imb, but we don't
 ;; want to have to include pal.h in our .s file.
-(define_insn ""
+;;
+;; Technically the type for call_pal is jsr, but we use that for determining
+;; if we need a GP.  Use ibr instead since it has the same EV5 scheduling
+;; characteristics.
+(define_insn "imb"
   [(unspec_volatile [(const_int 0)] 0)]
   ""
-  "call_pal 0x86")
+  "call_pal 0x86"
+  [(set_attr "type" "ibr")])
 
 ;; Finally, we have the basic data motion insns.  The byte and word insns
 ;; are done via define_expand.  Start with the floating-point insns, since
@@ -2959,32 +3989,70 @@
 (define_insn ""
   [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m")
 	(match_operand:SF 1 "input_operand" "rG,m,rG,f,G,m,fG"))]
-  "register_operand (operands[0], SFmode)
-   || reg_or_fp0_operand (operands[1], SFmode)"
+  "! TARGET_CIX
+   && (register_operand (operands[0], SFmode)
+       || reg_or_fp0_operand (operands[1], SFmode))"
+  "@
+   bis %r1,%r1,%0
+   ldl %0,%1
+   stl %r1,%0
+   cpys %1,%1,%0
+   cpys $f31,$f31,%0
+   ld%, %0,%1
+   st%, %R1,%0"
+  [(set_attr "type" "ilog,ild,ist,fcpys,fcpys,fld,fst")])
+
+(define_insn ""
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m,f,*r")
+	(match_operand:SF 1 "input_operand" "rG,m,rG,f,G,m,fG,r,*f"))]
+  "TARGET_CIX
+   && (register_operand (operands[0], SFmode)
+       || reg_or_fp0_operand (operands[1], SFmode))"
   "@
    bis %r1,%r1,%0
    ldl %0,%1
    stl %r1,%0
    cpys %1,%1,%0
    cpys $f31,$f31,%0
-   lds %0,%1
-   sts %R1,%0"
-  [(set_attr "type" "iaddlog,ld,st,fpop,fpop,ld,st")])
+   ld%, %0,%1
+   st%, %R1,%0
+   itofs %1,%0
+   ftois %1,%0"
+  [(set_attr "type" "ilog,ild,ist,fcpys,fcpys,fld,fst,itof,ftoi")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m")
 	(match_operand:DF 1 "input_operand" "rG,m,rG,f,G,m,fG"))]
-  "register_operand (operands[0], DFmode)
-   || reg_or_fp0_operand (operands[1], DFmode)"
+  "! TARGET_CIX
+   && (register_operand (operands[0], DFmode)
+       || reg_or_fp0_operand (operands[1], DFmode))"
   "@
    bis %r1,%r1,%0
    ldq %0,%1
    stq %r1,%0
    cpys %1,%1,%0
    cpys $f31,$f31,%0
-   ldt %0,%1
-   stt %R1,%0"
-  [(set_attr "type" "iaddlog,ld,st,fpop,fpop,ld,st")])
+   ld%- %0,%1
+   st%- %R1,%0"
+  [(set_attr "type" "ilog,ild,ist,fcpys,fcpys,fld,fst")])
+
+(define_insn ""
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,f,f,f,m,f,*r")
+	(match_operand:DF 1 "input_operand" "rG,m,rG,f,G,m,fG,r,*f"))]
+  "TARGET_CIX
+   && (register_operand (operands[0], DFmode)
+       || reg_or_fp0_operand (operands[1], DFmode))"
+  "@
+   bis %r1,%r1,%0
+   ldq %0,%1
+   stq %r1,%0
+   cpys %1,%1,%0
+   cpys $f31,$f31,%0
+   ld%- %0,%1
+   st%- %R1,%0
+   itoft %1,%0
+   ftoit %1,%0"
+  [(set_attr "type" "ilog,ild,ist,fcpys,fcpys,fld,fst,itof,ftoi")])
 
 (define_expand "movsf"
   [(set (match_operand:SF 0 "nonimmediate_operand" "")
@@ -3011,8 +4079,9 @@
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,f,f,f,m")
 	(match_operand:SI 1 "input_operand" "r,J,I,K,L,m,rJ,f,J,m,fG"))]
-  "! WINDOWS_NT && (register_operand (operands[0], SImode)
-		    || reg_or_0_operand (operands[1], SImode))"
+  "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && ! TARGET_CIX
+   && (register_operand (operands[0], SImode)
+       || reg_or_0_operand (operands[1], SImode))"
   "@
    bis %1,%1,%0
    bis $31,$31,%0
@@ -3023,15 +4092,38 @@
    stl %r1,%0
    cpys %1,%1,%0
    cpys $f31,$f31,%0
-   lds %0,%1
-   sts %R1,%0"
-  [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,iaddlog,ld,st,fpop,fpop,ld,st")])
+   ld%, %0,%1
+   st%, %R1,%0"
+  [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ild,ist,fcpys,fcpys,fld,fst")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,f,f,f,m,r,*f")
+	(match_operand:SI 1 "input_operand" "r,J,I,K,L,m,rJ,f,J,m,fG,f,*r"))]
+  "! TARGET_WINDOWS_NT && ! TARGET_OPEN_VMS && TARGET_CIX
+   && (register_operand (operands[0], SImode)
+       || reg_or_0_operand (operands[1], SImode))"
+  "@
+   bis %1,%1,%0
+   bis $31,$31,%0
+   bis $31,%1,%0
+   lda %0,%1
+   ldah %0,%h1
+   ldl %0,%1
+   stl %r1,%0
+   cpys %1,%1,%0
+   cpys $f31,$f31,%0
+   ld%, %0,%1
+   st%, %R1,%0
+   ftois %1,%0
+   itofs %1,%0"
+  [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ild,ist,fcpys,fcpys,fld,fst,ftoi,itof")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,f,f,f,m")
 	(match_operand:SI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,m,fG"))]
-  "WINDOWS_NT && (register_operand (operands[0], SImode)
-		  || reg_or_0_operand (operands[1], SImode))"
+  "(TARGET_WINDOWS_NT || TARGET_OPEN_VMS)
+    && (register_operand (operands[0], SImode)
+        || reg_or_0_operand (operands[1], SImode))"
   "@
    bis %1,%1,%0
    bis $31,$31,%0
@@ -3043,15 +4135,16 @@
    stl %r1,%0
    cpys %1,%1,%0
    cpys $f31,$f31,%0
-   lds %0,%1
-   sts %R1,%0"
-  [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,iaddlog,ldsym,ld,st,fpop,fpop,ld,st")])
+   ld%, %0,%1
+   st%, %R1,%0"
+  [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ldsym,ild,ist,fcpys,fcpys,fld,fst")])
 
 (define_insn ""
   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,f,f")
 	(match_operand:HI 1 "input_operand" "r,J,I,n,f,J"))]
-  "register_operand (operands[0], HImode)
-   || register_operand (operands[1], HImode)"
+  "! TARGET_BWX
+   && (register_operand (operands[0], HImode)
+       || register_operand (operands[1], HImode))"
   "@
    bis %1,%1,%0
    bis $31,$31,%0
@@ -3059,21 +4152,56 @@
    lda %0,%L1
    cpys %1,%1,%0
    cpys $f31,$f31,%0"
-  [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,fpop,fpop")])
+  [(set_attr "type" "ilog,ilog,ilog,iadd,fcpys,fcpys")])
+
+(define_insn ""
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,r,r,m,f,f")
+	(match_operand:HI 1 "input_operand" "r,J,I,n,m,rJ,f,J"))]
+  "TARGET_BWX
+   && (register_operand (operands[0], HImode)
+       || reg_or_0_operand (operands[1], HImode))"
+  "@
+   bis %1,%1,%0
+   bis $31,$31,%0
+   bis $31,%1,%0
+   lda %0,%L1
+   ldwu %0,%1
+   stw %r1,%0
+   cpys %1,%1,%0
+   cpys $f31,$f31,%0"
+  [(set_attr "type" "ilog,ilog,ilog,iadd,ild,ist,fcpys,fcpys")])
 
 (define_insn ""
   [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,r,f,f")
 	(match_operand:QI 1 "input_operand" "r,J,I,n,f,J"))]
-  "register_operand (operands[0], QImode)
-   || register_operand (operands[1], QImode)"
+  "! TARGET_BWX
+   && (register_operand (operands[0], QImode)
+       || register_operand (operands[1], QImode))"
+  "@
+   bis %1,%1,%0
+   bis $31,$31,%0
+   bis $31,%1,%0
+   lda %0,%L1
+   cpys %1,%1,%0
+   cpys $f31,$f31,%0"
+  [(set_attr "type" "ilog,ilog,ilog,iadd,fcpys,fcpys")])
+
+(define_insn ""
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,r,r,m,f,f")
+	(match_operand:QI 1 "input_operand" "r,J,I,n,m,rJ,f,J"))]
+  "TARGET_BWX
+   && (register_operand (operands[0], QImode)
+       || reg_or_0_operand (operands[1], QImode))"
   "@
    bis %1,%1,%0
    bis $31,$31,%0
    bis $31,%1,%0
    lda %0,%L1
+   ldbu %0,%1
+   stb %r1,%0
    cpys %1,%1,%0
    cpys $f31,$f31,%0"
-  [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,fpop,fpop")])
+  [(set_attr "type" "ilog,ilog,ilog,iadd,ild,ist,fcpys,fcpys")])
 
 ;; We do two major things here: handle mem->mem and construct long
 ;; constants.
@@ -3121,8 +4249,9 @@
 (define_insn ""
   [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,r,r,m,f,f,f,Q")
 	(match_operand:DI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,Q,fG"))]
-  "register_operand (operands[0], DImode)
-   || reg_or_0_operand (operands[1], DImode)"
+  "! TARGET_CIX
+   && (register_operand (operands[0], DImode)
+       || reg_or_0_operand (operands[1], DImode))"
   "@
    bis %1,%1,%0
    bis $31,$31,%0
@@ -3136,7 +4265,30 @@
    cpys $f31,$f31,%0
    ldt %0,%1
    stt %R1,%0"
-  [(set_attr "type" "iaddlog,iaddlog,iaddlog,iaddlog,iaddlog,ldsym,ld,st,fpop,fpop,ld,st")])
+  [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ldsym,ild,ist,fcpys,fcpys,fld,fst")])
+
+(define_insn ""
+  [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,r,r,m,f,f,f,Q,r,*f")
+	(match_operand:DI 1 "input_operand" "r,J,I,K,L,s,m,rJ,f,J,Q,fG,f,*r"))]
+  "TARGET_CIX
+   && (register_operand (operands[0], DImode)
+       || reg_or_0_operand (operands[1], DImode))"
+  "@
+   bis %1,%1,%0
+   bis $31,$31,%0
+   bis $31,%1,%0
+   lda %0,%1
+   ldah %0,%h1
+   lda %0,%1
+   ldq%A1 %0,%1
+   stq%A0 %r1,%0
+   cpys %1,%1,%0
+   cpys $f31,$f31,%0
+   ldt %0,%1
+   stt %R1,%0
+   ftoit %1,%0
+   itoft %1,%0"
+  [(set_attr "type" "ilog,ilog,ilog,iadd,iadd,ldsym,ild,ist,fcpys,fcpys,fld,fst,ftoi,itof")])
 
 ;; We do three major things here: handle mem->mem, put 64-bit constants in
 ;; memory, and construct long 32-bit constants.
@@ -3166,15 +4318,39 @@
     }
   else if (CONSTANT_P (operands[1]))
     {
-      operands[1] = force_const_mem (DImode, operands[1]);
-      if (reload_in_progress)
+      if (TARGET_BUILD_CONSTANTS)
 	{
-	  emit_move_insn (operands[0], XEXP (operands[1], 0));
-	  operands[1] = copy_rtx (operands[1]);
-	  XEXP (operands[1], 0) = operands[0];
+#if HOST_BITS_PER_WIDE_INT == 64
+	  HOST_WIDE_INT i;
+
+	  if (GET_CODE (operands[1]) == CONST_INT)
+	    i = INTVAL (operands[1]);
+	  else if (GET_CODE (operands[1]) == CONST_DOUBLE)
+	    i = CONST_DOUBLE_LOW (operands[1]);
+	  else
+	    abort();
+	  
+          tem = alpha_emit_set_long_const (operands[0], i);
+          if (rtx_equal_p (tem, operands[0]))
+	    DONE;
+          else
+	    operands[1] = tem;
+#else
+          abort();
+#endif
 	}
       else
-	operands[1] = validize_mem (operands[1]);
+	{
+	  operands[1] = force_const_mem (DImode, operands[1]);
+	  if (reload_in_progress)
+	    {
+	      emit_move_insn (operands[0], XEXP (operands[1], 0));
+	      operands[1] = copy_rtx (operands[1]);
+	      XEXP (operands[1], 0) = operands[0];
+	    }
+	  else
+	    operands[1] = validize_mem (operands[1]);
+	}
     }
   else
     abort ();
@@ -3230,16 +4406,10 @@
   ""
   "")
   
-;; Similar for unaligned loads.  For QImode, we use the sequence from the
-;; Alpha Architecture manual.  However, for HImode, we do not.  HImode pointers
-;; are normally aligned to the byte boundary, so an HImode object cannot
-;; cross a longword boundary.  We could use a sequence similar to that for
-;; QImode, but that would fail if the pointer, was, in fact, not aligned.
-;; Instead, we clear bit 1 in the address and do an ldl.  If the low-order
-;; bit was not aligned, this will trap and the trap handler will do what is
-;; needed.
+;; Similar for unaligned loads, where we use the sequence from the
+;; Alpha Architecture manual.
 ;;
-;; Here operand 1 is the address.  Operands 2 and 3 are temporaries, where
+;; Operand 1 is the address.  Operands 2 and 3 are temporaries, where
 ;; operand 3 can overlap the input and output registers.
 
 (define_expand "unaligned_loadqi"
@@ -3255,26 +4425,19 @@
   ""
   "")
 
-;; For this, the address must already be in a register.  We also need two
-;; DImode temporaries, neither of which may overlap the input (and hence the
-;; output, since they might be the same register), but both of which may
-;; be the same.
-
 (define_expand "unaligned_loadhi"
   [(set (match_operand:DI 2 "register_operand" "")
-	(and:DI (match_operand:DI 1 "register_operand" "")
-		(const_int -7)))
+	(mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
+			(const_int -8))))
    (set (match_operand:DI 3 "register_operand" "")
-	(mem:DI (match_dup 2)))
-   (set (match_operand:DI 4 "register_operand" "")
-	(and:DI (match_dup 1) (const_int -2)))
-   (set (subreg:DI (match_operand:HI 0 "register_operand" "") 0)
-	(zero_extract:DI (match_dup 3)
+	(match_dup 1))
+   (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
+	(zero_extract:DI (match_dup 2)
 			 (const_int 16)
-			 (ashift:DI (match_dup 4) (const_int 3))))]
+			 (ashift:DI (match_dup 3) (const_int 3))))]
   ""
   "")
-       
+
 ;; Storing an aligned byte or word requires two temporaries.  Operand 0 is the
 ;; aligned SImode MEM.  Operand 1 is the register containing the 
 ;; byte or word to store.  Operand 2 is the number of bits within the word that
@@ -3297,8 +4460,8 @@
 			    << INTVAL (operands[2])));
 }")
 
-;; For the unaligned byte case, we use code similar to that in the
-;; Architecture book, but reordered to lower the number of registers
+;; For the unaligned byte and halfword cases, we use code similar to that
+;; in the ;; Architecture book, but reordered to lower the number of registers
 ;; required.  Operand 0 is the address.  Operand 1 is the data to store.
 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
 ;; be the same temporary, if desired.  If the address is in a register,
@@ -3323,42 +4486,22 @@
   ""
   "")
 
-;; This is the code for storing into an unaligned short.  It uses the same
-;; trick as loading from an unaligned short.  It needs lots of temporaries.
-;; However, during reload, we only have two registers available.  So we
-;; repeat code so that only two temporaries are available.  During RTL
-;; generation, we can use different pseudos for each temporary and CSE
-;; will remove the redundancies.  During reload, we have to settle with
-;; what we get.  Luckily, unaligned accesses of this kind produced during
-;; reload are quite rare.
-;;
-;; Operand 0 is the address of the memory location.  Operand 1 contains the
-;; data to store.  The rest of the operands are all temporaries, with
-;; various overlap possibilities during reload.  See reload_outhi for
-;; details of this use.
-
 (define_expand "unaligned_storehi"
-  [(set (match_operand:DI 2 "register_operand" "")
-	(match_operand:DI 0 "address_operand" ""))
-   (set (match_operand:DI 3 "register_operand" "")
-	(and:DI (match_dup 2) (const_int -7)))
-   (set (match_operand:DI 4 "register_operand" "")
-	(mem:DI (match_dup 3)))
-   (set (match_operand:DI 10 "register_operand" "")
-	(and:DI (match_dup 2) (const_int -2)))
-   (set (match_operand:DI 5 "register_operand" "")
+  [(set (match_operand:DI 3 "register_operand" "")
+	(mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
+			(const_int -8))))
+   (set (match_operand:DI 2 "register_operand" "")
+	(match_dup 0))
+   (set (match_dup 3)
 	(and:DI (not:DI (ashift:DI (const_int 65535)
-				   (ashift:DI (match_dup 10) (const_int 3))))
-		(match_dup 4)))
-   (set (match_operand:DI 6 "register_operand" "")
+				   (ashift:DI (match_dup 2) (const_int 3))))
+		(match_dup 3)))
+   (set (match_operand:DI 4 "register_operand" "")
 	(ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
-		   (ashift:DI (match_dup 10) (const_int 3))))
-   (set (match_operand:DI 7 "register_operand" "")
-	(ior:DI (match_dup 5) (match_dup 6)))
-   (set (match_operand:DI 8 "register_operand" "") (match_dup 0))
-   (set (match_operand:DI 9 "register_operand" "")
-	(and:DI (match_dup 8) (const_int -7)))
-   (set (mem:DI (match_dup 9)) (match_dup 7))]
+		   (ashift:DI (match_dup 2) (const_int 3))))
+   (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
+   (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
+	(match_dup 4))]
   ""
   "")
 
@@ -3371,7 +4514,25 @@
 	(match_operand:QI 1 "general_operand" ""))]
   ""
   "
-{ extern rtx get_unaligned_address ();
+{
+  if (TARGET_BWX)
+    {
+      if (GET_CODE (operands[0]) == MEM
+	  && ! reg_or_0_operand (operands[1], QImode))
+	operands[1] = force_reg (QImode, operands[1]);
+
+      if (GET_CODE (operands[1]) == CONST_INT
+	       && ! input_operand (operands[1], QImode))
+	{
+	  operands[1] = alpha_emit_set_const (operands[0], QImode,
+					      INTVAL (operands[1]), 3);
+
+	  if (rtx_equal_p (operands[0], operands[1]))
+	    DONE;
+	}
+
+      goto def;
+    }
 
   /* If the output is not a register, the input must be.  */
   if (GET_CODE (operands[0]) == MEM)
@@ -3394,7 +4555,7 @@
 	{
 	  rtx aligned_mem, bitnum;
 	  rtx scratch = (reload_in_progress
-			 ? gen_rtx (REG, SImode, REGNO (operands[0]))
+			 ? gen_rtx_REG (SImode, REGNO (operands[0]))
 			 : gen_reg_rtx (SImode));
 
 	  get_aligned_mem (operands[1], &aligned_mem, &bitnum);
@@ -3410,9 +4571,10 @@
 
 	  rtx temp1 = gen_reg_rtx (DImode);
 	  rtx temp2 = gen_reg_rtx (DImode);
-	  rtx seq = gen_unaligned_loadqi (operands[0],
-					  get_unaligned_address (operands[1]),
-					  temp1, temp2);
+	  rtx seq
+	    = gen_unaligned_loadqi (operands[0],
+				    get_unaligned_address (operands[1], 0),
+				    temp1, temp2);
 
 	  alpha_set_memflags (seq, operands[1]);
 	  emit_insn (seq);
@@ -3446,7 +4608,8 @@
 	  rtx temp1 = gen_reg_rtx (DImode);
 	  rtx temp2 = gen_reg_rtx (DImode);
 	  rtx temp3 = gen_reg_rtx (DImode);
-	  rtx seq = gen_unaligned_storeqi (get_unaligned_address (operands[0]),
+	  rtx seq
+	    = gen_unaligned_storeqi (get_unaligned_address (operands[0], 0),
 					   operands[1], temp1, temp2, temp3);
 
 	  alpha_set_memflags (seq, operands[0]);
@@ -3454,6 +4617,7 @@
 	}
       DONE;
     }
+ def:;
 }")
 
 (define_expand "movhi"
@@ -3461,7 +4625,25 @@
 	(match_operand:HI 1 "general_operand" ""))]
   ""
   "
-{ extern rtx get_unaligned_address ();
+{
+  if (TARGET_BWX)
+    {
+      if (GET_CODE (operands[0]) == MEM
+	  && ! reg_or_0_operand (operands[1], HImode))
+	operands[1] = force_reg (HImode, operands[1]);
+
+      if (GET_CODE (operands[1]) == CONST_INT
+	       && ! input_operand (operands[1], HImode))
+	{
+	  operands[1] = alpha_emit_set_const (operands[0], HImode,
+					      INTVAL (operands[1]), 3);
+
+	  if (rtx_equal_p (operands[0], operands[1]))
+	    DONE;
+	}
+
+      goto def;
+    }
 
   /* If the output is not a register, the input must be.  */
   if (GET_CODE (operands[0]) == MEM)
@@ -3484,7 +4666,7 @@
 	{
 	  rtx aligned_mem, bitnum;
 	  rtx scratch = (reload_in_progress
-			 ? gen_rtx (REG, SImode, REGNO (operands[0]))
+			 ? gen_rtx_REG (SImode, REGNO (operands[0]))
 			 : gen_reg_rtx (SImode));
 
 	  get_aligned_mem (operands[1], &aligned_mem, &bitnum);
@@ -3494,16 +4676,16 @@
 	}
       else
 	{
-	  rtx addr
-	    = force_reg (DImode,
-			 force_operand (get_unaligned_address (operands[1]),
-					NULL_RTX));
-	  rtx scratch1 = gen_reg_rtx (DImode);
-	  rtx scratch2 = gen_reg_rtx (DImode);
-	  rtx scratch3 = gen_reg_rtx (DImode);
+	  /* Don't pass these as parameters since that makes the generated
+	     code depend on parameter evaluation order which will cause
+	     bootstrap failures.  */
 
-	  rtx seq = gen_unaligned_loadhi (operands[0], addr, scratch1,
-					  scratch2, scratch3);
+	  rtx temp1 = gen_reg_rtx (DImode);
+	  rtx temp2 = gen_reg_rtx (DImode);
+	  rtx seq
+	    = gen_unaligned_loadhi (operands[0],
+				    get_unaligned_address (operands[1], 0),
+				    temp1, temp2);
 
 	  alpha_set_memflags (seq, operands[1]);
 	  emit_insn (seq);
@@ -3537,17 +4719,9 @@
 	  rtx temp1 = gen_reg_rtx (DImode);
 	  rtx temp2 = gen_reg_rtx (DImode);
 	  rtx temp3 = gen_reg_rtx (DImode);
-	  rtx temp4 = gen_reg_rtx (DImode);
-	  rtx temp5 = gen_reg_rtx (DImode);
-	  rtx temp6 = gen_reg_rtx (DImode);
-	  rtx temp7 = gen_reg_rtx (DImode);
-	  rtx temp8 = gen_reg_rtx (DImode);
-	  rtx temp9 = gen_reg_rtx (DImode);
-
-	  rtx seq = gen_unaligned_storehi (get_unaligned_address (operands[0]),
-					   operands[1], temp1, temp2,temp3,
-					   temp4, temp5, temp6,temp7,
-					   temp8, temp9);
+	  rtx seq
+	    = gen_unaligned_storehi (get_unaligned_address (operands[0], 0),
+				     operands[1], temp1, temp2, temp3);
 
 	  alpha_set_memflags (seq, operands[0]);
 	  emit_insn (seq);
@@ -3555,6 +4729,7 @@
 
       DONE;
     }
+ def:;
 }")
 
 ;; Here are the versions for reload.  Note that in the unaligned cases
@@ -3565,18 +4740,20 @@
   [(parallel [(match_operand:QI 0 "register_operand" "=r")
 	      (match_operand:QI 1 "unaligned_memory_operand" "m")
 	      (match_operand:TI 2 "register_operand" "=&r")])]
-  ""
+  "! TARGET_BWX"
   "
-{ extern rtx get_unaligned_address ();
-  rtx addr = get_unaligned_address (operands[1]);
+{
+  rtx addr = get_unaligned_address (operands[1], 0);
+
   /* It is possible that one of the registers we got for operands[2]
      might coincide with that of operands[0] (which is why we made
      it TImode).  Pick the other one to use as our scratch.  */
-  rtx scratch = gen_rtx (REG, DImode,
-			 REGNO (operands[0]) == REGNO (operands[2]) 
-			 ? REGNO (operands[2]) + 1 : REGNO (operands[2]));
+  rtx scratch = gen_rtx_REG (DImode,
+			     REGNO (operands[0]) == REGNO (operands[2]) 
+			     ? REGNO (operands[2]) + 1 : REGNO (operands[2]));
+
   rtx seq = gen_unaligned_loadqi (operands[0], addr, scratch,
-				  gen_rtx (REG, DImode, REGNO (operands[0])));
+				  gen_rtx_REG (DImode, REGNO (operands[0])));
 
   alpha_set_memflags (seq, operands[1]);
   emit_insn (seq);
@@ -3587,21 +4764,21 @@
   [(parallel [(match_operand:HI 0 "register_operand" "=r")
 	      (match_operand:HI 1 "unaligned_memory_operand" "m")
 	      (match_operand:TI 2 "register_operand" "=&r")])]
-  ""
+  "! TARGET_BWX"
   "
-{ extern rtx get_unaligned_address ();
-  rtx addr = get_unaligned_address (operands[1]);
-  rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2]));
-  rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1);
-  rtx seq;
+{
+  rtx addr = get_unaligned_address (operands[1], 0);
+
+  /* It is possible that one of the registers we got for operands[2]
+     might coincide with that of operands[0] (which is why we made
+     it TImode).  Pick the other one to use as our scratch.  */
+  rtx scratch = gen_rtx_REG (DImode,
+			     REGNO (operands[0]) == REGNO (operands[2]) 
+			     ? REGNO (operands[2]) + 1 : REGNO (operands[2]));
+
+  rtx seq = gen_unaligned_loadhi (operands[0], addr, scratch,
+				  gen_rtx_REG (DImode, REGNO (operands[0])));
 
-  if (GET_CODE (addr) != REG)
-    {
-      emit_insn (gen_rtx (SET, VOIDmode, scratch2, addr));
-      addr = scratch2;
-    }
-      
-  seq = gen_unaligned_loadhi (operands[0], addr, scratch1, scratch1, scratch2);
   alpha_set_memflags (seq, operands[1]);
   emit_insn (seq);
   DONE;
@@ -3611,10 +4788,9 @@
   [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
 	      (match_operand:QI 1 "register_operand" "r")
 	      (match_operand:TI 2 "register_operand" "=&r")])]
-  ""
+  "! TARGET_BWX"
   "
-{ extern rtx get_unaligned_address ();
-
+{
   if (aligned_memory_operand (operands[0], QImode))
     {
       rtx aligned_mem, bitnum;
@@ -3622,15 +4798,15 @@
       get_aligned_mem (operands[0], &aligned_mem, &bitnum);
 
       emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
-				    gen_rtx (REG, SImode, REGNO (operands[2])),
-				    gen_rtx (REG, SImode,
-					     REGNO (operands[2]) + 1)));
+				    gen_rtx_REG (SImode, REGNO (operands[2])),
+				    gen_rtx_REG (SImode,
+						 REGNO (operands[2]) + 1)));
     }
   else
     {
-      rtx addr = get_unaligned_address (operands[0]);
-      rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2]));
-      rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1);
+      rtx addr = get_unaligned_address (operands[0], 0);
+      rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
+      rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
       rtx scratch3 = scratch1;
       rtx seq;
 
@@ -3650,10 +4826,9 @@
   [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
 	      (match_operand:HI 1 "register_operand" "r")
 	      (match_operand:TI 2 "register_operand" "=&r")])]
-  ""
+  "! TARGET_BWX"
   "
-{ extern rtx get_unaligned_address ();
-
+{
   if (aligned_memory_operand (operands[0], HImode))
     {
       rtx aligned_mem, bitnum;
@@ -3661,22 +4836,23 @@
       get_aligned_mem (operands[0], &aligned_mem, &bitnum);
 
       emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
-				    gen_rtx (REG, SImode, REGNO (operands[2])),
-				    gen_rtx (REG, SImode,
-					     REGNO (operands[2]) + 1)));
+				    gen_rtx_REG (SImode, REGNO (operands[2])),
+				    gen_rtx_REG (SImode,
+						 REGNO (operands[2]) + 1)));
     }
   else
     {
-      rtx addr = get_unaligned_address (operands[0]);
-      rtx scratch1 = gen_rtx (REG, DImode, REGNO (operands[2]));
-      rtx scratch2 = gen_rtx (REG, DImode, REGNO (operands[2]) + 1);
-      rtx scratch_a = GET_CODE (addr) == REG ? addr : scratch1;
+      rtx addr = get_unaligned_address (operands[0], 0);
+      rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
+      rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
+      rtx scratch3 = scratch1;
       rtx seq;
 
-      seq = gen_unaligned_storehi (addr, operands[1], scratch_a,
-				   scratch2, scratch2, scratch2,
-				   scratch1, scratch2, scratch_a,
-				   scratch1, scratch_a);
+      if (GET_CODE (addr) == REG)
+	scratch1 = addr;
+
+      seq = gen_unaligned_storehi (addr, operands[1], scratch1,
+				   scratch2, scratch3);
       alpha_set_memflags (seq, operands[0]);
       emit_insn (seq);
     }
@@ -3684,14 +4860,133 @@
   DONE;
 }")
 
+;; Bit field extract patterns which use ext[wlq][lh]
+
+(define_expand "extv"
+  [(set (match_operand:DI 0 "register_operand" "")
+	(sign_extract:DI (match_operand:QI 1 "memory_operand" "")
+			 (match_operand:DI 2 "immediate_operand" "")
+			 (match_operand:DI 3 "immediate_operand" "")))]
+  ""
+  "
+{
+  /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries.  */
+  if (INTVAL (operands[3]) % 8 != 0
+      || (INTVAL (operands[2]) != 16
+	  && INTVAL (operands[2]) != 32
+	  && INTVAL (operands[2]) != 64))
+    FAIL;
+
+  /* From mips.md: extract_bit_field doesn't verify that our source
+     matches the predicate, so we force it to be a MEM here.  */
+  if (GET_CODE (operands[1]) != MEM)
+    FAIL;
+
+  alpha_expand_unaligned_load (operands[0], operands[1],
+			       INTVAL (operands[2]) / 8,
+			       INTVAL (operands[3]) / 8, 1);
+  DONE;
+}")
+
+(define_expand "extzv"
+  [(set (match_operand:DI 0 "register_operand" "")
+	(zero_extract:DI (match_operand:DI 1 "general_operand" "")
+			 (match_operand:DI 2 "immediate_operand" "")
+			 (match_operand:DI 3 "immediate_operand" "")))]
+  ""
+  "
+{
+  /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries.  */
+  if (INTVAL (operands[3]) % 8 != 0
+      || (INTVAL (operands[2]) != 8
+	  && INTVAL (operands[2]) != 16
+	  && INTVAL (operands[2]) != 32
+	  && INTVAL (operands[2]) != 64))
+    FAIL;
+
+  if (GET_CODE (operands[1]) == MEM)
+    {
+      /* Fail 8 bit fields, falling back on a simple byte load.  */
+      if (INTVAL (operands[2]) == 8)
+	FAIL;
+
+      alpha_expand_unaligned_load (operands[0], operands[1],
+			           INTVAL (operands[2]) / 8,
+			           INTVAL (operands[3]) / 8, 0);
+      DONE;
+    }
+}")
+
+(define_expand "insv"
+  [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
+			 (match_operand:DI 1 "immediate_operand" "")
+			 (match_operand:DI 2 "immediate_operand" ""))
+	(match_operand:DI 3 "register_operand" ""))]
+  ""
+  "
+{
+  /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries.  */
+  if (INTVAL (operands[2]) % 8 != 0
+      || (INTVAL (operands[1]) != 16
+	  && INTVAL (operands[1]) != 32
+	  && INTVAL (operands[1]) != 64))
+    FAIL;
+
+  /* From mips.md: store_bit_field doesn't verify that our source
+     matches the predicate, so we force it to be a MEM here.  */
+  if (GET_CODE (operands[0]) != MEM)
+    FAIL;
+
+  alpha_expand_unaligned_store (operands[0], operands[3],
+			        INTVAL (operands[1]) / 8,
+			        INTVAL (operands[2]) / 8);
+  DONE;
+}")
+
+
+
+;; Block move/clear, see alpha.c for more details.
+;; Argument 0 is the destination
+;; Argument 1 is the source
+;; Argument 2 is the length
+;; Argument 3 is the alignment
+
+(define_expand "movstrqi"
+  [(parallel [(set (match_operand:BLK 0 "general_operand" "")
+		   (match_operand:BLK 1 "general_operand" ""))
+	      (use (match_operand:DI 2 "immediate_operand" ""))
+	      (use (match_operand:DI 3 "immediate_operand" ""))])]
+  ""
+  "
+{
+  if (alpha_expand_block_move (operands))
+    DONE;
+  else
+    FAIL;
+}")
+
+(define_expand "clrstrqi"
+  [(parallel [(set (match_operand:BLK 0 "general_operand" "")
+		   (const_int 0))
+	      (use (match_operand:DI 1 "immediate_operand" ""))
+	      (use (match_operand:DI 2 "immediate_operand" ""))])]
+  ""
+  "
+{
+  if (alpha_expand_block_clear (operands))
+    DONE;
+  else
+    FAIL;
+}")
+
 ;; Subroutine of stack space allocation.  Perform a stack probe.
 (define_expand "probe_stack"
   [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
   ""
   "
 {
-  operands[1] = gen_rtx (MEM, DImode, plus_constant (stack_pointer_rtx,
-						     INTVAL (operands[0])));
+  operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
+						    INTVAL (operands[0])));
   MEM_VOLATILE_P (operands[1]) = 1;
 
   operands[0] = const0_rtx;
@@ -3706,14 +5001,16 @@
 (define_expand "allocate_stack"
   [(set (reg:DI 30)
 	(plus:DI (reg:DI 30)
-		 (match_operand:DI 0 "reg_or_cint_operand" "")))]
+		 (match_operand:DI 1 "reg_or_cint_operand" "")))
+   (set (match_operand:DI 0 "register_operand" "=r")
+	(match_dup 2))]
   ""
   "
 {
-  if (GET_CODE (operands[0]) == CONST_INT
-	   && INTVAL (operands[0]) < 32768)
+  if (GET_CODE (operands[1]) == CONST_INT
+      && INTVAL (operands[1]) < 32768)
     {
-      if (INTVAL (operands[0]) >= 4096)
+      if (INTVAL (operands[1]) >= 4096)
 	{
 	  /* We do this the same way as in the prologue and generate explicit
 	     probes.  Then we update the stack by the constant.  */
@@ -3721,14 +5018,15 @@
 	  int probed = 4096;
 
 	  emit_insn (gen_probe_stack (GEN_INT (- probed)));
-	  while (probed + 8192 < INTVAL (operands[0]))
+	  while (probed + 8192 < INTVAL (operands[1]))
 	    emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
 
-	  if (probed + 4096 < INTVAL (operands[0]))
-	    emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[0]))));
+	  if (probed + 4096 < INTVAL (operands[1]))
+	    emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
 	}
 
-      operands[0] = GEN_INT (- INTVAL (operands[0]));
+      operands[1] = GEN_INT (- INTVAL (operands[1]));
+      operands[2] = virtual_stack_dynamic_rtx;
     }
   else
     {
@@ -3739,10 +5037,10 @@
       rtx memref;
 
       emit_insn (gen_subdi3 (want, stack_pointer_rtx,
-			     force_reg (Pmode, operands[0])));
+			     force_reg (Pmode, operands[1])));
       emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
 
-      if (GET_CODE (operands[0]) != CONST_INT)
+      if (GET_CODE (operands[1]) != CONST_INT)
 	{
 	  out_label = gen_label_rtx ();
 	  emit_insn (gen_cmpdi (want, tmp));
@@ -3750,13 +5048,16 @@
 	}
 
       emit_label (loop_label);
-      memref = gen_rtx (MEM, DImode, tmp);
+      memref = gen_rtx_MEM (DImode, tmp);
       MEM_VOLATILE_P (memref) = 1;
       emit_move_insn (memref, const0_rtx);
       emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
       emit_insn (gen_cmpdi (tmp, want));
       emit_jump_insn (gen_bgtu (loop_label));
-      memref = gen_rtx (MEM, DImode, want);
+      if (obey_regdecls)
+	gen_rtx_USE (VOIDmode, tmp);
+
+      memref = gen_rtx_MEM (DImode, want);
       MEM_VOLATILE_P (memref) = 1;
       emit_move_insn (memref, const0_rtx);
 
@@ -3764,7 +5065,160 @@
 	emit_label (out_label);
 
       emit_move_insn (stack_pointer_rtx, want);
-
+      emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
       DONE;
     }
 }")
+
+;; This is used by alpha_expand_prolog to do the same thing as above,
+;; except we cannot at that time generate new basic blocks, so we hide
+;; the loop in this one insn.
+
+(define_insn "prologue_stack_probe_loop"
+  [(unspec_volatile [(match_operand 0 "register_operand" "r")
+		     (match_operand 1 "register_operand" "r")] 5)]
+  ""
+  "*
+{
+  static int label_no;
+  int count_regno = REGNO (operands[0]);
+  int ptr_regno = REGNO (operands[1]);
+  char label[64];
+
+  /* Ho hum, output the hard way to get the label at the beginning of
+     the line.  Wish there were a magic char you could get
+     asm_output_printf to do that.  Then we could use %= as well and
+     get rid of the label_no bits here too.  */
+
+  ASM_GENERATE_INTERNAL_LABEL (label, \"LSC\", label_no);
+  ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LSC\", label_no++);
+
+  fprintf (asm_out_file, \"\\tstq $31,-8192($%d)\\n\", ptr_regno);
+  fprintf (asm_out_file, \"\\tsubq $%d,1,$%d\\n\", count_regno, count_regno);
+  fprintf (asm_out_file, \"\\tlda $%d,-8192($%d)\\n\", ptr_regno, ptr_regno);
+  fprintf (asm_out_file, \"\\tbne $%d,\", count_regno);
+  assemble_name (asm_out_file, label);
+  putc ('\\n', asm_out_file);
+
+  return \"\";
+}"
+  [(set_attr "length" "16")])
+
+(define_expand "prologue"
+  [(clobber (const_int 0))]
+  ""
+  "alpha_expand_prologue (); DONE;")
+
+(define_insn "init_fp"
+  [(set (match_operand:DI 0 "register_operand" "r")
+        (match_operand:DI 1 "register_operand" "r"))
+   (clobber (mem:BLK (match_operand:DI 2 "register_operand" "r")))]
+  ""
+  "bis %1,%1,%0")
+
+(define_expand "epilogue"
+  [(clobber (const_int 0))]
+  ""
+  "alpha_expand_epilogue (); DONE;")
+
+(define_expand "builtin_longjmp"
+  [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
+  "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
+  "
+{
+  /* The elements of the buffer are, in order:  */
+  rtx fp = gen_rtx_MEM (Pmode, operands[0]);
+  rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
+  rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
+  rtx pv = gen_rtx_REG (Pmode, 27);
+
+  /* This bit is the same as expand_builtin_longjmp.  */
+  emit_move_insn (hard_frame_pointer_rtx, fp);
+  emit_move_insn (pv, lab);
+  emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
+  emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
+  emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
+
+  /* Load the label we are jumping through into $27 so that we know
+     where to look for it when we get back to setjmp's function for
+     restoring the gp.  */
+  emit_indirect_jump (pv);
+}")
+
+(define_insn "builtin_setjmp_receiver"
+  [(unspec_volatile [(match_operand 0 "" "")] 2)]
+  "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT && TARGET_AS_CAN_SUBTRACT_LABELS"
+  "\\n$LSJ%=:\;ldgp $29,$LSJ%=-%l0($27)"
+  [(set_attr "length" "8")])
+
+(define_insn ""
+  [(unspec_volatile [(match_operand 0 "" "")] 2)]
+  "! TARGET_OPEN_VMS && ! TARGET_WINDOWS_NT"
+  "br $27,$LSJ%=\\n$LSJ%=:\;ldgp $29,0($27)"
+  [(set_attr "length" "12")])
+
+(define_expand "nonlocal_goto_receiver"
+  [(unspec_volatile [(const_int 0)] 1)
+   (set (reg:DI 27) (mem:DI (reg:DI 29)))
+   (unspec_volatile [(const_int 0)] 1)
+   (use (reg:DI 27))]
+  "TARGET_OPEN_VMS"
+  "")
+
+(define_insn "arg_home"
+  [(unspec [(const_int 0)] 0)
+   (use (reg:DI 1))
+   (use (reg:DI 25))
+   (use (reg:DI 16))
+   (use (reg:DI 17))
+   (use (reg:DI 18))
+   (use (reg:DI 19))
+   (use (reg:DI 20))
+   (use (reg:DI 21))
+   (use (reg:DI 48))
+   (use (reg:DI 49))
+   (use (reg:DI 50))
+   (use (reg:DI 51))
+   (use (reg:DI 52))
+   (use (reg:DI 53))
+   (clobber (mem:BLK (const_int 0)))
+   (clobber (reg:DI 24))
+   (clobber (reg:DI 25))
+   (clobber (reg:DI 0))]
+  "TARGET_OPEN_VMS"
+  "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
+  [(set_attr "length" "16")])
+
+;; Close the trap shadow of preceeding instructions.  This is generated
+;; by alpha_reorg.
+
+(define_insn "trapb"
+  [(unspec_volatile [(const_int 0)] 4)]
+  ""
+  "trapb"
+  [(set_attr "type" "misc")])
+
+;; Peepholes go at the end.
+
+;; Optimize sign-extension of SImode loads.  This shows up in the wake of
+;; reload when converting fp->int.
+;;
+;; ??? What to do now that we actually care about the packing and
+;; alignment of instructions?  Perhaps reload can be enlightened, or
+;; the peephole pass moved up after reload but before sched2?
+;
+;(define_peephole
+;  [(set (match_operand:SI 0 "register_operand" "=r")
+;        (match_operand:SI 1 "memory_operand" "m"))
+;   (set (match_operand:DI 2 "register_operand" "=r")
+;        (sign_extend:DI (match_dup 0)))]
+;  "dead_or_set_p (insn, operands[0])"
+;  "ldl %2,%1")
+;
+;(define_peephole
+;  [(set (match_operand:SI 0 "register_operand" "=r")
+;        (match_operand:SI 1 "hard_fp_register_operand" "f"))
+;   (set (match_operand:DI 2 "register_operand" "=r")
+;        (sign_extend:DI (match_dup 0)))]
+;  "TARGET_CIX && dead_or_set_p (insn, operands[0])"
+;  "ftois %1,%2")
diff --git a/contrib/gcc/config/alpha/crtbegin.asm b/contrib/gcc/config/alpha/crtbegin.asm
new file mode 100644
index 000000000000..c28440d8a248
--- /dev/null
+++ b/contrib/gcc/config/alpha/crtbegin.asm
@@ -0,0 +1,111 @@
+ # Copyright (C) 1996, 1998 Free Software Foundation, Inc.
+ #  Contributed by Richard Henderson (rth@tamu.edu)
+ #
+ # This file is free software; you can redistribute it and/or modify it
+ # under the terms of the GNU General Public License as published by the
+ # Free Software Foundation; either version 2, or (at your option) any
+ # later version.
+ # 
+ # In addition to the permissions in the GNU General Public License, the
+ # Free Software Foundation gives you unlimited permission to link the
+ # compiled version of this file with other programs, and to distribute
+ # those programs without any restriction coming from the use of this
+ # file.  (The General Public License restrictions do apply in other
+ # respects; for example, they cover modification of the file, and
+ # distribution when not linked into another program.)
+ # 
+ # This file is distributed in the hope that it will be useful, but
+ # WITHOUT ANY WARRANTY; without even the implied warranty of
+ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ # General Public License for more details.
+ # 
+ # You should have received a copy of the GNU General Public License
+ # along with this program; see the file COPYING.  If not, write to
+ # the Free Software Foundation, 59 Temple Place - Suite 330,
+ # Boston, MA 02111-1307, USA.
+ # 
+ #    As a special exception, if you link this library with files
+ #    compiled with GCC to produce an executable, this does not cause
+ #    the resulting executable to be covered by the GNU General Public License.
+ #    This exception does not however invalidate any other reasons why
+ #    the executable file might be covered by the GNU General Public License.
+
+ #
+ # Heads of the constructor/destructor lists.
+ #
+
+ # The __*TOR_LIST__ symbols are not global because when this file is used
+ # in a shared library, we do not want the symbol to fall over to the
+ # application's lists.
+
+.section .ctors,"aw"
+
+	.align 3
+__CTOR_LIST__:
+	.quad -1
+
+.section .dtors,"aw"
+
+	.align 3
+__DTOR_LIST__:
+	.quad -1
+
+
+ #
+ # Fragment of the ELF _fini routine that invokes our dtor cleanup.
+ #
+
+.section .fini,"ax"
+
+	# Since the bits of the _fini function are spread across many
+	# object files, each potentially with its own GP, we must
+	# assume we need to load ours.  Further, our .fini section
+	# can easily be more than 4MB away from our .text bits so we
+	# can't use bsr.
+
+	br      $29,1f
+1:	ldgp    $29,0($29)
+	jsr     $26,__do_global_dtors_aux
+
+	# Must match the alignment we got from crti.o else we get
+	# zero-filled holes in our _fini function and then SIGILL.
+	.align 3
+
+ #
+ # Invoke our destructors in order.
+ #
+
+.data
+
+ # Support recursive calls to exit.
+9:	.quad	__DTOR_LIST__
+
+.text
+
+	.align 3
+	.ent __do_global_dtors_aux
+
+__do_global_dtors_aux:
+	ldgp	$29,0($27)
+	lda     $30,-16($30)
+	.frame  $30,16,$26,0
+	stq	$9,8($30)
+	stq     $26,0($30)
+	.mask   0x4000200,-16
+	.prologue 1
+
+	lda     $9,9b
+	br      1f
+0:	stq	$1,0($9)
+	jsr     $26,($27)
+1:	ldq	$1,0($9)
+	ldq     $27,8($1)
+	addq    $1,8,$1
+	bne     $27,0b
+
+	ldq     $26,0($30)
+	ldq	$9,8($30)
+	lda     $30,16($30)
+	ret
+
+	.end __do_global_dtors_aux
diff --git a/contrib/gcc/config/alpha/crtend.asm b/contrib/gcc/config/alpha/crtend.asm
new file mode 100644
index 000000000000..36f11b9723aa
--- /dev/null
+++ b/contrib/gcc/config/alpha/crtend.asm
@@ -0,0 +1,105 @@
+ # Copyright (C) 1996 Free Software Foundation, Inc.
+ #  Contributed by Richard Henderson (rth@tamu.edu)
+ #
+ # This file is free software; you can redistribute it and/or modify it
+ # under the terms of the GNU General Public License as published by the
+ # Free Software Foundation; either version 2, or (at your option) any
+ # later version.
+ # 
+ # In addition to the permissions in the GNU General Public License, the
+ # Free Software Foundation gives you unlimited permission to link the
+ # compiled version of this file with other programs, and to distribute
+ # those programs without any restriction coming from the use of this
+ # file.  (The General Public License restrictions do apply in other
+ # respects; for example, they cover modification of the file, and
+ # distribution when not linked into another program.)
+ # 
+ # This file is distributed in the hope that it will be useful, but
+ # WITHOUT ANY WARRANTY; without even the implied warranty of
+ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ # General Public License for more details.
+ # 
+ # You should have received a copy of the GNU General Public License
+ # along with this program; see the file COPYING.  If not, write to
+ # the Free Software Foundation, 59 Temple Place - Suite 330,
+ # Boston, MA 02111-1307, USA.
+ # 
+ #    As a special exception, if you link this library with files
+ #    compiled with GCC to produce an executable, this does not cause
+ #    the resulting executable to be covered by the GNU General Public License.
+ #    This exception does not however invalidate any other reasons why
+ #    the executable file might be covered by the GNU General Public License.
+
+ #
+ # Tails of the constructor/destructor lists.
+ #
+
+ # The __*TOR_END__ symbols are not global because when this file is used
+ # in a shared library, we do not want the symbol to fall over to the
+ # application's lists.
+
+.section .ctors,"aw"
+
+	.align 3
+__CTOR_END__:
+	.quad   0
+
+.section .dtors,"aw"
+
+	.align 3
+__DTOR_END__:
+	.quad   0
+
+
+ #
+ # Fragment of the ELF _init routine that invokes our ctor startup
+ #
+
+.section .init,"ax"
+
+	# Since the bits of the _init function are spread across many
+	# object files, each potentially with its own GP, we must
+	# assume we need to load ours.  Further, our .init section
+	# can easily be more than 4MB away from our .text bits so we
+	# can't use bsr.
+
+	br      $29,1f
+1:	ldgp    $29,0($29)
+	jsr     $26,__do_global_ctors_aux
+
+	# Must match the alignment we got from crti.o else we get
+	# zero-filled holes in our _init function and thense SIGILL.
+	.align 3
+
+ #
+ # Invoke our destructors in order.
+ #
+
+.text
+
+	.align 3
+	.ent __do_global_ctors_aux
+
+__do_global_ctors_aux:
+	ldgp	$29,0($27)
+	lda     $30,-16($30)
+	.frame  $30,16,$26,0
+	stq     $9,8($30)
+	stq     $26,0($30)
+	.mask   0x4000200,-16
+	.prologue 1
+
+	lda     $9,__CTOR_END__
+	br      1f
+0:	jsr     $26,($27)
+1:	ldq     $27,-8($9)
+	subq    $9,8,$9
+	not     $27,$0
+	bne     $0,0b
+
+	ldq     $26,0($30)
+	ldq     $9,8($30)
+	lda     $30,16($30)
+	ret
+
+	.end __do_global_ctors_aux
diff --git a/contrib/gcc/config/alpha/elf.h b/contrib/gcc/config/alpha/elf.h
index 82f04104ec25..4f4703c14ef0 100644
--- a/contrib/gcc/config/alpha/elf.h
+++ b/contrib/gcc/config/alpha/elf.h
@@ -1,5 +1,5 @@
 /* Definitions of target machine for GNU compiler, for DEC Alpha w/ELF.
-   Copyright (C) 1996 Free Software Foundation, Inc.
+   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
    Contributed by Richard Henderson (rth@tamu.edu).
 
 This file is part of GNU CC.
@@ -19,53 +19,49 @@ along with GNU CC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.    */
 
-/* This is used on Alpha platforms that use the ELF format.
-Currently only Linux uses this. */
-
-#if 0
-#include "alpha/linux.h"
-#endif
-
-#undef TARGET_VERSION
-#define TARGET_VERSION fprintf (stderr, " (Alpha Linux/ELF)");
-
 #undef OBJECT_FORMAT_COFF
 #undef EXTENDED_COFF
 #define OBJECT_FORMAT_ELF
 
-#define SDB_DEBUGGING_INFO
+#define DBX_DEBUGGING_INFO
+
+#undef PREFERRED_DEBUGGING_TYPE
+#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
 
 #undef ASM_FINAL_SPEC
 
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "\
--D__alpha -D__alpha__ -D__linux__ -D__linux -D_LONGLONG -Dlinux -Dunix \
--Asystem(linux) -Acpu(alpha) -Amachine(alpha) -D__ELF__"
+#undef CC1_SPEC
+#define CC1_SPEC  "%{G*}"
+
+#undef ASM_SPEC
+#define ASM_SPEC  "%{G*} %{relax:-relax}"
 
 #undef LINK_SPEC
-#define LINK_SPEC "-m elf64alpha -G 8 %{O*:-O3} %{!O*:-O1}	\
+#define LINK_SPEC "-m elf64alpha %{G*} %{relax:-relax}		\
+  %{O*:-O3} %{!O*:-O1}						\
   %{shared:-shared}						\
   %{!shared:							\
     %{!static:							\
       %{rdynamic:-export-dynamic}				\
-      %{!dynamic-linker:-dynamic-linker /lib/ld.so.1}}		\
+      %{!dynamic-linker:-dynamic-linker %(elf_dynamic_linker)}}	\
     %{static:-static}}"
 
 /* Output at beginning of assembler file.  */
-
 #undef ASM_FILE_START
 #define ASM_FILE_START(FILE)					\
 {								\
   alpha_write_verstamp (FILE);					\
   output_file_directive (FILE, main_input_filename);		\
-  fprintf (FILE, "\t.version\t\"01.01\"\n");			\
   fprintf (FILE, "\t.set noat\n");				\
+  fprintf (FILE, "\t.set noreorder\n");                         \
+  if (TARGET_BWX | TARGET_MAX | TARGET_CIX)			\
+    {								\
+      fprintf (FILE, "\t.arch %s\n",				\
+               (alpha_cpu == PROCESSOR_EV6 ? "ev6"		\
+                : TARGET_MAX ? "pca56" : "ev56"));		\
+    }								\
 }
 
-#define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE)			\
-  alpha_output_lineno (STREAM, LINE)
-extern void alpha_output_lineno ();
-
 extern void output_file_directive ();
 
 /* Attach a special .ident directive to the end of the file to identify
@@ -77,8 +73,8 @@ extern void output_file_directive ();
 
 #ifdef IDENTIFY_WITH_IDENT
 #define ASM_IDENTIFY_GCC(FILE) /* nothing */
-#define ASM_IDENTIFY_LANGUAGE(FILE)				\
- fprintf(FILE, "\t%s \"GCC (%s) %s\"\n", IDENT_ASM_OP,		\
+#define ASM_IDENTIFY_LANGUAGE(FILE)			\
+ fprintf(FILE, "\t%s \"GCC (%s) %s\"\n", IDENT_ASM_OP,	\
 	 lang_identify(), version_string)
 #else
 #define ASM_FILE_END(FILE)					\
@@ -89,11 +85,9 @@ do {				 				\
 #endif
 
 /* Allow #sccs in preprocessor.  */
-
 #define SCCS_DIRECTIVE
 
 /* Output #ident as a .ident.  */
-
 #define ASM_OUTPUT_IDENT(FILE, NAME) \
   fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
 
@@ -155,22 +149,46 @@ do {									\
    the linker seems to want the alignment of data objects
    to depend on their types.  We do exactly that here.  */
 
-#define LOCAL_ASM_OP	".local"
-
 #undef ASM_OUTPUT_ALIGNED_LOCAL
 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN)		\
 do {									\
-  fprintf ((FILE), "\t%s\t", LOCAL_ASM_OP);				\
-  assemble_name ((FILE), (NAME));					\
-  fprintf ((FILE), "\n");						\
-  ASM_OUTPUT_ALIGNED_COMMON (FILE, NAME, SIZE, ALIGN);			\
+  if ((SIZE) <= g_switch_value)						\
+    sbss_section();							\
+  else									\
+    bss_section();							\
+  fprintf (FILE, "\t%s\t ", TYPE_ASM_OP);				\
+  assemble_name (FILE, NAME);						\
+  putc (',', FILE);							\
+  fprintf (FILE, TYPE_OPERAND_FMT, "object");				\
+  putc ('\n', FILE);							\
+  if (!flag_inhibit_size_directive)					\
+    {									\
+      fprintf (FILE, "\t%s\t ", SIZE_ASM_OP);				\
+      assemble_name (FILE, NAME);					\
+      fprintf (FILE, ",%d\n", (SIZE));					\
+    }									\
+  ASM_OUTPUT_ALIGN ((FILE), exact_log2((ALIGN) / BITS_PER_UNIT));	\
+  ASM_OUTPUT_LABEL(FILE, NAME);						\
+  ASM_OUTPUT_SKIP((FILE), (SIZE));					\
 } while (0)
 
 /* This is the pseudo-op used to generate a 64-bit word of data with a
-   specific value in some section.    */
+   specific value in some section.  */
 
 #define INT_ASM_OP		".quad"
 
+/* Biggest alignment supported by the object file format of this
+   machine.  Use this macro to limit the alignment which can be
+   specified using the `__attribute__ ((aligned (N)))' construct.  If
+   not defined, the default value is `BIGGEST_ALIGNMENT'. 
+
+   This value is really 2^63.  Since gcc figures the alignment in bits,
+   we could only potentially get to 2^60 on suitible hosts.  Due to other
+   considerations in varasm, we must restrict this to what fits in an int.  */
+
+#define MAX_OFILE_ALIGNMENT \
+  (1 << (HOST_BITS_PER_INT < 64 ? HOST_BITS_PER_INT - 2 : 62))
+
 /* This is the pseudo-op used to generate a contiguous sequence of byte
    values from a double-quoted string WITHOUT HAVING A TERMINATING NUL
    AUTOMATICALLY APPENDED.  This is the same for most svr4 assemblers.  */
@@ -208,6 +226,11 @@ do {									\
 #define CTORS_SECTION_ASM_OP	".section\t.ctors,\"aw\""
 #define DTORS_SECTION_ASM_OP	".section\t.dtors,\"aw\""
 
+/* Handle the small data sections.  */
+#define BSS_SECTION_ASM_OP	".section\t.bss"
+#define SBSS_SECTION_ASM_OP	".section\t.sbss,\"aw\""
+#define SDATA_SECTION_ASM_OP	".section\t.sdata,\"aw\""
+
 /* On svr4, we *do* have support for the .init and .fini sections, and we
    can put stuff in there to be executed before and after `main'.  We let
    crtstuff.c and other files know this by defining the following symbols.
@@ -217,17 +240,13 @@ do {									\
 #define INIT_SECTION_ASM_OP	".section\t.init"
 #define FINI_SECTION_ASM_OP	".section\t.fini"
 
-/* Support non-common, uninitialized data in the .bss section.  */
-
-#define BSS_SECTION_ASM_OP	".section\t.bss"
-
 /* A default list of other sections which we might be "in" at any given
    time.  For targets that use additional sections (e.g. .tdesc) you
    should override this definition in the target-specific file which
    includes this file.  */
 
 #undef EXTRA_SECTIONS
-#define EXTRA_SECTIONS in_const, in_ctors, in_dtors, in_bss
+#define EXTRA_SECTIONS in_const, in_ctors, in_dtors, in_sbss, in_sdata
 
 /* A default list of extra section function definitions.  For targets
    that use additional sections (e.g. .tdesc) you should override this
@@ -236,9 +255,10 @@ do {									\
 #undef EXTRA_SECTION_FUNCTIONS
 #define EXTRA_SECTION_FUNCTIONS						\
   CONST_SECTION_FUNCTION						\
-  CTORS_SECTION_FUNCTION						\
-  DTORS_SECTION_FUNCTION						\
-  BSS_SECTION_FUNCTION
+  SECTION_FUNCTION_TEMPLATE(ctors_section, in_ctors, CTORS_SECTION_ASM_OP) \
+  SECTION_FUNCTION_TEMPLATE(dtors_section, in_dtors, DTORS_SECTION_ASM_OP) \
+  SECTION_FUNCTION_TEMPLATE(sbss_section, in_sbss, SBSS_SECTION_ASM_OP)	\
+  SECTION_FUNCTION_TEMPLATE(sdata_section, in_sdata, SDATA_SECTION_ASM_OP)
 
 #undef READONLY_DATA_SECTION
 #define READONLY_DATA_SECTION() const_section ()
@@ -258,36 +278,13 @@ const_section ()							\
     }									\
 }
 
-#define CTORS_SECTION_FUNCTION						\
-void									\
-ctors_section ()							\
+#define SECTION_FUNCTION_TEMPLATE(FN, ENUM, OP)				\
+void FN ()								\
 {									\
-  if (in_section != in_ctors)						\
+  if (in_section != ENUM)						\
     {									\
-      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);		\
-      in_section = in_ctors;						\
-    }									\
-}
-
-#define DTORS_SECTION_FUNCTION						\
-void									\
-dtors_section ()							\
-{									\
-  if (in_section != in_dtors)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);		\
-      in_section = in_dtors;						\
-    }									\
-}
-
-#define BSS_SECTION_FUNCTION						\
-void									\
-bss_section ()								\
-{									\
-  if (in_section != in_bss)						\
-    {									\
-      fprintf (asm_out_file, "%s\n", BSS_SECTION_ASM_OP);		\
-      in_section = in_bss;						\
+      fprintf (asm_out_file, "%s\n", OP);				\
+      in_section = ENUM;						\
     }									\
 }
 
@@ -297,10 +294,10 @@ bss_section ()								\
 
    We make the section read-only and executable for a function decl,
    read-only for a const data decl, and writable for a non-const data decl.  */
-#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME) \
+#define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
   fprintf (FILE, ".section\t%s,\"%s\",@progbits\n", NAME, \
 	   (DECL) && TREE_CODE (DECL) == FUNCTION_DECL ? "ax" : \
-	   (DECL) && TREE_READONLY (DECL) ? "a" : "aw")
+	   (DECL) && DECL_READONLY_SECTION (DECL, RELOC) ? "a" : "aw")
 
 
 /* A C statement (sans semicolon) to output an element in the table of
@@ -344,11 +341,10 @@ bss_section ()								\
 	  || !DECL_INITIAL (DECL)					\
 	  || (DECL_INITIAL (DECL) != error_mark_node			\
 	      && !TREE_CONSTANT (DECL_INITIAL (DECL))))			\
-        {								\
-          if (DECL_COMMON (DECL)					\
-	      && !DECL_INITIAL (DECL))					\
-	          /* || DECL_INITIAL (DECL) == error_mark_node)) */	\
-	    bss_section();						\
+	{								\
+	  int size = int_size_in_bytes (TREE_TYPE (DECL));		\
+	  if (size >= 0 && size <= g_switch_value)			\
+	    sdata_section ();						\
 	  else								\
 	    data_section ();						\
 	}								\
@@ -486,39 +482,39 @@ do {									 \
    escape sequence like \377 would count as four bytes.
 
    If your target assembler doesn't support the .string directive, you
-   should define this to zero.
-*/
+   should define this to zero.  */
 
 #define STRING_LIMIT	((unsigned) 256)
-
 #define STRING_ASM_OP	".string"
 
-/*
- * We always use gas here, so we don't worry about ECOFF assembler problems.
- */
+/* GAS is the only Alpha/ELF assembler.  */
 #undef TARGET_GAS
 #define TARGET_GAS	(1)
 
-#undef PREFERRED_DEBUGGING_TYPE
-#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
+/* Provide a STARTFILE_SPEC appropriate for ELF.  Here we add the
+   (even more) magical crtbegin.o file which provides part of the
+   support for getting C++ file-scope static object constructed before
+   entering `main'. 
 
-/* Provide a STARTFILE_SPEC appropriate for Linux.  Here we add
-   the Linux magical crtbegin.o file (see crtstuff.c) which
-   provides part of the support for getting C++ file-scope static
-   object constructed before entering `main'. */
+   Don't bother seeing crtstuff.c -- there is absolutely no hope of
+   getting that file to understand multiple GPs.  GNU Libc provides a
+   hand-coded version that is used on Linux; it could be copied here
+   if there is ever a need. */
    
 #undef	STARTFILE_SPEC
 #define STARTFILE_SPEC \
   "%{!shared: \
      %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} %{!p:crt1.o%s}}}\
-   crti.o%s %{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}"
+   crti.o%s crtbegin.o%s"
 
-/* Provide a ENDFILE_SPEC appropriate for Linux.  Here we tack on
-   the Linux magical crtend.o file (see crtstuff.c) which
-   provides part of the support for getting C++ file-scope static
-   object constructed before entering `main', followed by a normal
-   Linux "finalizer" file, `crtn.o'.  */
+/* Provide a ENDFILE_SPEC appropriate for ELF.  Here we tack on the
+   magical crtend.o file which provides part of the support for
+   getting C++ file-scope static object constructed before entering
+   `main', followed by a normal ELF "finalizer" file, `crtn.o'.  */
 
 #undef	ENDFILE_SPEC
 #define ENDFILE_SPEC \
-  "%{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s"
+  "crtend.o%s crtn.o%s"
+
+/* We support #pragma.  */
+#define HANDLE_SYSV_PRAGMA
diff --git a/contrib/gcc/config/alpha/linux-ecoff.h b/contrib/gcc/config/alpha/linux-ecoff.h
new file mode 100644
index 000000000000..a6cd5b238c80
--- /dev/null
+++ b/contrib/gcc/config/alpha/linux-ecoff.h
@@ -0,0 +1,36 @@
+/* Definitions of target machine for GNU compiler
+   for Alpha Linux-based GNU systems using ECOFF.
+   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+   Contributed by Bob Manson.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#undef TARGET_VERSION
+#define TARGET_VERSION fprintf (stderr, " (Alpha GNU/Linux for ECOFF)");
+
+#undef SUB_CPP_PREDEFINES
+#define SUB_CPP_PREDEFINES "-D__ECOFF__"
+
+#undef LINK_SPEC
+#define LINK_SPEC "-G 8 %{O*:-O3} %{!O*:-O1}"
+
+/* stabs get slurped by the assembler into a queer ecoff format.  */
+#undef PREFERRED_DEBUGGING_TYPE
+#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
+
+/* We support #pragma.  */
+#define HANDLE_SYSV_PRAGMA
diff --git a/contrib/gcc/config/alpha/linux-elf.h b/contrib/gcc/config/alpha/linux-elf.h
new file mode 100644
index 000000000000..90009f1c5d0c
--- /dev/null
+++ b/contrib/gcc/config/alpha/linux-elf.h
@@ -0,0 +1,47 @@
+/* Definitions of target machine for GNU compiler
+   for Alpha Linux-based GNU systems using ELF.
+   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+   Contributed by Richard Henderson.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#undef TARGET_VERSION
+#define TARGET_VERSION fprintf (stderr, " (Alpha GNU/Linux for ELF)");
+
+#undef SUBTARGET_EXTRA_SPECS
+#define SUBTARGET_EXTRA_SPECS \
+{ "elf_dynamic_linker", ELF_DYNAMIC_LINKER },
+
+#undef SUB_CPP_PREDEFINES
+#define SUB_CPP_PREDEFINES	"-D__ELF__"
+
+#ifdef USE_GNULIBC_1
+#define ELF_DYNAMIC_LINKER	"/lib/ld.so.1"
+#else
+#define ELF_DYNAMIC_LINKER	"/lib/ld-linux.so.2"
+#endif
+
+#ifndef USE_GNULIBC_1
+#undef DEFAULT_VTABLE_THUNKS
+#define DEFAULT_VTABLE_THUNKS 1
+#endif
+
+#ifndef USE_GNULIBC_1
+#undef LIB_SPEC
+#define LIB_SPEC \
+"%{shared:-lc}%{!shared:%{pthread:-lpthread }%{profile:-lc_p}%{!profile:-lc}} "
+#endif
diff --git a/contrib/gcc/config/alpha/linux.h b/contrib/gcc/config/alpha/linux.h
new file mode 100644
index 000000000000..3791c8944eb0
--- /dev/null
+++ b/contrib/gcc/config/alpha/linux.h
@@ -0,0 +1,44 @@
+/* Definitions of target machine for GNU compiler,
+   for Alpha Linux-based GNU systems.
+   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+   Contributed by Richard Henderson.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#undef TARGET_DEFAULT
+#define TARGET_DEFAULT (MASK_FP | MASK_FPREGS | MASK_GAS)
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES \
+"-Dlinux -Dunix -Asystem(linux) -D_LONGLONG -D__alpha__ " SUB_CPP_PREDEFINES
+
+#undef LIB_SPEC
+#define LIB_SPEC "%{pg:-lgmon} %{pg:-lc_p} %{!pg:-lc}"
+
+/* Generate calls to memcpy, etc., not bcopy, etc. */
+#define TARGET_MEM_FUNCTIONS 1
+
+#undef FUNCTION_PROFILER
+#define FUNCTION_PROFILER(FILE, LABELNO)			\
+	fputs ("\tlda $28,_mcount\n\tjsr $28,($28),_mcount\n", (FILE))
+
+/* Show that we need a GP when profiling.  */
+#define TARGET_PROFILING_NEEDS_GP 1
+
+/* Don't care about faults in the prologue.  */
+#undef TARGET_CAN_FAULT_IN_PROLOGUE
+#define TARGET_CAN_FAULT_IN_PROLOGUE 1
diff --git a/contrib/gcc/config/alpha/netbsd-elf.h b/contrib/gcc/config/alpha/netbsd-elf.h
new file mode 100644
index 000000000000..17d7bb0e4ae1
--- /dev/null
+++ b/contrib/gcc/config/alpha/netbsd-elf.h
@@ -0,0 +1,31 @@
+/* Definitions of target machine for GNU compiler
+   for Alpha NetBSD systems using ELF.
+   Copyright (C) 1998 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#undef TARGET_VERSION
+#define TARGET_VERSION fprintf (stderr, " (Alpha NetBSD/ELF)");
+
+#undef SUB_CPP_PREDEFINES
+#define SUB_CPP_PREDEFINES "-D__ELF__"
+
+#undef SUBTARGET_EXTRA_SPECS
+#define SUBTARGET_EXTRA_SPECS \
+{ "elf_dynamic_linker", ELF_DYNAMIC_LINKER },
+
+#define ELF_DYNAMIC_LINKER	"/usr/libexec/ld.elf_so"
diff --git a/contrib/gcc/config/alpha/netbsd.h b/contrib/gcc/config/alpha/netbsd.h
new file mode 100644
index 000000000000..054e9e063b46
--- /dev/null
+++ b/contrib/gcc/config/alpha/netbsd.h
@@ -0,0 +1,38 @@
+/* Definitions of target machine for GNU compiler,
+   for Alpha NetBSD systems.
+   Copyright (C) 1998 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
+
+#undef TARGET_DEFAULT
+#define TARGET_DEFAULT (MASK_FP | MASK_FPREGS | MASK_GAS)
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES "-D_LONGLONG -Dnetbsd -Dunix " SUB_CPP_PREDEFINES
+
+#undef LIB_SPEC
+#define LIB_SPEC "%{pg:-lgmon} %{pg:-lc_p} %{!pg:-lc}"
+
+/* Generate calls to memcpy, etc., not bcopy, etc. */
+#define TARGET_MEM_FUNCTIONS
+
+#undef FUNCTION_PROFILER
+#define FUNCTION_PROFILER(FILE, LABELNO)			\
+	fputs ("\tlda $28,_mcount\n\tjsr $28,($28),_mcount\n", (FILE))
+
+/* Show that we need a GP when profiling.  */
+#define TARGET_PROFILING_NEEDS_GP
diff --git a/contrib/gcc/config/alpha/openbsd.h b/contrib/gcc/config/alpha/openbsd.h
new file mode 100644
index 000000000000..60591d554f56
--- /dev/null
+++ b/contrib/gcc/config/alpha/openbsd.h
@@ -0,0 +1,126 @@
+/* Configuration file for an alpha OpenBSD target.
+   Copyright (C) 1999 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* We settle for little endian for now.  */
+#define TARGET_ENDIAN_DEFAULT 0
+
+#include <alpha/alpha.h>
+
+#define OBSD_NO_DYNAMIC_LIBRARIES
+#define OBSD_HAS_DECLARE_FUNCTION_NAME
+#define OBSD_HAS_DECLARE_FUNCTION_SIZE
+#define OBSD_HAS_DECLARE_OBJECT
+
+/* alpha ecoff supports only weak aliases, see below.  */
+#define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS (FILE,NAME,0)
+
+#include <openbsd.h>
+
+/* Controlling the compilation driver.  */
+
+/* alpha needs __start.  */
+#undef LINK_SPEC
+#define LINK_SPEC \
+  "%{!nostdlib:%{!r*:%{!e*:-e __start}}} -dc -dp %{assert*}"
+
+/* run-time target specifications */
+#define CPP_PREDEFINES "-D__unix__ -D__ANSI_COMPAT -Asystem(unix) \
+-D__OpenBSD__ -D__alpha__ -D__alpha"
+
+/* Layout of source language data types.  */
+
+/* This must agree with <machine/ansi.h> */
+#undef SIZE_TYPE
+#define SIZE_TYPE "long unsigned int"
+
+#undef PTRDIFF_TYPE
+#define PTRDIFF_TYPE "long int"
+
+#undef WCHAR_TYPE
+#define WCHAR_TYPE "int"
+
+#undef WCHAR_TYPE_SIZE
+#define WCHAR_TYPE_SIZE 32
+
+
+#undef PREFERRED_DEBUGGING_TYPE
+#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
+
+#define LOCAL_LABEL_PREFIX	"."
+
+/* We don't have an init section yet.  */
+#undef HAS_INIT_SECTION
+
+/* collect2 support (assembler format: macros for initialization).  */
+
+/* Don't tell collect2 we use COFF as we don't have (yet ?) a dynamic ld
+   library with the proper functions to handle this -> collect2 will
+   default to using nm.  */
+#undef OBJECT_FORMAT_COFF
+#undef EXTENDED_COFF
+
+/* Assembler format: exception region output.  */
+
+/* All configurations that don't use elf must be explicit about not using
+   dwarf unwind information. egcs doesn't try too hard to check internal
+   configuration files...  */
+#ifdef INCOMING_RETURN_ADDR_RTX
+#undef DWARF2_UNWIND_INFO
+#define DWARF2_UNWIND_INFO 0
+#endif
+
+/* Assembler format: file framework.  */
+
+/* Taken from alpha/osf.h. This used to be common to all alpha
+   configurations, but elf has departed from it.
+   Check alpha/alpha.h, alpha/osf.h for it when egcs is upgraded.  */
+#ifndef ASM_FILE_START
+#define ASM_FILE_START(FILE)					\
+{								\
+  alpha_write_verstamp (FILE);					\
+  fprintf (FILE, "\t.set noreorder\n");				\
+  fprintf (FILE, "\t.set volatile\n");                          \
+  fprintf (FILE, "\t.set noat\n");				\
+  if (TARGET_SUPPORT_ARCH)					\
+    fprintf (FILE, "\t.arch %s\n",				\
+             alpha_cpu == PROCESSOR_EV6 ? "ev6"			\
+	     : (alpha_cpu == PROCESSOR_EV5			\
+		? (TARGET_MAX ? "pca56" : TARGET_BWX ? "ev56" : "ev5") \
+		: "ev4"));					\
+								\
+  ASM_OUTPUT_SOURCE_FILENAME (FILE, main_input_filename);	\
+}
+#endif
+
+/* Assembler format: label output.  */
+
+#define ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,VALUE)	\
+ do {						\
+  fputs ("\t.weakext\t", FILE);			\
+  assemble_name (FILE, NAME);			\
+  if (VALUE)					\
+    {						\
+      fputs (" , ", FILE);			\
+      assemble_name (FILE, VALUE);		\
+    }						\
+  fputc ('\n', FILE);				\
+ } while (0)
+
+
diff --git a/contrib/gcc/config/alpha/osf.h b/contrib/gcc/config/alpha/osf.h
new file mode 100644
index 000000000000..956961f7cf3c
--- /dev/null
+++ b/contrib/gcc/config/alpha/osf.h
@@ -0,0 +1,127 @@
+/* Definitions of target machine for GNU compiler, for DEC Alpha on OSF/1.
+   Copyright (C) 1992, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
+   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* As of OSF 4.0, as can subtract adjacent labels.  */
+
+#undef TARGET_AS_CAN_SUBTRACT_LABELS
+#define TARGET_AS_CAN_SUBTRACT_LABELS 1
+
+/* Names to predefine in the preprocessor for this target machine.  */
+
+#define CPP_PREDEFINES "\
+-Dunix -D__osf__ -D_LONGLONG -DSYSTYPE_BSD \
+-D_SYSTYPE_BSD -Asystem(unix) -Asystem(xpg4)"
+
+/* Under OSF4, -p and -pg require -lprof1, and -lprof1 requires -lpdf.  */
+
+#define LIB_SPEC "%{p:-lprof1 -lpdf} %{pg:-lprof1 -lpdf} %{a:-lprof2} -lc"
+
+/* Pass "-G 8" to ld because Alpha's CC does.  Pass -O3 if we are
+   optimizing, -O1 if we are not.  Pass -shared, -non_shared or
+   -call_shared as appropriate.  Also pass -pg.  */
+#define LINK_SPEC  \
+  "-G 8 %{O*:-O3} %{!O*:-O1} %{static:-non_shared} \
+   %{!static:%{shared:-shared} %{!shared:-call_shared}} %{pg} %{taso} \
+   %{rpath*}"
+
+#define STARTFILE_SPEC  \
+  "%{!shared:%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}}"
+
+#define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
+
+#define ASM_FILE_START(FILE)					\
+{								\
+  alpha_write_verstamp (FILE);					\
+  fprintf (FILE, "\t.set noreorder\n");				\
+  fprintf (FILE, "\t.set volatile\n");                          \
+  fprintf (FILE, "\t.set noat\n");				\
+  if (TARGET_SUPPORT_ARCH)					\
+    fprintf (FILE, "\t.arch %s\n",				\
+             alpha_cpu == PROCESSOR_EV6 ? "ev6"			\
+	     : (alpha_cpu == PROCESSOR_EV5			\
+		? (TARGET_MAX ? "pca56" : TARGET_BWX ? "ev56" : "ev5") \
+		: "ev4"));					\
+								\
+  ASM_OUTPUT_SOURCE_FILENAME (FILE, main_input_filename);	\
+}
+
+/* No point in running CPP on our assembler output.  */
+#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_GAS) != 0
+/* Don't pass -g to GNU as, because some versions don't accept this option.  */
+#define ASM_SPEC "%{malpha-as:-g} -nocpp %{pg}"
+#else
+/* In OSF/1 v3.2c, the assembler by default does not output file names which
+   causes mips-tfile to fail.  Passing -g to the assembler fixes this problem.
+   ??? Strictly speaking, we need -g only if the user specifies -g.  Passing
+   it always means that we get slightly larger than necessary object files
+   if the user does not specify -g.  If we don't pass -g, then mips-tfile
+   will need to be fixed to work in this case.  Pass -O0 since some
+   optimization are broken and don't help us anyway.  */
+#define ASM_SPEC "%{!mgas:-g} -nocpp %{pg} -O0"
+#endif
+
+/* Specify to run a post-processor, mips-tfile after the assembler
+   has run to stuff the ecoff debug information into the object file.
+   This is needed because the Alpha assembler provides no way
+   of specifying such information in the assembly file.  */
+
+#if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_GAS) != 0
+
+#define ASM_FINAL_SPEC "\
+%{malpha-as: %{!mno-mips-tfile: \
+	\n mips-tfile %{v*: -v} \
+		%{K: -I %b.o~} \
+		%{!K: %{save-temps: -I %b.o~}} \
+		%{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
+		%{.s:%i} %{!.s:%g.s}}}"
+
+#else
+#define ASM_FINAL_SPEC "\
+%{!mgas: %{!mno-mips-tfile: \
+	\n mips-tfile %{v*: -v} \
+		%{K: -I %b.o~} \
+		%{!K: %{save-temps: -I %b.o~}} \
+		%{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
+		%{.s:%i} %{!.s:%g.s}}}"
+
+#endif
+
+/* Indicate that we have a stamp.h to use.  */
+#ifndef CROSS_COMPILE
+#define HAVE_STAMP_H 1
+#endif
+
+/* Attempt to turn on access permissions for the stack.  */
+
+#define TRANSFER_FROM_TRAMPOLINE					\
+void									\
+__enable_execute_stack (addr)						\
+     void *addr;							\
+{									\
+  long size = getpagesize ();						\
+  long mask = ~(size-1);						\
+  char *page = (char *) (((long) addr) & mask);				\
+  char *end  = (char *) ((((long) (addr + TRAMPOLINE_SIZE)) & mask) + size); \
+									\
+  /* 7 is PROT_READ | PROT_WRITE | PROT_EXEC */				\
+  if (mprotect (page, end - page, 7) < 0)				\
+    perror ("mprotect of trampoline code");				\
+}
diff --git a/contrib/gcc/config/alpha/osf12.h b/contrib/gcc/config/alpha/osf12.h
index fe9112c007aa..87e21111f4dc 100644
--- a/contrib/gcc/config/alpha/osf12.h
+++ b/contrib/gcc/config/alpha/osf12.h
@@ -1,5 +1,5 @@
 /* Definitions of target machine for GNU compiler, for DEC Alpha.
-   Copyright (C) 1992, 1993, 1995 Free Software Foundation, Inc.
+   Copyright (C) 1992, 1993, 1995, 1996 Free Software Foundation, Inc.
    Contributed by Richard Kenner (kenner@nyu.edu)
 
 This file is part of GNU CC.
@@ -19,9 +19,6 @@ along with GNU CC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-
-#include "alpha/alpha.h"
-
 /* In OSF 1.2, there is a linker bug that prevents use of -O3 to
    the linker.  */
 
@@ -29,3 +26,8 @@ Boston, MA 02111-1307, USA.  */
 #define LINK_SPEC  \
   "-G 8 -O1 %{static:-non_shared} %{rpath*} \
    %{!static:%{shared:-shared} %{!shared:-call_shared}} %{taso}"
+
+#undef WCHAR_TYPE
+#define WCHAR_TYPE "short unsigned int"
+#undef WCHAR_TYPE_SIZE
+#define WCHAR_TYPE_SIZE 16
diff --git a/contrib/gcc/config/alpha/osf2or3.h b/contrib/gcc/config/alpha/osf2or3.h
new file mode 100644
index 000000000000..5abdb0e98b13
--- /dev/null
+++ b/contrib/gcc/config/alpha/osf2or3.h
@@ -0,0 +1,30 @@
+/* Definitions of target machine for GNU compiler, for DEC Alpha, osf[23].
+   Copyright (C) 1997 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* In OSF 2 or 3, linking with -lprof1 doesn't require -lpdf.  */
+
+#undef LIB_SPEC
+#define LIB_SPEC "%{p:-lprof1} %{pg:-lprof1} %{a:-lprof2} -lc"
+
+/* As of OSF 3.2, as still can't subtract adjacent labels.  */
+
+#undef TARGET_AS_CAN_SUBTRACT_LABELS
+#define TARGET_AS_CAN_SUBTRACT_LABELS 0
+
diff --git a/contrib/gcc/config/alpha/t-crtbe b/contrib/gcc/config/alpha/t-crtbe
new file mode 100644
index 000000000000..5e82b923c720
--- /dev/null
+++ b/contrib/gcc/config/alpha/t-crtbe
@@ -0,0 +1,9 @@
+# Effectively disable the crtbegin/end rules using crtstuff.c
+T = disable
+
+# Assemble startup files.
+crtbegin.o: $(srcdir)/config/alpha/crtbegin.asm $(GCC_PASSES)
+	$(GCC_FOR_TARGET) -c -o crtbegin.o -x assembler $(srcdir)/config/alpha/crtbegin.asm
+
+crtend.o: $(srcdir)/config/alpha/crtend.asm $(GCC_PASSES)
+	$(GCC_FOR_TARGET) -c -o crtend.o -x assembler $(srcdir)/config/alpha/crtend.asm
diff --git a/contrib/gcc/config/alpha/t-vms b/contrib/gcc/config/alpha/t-vms
new file mode 100644
index 000000000000..12ac24098ce7
--- /dev/null
+++ b/contrib/gcc/config/alpha/t-vms
@@ -0,0 +1,6 @@
+# Do not build libgcc1.
+LIBGCC1 = 
+CROSS_LIBGCC1 =
+
+LIB2FUNCS_EXTRA = tramp.s
+
diff --git a/contrib/gcc/config/alpha/va_list.h b/contrib/gcc/config/alpha/va_list.h
new file mode 100644
index 000000000000..c9ab2b0b50e2
--- /dev/null
+++ b/contrib/gcc/config/alpha/va_list.h
@@ -0,0 +1,16 @@
+/* A replacement for Digital Unix's <va_list.h>.  */
+
+#include <va-alpha.h>
+
+#if !defined(_VA_LIST) && !defined(_HIDDEN_VA_LIST)
+#define _VA_LIST
+typedef __gnuc_va_list va_list;
+
+#elif defined(_HIDDEN_VA_LIST) && !defined(_HIDDEN_VA_LIST_DONE)
+#define _HIDDEN_VA_LIST_DONE
+typedef __gnuc_va_list __va_list;
+
+#elif defined(_HIDDEN_VA_LIST) && defined(_VA_LIST)
+#undef _HIDDEN_VA_LIST
+
+#endif
diff --git a/contrib/gcc/config/alpha/vms-tramp.asm b/contrib/gcc/config/alpha/vms-tramp.asm
new file mode 100644
index 000000000000..fce9ec539cad
--- /dev/null
+++ b/contrib/gcc/config/alpha/vms-tramp.asm
@@ -0,0 +1,22 @@
+;# New Alpha OpenVMS trampoline
+;#
+	.set noreorder
+	.set volatile
+	.set noat
+	.file 1 "tramp.s"
+.text
+	.align 3
+	.globl __tramp
+	.ent __tramp
+__tramp..en:
+
+.link
+	.align 3
+__tramp:
+	.pdesc __tramp..en,null
+.text
+	ldq $1,24($27)
+	ldq $27,16($27)
+	ldq $28,8($27)
+	jmp $31,($28),0
+	.end __tramp
diff --git a/contrib/gcc/config/alpha/vms.h b/contrib/gcc/config/alpha/vms.h
new file mode 100644
index 000000000000..44cf5bf82dff
--- /dev/null
+++ b/contrib/gcc/config/alpha/vms.h
@@ -0,0 +1,510 @@
+/* Output variables, constants and external declarations, for GNU compiler.
+   Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define OPEN_VMS 1
+
+/* This enables certain macros in alpha.h, which will make an indirect
+   reference to an external symbol an invalid address.  This needs to be
+   defined before we include alpha.h, since it determines which macros
+   are used for GO_IF_*.  */
+
+#define NO_EXTERNAL_INDIRECT_ADDRESS
+
+#include "alpha/alpha.h"
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES \
+"-D__ALPHA -Dvms -DVMS -D__vms__ -D__VMS__ -Asystem(vms)"
+
+#undef CPP_SUBTARGET_SPEC
+#define CPP_SUBTARGET_SPEC "\
+%{mfloat-ieee:-D__IEEE_FLOAT} \
+%{mfloat-vax:-D__G_FLOAT} \
+%{!mfloat-vax:-D__IEEE_FLOAT}"
+
+/* Under OSF4, -p and -pg require -lprof1, and -lprof1 requires -lpdf.  */
+
+#define LIB_SPEC "%{p:-lprof1 -lpdf} %{pg:-lprof1 -lpdf} %{a:-lprof2} -lc"
+
+/* Pass "-G 8" to ld because Alpha's CC does.  Pass -O3 if we are
+   optimizing, -O1 if we are not.  Pass -shared, -non_shared or
+   -call_shared as appropriate.  Also pass -pg.  */
+#define LINK_SPEC  \
+  "-G 8 %{O*:-O3} %{!O*:-O1} %{static:-non_shared} \
+   %{!static:%{shared:-shared} %{!shared:-call_shared}} %{pg} %{taso} \
+   %{rpath*}"
+
+/* We allow $'s in identifiers unless -ansi is used .. */
+
+#define DOLLARS_IN_IDENTIFIERS 2
+
+/* These match the definitions used in DECCRTL, the VMS C run-time library
+
+#define SIZE_TYPE	"unsigned int"
+#define PTRDIFF_TYPE	"int"
+*/
+
+/* Use memcpy for structure copying, and so forth.  */
+#define TARGET_MEM_FUNCTIONS
+
+/* By default, allow $ to be part of an identifier.  */
+#define DOLLARS_IN_IDENTIFIERS 2
+
+#undef TARGET_DEFAULT
+#define TARGET_DEFAULT (MASK_FP|MASK_FPREGS|MASK_GAS)
+#undef TARGET_OPEN_VMS
+#define TARGET_OPEN_VMS 1
+
+#undef TARGET_NAME   
+#define TARGET_NAME "OpenVMS/Alpha"
+#undef TARGET_VERSION
+#define TARGET_VERSION fprintf (stderr, " (%s)", TARGET_NAME);           
+
+/* The structure return address arrives as an "argument" on VMS.  */
+#undef STRUCT_VALUE_REGNUM
+#define STRUCT_VALUE 0
+#undef PCC_STATIC_STRUCT_RETURN
+
+/* no floating emulation.  */
+#undef REAL_ARITHMETIC
+
+/* "long" is 32 bits.  */
+#undef LONG_TYPE_SIZE
+#define LONG_TYPE_SIZE 32
+
+/* Pointer is 32 bits but the hardware has 64-bit addresses, sign extended. */
+#undef POINTER_SIZE
+#define POINTER_SIZE 32
+#define POINTERS_EXTEND_UNSIGNED 0
+
+#define MAX_OFILE_ALIGNMENT 524288  /* 8 x 2^16 by DEC Ada Test CD40VRA */
+
+#undef FIXED_REGISTERS
+#define FIXED_REGISTERS  \
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }
+
+#undef CALL_USED_REGISTERS
+#define CALL_USED_REGISTERS  \
+ {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+  1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
+  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }
+
+#undef HARD_FRAME_POINTER_REGNUM
+#define HARD_FRAME_POINTER_REGNUM 29
+
+#undef CAN_ELIMINATE
+#define CAN_ELIMINATE(FROM, TO)  \
+((TO) != STACK_POINTER_REGNUM || ! alpha_using_fp ())
+
+#undef INITIAL_ELIMINATION_OFFSET
+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)			\
+{ if ((FROM) == FRAME_POINTER_REGNUM)					\
+    (OFFSET) = alpha_sa_size () + alpha_pv_save_size ();		\
+  else if ((FROM) == ARG_POINTER_REGNUM)				\
+    (OFFSET) = (ALPHA_ROUND (alpha_sa_size () + alpha_pv_save_size ()	\
+			     + get_frame_size ()			\
+			     + current_function_pretend_args_size)	\
+		- current_function_pretend_args_size);			\
+  if ((TO) == STACK_POINTER_REGNUM)					\
+    (OFFSET) += ALPHA_ROUND (current_function_outgoing_args_size);	\
+}
+
+/* Define a data type for recording info about an argument list
+   during the scan of that argument list.  This data type should
+   hold all necessary information about the function itself
+   and about the args processed so far, enough to enable macros
+   such as FUNCTION_ARG to determine where the next arg should go.
+
+   On Alpha/VMS, this is a structure that contains the number of
+   arguments and, for each argument, the datatype of that argument.
+
+   The number of arguments is a number of words of arguments scanned so far.
+   Thus 6 or more means all following args should go on the stack.  */
+
+enum avms_arg_type {I64, FF, FD, FG, FS, FT};
+typedef struct {char num_args; enum avms_arg_type atypes[6];} avms_arg_info;
+
+#undef CUMULATIVE_ARGS
+#define CUMULATIVE_ARGS avms_arg_info
+
+/* Initialize a variable CUM of type CUMULATIVE_ARGS
+   for a call to a function whose data type is FNTYPE.
+   For a library call, FNTYPE is 0.  */
+
+#undef INIT_CUMULATIVE_ARGS
+#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
+  (CUM).num_args = 0;						\
+  (CUM).atypes[0] = (CUM).atypes[1] = (CUM).atypes[2] = I64;	\
+  (CUM).atypes[3] = (CUM).atypes[4] = (CUM).atypes[5] = I64;
+
+/* Update the data in CUM to advance over an argument
+   of mode MODE and data type TYPE.
+   (TYPE is null for libcalls where that information may not be available.)  */
+
+extern enum avms_arg_type alpha_arg_type ();
+
+/* Determine where to put an argument to a function.
+   Value is zero to push the argument on the stack,
+   or a hard register in which to store the argument.
+
+   MODE is the argument's machine mode (or VOIDmode for no more args).
+   TYPE is the data type of the argument (as a tree).
+    This is null for libcalls where that information may
+    not be available.
+   CUM is a variable of type CUMULATIVE_ARGS which gives info about
+    the preceding args and about the function being called.
+   NAMED is nonzero if this argument is a named parameter
+    (otherwise it is an extra parameter matching an ellipsis).
+
+   On Alpha the first 6 words of args are normally in registers
+   and the rest are pushed.  */
+
+extern struct rtx_def *alpha_arg_info_reg_val ();
+#undef FUNCTION_ARG
+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)	\
+((MODE) == VOIDmode ? alpha_arg_info_reg_val (CUM)		\
+ : ((CUM.num_args) < 6 && ! MUST_PASS_IN_STACK (MODE, TYPE)	\
+    ? gen_rtx(REG, (MODE),					\
+	      ((CUM).num_args + 16				\
+	       + ((TARGET_FPREGS				\
+		   && (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
+		       || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
+		  * 32)))			\
+    : 0))
+
+#undef FUNCTION_ARG_ADVANCE
+#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)			\
+  if (MUST_PASS_IN_STACK (MODE, TYPE))					\
+    (CUM).num_args += 6;						\
+  else									\
+    {									\
+      if ((CUM).num_args < 6)						\
+        (CUM).atypes[(CUM).num_args] = alpha_arg_type (MODE);		\
+									\
+     (CUM).num_args += ALPHA_ARG_SIZE (MODE, TYPE, NAMED);		\
+    }
+
+/* For an arg passed partly in registers and partly in memory,
+   this is the number of registers used.
+   For args passed entirely in registers or entirely in memory, zero.  */
+
+#undef FUNCTION_ARG_PARTIAL_NREGS
+#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED)		\
+((CUM).num_args < 6 && 6 < (CUM).num_args				\
+   + ALPHA_ARG_SIZE (MODE, TYPE, NAMED)					\
+ ? 6 - (CUM).num_args : 0)
+
+/* Perform any needed actions needed for a function that is receiving a
+   variable number of arguments. 
+
+   CUM is as for INIT_CUMULATIVE_ARGS.
+
+   MODE and TYPE are the mode and type of the current parameter.
+
+   PRETEND_SIZE is a variable that should be set to the amount of stack
+   that must be pushed by the prolog to pretend that our caller pushed
+   it.
+
+   Normally, this macro will push all remaining incoming registers on the
+   stack and set PRETEND_SIZE to the length of the registers pushed. 
+
+   For VMS, we allocate space for all 6 arg registers plus a count.
+
+   However, if NO registers need to be saved, don't allocate any space.
+   This is not only because we won't need the space, but because AP includes
+   the current_pretend_args_size and we don't want to mess up any
+   ap-relative addresses already made.   */
+
+#undef SETUP_INCOMING_VARARGS
+#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL)	\
+{ if ((CUM).num_args < 6)				\
+    {							\
+      if (! (NO_RTL))					\
+	{						\
+	  emit_move_insn (gen_rtx (REG, DImode, 1),	\
+			  virtual_incoming_args_rtx);	\
+	  emit_insn (gen_arg_home ());			\
+	}						\
+						        \
+      PRETEND_SIZE = 7 * UNITS_PER_WORD;		\
+    }							\
+}
+
+#undef ASM_FILE_START
+#define ASM_FILE_START(FILE)					\
+{								\
+  alpha_write_verstamp (FILE);					\
+  fprintf (FILE, "\t.set noreorder\n");				\
+  fprintf (FILE, "\t.set volatile\n");				\
+  ASM_OUTPUT_SOURCE_FILENAME (FILE, main_input_filename);	\
+}
+
+#undef ASM_OUTPUT_FLOAT
+#define ASM_OUTPUT_FLOAT(FILE,VALUE)					\
+  {									\
+    if (REAL_VALUE_ISINF (VALUE)					\
+        || REAL_VALUE_ISNAN (VALUE)					\
+	|| REAL_VALUE_MINUS_ZERO (VALUE))				\
+      {									\
+	long t;								\
+	REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t);			\
+	fprintf (FILE, "\t.long 0x%lx\n", t & 0xffffffff);		\
+      }									\
+    else								\
+      {									\
+	char str[30];							\
+	REAL_VALUE_TO_DECIMAL ((VALUE), "%.20e", str);			\
+	fprintf (FILE, "\t.%c_floating %s\n", (TARGET_FLOAT_VAX)?'f':'s', str);	\
+      }									\
+  }
+
+#define LINK_SECTION_ASM_OP ".link"
+#define READONLY_SECTION_ASM_OP ".rdata"
+#define LITERALS_SECTION_ASM_OP ".literals"
+#define CTORS_SECTION_ASM_OP ".ctors"
+#define DTORS_SECTION_ASM_OP ".dtors"
+
+#undef EXTRA_SECTIONS
+#define EXTRA_SECTIONS	in_link, in_rdata, in_literals, in_ctors, in_dtors
+
+#undef EXTRA_SECTION_FUNCTIONS
+#define EXTRA_SECTION_FUNCTIONS					\
+void								\
+readonly_section ()						\
+{								\
+  if (in_section != in_rdata)				\
+    {								\
+      fprintf (asm_out_file, "%s\n", READONLY_SECTION_ASM_OP);	\
+      in_section = in_rdata;				\
+    }								\
+}								\
+void								\
+link_section ()							\
+{								\
+  if (in_section != in_link)					\
+    {								\
+      fprintf (asm_out_file, "%s\n", LINK_SECTION_ASM_OP); 	\
+      in_section = in_link;					\
+    }								\
+}                                                               \
+void								\
+literals_section ()						\
+{								\
+  if (in_section != in_literals)				\
+    {								\
+      fprintf (asm_out_file, "%s\n", LITERALS_SECTION_ASM_OP); 	\
+      in_section = in_literals;					\
+    }								\
+}								\
+void								\
+ctors_section ()						\
+{								\
+  if (in_section != in_ctors)					\
+    {								\
+      fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP);	\
+      in_section = in_ctors;					\
+    }								\
+}								\
+void								\
+dtors_section ()						\
+{								\
+  if (in_section != in_dtors)					\
+    {								\
+      fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP);	\
+      in_section = in_dtors;					\
+    }								\
+}
+
+#undef ASM_OUTPUT_ADDR_DIFF_ELT
+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) abort ()
+
+#undef ASM_OUTPUT_ADDR_VEC_ELT
+#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
+  fprintf (FILE, "\t.quad $L%d\n", (VALUE))
+
+#undef READONLY_DATA_SECTION
+#define READONLY_DATA_SECTION readonly_section
+
+#define ASM_FILE_END(FILE) alpha_write_linkage (FILE);
+
+#undef CASE_VECTOR_MODE
+#define CASE_VECTOR_MODE DImode
+#undef CASE_VECTOR_PC_RELATIVE
+
+#undef ASM_OUTPUT_CASE_LABEL
+#define ASM_OUTPUT_CASE_LABEL(FILE,PREFIX,NUM,TABLEINSN)	\
+{ ASM_OUTPUT_ALIGN (FILE, 3); ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); }
+
+/* This says how to output assembler code to declare an                
+   uninitialized external linkage data object.  */ 
+
+#define COMMON_ASM_OP ".comm"
+
+#undef ASM_OUTPUT_ALIGNED_COMMON
+#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN)		\
+do {									\
+  fprintf ((FILE), "\t%s\t", COMMON_ASM_OP);				\
+  assemble_name ((FILE), (NAME));					\
+  fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT);	\
+} while (0)
+
+#define NO_MD_PROTOTYPES
+
+/* Output assembler code for a block containing the constant parts
+   of a trampoline, leaving space for the variable parts.
+
+   The trampoline should set the static chain pointer to value placed
+   into the trampoline and should branch to the specified routine.  
+   Note that $27 has been set to the address of the trampoline, so we can
+   use it for addressability of the two data items.  Trampolines are always
+   aligned to FUNCTION_BOUNDARY, which is 64 bits.  */
+
+#undef TRAMPOLINE_TEMPLATE
+#define TRAMPOLINE_TEMPLATE(FILE)		\
+{						\
+  fprintf (FILE, "\t.quad 0\n");		\
+  fprintf (FILE, "\t.linkage __tramp\n");	\
+  fprintf (FILE, "\t.quad 0\n");		\
+}
+
+/* Length in units of the trampoline for entering a nested function.  */
+
+#undef TRAMPOLINE_SIZE
+#define TRAMPOLINE_SIZE    32
+
+/* Emit RTL insns to initialize the variable parts of a trampoline.
+   FNADDR is an RTX for the address of the function's pure code.
+   CXT is an RTX for the static chain value for the function.  */
+
+#undef INITIALIZE_TRAMPOLINE
+#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
+  alpha_initialize_trampoline (TRAMP, FNADDR, CXT, 16, 24, -1)
+
+/* A C statement (sans semicolon) to output an element in the table of
+   global constructors.  */
+#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME)		\
+  do {							\
+    ctors_section ();					\
+    fprintf (FILE, "\t.quad "); 			\
+    assemble_name (FILE, NAME); 			\
+    fprintf (FILE, "\n");				\
+  } while (0)
+
+/* A C statement (sans semicolon) to output an element in the table of
+   global destructors.	*/
+#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME)		\
+  do {							\
+    dtors_section ();					\
+    fprintf (FILE, "\t.quad "); 			\
+    assemble_name (FILE, NAME); 			\
+    fprintf (FILE, "\n");				\
+  } while (0)
+
+#define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, NAME, ARGS) \
+  (vms_valid_decl_attribute_p (DECL, ATTRIBUTES, NAME, ARGS))
+extern int vms_valid_decl_attribute_p ();
+
+#undef SDB_DEBUGGING_INFO
+#undef MIPS_DEBUGGING_INFO
+#undef DBX_DEBUGGING_INFO
+
+#define DWARF2_DEBUGGING_INFO
+
+/* This is how to output an assembler line
+   that says to advance the location counter
+   to a multiple of 2**LOG bytes.  */
+
+#undef ASM_OUTPUT_ALIGN
+#define ASM_OUTPUT_ALIGN(FILE,LOG)	\
+    fprintf (FILE, "\t.align %d\n", LOG);
+
+#define UNALIGNED_SHORT_ASM_OP	".word"
+#define UNALIGNED_INT_ASM_OP	".long"
+#define UNALIGNED_DOUBLE_INT_ASM_OP	".quad"
+
+#define ASM_OUTPUT_SECTION(FILE,SECTION)			\
+   (strcmp (SECTION, ".text") == 0)				\
+     ? text_section ()						\
+     : named_section (NULL_TREE, SECTION, 0),			\
+       ASM_OUTPUT_ALIGN (FILE, 0)				\
+
+#define ASM_OUTPUT_SECTION_NAME(FILE,DECL,NAME,RELOC)		\
+  do								\
+    {								\
+      char *flags;					 	\
+      int ovr = 0;						\
+      if (DECL && DECL_MACHINE_ATTRIBUTES (DECL)		\
+	  && lookup_attribute					\
+	      ("overlaid", DECL_MACHINE_ATTRIBUTES (DECL)))	\
+	flags = ",OVR", ovr = 1;				\
+      else if (strncmp (NAME,".debug", 6) == 0)			\
+	flags = ",NOWRT";					\
+      else							\
+	flags = "";						\
+      fputc ('\n', (FILE));					\
+      fprintf (FILE, ".section\t%s%s\n", NAME, flags);		\
+      if (ovr)							\
+        (NAME) = "";						\
+    } while (0)
+
+#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2)				\
+  do {	literals_section();                                             \
+	fprintf ((FILE), "\t");						\
+	assemble_name (FILE, LABEL1);					\
+	fprintf (FILE, " = ");						\
+	assemble_name (FILE, LABEL2);					\
+	fprintf (FILE, "\n");						\
+  } while (0)
+
+#undef PREFERRED_DEBUGGING_TYPE
+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
+
+#undef ASM_FORMAT_PRIVATE_NAME
+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)	\
+( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 12),	\
+  sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO)))
+
+/* ??? VMS uses different linkage.  */
+#undef ASM_OUTPUT_MI_THUNK
+
+#undef ASM_SPEC
+#undef ASM_FINAL_SPEC
+#undef LINK_SPEC
+#undef STARTFILE_SPEC
+#define ASM_SPEC "-nocpp %{pg}"
+#define LINK_SPEC "%{g3:-g3} %{g0:-g0} %{shared:-shared} %{v:-v}"
+
+/* Define the names of the division and modulus functions.  */
+#define DIVSI3_LIBCALL "OTS$DIV_I"
+#define DIVDI3_LIBCALL "OTS$DIV_L"
+#define UDIVSI3_LIBCALL "OTS$DIV_UI"
+#define UDIVDI3_LIBCALL "OTS$DIV_UL"
+#define MODSI3_LIBCALL "OTS$REM_I"
+#define MODDI3_LIBCALL "OTS$REM_L"
+#define UMODSI3_LIBCALL "OTS$REM_UI"
+#define UMODDI3_LIBCALL "OTS$REM_UL"
+
+#define DIR_SEPARATOR ']'
+
+#define PREFIX "GNU_ROOT:"
diff --git a/contrib/gcc/config/alpha/vxworks.h b/contrib/gcc/config/alpha/vxworks.h
new file mode 100644
index 000000000000..6dee4b3e7211
--- /dev/null
+++ b/contrib/gcc/config/alpha/vxworks.h
@@ -0,0 +1,51 @@
+/* Definitions of target machine for GNU compiler.  Vxworks Alpha version.
+   Copyright (C) 1998 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* This file just exists to give specs for the Alpha running on VxWorks.  */
+
+#undef CPP_SUBTARGET_SPEC
+#define CPP_SUBTARGET_SPEC "\
+%{mvxsim:-DCPU=SIMALPHADUNIX} \
+%{!mvxsim: %{!mcpu*|mcpu=21064:-DCPU=21064} %{mcpu=21164:-DCPU=21164}} \
+%{posix: -D_POSIX_SOURCE}"
+
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES "\
+-D__vxworks -D__alpha_vxworks -Asystem(vxworks) \
+-Asystem(embedded) -D_LONGLONG"
+
+/* VxWorks does all the library stuff itself.  */
+
+#undef LIB_SPEC
+#define LIB_SPEC ""
+
+/* VxWorks uses object files, not loadable images.  make linker just
+   combine objects. */
+
+#undef LINK_SPEC
+#define LINK_SPEC "-r"
+
+/* VxWorks provides the functionality of crt0.o and friends itself.  */
+
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC ""
+
+#undef ENDFILE_SPEC
+#define ENDFILE_SPEC ""
diff --git a/contrib/gcc/config/alpha/x-alpha b/contrib/gcc/config/alpha/x-alpha
index 991974797980..9686ab96472a 100644
--- a/contrib/gcc/config/alpha/x-alpha
+++ b/contrib/gcc/config/alpha/x-alpha
@@ -1 +1,2 @@
 CLIB=-lmld
+EXTRA_HEADERS = $(srcdir)/config/alpha/va_list.h
diff --git a/contrib/gcc/config/alpha/xm-alpha.h b/contrib/gcc/config/alpha/xm-alpha.h
index 642e1cf1a6e0..7665127b7147 100644
--- a/contrib/gcc/config/alpha/xm-alpha.h
+++ b/contrib/gcc/config/alpha/xm-alpha.h
@@ -41,12 +41,18 @@ Boston, MA 02111-1307, USA.  */
 #define	SUCCESS_EXIT_CODE	0
 #define	FATAL_EXIT_CODE		33
 
-/* If not compiled with GNU C, use the builtin alloca.  */
-#if !defined(__GNUC__) && !defined(_WIN32)
+/* If compiled with GNU C, use the builtin alloca.  */
+#ifndef alloca
+#if defined(__GNUC__) && !defined(USE_C_ALLOCA)
+#define alloca __builtin_alloca
+#else
+#if !defined(_WIN32) && !defined(USE_C_ALLOCA) && !defined(OPEN_VMS)
 #include <alloca.h>
 #else
 extern void *alloca ();
 #endif
+#endif
+#endif
 
 /* The host compiler has problems with enum bitfields since it makes
    them signed so we can't fit all our codes in.  */
@@ -65,14 +71,6 @@ extern void *malloc (), *realloc (), *calloc ();
 #include "string.h"
 #endif
 
-/* OSF/1 has vprintf.  */
-
-#define HAVE_VPRINTF
-
-/* OSF/1 has putenv.  */
-
-#define HAVE_PUTENV
-
 /* OSF/1 is POSIX.1 compliant.  */
 
 #define POSIX
diff --git a/contrib/gcc/config/alpha/xm-openbsd.h b/contrib/gcc/config/alpha/xm-openbsd.h
new file mode 100644
index 000000000000..50f436695a71
--- /dev/null
+++ b/contrib/gcc/config/alpha/xm-openbsd.h
@@ -0,0 +1,23 @@
+/* Configuration file for an host running alpha OpenBSD.
+   Copyright (C) 1999 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#include <xm-openbsd.h>
+#include <alpha/xm-alpha.h>
+
diff --git a/contrib/gcc/config/alpha/xm-vms.h b/contrib/gcc/config/alpha/xm-vms.h
new file mode 100644
index 000000000000..472a225672be
--- /dev/null
+++ b/contrib/gcc/config/alpha/xm-vms.h
@@ -0,0 +1,93 @@
+/* Configuration for GNU C-compiler for openVMS/Alpha.
+   Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+   Contributed by Klaus Kaempf (kkaempf@progis.de).
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* If compiling with DECC, need to fix problem with <stdio.h>
+   which defines a macro called FILE_TYPE that breaks "tree.h".
+   Fortunately it uses #ifndef to suppress multiple inclusions.
+   Three possible cases:
+        1) <stdio.h> has already been included -- ours will be no-op;
+        2) <stdio.h> will be included after us -- "theirs" will be no-op;
+        3) <stdio.h> isn't needed -- including it here shouldn't hurt.
+   In all three cases, the problem macro will be removed here.  */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#ifdef __DECC
+#undef FILE_TYPE
+#endif
+
+#undef HOST_BITS_PER_LONG
+#define HOST_BITS_PER_LONG 32
+
+#define HOST_WIDE_INT long long
+#define HOST_BITS_PER_WIDE_INT 64
+
+#undef SUCCESS_EXIT_CODE
+#define SUCCESS_EXIT_CODE 1
+#undef FATAL_EXIT_CODE
+#define FATAL_EXIT_CODE (44 | 0x10000000)  /* Abort, and no DCL message.  */
+
+/* A couple of conditionals for execution machine are controlled here.  */
+#ifndef VMS
+#define VMS
+#endif
+
+#define GCC_INCLUDE_DIR ""
+/* Specify the list of include file directories.  */
+#define INCLUDE_DEFAULTS		\
+{					\
+  { "GNU_GXX_INCLUDE:", "G++", 1, 1 },	\
+  { "GNU_CC_INCLUDE:", "GCC", 0, 0 },	\
+  { ".", 0, 0, 1 },			\
+  { 0, 0, 0, 0 }			\
+}
+
+/* Define a local equivalent (sort of) for unlink */
+#define unlink remove
+
+#define NEED_ATEXIT
+#define HAVE_VPRINTF
+#define HAVE_PUTENV
+#define HAVE_STRERROR
+#define HAVE_ATOLL
+
+#define NO_SYS_PARAMS_H		/* Don't have <sys/params.h> */
+#define USE_C_ALLOCA		/* Using alloca.c */
+
+#define HAVE_FCNTL_H 1
+#define HAVE_STDLIB_H 1
+#define HAVE_UNISTD_H 1
+#define HAVE_STRING_H 1
+#define HAVE_LIMITS_H 1
+#define HAVE_STDDEF_H 1
+#define HAVE_TIME_H 1
+#define STDC_HEADERS 1
+#define HAVE_CPP_STRINGIFY 1
+
+#if __STDC__
+extern void *alloca (size_t);
+#else
+extern char *alloca (unsigned int);
+#endif
+
+#define OBJECT_SUFFIX ".obj"
+#define EXECUTABLE_SUFFIX ".exe"