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authorEmmanuel Vadot <manu@FreeBSD.org>2023-08-09 13:31:58 +0000
committerEmmanuel Vadot <manu@FreeBSD.org>2023-08-09 13:31:58 +0000
commitc47d0ea183983e0631f8cc41e9d25e4854368a0a (patch)
tree329e5cd35d28aea1a42c6228cb539abaddf662a2 /Bindings/dma/renesas,rz-dmac.yaml
parent4a8223f297bb7dff7a684da702777d7e94d054fe (diff)
Import device-tree files from Linux 6.4vendor/device-tree/6.4
Diffstat (limited to 'Bindings/dma/renesas,rz-dmac.yaml')
-rw-r--r--Bindings/dma/renesas,rz-dmac.yaml14
1 files changed, 14 insertions, 0 deletions
diff --git a/Bindings/dma/renesas,rz-dmac.yaml b/Bindings/dma/renesas,rz-dmac.yaml
index f638d3934e71..c284abc6784a 100644
--- a/Bindings/dma/renesas,rz-dmac.yaml
+++ b/Bindings/dma/renesas,rz-dmac.yaml
@@ -54,6 +54,11 @@ properties:
- description: DMA main clock
- description: DMA register access clock
+ clock-names:
+ items:
+ - const: main
+ - const: register
+
'#dma-cells':
const: 1
description:
@@ -77,16 +82,23 @@ properties:
- description: Reset for DMA ARESETN reset terminal
- description: Reset for DMA RST_ASYNC reset terminal
+ reset-names:
+ items:
+ - const: arst
+ - const: rst_async
+
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
+ - clock-names
- '#dma-cells'
- dma-channels
- power-domains
- resets
+ - reset-names
additionalProperties: false
@@ -124,9 +136,11 @@ examples:
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
<&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
+ clock-names = "main", "register";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_DMAC_ARESETN>,
<&cpg R9A07G044_DMAC_RST_ASYNC>;
+ reset-names = "arst", "rst_async";
#dma-cells = <1>;
dma-channels = <16>;
};