Vendor import of llvm 6.0.0 release r326565:vendor/llvm/llvm-release_600-r326565

https://llvm.org/svn/llvm-project/llvm/tags/RELEASE_600/final@326565

5 files changed, 61 insertions, 66 deletions

diff --git a/bindings/go/README.txt b/bindings/go/README.txt
index 2fc4afa07715..6ed224d8280e 100644
--- a/bindings/go/README.txt
+++ b/bindings/go/README.txt
@@ -51,3 +51,11 @@ CGO_CPPFLAGS, CGO_CXXFLAGS and CGO_LDFLAGS environment variables:
     $ export CGO_CXXFLAGS=-std=c++11
     $ export CGO_LDFLAGS="`/path/to/llvm-build/bin/llvm-config --ldflags --libs --system-libs all`"
     $ go build -tags byollvm
+
+If you see a compilation error while compiling your code with Go 1.9.4 or later as follows,
+
+    go build llvm.org/llvm/bindings/go/llvm: invalid flag in #cgo LDFLAGS: -Wl,-headerpad_max_install_names
+
+you need to setup $CGO_LDFLAGS_ALLOW to allow a compiler to specify some linker options:
+
+    $ export CGO_LDFLAGS_ALLOW='-Wl,(-search_paths_first|-headerpad_max_install_names)'
diff --git a/docs/ReleaseNotes.rst b/docs/ReleaseNotes.rst
index f2bbdc871add..ed867d5a9dc0 100644
--- a/docs/ReleaseNotes.rst
+++ b/docs/ReleaseNotes.rst
@@ -22,12 +22,12 @@ them.
 
 Non-comprehensive list of changes in this release
 =================================================
-.. NOTE
-   For small 1-3 sentence descriptions, just add an entry at the end of
-   this list. If your description won't fit comfortably in one bullet
-   point (e.g. maybe you would like to give an example of the
-   functionality, or simply have a lot to talk about), see the `NOTE` below
-   for adding a new subsection.
+
+* Support for `retpolines <https://support.google.com/faqs/answer/7625886>`_
+  was added to help mitigate "branch target injection" (variant #2) of the
+  "Spectre" speculative side channels described by `Project Zero
+  <https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html>`_
+  and the `Spectre paper <https://spectreattack.com/spectre.pdf>`_.
 
 * The ``Redirects`` argument of ``llvm::sys::ExecuteAndWait`` and
   ``llvm::sys::ExecuteNoWait`` was changed to an ``ArrayRef`` of optional
@@ -48,17 +48,6 @@ Non-comprehensive list of changes in this release
 * Preliminary support for Sanitizers and sibling features on X86(_64) NetBSD
   (ASan, UBsan, TSan, MSan, SafeStack, libFuzzer).
 
-* Note..
-
-.. NOTE
-   If you would like to document a larger change, then you can add a
-   subsection about it right here. You can copy the following boilerplate
-   and un-indent it (the indentation causes it to be inside this comment).
-
-   Special New Feature
-   -------------------
-
-   Makes programs 10x faster by doing Special New Thing.
 
 Changes to the LLVM IR
 ----------------------
@@ -72,19 +61,17 @@ Changes to the LLVM IR
   to enable/disable specific floating-point optimizations. Making the
   optimizer respond appropriately to these flags is an ongoing effort.
 
+
 Changes to the AArch64 Target
 -----------------------------
 
-During this release:
+* Enabled the new GlobalISel instruction selection framework by default at ``-O0``.
 
- * Enabled the new GlobalISel instruction selection framework by default at ``-O0``.
 
 Changes to the ARM Target
 -------------------------
 
-During this release the ARM target has:
-
-* Got support for enabling SjLj exception handling on platforms where it
+* Support for enabling SjLj exception handling on platforms where it
   isn't the default.
 
 
@@ -93,12 +80,12 @@ Changes to the Hexagon Target
 
 * The Hexagon backend now supports V65 ISA.
 
-* The ``-mhvx`` option now takes an optional value that specified the ISA
+* The ``-mhvx`` option now takes an optional value that specifies the ISA
   version of the HVX coprocessor.  The available values are v60, v62 and v65.
   By default, the value is set to be the same as the CPU version.
 
 * The compiler option ``-mhvx-double`` is deprecated and will be removed in
-  the next release of the compiler. Programmers should use ``-mhvx-length``
+  the next release of the compiler. Programmers should use the ``-mhvx-length``
   option to specify the desired vector length: ``-mhvx-length=64b`` for
   64-byte vectors and ``-mhvx-length=128b`` for 128-byte vectors. While the
   current default vector length is 64 bytes, users should always specify the
@@ -130,8 +117,8 @@ Fixed numerous bugs:
 * Corrected the encoding of movep for microMIPS32r6.
 * Fixed an issue with the usage of insert instructions having an invalid set of
   operands.
-* Fixed an issue where TLS symbols where not marked as such.
-* Enabled the usage of register scavanging with MSA, due to its' shorter offsets
+* Fixed an issue where TLS symbols were not marked as such.
+* Enabled the usage of register scavenging with MSA, due to its shorter offsets
   for loads and stores.
 * Corrected the ELF headers when using the DSP ASE.
 
@@ -152,10 +139,6 @@ Deprecation notices:
 * microMIPS64R6 support was been deprecated since 5.0, and has now been
   completely removed.
 
-Changes to the PowerPC Target
------------------------------
-
- During this release ...
 
 Changes to the SystemZ Target
 -----------------------------
@@ -204,32 +187,30 @@ During this release the X86 target has:
 
 * Gained initial support recognizing variable shuffles from vector element extracts and inserts.
 
-* Improved documentation for SSE/AVX intrinsics in *intrin.h header files.
-
-Changes to the AMDGPU Target
------------------------------
-
- During this release ...
-
-Changes to the AVR Target
------------------------------
-
- During this release ...
-
-Changes to the OCaml bindings
------------------------------
+* Improved documentation for SSE/AVX intrinsics in intrin.h header files.
 
- During this release ...
+* Gained support for emitting `retpolines
+  <https://support.google.com/faqs/answer/7625886>`_, including automatic
+  insertion of the necessary thunks or using external thunks.
 
 
-Changes to the C API
---------------------
+External Open Source Projects Using LLVM 6
+==========================================
 
- During this release ...
+LDC - the LLVM-based D compiler
+-------------------------------
 
+`D <http://dlang.org>`_ is a language with C-like syntax and static typing. It
+pragmatically combines efficiency, control, and modeling power, with safety and
+programmer productivity. D supports powerful concepts like Compile-Time Function
+Execution (CTFE) and Template Meta-Programming, provides an innovative approach
+to concurrency and offers many classical paradigms.
 
-External Open Source Projects Using LLVM 6
-==========================================
+`LDC <http://wiki.dlang.org/LDC>`_ uses the frontend from the reference compiler
+combined with LLVM as backend to produce efficient native code. LDC targets
+x86/x86_64 systems like Linux, OS X, FreeBSD and Windows and also Linux on ARM
+and PowerPC (32/64 bit). Ports to other architectures like AArch64 and MIPS64
+are underway.
 
 JFS - JIT Fuzzing Solver
 ------------------------
@@ -257,21 +238,6 @@ import of .h symbols - even inline functions and macros. Zig uses LLD combined
 with lazily building compiler-rt to provide out-of-the-box cross-compiling for
 all supported targets.
 
-LDC - the LLVM-based D compiler
--------------------------------
-
-`D <http://dlang.org>`_ is a language with C-like syntax and static typing. It
-pragmatically combines efficiency, control, and modeling power, with safety and
-programmer productivity. D supports powerful concepts like Compile-Time Function
-Execution (CTFE) and Template Meta-Programming, provides an innovative approach
-to concurrency and offers many classical paradigms.
-
-`LDC <http://wiki.dlang.org/LDC>`_ uses the frontend from the reference compiler
-combined with LLVM as backend to produce efficient native code. LDC targets
-x86/x86_64 systems like Linux, OS X, FreeBSD and Windows and also Linux on ARM
-and PowerPC (32/64 bit). Ports to other architectures like AArch64 and MIPS64
-are underway.
-
 Additional Information
 ======================
 
diff --git a/lib/Target/AArch64/AArch64InstructionSelector.cpp b/lib/Target/AArch64/AArch64InstructionSelector.cpp
index 0bc5b395499e..7d2ec1be2888 100644
--- a/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -840,6 +840,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I,
   case TargetOpcode::G_EXTRACT: {
     LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
     LLT DstTy = MRI.getType(I.getOperand(0).getReg());
+    (void)DstTy;
     unsigned SrcSize = SrcTy.getSizeInBits();
     // Larger extracts are vectors, same-size extracts should be something else
     // by now (either split up or simplified to a COPY).
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 9237833a2cd0..10e19f92b4a6 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -35520,7 +35520,7 @@ static SDValue combineFneg(SDNode *N, SelectionDAG &DAG,
   // If we're negating an FMA node, then we can adjust the
   // instruction to include the extra negation.
   unsigned NewOpcode = 0;
-  if (Arg.hasOneUse()) {
+  if (Arg.hasOneUse() && Subtarget.hasAnyFMA()) {
     switch (Arg.getOpcode()) {
     case ISD::FMA:             NewOpcode = X86ISD::FNMSUB;       break;
     case X86ISD::FMSUB:        NewOpcode = X86ISD::FNMADD;       break;
diff --git a/test/CodeGen/X86/pr36553.ll b/test/CodeGen/X86/pr36553.ll
new file mode 100644
index 000000000000..827f80a3e07e
--- /dev/null
+++ b/test/CodeGen/X86/pr36553.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s
+
+; Make sure we don't crash because we negated an fma when we didn't have any fma instructions.
+
+define float @pr36553(float %a, float %b, float %c) nounwind {
+; CHECK-LABEL: pr36553:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    callq _fmaf
+; CHECK-NEXT:    xorps {{.*}}(%rip), %xmm0
+; CHECK-NEXT:    popq %rax
+; CHECK-NEXT:    retq
+entry:
+  %0 = tail call float @llvm.fma.f32(float %a, float %b, float %c)
+  %sub = fsub float -0.000000e+00, %0
+  ret float %sub
+}
+
+declare float @llvm.fma.f32(float, float, float)